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Merge branch 'master' into next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nouveau_state.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin
3 * Copyright 2008 Stuart Bennett
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 */
25
26#include <linux/swab.h>
5a0e3ad6 27#include <linux/slab.h>
6ee73861
BS		 28#include "drmP.h"
29#include "drm.h"
30#include "drm_sarea.h"
31#include "drm_crtc_helper.h"
32#include <linux/vgaarb.h>
6a9ee8af 33#include <linux/vga_switcheroo.h>
6ee73861
BS		 34
35#include "nouveau_drv.h"
36#include "nouveau_drm.h"
38651674 37#include "nouveau_fbcon.h"
a8eaebc6 38#include "nouveau_ramht.h"
330c5988 39#include "nouveau_pm.h"
6ee73861
BS		 40#include "nv50_display.h"
41
6ee73861 42static void nouveau_stub_takedown(struct drm_device *dev) {}
ee2e0131 43static int nouveau_stub_init(struct drm_device *dev) { return 0; }
6ee73861
BS		 44
45static int nouveau_init_engine_ptrs(struct drm_device *dev)
46{
47 struct drm_nouveau_private *dev_priv = dev->dev_private;
48 struct nouveau_engine *engine = &dev_priv->engine;
49
50 switch (dev_priv->chipset & 0xf0) {
51 case 0x00:
52 engine->instmem.init = nv04_instmem_init;
53 engine->instmem.takedown = nv04_instmem_takedown;
54 engine->instmem.suspend = nv04_instmem_suspend;
55 engine->instmem.resume = nv04_instmem_resume;
e41115d0
BS		 56 engine->instmem.get = nv04_instmem_get;
57 engine->instmem.put = nv04_instmem_put;
58 engine->instmem.map = nv04_instmem_map;
59 engine->instmem.unmap = nv04_instmem_unmap;
f56cb86f 60 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 61 engine->mc.init = nv04_mc_init;
62 engine->mc.takedown = nv04_mc_takedown;
63 engine->timer.init = nv04_timer_init;
64 engine->timer.read = nv04_timer_read;
65 engine->timer.takedown = nv04_timer_takedown;
66 engine->fb.init = nv04_fb_init;
67 engine->fb.takedown = nv04_fb_takedown;
6ee73861
BS		 68 engine->graph.init = nv04_graph_init;
69 engine->graph.takedown = nv04_graph_takedown;
70 engine->graph.fifo_access = nv04_graph_fifo_access;
71 engine->graph.channel = nv04_graph_channel;
72 engine->graph.create_context = nv04_graph_create_context;
73 engine->graph.destroy_context = nv04_graph_destroy_context;
74 engine->graph.load_context = nv04_graph_load_context;
75 engine->graph.unload_context = nv04_graph_unload_context;
76 engine->fifo.channels = 16;
77 engine->fifo.init = nv04_fifo_init;
5178d40d 78 engine->fifo.takedown = nv04_fifo_fini;
6ee73861
BS		 79 engine->fifo.disable = nv04_fifo_disable;
80 engine->fifo.enable = nv04_fifo_enable;
81 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12 82 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 83 engine->fifo.channel_id = nv04_fifo_channel_id;
84 engine->fifo.create_context = nv04_fifo_create_context;
85 engine->fifo.destroy_context = nv04_fifo_destroy_context;
86 engine->fifo.load_context = nv04_fifo_load_context;
87 engine->fifo.unload_context = nv04_fifo_unload_context;
c88c2e06
FJ		 88 engine->display.early_init = nv04_display_early_init;
89 engine->display.late_takedown = nv04_display_late_takedown;
90 engine->display.create = nv04_display_create;
91 engine->display.init = nv04_display_init;
92 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 93 engine->gpio.init = nouveau_stub_init;
94 engine->gpio.takedown = nouveau_stub_takedown;
95 engine->gpio.get = NULL;
96 engine->gpio.set = NULL;
97 engine->gpio.irq_enable = NULL;
442b626e
BS		 98 engine->pm.clock_get = nv04_pm_clock_get;
99 engine->pm.clock_pre = nv04_pm_clock_pre;
100 engine->pm.clock_set = nv04_pm_clock_set;
bd2e597d
BS		 101 engine->crypt.init = nouveau_stub_init;
102 engine->crypt.takedown = nouveau_stub_takedown;
60d2a88a
BS		 103 engine->vram.init = nouveau_mem_detect;
104 engine->vram.flags_valid = nouveau_mem_flags_valid;
6ee73861
BS		 105 break;
106 case 0x10:
107 engine->instmem.init = nv04_instmem_init;
108 engine->instmem.takedown = nv04_instmem_takedown;
109 engine->instmem.suspend = nv04_instmem_suspend;
110 engine->instmem.resume = nv04_instmem_resume;
e41115d0
BS		 111 engine->instmem.get = nv04_instmem_get;
112 engine->instmem.put = nv04_instmem_put;
113 engine->instmem.map = nv04_instmem_map;
114 engine->instmem.unmap = nv04_instmem_unmap;
f56cb86f 115 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 116 engine->mc.init = nv04_mc_init;
117 engine->mc.takedown = nv04_mc_takedown;
118 engine->timer.init = nv04_timer_init;
119 engine->timer.read = nv04_timer_read;
120 engine->timer.takedown = nv04_timer_takedown;
121 engine->fb.init = nv10_fb_init;
122 engine->fb.takedown = nv10_fb_takedown;
a5cf68b0
FJ		 123 engine->fb.init_tile_region = nv10_fb_init_tile_region;
124 engine->fb.set_tile_region = nv10_fb_set_tile_region;
125 engine->fb.free_tile_region = nv10_fb_free_tile_region;
6ee73861
BS		 126 engine->graph.init = nv10_graph_init;
127 engine->graph.takedown = nv10_graph_takedown;
128 engine->graph.channel = nv10_graph_channel;
129 engine->graph.create_context = nv10_graph_create_context;
130 engine->graph.destroy_context = nv10_graph_destroy_context;
131 engine->graph.fifo_access = nv04_graph_fifo_access;
132 engine->graph.load_context = nv10_graph_load_context;
133 engine->graph.unload_context = nv10_graph_unload_context;
a5cf68b0 134 engine->graph.set_tile_region = nv10_graph_set_tile_region;
6ee73861
BS		 135 engine->fifo.channels = 32;
136 engine->fifo.init = nv10_fifo_init;
5178d40d 137 engine->fifo.takedown = nv04_fifo_fini;
6ee73861
BS		 138 engine->fifo.disable = nv04_fifo_disable;
139 engine->fifo.enable = nv04_fifo_enable;
140 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12 141 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 142 engine->fifo.channel_id = nv10_fifo_channel_id;
143 engine->fifo.create_context = nv10_fifo_create_context;
3945e475 144 engine->fifo.destroy_context = nv04_fifo_destroy_context;
6ee73861
BS		 145 engine->fifo.load_context = nv10_fifo_load_context;
146 engine->fifo.unload_context = nv10_fifo_unload_context;
c88c2e06
FJ		 147 engine->display.early_init = nv04_display_early_init;
148 engine->display.late_takedown = nv04_display_late_takedown;
149 engine->display.create = nv04_display_create;
150 engine->display.init = nv04_display_init;
151 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 152 engine->gpio.init = nouveau_stub_init;
153 engine->gpio.takedown = nouveau_stub_takedown;
154 engine->gpio.get = nv10_gpio_get;
155 engine->gpio.set = nv10_gpio_set;
156 engine->gpio.irq_enable = NULL;
442b626e
BS		 157 engine->pm.clock_get = nv04_pm_clock_get;
158 engine->pm.clock_pre = nv04_pm_clock_pre;
159 engine->pm.clock_set = nv04_pm_clock_set;
bd2e597d
BS		 160 engine->crypt.init = nouveau_stub_init;
161 engine->crypt.takedown = nouveau_stub_takedown;
60d2a88a
BS		 162 engine->vram.init = nouveau_mem_detect;
163 engine->vram.flags_valid = nouveau_mem_flags_valid;
6ee73861
BS		 164 break;
165 case 0x20:
166 engine->instmem.init = nv04_instmem_init;
167 engine->instmem.takedown = nv04_instmem_takedown;
168 engine->instmem.suspend = nv04_instmem_suspend;
169 engine->instmem.resume = nv04_instmem_resume;
e41115d0
BS		 170 engine->instmem.get = nv04_instmem_get;
171 engine->instmem.put = nv04_instmem_put;
172 engine->instmem.map = nv04_instmem_map;
173 engine->instmem.unmap = nv04_instmem_unmap;
f56cb86f 174 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 175 engine->mc.init = nv04_mc_init;
176 engine->mc.takedown = nv04_mc_takedown;
177 engine->timer.init = nv04_timer_init;
178 engine->timer.read = nv04_timer_read;
179 engine->timer.takedown = nv04_timer_takedown;
180 engine->fb.init = nv10_fb_init;
181 engine->fb.takedown = nv10_fb_takedown;
a5cf68b0
FJ		 182 engine->fb.init_tile_region = nv10_fb_init_tile_region;
183 engine->fb.set_tile_region = nv10_fb_set_tile_region;
184 engine->fb.free_tile_region = nv10_fb_free_tile_region;
6ee73861
BS		 185 engine->graph.init = nv20_graph_init;
186 engine->graph.takedown = nv20_graph_takedown;
187 engine->graph.channel = nv10_graph_channel;
188 engine->graph.create_context = nv20_graph_create_context;
189 engine->graph.destroy_context = nv20_graph_destroy_context;
190 engine->graph.fifo_access = nv04_graph_fifo_access;
191 engine->graph.load_context = nv20_graph_load_context;
192 engine->graph.unload_context = nv20_graph_unload_context;
a5cf68b0 193 engine->graph.set_tile_region = nv20_graph_set_tile_region;
6ee73861
BS		 194 engine->fifo.channels = 32;
195 engine->fifo.init = nv10_fifo_init;
5178d40d 196 engine->fifo.takedown = nv04_fifo_fini;
6ee73861
BS		 197 engine->fifo.disable = nv04_fifo_disable;
198 engine->fifo.enable = nv04_fifo_enable;
199 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12 200 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 201 engine->fifo.channel_id = nv10_fifo_channel_id;
202 engine->fifo.create_context = nv10_fifo_create_context;
3945e475 203 engine->fifo.destroy_context = nv04_fifo_destroy_context;
6ee73861
BS		 204 engine->fifo.load_context = nv10_fifo_load_context;
205 engine->fifo.unload_context = nv10_fifo_unload_context;
c88c2e06
FJ		 206 engine->display.early_init = nv04_display_early_init;
207 engine->display.late_takedown = nv04_display_late_takedown;
208 engine->display.create = nv04_display_create;
209 engine->display.init = nv04_display_init;
210 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 211 engine->gpio.init = nouveau_stub_init;
212 engine->gpio.takedown = nouveau_stub_takedown;
213 engine->gpio.get = nv10_gpio_get;
214 engine->gpio.set = nv10_gpio_set;
215 engine->gpio.irq_enable = NULL;
442b626e
BS		 216 engine->pm.clock_get = nv04_pm_clock_get;
217 engine->pm.clock_pre = nv04_pm_clock_pre;
218 engine->pm.clock_set = nv04_pm_clock_set;
bd2e597d
BS		 219 engine->crypt.init = nouveau_stub_init;
220 engine->crypt.takedown = nouveau_stub_takedown;
60d2a88a
BS		 221 engine->vram.init = nouveau_mem_detect;
222 engine->vram.flags_valid = nouveau_mem_flags_valid;
6ee73861
BS		 223 break;
224 case 0x30:
225 engine->instmem.init = nv04_instmem_init;
226 engine->instmem.takedown = nv04_instmem_takedown;
227 engine->instmem.suspend = nv04_instmem_suspend;
228 engine->instmem.resume = nv04_instmem_resume;
e41115d0
BS		 229 engine->instmem.get = nv04_instmem_get;
230 engine->instmem.put = nv04_instmem_put;
231 engine->instmem.map = nv04_instmem_map;
232 engine->instmem.unmap = nv04_instmem_unmap;
f56cb86f 233 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 234 engine->mc.init = nv04_mc_init;
235 engine->mc.takedown = nv04_mc_takedown;
236 engine->timer.init = nv04_timer_init;
237 engine->timer.read = nv04_timer_read;
238 engine->timer.takedown = nv04_timer_takedown;
8bded189
FJ		 239 engine->fb.init = nv30_fb_init;
240 engine->fb.takedown = nv30_fb_takedown;
a5cf68b0
FJ		 241 engine->fb.init_tile_region = nv30_fb_init_tile_region;
242 engine->fb.set_tile_region = nv10_fb_set_tile_region;
243 engine->fb.free_tile_region = nv30_fb_free_tile_region;
6ee73861
BS		 244 engine->graph.init = nv30_graph_init;
245 engine->graph.takedown = nv20_graph_takedown;
246 engine->graph.fifo_access = nv04_graph_fifo_access;
247 engine->graph.channel = nv10_graph_channel;
248 engine->graph.create_context = nv20_graph_create_context;
249 engine->graph.destroy_context = nv20_graph_destroy_context;
250 engine->graph.load_context = nv20_graph_load_context;
251 engine->graph.unload_context = nv20_graph_unload_context;
a5cf68b0 252 engine->graph.set_tile_region = nv20_graph_set_tile_region;
6ee73861
BS		 253 engine->fifo.channels = 32;
254 engine->fifo.init = nv10_fifo_init;
5178d40d 255 engine->fifo.takedown = nv04_fifo_fini;
6ee73861
BS		 256 engine->fifo.disable = nv04_fifo_disable;
257 engine->fifo.enable = nv04_fifo_enable;
258 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12 259 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 260 engine->fifo.channel_id = nv10_fifo_channel_id;
261 engine->fifo.create_context = nv10_fifo_create_context;
3945e475 262 engine->fifo.destroy_context = nv04_fifo_destroy_context;
6ee73861
BS		 263 engine->fifo.load_context = nv10_fifo_load_context;
264 engine->fifo.unload_context = nv10_fifo_unload_context;
c88c2e06
FJ		 265 engine->display.early_init = nv04_display_early_init;
266 engine->display.late_takedown = nv04_display_late_takedown;
267 engine->display.create = nv04_display_create;
268 engine->display.init = nv04_display_init;
269 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 270 engine->gpio.init = nouveau_stub_init;
271 engine->gpio.takedown = nouveau_stub_takedown;
272 engine->gpio.get = nv10_gpio_get;
273 engine->gpio.set = nv10_gpio_set;
274 engine->gpio.irq_enable = NULL;
442b626e
BS		 275 engine->pm.clock_get = nv04_pm_clock_get;
276 engine->pm.clock_pre = nv04_pm_clock_pre;
277 engine->pm.clock_set = nv04_pm_clock_set;
278 engine->pm.voltage_get = nouveau_voltage_gpio_get;
279 engine->pm.voltage_set = nouveau_voltage_gpio_set;
bd2e597d
BS		 280 engine->crypt.init = nouveau_stub_init;
281 engine->crypt.takedown = nouveau_stub_takedown;
60d2a88a
BS		 282 engine->vram.init = nouveau_mem_detect;
283 engine->vram.flags_valid = nouveau_mem_flags_valid;
6ee73861
BS		 284 break;
285 case 0x40:
286 case 0x60:
287 engine->instmem.init = nv04_instmem_init;
288 engine->instmem.takedown = nv04_instmem_takedown;
289 engine->instmem.suspend = nv04_instmem_suspend;
290 engine->instmem.resume = nv04_instmem_resume;
e41115d0
BS		 291 engine->instmem.get = nv04_instmem_get;
292 engine->instmem.put = nv04_instmem_put;
293 engine->instmem.map = nv04_instmem_map;
294 engine->instmem.unmap = nv04_instmem_unmap;
f56cb86f 295 engine->instmem.flush = nv04_instmem_flush;
6ee73861
BS		 296 engine->mc.init = nv40_mc_init;
297 engine->mc.takedown = nv40_mc_takedown;
298 engine->timer.init = nv04_timer_init;
299 engine->timer.read = nv04_timer_read;
300 engine->timer.takedown = nv04_timer_takedown;
301 engine->fb.init = nv40_fb_init;
302 engine->fb.takedown = nv40_fb_takedown;
a5cf68b0
FJ		 303 engine->fb.init_tile_region = nv30_fb_init_tile_region;
304 engine->fb.set_tile_region = nv40_fb_set_tile_region;
305 engine->fb.free_tile_region = nv30_fb_free_tile_region;
6ee73861
BS		 306 engine->graph.init = nv40_graph_init;
307 engine->graph.takedown = nv40_graph_takedown;
308 engine->graph.fifo_access = nv04_graph_fifo_access;
309 engine->graph.channel = nv40_graph_channel;
310 engine->graph.create_context = nv40_graph_create_context;
311 engine->graph.destroy_context = nv40_graph_destroy_context;
312 engine->graph.load_context = nv40_graph_load_context;
313 engine->graph.unload_context = nv40_graph_unload_context;
a5cf68b0 314 engine->graph.set_tile_region = nv40_graph_set_tile_region;
6ee73861
BS		 315 engine->fifo.channels = 32;
316 engine->fifo.init = nv40_fifo_init;
5178d40d 317 engine->fifo.takedown = nv04_fifo_fini;
6ee73861
BS		 318 engine->fifo.disable = nv04_fifo_disable;
319 engine->fifo.enable = nv04_fifo_enable;
320 engine->fifo.reassign = nv04_fifo_reassign;
588d7d12 321 engine->fifo.cache_pull = nv04_fifo_cache_pull;
6ee73861
BS		 322 engine->fifo.channel_id = nv10_fifo_channel_id;
323 engine->fifo.create_context = nv40_fifo_create_context;
3945e475 324 engine->fifo.destroy_context = nv04_fifo_destroy_context;
6ee73861
BS		 325 engine->fifo.load_context = nv40_fifo_load_context;
326 engine->fifo.unload_context = nv40_fifo_unload_context;
c88c2e06
FJ		 327 engine->display.early_init = nv04_display_early_init;
328 engine->display.late_takedown = nv04_display_late_takedown;
329 engine->display.create = nv04_display_create;
330 engine->display.init = nv04_display_init;
331 engine->display.destroy = nv04_display_destroy;
ee2e0131
BS		 332 engine->gpio.init = nouveau_stub_init;
333 engine->gpio.takedown = nouveau_stub_takedown;
334 engine->gpio.get = nv10_gpio_get;
335 engine->gpio.set = nv10_gpio_set;
336 engine->gpio.irq_enable = NULL;
442b626e
BS		 337 engine->pm.clock_get = nv04_pm_clock_get;
338 engine->pm.clock_pre = nv04_pm_clock_pre;
339 engine->pm.clock_set = nv04_pm_clock_set;
340 engine->pm.voltage_get = nouveau_voltage_gpio_get;
341 engine->pm.voltage_set = nouveau_voltage_gpio_set;
8155cac4 342 engine->pm.temp_get = nv40_temp_get;
bd2e597d
BS		 343 engine->crypt.init = nouveau_stub_init;
344 engine->crypt.takedown = nouveau_stub_takedown;
60d2a88a
BS		 345 engine->vram.init = nouveau_mem_detect;
346 engine->vram.flags_valid = nouveau_mem_flags_valid;
6ee73861
BS		 347 break;
348 case 0x50:
349 case 0x80: /* gotta love NVIDIA's consistency.. */
350 case 0x90:
351 case 0xA0:
352 engine->instmem.init = nv50_instmem_init;
353 engine->instmem.takedown = nv50_instmem_takedown;
354 engine->instmem.suspend = nv50_instmem_suspend;
355 engine->instmem.resume = nv50_instmem_resume;
e41115d0
BS		 356 engine->instmem.get = nv50_instmem_get;
357 engine->instmem.put = nv50_instmem_put;
358 engine->instmem.map = nv50_instmem_map;
359 engine->instmem.unmap = nv50_instmem_unmap;
734ee835
BS		 360 if (dev_priv->chipset == 0x50)
361 engine->instmem.flush = nv50_instmem_flush;
362 else
363 engine->instmem.flush = nv84_instmem_flush;
6ee73861
BS		 364 engine->mc.init = nv50_mc_init;
365 engine->mc.takedown = nv50_mc_takedown;
366 engine->timer.init = nv04_timer_init;
367 engine->timer.read = nv04_timer_read;
368 engine->timer.takedown = nv04_timer_takedown;
304424e1
MK		 369 engine->fb.init = nv50_fb_init;
370 engine->fb.takedown = nv50_fb_takedown;
6ee73861
BS		 371 engine->graph.init = nv50_graph_init;
372 engine->graph.takedown = nv50_graph_takedown;
373 engine->graph.fifo_access = nv50_graph_fifo_access;
374 engine->graph.channel = nv50_graph_channel;
375 engine->graph.create_context = nv50_graph_create_context;
376 engine->graph.destroy_context = nv50_graph_destroy_context;
377 engine->graph.load_context = nv50_graph_load_context;
378 engine->graph.unload_context = nv50_graph_unload_context;
2b4cebe4
BS		 379 if (dev_priv->chipset == 0x50 ||
380 dev_priv->chipset == 0xac)
56ac7475 381 engine->graph.tlb_flush = nv50_graph_tlb_flush;
2b4cebe4
BS		 382 else
383 engine->graph.tlb_flush = nv84_graph_tlb_flush;
6ee73861
BS		 384 engine->fifo.channels = 128;
385 engine->fifo.init = nv50_fifo_init;
386 engine->fifo.takedown = nv50_fifo_takedown;
387 engine->fifo.disable = nv04_fifo_disable;
388 engine->fifo.enable = nv04_fifo_enable;
389 engine->fifo.reassign = nv04_fifo_reassign;
390 engine->fifo.channel_id = nv50_fifo_channel_id;
391 engine->fifo.create_context = nv50_fifo_create_context;
392 engine->fifo.destroy_context = nv50_fifo_destroy_context;
393 engine->fifo.load_context = nv50_fifo_load_context;
394 engine->fifo.unload_context = nv50_fifo_unload_context;
56ac7475 395 engine->fifo.tlb_flush = nv50_fifo_tlb_flush;
c88c2e06
FJ		 396 engine->display.early_init = nv50_display_early_init;
397 engine->display.late_takedown = nv50_display_late_takedown;
398 engine->display.create = nv50_display_create;
399 engine->display.init = nv50_display_init;
400 engine->display.destroy = nv50_display_destroy;
ee2e0131 401 engine->gpio.init = nv50_gpio_init;
2cbd4c81 402 engine->gpio.takedown = nv50_gpio_fini;
ee2e0131
BS		 403 engine->gpio.get = nv50_gpio_get;
404 engine->gpio.set = nv50_gpio_set;
fce2bad0
BS		 405 engine->gpio.irq_register = nv50_gpio_irq_register;
406 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
ee2e0131 407 engine->gpio.irq_enable = nv50_gpio_irq_enable;
fade7ad5 408 switch (dev_priv->chipset) {
bd2e597d
BS		 409 case 0x84:
410 case 0x86:
411 case 0x92:
412 case 0x94:
413 case 0x96:
414 case 0x98:
415 case 0xa0:
5f80198e
BS		 416 case 0xaa:
417 case 0xac:
bd2e597d 418 case 0x50:
fade7ad5
BS		 419 engine->pm.clock_get = nv50_pm_clock_get;
420 engine->pm.clock_pre = nv50_pm_clock_pre;
421 engine->pm.clock_set = nv50_pm_clock_set;
422 break;
bd2e597d
BS		 423 default:
424 engine->pm.clock_get = nva3_pm_clock_get;
425 engine->pm.clock_pre = nva3_pm_clock_pre;
426 engine->pm.clock_set = nva3_pm_clock_set;
427 break;
fade7ad5 428 }
02c30ca0
BS		 429 engine->pm.voltage_get = nouveau_voltage_gpio_get;
430 engine->pm.voltage_set = nouveau_voltage_gpio_set;
8155cac4
FJ		 431 if (dev_priv->chipset >= 0x84)
432 engine->pm.temp_get = nv84_temp_get;
433 else
434 engine->pm.temp_get = nv40_temp_get;
bd2e597d
BS		 435 switch (dev_priv->chipset) {
436 case 0x84:
437 case 0x86:
438 case 0x92:
439 case 0x94:
440 case 0x96:
441 case 0xa0:
442 engine->crypt.init = nv84_crypt_init;
443 engine->crypt.takedown = nv84_crypt_fini;
444 engine->crypt.create_context = nv84_crypt_create_context;
445 engine->crypt.destroy_context = nv84_crypt_destroy_context;
2cb3d3b6 446 engine->crypt.tlb_flush = nv84_crypt_tlb_flush;
bd2e597d
BS		 447 break;
448 default:
449 engine->crypt.init = nouveau_stub_init;
450 engine->crypt.takedown = nouveau_stub_takedown;
451 break;
452 }
60d2a88a
BS		 453 engine->vram.init = nv50_vram_init;
454 engine->vram.get = nv50_vram_new;
455 engine->vram.put = nv50_vram_del;
456 engine->vram.flags_valid = nv50_vram_flags_valid;
6ee73861 457 break;
4b223eef
BS		 458 case 0xC0:
459 engine->instmem.init = nvc0_instmem_init;
460 engine->instmem.takedown = nvc0_instmem_takedown;
461 engine->instmem.suspend = nvc0_instmem_suspend;
462 engine->instmem.resume = nvc0_instmem_resume;
8984e046
BS		 463 engine->instmem.get = nv50_instmem_get;
464 engine->instmem.put = nv50_instmem_put;
465 engine->instmem.map = nv50_instmem_map;
466 engine->instmem.unmap = nv50_instmem_unmap;
467 engine->instmem.flush = nv84_instmem_flush;
4b223eef
BS		 468 engine->mc.init = nv50_mc_init;
469 engine->mc.takedown = nv50_mc_takedown;
470 engine->timer.init = nv04_timer_init;
471 engine->timer.read = nv04_timer_read;
472 engine->timer.takedown = nv04_timer_takedown;
473 engine->fb.init = nvc0_fb_init;
474 engine->fb.takedown = nvc0_fb_takedown;
4b223eef
BS		 475 engine->graph.init = nvc0_graph_init;
476 engine->graph.takedown = nvc0_graph_takedown;
477 engine->graph.fifo_access = nvc0_graph_fifo_access;
478 engine->graph.channel = nvc0_graph_channel;
479 engine->graph.create_context = nvc0_graph_create_context;
480 engine->graph.destroy_context = nvc0_graph_destroy_context;
481 engine->graph.load_context = nvc0_graph_load_context;
482 engine->graph.unload_context = nvc0_graph_unload_context;
483 engine->fifo.channels = 128;
484 engine->fifo.init = nvc0_fifo_init;
485 engine->fifo.takedown = nvc0_fifo_takedown;
486 engine->fifo.disable = nvc0_fifo_disable;
487 engine->fifo.enable = nvc0_fifo_enable;
488 engine->fifo.reassign = nvc0_fifo_reassign;
489 engine->fifo.channel_id = nvc0_fifo_channel_id;
490 engine->fifo.create_context = nvc0_fifo_create_context;
491 engine->fifo.destroy_context = nvc0_fifo_destroy_context;
492 engine->fifo.load_context = nvc0_fifo_load_context;
493 engine->fifo.unload_context = nvc0_fifo_unload_context;
494 engine->display.early_init = nv50_display_early_init;
495 engine->display.late_takedown = nv50_display_late_takedown;
496 engine->display.create = nv50_display_create;
497 engine->display.init = nv50_display_init;
498 engine->display.destroy = nv50_display_destroy;
499 engine->gpio.init = nv50_gpio_init;
500 engine->gpio.takedown = nouveau_stub_takedown;
501 engine->gpio.get = nv50_gpio_get;
502 engine->gpio.set = nv50_gpio_set;
fce2bad0
BS		 503 engine->gpio.irq_register = nv50_gpio_irq_register;
504 engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
4b223eef 505 engine->gpio.irq_enable = nv50_gpio_irq_enable;
bd2e597d
BS		 506 engine->crypt.init = nouveau_stub_init;
507 engine->crypt.takedown = nouveau_stub_takedown;
8984e046
BS		 508 engine->vram.init = nvc0_vram_init;
509 engine->vram.get = nvc0_vram_new;
510 engine->vram.put = nv50_vram_del;
511 engine->vram.flags_valid = nvc0_vram_flags_valid;
4b223eef 512 break;
6ee73861
BS		 513 default:
514 NV_ERROR(dev, "NV%02x unsupported\n", dev_priv->chipset);
515 return 1;
516 }
517
518 return 0;
519}
520
521static unsigned int
522nouveau_vga_set_decode(void *priv, bool state)
523{
9967b948
MK		 524 struct drm_device *dev = priv;
525 struct drm_nouveau_private *dev_priv = dev->dev_private;
526
527 if (dev_priv->chipset >= 0x40)
528 nv_wr32(dev, 0x88054, state);
529 else
530 nv_wr32(dev, 0x1854, state);
531
6ee73861
BS		 532 if (state)
533 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
534 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
535 else
536 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
537}
538
0735f62e
BS		 539static int
540nouveau_card_init_channel(struct drm_device *dev)
541{
542 struct drm_nouveau_private *dev_priv = dev->dev_private;
0735f62e
BS		 543 int ret;
544
545 ret = nouveau_channel_alloc(dev, &dev_priv->channel,
a8eaebc6 546 (struct drm_file *)-2, NvDmaFB, NvDmaTT);
0735f62e
BS		 547 if (ret)
548 return ret;
549
cff5c133 550 mutex_unlock(&dev_priv->channel->mutex);
0735f62e 551 return 0;
0735f62e
BS		 552}
553
6a9ee8af
DA		 554static void nouveau_switcheroo_set_state(struct pci_dev *pdev,
555 enum vga_switcheroo_state state)
556{
fbf81762 557 struct drm_device *dev = pci_get_drvdata(pdev);
6a9ee8af
DA		 558 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
559 if (state == VGA_SWITCHEROO_ON) {
560 printk(KERN_ERR "VGA switcheroo: switched nouveau on\n");
5bcf719b 561 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
6a9ee8af 562 nouveau_pci_resume(pdev);
fbf81762 563 drm_kms_helper_poll_enable(dev);
5bcf719b 564 dev->switch_power_state = DRM_SWITCH_POWER_ON;
6a9ee8af
DA		 565 } else {
566 printk(KERN_ERR "VGA switcheroo: switched nouveau off\n");
5bcf719b 567 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
fbf81762 568 drm_kms_helper_poll_disable(dev);
6a9ee8af 569 nouveau_pci_suspend(pdev, pmm);
5bcf719b 570 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
6a9ee8af
DA		 571 }
572}
573
8d608aa6
DA		 574static void nouveau_switcheroo_reprobe(struct pci_dev *pdev)
575{
576 struct drm_device *dev = pci_get_drvdata(pdev);
577 nouveau_fbcon_output_poll_changed(dev);
578}
579
6a9ee8af
DA		 580static bool nouveau_switcheroo_can_switch(struct pci_dev *pdev)
581{
582 struct drm_device *dev = pci_get_drvdata(pdev);
583 bool can_switch;
584
585 spin_lock(&dev->count_lock);
586 can_switch = (dev->open_count == 0);
587 spin_unlock(&dev->count_lock);
588 return can_switch;
589}
590
6ee73861
BS		 591int
592nouveau_card_init(struct drm_device *dev)
593{
594 struct drm_nouveau_private *dev_priv = dev->dev_private;
595 struct nouveau_engine *engine;
6ee73861
BS		 596 int ret;
597
6ee73861 598 vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
6a9ee8af 599 vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
8d608aa6 600 nouveau_switcheroo_reprobe,
6a9ee8af 601 nouveau_switcheroo_can_switch);
6ee73861
BS		 602
603 /* Initialise internal driver API hooks */
604 ret = nouveau_init_engine_ptrs(dev);
605 if (ret)
c5804be0 606 goto out;
6ee73861 607 engine = &dev_priv->engine;
cff5c133 608 spin_lock_init(&dev_priv->channels.lock);
a5cf68b0 609 spin_lock_init(&dev_priv->tile.lock);
ff9e5279 610 spin_lock_init(&dev_priv->context_switch_lock);
04eb34a4 611 spin_lock_init(&dev_priv->vm_lock);
6ee73861 612
c88c2e06
FJ		 613 /* Make the CRTCs and I2C buses accessible */
614 ret = engine->display.early_init(dev);
615 if (ret)
616 goto out;
617
6ee73861 618 /* Parse BIOS tables / Run init tables if card not POSTed */
cd0b072f
BS		 619 ret = nouveau_bios_init(dev);
620 if (ret)
c88c2e06 621 goto out_display_early;
6ee73861 622
330c5988
BS		 623 nouveau_pm_init(dev);
624
fbd2895e 625 ret = nouveau_mem_vram_init(dev);
a76fb4e8
BS		 626 if (ret)
627 goto out_bios;
628
fbd2895e 629 ret = nouveau_gpuobj_init(dev);
6ee73861 630 if (ret)
fbd2895e 631 goto out_vram;
6ee73861 632
6ee73861
BS		 633 ret = engine->instmem.init(dev);
634 if (ret)
fbd2895e 635 goto out_gpuobj;
6ee73861 636
fbd2895e 637 ret = nouveau_mem_gart_init(dev);
6ee73861 638 if (ret)
c5804be0 639 goto out_instmem;
6ee73861 640
6ee73861
BS		 641 /* PMC */
642 ret = engine->mc.init(dev);
643 if (ret)
fbd2895e 644 goto out_gart;
6ee73861 645
ee2e0131
BS		 646 /* PGPIO */
647 ret = engine->gpio.init(dev);
648 if (ret)
649 goto out_mc;
650
6ee73861
BS		 651 /* PTIMER */
652 ret = engine->timer.init(dev);
653 if (ret)
ee2e0131 654 goto out_gpio;
6ee73861
BS		 655
656 /* PFB */
657 ret = engine->fb.init(dev);
658 if (ret)
c5804be0 659 goto out_timer;
6ee73861 660
a32ed69d
MK		 661 if (nouveau_noaccel)
662 engine->graph.accel_blocked = true;
663 else {
664 /* PGRAPH */
665 ret = engine->graph.init(dev);
666 if (ret)
667 goto out_fb;
6ee73861 668
bd2e597d
BS		 669 /* PCRYPT */
670 ret = engine->crypt.init(dev);
671 if (ret)
672 goto out_graph;
673
a32ed69d
MK		 674 /* PFIFO */
675 ret = engine->fifo.init(dev);
676 if (ret)
bd2e597d 677 goto out_crypt;
a32ed69d 678 }
6ee73861 679
c88c2e06 680 ret = engine->display.create(dev);
e88efe05
BS		 681 if (ret)
682 goto out_fifo;
683
042206c0 684 ret = drm_vblank_init(dev, nv_two_heads(dev) ? 2 : 1);
6ee73861 685 if (ret)
042206c0 686 goto out_vblank;
6ee73861 687
042206c0 688 ret = nouveau_irq_init(dev);
6ee73861 689 if (ret)
042206c0 690 goto out_vblank;
6ee73861
BS		 691
692 /* what about PVIDEO/PCRTC/PRAMDAC etc? */
693
0735f62e 694 if (!engine->graph.accel_blocked) {
0c6c1c2f 695 ret = nouveau_fence_init(dev);
0735f62e
BS		 696 if (ret)
697 goto out_irq;
0c6c1c2f
FJ		 698
699 ret = nouveau_card_init_channel(dev);
700 if (ret)
701 goto out_fence;
6ee73861
BS		 702 }
703
cd0b072f
BS		 704 nouveau_fbcon_init(dev);
705 drm_kms_helper_poll_init(dev);
6ee73861 706 return 0;
c5804be0 707
0c6c1c2f
FJ		 708out_fence:
709 nouveau_fence_fini(dev);
c5804be0 710out_irq:
35fa2f2a 711 nouveau_irq_fini(dev);
042206c0
FJ		 712out_vblank:
713 drm_vblank_cleanup(dev);
c88c2e06 714 engine->display.destroy(dev);
c5804be0 715out_fifo:
a32ed69d
MK		 716 if (!nouveau_noaccel)
717 engine->fifo.takedown(dev);
bd2e597d
BS		 718out_crypt:
719 if (!nouveau_noaccel)
720 engine->crypt.takedown(dev);
c5804be0 721out_graph:
a32ed69d
MK		 722 if (!nouveau_noaccel)
723 engine->graph.takedown(dev);
c5804be0
MK		 724out_fb:
725 engine->fb.takedown(dev);
726out_timer:
727 engine->timer.takedown(dev);
ee2e0131
BS		 728out_gpio:
729 engine->gpio.takedown(dev);
c5804be0
MK		 730out_mc:
731 engine->mc.takedown(dev);
fbd2895e
BS		 732out_gart:
733 nouveau_mem_gart_fini(dev);
c5804be0
MK		 734out_instmem:
735 engine->instmem.takedown(dev);
fbd2895e
BS		 736out_gpuobj:
737 nouveau_gpuobj_takedown(dev);
738out_vram:
739 nouveau_mem_vram_fini(dev);
c5804be0 740out_bios:
330c5988 741 nouveau_pm_fini(dev);
c5804be0 742 nouveau_bios_takedown(dev);
c88c2e06
FJ		 743out_display_early:
744 engine->display.late_takedown(dev);
c5804be0
MK		 745out:
746 vga_client_register(dev->pdev, NULL, NULL, NULL);
747 return ret;
6ee73861
BS		 748}
749
750static void nouveau_card_takedown(struct drm_device *dev)
751{
752 struct drm_nouveau_private *dev_priv = dev->dev_private;
753 struct nouveau_engine *engine = &dev_priv->engine;
754
0c6c1c2f
FJ		 755 if (!engine->graph.accel_blocked) {
756 nouveau_fence_fini(dev);
36c952e8 757 nouveau_channel_put_unlocked(&dev_priv->channel);
b6d3d871 758 }
6ee73861 759
b6d3d871
BS		 760 if (!nouveau_noaccel) {
761 engine->fifo.takedown(dev);
bd2e597d 762 engine->crypt.takedown(dev);
b6d3d871
BS		 763 engine->graph.takedown(dev);
764 }
765 engine->fb.takedown(dev);
766 engine->timer.takedown(dev);
ee2e0131 767 engine->gpio.takedown(dev);
b6d3d871 768 engine->mc.takedown(dev);
c88c2e06 769 engine->display.late_takedown(dev);
6ee73861 770
7a7b94ad
JR		 771 if (dev_priv->vga_ram) {
772 nouveau_bo_unpin(dev_priv->vga_ram);
773 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
774 }
775
b6d3d871
BS		 776 mutex_lock(&dev->struct_mutex);
777 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM);
778 ttm_bo_clean_mm(&dev_priv->ttm.bdev, TTM_PL_TT);
779 mutex_unlock(&dev->struct_mutex);
fbd2895e 780 nouveau_mem_gart_fini(dev);
6ee73861 781
b6d3d871 782 engine->instmem.takedown(dev);
fbd2895e
BS		 783 nouveau_gpuobj_takedown(dev);
784 nouveau_mem_vram_fini(dev);
6ee73861 785
35fa2f2a 786 nouveau_irq_fini(dev);
042206c0 787 drm_vblank_cleanup(dev);
6ee73861 788
330c5988 789 nouveau_pm_fini(dev);
b6d3d871 790 nouveau_bios_takedown(dev);
6ee73861 791
b6d3d871 792 vga_client_register(dev->pdev, NULL, NULL, NULL);
6ee73861
BS		 793}
794
795/* here a client dies, release the stuff that was allocated for its
796 * file_priv */
797void nouveau_preclose(struct drm_device *dev, struct drm_file *file_priv)
798{
799 nouveau_channel_cleanup(dev, file_priv);
800}
801
802/* first module load, setup the mmio/fb mapping */
803/* KMS: we need mmio at load time, not when the first drm client opens. */
804int nouveau_firstopen(struct drm_device *dev)
805{
806 return 0;
807}
808
809/* if we have an OF card, copy vbios to RAMIN */
810static void nouveau_OF_copy_vbios_to_ramin(struct drm_device *dev)
811{
812#if defined(__powerpc__)
813 int size, i;
814 const uint32_t *bios;
815 struct device_node *dn = pci_device_to_OF_node(dev->pdev);
816 if (!dn) {
817 NV_INFO(dev, "Unable to get the OF node\n");
818 return;
819 }
820
821 bios = of_get_property(dn, "NVDA,BMP", &size);
822 if (bios) {
823 for (i = 0; i < size; i += 4)
824 nv_wi32(dev, i, bios[i/4]);
825 NV_INFO(dev, "OF bios successfully copied (%d bytes)\n", size);
826 } else {
827 NV_INFO(dev, "Unable to get the OF bios\n");
828 }
829#endif
830}
831
06415c56
MS		 832static struct apertures_struct *nouveau_get_apertures(struct drm_device *dev)
833{
834 struct pci_dev *pdev = dev->pdev;
835 struct apertures_struct *aper = alloc_apertures(3);
836 if (!aper)
837 return NULL;
838
839 aper->ranges[0].base = pci_resource_start(pdev, 1);
840 aper->ranges[0].size = pci_resource_len(pdev, 1);
841 aper->count = 1;
842
843 if (pci_resource_len(pdev, 2)) {
844 aper->ranges[aper->count].base = pci_resource_start(pdev, 2);
845 aper->ranges[aper->count].size = pci_resource_len(pdev, 2);
846 aper->count++;
847 }
848
849 if (pci_resource_len(pdev, 3)) {
850 aper->ranges[aper->count].base = pci_resource_start(pdev, 3);
851 aper->ranges[aper->count].size = pci_resource_len(pdev, 3);
852 aper->count++;
853 }
854
855 return aper;
856}
857
858static int nouveau_remove_conflicting_drivers(struct drm_device *dev)
859{
860 struct drm_nouveau_private *dev_priv = dev->dev_private;
3b9676e7 861 bool primary = false;
06415c56
MS		 862 dev_priv->apertures = nouveau_get_apertures(dev);
863 if (!dev_priv->apertures)
864 return -ENOMEM;
865
3b9676e7
MS		 866#ifdef CONFIG_X86
867 primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
868#endif
869
870 remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
06415c56
MS		 871 return 0;
872}
873
6ee73861
BS		 874int nouveau_load(struct drm_device *dev, unsigned long flags)
875{
876 struct drm_nouveau_private *dev_priv;
877 uint32_t reg0;
878 resource_size_t mmio_start_offs;
cd0b072f 879 int ret;
6ee73861
BS		 880
881 dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
a0d069ea
DC		 882 if (!dev_priv) {
883 ret = -ENOMEM;
884 goto err_out;
885 }
6ee73861
BS		 886 dev->dev_private = dev_priv;
887 dev_priv->dev = dev;
888
889 dev_priv->flags = flags & NOUVEAU_FLAGS;
6ee73861
BS		 890
891 NV_DEBUG(dev, "vendor: 0x%X device: 0x%X class: 0x%X\n",
892 dev->pci_vendor, dev->pci_device, dev->pdev->class);
893
6ee73861
BS		 894 /* resource 0 is mmio regs */
895 /* resource 1 is linear FB */
896 /* resource 2 is RAMIN (mmio regs + 0x1000000) */
897 /* resource 6 is bios */
898
899 /* map the mmio regs */
900 mmio_start_offs = pci_resource_start(dev->pdev, 0);
901 dev_priv->mmio = ioremap(mmio_start_offs, 0x00800000);
902 if (!dev_priv->mmio) {
903 NV_ERROR(dev, "Unable to initialize the mmio mapping. "
904 "Please report your setup to " DRIVER_EMAIL "\n");
a0d069ea 905 ret = -EINVAL;
d82f8e6c 906 goto err_priv;
6ee73861
BS		 907 }
908 NV_DEBUG(dev, "regs mapped ok at 0x%llx\n",
909 (unsigned long long)mmio_start_offs);
910
911#ifdef __BIG_ENDIAN
912 /* Put the card in BE mode if it's not */
913 if (nv_rd32(dev, NV03_PMC_BOOT_1))
914 nv_wr32(dev, NV03_PMC_BOOT_1, 0x00000001);
915
916 DRM_MEMORYBARRIER();
917#endif
918
919 /* Time to determine the card architecture */
920 reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
921
922 /* We're dealing with >=NV10 */
923 if ((reg0 & 0x0f000000) > 0) {
924 /* Bit 27-20 contain the architecture in hex */
925 dev_priv->chipset = (reg0 & 0xff00000) >> 20;
926 /* NV04 or NV05 */
927 } else if ((reg0 & 0xff00fff0) == 0x20004000) {
1dee7a93
BS		 928 if (reg0 & 0x00f00000)
929 dev_priv->chipset = 0x05;
930 else
931 dev_priv->chipset = 0x04;
6ee73861
BS		 932 } else
933 dev_priv->chipset = 0xff;
934
935 switch (dev_priv->chipset & 0xf0) {
936 case 0x00:
937 case 0x10:
938 case 0x20:
939 case 0x30:
940 dev_priv->card_type = dev_priv->chipset & 0xf0;
941 break;
942 case 0x40:
943 case 0x60:
944 dev_priv->card_type = NV_40;
945 break;
946 case 0x50:
947 case 0x80:
948 case 0x90:
949 case 0xa0:
950 dev_priv->card_type = NV_50;
951 break;
4b223eef
BS		 952 case 0xc0:
953 dev_priv->card_type = NV_C0;
954 break;
6ee73861
BS		 955 default:
956 NV_INFO(dev, "Unsupported chipset 0x%08x\n", reg0);
a0d069ea
DC		 957 ret = -EINVAL;
958 goto err_mmio;
6ee73861
BS		 959 }
960
961 NV_INFO(dev, "Detected an NV%2x generation card (0x%08x)\n",
962 dev_priv->card_type, reg0);
963
cd0b072f
BS		 964 ret = nouveau_remove_conflicting_drivers(dev);
965 if (ret)
a0d069ea 966 goto err_mmio;
06415c56 967
25985edc 968 /* Map PRAMIN BAR, or on older cards, the aperture within BAR0 */
6ee73861
BS		 969 if (dev_priv->card_type >= NV_40) {
970 int ramin_bar = 2;
971 if (pci_resource_len(dev->pdev, ramin_bar) == 0)
972 ramin_bar = 3;
973
974 dev_priv->ramin_size = pci_resource_len(dev->pdev, ramin_bar);
6d696305
BS		 975 dev_priv->ramin =
976 ioremap(pci_resource_start(dev->pdev, ramin_bar),
6ee73861
BS		 977 dev_priv->ramin_size);
978 if (!dev_priv->ramin) {
6d696305 979 NV_ERROR(dev, "Failed to PRAMIN BAR");
a0d069ea
DC		 980 ret = -ENOMEM;
981 goto err_mmio;
6ee73861 982 }
6d696305 983 } else {
6ee73861
BS		 984 dev_priv->ramin_size = 1 * 1024 * 1024;
985 dev_priv->ramin = ioremap(mmio_start_offs + NV_RAMIN,
6d696305 986 dev_priv->ramin_size);
6ee73861
BS		 987 if (!dev_priv->ramin) {
988 NV_ERROR(dev, "Failed to map BAR0 PRAMIN.\n");
a0d069ea
DC		 989 ret = -ENOMEM;
990 goto err_mmio;
6ee73861
BS		 991 }
992 }
993
994 nouveau_OF_copy_vbios_to_ramin(dev);
995
996 /* Special flags */
997 if (dev->pci_device == 0x01a0)
998 dev_priv->flags |= NV_NFORCE;
999 else if (dev->pci_device == 0x01f0)
1000 dev_priv->flags |= NV_NFORCE2;
1001
1002 /* For kernel modesetting, init card now and bring up fbcon */
cd0b072f
BS		 1003 ret = nouveau_card_init(dev);
1004 if (ret)
a0d069ea 1005 goto err_ramin;
6ee73861
BS		 1006
1007 return 0;
a0d069ea
DC		 1008
1009err_ramin:
1010 iounmap(dev_priv->ramin);
1011err_mmio:
1012 iounmap(dev_priv->mmio);
a0d069ea
DC		 1013err_priv:
1014 kfree(dev_priv);
1015 dev->dev_private = NULL;
1016err_out:
1017 return ret;
6ee73861
BS		 1018}
1019
6ee73861
BS		 1020void nouveau_lastclose(struct drm_device *dev)
1021{
5ccb377f 1022 vga_switcheroo_process_delayed_switch();
6ee73861
BS		 1023}
1024
1025int nouveau_unload(struct drm_device *dev)
1026{
1027 struct drm_nouveau_private *dev_priv = dev->dev_private;
c88c2e06 1028 struct nouveau_engine *engine = &dev_priv->engine;
6ee73861 1029
cd0b072f
BS		 1030 drm_kms_helper_poll_fini(dev);
1031 nouveau_fbcon_fini(dev);
c88c2e06 1032 engine->display.destroy(dev);
cd0b072f 1033 nouveau_card_takedown(dev);
6ee73861
BS		 1034
1035 iounmap(dev_priv->mmio);
1036 iounmap(dev_priv->ramin);
1037
1038 kfree(dev_priv);
1039 dev->dev_private = NULL;
1040 return 0;
1041}
1042
6ee73861
BS		 1043int nouveau_ioctl_getparam(struct drm_device *dev, void *data,
1044 struct drm_file *file_priv)
1045{
1046 struct drm_nouveau_private *dev_priv = dev->dev_private;
1047 struct drm_nouveau_getparam *getparam = data;
1048
6ee73861
BS		 1049 switch (getparam->param) {
1050 case NOUVEAU_GETPARAM_CHIPSET_ID:
1051 getparam->value = dev_priv->chipset;
1052 break;
1053 case NOUVEAU_GETPARAM_PCI_VENDOR:
1054 getparam->value = dev->pci_vendor;
1055 break;
1056 case NOUVEAU_GETPARAM_PCI_DEVICE:
1057 getparam->value = dev->pci_device;
1058 break;
1059 case NOUVEAU_GETPARAM_BUS_TYPE:
8410ea3b 1060 if (drm_pci_device_is_agp(dev))
6ee73861 1061 getparam->value = NV_AGP;
8410ea3b 1062 else if (drm_pci_device_is_pcie(dev))
6ee73861
BS		 1063 getparam->value = NV_PCIE;
1064 else
1065 getparam->value = NV_PCI;
1066 break;
6ee73861
BS		 1067 case NOUVEAU_GETPARAM_FB_SIZE:
1068 getparam->value = dev_priv->fb_available_size;
1069 break;
1070 case NOUVEAU_GETPARAM_AGP_SIZE:
1071 getparam->value = dev_priv->gart_info.aper_size;
1072 break;
1073 case NOUVEAU_GETPARAM_VM_VRAM_BASE:
6d6c5a15 1074 getparam->value = 0; /* deprecated */
6ee73861 1075 break;
7fc74f17
MK		 1076 case NOUVEAU_GETPARAM_PTIMER_TIME:
1077 getparam->value = dev_priv->engine.timer.read(dev);
1078 break;
f13b3263
FJ		 1079 case NOUVEAU_GETPARAM_HAS_BO_USAGE:
1080 getparam->value = 1;
1081 break;
332b242f 1082 case NOUVEAU_GETPARAM_HAS_PAGEFLIP:
bd2f2037 1083 getparam->value = 1;
332b242f 1084 break;
69c9700b
MK		 1085 case NOUVEAU_GETPARAM_GRAPH_UNITS:
1086 /* NV40 and NV50 versions are quite different, but register
1087 * address is the same. User is supposed to know the card
1088 * family anyway... */
1089 if (dev_priv->chipset >= 0x40) {
1090 getparam->value = nv_rd32(dev, NV40_PMC_GRAPH_UNITS);
1091 break;
1092 }
1093 /* FALLTHRU */
6ee73861 1094 default:
1397b42b 1095 NV_DEBUG(dev, "unknown parameter %lld\n", getparam->param);
6ee73861
BS		 1096 return -EINVAL;
1097 }
1098
1099 return 0;
1100}
1101
1102int
1103nouveau_ioctl_setparam(struct drm_device *dev, void *data,
1104 struct drm_file *file_priv)
1105{
1106 struct drm_nouveau_setparam *setparam = data;
1107
6ee73861
BS		 1108 switch (setparam->param) {
1109 default:
1397b42b 1110 NV_DEBUG(dev, "unknown parameter %lld\n", setparam->param);
6ee73861
BS		 1111 return -EINVAL;
1112 }
1113
1114 return 0;
1115}
1116
1117/* Wait until (value(reg) & mask) == val, up until timeout has hit */
12fb9525
BS		 1118bool
1119nouveau_wait_eq(struct drm_device *dev, uint64_t timeout,
1120 uint32_t reg, uint32_t mask, uint32_t val)
6ee73861
BS		 1121{
1122 struct drm_nouveau_private *dev_priv = dev->dev_private;
1123 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1124 uint64_t start = ptimer->read(dev);
1125
1126 do {
1127 if ((nv_rd32(dev, reg) & mask) == val)
1128 return true;
1129 } while (ptimer->read(dev) - start < timeout);
1130
1131 return false;
1132}
1133
12fb9525
BS		 1134/* Wait until (value(reg) & mask) != val, up until timeout has hit */
1135bool
1136nouveau_wait_ne(struct drm_device *dev, uint64_t timeout,
1137 uint32_t reg, uint32_t mask, uint32_t val)
1138{
1139 struct drm_nouveau_private *dev_priv = dev->dev_private;
1140 struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
1141 uint64_t start = ptimer->read(dev);
1142
1143 do {
1144 if ((nv_rd32(dev, reg) & mask) != val)
1145 return true;
1146 } while (ptimer->read(dev) - start < timeout);
1147
1148 return false;
1149}
1150
6ee73861
BS		 1151/* Waits for PGRAPH to go completely idle */
1152bool nouveau_wait_for_idle(struct drm_device *dev)
1153{
0541324a
FJ		 1154 struct drm_nouveau_private *dev_priv = dev->dev_private;
1155 uint32_t mask = ~0;
1156
1157 if (dev_priv->card_type == NV_40)
1158 mask &= ~NV40_PGRAPH_STATUS_SYNC_STALL;
1159
1160 if (!nv_wait(dev, NV04_PGRAPH_STATUS, mask, 0)) {
6ee73861
BS		 1161 NV_ERROR(dev, "PGRAPH idle timed out with status 0x%08x\n",
1162 nv_rd32(dev, NV04_PGRAPH_STATUS));
1163 return false;
1164 }
1165
1166 return true;
1167}
1168
kernel source for telekom puls (alcatel/mediatek)