[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nouveau_perf.c

/*
 * Copyright 2010 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <drm/drmP.h>

#include "nouveau_drm.h"
#include "nouveau_reg.h"
#include "nouveau_pm.h"

static u8 *
nouveau_perf_table(struct drm_device *dev, u8 *ver)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nvbios *bios = &drm->vbios;
	struct bit_entry P;

	if (!bit_table(dev, 'P', &P) && P.version && P.version <= 2) {
		u8 *perf = ROMPTR(dev, P.data[0]);
		if (perf) {
			*ver = perf[0];
			return perf;
		}
	}

	if (bios->type == NVBIOS_BMP) {
		if (bios->data[bios->offset + 6] >= 0x25) {
			u8 *perf = ROMPTR(dev, bios->data[bios->offset + 0x94]);
			if (perf) {
				*ver = perf[1];
				return perf;
			}
		}
	}

	return NULL;
}

static u8 *
nouveau_perf_entry(struct drm_device *dev, int idx,
		   u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
	u8 *perf = nouveau_perf_table(dev, ver);
	if (perf) {
		if (*ver >= 0x12 && *ver < 0x20 && idx < perf[2]) {
			*hdr = perf[3];
			*cnt = 0;
			*len = 0;
			return perf + perf[0] + idx * perf[3];
		} else
		if (*ver >= 0x20 && *ver < 0x40 && idx < perf[2]) {
			*hdr = perf[3];
			*cnt = perf[4];
			*len = perf[5];
			return perf + perf[1] + idx * (*hdr + (*cnt * *len));
		} else
		if (*ver >= 0x40 && *ver < 0x41 && idx < perf[5]) {
			*hdr = perf[2];
			*cnt = perf[4];
			*len = perf[3];
			return perf + perf[1] + idx * (*hdr + (*cnt * *len));
		}
	}
	return NULL;
}

u8 *
nouveau_perf_rammap(struct drm_device *dev, u32 freq,
		    u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct bit_entry P;
	u8 *perf, i = 0;

	if (!bit_table(dev, 'P', &P) && P.version == 2) {
		u8 *rammap = ROMPTR(dev, P.data[4]);
		if (rammap) {
			u8 *ramcfg = rammap + rammap[1];

			*ver = rammap[0];
			*hdr = rammap[2];
			*cnt = rammap[4];
			*len = rammap[3];

			freq /= 1000;
			for (i = 0; i < rammap[5]; i++) {
				if (freq >= ROM16(ramcfg[0]) &&
				    freq <= ROM16(ramcfg[2]))
					return ramcfg;

				ramcfg += *hdr + (*cnt * *len);
			}
		}

		return NULL;
	}

	if (nv_device(drm->device)->chipset == 0x49 ||
	    nv_device(drm->device)->chipset == 0x4b)
		freq /= 2;

	while ((perf = nouveau_perf_entry(dev, i++, ver, hdr, cnt, len))) {
		if (*ver >= 0x20 && *ver < 0x25) {
			if (perf[0] != 0xff && freq <= ROM16(perf[11]) * 1000)
				break;
		} else
		if (*ver >= 0x25 && *ver < 0x40) {
			if (perf[0] != 0xff && freq <= ROM16(perf[12]) * 1000)
				break;
		}
	}

	if (perf) {
		u8 *ramcfg = perf + *hdr;
		*ver = 0x00;
		*hdr = 0;
		return ramcfg;
	}

	return NULL;
}

u8 *
nouveau_perf_ramcfg(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
{
	struct nouveau_device *device = nouveau_dev(dev);
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nvbios *bios = &drm->vbios;
	u8 strap, hdr, cnt;
	u8 *rammap;

	strap = (nv_rd32(device, 0x101000) & 0x0000003c) >> 2;
	if (bios->ram_restrict_tbl_ptr)
		strap = bios->data[bios->ram_restrict_tbl_ptr + strap];

	rammap = nouveau_perf_rammap(dev, freq, ver, &hdr, &cnt, len);
	if (rammap && strap < cnt)
		return rammap + hdr + (strap * *len);

	return NULL;
}

u8 *
nouveau_perf_timing(struct drm_device *dev, u32 freq, u8 *ver, u8 *len)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nvbios *bios = &drm->vbios;
	struct bit_entry P;
	u8 *perf, *timing = NULL;
	u8 i = 0, hdr, cnt;

	if (bios->type == NVBIOS_BMP) {
		while ((perf = nouveau_perf_entry(dev, i++, ver, &hdr, &cnt,
						  len)) && *ver == 0x15) {
			if (freq <= ROM32(perf[5]) * 20) {
				*ver = 0x00;
				*len = 14;
				return perf + 41;
			}
		}
		return NULL;
	}

	if (!bit_table(dev, 'P', &P)) {
		if (P.version == 1)
			timing = ROMPTR(dev, P.data[4]);
		else
		if (P.version == 2)
			timing = ROMPTR(dev, P.data[8]);
	}

	if (timing && timing[0] == 0x10) {
		u8 *ramcfg = nouveau_perf_ramcfg(dev, freq, ver, len);
		if (ramcfg && ramcfg[1] < timing[2]) {
			*ver = timing[0];
			*len = timing[3];
			return timing + timing[1] + (ramcfg[1] * timing[3]);
		}
	}

	return NULL;
}

static void
legacy_perf_init(struct drm_device *dev)
{
	struct nouveau_device *device = nouveau_dev(dev);
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nvbios *bios = &drm->vbios;
	struct nouveau_pm *pm = nouveau_pm(dev);
	char *perf, *entry, *bmp = &bios->data[bios->offset];
	int headerlen, use_straps;

	if (bmp[5] < 0x5 || bmp[6] < 0x14) {
		NV_DEBUG(drm, "BMP version too old for perf\n");
		return;
	}

	perf = ROMPTR(dev, bmp[0x73]);
	if (!perf) {
		NV_DEBUG(drm, "No memclock table pointer found.\n");
		return;
	}

	switch (perf[0]) {
	case 0x12:
	case 0x14:
	case 0x18:
		use_straps = 0;
		headerlen = 1;
		break;
	case 0x01:
		use_straps = perf[1] & 1;
		headerlen = (use_straps ? 8 : 2);
		break;
	default:
		NV_WARN(drm, "Unknown memclock table version %x.\n", perf[0]);
		return;
	}

	entry = perf + headerlen;
	if (use_straps)
		entry += (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;

	sprintf(pm->perflvl[0].name, "performance_level_0");
	pm->perflvl[0].memory = ROM16(entry[0]) * 20;
	pm->nr_perflvl = 1;
}

static void
nouveau_perf_voltage(struct drm_device *dev, struct nouveau_pm_level *perflvl)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct bit_entry P;
	u8 *vmap;
	int id;

	id = perflvl->volt_min;
	perflvl->volt_min = 0;

	/* boards using voltage table version <0x40 store the voltage
	 * level directly in the perflvl entry as a multiple of 10mV
	 */
	if (drm->pm->voltage.version < 0x40) {
		perflvl->volt_min = id * 10000;
		perflvl->volt_max = perflvl->volt_min;
		return;
	}

	/* on newer ones, the perflvl stores an index into yet another
	 * vbios table containing a min/max voltage value for the perflvl
	 */
	if (bit_table(dev, 'P', &P) || P.version != 2 || P.length < 34) {
		NV_DEBUG(drm, "where's our volt map table ptr? %d %d\n",
			 P.version, P.length);
		return;
	}

	vmap = ROMPTR(dev, P.data[32]);
	if (!vmap) {
		NV_DEBUG(drm, "volt map table pointer invalid\n");
		return;
	}

	if (id < vmap[3]) {
		vmap += vmap[1] + (vmap[2] * id);
		perflvl->volt_min = ROM32(vmap[0]);
		perflvl->volt_max = ROM32(vmap[4]);
	}
}

void
nouveau_perf_init(struct drm_device *dev)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_pm *pm = nouveau_pm(dev);
	struct nvbios *bios = &drm->vbios;
	u8 *perf, ver, hdr, cnt, len;
	int ret, vid, i = -1;

	if (bios->type == NVBIOS_BMP && bios->data[bios->offset + 6] < 0x25) {
		legacy_perf_init(dev);
		return;
	}

	perf = nouveau_perf_table(dev, &ver);

	while ((perf = nouveau_perf_entry(dev, ++i, &ver, &hdr, &cnt, &len))) {
		struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];

		if (perf[0] == 0xff)
			continue;

		switch (ver) {
		case 0x12:
		case 0x13:
		case 0x15:
			perflvl->fanspeed = perf[55];
			if (hdr > 56)
				perflvl->volt_min = perf[56];
			perflvl->core = ROM32(perf[1]) * 10;
			perflvl->memory = ROM32(perf[5]) * 20;
			break;
		case 0x21:
		case 0x23:
		case 0x24:
			perflvl->fanspeed = perf[4];
			perflvl->volt_min = perf[5];
			perflvl->shader = ROM16(perf[6]) * 1000;
			perflvl->core = perflvl->shader;
			perflvl->core += (signed char)perf[8] * 1000;
			if (nv_device(drm->device)->chipset == 0x49 ||
			    nv_device(drm->device)->chipset == 0x4b)
				perflvl->memory = ROM16(perf[11]) * 1000;
			else
				perflvl->memory = ROM16(perf[11]) * 2000;
			break;
		case 0x25:
			perflvl->fanspeed = perf[4];
			perflvl->volt_min = perf[5];
			perflvl->core = ROM16(perf[6]) * 1000;
			perflvl->shader = ROM16(perf[10]) * 1000;
			perflvl->memory = ROM16(perf[12]) * 1000;
			break;
		case 0x30:
			perflvl->memscript = ROM16(perf[2]);
		case 0x35:
			perflvl->fanspeed = perf[6];
			perflvl->volt_min = perf[7];
			perflvl->core = ROM16(perf[8]) * 1000;
			perflvl->shader = ROM16(perf[10]) * 1000;
			perflvl->memory = ROM16(perf[12]) * 1000;
			perflvl->vdec = ROM16(perf[16]) * 1000;
			perflvl->dom6 = ROM16(perf[20]) * 1000;
			break;
		case 0x40:
#define subent(n) ((ROM16(perf[hdr + (n) * len]) & 0xfff) * 1000)
			perflvl->fanspeed = 0; /*XXX*/
			perflvl->volt_min = perf[2];
			if (nv_device(drm->device)->card_type == NV_50) {
				perflvl->core   = subent(0);
				perflvl->shader = subent(1);
				perflvl->memory = subent(2);
				perflvl->vdec   = subent(3);
				perflvl->unka0  = subent(4);
			} else {
				perflvl->hub06  = subent(0);
				perflvl->hub01  = subent(1);
				perflvl->copy   = subent(2);
				perflvl->shader = subent(3);
				perflvl->rop    = subent(4);
				perflvl->memory = subent(5);
				perflvl->vdec   = subent(6);
				perflvl->daemon = subent(10);
				perflvl->hub07  = subent(11);
				perflvl->core   = perflvl->shader / 2;
			}
			break;
		}

		/* make sure vid is valid */
		nouveau_perf_voltage(dev, perflvl);
		if (pm->voltage.supported && perflvl->volt_min) {
			vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
			if (vid < 0) {
				NV_DEBUG(drm, "perflvl %d, bad vid\n", i);
				continue;
			}
		}

		/* get the corresponding memory timings */
		ret = nouveau_mem_timing_calc(dev, perflvl->memory,
					          &perflvl->timing);
		if (ret) {
			NV_DEBUG(drm, "perflvl %d, bad timing: %d\n", i, ret);
			continue;
		}

		snprintf(perflvl->name, sizeof(perflvl->name),
			 "performance_level_%d", i);
		perflvl->id = i;

		snprintf(perflvl->profile.name, sizeof(perflvl->profile.name),
			 "%d", perflvl->id);
		perflvl->profile.func = &nouveau_pm_static_profile_func;
		list_add_tail(&perflvl->profile.head, &pm->profiles);


		pm->nr_perflvl++;
	}
}

void
nouveau_perf_fini(struct drm_device *dev)
{
}
Commit	Line	Data
330c5988 BS	1	/*
	2	* Copyright 2010 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
760285e7	25	#include <drm/drmP.h>
330c5988	26
77145f1c BS	27	#include "nouveau_drm.h"
77145f1c BS	28	#include "nouveau_reg.h"
330c5988 BS	29	#include "nouveau_pm.h"
330c5988 BS	30
03ddf04b BS	31	static u8 *
	32	nouveau_perf_table(struct drm_device dev, u8 ver)
	33	{
77145f1c BS	34	struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c BS	35	struct nvbios *bios = &drm->vbios;
03ddf04b BS	36	struct bit_entry P;
	37
	38	if (!bit_table(dev, 'P', &P) && P.version && P.version <= 2) {
	39	u8 *perf = ROMPTR(dev, P.data[0]);
	40	if (perf) {
	41	*ver = perf[0];
	42	return perf;
	43	}
	44	}
	45
	46	if (bios->type == NVBIOS_BMP) {
	47	if (bios->data[bios->offset + 6] >= 0x25) {
	48	u8 *perf = ROMPTR(dev, bios->data[bios->offset + 0x94]);
	49	if (perf) {
	50	*ver = perf[1];
	51	return perf;
	52	}
	53	}
	54	}
	55
	56	return NULL;
	57	}
	58
	59	static u8 *
	60	nouveau_perf_entry(struct drm_device *dev, int idx,
	61	u8 ver, u8 hdr, u8 cnt, u8 len)
	62	{
	63	u8 *perf = nouveau_perf_table(dev, ver);
	64	if (perf) {
	65	if (ver >= 0x12 && ver < 0x20 && idx < perf[2]) {
	66	*hdr = perf[3];
	67	*cnt = 0;
	68	*len = 0;
	69	return perf + perf[0] + idx * perf[3];
	70	} else
	71	if (ver >= 0x20 && ver < 0x40 && idx < perf[2]) {
	72	*hdr = perf[3];
	73	*cnt = perf[4];
	74	*len = perf[5];
	75	return perf + perf[1] + idx * (hdr + (cnt * *len));
	76	} else
	77	if (ver >= 0x40 && ver < 0x41 && idx < perf[5]) {
	78	*hdr = perf[2];
	79	*cnt = perf[4];
	80	*len = perf[3];
	81	return perf + perf[1] + idx * (hdr + (cnt * *len));
	82	}
	83	}
	84	return NULL;
	85	}
	86
27740383	87	u8 *
03ddf04b BS	88	nouveau_perf_rammap(struct drm_device *dev, u32 freq,
	89	u8 ver, u8 hdr, u8 cnt, u8 len)
	90	{
77145f1c	91	struct nouveau_drm *drm = nouveau_drm(dev);
03ddf04b	92	struct bit_entry P;
fd99fd61	93	u8 *perf, i = 0;
03ddf04b BS	94
	95	if (!bit_table(dev, 'P', &P) && P.version == 2) {
	96	u8 *rammap = ROMPTR(dev, P.data[4]);
	97	if (rammap) {
	98	u8 *ramcfg = rammap + rammap[1];
	99
	100	*ver = rammap[0];
	101	*hdr = rammap[2];
	102	*cnt = rammap[4];
	103	*len = rammap[3];
	104
	105	freq /= 1000;
	106	for (i = 0; i < rammap[5]; i++) {
	107	if (freq >= ROM16(ramcfg[0]) &&
	108	freq <= ROM16(ramcfg[2]))
	109	return ramcfg;
	110
	111	ramcfg += hdr + (cnt * *len);
	112	}
	113	}
	114
	115	return NULL;
	116	}
	117
77145f1c BS	118	if (nv_device(drm->device)->chipset == 0x49 \|\|
77145f1c BS	119	nv_device(drm->device)->chipset == 0x4b)
03ddf04b BS	120	freq /= 2;
	121
	122	while ((perf = nouveau_perf_entry(dev, i++, ver, hdr, cnt, len))) {
	123	if (ver >= 0x20 && ver < 0x25) {
	124	if (perf[0] != 0xff && freq <= ROM16(perf[11]) * 1000)
	125	break;
	126	} else
	127	if (ver >= 0x25 && ver < 0x40) {
	128	if (perf[0] != 0xff && freq <= ROM16(perf[12]) * 1000)
	129	break;
	130	}
	131	}
	132
	133	if (perf) {
	134	u8 ramcfg = perf + hdr;
	135	*ver = 0x00;
	136	*hdr = 0;
	137	return ramcfg;
	138	}
	139
	140	return NULL;
	141	}
	142
a9bc247c	143	u8 *
03ddf04b BS	144	nouveau_perf_ramcfg(struct drm_device dev, u32 freq, u8 ver, u8 *len)
03ddf04b BS	145	{
77145f1c BS	146	struct nouveau_device *device = nouveau_dev(dev);
	147	struct nouveau_drm *drm = nouveau_drm(dev);
	148	struct nvbios *bios = &drm->vbios;
03ddf04b BS	149	u8 strap, hdr, cnt;
	150	u8 *rammap;
	151
77145f1c	152	strap = (nv_rd32(device, 0x101000) & 0x0000003c) >> 2;
03ddf04b BS	153	if (bios->ram_restrict_tbl_ptr)
	154	strap = bios->data[bios->ram_restrict_tbl_ptr + strap];
	155
	156	rammap = nouveau_perf_rammap(dev, freq, ver, &hdr, &cnt, len);
	157	if (rammap && strap < cnt)
	158	return rammap + hdr + (strap * *len);
	159
	160	return NULL;
	161	}
	162
fd99fd61	163	u8 *
03ddf04b BS	164	nouveau_perf_timing(struct drm_device dev, u32 freq, u8 ver, u8 *len)
03ddf04b BS	165	{
77145f1c BS	166	struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c BS	167	struct nvbios *bios = &drm->vbios;
03ddf04b BS	168	struct bit_entry P;
	169	u8 perf, timing = NULL;
	170	u8 i = 0, hdr, cnt;
	171
	172	if (bios->type == NVBIOS_BMP) {
	173	while ((perf = nouveau_perf_entry(dev, i++, ver, &hdr, &cnt,
	174	len)) && *ver == 0x15) {
	175	if (freq <= ROM32(perf[5]) * 20) {
	176	*ver = 0x00;
	177	*len = 14;
	178	return perf + 41;
	179	}
	180	}
	181	return NULL;
	182	}
	183
	184	if (!bit_table(dev, 'P', &P)) {
	185	if (P.version == 1)
	186	timing = ROMPTR(dev, P.data[4]);
	187	else
	188	if (P.version == 2)
	189	timing = ROMPTR(dev, P.data[8]);
	190	}
	191
	192	if (timing && timing[0] == 0x10) {
	193	u8 *ramcfg = nouveau_perf_ramcfg(dev, freq, ver, len);
	194	if (ramcfg && ramcfg[1] < timing[2]) {
	195	*ver = timing[0];
	196	*len = timing[3];
	197	return timing + timing[1] + (ramcfg[1] * timing[3]);
	198	}
	199	}
	200
	201	return NULL;
	202	}
	203
0fbb114a FJ	204	static void
	205	legacy_perf_init(struct drm_device *dev)
	206	{
77145f1c BS	207	struct nouveau_device *device = nouveau_dev(dev);
	208	struct nouveau_drm *drm = nouveau_drm(dev);
	209	struct nvbios *bios = &drm->vbios;
	210	struct nouveau_pm *pm = nouveau_pm(dev);
0fbb114a FJ	211	char perf, entry, *bmp = &bios->data[bios->offset];
	212	int headerlen, use_straps;
	213
	214	if (bmp[5] < 0x5 \|\| bmp[6] < 0x14) {
77145f1c	215	NV_DEBUG(drm, "BMP version too old for perf\n");
0fbb114a FJ	216	return;
	217	}
	218
f9f9f536	219	perf = ROMPTR(dev, bmp[0x73]);
0fbb114a	220	if (!perf) {
77145f1c	221	NV_DEBUG(drm, "No memclock table pointer found.\n");
0fbb114a FJ	222	return;
	223	}
	224
	225	switch (perf[0]) {
	226	case 0x12:
	227	case 0x14:
	228	case 0x18:
	229	use_straps = 0;
	230	headerlen = 1;
	231	break;
	232	case 0x01:
	233	use_straps = perf[1] & 1;
	234	headerlen = (use_straps ? 8 : 2);
	235	break;
	236	default:
77145f1c	237	NV_WARN(drm, "Unknown memclock table version %x.\n", perf[0]);
0fbb114a FJ	238	return;
	239	}
	240
	241	entry = perf + headerlen;
	242	if (use_straps)
77145f1c	243	entry += (nv_rd32(device, NV_PEXTDEV_BOOT_0) & 0x3c) >> 1;
0fbb114a FJ	244
	245	sprintf(pm->perflvl[0].name, "performance_level_0");
	246	pm->perflvl[0].memory = ROM16(entry[0]) * 20;
	247	pm->nr_perflvl = 1;
	248	}
	249
3b5565dd	250	static void
03ddf04b	251	nouveau_perf_voltage(struct drm_device dev, struct nouveau_pm_level perflvl)
3b5565dd	252	{
77145f1c	253	struct nouveau_drm *drm = nouveau_drm(dev);
03ddf04b	254	struct bit_entry P;
3b5565dd BS	255	u8 *vmap;
	256	int id;
	257
	258	id = perflvl->volt_min;
	259	perflvl->volt_min = 0;
	260
03ce8d9e BS	261	/* boards using voltage table version <0x40 store the voltage
03ce8d9e BS	262	* level directly in the perflvl entry as a multiple of 10mV
3b5565dd	263	*/
77145f1c	264	if (drm->pm->voltage.version < 0x40) {
3b5565dd BS	265	perflvl->volt_min = id * 10000;
	266	perflvl->volt_max = perflvl->volt_min;
	267	return;
	268	}
	269
03ce8d9e	270	/* on newer ones, the perflvl stores an index into yet another
3b5565dd BS	271	* vbios table containing a min/max voltage value for the perflvl
3b5565dd BS	272	*/
03ddf04b	273	if (bit_table(dev, 'P', &P) \|\| P.version != 2 \|\| P.length < 34) {
77145f1c	274	NV_DEBUG(drm, "where's our volt map table ptr? %d %d\n",
03ddf04b	275	P.version, P.length);
3b5565dd BS	276	return;
	277	}
	278
03ddf04b	279	vmap = ROMPTR(dev, P.data[32]);
3b5565dd	280	if (!vmap) {
77145f1c	281	NV_DEBUG(drm, "volt map table pointer invalid\n");
3b5565dd BS	282	return;
	283	}
	284
	285	if (id < vmap[3]) {
	286	vmap += vmap[1] + (vmap[2] * id);
	287	perflvl->volt_min = ROM32(vmap[0]);
	288	perflvl->volt_max = ROM32(vmap[4]);
	289	}
	290	}
	291
330c5988 BS	292	void
	293	nouveau_perf_init(struct drm_device *dev)
	294	{
77145f1c BS	295	struct nouveau_drm *drm = nouveau_drm(dev);
	296	struct nouveau_pm *pm = nouveau_pm(dev);
	297	struct nvbios *bios = &drm->vbios;
03ddf04b	298	u8 *perf, ver, hdr, cnt, len;
085028ce	299	int ret, vid, i = -1;
330c5988	300
03ddf04b BS	301	if (bios->type == NVBIOS_BMP && bios->data[bios->offset + 6] < 0x25) {
	302	legacy_perf_init(dev);
	303	return;
9a782488 RS	304	}
9a782488 RS	305
8b83d67c	306	perf = nouveau_perf_table(dev, &ver);
8b83d67c	307
03ddf04b	308	while ((perf = nouveau_perf_entry(dev, ++i, &ver, &hdr, &cnt, &len))) {
330c5988 BS	309	struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
330c5988 BS	310
03ddf04b	311	if (perf[0] == 0xff)
330c5988	312	continue;
330c5988	313
03ddf04b	314	switch (ver) {
330c5988 BS	315	case 0x12:
	316	case 0x13:
	317	case 0x15:
03ddf04b BS	318	perflvl->fanspeed = perf[55];
	319	if (hdr > 56)
	320	perflvl->volt_min = perf[56];
	321	perflvl->core = ROM32(perf[1]) * 10;
	322	perflvl->memory = ROM32(perf[5]) * 20;
330c5988 BS	323	break;
	324	case 0x21:
	325	case 0x23:
	326	case 0x24:
03ddf04b BS	327	perflvl->fanspeed = perf[4];
	328	perflvl->volt_min = perf[5];
	329	perflvl->shader = ROM16(perf[6]) * 1000;
9f403603	330	perflvl->core = perflvl->shader;
03ddf04b	331	perflvl->core += (signed char)perf[8] * 1000;
77145f1c BS	332	if (nv_device(drm->device)->chipset == 0x49 \|\|
77145f1c BS	333	nv_device(drm->device)->chipset == 0x4b)
03ddf04b	334	perflvl->memory = ROM16(perf[11]) * 1000;
e829d804	335	else
03ddf04b	336	perflvl->memory = ROM16(perf[11]) * 2000;
330c5988 BS	337	break;
330c5988 BS	338	case 0x25:
03ddf04b BS	339	perflvl->fanspeed = perf[4];
	340	perflvl->volt_min = perf[5];
	341	perflvl->core = ROM16(perf[6]) * 1000;
	342	perflvl->shader = ROM16(perf[10]) * 1000;
	343	perflvl->memory = ROM16(perf[12]) * 1000;
330c5988 BS	344	break;
330c5988 BS	345	case 0x30:
03ddf04b	346	perflvl->memscript = ROM16(perf[2]);
330c5988	347	case 0x35:
03ddf04b BS	348	perflvl->fanspeed = perf[6];
	349	perflvl->volt_min = perf[7];
	350	perflvl->core = ROM16(perf[8]) * 1000;
	351	perflvl->shader = ROM16(perf[10]) * 1000;
	352	perflvl->memory = ROM16(perf[12]) * 1000;
	353	perflvl->vdec = ROM16(perf[16]) * 1000;
	354	perflvl->dom6 = ROM16(perf[20]) * 1000;
330c5988 BS	355	break;
330c5988 BS	356	case 0x40:
03ddf04b	357	#define subent(n) ((ROM16(perf[hdr + (n) * len]) & 0xfff) * 1000)
330c5988	358	perflvl->fanspeed = 0; /XXX/
03ddf04b	359	perflvl->volt_min = perf[2];
77145f1c	360	if (nv_device(drm->device)->card_type == NV_50) {
9698b9a6 BS	361	perflvl->core = subent(0);
	362	perflvl->shader = subent(1);
	363	perflvl->memory = subent(2);
	364	perflvl->vdec = subent(3);
	365	perflvl->unka0 = subent(4);
40f6193b	366	} else {
9698b9a6 BS	367	perflvl->hub06 = subent(0);
	368	perflvl->hub01 = subent(1);
	369	perflvl->copy = subent(2);
	370	perflvl->shader = subent(3);
	371	perflvl->rop = subent(4);
	372	perflvl->memory = subent(5);
	373	perflvl->vdec = subent(6);
	374	perflvl->daemon = subent(10);
	375	perflvl->hub07 = subent(11);
40f6193b	376	perflvl->core = perflvl->shader / 2;
40f6193b	377	}
330c5988 BS	378	break;
	379	}
	380
330c5988	381	/* make sure vid is valid */
03ddf04b	382	nouveau_perf_voltage(dev, perflvl);
3b5565dd BS	383	if (pm->voltage.supported && perflvl->volt_min) {
3b5565dd BS	384	vid = nouveau_volt_vid_lookup(dev, perflvl->volt_min);
330c5988	385	if (vid < 0) {
77145f1c	386	NV_DEBUG(drm, "perflvl %d, bad vid\n", i);
330c5988 BS	387	continue;
	388	}
	389	}
	390
e614b2e7	391	/* get the corresponding memory timings */
085028ce BS	392	ret = nouveau_mem_timing_calc(dev, perflvl->memory,
	393	&perflvl->timing);
	394	if (ret) {
77145f1c	395	NV_DEBUG(drm, "perflvl %d, bad timing: %d\n", i, ret);
085028ce BS	396	continue;
085028ce BS	397	}
e614b2e7	398
330c5988 BS	399	snprintf(perflvl->name, sizeof(perflvl->name),
	400	"performance_level_%d", i);
	401	perflvl->id = i;
8d7bb400 BS	402
	403	snprintf(perflvl->profile.name, sizeof(perflvl->profile.name),
	404	"%d", perflvl->id);
	405	perflvl->profile.func = &nouveau_pm_static_profile_func;
	406	list_add_tail(&perflvl->profile.head, &pm->profiles);
	407
	408
330c5988	409	pm->nr_perflvl++;
330c5988 BS	410	}
	411	}
	412
	413	void
	414	nouveau_perf_fini(struct drm_device *dev)
	415	{
	416	}