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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2006 Ben Skeggs. | |
3 | * | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining | |
7 | * a copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sublicense, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial | |
16 | * portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
19 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
21 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
22 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
23 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
24 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Authors: | |
30 | * Ben Skeggs <darktama@iinet.net.au> | |
31 | */ | |
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "nouveau_drv.h" | |
36 | #include "nouveau_drm.h" | |
479dcaea | 37 | #include "nouveau_ramht.h" |
6ee73861 BS |
38 | |
39 | /* NVidia uses context objects to drive drawing operations. | |
40 | ||
41 | Context objects can be selected into 8 subchannels in the FIFO, | |
42 | and then used via DMA command buffers. | |
43 | ||
44 | A context object is referenced by a user defined handle (CARD32). The HW | |
45 | looks up graphics objects in a hash table in the instance RAM. | |
46 | ||
47 | An entry in the hash table consists of 2 CARD32. The first CARD32 contains | |
48 | the handle, the second one a bitfield, that contains the address of the | |
49 | object in instance RAM. | |
50 | ||
51 | The format of the second CARD32 seems to be: | |
52 | ||
53 | NV4 to NV30: | |
54 | ||
55 | 15: 0 instance_addr >> 4 | |
56 | 17:16 engine (here uses 1 = graphics) | |
57 | 28:24 channel id (here uses 0) | |
58 | 31 valid (use 1) | |
59 | ||
60 | NV40: | |
61 | ||
62 | 15: 0 instance_addr >> 4 (maybe 19-0) | |
63 | 21:20 engine (here uses 1 = graphics) | |
64 | I'm unsure about the other bits, but using 0 seems to work. | |
65 | ||
66 | The key into the hash table depends on the object handle and channel id and | |
67 | is given as: | |
68 | */ | |
6ee73861 BS |
69 | |
70 | int | |
71 | nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, | |
72 | uint32_t size, int align, uint32_t flags, | |
73 | struct nouveau_gpuobj **gpuobj_ret) | |
74 | { | |
75 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
76 | struct nouveau_engine *engine = &dev_priv->engine; | |
77 | struct nouveau_gpuobj *gpuobj; | |
5125bfd8 | 78 | struct drm_mm_node *ramin = NULL; |
6ee73861 BS |
79 | int ret; |
80 | ||
81 | NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n", | |
82 | chan ? chan->id : -1, size, align, flags); | |
83 | ||
84 | if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL) | |
85 | return -EINVAL; | |
86 | ||
87 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | |
88 | if (!gpuobj) | |
89 | return -ENOMEM; | |
90 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); | |
b3beb167 | 91 | gpuobj->dev = dev; |
6ee73861 | 92 | gpuobj->flags = flags; |
a8eaebc6 | 93 | gpuobj->refcount = 1; |
43efc9ce | 94 | gpuobj->size = size; |
6ee73861 BS |
95 | |
96 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); | |
97 | ||
6ee73861 | 98 | if (chan) { |
816544b2 | 99 | NV_DEBUG(dev, "channel heap\n"); |
5125bfd8 BS |
100 | |
101 | ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0); | |
102 | if (ramin) | |
103 | ramin = drm_mm_get_block(ramin, size, align); | |
104 | ||
105 | if (!ramin) { | |
106 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
107 | return -ENOMEM; | |
108 | } | |
6ee73861 BS |
109 | } else { |
110 | NV_DEBUG(dev, "global heap\n"); | |
6ee73861 | 111 | |
5125bfd8 | 112 | /* allocate backing pages, sets vinst */ |
6ee73861 BS |
113 | ret = engine->instmem.populate(dev, gpuobj, &size); |
114 | if (ret) { | |
a8eaebc6 | 115 | nouveau_gpuobj_ref(NULL, &gpuobj); |
6ee73861 BS |
116 | return ret; |
117 | } | |
6ee73861 | 118 | |
5125bfd8 BS |
119 | /* try and get aperture space */ |
120 | ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, align, 0); | |
121 | if (ramin) | |
122 | ramin = drm_mm_get_block(ramin, size, align); | |
b833ac26 | 123 | |
5125bfd8 BS |
124 | /* on nv50 it's ok to fail, we have a fallback path */ |
125 | if (!ramin && dev_priv->card_type < NV_50) { | |
126 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
127 | return -ENOMEM; | |
128 | } | |
6ee73861 BS |
129 | } |
130 | ||
5125bfd8 BS |
131 | /* if we got a chunk of the aperture, map pages into it */ |
132 | gpuobj->im_pramin = ramin; | |
fbd2895e | 133 | if (!chan && gpuobj->im_pramin && dev_priv->ramin_available) { |
6ee73861 BS |
134 | ret = engine->instmem.bind(dev, gpuobj); |
135 | if (ret) { | |
a8eaebc6 | 136 | nouveau_gpuobj_ref(NULL, &gpuobj); |
6ee73861 BS |
137 | return ret; |
138 | } | |
139 | } | |
140 | ||
de3a6c0a BS |
141 | /* calculate the various different addresses for the object */ |
142 | if (chan) { | |
5125bfd8 BS |
143 | gpuobj->pinst = chan->ramin->pinst; |
144 | if (gpuobj->pinst != ~0) | |
145 | gpuobj->pinst += gpuobj->im_pramin->start; | |
146 | ||
de3a6c0a BS |
147 | if (dev_priv->card_type < NV_50) { |
148 | gpuobj->cinst = gpuobj->pinst; | |
149 | } else { | |
150 | gpuobj->cinst = gpuobj->im_pramin->start; | |
151 | gpuobj->vinst = gpuobj->im_pramin->start + | |
43efc9ce | 152 | chan->ramin->vinst; |
de3a6c0a BS |
153 | } |
154 | } else { | |
5125bfd8 BS |
155 | if (gpuobj->im_pramin) |
156 | gpuobj->pinst = gpuobj->im_pramin->start; | |
157 | else | |
158 | gpuobj->pinst = ~0; | |
de3a6c0a | 159 | gpuobj->cinst = 0xdeadbeef; |
de3a6c0a BS |
160 | } |
161 | ||
6ee73861 BS |
162 | if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { |
163 | int i; | |
164 | ||
43efc9ce | 165 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 166 | nv_wo32(gpuobj, i, 0); |
f56cb86f | 167 | engine->instmem.flush(dev); |
6ee73861 BS |
168 | } |
169 | ||
a8eaebc6 | 170 | |
6ee73861 BS |
171 | *gpuobj_ret = gpuobj; |
172 | return 0; | |
173 | } | |
174 | ||
175 | int | |
fbd2895e | 176 | nouveau_gpuobj_init(struct drm_device *dev) |
6ee73861 BS |
177 | { |
178 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
179 | ||
180 | NV_DEBUG(dev, "\n"); | |
181 | ||
182 | INIT_LIST_HEAD(&dev_priv->gpuobj_list); | |
5125bfd8 BS |
183 | spin_lock_init(&dev_priv->ramin_lock); |
184 | dev_priv->ramin_base = ~0; | |
6ee73861 BS |
185 | |
186 | return 0; | |
187 | } | |
188 | ||
6ee73861 BS |
189 | void |
190 | nouveau_gpuobj_takedown(struct drm_device *dev) | |
191 | { | |
192 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
193 | ||
194 | NV_DEBUG(dev, "\n"); | |
6ee73861 BS |
195 | } |
196 | ||
197 | void | |
198 | nouveau_gpuobj_late_takedown(struct drm_device *dev) | |
199 | { | |
200 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
201 | struct nouveau_gpuobj *gpuobj = NULL; | |
202 | struct list_head *entry, *tmp; | |
203 | ||
204 | NV_DEBUG(dev, "\n"); | |
205 | ||
206 | list_for_each_safe(entry, tmp, &dev_priv->gpuobj_list) { | |
207 | gpuobj = list_entry(entry, struct nouveau_gpuobj, list); | |
208 | ||
209 | NV_ERROR(dev, "gpuobj %p still exists at takedown, refs=%d\n", | |
210 | gpuobj, gpuobj->refcount); | |
a8eaebc6 BS |
211 | |
212 | gpuobj->refcount = 1; | |
213 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
6ee73861 BS |
214 | } |
215 | } | |
216 | ||
a8eaebc6 BS |
217 | static int |
218 | nouveau_gpuobj_del(struct nouveau_gpuobj *gpuobj) | |
6ee73861 | 219 | { |
a8eaebc6 | 220 | struct drm_device *dev = gpuobj->dev; |
6ee73861 BS |
221 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
222 | struct nouveau_engine *engine = &dev_priv->engine; | |
6ee73861 BS |
223 | int i; |
224 | ||
a8eaebc6 | 225 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); |
6ee73861 BS |
226 | |
227 | if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) { | |
43efc9ce | 228 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 229 | nv_wo32(gpuobj, i, 0); |
f56cb86f | 230 | engine->instmem.flush(dev); |
6ee73861 BS |
231 | } |
232 | ||
233 | if (gpuobj->dtor) | |
234 | gpuobj->dtor(dev, gpuobj); | |
235 | ||
43efc9ce | 236 | if (gpuobj->im_backing) |
6ee73861 BS |
237 | engine->instmem.clear(dev, gpuobj); |
238 | ||
43efc9ce BS |
239 | if (gpuobj->im_pramin) |
240 | drm_mm_put_block(gpuobj->im_pramin); | |
6ee73861 BS |
241 | |
242 | list_del(&gpuobj->list); | |
243 | ||
6ee73861 BS |
244 | kfree(gpuobj); |
245 | return 0; | |
246 | } | |
247 | ||
a8eaebc6 BS |
248 | void |
249 | nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr) | |
6ee73861 | 250 | { |
a8eaebc6 BS |
251 | if (ref) |
252 | ref->refcount++; | |
6ee73861 | 253 | |
a8eaebc6 BS |
254 | if (*ptr && --(*ptr)->refcount == 0) |
255 | nouveau_gpuobj_del(*ptr); | |
6ee73861 | 256 | |
a8eaebc6 | 257 | *ptr = ref; |
6ee73861 BS |
258 | } |
259 | ||
260 | int | |
43efc9ce BS |
261 | nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst, |
262 | u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj) | |
6ee73861 BS |
263 | { |
264 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
265 | struct nouveau_gpuobj *gpuobj = NULL; | |
266 | int i; | |
267 | ||
268 | NV_DEBUG(dev, | |
43efc9ce BS |
269 | "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n", |
270 | pinst, vinst, size, flags); | |
6ee73861 BS |
271 | |
272 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | |
273 | if (!gpuobj) | |
274 | return -ENOMEM; | |
275 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); | |
b3beb167 | 276 | gpuobj->dev = dev; |
43efc9ce | 277 | gpuobj->flags = flags; |
a8eaebc6 | 278 | gpuobj->refcount = 1; |
43efc9ce BS |
279 | gpuobj->size = size; |
280 | gpuobj->pinst = pinst; | |
de3a6c0a | 281 | gpuobj->cinst = 0xdeadbeef; |
43efc9ce | 282 | gpuobj->vinst = vinst; |
de3a6c0a | 283 | |
6ee73861 | 284 | if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { |
43efc9ce | 285 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 286 | nv_wo32(gpuobj, i, 0); |
f56cb86f | 287 | dev_priv->engine.instmem.flush(dev); |
6ee73861 BS |
288 | } |
289 | ||
43efc9ce BS |
290 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); |
291 | *pgpuobj = gpuobj; | |
6ee73861 BS |
292 | return 0; |
293 | } | |
294 | ||
295 | ||
296 | static uint32_t | |
297 | nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class) | |
298 | { | |
299 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
300 | ||
301 | /*XXX: dodgy hack for now */ | |
302 | if (dev_priv->card_type >= NV_50) | |
303 | return 24; | |
304 | if (dev_priv->card_type >= NV_40) | |
305 | return 32; | |
306 | return 16; | |
307 | } | |
308 | ||
309 | /* | |
310 | DMA objects are used to reference a piece of memory in the | |
311 | framebuffer, PCI or AGP address space. Each object is 16 bytes big | |
312 | and looks as follows: | |
313 | ||
314 | entry[0] | |
315 | 11:0 class (seems like I can always use 0 here) | |
316 | 12 page table present? | |
317 | 13 page entry linear? | |
318 | 15:14 access: 0 rw, 1 ro, 2 wo | |
319 | 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP | |
320 | 31:20 dma adjust (bits 0-11 of the address) | |
321 | entry[1] | |
322 | dma limit (size of transfer) | |
323 | entry[X] | |
324 | 1 0 readonly, 1 readwrite | |
325 | 31:12 dma frame address of the page (bits 12-31 of the address) | |
326 | entry[N] | |
327 | page table terminator, same value as the first pte, as does nvidia | |
328 | rivatv uses 0xffffffff | |
329 | ||
330 | Non linear page tables need a list of frame addresses afterwards, | |
331 | the rivatv project has some info on this. | |
332 | ||
333 | The method below creates a DMA object in instance RAM and returns a handle | |
334 | to it that can be used to set up context objects. | |
335 | */ | |
336 | int | |
337 | nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, | |
338 | uint64_t offset, uint64_t size, int access, | |
339 | int target, struct nouveau_gpuobj **gpuobj) | |
340 | { | |
341 | struct drm_device *dev = chan->dev; | |
342 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
343 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | |
344 | int ret; | |
345 | ||
346 | NV_DEBUG(dev, "ch%d class=0x%04x offset=0x%llx size=0x%llx\n", | |
347 | chan->id, class, offset, size); | |
348 | NV_DEBUG(dev, "access=%d target=%d\n", access, target); | |
349 | ||
350 | switch (target) { | |
351 | case NV_DMA_TARGET_AGP: | |
352 | offset += dev_priv->gart_info.aper_base; | |
353 | break; | |
354 | default: | |
355 | break; | |
356 | } | |
357 | ||
358 | ret = nouveau_gpuobj_new(dev, chan, | |
359 | nouveau_gpuobj_class_instmem_size(dev, class), | |
360 | 16, NVOBJ_FLAG_ZERO_ALLOC | | |
361 | NVOBJ_FLAG_ZERO_FREE, gpuobj); | |
362 | if (ret) { | |
363 | NV_ERROR(dev, "Error creating gpuobj: %d\n", ret); | |
364 | return ret; | |
365 | } | |
366 | ||
6ee73861 BS |
367 | if (dev_priv->card_type < NV_50) { |
368 | uint32_t frame, adjust, pte_flags = 0; | |
369 | ||
370 | if (access != NV_DMA_ACCESS_RO) | |
371 | pte_flags |= (1<<1); | |
372 | adjust = offset & 0x00000fff; | |
373 | frame = offset & ~0x00000fff; | |
374 | ||
b3beb167 BS |
375 | nv_wo32(*gpuobj, 0, ((1<<12) | (1<<13) | (adjust << 20) | |
376 | (access << 14) | (target << 16) | | |
377 | class)); | |
378 | nv_wo32(*gpuobj, 4, size - 1); | |
379 | nv_wo32(*gpuobj, 8, frame | pte_flags); | |
380 | nv_wo32(*gpuobj, 12, frame | pte_flags); | |
6ee73861 BS |
381 | } else { |
382 | uint64_t limit = offset + size - 1; | |
383 | uint32_t flags0, flags5; | |
384 | ||
385 | if (target == NV_DMA_TARGET_VIDMEM) { | |
386 | flags0 = 0x00190000; | |
387 | flags5 = 0x00010000; | |
388 | } else { | |
389 | flags0 = 0x7fc00000; | |
390 | flags5 = 0x00080000; | |
391 | } | |
392 | ||
b3beb167 BS |
393 | nv_wo32(*gpuobj, 0, flags0 | class); |
394 | nv_wo32(*gpuobj, 4, lower_32_bits(limit)); | |
395 | nv_wo32(*gpuobj, 8, lower_32_bits(offset)); | |
396 | nv_wo32(*gpuobj, 12, ((upper_32_bits(limit) & 0xff) << 24) | | |
397 | (upper_32_bits(offset) & 0xff)); | |
398 | nv_wo32(*gpuobj, 20, flags5); | |
6ee73861 BS |
399 | } |
400 | ||
f56cb86f | 401 | instmem->flush(dev); |
6ee73861 BS |
402 | |
403 | (*gpuobj)->engine = NVOBJ_ENGINE_SW; | |
404 | (*gpuobj)->class = class; | |
405 | return 0; | |
406 | } | |
407 | ||
408 | int | |
409 | nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan, | |
410 | uint64_t offset, uint64_t size, int access, | |
411 | struct nouveau_gpuobj **gpuobj, | |
412 | uint32_t *o_ret) | |
413 | { | |
414 | struct drm_device *dev = chan->dev; | |
415 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
416 | int ret; | |
417 | ||
418 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP || | |
419 | (dev_priv->card_type >= NV_50 && | |
420 | dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) { | |
421 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
422 | offset + dev_priv->vm_gart_base, | |
423 | size, access, NV_DMA_TARGET_AGP, | |
424 | gpuobj); | |
425 | if (o_ret) | |
426 | *o_ret = 0; | |
427 | } else | |
428 | if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) { | |
a8eaebc6 | 429 | nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, gpuobj); |
6ee73861 BS |
430 | if (offset & ~0xffffffffULL) { |
431 | NV_ERROR(dev, "obj offset exceeds 32-bits\n"); | |
432 | return -EINVAL; | |
433 | } | |
434 | if (o_ret) | |
435 | *o_ret = (uint32_t)offset; | |
436 | ret = (*gpuobj != NULL) ? 0 : -EINVAL; | |
437 | } else { | |
438 | NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type); | |
439 | return -EINVAL; | |
440 | } | |
441 | ||
442 | return ret; | |
443 | } | |
444 | ||
445 | /* Context objects in the instance RAM have the following structure. | |
446 | * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes. | |
447 | ||
448 | NV4 - NV30: | |
449 | ||
450 | entry[0] | |
451 | 11:0 class | |
452 | 12 chroma key enable | |
453 | 13 user clip enable | |
454 | 14 swizzle enable | |
455 | 17:15 patch config: | |
456 | scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre | |
457 | 18 synchronize enable | |
458 | 19 endian: 1 big, 0 little | |
459 | 21:20 dither mode | |
460 | 23 single step enable | |
461 | 24 patch status: 0 invalid, 1 valid | |
462 | 25 context_surface 0: 1 valid | |
463 | 26 context surface 1: 1 valid | |
464 | 27 context pattern: 1 valid | |
465 | 28 context rop: 1 valid | |
466 | 29,30 context beta, beta4 | |
467 | entry[1] | |
468 | 7:0 mono format | |
469 | 15:8 color format | |
470 | 31:16 notify instance address | |
471 | entry[2] | |
472 | 15:0 dma 0 instance address | |
473 | 31:16 dma 1 instance address | |
474 | entry[3] | |
475 | dma method traps | |
476 | ||
477 | NV40: | |
478 | No idea what the exact format is. Here's what can be deducted: | |
479 | ||
480 | entry[0]: | |
481 | 11:0 class (maybe uses more bits here?) | |
482 | 17 user clip enable | |
483 | 21:19 patch config | |
484 | 25 patch status valid ? | |
485 | entry[1]: | |
486 | 15:0 DMA notifier (maybe 20:0) | |
487 | entry[2]: | |
488 | 15:0 DMA 0 instance (maybe 20:0) | |
489 | 24 big endian | |
490 | entry[3]: | |
491 | 15:0 DMA 1 instance (maybe 20:0) | |
492 | entry[4]: | |
493 | entry[5]: | |
494 | set to 0? | |
495 | */ | |
496 | int | |
497 | nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, | |
498 | struct nouveau_gpuobj **gpuobj) | |
499 | { | |
500 | struct drm_device *dev = chan->dev; | |
501 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
502 | int ret; | |
503 | ||
504 | NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class); | |
505 | ||
506 | ret = nouveau_gpuobj_new(dev, chan, | |
507 | nouveau_gpuobj_class_instmem_size(dev, class), | |
508 | 16, | |
509 | NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, | |
510 | gpuobj); | |
511 | if (ret) { | |
512 | NV_ERROR(dev, "Error creating gpuobj: %d\n", ret); | |
513 | return ret; | |
514 | } | |
515 | ||
6ee73861 | 516 | if (dev_priv->card_type >= NV_50) { |
b3beb167 BS |
517 | nv_wo32(*gpuobj, 0, class); |
518 | nv_wo32(*gpuobj, 20, 0x00010000); | |
6ee73861 BS |
519 | } else { |
520 | switch (class) { | |
521 | case NV_CLASS_NULL: | |
b3beb167 BS |
522 | nv_wo32(*gpuobj, 0, 0x00001030); |
523 | nv_wo32(*gpuobj, 4, 0xFFFFFFFF); | |
6ee73861 BS |
524 | break; |
525 | default: | |
526 | if (dev_priv->card_type >= NV_40) { | |
b3beb167 | 527 | nv_wo32(*gpuobj, 0, class); |
6ee73861 | 528 | #ifdef __BIG_ENDIAN |
b3beb167 | 529 | nv_wo32(*gpuobj, 8, 0x01000000); |
6ee73861 BS |
530 | #endif |
531 | } else { | |
532 | #ifdef __BIG_ENDIAN | |
b3beb167 | 533 | nv_wo32(*gpuobj, 0, class | 0x00080000); |
6ee73861 | 534 | #else |
b3beb167 | 535 | nv_wo32(*gpuobj, 0, class); |
6ee73861 BS |
536 | #endif |
537 | } | |
538 | } | |
539 | } | |
f56cb86f | 540 | dev_priv->engine.instmem.flush(dev); |
6ee73861 BS |
541 | |
542 | (*gpuobj)->engine = NVOBJ_ENGINE_GR; | |
543 | (*gpuobj)->class = class; | |
544 | return 0; | |
545 | } | |
546 | ||
f03a314b | 547 | int |
6ee73861 BS |
548 | nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class, |
549 | struct nouveau_gpuobj **gpuobj_ret) | |
550 | { | |
dd19e44b | 551 | struct drm_nouveau_private *dev_priv; |
6ee73861 BS |
552 | struct nouveau_gpuobj *gpuobj; |
553 | ||
554 | if (!chan || !gpuobj_ret || *gpuobj_ret != NULL) | |
555 | return -EINVAL; | |
dd19e44b | 556 | dev_priv = chan->dev->dev_private; |
6ee73861 BS |
557 | |
558 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | |
559 | if (!gpuobj) | |
560 | return -ENOMEM; | |
a8eaebc6 | 561 | gpuobj->dev = chan->dev; |
6ee73861 BS |
562 | gpuobj->engine = NVOBJ_ENGINE_SW; |
563 | gpuobj->class = class; | |
a8eaebc6 BS |
564 | gpuobj->refcount = 1; |
565 | gpuobj->cinst = 0x40; | |
6ee73861 BS |
566 | |
567 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); | |
568 | *gpuobj_ret = gpuobj; | |
569 | return 0; | |
570 | } | |
571 | ||
572 | static int | |
573 | nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | |
574 | { | |
575 | struct drm_device *dev = chan->dev; | |
576 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
6ee73861 BS |
577 | uint32_t size; |
578 | uint32_t base; | |
579 | int ret; | |
580 | ||
581 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
582 | ||
583 | /* Base amount for object storage (4KiB enough?) */ | |
584 | size = 0x1000; | |
585 | base = 0; | |
586 | ||
587 | /* PGRAPH context */ | |
816544b2 | 588 | size += dev_priv->engine.graph.grctx_size; |
6ee73861 BS |
589 | |
590 | if (dev_priv->card_type == NV_50) { | |
591 | /* Various fixed table thingos */ | |
592 | size += 0x1400; /* mostly unknown stuff */ | |
593 | size += 0x4000; /* vm pd */ | |
594 | base = 0x6000; | |
595 | /* RAMHT, not sure about setting size yet, 32KiB to be safe */ | |
596 | size += 0x8000; | |
597 | /* RAMFC */ | |
598 | size += 0x1000; | |
6ee73861 BS |
599 | } |
600 | ||
a8eaebc6 | 601 | ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin); |
6ee73861 BS |
602 | if (ret) { |
603 | NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret); | |
604 | return ret; | |
605 | } | |
6ee73861 | 606 | |
de3a6c0a | 607 | ret = drm_mm_init(&chan->ramin_heap, base, size); |
6ee73861 BS |
608 | if (ret) { |
609 | NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret); | |
a8eaebc6 | 610 | nouveau_gpuobj_ref(NULL, &chan->ramin); |
6ee73861 BS |
611 | return ret; |
612 | } | |
613 | ||
614 | return 0; | |
615 | } | |
616 | ||
617 | int | |
618 | nouveau_gpuobj_channel_init(struct nouveau_channel *chan, | |
619 | uint32_t vram_h, uint32_t tt_h) | |
620 | { | |
621 | struct drm_device *dev = chan->dev; | |
622 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
623 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | |
624 | struct nouveau_gpuobj *vram = NULL, *tt = NULL; | |
625 | int ret, i; | |
626 | ||
6ee73861 BS |
627 | NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); |
628 | ||
816544b2 BS |
629 | /* Allocate a chunk of memory for per-channel object storage */ |
630 | ret = nouveau_gpuobj_channel_init_pramin(chan); | |
631 | if (ret) { | |
632 | NV_ERROR(dev, "init pramin\n"); | |
633 | return ret; | |
6ee73861 BS |
634 | } |
635 | ||
636 | /* NV50 VM | |
637 | * - Allocate per-channel page-directory | |
638 | * - Map GART and VRAM into the channel's address space at the | |
639 | * locations determined during init. | |
640 | */ | |
641 | if (dev_priv->card_type >= NV_50) { | |
5125bfd8 BS |
642 | u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200; |
643 | u64 vm_vinst = chan->ramin->vinst + pgd_offs; | |
644 | u32 vm_pinst = chan->ramin->pinst; | |
645 | u32 pde; | |
6ee73861 | 646 | |
5125bfd8 BS |
647 | if (vm_pinst != ~0) |
648 | vm_pinst += pgd_offs; | |
6ee73861 | 649 | |
5125bfd8 | 650 | ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000, |
a8eaebc6 | 651 | 0, &chan->vm_pd); |
f56cb86f | 652 | if (ret) |
6ee73861 | 653 | return ret; |
6ee73861 | 654 | for (i = 0; i < 0x4000; i += 8) { |
b3beb167 BS |
655 | nv_wo32(chan->vm_pd, i + 0, 0x00000000); |
656 | nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe); | |
6ee73861 BS |
657 | } |
658 | ||
a8eaebc6 BS |
659 | nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, |
660 | &chan->vm_gart_pt); | |
b3beb167 | 661 | pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 8; |
a8eaebc6 | 662 | nv_wo32(chan->vm_pd, pde + 0, chan->vm_gart_pt->vinst | 3); |
b3beb167 | 663 | nv_wo32(chan->vm_pd, pde + 4, 0x00000000); |
6ee73861 | 664 | |
b3beb167 | 665 | pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 8; |
6ee73861 | 666 | for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) { |
a8eaebc6 BS |
667 | nouveau_gpuobj_ref(dev_priv->vm_vram_pt[i], |
668 | &chan->vm_vram_pt[i]); | |
6ee73861 | 669 | |
b3beb167 | 670 | nv_wo32(chan->vm_pd, pde + 0, |
a8eaebc6 | 671 | chan->vm_vram_pt[i]->vinst | 0x61); |
b3beb167 BS |
672 | nv_wo32(chan->vm_pd, pde + 4, 0x00000000); |
673 | pde += 8; | |
6ee73861 BS |
674 | } |
675 | ||
f56cb86f | 676 | instmem->flush(dev); |
6ee73861 BS |
677 | } |
678 | ||
679 | /* RAMHT */ | |
680 | if (dev_priv->card_type < NV_50) { | |
a8eaebc6 BS |
681 | nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL); |
682 | } else { | |
683 | struct nouveau_gpuobj *ramht = NULL; | |
684 | ||
685 | ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16, | |
686 | NVOBJ_FLAG_ZERO_ALLOC, &ramht); | |
6ee73861 BS |
687 | if (ret) |
688 | return ret; | |
a8eaebc6 BS |
689 | |
690 | ret = nouveau_ramht_new(dev, ramht, &chan->ramht); | |
691 | nouveau_gpuobj_ref(NULL, &ramht); | |
6ee73861 BS |
692 | if (ret) |
693 | return ret; | |
694 | } | |
695 | ||
696 | /* VRAM ctxdma */ | |
697 | if (dev_priv->card_type >= NV_50) { | |
698 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
699 | 0, dev_priv->vm_end, | |
700 | NV_DMA_ACCESS_RW, | |
701 | NV_DMA_TARGET_AGP, &vram); | |
702 | if (ret) { | |
703 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
704 | return ret; | |
705 | } | |
706 | } else { | |
707 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
a8eaebc6 BS |
708 | 0, dev_priv->fb_available_size, |
709 | NV_DMA_ACCESS_RW, | |
710 | NV_DMA_TARGET_VIDMEM, &vram); | |
6ee73861 BS |
711 | if (ret) { |
712 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
713 | return ret; | |
714 | } | |
715 | } | |
716 | ||
a8eaebc6 BS |
717 | ret = nouveau_ramht_insert(chan, vram_h, vram); |
718 | nouveau_gpuobj_ref(NULL, &vram); | |
6ee73861 | 719 | if (ret) { |
a8eaebc6 | 720 | NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret); |
6ee73861 BS |
721 | return ret; |
722 | } | |
723 | ||
724 | /* TT memory ctxdma */ | |
725 | if (dev_priv->card_type >= NV_50) { | |
a8eaebc6 BS |
726 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, |
727 | 0, dev_priv->vm_end, | |
728 | NV_DMA_ACCESS_RW, | |
729 | NV_DMA_TARGET_AGP, &tt); | |
730 | if (ret) { | |
731 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
732 | return ret; | |
733 | } | |
6ee73861 BS |
734 | } else |
735 | if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) { | |
736 | ret = nouveau_gpuobj_gart_dma_new(chan, 0, | |
737 | dev_priv->gart_info.aper_size, | |
738 | NV_DMA_ACCESS_RW, &tt, NULL); | |
739 | } else { | |
740 | NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type); | |
741 | ret = -EINVAL; | |
742 | } | |
743 | ||
744 | if (ret) { | |
745 | NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret); | |
746 | return ret; | |
747 | } | |
748 | ||
a8eaebc6 BS |
749 | ret = nouveau_ramht_insert(chan, tt_h, tt); |
750 | nouveau_gpuobj_ref(NULL, &tt); | |
6ee73861 | 751 | if (ret) { |
a8eaebc6 | 752 | NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret); |
6ee73861 BS |
753 | return ret; |
754 | } | |
755 | ||
756 | return 0; | |
757 | } | |
758 | ||
759 | void | |
760 | nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) | |
761 | { | |
762 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
763 | struct drm_device *dev = chan->dev; | |
6ee73861 BS |
764 | int i; |
765 | ||
766 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
767 | ||
a8eaebc6 | 768 | if (!chan->ramht) |
6ee73861 BS |
769 | return; |
770 | ||
a8eaebc6 | 771 | nouveau_ramht_ref(NULL, &chan->ramht, chan); |
6ee73861 | 772 | |
a8eaebc6 BS |
773 | nouveau_gpuobj_ref(NULL, &chan->vm_pd); |
774 | nouveau_gpuobj_ref(NULL, &chan->vm_gart_pt); | |
6ee73861 | 775 | for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) |
a8eaebc6 | 776 | nouveau_gpuobj_ref(NULL, &chan->vm_vram_pt[i]); |
6ee73861 | 777 | |
b833ac26 BS |
778 | if (chan->ramin_heap.free_stack.next) |
779 | drm_mm_takedown(&chan->ramin_heap); | |
a8eaebc6 | 780 | nouveau_gpuobj_ref(NULL, &chan->ramin); |
6ee73861 BS |
781 | } |
782 | ||
783 | int | |
784 | nouveau_gpuobj_suspend(struct drm_device *dev) | |
785 | { | |
786 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
787 | struct nouveau_gpuobj *gpuobj; | |
788 | int i; | |
789 | ||
790 | if (dev_priv->card_type < NV_50) { | |
791 | dev_priv->susres.ramin_copy = vmalloc(dev_priv->ramin_rsvd_vram); | |
792 | if (!dev_priv->susres.ramin_copy) | |
793 | return -ENOMEM; | |
794 | ||
795 | for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4) | |
796 | dev_priv->susres.ramin_copy[i/4] = nv_ri32(dev, i); | |
797 | return 0; | |
798 | } | |
799 | ||
800 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { | |
43efc9ce | 801 | if (!gpuobj->im_backing) |
6ee73861 BS |
802 | continue; |
803 | ||
43efc9ce | 804 | gpuobj->im_backing_suspend = vmalloc(gpuobj->size); |
6ee73861 BS |
805 | if (!gpuobj->im_backing_suspend) { |
806 | nouveau_gpuobj_resume(dev); | |
807 | return -ENOMEM; | |
808 | } | |
809 | ||
43efc9ce | 810 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 811 | gpuobj->im_backing_suspend[i/4] = nv_ro32(gpuobj, i); |
6ee73861 BS |
812 | } |
813 | ||
814 | return 0; | |
815 | } | |
816 | ||
817 | void | |
818 | nouveau_gpuobj_suspend_cleanup(struct drm_device *dev) | |
819 | { | |
820 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
821 | struct nouveau_gpuobj *gpuobj; | |
822 | ||
823 | if (dev_priv->card_type < NV_50) { | |
824 | vfree(dev_priv->susres.ramin_copy); | |
825 | dev_priv->susres.ramin_copy = NULL; | |
826 | return; | |
827 | } | |
828 | ||
829 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { | |
830 | if (!gpuobj->im_backing_suspend) | |
831 | continue; | |
832 | ||
833 | vfree(gpuobj->im_backing_suspend); | |
834 | gpuobj->im_backing_suspend = NULL; | |
835 | } | |
836 | } | |
837 | ||
838 | void | |
839 | nouveau_gpuobj_resume(struct drm_device *dev) | |
840 | { | |
841 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
842 | struct nouveau_gpuobj *gpuobj; | |
843 | int i; | |
844 | ||
845 | if (dev_priv->card_type < NV_50) { | |
846 | for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4) | |
847 | nv_wi32(dev, i, dev_priv->susres.ramin_copy[i/4]); | |
848 | nouveau_gpuobj_suspend_cleanup(dev); | |
849 | return; | |
850 | } | |
851 | ||
852 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { | |
853 | if (!gpuobj->im_backing_suspend) | |
854 | continue; | |
855 | ||
43efc9ce | 856 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 857 | nv_wo32(gpuobj, i, gpuobj->im_backing_suspend[i/4]); |
f56cb86f | 858 | dev_priv->engine.instmem.flush(dev); |
6ee73861 BS |
859 | } |
860 | ||
861 | nouveau_gpuobj_suspend_cleanup(dev); | |
862 | } | |
863 | ||
864 | int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, | |
865 | struct drm_file *file_priv) | |
866 | { | |
867 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
868 | struct drm_nouveau_grobj_alloc *init = data; | |
869 | struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph; | |
870 | struct nouveau_pgraph_object_class *grc; | |
871 | struct nouveau_gpuobj *gr = NULL; | |
872 | struct nouveau_channel *chan; | |
873 | int ret; | |
874 | ||
6ee73861 BS |
875 | NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(init->channel, file_priv, chan); |
876 | ||
877 | if (init->handle == ~0) | |
878 | return -EINVAL; | |
879 | ||
880 | grc = pgraph->grclass; | |
881 | while (grc->id) { | |
882 | if (grc->id == init->class) | |
883 | break; | |
884 | grc++; | |
885 | } | |
886 | ||
887 | if (!grc->id) { | |
888 | NV_ERROR(dev, "Illegal object class: 0x%x\n", init->class); | |
889 | return -EPERM; | |
890 | } | |
891 | ||
a8eaebc6 | 892 | if (nouveau_ramht_find(chan, init->handle)) |
6ee73861 BS |
893 | return -EEXIST; |
894 | ||
895 | if (!grc->software) | |
896 | ret = nouveau_gpuobj_gr_new(chan, grc->id, &gr); | |
897 | else | |
898 | ret = nouveau_gpuobj_sw_new(chan, grc->id, &gr); | |
6ee73861 BS |
899 | if (ret) { |
900 | NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n", | |
901 | ret, init->channel, init->handle); | |
902 | return ret; | |
903 | } | |
904 | ||
a8eaebc6 BS |
905 | ret = nouveau_ramht_insert(chan, init->handle, gr); |
906 | nouveau_gpuobj_ref(NULL, &gr); | |
6ee73861 BS |
907 | if (ret) { |
908 | NV_ERROR(dev, "Error referencing object: %d (%d/0x%08x)\n", | |
909 | ret, init->channel, init->handle); | |
6ee73861 BS |
910 | return ret; |
911 | } | |
912 | ||
913 | return 0; | |
914 | } | |
915 | ||
916 | int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data, | |
917 | struct drm_file *file_priv) | |
918 | { | |
919 | struct drm_nouveau_gpuobj_free *objfree = data; | |
a8eaebc6 | 920 | struct nouveau_gpuobj *gpuobj; |
6ee73861 | 921 | struct nouveau_channel *chan; |
6ee73861 | 922 | |
6ee73861 BS |
923 | NOUVEAU_GET_USER_CHANNEL_WITH_RETURN(objfree->channel, file_priv, chan); |
924 | ||
a8eaebc6 BS |
925 | gpuobj = nouveau_ramht_find(chan, objfree->handle); |
926 | if (!gpuobj) | |
927 | return -ENOENT; | |
6ee73861 | 928 | |
a8eaebc6 | 929 | nouveau_ramht_remove(chan, objfree->handle); |
6ee73861 BS |
930 | return 0; |
931 | } | |
b3beb167 BS |
932 | |
933 | u32 | |
934 | nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset) | |
935 | { | |
5125bfd8 BS |
936 | struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; |
937 | struct drm_device *dev = gpuobj->dev; | |
938 | ||
939 | if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { | |
940 | u64 ptr = gpuobj->vinst + offset; | |
941 | u32 base = ptr >> 16; | |
942 | u32 val; | |
943 | ||
944 | spin_lock(&dev_priv->ramin_lock); | |
945 | if (dev_priv->ramin_base != base) { | |
946 | dev_priv->ramin_base = base; | |
947 | nv_wr32(dev, 0x001700, dev_priv->ramin_base); | |
948 | } | |
949 | val = nv_rd32(dev, 0x700000 + (ptr & 0xffff)); | |
950 | spin_unlock(&dev_priv->ramin_lock); | |
951 | return val; | |
952 | } | |
953 | ||
954 | return nv_ri32(dev, gpuobj->pinst + offset); | |
b3beb167 BS |
955 | } |
956 | ||
957 | void | |
958 | nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val) | |
959 | { | |
5125bfd8 BS |
960 | struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; |
961 | struct drm_device *dev = gpuobj->dev; | |
962 | ||
963 | if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { | |
964 | u64 ptr = gpuobj->vinst + offset; | |
965 | u32 base = ptr >> 16; | |
966 | ||
967 | spin_lock(&dev_priv->ramin_lock); | |
968 | if (dev_priv->ramin_base != base) { | |
969 | dev_priv->ramin_base = base; | |
970 | nv_wr32(dev, 0x001700, dev_priv->ramin_base); | |
971 | } | |
972 | nv_wr32(dev, 0x700000 + (ptr & 0xffff), val); | |
973 | spin_unlock(&dev_priv->ramin_lock); | |
974 | return; | |
975 | } | |
976 | ||
977 | nv_wi32(dev, gpuobj->pinst + offset, val); | |
b3beb167 | 978 | } |