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6ee73861 BS |
1 | /* |
2 | * Copyright (C) 2006 Ben Skeggs. | |
3 | * | |
4 | * All Rights Reserved. | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining | |
7 | * a copy of this software and associated documentation files (the | |
8 | * "Software"), to deal in the Software without restriction, including | |
9 | * without limitation the rights to use, copy, modify, merge, publish, | |
10 | * distribute, sublicense, and/or sell copies of the Software, and to | |
11 | * permit persons to whom the Software is furnished to do so, subject to | |
12 | * the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice (including the | |
15 | * next paragraph) shall be included in all copies or substantial | |
16 | * portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
19 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. | |
21 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE | |
22 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION | |
23 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION | |
24 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | */ | |
27 | ||
28 | /* | |
29 | * Authors: | |
30 | * Ben Skeggs <darktama@iinet.net.au> | |
31 | */ | |
32 | ||
33 | #include "drmP.h" | |
34 | #include "drm.h" | |
35 | #include "nouveau_drv.h" | |
36 | #include "nouveau_drm.h" | |
479dcaea | 37 | #include "nouveau_ramht.h" |
6ee73861 | 38 | |
b8c157d3 BS |
39 | struct nouveau_gpuobj_method { |
40 | struct list_head head; | |
41 | u32 mthd; | |
42 | int (*exec)(struct nouveau_channel *, u32 class, u32 mthd, u32 data); | |
43 | }; | |
44 | ||
45 | struct nouveau_gpuobj_class { | |
46 | struct list_head head; | |
47 | struct list_head methods; | |
48 | u32 id; | |
49 | u32 engine; | |
50 | }; | |
51 | ||
52 | int | |
53 | nouveau_gpuobj_class_new(struct drm_device *dev, u32 class, u32 engine) | |
54 | { | |
55 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
56 | struct nouveau_gpuobj_class *oc; | |
57 | ||
58 | oc = kzalloc(sizeof(*oc), GFP_KERNEL); | |
59 | if (!oc) | |
60 | return -ENOMEM; | |
61 | ||
62 | INIT_LIST_HEAD(&oc->methods); | |
63 | oc->id = class; | |
64 | oc->engine = engine; | |
65 | list_add(&oc->head, &dev_priv->classes); | |
66 | return 0; | |
67 | } | |
68 | ||
69 | int | |
70 | nouveau_gpuobj_mthd_new(struct drm_device *dev, u32 class, u32 mthd, | |
71 | int (*exec)(struct nouveau_channel *, u32, u32, u32)) | |
72 | { | |
73 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
74 | struct nouveau_gpuobj_method *om; | |
75 | struct nouveau_gpuobj_class *oc; | |
76 | ||
77 | list_for_each_entry(oc, &dev_priv->classes, head) { | |
78 | if (oc->id == class) | |
79 | goto found; | |
80 | } | |
81 | ||
82 | return -EINVAL; | |
83 | ||
84 | found: | |
85 | om = kzalloc(sizeof(*om), GFP_KERNEL); | |
86 | if (!om) | |
87 | return -ENOMEM; | |
88 | ||
89 | om->mthd = mthd; | |
90 | om->exec = exec; | |
91 | list_add(&om->head, &oc->methods); | |
92 | return 0; | |
93 | } | |
94 | ||
95 | int | |
96 | nouveau_gpuobj_mthd_call(struct nouveau_channel *chan, | |
97 | u32 class, u32 mthd, u32 data) | |
98 | { | |
99 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
100 | struct nouveau_gpuobj_method *om; | |
101 | struct nouveau_gpuobj_class *oc; | |
102 | ||
103 | list_for_each_entry(oc, &dev_priv->classes, head) { | |
104 | if (oc->id != class) | |
105 | continue; | |
106 | ||
107 | list_for_each_entry(om, &oc->methods, head) { | |
108 | if (om->mthd == mthd) | |
109 | return om->exec(chan, class, mthd, data); | |
110 | } | |
111 | } | |
112 | ||
113 | return -ENOENT; | |
114 | } | |
115 | ||
6ee73861 BS |
116 | /* NVidia uses context objects to drive drawing operations. |
117 | ||
118 | Context objects can be selected into 8 subchannels in the FIFO, | |
119 | and then used via DMA command buffers. | |
120 | ||
121 | A context object is referenced by a user defined handle (CARD32). The HW | |
122 | looks up graphics objects in a hash table in the instance RAM. | |
123 | ||
124 | An entry in the hash table consists of 2 CARD32. The first CARD32 contains | |
125 | the handle, the second one a bitfield, that contains the address of the | |
126 | object in instance RAM. | |
127 | ||
128 | The format of the second CARD32 seems to be: | |
129 | ||
130 | NV4 to NV30: | |
131 | ||
132 | 15: 0 instance_addr >> 4 | |
133 | 17:16 engine (here uses 1 = graphics) | |
134 | 28:24 channel id (here uses 0) | |
135 | 31 valid (use 1) | |
136 | ||
137 | NV40: | |
138 | ||
139 | 15: 0 instance_addr >> 4 (maybe 19-0) | |
140 | 21:20 engine (here uses 1 = graphics) | |
141 | I'm unsure about the other bits, but using 0 seems to work. | |
142 | ||
143 | The key into the hash table depends on the object handle and channel id and | |
144 | is given as: | |
145 | */ | |
6ee73861 BS |
146 | |
147 | int | |
148 | nouveau_gpuobj_new(struct drm_device *dev, struct nouveau_channel *chan, | |
149 | uint32_t size, int align, uint32_t flags, | |
150 | struct nouveau_gpuobj **gpuobj_ret) | |
151 | { | |
152 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
153 | struct nouveau_engine *engine = &dev_priv->engine; | |
154 | struct nouveau_gpuobj *gpuobj; | |
5125bfd8 | 155 | struct drm_mm_node *ramin = NULL; |
6ee73861 BS |
156 | int ret; |
157 | ||
158 | NV_DEBUG(dev, "ch%d size=%u align=%d flags=0x%08x\n", | |
159 | chan ? chan->id : -1, size, align, flags); | |
160 | ||
161 | if (!dev_priv || !gpuobj_ret || *gpuobj_ret != NULL) | |
162 | return -EINVAL; | |
163 | ||
164 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | |
165 | if (!gpuobj) | |
166 | return -ENOMEM; | |
167 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); | |
b3beb167 | 168 | gpuobj->dev = dev; |
6ee73861 | 169 | gpuobj->flags = flags; |
eb9bcbdc | 170 | kref_init(&gpuobj->refcount); |
43efc9ce | 171 | gpuobj->size = size; |
6ee73861 | 172 | |
e05d7eae | 173 | spin_lock(&dev_priv->ramin_lock); |
6ee73861 | 174 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); |
e05d7eae | 175 | spin_unlock(&dev_priv->ramin_lock); |
6ee73861 | 176 | |
6ee73861 | 177 | if (chan) { |
816544b2 | 178 | NV_DEBUG(dev, "channel heap\n"); |
5125bfd8 BS |
179 | |
180 | ramin = drm_mm_search_free(&chan->ramin_heap, size, align, 0); | |
181 | if (ramin) | |
182 | ramin = drm_mm_get_block(ramin, size, align); | |
183 | ||
184 | if (!ramin) { | |
185 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
186 | return -ENOMEM; | |
187 | } | |
6ee73861 BS |
188 | } else { |
189 | NV_DEBUG(dev, "global heap\n"); | |
6ee73861 | 190 | |
5125bfd8 | 191 | /* allocate backing pages, sets vinst */ |
9100468d | 192 | ret = engine->instmem.populate(dev, gpuobj, &size, align); |
6ee73861 | 193 | if (ret) { |
a8eaebc6 | 194 | nouveau_gpuobj_ref(NULL, &gpuobj); |
6ee73861 BS |
195 | return ret; |
196 | } | |
6ee73861 | 197 | |
5125bfd8 | 198 | /* try and get aperture space */ |
e05d7eae BS |
199 | do { |
200 | if (drm_mm_pre_get(&dev_priv->ramin_heap)) | |
201 | return -ENOMEM; | |
202 | ||
203 | spin_lock(&dev_priv->ramin_lock); | |
204 | ramin = drm_mm_search_free(&dev_priv->ramin_heap, size, | |
205 | align, 0); | |
206 | if (ramin == NULL) { | |
207 | spin_unlock(&dev_priv->ramin_lock); | |
208 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
dd661e5f | 209 | return -ENOMEM; |
e05d7eae BS |
210 | } |
211 | ||
212 | ramin = drm_mm_get_block_atomic(ramin, size, align); | |
213 | spin_unlock(&dev_priv->ramin_lock); | |
214 | } while (ramin == NULL); | |
b833ac26 | 215 | |
5125bfd8 BS |
216 | /* on nv50 it's ok to fail, we have a fallback path */ |
217 | if (!ramin && dev_priv->card_type < NV_50) { | |
218 | nouveau_gpuobj_ref(NULL, &gpuobj); | |
219 | return -ENOMEM; | |
220 | } | |
6ee73861 BS |
221 | } |
222 | ||
5125bfd8 BS |
223 | /* if we got a chunk of the aperture, map pages into it */ |
224 | gpuobj->im_pramin = ramin; | |
fbd2895e | 225 | if (!chan && gpuobj->im_pramin && dev_priv->ramin_available) { |
6ee73861 BS |
226 | ret = engine->instmem.bind(dev, gpuobj); |
227 | if (ret) { | |
a8eaebc6 | 228 | nouveau_gpuobj_ref(NULL, &gpuobj); |
6ee73861 BS |
229 | return ret; |
230 | } | |
231 | } | |
232 | ||
de3a6c0a BS |
233 | /* calculate the various different addresses for the object */ |
234 | if (chan) { | |
5125bfd8 BS |
235 | gpuobj->pinst = chan->ramin->pinst; |
236 | if (gpuobj->pinst != ~0) | |
237 | gpuobj->pinst += gpuobj->im_pramin->start; | |
238 | ||
de3a6c0a BS |
239 | if (dev_priv->card_type < NV_50) { |
240 | gpuobj->cinst = gpuobj->pinst; | |
241 | } else { | |
242 | gpuobj->cinst = gpuobj->im_pramin->start; | |
243 | gpuobj->vinst = gpuobj->im_pramin->start + | |
43efc9ce | 244 | chan->ramin->vinst; |
de3a6c0a BS |
245 | } |
246 | } else { | |
5125bfd8 BS |
247 | if (gpuobj->im_pramin) |
248 | gpuobj->pinst = gpuobj->im_pramin->start; | |
249 | else | |
250 | gpuobj->pinst = ~0; | |
de3a6c0a | 251 | gpuobj->cinst = 0xdeadbeef; |
de3a6c0a BS |
252 | } |
253 | ||
6ee73861 BS |
254 | if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { |
255 | int i; | |
256 | ||
43efc9ce | 257 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 258 | nv_wo32(gpuobj, i, 0); |
f56cb86f | 259 | engine->instmem.flush(dev); |
6ee73861 BS |
260 | } |
261 | ||
a8eaebc6 | 262 | |
6ee73861 BS |
263 | *gpuobj_ret = gpuobj; |
264 | return 0; | |
265 | } | |
266 | ||
267 | int | |
fbd2895e | 268 | nouveau_gpuobj_init(struct drm_device *dev) |
6ee73861 BS |
269 | { |
270 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
271 | ||
272 | NV_DEBUG(dev, "\n"); | |
273 | ||
274 | INIT_LIST_HEAD(&dev_priv->gpuobj_list); | |
5125bfd8 BS |
275 | spin_lock_init(&dev_priv->ramin_lock); |
276 | dev_priv->ramin_base = ~0; | |
6ee73861 BS |
277 | |
278 | return 0; | |
279 | } | |
280 | ||
6ee73861 BS |
281 | void |
282 | nouveau_gpuobj_takedown(struct drm_device *dev) | |
283 | { | |
284 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
b8c157d3 BS |
285 | struct nouveau_gpuobj_method *om, *tm; |
286 | struct nouveau_gpuobj_class *oc, *tc; | |
6ee73861 BS |
287 | |
288 | NV_DEBUG(dev, "\n"); | |
6ee73861 | 289 | |
b8c157d3 BS |
290 | list_for_each_entry_safe(oc, tc, &dev_priv->classes, head) { |
291 | list_for_each_entry_safe(om, tm, &oc->methods, head) { | |
292 | list_del(&om->head); | |
293 | kfree(om); | |
294 | } | |
295 | list_del(&oc->head); | |
296 | kfree(oc); | |
297 | } | |
298 | ||
eb9bcbdc | 299 | BUG_ON(!list_empty(&dev_priv->gpuobj_list)); |
6ee73861 BS |
300 | } |
301 | ||
185abecc | 302 | |
eb9bcbdc BS |
303 | static void |
304 | nouveau_gpuobj_del(struct kref *ref) | |
6ee73861 | 305 | { |
eb9bcbdc BS |
306 | struct nouveau_gpuobj *gpuobj = |
307 | container_of(ref, struct nouveau_gpuobj, refcount); | |
a8eaebc6 | 308 | struct drm_device *dev = gpuobj->dev; |
6ee73861 BS |
309 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
310 | struct nouveau_engine *engine = &dev_priv->engine; | |
6ee73861 BS |
311 | int i; |
312 | ||
a8eaebc6 | 313 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); |
6ee73861 BS |
314 | |
315 | if (gpuobj->im_pramin && (gpuobj->flags & NVOBJ_FLAG_ZERO_FREE)) { | |
43efc9ce | 316 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 317 | nv_wo32(gpuobj, i, 0); |
f56cb86f | 318 | engine->instmem.flush(dev); |
6ee73861 BS |
319 | } |
320 | ||
321 | if (gpuobj->dtor) | |
322 | gpuobj->dtor(dev, gpuobj); | |
323 | ||
43efc9ce | 324 | if (gpuobj->im_backing) |
6ee73861 BS |
325 | engine->instmem.clear(dev, gpuobj); |
326 | ||
e05d7eae | 327 | spin_lock(&dev_priv->ramin_lock); |
43efc9ce BS |
328 | if (gpuobj->im_pramin) |
329 | drm_mm_put_block(gpuobj->im_pramin); | |
6ee73861 | 330 | list_del(&gpuobj->list); |
e05d7eae | 331 | spin_unlock(&dev_priv->ramin_lock); |
6ee73861 | 332 | |
6ee73861 | 333 | kfree(gpuobj); |
6ee73861 BS |
334 | } |
335 | ||
a8eaebc6 BS |
336 | void |
337 | nouveau_gpuobj_ref(struct nouveau_gpuobj *ref, struct nouveau_gpuobj **ptr) | |
6ee73861 | 338 | { |
a8eaebc6 | 339 | if (ref) |
eb9bcbdc | 340 | kref_get(&ref->refcount); |
6ee73861 | 341 | |
eb9bcbdc BS |
342 | if (*ptr) |
343 | kref_put(&(*ptr)->refcount, nouveau_gpuobj_del); | |
6ee73861 | 344 | |
a8eaebc6 | 345 | *ptr = ref; |
6ee73861 BS |
346 | } |
347 | ||
348 | int | |
43efc9ce BS |
349 | nouveau_gpuobj_new_fake(struct drm_device *dev, u32 pinst, u64 vinst, |
350 | u32 size, u32 flags, struct nouveau_gpuobj **pgpuobj) | |
6ee73861 BS |
351 | { |
352 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
353 | struct nouveau_gpuobj *gpuobj = NULL; | |
354 | int i; | |
355 | ||
356 | NV_DEBUG(dev, | |
43efc9ce BS |
357 | "pinst=0x%08x vinst=0x%010llx size=0x%08x flags=0x%08x\n", |
358 | pinst, vinst, size, flags); | |
6ee73861 BS |
359 | |
360 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | |
361 | if (!gpuobj) | |
362 | return -ENOMEM; | |
363 | NV_DEBUG(dev, "gpuobj %p\n", gpuobj); | |
b3beb167 | 364 | gpuobj->dev = dev; |
43efc9ce | 365 | gpuobj->flags = flags; |
eb9bcbdc | 366 | kref_init(&gpuobj->refcount); |
43efc9ce BS |
367 | gpuobj->size = size; |
368 | gpuobj->pinst = pinst; | |
de3a6c0a | 369 | gpuobj->cinst = 0xdeadbeef; |
43efc9ce | 370 | gpuobj->vinst = vinst; |
de3a6c0a | 371 | |
6ee73861 | 372 | if (gpuobj->flags & NVOBJ_FLAG_ZERO_ALLOC) { |
43efc9ce | 373 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 374 | nv_wo32(gpuobj, i, 0); |
f56cb86f | 375 | dev_priv->engine.instmem.flush(dev); |
6ee73861 BS |
376 | } |
377 | ||
e05d7eae | 378 | spin_lock(&dev_priv->ramin_lock); |
43efc9ce | 379 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); |
e05d7eae | 380 | spin_unlock(&dev_priv->ramin_lock); |
43efc9ce | 381 | *pgpuobj = gpuobj; |
6ee73861 BS |
382 | return 0; |
383 | } | |
384 | ||
385 | ||
386 | static uint32_t | |
387 | nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class) | |
388 | { | |
389 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
390 | ||
391 | /*XXX: dodgy hack for now */ | |
392 | if (dev_priv->card_type >= NV_50) | |
393 | return 24; | |
394 | if (dev_priv->card_type >= NV_40) | |
395 | return 32; | |
396 | return 16; | |
397 | } | |
398 | ||
399 | /* | |
400 | DMA objects are used to reference a piece of memory in the | |
401 | framebuffer, PCI or AGP address space. Each object is 16 bytes big | |
402 | and looks as follows: | |
403 | ||
404 | entry[0] | |
405 | 11:0 class (seems like I can always use 0 here) | |
406 | 12 page table present? | |
407 | 13 page entry linear? | |
408 | 15:14 access: 0 rw, 1 ro, 2 wo | |
409 | 17:16 target: 0 NV memory, 1 NV memory tiled, 2 PCI, 3 AGP | |
410 | 31:20 dma adjust (bits 0-11 of the address) | |
411 | entry[1] | |
412 | dma limit (size of transfer) | |
413 | entry[X] | |
414 | 1 0 readonly, 1 readwrite | |
415 | 31:12 dma frame address of the page (bits 12-31 of the address) | |
416 | entry[N] | |
417 | page table terminator, same value as the first pte, as does nvidia | |
418 | rivatv uses 0xffffffff | |
419 | ||
420 | Non linear page tables need a list of frame addresses afterwards, | |
421 | the rivatv project has some info on this. | |
422 | ||
423 | The method below creates a DMA object in instance RAM and returns a handle | |
424 | to it that can be used to set up context objects. | |
425 | */ | |
426 | int | |
427 | nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, | |
428 | uint64_t offset, uint64_t size, int access, | |
429 | int target, struct nouveau_gpuobj **gpuobj) | |
430 | { | |
431 | struct drm_device *dev = chan->dev; | |
432 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
433 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | |
434 | int ret; | |
435 | ||
436 | NV_DEBUG(dev, "ch%d class=0x%04x offset=0x%llx size=0x%llx\n", | |
437 | chan->id, class, offset, size); | |
438 | NV_DEBUG(dev, "access=%d target=%d\n", access, target); | |
439 | ||
440 | switch (target) { | |
441 | case NV_DMA_TARGET_AGP: | |
442 | offset += dev_priv->gart_info.aper_base; | |
443 | break; | |
444 | default: | |
445 | break; | |
446 | } | |
447 | ||
448 | ret = nouveau_gpuobj_new(dev, chan, | |
449 | nouveau_gpuobj_class_instmem_size(dev, class), | |
450 | 16, NVOBJ_FLAG_ZERO_ALLOC | | |
451 | NVOBJ_FLAG_ZERO_FREE, gpuobj); | |
452 | if (ret) { | |
453 | NV_ERROR(dev, "Error creating gpuobj: %d\n", ret); | |
454 | return ret; | |
455 | } | |
456 | ||
6ee73861 BS |
457 | if (dev_priv->card_type < NV_50) { |
458 | uint32_t frame, adjust, pte_flags = 0; | |
459 | ||
460 | if (access != NV_DMA_ACCESS_RO) | |
461 | pte_flags |= (1<<1); | |
462 | adjust = offset & 0x00000fff; | |
463 | frame = offset & ~0x00000fff; | |
464 | ||
b3beb167 BS |
465 | nv_wo32(*gpuobj, 0, ((1<<12) | (1<<13) | (adjust << 20) | |
466 | (access << 14) | (target << 16) | | |
467 | class)); | |
468 | nv_wo32(*gpuobj, 4, size - 1); | |
469 | nv_wo32(*gpuobj, 8, frame | pte_flags); | |
470 | nv_wo32(*gpuobj, 12, frame | pte_flags); | |
6ee73861 BS |
471 | } else { |
472 | uint64_t limit = offset + size - 1; | |
473 | uint32_t flags0, flags5; | |
474 | ||
475 | if (target == NV_DMA_TARGET_VIDMEM) { | |
476 | flags0 = 0x00190000; | |
477 | flags5 = 0x00010000; | |
478 | } else { | |
479 | flags0 = 0x7fc00000; | |
480 | flags5 = 0x00080000; | |
481 | } | |
482 | ||
b3beb167 BS |
483 | nv_wo32(*gpuobj, 0, flags0 | class); |
484 | nv_wo32(*gpuobj, 4, lower_32_bits(limit)); | |
485 | nv_wo32(*gpuobj, 8, lower_32_bits(offset)); | |
486 | nv_wo32(*gpuobj, 12, ((upper_32_bits(limit) & 0xff) << 24) | | |
487 | (upper_32_bits(offset) & 0xff)); | |
488 | nv_wo32(*gpuobj, 20, flags5); | |
6ee73861 BS |
489 | } |
490 | ||
f56cb86f | 491 | instmem->flush(dev); |
6ee73861 BS |
492 | |
493 | (*gpuobj)->engine = NVOBJ_ENGINE_SW; | |
494 | (*gpuobj)->class = class; | |
495 | return 0; | |
496 | } | |
497 | ||
498 | int | |
499 | nouveau_gpuobj_gart_dma_new(struct nouveau_channel *chan, | |
500 | uint64_t offset, uint64_t size, int access, | |
501 | struct nouveau_gpuobj **gpuobj, | |
502 | uint32_t *o_ret) | |
503 | { | |
504 | struct drm_device *dev = chan->dev; | |
505 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
506 | int ret; | |
507 | ||
508 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP || | |
509 | (dev_priv->card_type >= NV_50 && | |
510 | dev_priv->gart_info.type == NOUVEAU_GART_SGDMA)) { | |
511 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
512 | offset + dev_priv->vm_gart_base, | |
513 | size, access, NV_DMA_TARGET_AGP, | |
514 | gpuobj); | |
515 | if (o_ret) | |
516 | *o_ret = 0; | |
517 | } else | |
518 | if (dev_priv->gart_info.type == NOUVEAU_GART_SGDMA) { | |
a8eaebc6 | 519 | nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, gpuobj); |
6ee73861 BS |
520 | if (offset & ~0xffffffffULL) { |
521 | NV_ERROR(dev, "obj offset exceeds 32-bits\n"); | |
522 | return -EINVAL; | |
523 | } | |
524 | if (o_ret) | |
525 | *o_ret = (uint32_t)offset; | |
526 | ret = (*gpuobj != NULL) ? 0 : -EINVAL; | |
527 | } else { | |
528 | NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type); | |
529 | return -EINVAL; | |
530 | } | |
531 | ||
532 | return ret; | |
533 | } | |
534 | ||
535 | /* Context objects in the instance RAM have the following structure. | |
536 | * On NV40 they are 32 byte long, on NV30 and smaller 16 bytes. | |
537 | ||
538 | NV4 - NV30: | |
539 | ||
540 | entry[0] | |
541 | 11:0 class | |
542 | 12 chroma key enable | |
543 | 13 user clip enable | |
544 | 14 swizzle enable | |
545 | 17:15 patch config: | |
546 | scrcopy_and, rop_and, blend_and, scrcopy, srccopy_pre, blend_pre | |
547 | 18 synchronize enable | |
548 | 19 endian: 1 big, 0 little | |
549 | 21:20 dither mode | |
550 | 23 single step enable | |
551 | 24 patch status: 0 invalid, 1 valid | |
552 | 25 context_surface 0: 1 valid | |
553 | 26 context surface 1: 1 valid | |
554 | 27 context pattern: 1 valid | |
555 | 28 context rop: 1 valid | |
556 | 29,30 context beta, beta4 | |
557 | entry[1] | |
558 | 7:0 mono format | |
559 | 15:8 color format | |
560 | 31:16 notify instance address | |
561 | entry[2] | |
562 | 15:0 dma 0 instance address | |
563 | 31:16 dma 1 instance address | |
564 | entry[3] | |
565 | dma method traps | |
566 | ||
567 | NV40: | |
568 | No idea what the exact format is. Here's what can be deducted: | |
569 | ||
570 | entry[0]: | |
571 | 11:0 class (maybe uses more bits here?) | |
572 | 17 user clip enable | |
573 | 21:19 patch config | |
574 | 25 patch status valid ? | |
575 | entry[1]: | |
576 | 15:0 DMA notifier (maybe 20:0) | |
577 | entry[2]: | |
578 | 15:0 DMA 0 instance (maybe 20:0) | |
579 | 24 big endian | |
580 | entry[3]: | |
581 | 15:0 DMA 1 instance (maybe 20:0) | |
582 | entry[4]: | |
583 | entry[5]: | |
584 | set to 0? | |
585 | */ | |
a6a1a380 BS |
586 | static int |
587 | nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class, | |
588 | struct nouveau_gpuobj **gpuobj_ret) | |
589 | { | |
590 | struct drm_nouveau_private *dev_priv; | |
591 | struct nouveau_gpuobj *gpuobj; | |
592 | ||
593 | if (!chan || !gpuobj_ret || *gpuobj_ret != NULL) | |
594 | return -EINVAL; | |
595 | dev_priv = chan->dev->dev_private; | |
596 | ||
597 | gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL); | |
598 | if (!gpuobj) | |
599 | return -ENOMEM; | |
600 | gpuobj->dev = chan->dev; | |
601 | gpuobj->engine = NVOBJ_ENGINE_SW; | |
602 | gpuobj->class = class; | |
603 | kref_init(&gpuobj->refcount); | |
604 | gpuobj->cinst = 0x40; | |
605 | ||
606 | spin_lock(&dev_priv->ramin_lock); | |
607 | list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list); | |
608 | spin_unlock(&dev_priv->ramin_lock); | |
609 | *gpuobj_ret = gpuobj; | |
610 | return 0; | |
611 | } | |
612 | ||
6ee73861 BS |
613 | int |
614 | nouveau_gpuobj_gr_new(struct nouveau_channel *chan, int class, | |
615 | struct nouveau_gpuobj **gpuobj) | |
616 | { | |
a6a1a380 | 617 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; |
6ee73861 | 618 | struct drm_device *dev = chan->dev; |
b8c157d3 | 619 | struct nouveau_gpuobj_class *oc; |
6ee73861 BS |
620 | int ret; |
621 | ||
622 | NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class); | |
623 | ||
b8c157d3 BS |
624 | list_for_each_entry(oc, &dev_priv->classes, head) { |
625 | if (oc->id == class) | |
626 | goto found; | |
a6a1a380 BS |
627 | } |
628 | ||
b8c157d3 BS |
629 | NV_ERROR(dev, "illegal object class: 0x%x\n", class); |
630 | return -EINVAL; | |
a6a1a380 | 631 | |
b8c157d3 BS |
632 | found: |
633 | if (oc->engine == NVOBJ_ENGINE_SW) | |
a6a1a380 BS |
634 | return nouveau_gpuobj_sw_new(chan, class, gpuobj); |
635 | ||
6ee73861 BS |
636 | ret = nouveau_gpuobj_new(dev, chan, |
637 | nouveau_gpuobj_class_instmem_size(dev, class), | |
638 | 16, | |
639 | NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE, | |
640 | gpuobj); | |
641 | if (ret) { | |
a6a1a380 | 642 | NV_ERROR(dev, "error creating gpuobj: %d\n", ret); |
6ee73861 BS |
643 | return ret; |
644 | } | |
645 | ||
6ee73861 | 646 | if (dev_priv->card_type >= NV_50) { |
b3beb167 BS |
647 | nv_wo32(*gpuobj, 0, class); |
648 | nv_wo32(*gpuobj, 20, 0x00010000); | |
6ee73861 BS |
649 | } else { |
650 | switch (class) { | |
651 | case NV_CLASS_NULL: | |
b3beb167 BS |
652 | nv_wo32(*gpuobj, 0, 0x00001030); |
653 | nv_wo32(*gpuobj, 4, 0xFFFFFFFF); | |
6ee73861 BS |
654 | break; |
655 | default: | |
656 | if (dev_priv->card_type >= NV_40) { | |
b3beb167 | 657 | nv_wo32(*gpuobj, 0, class); |
6ee73861 | 658 | #ifdef __BIG_ENDIAN |
b3beb167 | 659 | nv_wo32(*gpuobj, 8, 0x01000000); |
6ee73861 BS |
660 | #endif |
661 | } else { | |
662 | #ifdef __BIG_ENDIAN | |
b3beb167 | 663 | nv_wo32(*gpuobj, 0, class | 0x00080000); |
6ee73861 | 664 | #else |
b3beb167 | 665 | nv_wo32(*gpuobj, 0, class); |
6ee73861 BS |
666 | #endif |
667 | } | |
668 | } | |
669 | } | |
f56cb86f | 670 | dev_priv->engine.instmem.flush(dev); |
6ee73861 | 671 | |
b8c157d3 BS |
672 | (*gpuobj)->engine = oc->engine; |
673 | (*gpuobj)->class = oc->id; | |
6ee73861 BS |
674 | return 0; |
675 | } | |
676 | ||
6ee73861 BS |
677 | static int |
678 | nouveau_gpuobj_channel_init_pramin(struct nouveau_channel *chan) | |
679 | { | |
680 | struct drm_device *dev = chan->dev; | |
681 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
6ee73861 BS |
682 | uint32_t size; |
683 | uint32_t base; | |
684 | int ret; | |
685 | ||
686 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
687 | ||
688 | /* Base amount for object storage (4KiB enough?) */ | |
689 | size = 0x1000; | |
690 | base = 0; | |
691 | ||
692 | /* PGRAPH context */ | |
816544b2 | 693 | size += dev_priv->engine.graph.grctx_size; |
6ee73861 BS |
694 | |
695 | if (dev_priv->card_type == NV_50) { | |
696 | /* Various fixed table thingos */ | |
697 | size += 0x1400; /* mostly unknown stuff */ | |
698 | size += 0x4000; /* vm pd */ | |
699 | base = 0x6000; | |
700 | /* RAMHT, not sure about setting size yet, 32KiB to be safe */ | |
701 | size += 0x8000; | |
702 | /* RAMFC */ | |
703 | size += 0x1000; | |
6ee73861 BS |
704 | } |
705 | ||
a8eaebc6 | 706 | ret = nouveau_gpuobj_new(dev, NULL, size, 0x1000, 0, &chan->ramin); |
6ee73861 BS |
707 | if (ret) { |
708 | NV_ERROR(dev, "Error allocating channel PRAMIN: %d\n", ret); | |
709 | return ret; | |
710 | } | |
6ee73861 | 711 | |
de3a6c0a | 712 | ret = drm_mm_init(&chan->ramin_heap, base, size); |
6ee73861 BS |
713 | if (ret) { |
714 | NV_ERROR(dev, "Error creating PRAMIN heap: %d\n", ret); | |
a8eaebc6 | 715 | nouveau_gpuobj_ref(NULL, &chan->ramin); |
6ee73861 BS |
716 | return ret; |
717 | } | |
718 | ||
719 | return 0; | |
720 | } | |
721 | ||
722 | int | |
723 | nouveau_gpuobj_channel_init(struct nouveau_channel *chan, | |
724 | uint32_t vram_h, uint32_t tt_h) | |
725 | { | |
726 | struct drm_device *dev = chan->dev; | |
727 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
728 | struct nouveau_instmem_engine *instmem = &dev_priv->engine.instmem; | |
729 | struct nouveau_gpuobj *vram = NULL, *tt = NULL; | |
730 | int ret, i; | |
731 | ||
6ee73861 BS |
732 | NV_DEBUG(dev, "ch%d vram=0x%08x tt=0x%08x\n", chan->id, vram_h, tt_h); |
733 | ||
816544b2 BS |
734 | /* Allocate a chunk of memory for per-channel object storage */ |
735 | ret = nouveau_gpuobj_channel_init_pramin(chan); | |
736 | if (ret) { | |
737 | NV_ERROR(dev, "init pramin\n"); | |
738 | return ret; | |
6ee73861 BS |
739 | } |
740 | ||
741 | /* NV50 VM | |
742 | * - Allocate per-channel page-directory | |
743 | * - Map GART and VRAM into the channel's address space at the | |
744 | * locations determined during init. | |
745 | */ | |
746 | if (dev_priv->card_type >= NV_50) { | |
5125bfd8 BS |
747 | u32 pgd_offs = (dev_priv->chipset == 0x50) ? 0x1400 : 0x0200; |
748 | u64 vm_vinst = chan->ramin->vinst + pgd_offs; | |
749 | u32 vm_pinst = chan->ramin->pinst; | |
750 | u32 pde; | |
6ee73861 | 751 | |
5125bfd8 BS |
752 | if (vm_pinst != ~0) |
753 | vm_pinst += pgd_offs; | |
6ee73861 | 754 | |
5125bfd8 | 755 | ret = nouveau_gpuobj_new_fake(dev, vm_pinst, vm_vinst, 0x4000, |
a8eaebc6 | 756 | 0, &chan->vm_pd); |
f56cb86f | 757 | if (ret) |
6ee73861 | 758 | return ret; |
6ee73861 | 759 | for (i = 0; i < 0x4000; i += 8) { |
b3beb167 BS |
760 | nv_wo32(chan->vm_pd, i + 0, 0x00000000); |
761 | nv_wo32(chan->vm_pd, i + 4, 0xdeadcafe); | |
6ee73861 BS |
762 | } |
763 | ||
a8eaebc6 BS |
764 | nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, |
765 | &chan->vm_gart_pt); | |
b3beb167 | 766 | pde = (dev_priv->vm_gart_base / (512*1024*1024)) * 8; |
a8eaebc6 | 767 | nv_wo32(chan->vm_pd, pde + 0, chan->vm_gart_pt->vinst | 3); |
b3beb167 | 768 | nv_wo32(chan->vm_pd, pde + 4, 0x00000000); |
6ee73861 | 769 | |
b3beb167 | 770 | pde = (dev_priv->vm_vram_base / (512*1024*1024)) * 8; |
6ee73861 | 771 | for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) { |
a8eaebc6 BS |
772 | nouveau_gpuobj_ref(dev_priv->vm_vram_pt[i], |
773 | &chan->vm_vram_pt[i]); | |
6ee73861 | 774 | |
b3beb167 | 775 | nv_wo32(chan->vm_pd, pde + 0, |
a8eaebc6 | 776 | chan->vm_vram_pt[i]->vinst | 0x61); |
b3beb167 BS |
777 | nv_wo32(chan->vm_pd, pde + 4, 0x00000000); |
778 | pde += 8; | |
6ee73861 BS |
779 | } |
780 | ||
f56cb86f | 781 | instmem->flush(dev); |
6ee73861 BS |
782 | } |
783 | ||
784 | /* RAMHT */ | |
785 | if (dev_priv->card_type < NV_50) { | |
a8eaebc6 BS |
786 | nouveau_ramht_ref(dev_priv->ramht, &chan->ramht, NULL); |
787 | } else { | |
788 | struct nouveau_gpuobj *ramht = NULL; | |
789 | ||
790 | ret = nouveau_gpuobj_new(dev, chan, 0x8000, 16, | |
791 | NVOBJ_FLAG_ZERO_ALLOC, &ramht); | |
6ee73861 BS |
792 | if (ret) |
793 | return ret; | |
a8eaebc6 BS |
794 | |
795 | ret = nouveau_ramht_new(dev, ramht, &chan->ramht); | |
796 | nouveau_gpuobj_ref(NULL, &ramht); | |
6ee73861 BS |
797 | if (ret) |
798 | return ret; | |
799 | } | |
800 | ||
801 | /* VRAM ctxdma */ | |
802 | if (dev_priv->card_type >= NV_50) { | |
803 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
804 | 0, dev_priv->vm_end, | |
805 | NV_DMA_ACCESS_RW, | |
806 | NV_DMA_TARGET_AGP, &vram); | |
807 | if (ret) { | |
808 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
809 | return ret; | |
810 | } | |
811 | } else { | |
812 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, | |
a8eaebc6 BS |
813 | 0, dev_priv->fb_available_size, |
814 | NV_DMA_ACCESS_RW, | |
815 | NV_DMA_TARGET_VIDMEM, &vram); | |
6ee73861 BS |
816 | if (ret) { |
817 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
818 | return ret; | |
819 | } | |
820 | } | |
821 | ||
a8eaebc6 BS |
822 | ret = nouveau_ramht_insert(chan, vram_h, vram); |
823 | nouveau_gpuobj_ref(NULL, &vram); | |
6ee73861 | 824 | if (ret) { |
a8eaebc6 | 825 | NV_ERROR(dev, "Error adding VRAM ctxdma to RAMHT: %d\n", ret); |
6ee73861 BS |
826 | return ret; |
827 | } | |
828 | ||
829 | /* TT memory ctxdma */ | |
830 | if (dev_priv->card_type >= NV_50) { | |
a8eaebc6 BS |
831 | ret = nouveau_gpuobj_dma_new(chan, NV_CLASS_DMA_IN_MEMORY, |
832 | 0, dev_priv->vm_end, | |
833 | NV_DMA_ACCESS_RW, | |
834 | NV_DMA_TARGET_AGP, &tt); | |
835 | if (ret) { | |
836 | NV_ERROR(dev, "Error creating VRAM ctxdma: %d\n", ret); | |
837 | return ret; | |
838 | } | |
6ee73861 BS |
839 | } else |
840 | if (dev_priv->gart_info.type != NOUVEAU_GART_NONE) { | |
841 | ret = nouveau_gpuobj_gart_dma_new(chan, 0, | |
842 | dev_priv->gart_info.aper_size, | |
843 | NV_DMA_ACCESS_RW, &tt, NULL); | |
844 | } else { | |
845 | NV_ERROR(dev, "Invalid GART type %d\n", dev_priv->gart_info.type); | |
846 | ret = -EINVAL; | |
847 | } | |
848 | ||
849 | if (ret) { | |
850 | NV_ERROR(dev, "Error creating TT ctxdma: %d\n", ret); | |
851 | return ret; | |
852 | } | |
853 | ||
a8eaebc6 BS |
854 | ret = nouveau_ramht_insert(chan, tt_h, tt); |
855 | nouveau_gpuobj_ref(NULL, &tt); | |
6ee73861 | 856 | if (ret) { |
a8eaebc6 | 857 | NV_ERROR(dev, "Error adding TT ctxdma to RAMHT: %d\n", ret); |
6ee73861 BS |
858 | return ret; |
859 | } | |
860 | ||
861 | return 0; | |
862 | } | |
863 | ||
864 | void | |
865 | nouveau_gpuobj_channel_takedown(struct nouveau_channel *chan) | |
866 | { | |
867 | struct drm_nouveau_private *dev_priv = chan->dev->dev_private; | |
868 | struct drm_device *dev = chan->dev; | |
6ee73861 BS |
869 | int i; |
870 | ||
871 | NV_DEBUG(dev, "ch%d\n", chan->id); | |
872 | ||
a8eaebc6 | 873 | if (!chan->ramht) |
6ee73861 BS |
874 | return; |
875 | ||
a8eaebc6 | 876 | nouveau_ramht_ref(NULL, &chan->ramht, chan); |
6ee73861 | 877 | |
a8eaebc6 BS |
878 | nouveau_gpuobj_ref(NULL, &chan->vm_pd); |
879 | nouveau_gpuobj_ref(NULL, &chan->vm_gart_pt); | |
6ee73861 | 880 | for (i = 0; i < dev_priv->vm_vram_pt_nr; i++) |
a8eaebc6 | 881 | nouveau_gpuobj_ref(NULL, &chan->vm_vram_pt[i]); |
6ee73861 | 882 | |
b833ac26 BS |
883 | if (chan->ramin_heap.free_stack.next) |
884 | drm_mm_takedown(&chan->ramin_heap); | |
a8eaebc6 | 885 | nouveau_gpuobj_ref(NULL, &chan->ramin); |
6ee73861 BS |
886 | } |
887 | ||
888 | int | |
889 | nouveau_gpuobj_suspend(struct drm_device *dev) | |
890 | { | |
891 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
892 | struct nouveau_gpuobj *gpuobj; | |
893 | int i; | |
894 | ||
895 | if (dev_priv->card_type < NV_50) { | |
896 | dev_priv->susres.ramin_copy = vmalloc(dev_priv->ramin_rsvd_vram); | |
897 | if (!dev_priv->susres.ramin_copy) | |
898 | return -ENOMEM; | |
899 | ||
900 | for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4) | |
901 | dev_priv->susres.ramin_copy[i/4] = nv_ri32(dev, i); | |
902 | return 0; | |
903 | } | |
904 | ||
905 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { | |
43efc9ce | 906 | if (!gpuobj->im_backing) |
6ee73861 BS |
907 | continue; |
908 | ||
43efc9ce | 909 | gpuobj->im_backing_suspend = vmalloc(gpuobj->size); |
6ee73861 BS |
910 | if (!gpuobj->im_backing_suspend) { |
911 | nouveau_gpuobj_resume(dev); | |
912 | return -ENOMEM; | |
913 | } | |
914 | ||
43efc9ce | 915 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 916 | gpuobj->im_backing_suspend[i/4] = nv_ro32(gpuobj, i); |
6ee73861 BS |
917 | } |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
922 | void | |
923 | nouveau_gpuobj_suspend_cleanup(struct drm_device *dev) | |
924 | { | |
925 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
926 | struct nouveau_gpuobj *gpuobj; | |
927 | ||
928 | if (dev_priv->card_type < NV_50) { | |
929 | vfree(dev_priv->susres.ramin_copy); | |
930 | dev_priv->susres.ramin_copy = NULL; | |
931 | return; | |
932 | } | |
933 | ||
934 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { | |
935 | if (!gpuobj->im_backing_suspend) | |
936 | continue; | |
937 | ||
938 | vfree(gpuobj->im_backing_suspend); | |
939 | gpuobj->im_backing_suspend = NULL; | |
940 | } | |
941 | } | |
942 | ||
943 | void | |
944 | nouveau_gpuobj_resume(struct drm_device *dev) | |
945 | { | |
946 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
947 | struct nouveau_gpuobj *gpuobj; | |
948 | int i; | |
949 | ||
950 | if (dev_priv->card_type < NV_50) { | |
951 | for (i = 0; i < dev_priv->ramin_rsvd_vram; i += 4) | |
952 | nv_wi32(dev, i, dev_priv->susres.ramin_copy[i/4]); | |
953 | nouveau_gpuobj_suspend_cleanup(dev); | |
954 | return; | |
955 | } | |
956 | ||
957 | list_for_each_entry(gpuobj, &dev_priv->gpuobj_list, list) { | |
958 | if (!gpuobj->im_backing_suspend) | |
959 | continue; | |
960 | ||
43efc9ce | 961 | for (i = 0; i < gpuobj->size; i += 4) |
b3beb167 | 962 | nv_wo32(gpuobj, i, gpuobj->im_backing_suspend[i/4]); |
f56cb86f | 963 | dev_priv->engine.instmem.flush(dev); |
6ee73861 BS |
964 | } |
965 | ||
966 | nouveau_gpuobj_suspend_cleanup(dev); | |
967 | } | |
968 | ||
969 | int nouveau_ioctl_grobj_alloc(struct drm_device *dev, void *data, | |
970 | struct drm_file *file_priv) | |
971 | { | |
6ee73861 | 972 | struct drm_nouveau_grobj_alloc *init = data; |
6ee73861 BS |
973 | struct nouveau_gpuobj *gr = NULL; |
974 | struct nouveau_channel *chan; | |
975 | int ret; | |
976 | ||
6ee73861 BS |
977 | if (init->handle == ~0) |
978 | return -EINVAL; | |
979 | ||
cff5c133 BS |
980 | chan = nouveau_channel_get(dev, file_priv, init->channel); |
981 | if (IS_ERR(chan)) | |
982 | return PTR_ERR(chan); | |
983 | ||
984 | if (nouveau_ramht_find(chan, init->handle)) { | |
985 | ret = -EEXIST; | |
986 | goto out; | |
987 | } | |
6ee73861 | 988 | |
a6a1a380 | 989 | ret = nouveau_gpuobj_gr_new(chan, init->class, &gr); |
6ee73861 BS |
990 | if (ret) { |
991 | NV_ERROR(dev, "Error creating object: %d (%d/0x%08x)\n", | |
992 | ret, init->channel, init->handle); | |
cff5c133 | 993 | goto out; |
6ee73861 BS |
994 | } |
995 | ||
a8eaebc6 BS |
996 | ret = nouveau_ramht_insert(chan, init->handle, gr); |
997 | nouveau_gpuobj_ref(NULL, &gr); | |
6ee73861 BS |
998 | if (ret) { |
999 | NV_ERROR(dev, "Error referencing object: %d (%d/0x%08x)\n", | |
1000 | ret, init->channel, init->handle); | |
6ee73861 BS |
1001 | } |
1002 | ||
cff5c133 BS |
1003 | out: |
1004 | nouveau_channel_put(&chan); | |
1005 | return ret; | |
6ee73861 BS |
1006 | } |
1007 | ||
1008 | int nouveau_ioctl_gpuobj_free(struct drm_device *dev, void *data, | |
1009 | struct drm_file *file_priv) | |
1010 | { | |
1011 | struct drm_nouveau_gpuobj_free *objfree = data; | |
6ee73861 | 1012 | struct nouveau_channel *chan; |
18a16a76 | 1013 | int ret; |
6ee73861 | 1014 | |
cff5c133 BS |
1015 | chan = nouveau_channel_get(dev, file_priv, objfree->channel); |
1016 | if (IS_ERR(chan)) | |
1017 | return PTR_ERR(chan); | |
6ee73861 | 1018 | |
18a16a76 | 1019 | ret = nouveau_ramht_remove(chan, objfree->handle); |
cff5c133 BS |
1020 | nouveau_channel_put(&chan); |
1021 | return ret; | |
6ee73861 | 1022 | } |
b3beb167 BS |
1023 | |
1024 | u32 | |
1025 | nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset) | |
1026 | { | |
5125bfd8 BS |
1027 | struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; |
1028 | struct drm_device *dev = gpuobj->dev; | |
1029 | ||
1030 | if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { | |
1031 | u64 ptr = gpuobj->vinst + offset; | |
1032 | u32 base = ptr >> 16; | |
1033 | u32 val; | |
1034 | ||
1035 | spin_lock(&dev_priv->ramin_lock); | |
1036 | if (dev_priv->ramin_base != base) { | |
1037 | dev_priv->ramin_base = base; | |
1038 | nv_wr32(dev, 0x001700, dev_priv->ramin_base); | |
1039 | } | |
1040 | val = nv_rd32(dev, 0x700000 + (ptr & 0xffff)); | |
1041 | spin_unlock(&dev_priv->ramin_lock); | |
1042 | return val; | |
1043 | } | |
1044 | ||
1045 | return nv_ri32(dev, gpuobj->pinst + offset); | |
b3beb167 BS |
1046 | } |
1047 | ||
1048 | void | |
1049 | nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val) | |
1050 | { | |
5125bfd8 BS |
1051 | struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; |
1052 | struct drm_device *dev = gpuobj->dev; | |
1053 | ||
1054 | if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { | |
1055 | u64 ptr = gpuobj->vinst + offset; | |
1056 | u32 base = ptr >> 16; | |
1057 | ||
1058 | spin_lock(&dev_priv->ramin_lock); | |
1059 | if (dev_priv->ramin_base != base) { | |
1060 | dev_priv->ramin_base = base; | |
1061 | nv_wr32(dev, 0x001700, dev_priv->ramin_base); | |
1062 | } | |
1063 | nv_wr32(dev, 0x700000 + (ptr & 0xffff), val); | |
1064 | spin_unlock(&dev_priv->ramin_lock); | |
1065 | return; | |
1066 | } | |
1067 | ||
1068 | nv_wi32(dev, gpuobj->pinst + offset, val); | |
b3beb167 | 1069 | } |