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Merge branch 'master' into next
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nouveau_mem.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
3 * Copyright 2005 Stephane Marchesin
4 *
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Whitwell <keith@tungstengraphics.com>
30 */
31
32
33#include "drmP.h"
34#include "drm.h"
35#include "drm_sarea.h"
6ee73861 36
cbab95db
FJ		 37#include "nouveau_drv.h"
38#include "nouveau_pm.h"
573a2a37 39#include "nouveau_mm.h"
a11c3198 40#include "nouveau_vm.h"
a845fff8 41
a0af9add
FJ		 42/*
43 * NV10-NV40 tiling helpers
44 */
45
46static void
a5cf68b0
FJ		 47nv10_mem_update_tile_region(struct drm_device *dev,
48 struct nouveau_tile_reg *tile, uint32_t addr,
49 uint32_t size, uint32_t pitch, uint32_t flags)
a0af9add
FJ		 50{
51 struct drm_nouveau_private *dev_priv = dev->dev_private;
52 struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
53 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
54 struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
a5cf68b0
FJ		 55 int i = tile - dev_priv->tile.reg;
56 unsigned long save;
a0af9add 57
382d62e5 58 nouveau_fence_unref(&tile->fence);
a0af9add 59
a5cf68b0
FJ		 60 if (tile->pitch)
61 pfb->free_tile_region(dev, i);
62
63 if (pitch)
64 pfb->init_tile_region(dev, i, addr, size, pitch, flags);
65
66 spin_lock_irqsave(&dev_priv->context_switch_lock, save);
a0af9add 67 pfifo->reassign(dev, false);
a0af9add
FJ		 68 pfifo->cache_pull(dev, false);
69
70 nouveau_wait_for_idle(dev);
71
a5cf68b0
FJ		 72 pfb->set_tile_region(dev, i);
73 pgraph->set_tile_region(dev, i);
a0af9add
FJ		 74
75 pfifo->cache_pull(dev, true);
76 pfifo->reassign(dev, true);
a5cf68b0 77 spin_unlock_irqrestore(&dev_priv->context_switch_lock, save);
a0af9add
FJ		 78}
79
a5cf68b0
FJ		 80static struct nouveau_tile_reg *
81nv10_mem_get_tile_region(struct drm_device *dev, int i)
a0af9add
FJ		 82{
83 struct drm_nouveau_private *dev_priv = dev->dev_private;
a5cf68b0 84 struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
a0af9add 85
a5cf68b0 86 spin_lock(&dev_priv->tile.lock);
a0af9add 87
a5cf68b0
FJ		 88 if (!tile->used &&
89 (!tile->fence || nouveau_fence_signalled(tile->fence)))
90 tile->used = true;
91 else
92 tile = NULL;
a0af9add 93
a5cf68b0
FJ		 94 spin_unlock(&dev_priv->tile.lock);
95 return tile;
96}
a0af9add 97
a5cf68b0
FJ		 98void
99nv10_mem_put_tile_region(struct drm_device *dev, struct nouveau_tile_reg *tile,
100 struct nouveau_fence *fence)
101{
102 struct drm_nouveau_private *dev_priv = dev->dev_private;
a0af9add 103
a5cf68b0
FJ		 104 if (tile) {
105 spin_lock(&dev_priv->tile.lock);
106 if (fence) {
107 /* Mark it as pending. */
108 tile->fence = fence;
109 nouveau_fence_ref(fence);
a0af9add 110 }
a0af9add 111
a5cf68b0
FJ		 112 tile->used = false;
113 spin_unlock(&dev_priv->tile.lock);
114 }
a0af9add
FJ		 115}
116
a5cf68b0
FJ		 117struct nouveau_tile_reg *
118nv10_mem_set_tiling(struct drm_device *dev, uint32_t addr, uint32_t size,
119 uint32_t pitch, uint32_t flags)
a0af9add 120{
a5cf68b0
FJ		 121 struct drm_nouveau_private *dev_priv = dev->dev_private;
122 struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
123 struct nouveau_tile_reg *tile, *found = NULL;
124 int i;
125
126 for (i = 0; i < pfb->num_tiles; i++) {
127 tile = nv10_mem_get_tile_region(dev, i);
128
129 if (pitch && !found) {
130 found = tile;
131 continue;
132
133 } else if (tile && tile->pitch) {
134 /* Kill an unused tile region. */
135 nv10_mem_update_tile_region(dev, tile, 0, 0, 0, 0);
136 }
137
138 nv10_mem_put_tile_region(dev, tile, NULL);
a0af9add
FJ		 139 }
140
a5cf68b0
FJ		 141 if (found)
142 nv10_mem_update_tile_region(dev, found, addr, size,
143 pitch, flags);
144 return found;
a0af9add
FJ		 145}
146
6ee73861
BS		 147/*
148 * Cleanup everything
149 */
b833ac26 150void
fbd2895e 151nouveau_mem_vram_fini(struct drm_device *dev)
6ee73861
BS		 152{
153 struct drm_nouveau_private *dev_priv = dev->dev_private;
154
6ee73861
BS		 155 ttm_bo_device_release(&dev_priv->ttm.bdev);
156
157 nouveau_ttm_global_release(dev_priv);
158
fbd2895e
BS		 159 if (dev_priv->fb_mtrr >= 0) {
160 drm_mtrr_del(dev_priv->fb_mtrr,
161 pci_resource_start(dev->pdev, 1),
162 pci_resource_len(dev->pdev, 1), DRM_MTRR_WC);
163 dev_priv->fb_mtrr = -1;
164 }
165}
166
167void
168nouveau_mem_gart_fini(struct drm_device *dev)
169{
170 nouveau_sgdma_takedown(dev);
171
cd0b072f 172 if (drm_core_has_AGP(dev) && dev->agp) {
6ee73861
BS		 173 struct drm_agp_mem *entry, *tempe;
174
175 /* Remove AGP resources, but leave dev->agp
176 intact until drv_cleanup is called. */
177 list_for_each_entry_safe(entry, tempe, &dev->agp->memory, head) {
178 if (entry->bound)
179 drm_unbind_agp(entry->memory);
180 drm_free_agp(entry->memory, entry->pages);
181 kfree(entry);
182 }
183 INIT_LIST_HEAD(&dev->agp->memory);
184
185 if (dev->agp->acquired)
186 drm_agp_release(dev);
187
188 dev->agp->acquired = 0;
189 dev->agp->enabled = 0;
190 }
6ee73861
BS		 191}
192
6ee73861 193static uint32_t
a76fb4e8
BS		 194nouveau_mem_detect_nv04(struct drm_device *dev)
195{
3c7066bc 196 uint32_t boot0 = nv_rd32(dev, NV04_PFB_BOOT_0);
a76fb4e8
BS		 197
198 if (boot0 & 0x00000100)
199 return (((boot0 >> 12) & 0xf) * 2 + 2) * 1024 * 1024;
200
3c7066bc
FJ		 201 switch (boot0 & NV04_PFB_BOOT_0_RAM_AMOUNT) {
202 case NV04_PFB_BOOT_0_RAM_AMOUNT_32MB:
a76fb4e8 203 return 32 * 1024 * 1024;
3c7066bc 204 case NV04_PFB_BOOT_0_RAM_AMOUNT_16MB:
a76fb4e8 205 return 16 * 1024 * 1024;
3c7066bc 206 case NV04_PFB_BOOT_0_RAM_AMOUNT_8MB:
a76fb4e8 207 return 8 * 1024 * 1024;
3c7066bc 208 case NV04_PFB_BOOT_0_RAM_AMOUNT_4MB:
a76fb4e8
BS		 209 return 4 * 1024 * 1024;
210 }
211
212 return 0;
213}
214
215static uint32_t
216nouveau_mem_detect_nforce(struct drm_device *dev)
6ee73861
BS		 217{
218 struct drm_nouveau_private *dev_priv = dev->dev_private;
219 struct pci_dev *bridge;
220 uint32_t mem;
221
222 bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 1));
223 if (!bridge) {
224 NV_ERROR(dev, "no bridge device\n");
225 return 0;
226 }
227
a76fb4e8 228 if (dev_priv->flags & NV_NFORCE) {
6ee73861
BS		 229 pci_read_config_dword(bridge, 0x7C, &mem);
230 return (uint64_t)(((mem >> 6) & 31) + 1)*1024*1024;
231 } else
a76fb4e8 232 if (dev_priv->flags & NV_NFORCE2) {
6ee73861
BS		 233 pci_read_config_dword(bridge, 0x84, &mem);
234 return (uint64_t)(((mem >> 4) & 127) + 1)*1024*1024;
235 }
236
237 NV_ERROR(dev, "impossible!\n");
238 return 0;
239}
240
60d2a88a 241int
a76fb4e8 242nouveau_mem_detect(struct drm_device *dev)
6ee73861
BS		 243{
244 struct drm_nouveau_private *dev_priv = dev->dev_private;
a76fb4e8
BS		 245
246 if (dev_priv->card_type == NV_04) {
247 dev_priv->vram_size = nouveau_mem_detect_nv04(dev);
248 } else
249 if (dev_priv->flags & (NV_NFORCE | NV_NFORCE2)) {
250 dev_priv->vram_size = nouveau_mem_detect_nforce(dev);
7a2e4e03
BS		 251 } else
252 if (dev_priv->card_type < NV_50) {
3c7066bc
FJ		 253 dev_priv->vram_size = nv_rd32(dev, NV04_PFB_FIFO_DATA);
254 dev_priv->vram_size &= NV10_PFB_FIFO_DATA_RAM_AMOUNT_MB_MASK;
6ee73861
BS		 255 }
256
a76fb4e8
BS		 257 if (dev_priv->vram_size)
258 return 0;
259 return -ENOMEM;
6ee73861
BS		 260}
261
60d2a88a
BS		 262bool
263nouveau_mem_flags_valid(struct drm_device *dev, u32 tile_flags)
264{
265 if (!(tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK))
266 return true;
267
268 return false;
269}
270
71d06186
FJ		 271#if __OS_HAS_AGP
272static unsigned long
273get_agp_mode(struct drm_device *dev, unsigned long mode)
274{
275 struct drm_nouveau_private *dev_priv = dev->dev_private;
276
277 /*
278 * FW seems to be broken on nv18, it makes the card lock up
279 * randomly.
280 */
281 if (dev_priv->chipset == 0x18)
282 mode &= ~PCI_AGP_COMMAND_FW;
283
de5899bd
FJ		 284 /*
285 * AGP mode set in the command line.
286 */
287 if (nouveau_agpmode > 0) {
288 bool agpv3 = mode & 0x8;
289 int rate = agpv3 ? nouveau_agpmode / 4 : nouveau_agpmode;
290
291 mode = (mode & ~0x7) | (rate & 0x7);
292 }
293
71d06186
FJ		 294 return mode;
295}
296#endif
297
e04d8e82
FJ		 298int
299nouveau_mem_reset_agp(struct drm_device *dev)
6ee73861 300{
e04d8e82
FJ		 301#if __OS_HAS_AGP
302 uint32_t saved_pci_nv_1, pmc_enable;
303 int ret;
304
305 /* First of all, disable fast writes, otherwise if it's
306 * already enabled in the AGP bridge and we disable the card's
307 * AGP controller we might be locking ourselves out of it. */
316f60a1
FJ		 308 if ((nv_rd32(dev, NV04_PBUS_PCI_NV_19) |
309 dev->agp->mode) & PCI_AGP_COMMAND_FW) {
e04d8e82
FJ		 310 struct drm_agp_info info;
311 struct drm_agp_mode mode;
312
313 ret = drm_agp_info(dev, &info);
314 if (ret)
315 return ret;
316
71d06186 317 mode.mode = get_agp_mode(dev, info.mode) & ~PCI_AGP_COMMAND_FW;
e04d8e82
FJ		 318 ret = drm_agp_enable(dev, mode);
319 if (ret)
320 return ret;
321 }
6ee73861
BS		 322
323 saved_pci_nv_1 = nv_rd32(dev, NV04_PBUS_PCI_NV_1);
6ee73861
BS		 324
325 /* clear busmaster bit */
326 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1 & ~0x4);
e04d8e82
FJ		 327 /* disable AGP */
328 nv_wr32(dev, NV04_PBUS_PCI_NV_19, 0);
6ee73861
BS		 329
330 /* power cycle pgraph, if enabled */
331 pmc_enable = nv_rd32(dev, NV03_PMC_ENABLE);
332 if (pmc_enable & NV_PMC_ENABLE_PGRAPH) {
333 nv_wr32(dev, NV03_PMC_ENABLE,
334 pmc_enable & ~NV_PMC_ENABLE_PGRAPH);
335 nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
336 NV_PMC_ENABLE_PGRAPH);
337 }
338
339 /* and restore (gives effect of resetting AGP) */
6ee73861 340 nv_wr32(dev, NV04_PBUS_PCI_NV_1, saved_pci_nv_1);
b694dfb2 341#endif
6ee73861 342
e04d8e82
FJ		 343 return 0;
344}
345
6ee73861
BS		 346int
347nouveau_mem_init_agp(struct drm_device *dev)
348{
b694dfb2 349#if __OS_HAS_AGP
6ee73861
BS		 350 struct drm_nouveau_private *dev_priv = dev->dev_private;
351 struct drm_agp_info info;
352 struct drm_agp_mode mode;
353 int ret;
354
6ee73861
BS		 355 if (!dev->agp->acquired) {
356 ret = drm_agp_acquire(dev);
357 if (ret) {
358 NV_ERROR(dev, "Unable to acquire AGP: %d\n", ret);
359 return ret;
360 }
361 }
362
2b495268
FJ		 363 nouveau_mem_reset_agp(dev);
364
6ee73861
BS		 365 ret = drm_agp_info(dev, &info);
366 if (ret) {
367 NV_ERROR(dev, "Unable to get AGP info: %d\n", ret);
368 return ret;
369 }
370
371 /* see agp.h for the AGPSTAT_* modes available */
71d06186 372 mode.mode = get_agp_mode(dev, info.mode);
6ee73861
BS		 373 ret = drm_agp_enable(dev, mode);
374 if (ret) {
375 NV_ERROR(dev, "Unable to enable AGP: %d\n", ret);
376 return ret;
377 }
378
379 dev_priv->gart_info.type = NOUVEAU_GART_AGP;
380 dev_priv->gart_info.aper_base = info.aperture_base;
381 dev_priv->gart_info.aper_size = info.aperture_size;
b694dfb2 382#endif
6ee73861
BS		 383 return 0;
384}
385
386int
fbd2895e 387nouveau_mem_vram_init(struct drm_device *dev)
6ee73861
BS		 388{
389 struct drm_nouveau_private *dev_priv = dev->dev_private;
390 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
fbd2895e 391 int ret, dma_bits;
6ee73861 392
e0435120
BS		 393 dma_bits = 32;
394 if (dev_priv->card_type >= NV_50) {
395 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(40)))
396 dma_bits = 40;
397 } else
398 if (drm_pci_device_is_pcie(dev) &&
01d15332 399 dev_priv->chipset > 0x40 &&
e0435120
BS		 400 dev_priv->chipset != 0x45) {
401 if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
402 dma_bits = 39;
403 }
6ee73861
BS		 404
405 ret = pci_set_dma_mask(dev->pdev, DMA_BIT_MASK(dma_bits));
fbd2895e 406 if (ret)
6ee73861 407 return ret;
fbd2895e 408
fbd2895e 409 dev_priv->fb_phys = pci_resource_start(dev->pdev, 1);
6ee73861
BS		 410
411 ret = nouveau_ttm_global_init(dev_priv);
412 if (ret)
413 return ret;
414
415 ret = ttm_bo_device_init(&dev_priv->ttm.bdev,
416 dev_priv->ttm.bo_global_ref.ref.object,
417 &nouveau_bo_driver, DRM_FILE_PAGE_OFFSET,
418 dma_bits <= 32 ? true : false);
419 if (ret) {
420 NV_ERROR(dev, "Error initialising bo driver: %d\n", ret);
421 return ret;
422 }
423
fbd2895e 424 /* reserve space at end of VRAM for PRAMIN */
459ca7e5
BS		 425 if (dev_priv->card_type >= NV_50) {
426 dev_priv->ramin_rsvd_vram = 1 * 1024 * 1024;
427 } else
428 if (dev_priv->card_type >= NV_40) {
429 u32 vs = hweight8((nv_rd32(dev, 0x001540) & 0x0000ff00) >> 8);
430 u32 rsvd;
431
432 /* estimate grctx size, the magics come from nv40_grctx.c */
433 if (dev_priv->chipset == 0x40) rsvd = 0x6aa0 * vs;
434 else if (dev_priv->chipset < 0x43) rsvd = 0x4f00 * vs;
435 else if (nv44_graph_class(dev)) rsvd = 0x4980 * vs;
436 else rsvd = 0x4a40 * vs;
437 rsvd += 16 * 1024;
438 rsvd *= dev_priv->engine.fifo.channels;
439
440 /* pciegart table */
441 if (drm_pci_device_is_pcie(dev))
442 rsvd += 512 * 1024;
443
444 /* object storage */
445 rsvd += 512 * 1024;
446
447 dev_priv->ramin_rsvd_vram = round_up(rsvd, 4096);
448 } else {
449 dev_priv->ramin_rsvd_vram = 512 * 1024;
450 }
fbd2895e 451
60d2a88a 452 ret = dev_priv->engine.vram.init(dev);
573a2a37
BS		 453 if (ret)
454 return ret;
455
60d2a88a
BS		 456 NV_INFO(dev, "Detected %dMiB VRAM\n", (int)(dev_priv->vram_size >> 20));
457 if (dev_priv->vram_sys_base) {
458 NV_INFO(dev, "Stolen system memory at: 0x%010llx\n",
459 dev_priv->vram_sys_base);
460 }
461
573a2a37
BS		 462 dev_priv->fb_available_size = dev_priv->vram_size;
463 dev_priv->fb_mappable_pages = dev_priv->fb_available_size;
464 if (dev_priv->fb_mappable_pages > pci_resource_len(dev->pdev, 1))
465 dev_priv->fb_mappable_pages = pci_resource_len(dev->pdev, 1);
466 dev_priv->fb_mappable_pages >>= PAGE_SHIFT;
467
6ee73861
BS		 468 dev_priv->fb_available_size -= dev_priv->ramin_rsvd_vram;
469 dev_priv->fb_aper_free = dev_priv->fb_available_size;
470
471 /* mappable vram */
472 ret = ttm_bo_init_mm(bdev, TTM_PL_VRAM,
473 dev_priv->fb_available_size >> PAGE_SHIFT);
474 if (ret) {
475 NV_ERROR(dev, "Failed VRAM mm init: %d\n", ret);
476 return ret;
477 }
478
d550c41e
BS		 479 if (dev_priv->card_type < NV_50) {
480 ret = nouveau_bo_new(dev, NULL, 256*1024, 0, TTM_PL_FLAG_VRAM,
481 0, 0, &dev_priv->vga_ram);
482 if (ret == 0)
483 ret = nouveau_bo_pin(dev_priv->vga_ram,
484 TTM_PL_FLAG_VRAM);
485
486 if (ret) {
487 NV_WARN(dev, "failed to reserve VGA memory\n");
488 nouveau_bo_ref(NULL, &dev_priv->vga_ram);
489 }
ac8fb975
BS		 490 }
491
fbd2895e
BS		 492 dev_priv->fb_mtrr = drm_mtrr_add(pci_resource_start(dev->pdev, 1),
493 pci_resource_len(dev->pdev, 1),
494 DRM_MTRR_WC);
495 return 0;
496}
497
498int
499nouveau_mem_gart_init(struct drm_device *dev)
500{
501 struct drm_nouveau_private *dev_priv = dev->dev_private;
502 struct ttm_bo_device *bdev = &dev_priv->ttm.bdev;
503 int ret;
504
505 dev_priv->gart_info.type = NOUVEAU_GART_NONE;
506
6ee73861 507#if !defined(__powerpc__) && !defined(__ia64__)
8410ea3b 508 if (drm_pci_device_is_agp(dev) && dev->agp && nouveau_agpmode) {
6ee73861
BS		 509 ret = nouveau_mem_init_agp(dev);
510 if (ret)
511 NV_ERROR(dev, "Error initialising AGP: %d\n", ret);
512 }
513#endif
514
515 if (dev_priv->gart_info.type == NOUVEAU_GART_NONE) {
516 ret = nouveau_sgdma_init(dev);
517 if (ret) {
518 NV_ERROR(dev, "Error initialising PCI(E): %d\n", ret);
519 return ret;
520 }
521 }
522
523 NV_INFO(dev, "%d MiB GART (aperture)\n",
524 (int)(dev_priv->gart_info.aper_size >> 20));
525 dev_priv->gart_info.aper_free = dev_priv->gart_info.aper_size;
526
527 ret = ttm_bo_init_mm(bdev, TTM_PL_TT,
528 dev_priv->gart_info.aper_size >> PAGE_SHIFT);
529 if (ret) {
530 NV_ERROR(dev, "Failed TT mm init: %d\n", ret);
531 return ret;
532 }
533
6ee73861
BS		 534 return 0;
535}
536
7760fcb0
RS		 537void
538nouveau_mem_timing_init(struct drm_device *dev)
539{
cac8f05b 540 /* cards < NVC0 only */
7760fcb0
RS		 541 struct drm_nouveau_private *dev_priv = dev->dev_private;
542 struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
543 struct nouveau_pm_memtimings *memtimings = &pm->memtimings;
544 struct nvbios *bios = &dev_priv->vbios;
545 struct bit_entry P;
546 u8 tUNK_0, tUNK_1, tUNK_2;
547 u8 tRP; /* Byte 3 */
548 u8 tRAS; /* Byte 5 */
549 u8 tRFC; /* Byte 7 */
550 u8 tRC; /* Byte 9 */
551 u8 tUNK_10, tUNK_11, tUNK_12, tUNK_13, tUNK_14;
552 u8 tUNK_18, tUNK_19, tUNK_20, tUNK_21;
ac5c15fa 553 u8 magic_number = 0; /* Yeah... sorry*/
7760fcb0
RS		 554 u8 *mem = NULL, *entry;
555 int i, recordlen, entries;
556
557 if (bios->type == NVBIOS_BIT) {
558 if (bit_table(dev, 'P', &P))
559 return;
560
561 if (P.version == 1)
562 mem = ROMPTR(bios, P.data[4]);
563 else
564 if (P.version == 2)
565 mem = ROMPTR(bios, P.data[8]);
566 else {
567 NV_WARN(dev, "unknown mem for BIT P %d\n", P.version);
568 }
569 } else {
570 NV_DEBUG(dev, "BMP version too old for memory\n");
571 return;
572 }
573
574 if (!mem) {
575 NV_DEBUG(dev, "memory timing table pointer invalid\n");
576 return;
577 }
578
579 if (mem[0] != 0x10) {
580 NV_WARN(dev, "memory timing table 0x%02x unknown\n", mem[0]);
581 return;
582 }
583
584 /* validate record length */
585 entries = mem[2];
586 recordlen = mem[3];
587 if (recordlen < 15) {
588 NV_ERROR(dev, "mem timing table length unknown: %d\n", mem[3]);
589 return;
590 }
591
592 /* parse vbios entries into common format */
593 memtimings->timing =
594 kcalloc(entries, sizeof(*memtimings->timing), GFP_KERNEL);
595 if (!memtimings->timing)
596 return;
597
ac5c15fa
RS		 598 /* Get "some number" from the timing reg for NV_40
599 * Used in calculations later */
600 if(dev_priv->card_type == NV_40) {
601 magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24;
602 }
603
7760fcb0
RS		 604 entry = mem + mem[1];
605 for (i = 0; i < entries; i++, entry += recordlen) {
606 struct nouveau_pm_memtiming *timing = &pm->memtimings.timing[i];
607 if (entry[0] == 0)
608 continue;
609
610 tUNK_18 = 1;
611 tUNK_19 = 1;
612 tUNK_20 = 0;
613 tUNK_21 = 0;
cac8f05b
RS		 614 switch (min(recordlen, 22)) {
615 case 22:
7760fcb0 616 tUNK_21 = entry[21];
cac8f05b 617 case 21:
7760fcb0 618 tUNK_20 = entry[20];
cac8f05b 619 case 20:
7760fcb0 620 tUNK_19 = entry[19];
cac8f05b 621 case 19:
7760fcb0
RS		 622 tUNK_18 = entry[18];
623 default:
624 tUNK_0 = entry[0];
625 tUNK_1 = entry[1];
626 tUNK_2 = entry[2];
627 tRP = entry[3];
628 tRAS = entry[5];
629 tRFC = entry[7];
630 tRC = entry[9];
631 tUNK_10 = entry[10];
632 tUNK_11 = entry[11];
633 tUNK_12 = entry[12];
634 tUNK_13 = entry[13];
635 tUNK_14 = entry[14];
636 break;
637 }
638
639 timing->reg_100220 = (tRC << 24 | tRFC << 16 | tRAS << 8 | tRP);
640
641 /* XXX: I don't trust the -1's and +1's... they must come
642 * from somewhere! */
ac5c15fa 643 timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
7760fcb0 644 tUNK_18 << 16 |
ac5c15fa
RS		 645 (tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
646 if(dev_priv->chipset == 0xa8) {
647 timing->reg_100224 |= (tUNK_2 - 1);
648 } else {
649 timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
650 }
7760fcb0
RS		 651
652 timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
ac5c15fa
RS		 653 if(dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) {
654 timing->reg_100228 |= (tUNK_19 - 1) << 24;
655 }
656
657 if(dev_priv->card_type == NV_40) {
658 /* NV40: don't know what the rest of the regs are..
659 * And don't need to know either */
660 timing->reg_100228 |= 0x20200000 | magic_number << 24;
661 } else if(dev_priv->card_type >= NV_50) {
662 /* XXX: reg_10022c */
663 timing->reg_10022c = tUNK_2 - 1;
664
665 timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
666 tUNK_13 << 8 | tUNK_13);
667
668 timing->reg_100234 = (tRAS << 24 | tRC);
669 timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
670
671 if(dev_priv->chipset < 0xa3) {
672 timing->reg_100234 |= (tUNK_2 + 2) << 8;
673 } else {
674 /* XXX: +6? */
675 timing->reg_100234 |= (tUNK_19 + 6) << 8;
676 }
677
678 /* XXX; reg_100238, reg_10023c
679 * reg_100238: 0x00??????
680 * reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */
cac8f05b 681 timing->reg_10023c = 0x202;
ac5c15fa
RS		 682 if(dev_priv->chipset < 0xa3) {
683 timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
684 } else {
685 /* currently unknown
686 * 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
687 }
7760fcb0
RS		 688 }
689
7760fcb0
RS		 690 NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
691 timing->reg_100220, timing->reg_100224,
692 timing->reg_100228, timing->reg_10022c);
693 NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
694 timing->reg_100230, timing->reg_100234,
695 timing->reg_100238, timing->reg_10023c);
696 }
697
ac5c15fa 698 memtimings->nr_timing = entries;
7760fcb0
RS		 699 memtimings->supported = true;
700}
701
702void
703nouveau_mem_timing_fini(struct drm_device *dev)
704{
705 struct drm_nouveau_private *dev_priv = dev->dev_private;
706 struct nouveau_pm_memtimings *mem = &dev_priv->engine.pm.memtimings;
707
708 kfree(mem->timing);
709}
573a2a37
BS		 710
711static int
712nouveau_vram_manager_init(struct ttm_mem_type_manager *man, unsigned long p_size)
713{
714 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
715 struct nouveau_mm *mm;
d550c41e 716 u64 size, block, rsvd;
573a2a37
BS		 717 int ret;
718
d550c41e
BS		 719 rsvd = (256 * 1024); /* vga memory */
720 size = (p_size << PAGE_SHIFT) - rsvd;
721 block = dev_priv->vram_rblock_size;
573a2a37 722
d550c41e 723 ret = nouveau_mm_init(&mm, rsvd >> 12, size >> 12, block >> 12);
573a2a37
BS		 724 if (ret)
725 return ret;
726
727 man->priv = mm;
728 return 0;
729}
730
731static int
732nouveau_vram_manager_fini(struct ttm_mem_type_manager *man)
733{
734 struct nouveau_mm *mm = man->priv;
735 int ret;
736
737 ret = nouveau_mm_fini(&mm);
738 if (ret)
739 return ret;
740
741 man->priv = NULL;
742 return 0;
743}
744
745static void
746nouveau_vram_manager_del(struct ttm_mem_type_manager *man,
747 struct ttm_mem_reg *mem)
748{
749 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
60d2a88a 750 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
d5f42394 751 struct nouveau_mem *node = mem->mm_node;
573a2a37
BS		 752 struct drm_device *dev = dev_priv->dev;
753
3425df48
BS		 754 if (node->tmp_vma.node) {
755 nouveau_vm_unmap(&node->tmp_vma);
756 nouveau_vm_put(&node->tmp_vma);
757 }
758
d5f42394 759 vram->put(dev, (struct nouveau_mem **)&mem->mm_node);
573a2a37
BS		 760}
761
762static int
763nouveau_vram_manager_new(struct ttm_mem_type_manager *man,
764 struct ttm_buffer_object *bo,
765 struct ttm_placement *placement,
766 struct ttm_mem_reg *mem)
767{
768 struct drm_nouveau_private *dev_priv = nouveau_bdev(man->bdev);
60d2a88a 769 struct nouveau_vram_engine *vram = &dev_priv->engine.vram;
573a2a37
BS		 770 struct drm_device *dev = dev_priv->dev;
771 struct nouveau_bo *nvbo = nouveau_bo(bo);
d5f42394 772 struct nouveau_mem *node;
5f6fdca5 773 u32 size_nc = 0;
573a2a37
BS		 774 int ret;
775
5f6fdca5
BS		 776 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG)
777 size_nc = 1 << nvbo->vma.node->type;
778
60d2a88a
BS		 779 ret = vram->get(dev, mem->num_pages << PAGE_SHIFT,
780 mem->page_alignment << PAGE_SHIFT, size_nc,
8f7286f8 781 (nvbo->tile_flags >> 8) & 0x3ff, &node);
ef1b2871
BS		 782 if (ret) {
783 mem->mm_node = NULL;
784 return (ret == -ENOSPC) ? 0 : ret;
785 }
573a2a37 786
4c74eb7f
BS		 787 node->page_shift = 12;
788 if (nvbo->vma.node)
789 node->page_shift = nvbo->vma.node->type;
790
60d2a88a
BS		 791 mem->mm_node = node;
792 mem->start = node->offset >> PAGE_SHIFT;
573a2a37
BS		 793 return 0;
794}
795
796void
797nouveau_vram_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
798{
573a2a37
BS		 799 struct nouveau_mm *mm = man->priv;
800 struct nouveau_mm_node *r;
8b464bfe 801 u32 total = 0, free = 0;
573a2a37
BS		 802
803 mutex_lock(&mm->mutex);
804 list_for_each_entry(r, &mm->nodes, nl_entry) {
8b464bfe
BS		 805 printk(KERN_DEBUG "%s %d: 0x%010llx 0x%010llx\n",
806 prefix, r->type, ((u64)r->offset << 12),
573a2a37 807 (((u64)r->offset + r->length) << 12));
8b464bfe 808
573a2a37 809 total += r->length;
8b464bfe
BS		 810 if (!r->type)
811 free += r->length;
573a2a37
BS		 812 }
813 mutex_unlock(&mm->mutex);
814
8b464bfe
BS		 815 printk(KERN_DEBUG "%s total: 0x%010llx free: 0x%010llx\n",
816 prefix, (u64)total << 12, (u64)free << 12);
817 printk(KERN_DEBUG "%s block: 0x%08x\n",
818 prefix, mm->block_size << 12);
573a2a37
BS		 819}
820
821const struct ttm_mem_type_manager_func nouveau_vram_manager = {
822 nouveau_vram_manager_init,
823 nouveau_vram_manager_fini,
824 nouveau_vram_manager_new,
825 nouveau_vram_manager_del,
826 nouveau_vram_manager_debug
827};
26c0c9e3
BS		 828
829static int
830nouveau_gart_manager_init(struct ttm_mem_type_manager *man, unsigned long psize)
831{
832 return 0;
833}
834
835static int
836nouveau_gart_manager_fini(struct ttm_mem_type_manager *man)
837{
838 return 0;
839}
840
841static void
842nouveau_gart_manager_del(struct ttm_mem_type_manager *man,
843 struct ttm_mem_reg *mem)
844{
845 struct nouveau_mem *node = mem->mm_node;
846
847 if (node->tmp_vma.node) {
848 nouveau_vm_unmap(&node->tmp_vma);
849 nouveau_vm_put(&node->tmp_vma);
850 }
851 mem->mm_node = NULL;
852}
853
854static int
855nouveau_gart_manager_new(struct ttm_mem_type_manager *man,
856 struct ttm_buffer_object *bo,
857 struct ttm_placement *placement,
858 struct ttm_mem_reg *mem)
859{
860 struct drm_nouveau_private *dev_priv = nouveau_bdev(bo->bdev);
861 struct nouveau_bo *nvbo = nouveau_bo(bo);
862 struct nouveau_vma *vma = &nvbo->vma;
863 struct nouveau_vm *vm = vma->vm;
864 struct nouveau_mem *node;
865 int ret;
866
867 if (unlikely((mem->num_pages << PAGE_SHIFT) >=
868 dev_priv->gart_info.aper_size))
869 return -ENOMEM;
870
871 node = kzalloc(sizeof(*node), GFP_KERNEL);
872 if (!node)
873 return -ENOMEM;
874
875 /* This node must be for evicting large-paged VRAM
876 * to system memory. Due to a nv50 limitation of
877 * not being able to mix large/small pages within
878 * the same PDE, we need to create a temporary
879 * small-paged VMA for the eviction.
880 */
881 if (vma->node->type != vm->spg_shift) {
882 ret = nouveau_vm_get(vm, (u64)vma->node->length << 12,
883 vm->spg_shift, NV_MEM_ACCESS_RW,
884 &node->tmp_vma);
885 if (ret) {
886 kfree(node);
887 return ret;
888 }
889 }
890
891 node->page_shift = nvbo->vma.node->type;
892 mem->mm_node = node;
893 mem->start = 0;
894 return 0;
895}
896
897void
898nouveau_gart_manager_debug(struct ttm_mem_type_manager *man, const char *prefix)
899{
900}
901
902const struct ttm_mem_type_manager_func nouveau_gart_manager = {
903 nouveau_gart_manager_init,
904 nouveau_gart_manager_fini,
905 nouveau_gart_manager_new,
906 nouveau_gart_manager_del,
907 nouveau_gart_manager_debug
908};
kernel source for telekom puls (alcatel/mediatek)