[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nouveau_hdmi.c

/*
 * Copyright 2011 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <drm/drmP.h>
#include "nouveau_drm.h"
#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"

static bool
hdmi_sor(struct drm_encoder *encoder)
{
	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
	if (nv_device(drm->device)->chipset <  0xa3 ||
	    nv_device(drm->device)->chipset == 0xaa ||
	    nv_device(drm->device)->chipset == 0xac)
		return false;
	return true;
}

static inline u32
hdmi_base(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
	if (!hdmi_sor(encoder))
		return 0x616500 + (nv_crtc->index * 0x800);
	return 0x61c500 + (nv_encoder->or * 0x800);
}

static void
hdmi_wr32(struct drm_encoder *encoder, u32 reg, u32 val)
{
	struct nouveau_device *device = nouveau_dev(encoder->dev);
	nv_wr32(device, hdmi_base(encoder) + reg, val);
}

static u32
hdmi_rd32(struct drm_encoder *encoder, u32 reg)
{
	struct nouveau_device *device = nouveau_dev(encoder->dev);
	return nv_rd32(device, hdmi_base(encoder) + reg);
}

static u32
hdmi_mask(struct drm_encoder *encoder, u32 reg, u32 mask, u32 val)
{
	u32 tmp = hdmi_rd32(encoder, reg);
	hdmi_wr32(encoder, reg, (tmp & ~mask) | val);
	return tmp;
}

static void
nouveau_audio_disconnect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_device *device = nouveau_dev(encoder->dev);
	u32 or = nv_encoder->or * 0x800;

	if (hdmi_sor(encoder))
		nv_mask(device, 0x61c448 + or, 0x00000003, 0x00000000);
}

static void
nouveau_audio_mode_set(struct drm_encoder *encoder,
		       struct drm_display_mode *mode)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_device *device = nouveau_dev(encoder->dev);
	struct nouveau_connector *nv_connector;
	u32 or = nv_encoder->or * 0x800;
	int i;

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	if (!drm_detect_monitor_audio(nv_connector->edid)) {
		nouveau_audio_disconnect(encoder);
		return;
	}

	if (hdmi_sor(encoder)) {
		nv_mask(device, 0x61c448 + or, 0x00000001, 0x00000001);

		drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
		if (nv_connector->base.eld[0]) {
			u8 *eld = nv_connector->base.eld;
			for (i = 0; i < eld[2] * 4; i++)
				nv_wr32(device, 0x61c440 + or, (i << 8) | eld[i]);
			for (i = eld[2] * 4; i < 0x60; i++)
				nv_wr32(device, 0x61c440 + or, (i << 8) | 0x00);
			nv_mask(device, 0x61c448 + or, 0x00000002, 0x00000002);
		}
	}
}

static void
nouveau_hdmi_infoframe(struct drm_encoder *encoder, u32 ctrl, u8 *frame)
{
	/* calculate checksum for the infoframe */
	u8 sum = 0, i;
	for (i = 0; i < frame[2]; i++)
		sum += frame[i];
	frame[3] = 256 - sum;

	/* disable infoframe, and write header */
	hdmi_mask(encoder, ctrl + 0x00, 0x00000001, 0x00000000);
	hdmi_wr32(encoder, ctrl + 0x08, *(u32 *)frame & 0xffffff);

	/* register scans tell me the audio infoframe has only one set of
	 * subpack regs, according to tegra (gee nvidia, it'd be nice if we
	 * could get those docs too!), the hdmi block pads out the rest of
	 * the packet on its own.
	 */
	if (ctrl == 0x020)
		frame[2] = 6;

	/* write out checksum and data, weird weird 7 byte register pairs */
	for (i = 0; i < frame[2] + 1; i += 7) {
		u32 rsubpack = ctrl + 0x0c + ((i / 7) * 8);
		u32 *subpack = (u32 *)&frame[3 + i];
		hdmi_wr32(encoder, rsubpack + 0, subpack[0]);
		hdmi_wr32(encoder, rsubpack + 4, subpack[1] & 0xffffff);
	}

	/* enable the infoframe */
	hdmi_mask(encoder, ctrl, 0x00000001, 0x00000001);
}

static void
nouveau_hdmi_video_infoframe(struct drm_encoder *encoder,
			     struct drm_display_mode *mode)
{
	const u8 Y = 0, A = 0, B = 0, S = 0, C = 0, M = 0, R = 0;
	const u8 ITC = 0, EC = 0, Q = 0, SC = 0, VIC = 0, PR = 0;
	const u8 bar_top = 0, bar_bottom = 0, bar_left = 0, bar_right = 0;
	u8 frame[20];

	frame[0x00] = 0x82; /* AVI infoframe */
	frame[0x01] = 0x02; /* version */
	frame[0x02] = 0x0d; /* length */
	frame[0x03] = 0x00;
	frame[0x04] = (Y << 5) | (A << 4) | (B << 2) | S;
	frame[0x05] = (C << 6) | (M << 4) | R;
	frame[0x06] = (ITC << 7) | (EC << 4) | (Q << 2) | SC;
	frame[0x07] = VIC;
	frame[0x08] = PR;
	frame[0x09] = bar_top & 0xff;
	frame[0x0a] = bar_top >> 8;
	frame[0x0b] = bar_bottom & 0xff;
	frame[0x0c] = bar_bottom >> 8;
	frame[0x0d] = bar_left & 0xff;
	frame[0x0e] = bar_left >> 8;
	frame[0x0f] = bar_right & 0xff;
	frame[0x10] = bar_right >> 8;
	frame[0x11] = 0x00;
	frame[0x12] = 0x00;
	frame[0x13] = 0x00;

	nouveau_hdmi_infoframe(encoder, 0x020, frame);
}

static void
nouveau_hdmi_audio_infoframe(struct drm_encoder *encoder,
			     struct drm_display_mode *mode)
{
	const u8 CT = 0x00, CC = 0x01, ceaSS = 0x00, SF = 0x00, FMT = 0x00;
	const u8 CA = 0x00, DM_INH = 0, LSV = 0x00;
	u8 frame[12];

	frame[0x00] = 0x84;	/* Audio infoframe */
	frame[0x01] = 0x01;	/* version */
	frame[0x02] = 0x0a;	/* length */
	frame[0x03] = 0x00;
	frame[0x04] = (CT << 4) | CC;
	frame[0x05] = (SF << 2) | ceaSS;
	frame[0x06] = FMT;
	frame[0x07] = CA;
	frame[0x08] = (DM_INH << 7) | (LSV << 3);
	frame[0x09] = 0x00;
	frame[0x0a] = 0x00;
	frame[0x0b] = 0x00;

	nouveau_hdmi_infoframe(encoder, 0x000, frame);
}

static void
nouveau_hdmi_disconnect(struct drm_encoder *encoder)
{
	nouveau_audio_disconnect(encoder);

	/* disable audio and avi infoframes */
	hdmi_mask(encoder, 0x000, 0x00000001, 0x00000000);
	hdmi_mask(encoder, 0x020, 0x00000001, 0x00000000);

	/* disable hdmi */
	hdmi_mask(encoder, 0x0a4, 0x40000000, 0x00000000);
}

void
nouveau_hdmi_mode_set(struct drm_encoder *encoder,
		      struct drm_display_mode *mode)
{
	struct nouveau_device *device = nouveau_dev(encoder->dev);
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_connector *nv_connector;
	u32 max_ac_packet, rekey;

	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	if (!mode || !nv_connector || !nv_connector->edid ||
	    !drm_detect_hdmi_monitor(nv_connector->edid)) {
		nouveau_hdmi_disconnect(encoder);
		return;
	}

	nouveau_hdmi_video_infoframe(encoder, mode);
	nouveau_hdmi_audio_infoframe(encoder, mode);

	hdmi_mask(encoder, 0x0d0, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
	hdmi_mask(encoder, 0x068, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
	hdmi_mask(encoder, 0x078, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */

	nv_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
	nv_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
	nv_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */

	/* value matches nvidia binary driver, and tegra constant */
	rekey = 56;

	max_ac_packet  = mode->htotal - mode->hdisplay;
	max_ac_packet -= rekey;
	max_ac_packet -= 18; /* constant from tegra */
	max_ac_packet /= 32;

	/* enable hdmi */
	hdmi_mask(encoder, 0x0a4, 0x5f1f003f, 0x40000000 | /* enable */
					      0x1f000000 | /* unknown */
					      max_ac_packet << 16 |
					      rekey);

	nouveau_audio_mode_set(encoder, mode);
}
Commit	Line	Data
25575b41 BS	1	/*
	2	* Copyright 2011 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
760285e7	25	#include <drm/drmP.h>
77145f1c	26	#include "nouveau_drm.h"
25575b41 BS	27	#include "nouveau_connector.h"
25575b41 BS	28	#include "nouveau_encoder.h"
52c7bcdb	29	#include "nouveau_crtc.h"
25575b41 BS	30
	31	static bool
	32	hdmi_sor(struct drm_encoder *encoder)
	33	{
77145f1c BS	34	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
	35	if (nv_device(drm->device)->chipset < 0xa3 \|\|
	36	nv_device(drm->device)->chipset == 0xaa \|\|
	37	nv_device(drm->device)->chipset == 0xac)
25575b41 BS	38	return false;
	39	return true;
	40	}
	41
52c7bcdb BS	42	static inline u32
	43	hdmi_base(struct drm_encoder *encoder)
	44	{
	45	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	46	struct nouveau_crtc *nv_crtc = nouveau_crtc(nv_encoder->crtc);
	47	if (!hdmi_sor(encoder))
	48	return 0x616500 + (nv_crtc->index * 0x800);
	49	return 0x61c500 + (nv_encoder->or * 0x800);
	50	}
	51
	52	static void
	53	hdmi_wr32(struct drm_encoder *encoder, u32 reg, u32 val)
	54	{
77145f1c BS	55	struct nouveau_device *device = nouveau_dev(encoder->dev);
77145f1c BS	56	nv_wr32(device, hdmi_base(encoder) + reg, val);
52c7bcdb BS	57	}
	58
	59	static u32
	60	hdmi_rd32(struct drm_encoder *encoder, u32 reg)
	61	{
77145f1c BS	62	struct nouveau_device *device = nouveau_dev(encoder->dev);
77145f1c BS	63	return nv_rd32(device, hdmi_base(encoder) + reg);
52c7bcdb BS	64	}
	65
	66	static u32
	67	hdmi_mask(struct drm_encoder *encoder, u32 reg, u32 mask, u32 val)
	68	{
	69	u32 tmp = hdmi_rd32(encoder, reg);
	70	hdmi_wr32(encoder, reg, (tmp & ~mask) \| val);
	71	return tmp;
	72	}
	73
25575b41 BS	74	static void
	75	nouveau_audio_disconnect(struct drm_encoder *encoder)
	76	{
	77	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
77145f1c	78	struct nouveau_device *device = nouveau_dev(encoder->dev);
52c7bcdb	79	u32 or = nv_encoder->or * 0x800;
25575b41	80
77145f1c BS	81	if (hdmi_sor(encoder))
77145f1c BS	82	nv_mask(device, 0x61c448 + or, 0x00000003, 0x00000000);
25575b41 BS	83	}
	84
	85	static void
	86	nouveau_audio_mode_set(struct drm_encoder *encoder,
	87	struct drm_display_mode *mode)
	88	{
	89	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
77145f1c	90	struct nouveau_device *device = nouveau_dev(encoder->dev);
25575b41	91	struct nouveau_connector *nv_connector;
25575b41 BS	92	u32 or = nv_encoder->or * 0x800;
	93	int i;
	94
	95	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	96	if (!drm_detect_monitor_audio(nv_connector->edid)) {
	97	nouveau_audio_disconnect(encoder);
	98	return;
	99	}
	100
	101	if (hdmi_sor(encoder)) {
77145f1c	102	nv_mask(device, 0x61c448 + or, 0x00000001, 0x00000001);
25575b41 BS	103
	104	drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
	105	if (nv_connector->base.eld[0]) {
	106	u8 *eld = nv_connector->base.eld;
	107	for (i = 0; i < eld[2] * 4; i++)
77145f1c	108	nv_wr32(device, 0x61c440 + or, (i << 8) \| eld[i]);
25575b41	109	for (i = eld[2] * 4; i < 0x60; i++)
77145f1c BS	110	nv_wr32(device, 0x61c440 + or, (i << 8) \| 0x00);
77145f1c BS	111	nv_mask(device, 0x61c448 + or, 0x00000002, 0x00000002);
25575b41 BS	112	}
	113	}
	114	}
	115
b2337f23 BS	116	static void
	117	nouveau_hdmi_infoframe(struct drm_encoder encoder, u32 ctrl, u8 frame)
	118	{
	119	/* calculate checksum for the infoframe */
	120	u8 sum = 0, i;
	121	for (i = 0; i < frame[2]; i++)
	122	sum += frame[i];
	123	frame[3] = 256 - sum;
	124
	125	/* disable infoframe, and write header */
	126	hdmi_mask(encoder, ctrl + 0x00, 0x00000001, 0x00000000);
	127	hdmi_wr32(encoder, ctrl + 0x08, (u32 )frame & 0xffffff);
	128
	129	/* register scans tell me the audio infoframe has only one set of
	130	* subpack regs, according to tegra (gee nvidia, it'd be nice if we
	131	* could get those docs too!), the hdmi block pads out the rest of
	132	* the packet on its own.
	133	*/
	134	if (ctrl == 0x020)
	135	frame[2] = 6;
	136
	137	/* write out checksum and data, weird weird 7 byte register pairs */
	138	for (i = 0; i < frame[2] + 1; i += 7) {
	139	u32 rsubpack = ctrl + 0x0c + ((i / 7) * 8);
	140	u32 subpack = (u32 )&frame[3 + i];
	141	hdmi_wr32(encoder, rsubpack + 0, subpack[0]);
	142	hdmi_wr32(encoder, rsubpack + 4, subpack[1] & 0xffffff);
	143	}
	144
	145	/* enable the infoframe */
	146	hdmi_mask(encoder, ctrl, 0x00000001, 0x00000001);
	147	}
	148
	149	static void
	150	nouveau_hdmi_video_infoframe(struct drm_encoder *encoder,
	151	struct drm_display_mode *mode)
	152	{
	153	const u8 Y = 0, A = 0, B = 0, S = 0, C = 0, M = 0, R = 0;
	154	const u8 ITC = 0, EC = 0, Q = 0, SC = 0, VIC = 0, PR = 0;
	155	const u8 bar_top = 0, bar_bottom = 0, bar_left = 0, bar_right = 0;
	156	u8 frame[20];
	157
	158	frame[0x00] = 0x82; /* AVI infoframe */
	159	frame[0x01] = 0x02; /* version */
	160	frame[0x02] = 0x0d; /* length */
	161	frame[0x03] = 0x00;
	162	frame[0x04] = (Y << 5) \| (A << 4) \| (B << 2) \| S;
	163	frame[0x05] = (C << 6) \| (M << 4) \| R;
	164	frame[0x06] = (ITC << 7) \| (EC << 4) \| (Q << 2) \| SC;
	165	frame[0x07] = VIC;
	166	frame[0x08] = PR;
	167	frame[0x09] = bar_top & 0xff;
	168	frame[0x0a] = bar_top >> 8;
	169	frame[0x0b] = bar_bottom & 0xff;
	170	frame[0x0c] = bar_bottom >> 8;
	171	frame[0x0d] = bar_left & 0xff;
	172	frame[0x0e] = bar_left >> 8;
	173	frame[0x0f] = bar_right & 0xff;
	174	frame[0x10] = bar_right >> 8;
	175	frame[0x11] = 0x00;
	176	frame[0x12] = 0x00;
	177	frame[0x13] = 0x00;
	178
	179	nouveau_hdmi_infoframe(encoder, 0x020, frame);
180	}
181
182	static void
183	nouveau_hdmi_audio_infoframe(struct drm_encoder *encoder,
184	struct drm_display_mode *mode)
185	{
186	const u8 CT = 0x00, CC = 0x01, ceaSS = 0x00, SF = 0x00, FMT = 0x00;
187	const u8 CA = 0x00, DM_INH = 0, LSV = 0x00;
188	u8 frame[12];
189
190	frame[0x00] = 0x84; /* Audio infoframe */
191	frame[0x01] = 0x01; /* version */
192	frame[0x02] = 0x0a; /* length */
193	frame[0x03] = 0x00;
194	frame[0x04] = (CT << 4) \| CC;
195	frame[0x05] = (SF << 2) \| ceaSS;
196	frame[0x06] = FMT;
197	frame[0x07] = CA;
198	frame[0x08] = (DM_INH << 7) \| (LSV << 3);
199	frame[0x09] = 0x00;
200	frame[0x0a] = 0x00;
201	frame[0x0b] = 0x00;
202
203	nouveau_hdmi_infoframe(encoder, 0x000, frame);
204	}
205
25575b41 BS	206	static void
	207	nouveau_hdmi_disconnect(struct drm_encoder *encoder)
	208	{
	209	nouveau_audio_disconnect(encoder);
b2337f23 BS	210
	211	/* disable audio and avi infoframes */
	212	hdmi_mask(encoder, 0x000, 0x00000001, 0x00000000);
	213	hdmi_mask(encoder, 0x020, 0x00000001, 0x00000000);
	214
	215	/* disable hdmi */
	216	hdmi_mask(encoder, 0x0a4, 0x40000000, 0x00000000);
25575b41 BS	217	}
	218
	219	void
	220	nouveau_hdmi_mode_set(struct drm_encoder *encoder,
	221	struct drm_display_mode *mode)
	222	{
77145f1c	223	struct nouveau_device *device = nouveau_dev(encoder->dev);
25575b41 BS	224	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
25575b41 BS	225	struct nouveau_connector *nv_connector;
50a01fe0	226	u32 max_ac_packet, rekey;
25575b41 BS	227
	228	nv_connector = nouveau_encoder_connector_get(nv_encoder);
	229	if (!mode \|\| !nv_connector \|\| !nv_connector->edid \|\|
	230	!drm_detect_hdmi_monitor(nv_connector->edid)) {
	231	nouveau_hdmi_disconnect(encoder);
	232	return;
	233	}
	234
b2337f23 BS	235	nouveau_hdmi_video_infoframe(encoder, mode);
	236	nouveau_hdmi_audio_infoframe(encoder, mode);
	237
50a01fe0 BS	238	hdmi_mask(encoder, 0x0d0, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
	239	hdmi_mask(encoder, 0x068, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
	240	hdmi_mask(encoder, 0x078, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
	241
77145f1c BS	242	nv_mask(device, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
	243	nv_mask(device, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
	244	nv_mask(device, 0x61733c, 0x00100000, 0x00000000); /* !RESETF */
50a01fe0 BS	245
	246	/* value matches nvidia binary driver, and tegra constant */
	247	rekey = 56;
	248
	249	max_ac_packet = mode->htotal - mode->hdisplay;
	250	max_ac_packet -= rekey;
	251	max_ac_packet -= 18; /* constant from tegra */
	252	max_ac_packet /= 32;
	253
	254	/* enable hdmi */
	255	hdmi_mask(encoder, 0x0a4, 0x5f1f003f, 0x40000000 \| /* enable */
	256	0x1f000000 \| /* unknown */
	257	max_ac_packet << 16 \|
	258	rekey);
	259
25575b41 BS	260	nouveau_audio_mode_set(encoder, mode);
25575b41 BS	261	}