projects / GitHub / mt8127 / android_kernel_alcatel_ttab.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/nv20: Add Z compression support.
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nouveau_drv.h
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005 Stephane Marchesin.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef __NOUVEAU_DRV_H__
26#define __NOUVEAU_DRV_H__
27
28#define DRIVER_AUTHOR "Stephane Marchesin"
29#define DRIVER_EMAIL "dri-devel@lists.sourceforge.net"
30
31#define DRIVER_NAME "nouveau"
32#define DRIVER_DESC "nVidia Riva/TNT/GeForce"
33#define DRIVER_DATE "20090420"
34
35#define DRIVER_MAJOR 0
36#define DRIVER_MINOR 0
a1606a95 37#define DRIVER_PATCHLEVEL 16
6ee73861
BS		 38
39#define NOUVEAU_FAMILY 0x0000FFFF
40#define NOUVEAU_FLAGS 0xFFFF0000
41
42#include "ttm/ttm_bo_api.h"
43#include "ttm/ttm_bo_driver.h"
44#include "ttm/ttm_placement.h"
45#include "ttm/ttm_memory.h"
46#include "ttm/ttm_module.h"
47
48struct nouveau_fpriv {
49 struct ttm_object_file *tfile;
50};
51
52#define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
53
54#include "nouveau_drm.h"
55#include "nouveau_reg.h"
56#include "nouveau_bios.h"
054b93e4 57struct nouveau_grctx;
6ee73861
BS		 58
59#define MAX_NUM_DCB_ENTRIES 16
60
61#define NOUVEAU_MAX_CHANNEL_NR 128
a0af9add 62#define NOUVEAU_MAX_TILE_NR 15
6ee73861
BS		 63
64#define NV50_VM_MAX_VRAM (2*1024*1024*1024ULL)
65#define NV50_VM_BLOCK (512*1024*1024ULL)
66#define NV50_VM_VRAM_NR (NV50_VM_MAX_VRAM / NV50_VM_BLOCK)
67
a0af9add 68struct nouveau_tile_reg {
a0af9add 69 bool used;
a5cf68b0
FJ		 70 uint32_t addr;
71 uint32_t limit;
72 uint32_t pitch;
87a326a3
FJ		 73 uint32_t zcomp;
74 struct drm_mm_node *tag_mem;
a5cf68b0 75 struct nouveau_fence *fence;
a0af9add
FJ		 76};
77
6ee73861
BS		 78struct nouveau_bo {
79 struct ttm_buffer_object bo;
80 struct ttm_placement placement;
81 u32 placements[3];
78ad0f7b 82 u32 busy_placements[3];
6ee73861
BS		 83 struct ttm_bo_kmap_obj kmap;
84 struct list_head head;
85
86 /* protected by ttm_bo_reserve() */
87 struct drm_file *reserved_by;
88 struct list_head entry;
89 int pbbo_index;
a1606a95 90 bool validate_mapped;
6ee73861
BS		 91
92 struct nouveau_channel *channel;
93
94 bool mappable;
95 bool no_vm;
96
97 uint32_t tile_mode;
98 uint32_t tile_flags;
a0af9add 99 struct nouveau_tile_reg *tile;
6ee73861
BS		 100
101 struct drm_gem_object *gem;
6ee73861
BS		 102 int pin_refcnt;
103};
104
f13b3263
FJ		 105#define nouveau_bo_tile_layout(nvbo) \
106 ((nvbo)->tile_flags & NOUVEAU_GEM_TILE_LAYOUT_MASK)
107
6ee73861
BS		 108static inline struct nouveau_bo *
109nouveau_bo(struct ttm_buffer_object *bo)
110{
111 return container_of(bo, struct nouveau_bo, bo);
112}
113
114static inline struct nouveau_bo *
115nouveau_gem_object(struct drm_gem_object *gem)
116{
117 return gem ? gem->driver_private : NULL;
118}
119
120/* TODO: submit equivalent to TTM generic API upstream? */
121static inline void __iomem *
122nvbo_kmap_obj_iovirtual(struct nouveau_bo *nvbo)
123{
124 bool is_iomem;
125 void __iomem *ioptr = (void __force __iomem *)ttm_kmap_obj_virtual(
126 &nvbo->kmap, &is_iomem);
127 WARN_ON_ONCE(ioptr && !is_iomem);
128 return ioptr;
129}
130
6ee73861
BS		 131enum nouveau_flags {
132 NV_NFORCE = 0x10000000,
133 NV_NFORCE2 = 0x20000000
134};
135
136#define NVOBJ_ENGINE_SW 0
137#define NVOBJ_ENGINE_GR 1
bd2e597d
BS		 138#define NVOBJ_ENGINE_PPP 2
139#define NVOBJ_ENGINE_COPY 3
140#define NVOBJ_ENGINE_VP 4
141#define NVOBJ_ENGINE_CRYPT 5
142#define NVOBJ_ENGINE_BSP 6
50536946 143#define NVOBJ_ENGINE_DISPLAY 0xcafe0001
6ee73861
BS		 144#define NVOBJ_ENGINE_INT 0xdeadbeef
145
6ee73861
BS		 146#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
147#define NVOBJ_FLAG_ZERO_FREE (1 << 2)
6ee73861 148struct nouveau_gpuobj {
b3beb167 149 struct drm_device *dev;
eb9bcbdc 150 struct kref refcount;
6ee73861
BS		 151 struct list_head list;
152
b833ac26 153 struct drm_mm_node *im_pramin;
6ee73861 154 struct nouveau_bo *im_backing;
6ee73861
BS		 155 uint32_t *im_backing_suspend;
156 int im_bound;
157
158 uint32_t flags;
6ee73861 159
43efc9ce 160 u32 size;
de3a6c0a
BS		 161 u32 pinst;
162 u32 cinst;
163 u64 vinst;
164
6ee73861
BS		 165 uint32_t engine;
166 uint32_t class;
167
168 void (*dtor)(struct drm_device *, struct nouveau_gpuobj *);
169 void *priv;
170};
171
332b242f
FJ		 172struct nouveau_page_flip_state {
173 struct list_head head;
174 struct drm_pending_vblank_event *event;
175 int crtc, bpp, pitch, x, y;
176 uint64_t offset;
177};
178
e419cf09
FJ		 179enum nouveau_channel_mutex_class {
180 NOUVEAU_UCHANNEL_MUTEX,
181 NOUVEAU_KCHANNEL_MUTEX
182};
183
6ee73861
BS		 184struct nouveau_channel {
185 struct drm_device *dev;
186 int id;
187
f091a3d4
FJ		 188 /* references to the channel data structure */
189 struct kref ref;
190 /* users of the hardware channel resources, the hardware
191 * context will be kicked off when it reaches zero. */
192 atomic_t users;
6a6b73f2
BS		 193 struct mutex mutex;
194
6ee73861
BS		 195 /* owner of this fifo */
196 struct drm_file *file_priv;
197 /* mapping of the fifo itself */
198 struct drm_local_map *map;
199
200 /* mapping of the regs controling the fifo */
201 void __iomem *user;
202 uint32_t user_get;
203 uint32_t user_put;
204
205 /* Fencing */
206 struct {
207 /* lock protects the pending list only */
208 spinlock_t lock;
209 struct list_head pending;
210 uint32_t sequence;
211 uint32_t sequence_ack;
047d1d3c 212 atomic_t last_sequence_irq;
6ee73861
BS		 213 } fence;
214
215 /* DMA push buffer */
a8eaebc6
BS		 216 struct nouveau_gpuobj *pushbuf;
217 struct nouveau_bo *pushbuf_bo;
218 uint32_t pushbuf_base;
6ee73861
BS		 219
220 /* Notifier memory */
221 struct nouveau_bo *notifier_bo;
b833ac26 222 struct drm_mm notifier_heap;
6ee73861
BS		 223
224 /* PFIFO context */
a8eaebc6
BS		 225 struct nouveau_gpuobj *ramfc;
226 struct nouveau_gpuobj *cache;
6ee73861
BS		 227
228 /* PGRAPH context */
229 /* XXX may be merge 2 pointers as private data ??? */
a8eaebc6 230 struct nouveau_gpuobj *ramin_grctx;
bd2e597d 231 struct nouveau_gpuobj *crypt_ctx;
6ee73861
BS		 232 void *pgraph_ctx;
233
234 /* NV50 VM */
a8eaebc6
BS		 235 struct nouveau_gpuobj *vm_pd;
236 struct nouveau_gpuobj *vm_gart_pt;
237 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
6ee73861
BS		 238
239 /* Objects */
a8eaebc6
BS		 240 struct nouveau_gpuobj *ramin; /* Private instmem */
241 struct drm_mm ramin_heap; /* Private PRAMIN heap */
242 struct nouveau_ramht *ramht; /* Hash table */
6ee73861
BS		 243
244 /* GPU object info for stuff used in-kernel (mm_enabled) */
245 uint32_t m2mf_ntfy;
246 uint32_t vram_handle;
247 uint32_t gart_handle;
248 bool accel_done;
249
250 /* Push buffer state (only for drm's channel on !mm_enabled) */
251 struct {
252 int max;
253 int free;
254 int cur;
255 int put;
256 /* access via pushbuf_bo */
9a391ad8
BS		 257
258 int ib_base;
259 int ib_max;
260 int ib_free;
261 int ib_put;
6ee73861
BS		 262 } dma;
263
264 uint32_t sw_subchannel[8];
265
266 struct {
267 struct nouveau_gpuobj *vblsem;
1f6d2de2 268 uint32_t vblsem_head;
6ee73861
BS		 269 uint32_t vblsem_offset;
270 uint32_t vblsem_rval;
271 struct list_head vbl_wait;
332b242f 272 struct list_head flip;
6ee73861
BS		 273 } nvsw;
274
275 struct {
276 bool active;
277 char name[32];
278 struct drm_info_list info;
279 } debugfs;
280};
281
282struct nouveau_instmem_engine {
283 void *priv;
284
285 int (*init)(struct drm_device *dev);
286 void (*takedown)(struct drm_device *dev);
287 int (*suspend)(struct drm_device *dev);
288 void (*resume)(struct drm_device *dev);
289
290 int (*populate)(struct drm_device *, struct nouveau_gpuobj *,
9100468d 291 u32 *size, u32 align);
6ee73861
BS		 292 void (*clear)(struct drm_device *, struct nouveau_gpuobj *);
293 int (*bind)(struct drm_device *, struct nouveau_gpuobj *);
294 int (*unbind)(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 295 void (*flush)(struct drm_device *);
6ee73861
BS		 296};
297
298struct nouveau_mc_engine {
299 int (*init)(struct drm_device *dev);
300 void (*takedown)(struct drm_device *dev);
301};
302
303struct nouveau_timer_engine {
304 int (*init)(struct drm_device *dev);
305 void (*takedown)(struct drm_device *dev);
306 uint64_t (*read)(struct drm_device *dev);
307};
308
309struct nouveau_fb_engine {
cb00f7c1 310 int num_tiles;
87a326a3 311 struct drm_mm tag_heap;
cb00f7c1 312
6ee73861
BS		 313 int (*init)(struct drm_device *dev);
314 void (*takedown)(struct drm_device *dev);
cb00f7c1 315
a5cf68b0
FJ		 316 void (*init_tile_region)(struct drm_device *dev, int i,
317 uint32_t addr, uint32_t size,
318 uint32_t pitch, uint32_t flags);
319 void (*set_tile_region)(struct drm_device *dev, int i);
320 void (*free_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 321};
322
323struct nouveau_fifo_engine {
6ee73861
BS		 324 int channels;
325
a8eaebc6 326 struct nouveau_gpuobj *playlist[2];
ac94a343
BS		 327 int cur_playlist;
328
6ee73861
BS		 329 int (*init)(struct drm_device *);
330 void (*takedown)(struct drm_device *);
331
332 void (*disable)(struct drm_device *);
333 void (*enable)(struct drm_device *);
334 bool (*reassign)(struct drm_device *, bool enable);
588d7d12 335 bool (*cache_pull)(struct drm_device *dev, bool enable);
6ee73861
BS		 336
337 int (*channel_id)(struct drm_device *);
338
339 int (*create_context)(struct nouveau_channel *);
340 void (*destroy_context)(struct nouveau_channel *);
341 int (*load_context)(struct nouveau_channel *);
342 int (*unload_context)(struct drm_device *);
56ac7475 343 void (*tlb_flush)(struct drm_device *dev);
6ee73861
BS		 344};
345
6ee73861 346struct nouveau_pgraph_engine {
6ee73861 347 bool accel_blocked;
b8c157d3 348 bool registered;
054b93e4 349 int grctx_size;
6ee73861 350
c50a5681 351 /* NV2x/NV3x context table (0x400780) */
a8eaebc6 352 struct nouveau_gpuobj *ctx_table;
c50a5681 353
6ee73861
BS		 354 int (*init)(struct drm_device *);
355 void (*takedown)(struct drm_device *);
356
357 void (*fifo_access)(struct drm_device *, bool);
358
359 struct nouveau_channel *(*channel)(struct drm_device *);
360 int (*create_context)(struct nouveau_channel *);
361 void (*destroy_context)(struct nouveau_channel *);
362 int (*load_context)(struct nouveau_channel *);
363 int (*unload_context)(struct drm_device *);
56ac7475 364 void (*tlb_flush)(struct drm_device *dev);
cb00f7c1 365
a5cf68b0 366 void (*set_tile_region)(struct drm_device *dev, int i);
6ee73861
BS		 367};
368
c88c2e06
FJ		 369struct nouveau_display_engine {
370 int (*early_init)(struct drm_device *);
371 void (*late_takedown)(struct drm_device *);
372 int (*create)(struct drm_device *);
373 int (*init)(struct drm_device *);
374 void (*destroy)(struct drm_device *);
375};
376
ee2e0131
BS		 377struct nouveau_gpio_engine {
378 int (*init)(struct drm_device *);
379 void (*takedown)(struct drm_device *);
380
381 int (*get)(struct drm_device *, enum dcb_gpio_tag);
382 int (*set)(struct drm_device *, enum dcb_gpio_tag, int state);
383
384 void (*irq_enable)(struct drm_device *, enum dcb_gpio_tag, bool on);
385};
386
330c5988
BS		 387struct nouveau_pm_voltage_level {
388 u8 voltage;
389 u8 vid;
390};
391
392struct nouveau_pm_voltage {
393 bool supported;
394 u8 vid_mask;
395
396 struct nouveau_pm_voltage_level *level;
397 int nr_level;
398};
399
400#define NOUVEAU_PM_MAX_LEVEL 8
401struct nouveau_pm_level {
402 struct device_attribute dev_attr;
403 char name[32];
404 int id;
405
406 u32 core;
407 u32 memory;
408 u32 shader;
409 u32 unk05;
410
411 u8 voltage;
412 u8 fanspeed;
aee582de
BS		 413
414 u16 memscript;
330c5988
BS		 415};
416
34e9d85a
MP		 417struct nouveau_pm_temp_sensor_constants {
418 u16 offset_constant;
419 s16 offset_mult;
420 u16 offset_div;
421 u16 slope_mult;
422 u16 slope_div;
423};
424
425struct nouveau_pm_threshold_temp {
426 s16 critical;
427 s16 down_clock;
428 s16 fan_boost;
429};
430
7760fcb0
RS		 431struct nouveau_pm_memtiming {
432 u32 reg_100220;
433 u32 reg_100224;
434 u32 reg_100228;
435 u32 reg_10022c;
436 u32 reg_100230;
437 u32 reg_100234;
438 u32 reg_100238;
439 u32 reg_10023c;
440};
441
442struct nouveau_pm_memtimings {
443 bool supported;
444 struct nouveau_pm_memtiming *timing;
445 int nr_timing;
446};
447
330c5988
BS		 448struct nouveau_pm_engine {
449 struct nouveau_pm_voltage voltage;
450 struct nouveau_pm_level perflvl[NOUVEAU_PM_MAX_LEVEL];
451 int nr_perflvl;
7760fcb0 452 struct nouveau_pm_memtimings memtimings;
34e9d85a
MP		 453 struct nouveau_pm_temp_sensor_constants sensor_constants;
454 struct nouveau_pm_threshold_temp threshold_temp;
330c5988
BS		 455
456 struct nouveau_pm_level boot;
457 struct nouveau_pm_level *cur;
458
8155cac4 459 struct device *hwmon;
6032649d 460 struct notifier_block acpi_nb;
8155cac4 461
330c5988 462 int (*clock_get)(struct drm_device *, u32 id);
5c6dc657
BS		 463 void *(*clock_pre)(struct drm_device *, struct nouveau_pm_level *,
464 u32 id, int khz);
330c5988
BS		 465 void (*clock_set)(struct drm_device *, void *);
466 int (*voltage_get)(struct drm_device *);
467 int (*voltage_set)(struct drm_device *, int voltage);
468 int (*fanspeed_get)(struct drm_device *);
469 int (*fanspeed_set)(struct drm_device *, int fanspeed);
8155cac4 470 int (*temp_get)(struct drm_device *);
330c5988
BS		 471};
472
bd2e597d
BS		 473struct nouveau_crypt_engine {
474 bool registered;
475
476 int (*init)(struct drm_device *);
477 void (*takedown)(struct drm_device *);
478 int (*create_context)(struct nouveau_channel *);
479 void (*destroy_context)(struct nouveau_channel *);
480 void (*tlb_flush)(struct drm_device *dev);
481};
482
6ee73861
BS		 483struct nouveau_engine {
484 struct nouveau_instmem_engine instmem;
485 struct nouveau_mc_engine mc;
486 struct nouveau_timer_engine timer;
487 struct nouveau_fb_engine fb;
488 struct nouveau_pgraph_engine graph;
489 struct nouveau_fifo_engine fifo;
c88c2e06 490 struct nouveau_display_engine display;
ee2e0131 491 struct nouveau_gpio_engine gpio;
330c5988 492 struct nouveau_pm_engine pm;
bd2e597d 493 struct nouveau_crypt_engine crypt;
6ee73861
BS		 494};
495
496struct nouveau_pll_vals {
497 union {
498 struct {
499#ifdef __BIG_ENDIAN
500 uint8_t N1, M1, N2, M2;
501#else
502 uint8_t M1, N1, M2, N2;
503#endif
504 };
505 struct {
506 uint16_t NM1, NM2;
507 } __attribute__((packed));
508 };
509 int log2P;
510
511 int refclk;
512};
513
514enum nv04_fp_display_regs {
515 FP_DISPLAY_END,
516 FP_TOTAL,
517 FP_CRTC,
518 FP_SYNC_START,
519 FP_SYNC_END,
520 FP_VALID_START,
521 FP_VALID_END
522};
523
524struct nv04_crtc_reg {
cbab95db 525 unsigned char MiscOutReg;
4a9f822f 526 uint8_t CRTC[0xa0];
6ee73861
BS		 527 uint8_t CR58[0x10];
528 uint8_t Sequencer[5];
529 uint8_t Graphics[9];
530 uint8_t Attribute[21];
cbab95db 531 unsigned char DAC[768];
6ee73861
BS		 532
533 /* PCRTC regs */
534 uint32_t fb_start;
535 uint32_t crtc_cfg;
536 uint32_t cursor_cfg;
537 uint32_t gpio_ext;
538 uint32_t crtc_830;
539 uint32_t crtc_834;
540 uint32_t crtc_850;
541 uint32_t crtc_eng_ctrl;
542
543 /* PRAMDAC regs */
544 uint32_t nv10_cursync;
545 struct nouveau_pll_vals pllvals;
546 uint32_t ramdac_gen_ctrl;
547 uint32_t ramdac_630;
548 uint32_t ramdac_634;
549 uint32_t tv_setup;
550 uint32_t tv_vtotal;
551 uint32_t tv_vskew;
552 uint32_t tv_vsync_delay;
553 uint32_t tv_htotal;
554 uint32_t tv_hskew;
555 uint32_t tv_hsync_delay;
556 uint32_t tv_hsync_delay2;
557 uint32_t fp_horiz_regs[7];
558 uint32_t fp_vert_regs[7];
559 uint32_t dither;
560 uint32_t fp_control;
561 uint32_t dither_regs[6];
562 uint32_t fp_debug_0;
563 uint32_t fp_debug_1;
564 uint32_t fp_debug_2;
565 uint32_t fp_margin_color;
566 uint32_t ramdac_8c0;
567 uint32_t ramdac_a20;
568 uint32_t ramdac_a24;
569 uint32_t ramdac_a34;
570 uint32_t ctv_regs[38];
571};
572
573struct nv04_output_reg {
574 uint32_t output;
575 int head;
576};
577
578struct nv04_mode_state {
cbab95db 579 struct nv04_crtc_reg crtc_reg[2];
6ee73861
BS		 580 uint32_t pllsel;
581 uint32_t sel_clk;
6ee73861
BS		 582};
583
584enum nouveau_card_type {
585 NV_04 = 0x00,
586 NV_10 = 0x10,
587 NV_20 = 0x20,
588 NV_30 = 0x30,
589 NV_40 = 0x40,
590 NV_50 = 0x50,
4b223eef 591 NV_C0 = 0xc0,
6ee73861
BS		 592};
593
594struct drm_nouveau_private {
595 struct drm_device *dev;
6ee73861
BS		 596
597 /* the card type, takes NV_* as values */
598 enum nouveau_card_type card_type;
599 /* exact chipset, derived from NV_PMC_BOOT_0 */
600 int chipset;
601 int flags;
602
603 void __iomem *mmio;
5125bfd8 604
e05d7eae 605 spinlock_t ramin_lock;
6ee73861 606 void __iomem *ramin;
5125bfd8
BS		 607 u32 ramin_size;
608 u32 ramin_base;
609 bool ramin_available;
e05d7eae
BS		 610 struct drm_mm ramin_heap;
611 struct list_head gpuobj_list;
b8c157d3 612 struct list_head classes;
6ee73861 613
ac8fb975
BS		 614 struct nouveau_bo *vga_ram;
615
35fa2f2a
BS		 616 /* interrupt handling */
617 bool msi_enabled;
6ee73861
BS		 618 struct workqueue_struct *wq;
619 struct work_struct irq_work;
a5acac66 620 struct work_struct hpd_work;
6ee73861 621
ab838338
AL		 622 struct {
623 spinlock_t lock;
624 uint32_t hpd0_bits;
625 uint32_t hpd1_bits;
626 } hpd_state;
627
6ee73861
BS		 628 struct list_head vbl_waiting;
629
630 struct {
ba4420c2 631 struct drm_global_reference mem_global_ref;
6ee73861
BS		 632 struct ttm_bo_global_ref bo_global_ref;
633 struct ttm_bo_device bdev;
6ee73861
BS		 634 atomic_t validate_sequence;
635 } ttm;
636
0c6c1c2f
FJ		 637 struct {
638 spinlock_t lock;
639 struct drm_mm heap;
640 struct nouveau_bo *bo;
641 } fence;
642
cff5c133
BS		 643 struct {
644 spinlock_t lock;
645 struct nouveau_channel *ptr[NOUVEAU_MAX_CHANNEL_NR];
646 } channels;
6ee73861
BS		 647
648 struct nouveau_engine engine;
649 struct nouveau_channel *channel;
650
ff9e5279
MM		 651 /* For PFIFO and PGRAPH. */
652 spinlock_t context_switch_lock;
653
6ee73861 654 /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
e05c5a31
BS		 655 struct nouveau_ramht *ramht;
656 struct nouveau_gpuobj *ramfc;
657 struct nouveau_gpuobj *ramro;
658
6ee73861 659 uint32_t ramin_rsvd_vram;
6ee73861 660
6ee73861
BS		 661 struct {
662 enum {
663 NOUVEAU_GART_NONE = 0,
664 NOUVEAU_GART_AGP,
665 NOUVEAU_GART_SGDMA
666 } type;
667 uint64_t aper_base;
668 uint64_t aper_size;
669 uint64_t aper_free;
670
671 struct nouveau_gpuobj *sg_ctxdma;
672 struct page *sg_dummy_page;
673 dma_addr_t sg_dummy_bus;
6ee73861
BS		 674 } gart_info;
675
a0af9add 676 /* nv10-nv40 tiling regions */
a5cf68b0
FJ		 677 struct {
678 struct nouveau_tile_reg reg[NOUVEAU_MAX_TILE_NR];
679 spinlock_t lock;
680 } tile;
a0af9add 681
a76fb4e8
BS		 682 /* VRAM/fb configuration */
683 uint64_t vram_size;
684 uint64_t vram_sys_base;
6c3d7ef2 685 u32 vram_rblock_size;
a76fb4e8
BS		 686
687 uint64_t fb_phys;
688 uint64_t fb_available_size;
689 uint64_t fb_mappable_pages;
690 uint64_t fb_aper_free;
691 int fb_mtrr;
692
6ee73861
BS		 693 /* G8x/G9x virtual address space */
694 uint64_t vm_gart_base;
695 uint64_t vm_gart_size;
696 uint64_t vm_vram_base;
697 uint64_t vm_vram_size;
698 uint64_t vm_end;
699 struct nouveau_gpuobj *vm_vram_pt[NV50_VM_VRAM_NR];
700 int vm_vram_pt_nr;
6ee73861 701
04a39c57 702 struct nvbios vbios;
6ee73861
BS		 703
704 struct nv04_mode_state mode_reg;
705 struct nv04_mode_state saved_reg;
706 uint32_t saved_vga_font[4][16384];
707 uint32_t crtc_owner;
708 uint32_t dac_users[4];
709
710 struct nouveau_suspend_resume {
6ee73861 711 uint32_t *ramin_copy;
6ee73861
BS		 712 } susres;
713
714 struct backlight_device *backlight;
6ee73861
BS		 715
716 struct nouveau_channel *evo;
1e96268a 717 u32 evo_alloc;
87c0e0e5
BS		 718 struct {
719 struct dcb_entry *dcb;
720 u16 script;
721 u32 pclk;
722 } evo_irq;
6ee73861
BS		 723
724 struct {
725 struct dentry *channel_root;
726 } debugfs;
38651674 727
8be48d92 728 struct nouveau_fbdev *nfbdev;
06415c56 729 struct apertures_struct *apertures;
6ee73861
BS		 730};
731
2730723b
FJ		 732static inline struct drm_nouveau_private *
733nouveau_private(struct drm_device *dev)
734{
735 return dev->dev_private;
736}
737
6ee73861
BS		 738static inline struct drm_nouveau_private *
739nouveau_bdev(struct ttm_bo_device *bd)
740{
741 return container_of(bd, struct drm_nouveau_private, ttm.bdev);
742}
743
744static inline int
745nouveau_bo_ref(struct nouveau_bo *ref, struct nouveau_bo **pnvbo)
746{
747 struct nouveau_bo *prev;
748
749 if (!pnvbo)
750 return -EINVAL;
751 prev = *pnvbo;
752
753 *pnvbo = ref ? nouveau_bo(ttm_bo_reference(&ref->bo)) : NULL;
754 if (prev) {
755 struct ttm_buffer_object *bo = &prev->bo;
756
757 ttm_bo_unref(&bo);
758 }
759
760 return 0;
761}
762
6ee73861 763/* nouveau_drv.c */
de5899bd 764extern int nouveau_agpmode;
6ee73861
BS		 765extern int nouveau_duallink;
766extern int nouveau_uscript_lvds;
767extern int nouveau_uscript_tmds;
768extern int nouveau_vram_pushbuf;
769extern int nouveau_vram_notify;
770extern int nouveau_fbpercrtc;
f4053509 771extern int nouveau_tv_disable;
6ee73861
BS		 772extern char *nouveau_tv_norm;
773extern int nouveau_reg_debug;
774extern char *nouveau_vbios;
a1470890 775extern int nouveau_ignorelid;
a32ed69d
MK		 776extern int nouveau_nofbaccel;
777extern int nouveau_noaccel;
0cba1b76 778extern int nouveau_force_post;
da647d5b 779extern int nouveau_override_conntype;
6f876986
BS		 780extern char *nouveau_perflvl;
781extern int nouveau_perflvl_wr;
35fa2f2a 782extern int nouveau_msi;
6ee73861 783
6a9ee8af
DA		 784extern int nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state);
785extern int nouveau_pci_resume(struct pci_dev *pdev);
786
6ee73861
BS		 787/* nouveau_state.c */
788extern void nouveau_preclose(struct drm_device *dev, struct drm_file *);
789extern int nouveau_load(struct drm_device *, unsigned long flags);
790extern int nouveau_firstopen(struct drm_device *);
791extern void nouveau_lastclose(struct drm_device *);
792extern int nouveau_unload(struct drm_device *);
793extern int nouveau_ioctl_getparam(struct drm_device *, void *data,
794 struct drm_file *);
795extern int nouveau_ioctl_setparam(struct drm_device *, void *data,
796 struct drm_file *);
797extern bool nouveau_wait_until(struct drm_device *, uint64_t timeout,
798 uint32_t reg, uint32_t mask, uint32_t val);
799extern bool nouveau_wait_for_idle(struct drm_device *);
800extern int nouveau_card_init(struct drm_device *);
6ee73861
BS		 801
802/* nouveau_mem.c */
fbd2895e
BS		 803extern int nouveau_mem_vram_init(struct drm_device *);
804extern void nouveau_mem_vram_fini(struct drm_device *);
805extern int nouveau_mem_gart_init(struct drm_device *);
806extern void nouveau_mem_gart_fini(struct drm_device *);
6ee73861 807extern int nouveau_mem_init_agp(struct drm_device *);
e04d8e82 808extern int nouveau_mem_reset_agp(struct drm_device *);
6ee73861 809extern void nouveau_mem_close(struct drm_device *);
a5cf68b0
FJ		 810extern struct nouveau_tile_reg *nv10_mem_set_tiling(
811 struct drm_device *dev, uint32_t addr, uint32_t size,
812 uint32_t pitch, uint32_t flags);
813extern void nv10_mem_put_tile_region(struct drm_device *dev,
814 struct nouveau_tile_reg *tile,
815 struct nouveau_fence *fence);
6ee73861
BS		 816extern int nv50_mem_vm_bind_linear(struct drm_device *, uint64_t virt,
817 uint32_t size, uint32_t flags,
818 uint64_t phys);
819extern void nv50_mem_vm_unbind(struct drm_device *, uint64_t virt,
820 uint32_t size);
821
822/* nouveau_notifier.c */
823extern int nouveau_notifier_init_channel(struct nouveau_channel *);
824extern void nouveau_notifier_takedown_channel(struct nouveau_channel *);
825extern int nouveau_notifier_alloc(struct nouveau_channel *, uint32_t handle,
826 int cout, uint32_t *offset);
827extern int nouveau_notifier_offset(struct nouveau_gpuobj *, uint32_t *);
828extern int nouveau_ioctl_notifier_alloc(struct drm_device *, void *data,
829 struct drm_file *);
830extern int nouveau_ioctl_notifier_free(struct drm_device *, void *data,
831 struct drm_file *);
832
833/* nouveau_channel.c */
834extern struct drm_ioctl_desc nouveau_ioctls[];
835extern int nouveau_max_ioctl;
836extern void nouveau_channel_cleanup(struct drm_device *, struct drm_file *);
6ee73861
BS		 837extern int nouveau_channel_alloc(struct drm_device *dev,
838 struct nouveau_channel **chan,
839 struct drm_file *file_priv,
840 uint32_t fb_ctxdma, uint32_t tt_ctxdma);
cff5c133 841extern struct nouveau_channel *
feeb0aec
FJ		 842nouveau_channel_get_unlocked(struct nouveau_channel *);
843extern struct nouveau_channel *
cff5c133 844nouveau_channel_get(struct drm_device *, struct drm_file *, int id);
feeb0aec 845extern void nouveau_channel_put_unlocked(struct nouveau_channel **);
cff5c133 846extern void nouveau_channel_put(struct nouveau_channel **);
f091a3d4
FJ		 847extern void nouveau_channel_ref(struct nouveau_channel *chan,
848 struct nouveau_channel **pchan);
6ee73861
BS		 849
850/* nouveau_object.c */
b8c157d3
BS		 851#define NVOBJ_CLASS(d,c,e) do { \
852 int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
853 if (ret) \
854 return ret; \
855} while(0)
856
857#define NVOBJ_MTHD(d,c,m,e) do { \
858 int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
859 if (ret) \
860 return ret; \
861} while(0)
862
6ee73861
BS		 863extern int nouveau_gpuobj_early_init(struct drm_device *);
864extern int nouveau_gpuobj_init(struct drm_device *);
865extern void nouveau_gpuobj_takedown(struct drm_device *);
6ee73861
BS		 866extern int nouveau_gpuobj_suspend(struct drm_device *dev);
867extern void nouveau_gpuobj_suspend_cleanup(struct drm_device *dev);
868extern void nouveau_gpuobj_resume(struct drm_device *dev);
b8c157d3
BS		 869extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
870extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
871 int (*exec)(struct nouveau_channel *,
872 u32 class, u32 mthd, u32 data));
873extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
6ee73861
BS		 874extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
875 uint32_t vram_h, uint32_t tt_h);
876extern void nouveau_gpuobj_channel_takedown(struct nouveau_channel *);
877extern int nouveau_gpuobj_new(struct drm_device *, struct nouveau_channel *,
878 uint32_t size, int align, uint32_t flags,
879 struct nouveau_gpuobj **);
a8eaebc6
BS		 880extern void nouveau_gpuobj_ref(struct nouveau_gpuobj *,
881 struct nouveau_gpuobj **);
43efc9ce
BS		 882extern int nouveau_gpuobj_new_fake(struct drm_device *, u32 pinst, u64 vinst,
883 u32 size, u32 flags,
a8eaebc6 884 struct nouveau_gpuobj **);
6ee73861
BS		 885extern int nouveau_gpuobj_dma_new(struct nouveau_channel *, int class,
886 uint64_t offset, uint64_t size, int access,
887 int target, struct nouveau_gpuobj **);
888extern int nouveau_gpuobj_gart_dma_new(struct nouveau_channel *,
889 uint64_t offset, uint64_t size,
890 int access, struct nouveau_gpuobj **,
891 uint32_t *o_ret);
892extern int nouveau_gpuobj_gr_new(struct nouveau_channel *, int class,
893 struct nouveau_gpuobj **);
894extern int nouveau_ioctl_grobj_alloc(struct drm_device *, void *data,
895 struct drm_file *);
896extern int nouveau_ioctl_gpuobj_free(struct drm_device *, void *data,
897 struct drm_file *);
898
899/* nouveau_irq.c */
35fa2f2a
BS		 900extern int nouveau_irq_init(struct drm_device *);
901extern void nouveau_irq_fini(struct drm_device *);
6ee73861
BS		 902extern irqreturn_t nouveau_irq_handler(DRM_IRQ_ARGS);
903extern void nouveau_irq_preinstall(struct drm_device *);
904extern int nouveau_irq_postinstall(struct drm_device *);
905extern void nouveau_irq_uninstall(struct drm_device *);
906
907/* nouveau_sgdma.c */
908extern int nouveau_sgdma_init(struct drm_device *);
909extern void nouveau_sgdma_takedown(struct drm_device *);
910extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
911 uint32_t *page);
912extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
913
914/* nouveau_debugfs.c */
915#if defined(CONFIG_DRM_NOUVEAU_DEBUG)
916extern int nouveau_debugfs_init(struct drm_minor *);
917extern void nouveau_debugfs_takedown(struct drm_minor *);
918extern int nouveau_debugfs_channel_init(struct nouveau_channel *);
919extern void nouveau_debugfs_channel_fini(struct nouveau_channel *);
920#else
921static inline int
922nouveau_debugfs_init(struct drm_minor *minor)
923{
924 return 0;
925}
926
927static inline void nouveau_debugfs_takedown(struct drm_minor *minor)
928{
929}
930
931static inline int
932nouveau_debugfs_channel_init(struct nouveau_channel *chan)
933{
934 return 0;
935}
936
937static inline void
938nouveau_debugfs_channel_fini(struct nouveau_channel *chan)
939{
940}
941#endif
942
943/* nouveau_dma.c */
75c99da6 944extern void nouveau_dma_pre_init(struct nouveau_channel *);
6ee73861 945extern int nouveau_dma_init(struct nouveau_channel *);
9a391ad8 946extern int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
6ee73861
BS		 947
948/* nouveau_acpi.c */
afeb3e11 949#define ROM_BIOS_PAGE 4096
2f41a7f1 950#if defined(CONFIG_ACPI)
6a9ee8af
DA		 951void nouveau_register_dsm_handler(void);
952void nouveau_unregister_dsm_handler(void);
afeb3e11
DA		 953int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len);
954bool nouveau_acpi_rom_supported(struct pci_dev *pdev);
a6ed76d7 955int nouveau_acpi_edid(struct drm_device *, struct drm_connector *);
8edb381d
DA		 956#else
957static inline void nouveau_register_dsm_handler(void) {}
958static inline void nouveau_unregister_dsm_handler(void) {}
afeb3e11
DA		 959static inline bool nouveau_acpi_rom_supported(struct pci_dev *pdev) { return false; }
960static inline int nouveau_acpi_get_bios_chunk(uint8_t *bios, int offset, int len) { return -EINVAL; }
5620ba46 961static inline int nouveau_acpi_edid(struct drm_device *dev, struct drm_connector *connector) { return -EINVAL; }
8edb381d 962#endif
6ee73861
BS		 963
964/* nouveau_backlight.c */
965#ifdef CONFIG_DRM_NOUVEAU_BACKLIGHT
966extern int nouveau_backlight_init(struct drm_device *);
967extern void nouveau_backlight_exit(struct drm_device *);
968#else
969static inline int nouveau_backlight_init(struct drm_device *dev)
970{
971 return 0;
972}
973
974static inline void nouveau_backlight_exit(struct drm_device *dev) { }
975#endif
976
977/* nouveau_bios.c */
978extern int nouveau_bios_init(struct drm_device *);
979extern void nouveau_bios_takedown(struct drm_device *dev);
980extern int nouveau_run_vbios_init(struct drm_device *);
981extern void nouveau_bios_run_init_table(struct drm_device *, uint16_t table,
982 struct dcb_entry *);
983extern struct dcb_gpio_entry *nouveau_bios_gpio_entry(struct drm_device *,
984 enum dcb_gpio_tag);
985extern struct dcb_connector_table_entry *
986nouveau_bios_connector_entry(struct drm_device *, int index);
855a95e4 987extern u32 get_pll_register(struct drm_device *, enum pll_types);
6ee73861
BS		 988extern int get_pll_limits(struct drm_device *, uint32_t limit_match,
989 struct pll_lims *);
990extern int nouveau_bios_run_display_table(struct drm_device *,
991 struct dcb_entry *,
992 uint32_t script, int pxclk);
993extern void *nouveau_bios_dp_table(struct drm_device *, struct dcb_entry *,
994 int *length);
995extern bool nouveau_bios_fp_mode(struct drm_device *, struct drm_display_mode *);
996extern uint8_t *nouveau_bios_embedded_edid(struct drm_device *);
997extern int nouveau_bios_parse_lvds_table(struct drm_device *, int pxclk,
998 bool *dl, bool *if_is_24bit);
999extern int run_tmds_table(struct drm_device *, struct dcb_entry *,
1000 int head, int pxclk);
1001extern int call_lvds_script(struct drm_device *, struct dcb_entry *, int head,
1002 enum LVDS_script, int pxclk);
1003
1004/* nouveau_ttm.c */
1005int nouveau_ttm_global_init(struct drm_nouveau_private *);
1006void nouveau_ttm_global_release(struct drm_nouveau_private *);
1007int nouveau_ttm_mmap(struct file *, struct vm_area_struct *);
1008
1009/* nouveau_dp.c */
1010int nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
1011 uint8_t *data, int data_nr);
1012bool nouveau_dp_detect(struct drm_encoder *);
1013bool nouveau_dp_link_train(struct drm_encoder *);
1014
1015/* nv04_fb.c */
1016extern int nv04_fb_init(struct drm_device *);
1017extern void nv04_fb_takedown(struct drm_device *);
1018
1019/* nv10_fb.c */
1020extern int nv10_fb_init(struct drm_device *);
1021extern void nv10_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1022extern void nv10_fb_init_tile_region(struct drm_device *dev, int i,
1023 uint32_t addr, uint32_t size,
1024 uint32_t pitch, uint32_t flags);
1025extern void nv10_fb_set_tile_region(struct drm_device *dev, int i);
1026extern void nv10_fb_free_tile_region(struct drm_device *dev, int i);
6ee73861 1027
8bded189
FJ		 1028/* nv30_fb.c */
1029extern int nv30_fb_init(struct drm_device *);
1030extern void nv30_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1031extern void nv30_fb_init_tile_region(struct drm_device *dev, int i,
1032 uint32_t addr, uint32_t size,
1033 uint32_t pitch, uint32_t flags);
1034extern void nv30_fb_free_tile_region(struct drm_device *dev, int i);
8bded189 1035
6ee73861
BS		 1036/* nv40_fb.c */
1037extern int nv40_fb_init(struct drm_device *);
1038extern void nv40_fb_takedown(struct drm_device *);
a5cf68b0
FJ		 1039extern void nv40_fb_set_tile_region(struct drm_device *dev, int i);
1040
304424e1
MK		 1041/* nv50_fb.c */
1042extern int nv50_fb_init(struct drm_device *);
1043extern void nv50_fb_takedown(struct drm_device *);
d96773e7 1044extern void nv50_fb_vm_trap(struct drm_device *, int display, const char *);
304424e1 1045
4b223eef
BS		 1046/* nvc0_fb.c */
1047extern int nvc0_fb_init(struct drm_device *);
1048extern void nvc0_fb_takedown(struct drm_device *);
1049
6ee73861
BS		 1050/* nv04_fifo.c */
1051extern int nv04_fifo_init(struct drm_device *);
1052extern void nv04_fifo_disable(struct drm_device *);
1053extern void nv04_fifo_enable(struct drm_device *);
1054extern bool nv04_fifo_reassign(struct drm_device *, bool);
588d7d12 1055extern bool nv04_fifo_cache_pull(struct drm_device *, bool);
6ee73861
BS		 1056extern int nv04_fifo_channel_id(struct drm_device *);
1057extern int nv04_fifo_create_context(struct nouveau_channel *);
1058extern void nv04_fifo_destroy_context(struct nouveau_channel *);
1059extern int nv04_fifo_load_context(struct nouveau_channel *);
1060extern int nv04_fifo_unload_context(struct drm_device *);
1061
1062/* nv10_fifo.c */
1063extern int nv10_fifo_init(struct drm_device *);
1064extern int nv10_fifo_channel_id(struct drm_device *);
1065extern int nv10_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1066extern int nv10_fifo_load_context(struct nouveau_channel *);
1067extern int nv10_fifo_unload_context(struct drm_device *);
1068
1069/* nv40_fifo.c */
1070extern int nv40_fifo_init(struct drm_device *);
1071extern int nv40_fifo_create_context(struct nouveau_channel *);
6ee73861
BS		 1072extern int nv40_fifo_load_context(struct nouveau_channel *);
1073extern int nv40_fifo_unload_context(struct drm_device *);
1074
1075/* nv50_fifo.c */
1076extern int nv50_fifo_init(struct drm_device *);
1077extern void nv50_fifo_takedown(struct drm_device *);
1078extern int nv50_fifo_channel_id(struct drm_device *);
1079extern int nv50_fifo_create_context(struct nouveau_channel *);
1080extern void nv50_fifo_destroy_context(struct nouveau_channel *);
1081extern int nv50_fifo_load_context(struct nouveau_channel *);
1082extern int nv50_fifo_unload_context(struct drm_device *);
56ac7475 1083extern void nv50_fifo_tlb_flush(struct drm_device *dev);
6ee73861 1084
4b223eef
BS		 1085/* nvc0_fifo.c */
1086extern int nvc0_fifo_init(struct drm_device *);
1087extern void nvc0_fifo_takedown(struct drm_device *);
1088extern void nvc0_fifo_disable(struct drm_device *);
1089extern void nvc0_fifo_enable(struct drm_device *);
1090extern bool nvc0_fifo_reassign(struct drm_device *, bool);
4b223eef
BS		 1091extern bool nvc0_fifo_cache_pull(struct drm_device *, bool);
1092extern int nvc0_fifo_channel_id(struct drm_device *);
1093extern int nvc0_fifo_create_context(struct nouveau_channel *);
1094extern void nvc0_fifo_destroy_context(struct nouveau_channel *);
1095extern int nvc0_fifo_load_context(struct nouveau_channel *);
1096extern int nvc0_fifo_unload_context(struct drm_device *);
1097
6ee73861 1098/* nv04_graph.c */
6ee73861
BS		 1099extern int nv04_graph_init(struct drm_device *);
1100extern void nv04_graph_takedown(struct drm_device *);
1101extern void nv04_graph_fifo_access(struct drm_device *, bool);
1102extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
1103extern int nv04_graph_create_context(struct nouveau_channel *);
1104extern void nv04_graph_destroy_context(struct nouveau_channel *);
1105extern int nv04_graph_load_context(struct nouveau_channel *);
1106extern int nv04_graph_unload_context(struct drm_device *);
1107extern void nv04_graph_context_switch(struct drm_device *);
332b242f
FJ		 1108extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
1109 u32 class, u32 mthd, u32 data);
6ee73861
BS		 1110
1111/* nv10_graph.c */
6ee73861
BS		 1112extern int nv10_graph_init(struct drm_device *);
1113extern void nv10_graph_takedown(struct drm_device *);
1114extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
1115extern int nv10_graph_create_context(struct nouveau_channel *);
1116extern void nv10_graph_destroy_context(struct nouveau_channel *);
1117extern int nv10_graph_load_context(struct nouveau_channel *);
1118extern int nv10_graph_unload_context(struct drm_device *);
1119extern void nv10_graph_context_switch(struct drm_device *);
a5cf68b0 1120extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1121
1122/* nv20_graph.c */
6ee73861
BS		 1123extern int nv20_graph_create_context(struct nouveau_channel *);
1124extern void nv20_graph_destroy_context(struct nouveau_channel *);
1125extern int nv20_graph_load_context(struct nouveau_channel *);
1126extern int nv20_graph_unload_context(struct drm_device *);
1127extern int nv20_graph_init(struct drm_device *);
1128extern void nv20_graph_takedown(struct drm_device *);
1129extern int nv30_graph_init(struct drm_device *);
a5cf68b0 1130extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1131
1132/* nv40_graph.c */
6ee73861
BS		 1133extern int nv40_graph_init(struct drm_device *);
1134extern void nv40_graph_takedown(struct drm_device *);
1135extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
1136extern int nv40_graph_create_context(struct nouveau_channel *);
1137extern void nv40_graph_destroy_context(struct nouveau_channel *);
1138extern int nv40_graph_load_context(struct nouveau_channel *);
1139extern int nv40_graph_unload_context(struct drm_device *);
054b93e4 1140extern void nv40_grctx_init(struct nouveau_grctx *);
a5cf68b0 1141extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
6ee73861
BS		 1142
1143/* nv50_graph.c */
6ee73861
BS		 1144extern int nv50_graph_init(struct drm_device *);
1145extern void nv50_graph_takedown(struct drm_device *);
1146extern void nv50_graph_fifo_access(struct drm_device *, bool);
1147extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
1148extern int nv50_graph_create_context(struct nouveau_channel *);
1149extern void nv50_graph_destroy_context(struct nouveau_channel *);
1150extern int nv50_graph_load_context(struct nouveau_channel *);
1151extern int nv50_graph_unload_context(struct drm_device *);
1152extern void nv50_graph_context_switch(struct drm_device *);
d5f3c90d 1153extern int nv50_grctx_init(struct nouveau_grctx *);
56ac7475
BS		 1154extern void nv50_graph_tlb_flush(struct drm_device *dev);
1155extern void nv86_graph_tlb_flush(struct drm_device *dev);
6ee73861 1156
4b223eef
BS		 1157/* nvc0_graph.c */
1158extern int nvc0_graph_init(struct drm_device *);
1159extern void nvc0_graph_takedown(struct drm_device *);
1160extern void nvc0_graph_fifo_access(struct drm_device *, bool);
1161extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
1162extern int nvc0_graph_create_context(struct nouveau_channel *);
1163extern void nvc0_graph_destroy_context(struct nouveau_channel *);
1164extern int nvc0_graph_load_context(struct nouveau_channel *);
1165extern int nvc0_graph_unload_context(struct drm_device *);
1166
bd2e597d
BS		 1167/* nv84_crypt.c */
1168extern int nv84_crypt_init(struct drm_device *dev);
1169extern void nv84_crypt_fini(struct drm_device *dev);
1170extern int nv84_crypt_create_context(struct nouveau_channel *);
1171extern void nv84_crypt_destroy_context(struct nouveau_channel *);
1172extern void nv84_crypt_tlb_flush(struct drm_device *dev);
1173
6ee73861
BS		 1174/* nv04_instmem.c */
1175extern int nv04_instmem_init(struct drm_device *);
1176extern void nv04_instmem_takedown(struct drm_device *);
1177extern int nv04_instmem_suspend(struct drm_device *);
1178extern void nv04_instmem_resume(struct drm_device *);
1179extern int nv04_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1180 u32 *size, u32 align);
6ee73861
BS		 1181extern void nv04_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1182extern int nv04_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1183extern int nv04_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1184extern void nv04_instmem_flush(struct drm_device *);
6ee73861
BS		 1185
1186/* nv50_instmem.c */
1187extern int nv50_instmem_init(struct drm_device *);
1188extern void nv50_instmem_takedown(struct drm_device *);
1189extern int nv50_instmem_suspend(struct drm_device *);
1190extern void nv50_instmem_resume(struct drm_device *);
1191extern int nv50_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1192 u32 *size, u32 align);
6ee73861
BS		 1193extern void nv50_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1194extern int nv50_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1195extern int nv50_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
f56cb86f 1196extern void nv50_instmem_flush(struct drm_device *);
734ee835 1197extern void nv84_instmem_flush(struct drm_device *);
63187215 1198extern void nv50_vm_flush(struct drm_device *, int engine);
6ee73861 1199
4b223eef
BS		 1200/* nvc0_instmem.c */
1201extern int nvc0_instmem_init(struct drm_device *);
1202extern void nvc0_instmem_takedown(struct drm_device *);
1203extern int nvc0_instmem_suspend(struct drm_device *);
1204extern void nvc0_instmem_resume(struct drm_device *);
1205extern int nvc0_instmem_populate(struct drm_device *, struct nouveau_gpuobj *,
9100468d 1206 u32 *size, u32 align);
4b223eef
BS		 1207extern void nvc0_instmem_clear(struct drm_device *, struct nouveau_gpuobj *);
1208extern int nvc0_instmem_bind(struct drm_device *, struct nouveau_gpuobj *);
1209extern int nvc0_instmem_unbind(struct drm_device *, struct nouveau_gpuobj *);
1210extern void nvc0_instmem_flush(struct drm_device *);
1211
6ee73861
BS		 1212/* nv04_mc.c */
1213extern int nv04_mc_init(struct drm_device *);
1214extern void nv04_mc_takedown(struct drm_device *);
1215
1216/* nv40_mc.c */
1217extern int nv40_mc_init(struct drm_device *);
1218extern void nv40_mc_takedown(struct drm_device *);
1219
1220/* nv50_mc.c */
1221extern int nv50_mc_init(struct drm_device *);
1222extern void nv50_mc_takedown(struct drm_device *);
1223
1224/* nv04_timer.c */
1225extern int nv04_timer_init(struct drm_device *);
1226extern uint64_t nv04_timer_read(struct drm_device *);
1227extern void nv04_timer_takedown(struct drm_device *);
1228
1229extern long nouveau_compat_ioctl(struct file *file, unsigned int cmd,
1230 unsigned long arg);
1231
1232/* nv04_dac.c */
8f1a6086 1233extern int nv04_dac_create(struct drm_connector *, struct dcb_entry *);
11d6eb2a 1234extern uint32_t nv17_dac_sample_load(struct drm_encoder *encoder);
6ee73861
BS		 1235extern int nv04_dac_output_offset(struct drm_encoder *encoder);
1236extern void nv04_dac_update_dacclk(struct drm_encoder *encoder, bool enable);
8ccfe9e0 1237extern bool nv04_dac_in_use(struct drm_encoder *encoder);
6ee73861
BS		 1238
1239/* nv04_dfp.c */
8f1a6086 1240extern int nv04_dfp_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1241extern int nv04_dfp_get_bound_head(struct drm_device *dev, struct dcb_entry *dcbent);
1242extern void nv04_dfp_bind_head(struct drm_device *dev, struct dcb_entry *dcbent,
1243 int head, bool dl);
1244extern void nv04_dfp_disable(struct drm_device *dev, int head);
1245extern void nv04_dfp_update_fp_control(struct drm_encoder *encoder, int mode);
1246
1247/* nv04_tv.c */
1248extern int nv04_tv_identify(struct drm_device *dev, int i2c_index);
8f1a6086 1249extern int nv04_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1250
1251/* nv17_tv.c */
8f1a6086 1252extern int nv17_tv_create(struct drm_connector *, struct dcb_entry *);
6ee73861
BS		 1253
1254/* nv04_display.c */
c88c2e06
FJ		 1255extern int nv04_display_early_init(struct drm_device *);
1256extern void nv04_display_late_takedown(struct drm_device *);
6ee73861 1257extern int nv04_display_create(struct drm_device *);
c88c2e06 1258extern int nv04_display_init(struct drm_device *);
6ee73861 1259extern void nv04_display_destroy(struct drm_device *);
6ee73861
BS		 1260
1261/* nv04_crtc.c */
1262extern int nv04_crtc_create(struct drm_device *, int index);
1263
1264/* nouveau_bo.c */
1265extern struct ttm_bo_driver nouveau_bo_driver;
1266extern int nouveau_bo_new(struct drm_device *, struct nouveau_channel *,
1267 int size, int align, uint32_t flags,
1268 uint32_t tile_mode, uint32_t tile_flags,
1269 bool no_vm, bool mappable, struct nouveau_bo **);
1270extern int nouveau_bo_pin(struct nouveau_bo *, uint32_t flags);
1271extern int nouveau_bo_unpin(struct nouveau_bo *);
1272extern int nouveau_bo_map(struct nouveau_bo *);
1273extern void nouveau_bo_unmap(struct nouveau_bo *);
78ad0f7b
FJ		 1274extern void nouveau_bo_placement_set(struct nouveau_bo *, uint32_t type,
1275 uint32_t busy);
6ee73861
BS		 1276extern u16 nouveau_bo_rd16(struct nouveau_bo *nvbo, unsigned index);
1277extern void nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val);
1278extern u32 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index);
1279extern void nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val);
332b242f 1280extern void nouveau_bo_fence(struct nouveau_bo *, struct nouveau_fence *);
6ee73861
BS		 1281
1282/* nouveau_fence.c */
1283struct nouveau_fence;
0c6c1c2f
FJ		 1284extern int nouveau_fence_init(struct drm_device *);
1285extern void nouveau_fence_fini(struct drm_device *);
2730723b
FJ		 1286extern int nouveau_fence_channel_init(struct nouveau_channel *);
1287extern void nouveau_fence_channel_fini(struct nouveau_channel *);
6ee73861
BS		 1288extern void nouveau_fence_update(struct nouveau_channel *);
1289extern int nouveau_fence_new(struct nouveau_channel *, struct nouveau_fence **,
1290 bool emit);
1291extern int nouveau_fence_emit(struct nouveau_fence *);
8ac3891b
FJ		 1292extern void nouveau_fence_work(struct nouveau_fence *fence,
1293 void (*work)(void *priv, bool signalled),
1294 void *priv);
6ee73861 1295struct nouveau_channel *nouveau_fence_channel(struct nouveau_fence *);
382d62e5
MS		 1296
1297extern bool __nouveau_fence_signalled(void *obj, void *arg);
1298extern int __nouveau_fence_wait(void *obj, void *arg, bool lazy, bool intr);
1299extern int __nouveau_fence_flush(void *obj, void *arg);
1300extern void __nouveau_fence_unref(void **obj);
1301extern void *__nouveau_fence_ref(void *obj);
1302
1303static inline bool nouveau_fence_signalled(struct nouveau_fence *obj)
1304{
1305 return __nouveau_fence_signalled(obj, NULL);
1306}
1307static inline int
1308nouveau_fence_wait(struct nouveau_fence *obj, bool lazy, bool intr)
1309{
1310 return __nouveau_fence_wait(obj, NULL, lazy, intr);
1311}
2730723b 1312extern int nouveau_fence_sync(struct nouveau_fence *, struct nouveau_channel *);
382d62e5
MS		 1313static inline int nouveau_fence_flush(struct nouveau_fence *obj)
1314{
1315 return __nouveau_fence_flush(obj, NULL);
1316}
1317static inline void nouveau_fence_unref(struct nouveau_fence **obj)
1318{
1319 __nouveau_fence_unref((void **)obj);
1320}
1321static inline struct nouveau_fence *nouveau_fence_ref(struct nouveau_fence *obj)
1322{
1323 return __nouveau_fence_ref(obj);
1324}
6ee73861
BS		 1325
1326/* nouveau_gem.c */
1327extern int nouveau_gem_new(struct drm_device *, struct nouveau_channel *,
1328 int size, int align, uint32_t flags,
1329 uint32_t tile_mode, uint32_t tile_flags,
1330 bool no_vm, bool mappable, struct nouveau_bo **);
1331extern int nouveau_gem_object_new(struct drm_gem_object *);
1332extern void nouveau_gem_object_del(struct drm_gem_object *);
1333extern int nouveau_gem_ioctl_new(struct drm_device *, void *,
1334 struct drm_file *);
1335extern int nouveau_gem_ioctl_pushbuf(struct drm_device *, void *,
1336 struct drm_file *);
6ee73861
BS		 1337extern int nouveau_gem_ioctl_cpu_prep(struct drm_device *, void *,
1338 struct drm_file *);
1339extern int nouveau_gem_ioctl_cpu_fini(struct drm_device *, void *,
1340 struct drm_file *);
1341extern int nouveau_gem_ioctl_info(struct drm_device *, void *,
1342 struct drm_file *);
1343
042206c0
FJ		 1344/* nouveau_display.c */
1345int nouveau_vblank_enable(struct drm_device *dev, int crtc);
1346void nouveau_vblank_disable(struct drm_device *dev, int crtc);
332b242f
FJ		 1347int nouveau_crtc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1348 struct drm_pending_vblank_event *event);
1349int nouveau_finish_page_flip(struct nouveau_channel *,
1350 struct nouveau_page_flip_state *);
042206c0 1351
ee2e0131
BS		 1352/* nv10_gpio.c */
1353int nv10_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1354int nv10_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
6ee73861 1355
45284162 1356/* nv50_gpio.c */
ee2e0131 1357int nv50_gpio_init(struct drm_device *dev);
45284162
BS		 1358int nv50_gpio_get(struct drm_device *dev, enum dcb_gpio_tag tag);
1359int nv50_gpio_set(struct drm_device *dev, enum dcb_gpio_tag tag, int state);
d0875edd 1360void nv50_gpio_irq_enable(struct drm_device *, enum dcb_gpio_tag, bool on);
45284162 1361
e9ebb68b
BS		 1362/* nv50_calc. */
1363int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
1364 int *N1, int *M1, int *N2, int *M2, int *P);
1365int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
1366 int clk, int *N, int *fN, int *M, int *P);
1367
6ee73861
BS		 1368#ifndef ioread32_native
1369#ifdef __BIG_ENDIAN
1370#define ioread16_native ioread16be
1371#define iowrite16_native iowrite16be
1372#define ioread32_native ioread32be
1373#define iowrite32_native iowrite32be
1374#else /* def __BIG_ENDIAN */
1375#define ioread16_native ioread16
1376#define iowrite16_native iowrite16
1377#define ioread32_native ioread32
1378#define iowrite32_native iowrite32
1379#endif /* def __BIG_ENDIAN else */
1380#endif /* !ioread32_native */
1381
1382/* channel control reg access */
1383static inline u32 nvchan_rd32(struct nouveau_channel *chan, unsigned reg)
1384{
1385 return ioread32_native(chan->user + reg);
1386}
1387
1388static inline void nvchan_wr32(struct nouveau_channel *chan,
1389 unsigned reg, u32 val)
1390{
1391 iowrite32_native(val, chan->user + reg);
1392}
1393
1394/* register access */
1395static inline u32 nv_rd32(struct drm_device *dev, unsigned reg)
1396{
1397 struct drm_nouveau_private *dev_priv = dev->dev_private;
1398 return ioread32_native(dev_priv->mmio + reg);
1399}
1400
1401static inline void nv_wr32(struct drm_device *dev, unsigned reg, u32 val)
1402{
1403 struct drm_nouveau_private *dev_priv = dev->dev_private;
1404 iowrite32_native(val, dev_priv->mmio + reg);
1405}
1406
2a7fdb2b 1407static inline u32 nv_mask(struct drm_device *dev, u32 reg, u32 mask, u32 val)
49eed80a
BS		 1408{
1409 u32 tmp = nv_rd32(dev, reg);
2a7fdb2b
BS		 1410 nv_wr32(dev, reg, (tmp & ~mask) | val);
1411 return tmp;
49eed80a
BS		 1412}
1413
6ee73861
BS		 1414static inline u8 nv_rd08(struct drm_device *dev, unsigned reg)
1415{
1416 struct drm_nouveau_private *dev_priv = dev->dev_private;
1417 return ioread8(dev_priv->mmio + reg);
1418}
1419
1420static inline void nv_wr08(struct drm_device *dev, unsigned reg, u8 val)
1421{
1422 struct drm_nouveau_private *dev_priv = dev->dev_private;
1423 iowrite8(val, dev_priv->mmio + reg);
1424}
1425
4b5c152a 1426#define nv_wait(dev, reg, mask, val) \
6ee73861
BS		 1427 nouveau_wait_until(dev, 2000000000ULL, (reg), (mask), (val))
1428
1429/* PRAMIN access */
1430static inline u32 nv_ri32(struct drm_device *dev, unsigned offset)
1431{
1432 struct drm_nouveau_private *dev_priv = dev->dev_private;
1433 return ioread32_native(dev_priv->ramin + offset);
1434}
1435
1436static inline void nv_wi32(struct drm_device *dev, unsigned offset, u32 val)
1437{
1438 struct drm_nouveau_private *dev_priv = dev->dev_private;
1439 iowrite32_native(val, dev_priv->ramin + offset);
1440}
1441
1442/* object access */
b3beb167
BS		 1443extern u32 nv_ro32(struct nouveau_gpuobj *, u32 offset);
1444extern void nv_wo32(struct nouveau_gpuobj *, u32 offset, u32 val);
6ee73861
BS		 1445
1446/*
1447 * Logging
1448 * Argument d is (struct drm_device *).
1449 */
1450#define NV_PRINTK(level, d, fmt, arg...) \
1451 printk(level "[" DRM_NAME "] " DRIVER_NAME " %s: " fmt, \
1452 pci_name(d->pdev), ##arg)
1453#ifndef NV_DEBUG_NOTRACE
1454#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1455 if (drm_debug & DRM_UT_DRIVER) { \
1456 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1457 __LINE__, ##arg); \
1458 } \
1459} while (0)
1460#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1461 if (drm_debug & DRM_UT_KMS) { \
6ee73861
BS		 1462 NV_PRINTK(KERN_DEBUG, d, "%s:%d - " fmt, __func__, \
1463 __LINE__, ##arg); \
1464 } \
1465} while (0)
1466#else
1467#define NV_DEBUG(d, fmt, arg...) do { \
ef2bb506
MM		 1468 if (drm_debug & DRM_UT_DRIVER) \
1469 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1470} while (0)
1471#define NV_DEBUG_KMS(d, fmt, arg...) do { \
1472 if (drm_debug & DRM_UT_KMS) \
6ee73861
BS		 1473 NV_PRINTK(KERN_DEBUG, d, fmt, ##arg); \
1474} while (0)
1475#endif
1476#define NV_ERROR(d, fmt, arg...) NV_PRINTK(KERN_ERR, d, fmt, ##arg)
1477#define NV_INFO(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1478#define NV_TRACEWARN(d, fmt, arg...) NV_PRINTK(KERN_NOTICE, d, fmt, ##arg)
1479#define NV_TRACE(d, fmt, arg...) NV_PRINTK(KERN_INFO, d, fmt, ##arg)
1480#define NV_WARN(d, fmt, arg...) NV_PRINTK(KERN_WARNING, d, fmt, ##arg)
1481
1482/* nouveau_reg_debug bitmask */
1483enum {
1484 NOUVEAU_REG_DEBUG_MC = 0x1,
1485 NOUVEAU_REG_DEBUG_VIDEO = 0x2,
1486 NOUVEAU_REG_DEBUG_FB = 0x4,
1487 NOUVEAU_REG_DEBUG_EXTDEV = 0x8,
1488 NOUVEAU_REG_DEBUG_CRTC = 0x10,
1489 NOUVEAU_REG_DEBUG_RAMDAC = 0x20,
1490 NOUVEAU_REG_DEBUG_VGACRTC = 0x40,
1491 NOUVEAU_REG_DEBUG_RMVIO = 0x80,
1492 NOUVEAU_REG_DEBUG_VGAATTR = 0x100,
1493 NOUVEAU_REG_DEBUG_EVO = 0x200,
1494};
1495
1496#define NV_REG_DEBUG(type, dev, fmt, arg...) do { \
1497 if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_##type) \
1498 NV_PRINTK(KERN_DEBUG, dev, "%s: " fmt, __func__, ##arg); \
1499} while (0)
1500
1501static inline bool
1502nv_two_heads(struct drm_device *dev)
1503{
1504 struct drm_nouveau_private *dev_priv = dev->dev_private;
1505 const int impl = dev->pci_device & 0x0ff0;
1506
1507 if (dev_priv->card_type >= NV_10 && impl != 0x0100 &&
1508 impl != 0x0150 && impl != 0x01a0 && impl != 0x0200)
1509 return true;
1510
1511 return false;
1512}
1513
1514static inline bool
1515nv_gf4_disp_arch(struct drm_device *dev)
1516{
1517 return nv_two_heads(dev) && (dev->pci_device & 0x0ff0) != 0x0110;
1518}
1519
1520static inline bool
1521nv_two_reg_pll(struct drm_device *dev)
1522{
1523 struct drm_nouveau_private *dev_priv = dev->dev_private;
1524 const int impl = dev->pci_device & 0x0ff0;
1525
1526 if (impl == 0x0310 || impl == 0x0340 || dev_priv->card_type >= NV_40)
1527 return true;
1528 return false;
1529}
1530
acae116c
FJ		 1531static inline bool
1532nv_match_device(struct drm_device *dev, unsigned device,
1533 unsigned sub_vendor, unsigned sub_device)
1534{
1535 return dev->pdev->device == device &&
1536 dev->pdev->subsystem_vendor == sub_vendor &&
1537 dev->pdev->subsystem_device == sub_device;
1538}
1539
f03a314b
FJ		 1540#define NV_SW 0x0000506e
1541#define NV_SW_DMA_SEMAPHORE 0x00000060
1542#define NV_SW_SEMAPHORE_OFFSET 0x00000064
1543#define NV_SW_SEMAPHORE_ACQUIRE 0x00000068
1544#define NV_SW_SEMAPHORE_RELEASE 0x0000006c
8af29ccd 1545#define NV_SW_YIELD 0x00000080
f03a314b
FJ		 1546#define NV_SW_DMA_VBLSEM 0x0000018c
1547#define NV_SW_VBLSEM_OFFSET 0x00000400
1548#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
1549#define NV_SW_VBLSEM_RELEASE 0x00000408
332b242f 1550#define NV_SW_PAGE_FLIP 0x00000500
6ee73861
BS		 1551
1552#endif /* __NOUVEAU_DRV_H__ */
kernel source for telekom puls (alcatel/mediatek)