Commit | Line | Data |
---|---|---|
6ee73861 BS |
1 | /* |
2 | * Copyright 2005 Stephane Marchesin. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
22 | * OTHER DEALINGS IN THE SOFTWARE. | |
23 | */ | |
24 | ||
25 | #include <linux/console.h> | |
26 | ||
27 | #include "drmP.h" | |
28 | #include "drm.h" | |
29 | #include "drm_crtc_helper.h" | |
30 | #include "nouveau_drv.h" | |
31 | #include "nouveau_hw.h" | |
32 | #include "nouveau_fb.h" | |
33 | #include "nouveau_fbcon.h" | |
64f1c11a | 34 | #include "nouveau_pm.h" |
6ee73861 BS |
35 | #include "nv50_display.h" |
36 | ||
37 | #include "drm_pciids.h" | |
38 | ||
de5899bd FJ |
39 | MODULE_PARM_DESC(agpmode, "AGP mode (0 to disable AGP)"); |
40 | int nouveau_agpmode = -1; | |
41 | module_param_named(agpmode, nouveau_agpmode, int, 0400); | |
6ee73861 BS |
42 | |
43 | MODULE_PARM_DESC(modeset, "Enable kernel modesetting"); | |
44 | static int nouveau_modeset = -1; /* kms */ | |
45 | module_param_named(modeset, nouveau_modeset, int, 0400); | |
46 | ||
47 | MODULE_PARM_DESC(vbios, "Override default VBIOS location"); | |
48 | char *nouveau_vbios; | |
49 | module_param_named(vbios, nouveau_vbios, charp, 0400); | |
50 | ||
51 | MODULE_PARM_DESC(vram_pushbuf, "Force DMA push buffers to be in VRAM"); | |
52 | int nouveau_vram_pushbuf; | |
53 | module_param_named(vram_pushbuf, nouveau_vram_pushbuf, int, 0400); | |
54 | ||
55 | MODULE_PARM_DESC(vram_notify, "Force DMA notifiers to be in VRAM"); | |
2dfe36b1 | 56 | int nouveau_vram_notify = 0; |
6ee73861 BS |
57 | module_param_named(vram_notify, nouveau_vram_notify, int, 0400); |
58 | ||
59 | MODULE_PARM_DESC(duallink, "Allow dual-link TMDS (>=GeForce 8)"); | |
60 | int nouveau_duallink = 1; | |
61 | module_param_named(duallink, nouveau_duallink, int, 0400); | |
62 | ||
63 | MODULE_PARM_DESC(uscript_lvds, "LVDS output script table ID (>=GeForce 8)"); | |
64 | int nouveau_uscript_lvds = -1; | |
65 | module_param_named(uscript_lvds, nouveau_uscript_lvds, int, 0400); | |
66 | ||
67 | MODULE_PARM_DESC(uscript_tmds, "TMDS output script table ID (>=GeForce 8)"); | |
68 | int nouveau_uscript_tmds = -1; | |
69 | module_param_named(uscript_tmds, nouveau_uscript_tmds, int, 0400); | |
70 | ||
a1470890 BS |
71 | MODULE_PARM_DESC(ignorelid, "Ignore ACPI lid status"); |
72 | int nouveau_ignorelid = 0; | |
73 | module_param_named(ignorelid, nouveau_ignorelid, int, 0400); | |
74 | ||
81e2d422 | 75 | MODULE_PARM_DESC(noaccel, "Disable all acceleration"); |
aba99a84 | 76 | int nouveau_noaccel = -1; |
a32ed69d MK |
77 | module_param_named(noaccel, nouveau_noaccel, int, 0400); |
78 | ||
81e2d422 | 79 | MODULE_PARM_DESC(nofbaccel, "Disable fbcon acceleration"); |
a32ed69d MK |
80 | int nouveau_nofbaccel = 0; |
81 | module_param_named(nofbaccel, nouveau_nofbaccel, int, 0400); | |
82 | ||
0cba1b76 MK |
83 | MODULE_PARM_DESC(force_post, "Force POST"); |
84 | int nouveau_force_post = 0; | |
85 | module_param_named(force_post, nouveau_force_post, int, 0400); | |
86 | ||
da647d5b BS |
87 | MODULE_PARM_DESC(override_conntype, "Ignore DCB connector type"); |
88 | int nouveau_override_conntype = 0; | |
89 | module_param_named(override_conntype, nouveau_override_conntype, int, 0400); | |
90 | ||
f4053509 BS |
91 | MODULE_PARM_DESC(tv_disable, "Disable TV-out detection\n"); |
92 | int nouveau_tv_disable = 0; | |
93 | module_param_named(tv_disable, nouveau_tv_disable, int, 0400); | |
94 | ||
6ee73861 BS |
95 | MODULE_PARM_DESC(tv_norm, "Default TV norm.\n" |
96 | "\t\tSupported: PAL, PAL-M, PAL-N, PAL-Nc, NTSC-M, NTSC-J,\n" | |
97 | "\t\t\thd480i, hd480p, hd576i, hd576p, hd720p, hd1080i.\n" | |
98 | "\t\tDefault: PAL\n" | |
99 | "\t\t*NOTE* Ignored for cards with external TV encoders."); | |
100 | char *nouveau_tv_norm; | |
101 | module_param_named(tv_norm, nouveau_tv_norm, charp, 0400); | |
102 | ||
103 | MODULE_PARM_DESC(reg_debug, "Register access debug bitmask:\n" | |
104 | "\t\t0x1 mc, 0x2 video, 0x4 fb, 0x8 extdev,\n" | |
105 | "\t\t0x10 crtc, 0x20 ramdac, 0x40 vgacrtc, 0x80 rmvio,\n" | |
106 | "\t\t0x100 vgaattr, 0x200 EVO (G80+). "); | |
107 | int nouveau_reg_debug; | |
108 | module_param_named(reg_debug, nouveau_reg_debug, int, 0600); | |
109 | ||
6f876986 BS |
110 | MODULE_PARM_DESC(perflvl, "Performance level (default: boot)\n"); |
111 | char *nouveau_perflvl; | |
112 | module_param_named(perflvl, nouveau_perflvl, charp, 0400); | |
113 | ||
114 | MODULE_PARM_DESC(perflvl_wr, "Allow perflvl changes (warning: dangerous!)\n"); | |
115 | int nouveau_perflvl_wr; | |
116 | module_param_named(perflvl_wr, nouveau_perflvl_wr, int, 0400); | |
117 | ||
35fa2f2a BS |
118 | MODULE_PARM_DESC(msi, "Enable MSI (default: off)\n"); |
119 | int nouveau_msi; | |
120 | module_param_named(msi, nouveau_msi, int, 0400); | |
121 | ||
0411de85 BS |
122 | MODULE_PARM_DESC(ctxfw, "Use external HUB/GPC ucode (fermi)\n"); |
123 | int nouveau_ctxfw; | |
124 | module_param_named(ctxfw, nouveau_ctxfw, int, 0400); | |
125 | ||
6ee73861 BS |
126 | int nouveau_fbpercrtc; |
127 | #if 0 | |
128 | module_param_named(fbpercrtc, nouveau_fbpercrtc, int, 0400); | |
129 | #endif | |
130 | ||
131 | static struct pci_device_id pciidlist[] = { | |
132 | { | |
133 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID), | |
134 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
135 | .class_mask = 0xff << 16, | |
136 | }, | |
137 | { | |
138 | PCI_DEVICE(PCI_VENDOR_ID_NVIDIA_SGS, PCI_ANY_ID), | |
139 | .class = PCI_BASE_CLASS_DISPLAY << 16, | |
140 | .class_mask = 0xff << 16, | |
141 | }, | |
142 | {} | |
143 | }; | |
144 | ||
145 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
146 | ||
147 | static struct drm_driver driver; | |
148 | ||
149 | static int __devinit | |
150 | nouveau_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
151 | { | |
dcdb1674 | 152 | return drm_get_pci_dev(pdev, ent, &driver); |
6ee73861 BS |
153 | } |
154 | ||
155 | static void | |
156 | nouveau_pci_remove(struct pci_dev *pdev) | |
157 | { | |
158 | struct drm_device *dev = pci_get_drvdata(pdev); | |
159 | ||
160 | drm_put_dev(dev); | |
161 | } | |
162 | ||
6a9ee8af | 163 | int |
6ee73861 BS |
164 | nouveau_pci_suspend(struct pci_dev *pdev, pm_message_t pm_state) |
165 | { | |
166 | struct drm_device *dev = pci_get_drvdata(pdev); | |
167 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
168 | struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; | |
6ee73861 BS |
169 | struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo; |
170 | struct nouveau_channel *chan; | |
171 | struct drm_crtc *crtc; | |
92abe749 | 172 | int ret, i, e; |
6ee73861 | 173 | |
6ee73861 BS |
174 | if (pm_state.event == PM_EVENT_PRETHAW) |
175 | return 0; | |
176 | ||
5bcf719b DA |
177 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
178 | return 0; | |
179 | ||
81441570 | 180 | NV_INFO(dev, "Disabling fbcon acceleration...\n"); |
38651674 | 181 | nouveau_fbcon_save_disable_accel(dev); |
6ee73861 | 182 | |
81441570 | 183 | NV_INFO(dev, "Unpinning framebuffer(s)...\n"); |
6ee73861 BS |
184 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
185 | struct nouveau_framebuffer *nouveau_fb; | |
186 | ||
187 | nouveau_fb = nouveau_framebuffer(crtc->fb); | |
188 | if (!nouveau_fb || !nouveau_fb->nvbo) | |
189 | continue; | |
190 | ||
191 | nouveau_bo_unpin(nouveau_fb->nvbo); | |
192 | } | |
193 | ||
b334f2b3 MM |
194 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
195 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
196 | ||
197 | nouveau_bo_unmap(nv_crtc->cursor.nvbo); | |
198 | nouveau_bo_unpin(nv_crtc->cursor.nvbo); | |
199 | } | |
200 | ||
6ee73861 BS |
201 | NV_INFO(dev, "Evicting buffers...\n"); |
202 | ttm_bo_evict_mm(&dev_priv->ttm.bdev, TTM_PL_VRAM); | |
203 | ||
204 | NV_INFO(dev, "Idling channels...\n"); | |
205 | for (i = 0; i < pfifo->channels; i++) { | |
cff5c133 | 206 | chan = dev_priv->channels.ptr[i]; |
6ee73861 | 207 | |
6dccd311 FJ |
208 | if (chan && chan->pushbuf_bo) |
209 | nouveau_channel_idle(chan); | |
6ee73861 BS |
210 | } |
211 | ||
6ee73861 BS |
212 | pfifo->reassign(dev, false); |
213 | pfifo->disable(dev); | |
214 | pfifo->unload_context(dev); | |
92abe749 BS |
215 | |
216 | for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) { | |
217 | if (dev_priv->eng[e]) { | |
218 | ret = dev_priv->eng[e]->fini(dev, e); | |
219 | if (ret) | |
220 | goto out_abort; | |
221 | } | |
222 | } | |
6ee73861 | 223 | |
dc1e5c0d | 224 | ret = pinstmem->suspend(dev); |
6ee73861 BS |
225 | if (ret) { |
226 | NV_ERROR(dev, "... failed: %d\n", ret); | |
227 | goto out_abort; | |
228 | } | |
229 | ||
dc1e5c0d BS |
230 | NV_INFO(dev, "Suspending GPU objects...\n"); |
231 | ret = nouveau_gpuobj_suspend(dev); | |
6ee73861 BS |
232 | if (ret) { |
233 | NV_ERROR(dev, "... failed: %d\n", ret); | |
dc1e5c0d | 234 | pinstmem->resume(dev); |
6ee73861 BS |
235 | goto out_abort; |
236 | } | |
237 | ||
238 | NV_INFO(dev, "And we're gone!\n"); | |
239 | pci_save_state(pdev); | |
240 | if (pm_state.event == PM_EVENT_SUSPEND) { | |
241 | pci_disable_device(pdev); | |
242 | pci_set_power_state(pdev, PCI_D3hot); | |
243 | } | |
244 | ||
ac751efa | 245 | console_lock(); |
38651674 | 246 | nouveau_fbcon_set_suspend(dev, 1); |
ac751efa | 247 | console_unlock(); |
38651674 | 248 | nouveau_fbcon_restore_accel(dev); |
6ee73861 BS |
249 | return 0; |
250 | ||
251 | out_abort: | |
252 | NV_INFO(dev, "Re-enabling acceleration..\n"); | |
92abe749 BS |
253 | for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) { |
254 | if (dev_priv->eng[e]) | |
255 | dev_priv->eng[e]->init(dev, e); | |
256 | } | |
6ee73861 BS |
257 | pfifo->enable(dev); |
258 | pfifo->reassign(dev, true); | |
6ee73861 BS |
259 | return ret; |
260 | } | |
261 | ||
6a9ee8af | 262 | int |
6ee73861 BS |
263 | nouveau_pci_resume(struct pci_dev *pdev) |
264 | { | |
265 | struct drm_device *dev = pci_get_drvdata(pdev); | |
266 | struct drm_nouveau_private *dev_priv = dev->dev_private; | |
267 | struct nouveau_engine *engine = &dev_priv->engine; | |
268 | struct drm_crtc *crtc; | |
6ee73861 BS |
269 | int ret, i; |
270 | ||
5bcf719b DA |
271 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
272 | return 0; | |
273 | ||
38651674 | 274 | nouveau_fbcon_save_disable_accel(dev); |
6ee73861 BS |
275 | |
276 | NV_INFO(dev, "We're back, enabling device...\n"); | |
277 | pci_set_power_state(pdev, PCI_D0); | |
278 | pci_restore_state(pdev); | |
279 | if (pci_enable_device(pdev)) | |
280 | return -1; | |
281 | pci_set_master(dev->pdev); | |
282 | ||
e04d8e82 FJ |
283 | /* Make sure the AGP controller is in a consistent state */ |
284 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) | |
285 | nouveau_mem_reset_agp(dev); | |
286 | ||
c88c2e06 FJ |
287 | /* Make the CRTCs accessible */ |
288 | engine->display.early_init(dev); | |
289 | ||
6ee73861 BS |
290 | NV_INFO(dev, "POSTing device...\n"); |
291 | ret = nouveau_run_vbios_init(dev); | |
292 | if (ret) | |
293 | return ret; | |
294 | ||
64f1c11a BS |
295 | nouveau_pm_resume(dev); |
296 | ||
6ee73861 BS |
297 | if (dev_priv->gart_info.type == NOUVEAU_GART_AGP) { |
298 | ret = nouveau_mem_init_agp(dev); | |
299 | if (ret) { | |
300 | NV_ERROR(dev, "error reinitialising AGP: %d\n", ret); | |
301 | return ret; | |
302 | } | |
303 | } | |
304 | ||
dc1e5c0d BS |
305 | NV_INFO(dev, "Restoring GPU objects...\n"); |
306 | nouveau_gpuobj_resume(dev); | |
307 | ||
6ee73861 BS |
308 | NV_INFO(dev, "Reinitialising engines...\n"); |
309 | engine->instmem.resume(dev); | |
310 | engine->mc.init(dev); | |
311 | engine->timer.init(dev); | |
312 | engine->fb.init(dev); | |
6dfdd7a6 BS |
313 | for (i = 0; i < NVOBJ_ENGINE_NR; i++) { |
314 | if (dev_priv->eng[i]) | |
315 | dev_priv->eng[i]->init(dev, i); | |
316 | } | |
6ee73861 BS |
317 | engine->fifo.init(dev); |
318 | ||
6ee73861 BS |
319 | nouveau_irq_postinstall(dev); |
320 | ||
321 | /* Re-write SKIPS, they'll have been lost over the suspend */ | |
322 | if (nouveau_vram_pushbuf) { | |
323 | struct nouveau_channel *chan; | |
324 | int j; | |
325 | ||
326 | for (i = 0; i < dev_priv->engine.fifo.channels; i++) { | |
cff5c133 | 327 | chan = dev_priv->channels.ptr[i]; |
3c8868d3 | 328 | if (!chan || !chan->pushbuf_bo) |
6ee73861 BS |
329 | continue; |
330 | ||
331 | for (j = 0; j < NOUVEAU_DMA_SKIPS; j++) | |
332 | nouveau_bo_wr32(chan->pushbuf_bo, i, 0); | |
333 | } | |
334 | } | |
335 | ||
336 | NV_INFO(dev, "Restoring mode...\n"); | |
337 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
338 | struct nouveau_framebuffer *nouveau_fb; | |
339 | ||
340 | nouveau_fb = nouveau_framebuffer(crtc->fb); | |
341 | if (!nouveau_fb || !nouveau_fb->nvbo) | |
342 | continue; | |
343 | ||
344 | nouveau_bo_pin(nouveau_fb->nvbo, TTM_PL_FLAG_VRAM); | |
345 | } | |
346 | ||
b334f2b3 MM |
347 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
348 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
b334f2b3 MM |
349 | |
350 | ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM); | |
351 | if (!ret) | |
352 | ret = nouveau_bo_map(nv_crtc->cursor.nvbo); | |
353 | if (ret) | |
354 | NV_ERROR(dev, "Could not pin/map cursor.\n"); | |
355 | } | |
356 | ||
c88c2e06 | 357 | engine->display.init(dev); |
6ee73861 | 358 | |
b334f2b3 MM |
359 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
360 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
4c136142 | 361 | u32 offset = nv_crtc->cursor.nvbo->bo.mem.start << PAGE_SHIFT; |
b334f2b3 | 362 | |
4c136142 | 363 | nv_crtc->cursor.set_offset(nv_crtc, offset); |
b334f2b3 | 364 | nv_crtc->cursor.set_pos(nv_crtc, nv_crtc->cursor_saved_x, |
4c136142 | 365 | nv_crtc->cursor_saved_y); |
b334f2b3 MM |
366 | } |
367 | ||
6ee73861 BS |
368 | /* Force CLUT to get re-loaded during modeset */ |
369 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
370 | struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); | |
371 | ||
372 | nv_crtc->lut.depth = 0; | |
373 | } | |
374 | ||
ac751efa | 375 | console_lock(); |
38651674 | 376 | nouveau_fbcon_set_suspend(dev, 0); |
ac751efa | 377 | console_unlock(); |
6ee73861 | 378 | |
38651674 | 379 | nouveau_fbcon_zfill_all(dev); |
6ee73861 BS |
380 | |
381 | drm_helper_resume_force_mode(dev); | |
38651674 DA |
382 | |
383 | nouveau_fbcon_restore_accel(dev); | |
6ee73861 BS |
384 | return 0; |
385 | } | |
386 | ||
387 | static struct drm_driver driver = { | |
388 | .driver_features = | |
389 | DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG | | |
cd0b072f BS |
390 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | |
391 | DRIVER_MODESET, | |
6ee73861 BS |
392 | .load = nouveau_load, |
393 | .firstopen = nouveau_firstopen, | |
394 | .lastclose = nouveau_lastclose, | |
395 | .unload = nouveau_unload, | |
396 | .preclose = nouveau_preclose, | |
397 | #if defined(CONFIG_DRM_NOUVEAU_DEBUG) | |
398 | .debugfs_init = nouveau_debugfs_init, | |
399 | .debugfs_cleanup = nouveau_debugfs_takedown, | |
400 | #endif | |
401 | .irq_preinstall = nouveau_irq_preinstall, | |
402 | .irq_postinstall = nouveau_irq_postinstall, | |
403 | .irq_uninstall = nouveau_irq_uninstall, | |
404 | .irq_handler = nouveau_irq_handler, | |
042206c0 FJ |
405 | .get_vblank_counter = drm_vblank_count, |
406 | .enable_vblank = nouveau_vblank_enable, | |
407 | .disable_vblank = nouveau_vblank_disable, | |
6ee73861 | 408 | .reclaim_buffers = drm_core_reclaim_buffers, |
6ee73861 BS |
409 | .ioctls = nouveau_ioctls, |
410 | .fops = { | |
411 | .owner = THIS_MODULE, | |
412 | .open = drm_open, | |
413 | .release = drm_release, | |
ed8b6704 | 414 | .unlocked_ioctl = drm_ioctl, |
6ee73861 BS |
415 | .mmap = nouveau_ttm_mmap, |
416 | .poll = drm_poll, | |
417 | .fasync = drm_fasync, | |
042206c0 | 418 | .read = drm_read, |
6ee73861 BS |
419 | #if defined(CONFIG_COMPAT) |
420 | .compat_ioctl = nouveau_compat_ioctl, | |
421 | #endif | |
dc880abe | 422 | .llseek = noop_llseek, |
6ee73861 | 423 | }, |
6ee73861 BS |
424 | |
425 | .gem_init_object = nouveau_gem_object_new, | |
426 | .gem_free_object = nouveau_gem_object_del, | |
427 | ||
428 | .name = DRIVER_NAME, | |
429 | .desc = DRIVER_DESC, | |
430 | #ifdef GIT_REVISION | |
431 | .date = GIT_REVISION, | |
432 | #else | |
433 | .date = DRIVER_DATE, | |
434 | #endif | |
435 | .major = DRIVER_MAJOR, | |
436 | .minor = DRIVER_MINOR, | |
437 | .patchlevel = DRIVER_PATCHLEVEL, | |
438 | }; | |
439 | ||
8410ea3b DA |
440 | static struct pci_driver nouveau_pci_driver = { |
441 | .name = DRIVER_NAME, | |
442 | .id_table = pciidlist, | |
443 | .probe = nouveau_pci_probe, | |
444 | .remove = nouveau_pci_remove, | |
445 | .suspend = nouveau_pci_suspend, | |
446 | .resume = nouveau_pci_resume | |
447 | }; | |
448 | ||
6ee73861 BS |
449 | static int __init nouveau_init(void) |
450 | { | |
451 | driver.num_ioctls = nouveau_max_ioctl; | |
452 | ||
453 | if (nouveau_modeset == -1) { | |
454 | #ifdef CONFIG_VGA_CONSOLE | |
455 | if (vgacon_text_force()) | |
456 | nouveau_modeset = 0; | |
457 | else | |
458 | #endif | |
459 | nouveau_modeset = 1; | |
460 | } | |
461 | ||
cd0b072f BS |
462 | if (!nouveau_modeset) |
463 | return 0; | |
6ee73861 | 464 | |
cd0b072f | 465 | nouveau_register_dsm_handler(); |
8410ea3b | 466 | return drm_pci_init(&driver, &nouveau_pci_driver); |
6ee73861 BS |
467 | } |
468 | ||
469 | static void __exit nouveau_exit(void) | |
470 | { | |
cd0b072f BS |
471 | if (!nouveau_modeset) |
472 | return; | |
473 | ||
8410ea3b | 474 | drm_pci_exit(&driver, &nouveau_pci_driver); |
6a9ee8af | 475 | nouveau_unregister_dsm_handler(); |
6ee73861 BS |
476 | } |
477 | ||
478 | module_init(nouveau_init); | |
479 | module_exit(nouveau_exit); | |
480 | ||
481 | MODULE_AUTHOR(DRIVER_AUTHOR); | |
482 | MODULE_DESCRIPTION(DRIVER_DESC); | |
483 | MODULE_LICENSE("GPL and additional rights"); |