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drm/nouveau: disable hotplug detect around DP link training
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nouveau_dp.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2009 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include "drmP.h"
b01f0608 26
6ee73861
BS		 27#include "nouveau_drv.h"
28#include "nouveau_i2c.h"
b01f0608 29#include "nouveau_connector.h"
6ee73861
BS		 30#include "nouveau_encoder.h"
31
32static int
33auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
34{
35 struct drm_device *dev = encoder->dev;
36 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
37 struct nouveau_i2c_chan *auxch;
38 int ret;
39
40 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
41 if (!auxch)
42 return -ENODEV;
43
44 ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
45 if (ret)
46 return ret;
47
48 return 0;
49}
50
51static int
52auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
53{
54 struct drm_device *dev = encoder->dev;
55 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
56 struct nouveau_i2c_chan *auxch;
57 int ret;
58
59 auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
60 if (!auxch)
61 return -ENODEV;
62
63 ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
64 return ret;
65}
66
67static int
68nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
69{
70 struct drm_device *dev = encoder->dev;
71 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
72 uint32_t tmp;
73 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
74
75 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
76 tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
77 NV50_SOR_DP_CTRL_LANE_MASK);
78 tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
79 if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
80 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
81 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
82
83 return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
84}
85
86static int
87nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
88{
89 struct drm_device *dev = encoder->dev;
90 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
91 uint32_t tmp;
92 int reg = 0x614300 + (nv_encoder->or * 0x800);
93
94 tmp = nv_rd32(dev, reg);
95 tmp &= 0xfff3ffff;
96 if (cmd == DP_LINK_BW_2_7)
97 tmp |= 0x00040000;
98 nv_wr32(dev, reg, tmp);
99
100 return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
101}
102
103static int
104nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
105{
106 struct drm_device *dev = encoder->dev;
107 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
108 uint32_t tmp;
109 uint8_t cmd;
110 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
111 int ret;
112
113 tmp = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
114 tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
115 tmp |= (pattern << 24);
116 nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
117
118 ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
119 if (ret)
120 return ret;
121 cmd &= ~DP_TRAINING_PATTERN_MASK;
122 cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
123 return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
124}
125
126static int
127nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
128{
129 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
130 struct drm_device *dev = encoder->dev;
131 struct bit_displayport_encoder_table_entry *dpse;
132 struct bit_displayport_encoder_table *dpe;
133 int i, dpe_headerlen, max_vs = 0;
134
135 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
136 if (!dpe)
137 return false;
138 dpse = (void *)((char *)dpe + dpe_headerlen);
139
140 for (i = 0; i < dpe_headerlen; i++, dpse++) {
141 if (dpse->vs_level > max_vs)
142 max_vs = dpse->vs_level;
143 }
144
145 return max_vs;
146}
147
148static int
149nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
150{
151 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
152 struct drm_device *dev = encoder->dev;
153 struct bit_displayport_encoder_table_entry *dpse;
154 struct bit_displayport_encoder_table *dpe;
155 int i, dpe_headerlen, max_pre = 0;
156
157 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
158 if (!dpe)
159 return false;
160 dpse = (void *)((char *)dpe + dpe_headerlen);
161
162 for (i = 0; i < dpe_headerlen; i++, dpse++) {
163 if (dpse->vs_level != vs)
164 continue;
165
166 if (dpse->pre_level > max_pre)
167 max_pre = dpse->pre_level;
168 }
169
170 return max_pre;
171}
172
173static bool
174nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
175{
176 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
177 struct drm_device *dev = encoder->dev;
178 struct bit_displayport_encoder_table_entry *dpse;
179 struct bit_displayport_encoder_table *dpe;
180 int ret, i, dpe_headerlen, vs = 0, pre = 0;
181 uint8_t request[2];
182
183 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
184 if (!dpe)
185 return false;
186 dpse = (void *)((char *)dpe + dpe_headerlen);
187
188 ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
189 if (ret)
190 return false;
191
ef2bb506 192 NV_DEBUG_KMS(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
6ee73861
BS		 193
194 /* Keep all lanes at the same level.. */
195 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
196 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
197 int lane_vs = lane_req & 3;
198 int lane_pre = (lane_req >> 2) & 3;
199
200 if (lane_vs > vs)
201 vs = lane_vs;
202 if (lane_pre > pre)
203 pre = lane_pre;
204 }
205
206 if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
207 vs = nouveau_dp_max_voltage_swing(encoder);
208 vs |= 4;
209 }
210
211 if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
212 pre = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
213 pre |= 4;
214 }
215
216 /* Update the configuration for all lanes.. */
217 for (i = 0; i < nv_encoder->dp.link_nr; i++)
218 config[i] = (pre << 3) | vs;
219
220 return true;
221}
222
223static bool
224nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
225{
226 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
227 struct drm_device *dev = encoder->dev;
228 struct bit_displayport_encoder_table_entry *dpse;
229 struct bit_displayport_encoder_table *dpe;
230 int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
231 int dpe_headerlen, ret, i;
232
ef2bb506 233 NV_DEBUG_KMS(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
6ee73861
BS		 234 config[0], config[1], config[2], config[3]);
235
236 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
237 if (!dpe)
238 return false;
239 dpse = (void *)((char *)dpe + dpe_headerlen);
240
241 for (i = 0; i < dpe->record_nr; i++, dpse++) {
242 if (dpse->vs_level == (config[0] & 3) &&
243 dpse->pre_level == ((config[0] >> 3) & 3))
244 break;
245 }
246 BUG_ON(i == dpe->record_nr);
247
248 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
249 const int shift[4] = { 16, 8, 0, 24 };
250 uint32_t mask = 0xff << shift[i];
251 uint32_t reg0, reg1, reg2;
252
253 reg0 = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
254 reg0 |= (dpse->reg0 << shift[i]);
255 reg1 = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
256 reg1 |= (dpse->reg1 << shift[i]);
257 reg2 = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
258 reg2 |= (dpse->reg2 << 8);
259 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
260 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
261 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
262 }
263
264 ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
265 if (ret)
266 return false;
267
268 return true;
269}
270
271bool
272nouveau_dp_link_train(struct drm_encoder *encoder)
273{
274 struct drm_device *dev = encoder->dev;
275 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
b01f0608 276 struct nouveau_connector *nv_connector;
ea4718d1
BS		 277 struct bit_displayport_encoder_table *dpe;
278 int dpe_headerlen;
279 uint8_t config[4], status[3];
6ee73861
BS		 280 bool cr_done, cr_max_vs, eq_done;
281 int ret = 0, i, tries, voltage;
282
ef2bb506 283 NV_DEBUG_KMS(dev, "link training!!\n");
ea4718d1 284
b01f0608
BS		 285 nv_connector = nouveau_encoder_connector_get(nv_encoder);
286 if (!nv_connector)
287 return false;
288
ea4718d1
BS		 289 dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
290 if (!dpe) {
291 NV_ERROR(dev, "SOR-%d: no DP encoder table!\n", nv_encoder->or);
292 return false;
293 }
294
b01f0608
BS		 295 /* disable hotplug detect, this flips around on some panels during
296 * link training.
297 */
298 nv50_gpio_irq_enable(dev, nv_connector->dcb->gpio_tag, false);
299
ea4718d1
BS		 300 if (dpe->script0) {
301 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 0\n", nv_encoder->or);
302 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script0),
303 nv_encoder->dcb);
304 }
305
6ee73861
BS		 306train:
307 cr_done = eq_done = false;
308
309 /* set link configuration */
ef2bb506 310 NV_DEBUG_KMS(dev, "\tbegin train: bw %d, lanes %d\n",
6ee73861
BS		 311 nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
312
313 ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
314 if (ret)
315 return false;
316
317 config[0] = nv_encoder->dp.link_nr;
318 if (nv_encoder->dp.dpcd_version >= 0x11)
319 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
320
321 ret = nouveau_dp_lane_count_set(encoder, config[0]);
322 if (ret)
323 return false;
324
325 /* clock recovery */
ef2bb506 326 NV_DEBUG_KMS(dev, "\tbegin cr\n");
6ee73861
BS		 327 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
328 if (ret)
329 goto stop;
330
331 tries = 0;
332 voltage = -1;
333 memset(config, 0x00, sizeof(config));
334 for (;;) {
335 if (!nouveau_dp_link_train_commit(encoder, config))
336 break;
337
338 udelay(100);
339
340 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
341 if (ret)
342 break;
ef2bb506 343 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
6ee73861
BS		 344 status[0], status[1]);
345
346 cr_done = true;
347 cr_max_vs = false;
348 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
349 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
350
351 if (!(lane & DP_LANE_CR_DONE)) {
352 cr_done = false;
353 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
354 cr_max_vs = true;
355 break;
356 }
357 }
358
359 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
360 voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
361 tries = 0;
362 }
363
364 if (cr_done || cr_max_vs || (++tries == 5))
365 break;
366
367 if (!nouveau_dp_link_train_adjust(encoder, config))
368 break;
369 }
370
371 if (!cr_done)
372 goto stop;
373
374 /* channel equalisation */
ef2bb506 375 NV_DEBUG_KMS(dev, "\tbegin eq\n");
6ee73861
BS		 376 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
377 if (ret)
378 goto stop;
379
380 for (tries = 0; tries <= 5; tries++) {
381 udelay(400);
382
383 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
384 if (ret)
385 break;
ef2bb506 386 NV_DEBUG_KMS(dev, "\t\tstatus: 0x%02x 0x%02x\n",
6ee73861
BS		 387 status[0], status[1]);
388
389 eq_done = true;
390 if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
391 eq_done = false;
392
393 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
394 int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
395
396 if (!(lane & DP_LANE_CR_DONE)) {
397 cr_done = false;
398 break;
399 }
400
401 if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
402 !(lane & DP_LANE_SYMBOL_LOCKED)) {
403 eq_done = false;
404 break;
405 }
406 }
407
408 if (eq_done || !cr_done)
409 break;
410
411 if (!nouveau_dp_link_train_adjust(encoder, config) ||
412 !nouveau_dp_link_train_commit(encoder, config))
413 break;
414 }
415
416stop:
417 /* end link training */
418 ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
419 if (ret)
420 return false;
421
422 /* retry at a lower setting, if possible */
423 if (!ret && !(eq_done && cr_done)) {
ef2bb506 424 NV_DEBUG_KMS(dev, "\twe failed\n");
6ee73861 425 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
ef2bb506 426 NV_DEBUG_KMS(dev, "retry link training at low rate\n");
6ee73861
BS		 427 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
428 goto train;
429 }
430 }
431
ea4718d1
BS		 432 if (dpe->script1) {
433 NV_DEBUG_KMS(dev, "SOR-%d: running DP script 1\n", nv_encoder->or);
434 nouveau_bios_run_init_table(dev, le16_to_cpu(dpe->script1),
435 nv_encoder->dcb);
436 }
437
b01f0608
BS		 438 /* re-enable hotplug detect */
439 nv50_gpio_irq_enable(dev, nv_connector->dcb->gpio_tag, true);
440
6ee73861
BS		 441 return eq_done;
442}
443
444bool
445nouveau_dp_detect(struct drm_encoder *encoder)
446{
447 struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
448 struct drm_device *dev = encoder->dev;
449 uint8_t dpcd[4];
450 int ret;
451
452 ret = auxch_rd(encoder, 0x0000, dpcd, 4);
453 if (ret)
454 return false;
455
ef2bb506 456 NV_DEBUG_KMS(dev, "encoder: link_bw %d, link_nr %d\n"
6ee73861
BS		 457 "display: link_bw %d, link_nr %d version 0x%02x\n",
458 nv_encoder->dcb->dpconf.link_bw,
459 nv_encoder->dcb->dpconf.link_nr,
460 dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
461
462 nv_encoder->dp.dpcd_version = dpcd[0];
463
464 nv_encoder->dp.link_bw = dpcd[1];
465 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
466 !nv_encoder->dcb->dpconf.link_bw)
467 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
468
469 nv_encoder->dp.link_nr = dpcd[2] & 0xf;
470 if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
471 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
472
473 return true;
474}
475
476int
477nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
478 uint8_t *data, int data_nr)
479{
480 struct drm_device *dev = auxch->dev;
481 uint32_t tmp, ctrl, stat = 0, data32[4] = {};
482 int ret = 0, i, index = auxch->rd;
483
ef2bb506 484 NV_DEBUG_KMS(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
6ee73861
BS		 485
486 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
487 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
488 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
489 if (!(tmp & 0x01000000)) {
490 NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
491 ret = -EIO;
492 goto out;
493 }
494
495 for (i = 0; i < 3; i++) {
496 tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
497 if (tmp & NV50_AUXCH_STAT_STATE_READY)
498 break;
499 udelay(100);
500 }
501
502 if (i == 3) {
503 ret = -EBUSY;
504 goto out;
505 }
506
507 if (!(cmd & 1)) {
508 memcpy(data32, data, data_nr);
509 for (i = 0; i < 4; i++) {
ef2bb506 510 NV_DEBUG_KMS(dev, "wr %d: 0x%08x\n", i, data32[i]);
6ee73861
BS		 511 nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
512 }
513 }
514
515 nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
516 ctrl = nv_rd32(dev, NV50_AUXCH_CTRL(index));
517 ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
518 ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
519 ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
520
8e024f13 521 for (i = 0; i < 16; i++) {
6ee73861
BS		 522 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
523 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
524 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
525 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
526 NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
527 nv_rd32(dev, NV50_AUXCH_CTRL(index)));
0107bae0
BS		 528 ret = -EBUSY;
529 goto out;
6ee73861
BS		 530 }
531
532 udelay(400);
533
534 stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
535 if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
536 NV50_AUXCH_STAT_REPLY_AUX_DEFER)
537 break;
538 }
539
8e024f13
BS		 540 if (i == 16) {
541 NV_ERROR(dev, "auxch DEFER too many times, bailing\n");
542 ret = -EREMOTEIO;
543 goto out;
544 }
545
6ee73861 546 if (cmd & 1) {
1ee7698f
BS		 547 if ((stat & NV50_AUXCH_STAT_COUNT) != data_nr) {
548 ret = -EREMOTEIO;
549 goto out;
550 }
551
6ee73861
BS		 552 for (i = 0; i < 4; i++) {
553 data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
ef2bb506 554 NV_DEBUG_KMS(dev, "rd %d: 0x%08x\n", i, data32[i]);
6ee73861
BS		 555 }
556 memcpy(data, data32, data_nr);
557 }
558
559out:
560 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
561 nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
562 tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
563 if (tmp & 0x01000000) {
564 NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
565 ret = -EIO;
566 }
567
568 udelay(400);
569
570 return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
571}
572
573int
574nouveau_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
575 uint8_t write_byte, uint8_t *read_byte)
576{
577 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
578 struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adapter;
579 struct drm_device *dev = auxch->dev;
580 int ret = 0, cmd, addr = algo_data->address;
581 uint8_t *buf;
582
583 if (mode == MODE_I2C_READ) {
584 cmd = AUX_I2C_READ;
585 buf = read_byte;
586 } else {
587 cmd = (mode & MODE_I2C_READ) ? AUX_I2C_READ : AUX_I2C_WRITE;
588 buf = &write_byte;
589 }
590
591 if (!(mode & MODE_I2C_STOP))
592 cmd |= AUX_I2C_MOT;
593
594 if (mode & MODE_I2C_START)
595 return 1;
596
597 for (;;) {
598 ret = nouveau_dp_auxch(auxch, cmd, addr, buf, 1);
599 if (ret < 0)
600 return ret;
601
602 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
603 case NV50_AUXCH_STAT_REPLY_I2C_ACK:
604 return 1;
605 case NV50_AUXCH_STAT_REPLY_I2C_NACK:
606 return -EREMOTEIO;
607 case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
608 udelay(100);
609 break;
610 default:
611 NV_ERROR(dev, "invalid auxch status: 0x%08x\n", ret);
612 return -EREMOTEIO;
613 }
614 }
615}
616
kernel source for telekom puls (alcatel/mediatek)