[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / gpu / drm / nouveau / nouveau_dp.c

/*
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <drm/drmP.h>
#include <drm/drm_dp_helper.h>

#include "nouveau_drm.h"
#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"

#include <core/class.h>

#include <subdev/gpio.h>
#include <subdev/i2c.h>

/******************************************************************************
 * link training
 *****************************************************************************/
struct dp_state {
	struct nouveau_i2c_port *auxch;
	struct nouveau_object *core;
	struct dcb_output *dcb;
	int crtc;
	u8 *dpcd;
	int link_nr;
	u32 link_bw;
	u8  stat[6];
	u8  conf[4];
};

static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
	u8 sink[2];
	u32 data;

	NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);

	/* set desired link configuration on the source */
	data = ((dp->link_bw / 27000) << 8) | dp->link_nr;
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
		data |= NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH;

	nv_call(dp->core, NV94_DISP_SOR_DP_LNKCTL + moff, data);

	/* inform the sink of the new configuration */
	sink[0] = dp->link_bw / 27000;
	sink[1] = dp->link_nr;
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
		sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
}

static void
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
	u8 sink_tp;

	NV_DEBUG(drm, "training pattern %d\n", pattern);

	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, pattern);

	nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
	sink_tp |= pattern;
	nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
}

static int
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;
	int i;

	for (i = 0; i < dp->link_nr; i++) {
		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 lpre = (lane & 0x0c) >> 2;
		u8 lvsw = (lane & 0x03) >> 0;

		dp->conf[i] = (lpre << 3) | lvsw;
		if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
			dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
		if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
			dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

		NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);

		nv_call(dp->core, NV94_DISP_SOR_DP_DRVCTL(i) + moff, (lvsw << 8) | lpre);
	}

	return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
}

static int
dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	int ret;

	udelay(delay);

	ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
	if (ret)
		return ret;

	NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
	return 0;
}

static int
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
{
	bool cr_done = false, abort = false;
	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);

	do {
		if (dp_link_train_commit(dev, dp) ||
		    dp_link_train_update(dev, dp, 100))
			break;

		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE)) {
				cr_done = false;
				if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
					abort = true;
				break;
			}
		}

		if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
			voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
			tries = 0;
		}
	} while (!cr_done && !abort && ++tries < 5);

	return cr_done ? 0 : -1;
}

static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
{
	bool eq_done, cr_done = true;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);

	do {
		if (dp_link_train_update(dev, dp, 400))
			break;

		eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE))
				cr_done = false;
			if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
			    !(lane & DP_LANE_SYMBOL_LOCKED))
				eq_done = false;
		}

		if (dp_link_train_commit(dev, dp))
			break;
	} while (!eq_done && cr_done && ++tries <= 5);

	return eq_done ? 0 : -1;
}

static void
dp_link_train_init(struct drm_device *dev, struct dp_state *dp, bool spread)
{
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;

	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, (spread ?
			  NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON :
			  NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF) |
			  NV94_DISP_SOR_DP_TRAIN_OP_INIT);
}

static void
dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
{
	struct dcb_output *dcb = dp->dcb;
	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	const u32 moff = (dp->crtc << 3) | (link << 2) | or;

	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff,
			  NV94_DISP_SOR_DP_TRAIN_OP_FINI);
}

static bool
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
		      struct nouveau_object *core)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector =
		nouveau_encoder_connector_get(nv_encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
	const u32 bw_list[] = { 270000, 162000, 0 };
	const u32 *link_bw = bw_list;
	struct dp_state dp;

	dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
	if (!dp.auxch)
		return false;

	dp.core = core;
	dp.dcb = nv_encoder->dcb;
	dp.crtc = nv_crtc->index;
	dp.dpcd = nv_encoder->dp.dpcd;

	/* adjust required bandwidth for 8B/10B coding overhead */
	datarate = (datarate / 8) * 10;

	/* some sinks toggle hotplug in response to some of the actions
	 * we take during link training (DP_SET_POWER is one), we need
	 * to ignore them for the moment to avoid races.
	 */
	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);

	/* enable down-spreading and execute pre-train script from vbios */
	dp_link_train_init(dev, &dp, nv_encoder->dp.dpcd[3] & 1);

	/* start off at highest link rate supported by encoder and display */
	while (*link_bw > nv_encoder->dp.link_bw)
		link_bw++;

	while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp.link_nr = nv_encoder->dp.link_nr;
		while ((dp.link_nr >> 1) * link_bw[0] > datarate)
			dp.link_nr >>= 1;

		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp.link_nr) > datarate)
			link_bw++;
		dp.link_bw = link_bw[0];

		/* program selected link configuration */
		dp_set_link_config(dev, &dp);

		/* attempt to train the link at this configuration */
		memset(dp.stat, 0x00, sizeof(dp.stat));
		if (!dp_link_train_cr(dev, &dp) &&
		    !dp_link_train_eq(dev, &dp))
			break;

		/* retry at lower rate */
		link_bw++;
	}

	/* finish link training */
	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);

	/* execute post-train script from vbios */
	dp_link_train_fini(dev, &dp);

	/* re-enable hotplug detect */
	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
	return true;
}

void
nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
		struct nouveau_object *core)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_i2c_port *auxch;
	u8 status;

	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return;

	if (mode == DRM_MODE_DPMS_ON)
		status = DP_SET_POWER_D0;
	else
		status = DP_SET_POWER_D3;

	nv_wraux(auxch, DP_SET_POWER, &status, 1);

	if (mode == DRM_MODE_DPMS_ON)
		nouveau_dp_link_train(encoder, datarate, core);
}

static void
nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
		     u8 *dpcd)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	u8 buf[3];

	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

	if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
		NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

	if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
		NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

}

bool
nouveau_dp_detect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_i2c_port *auxch;
	u8 *dpcd = nv_encoder->dp.dpcd;
	int ret;

	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return false;

	ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
	if (ret)
		return false;

	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;

	NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	NV_DEBUG(drm, "encoder: %dx%d\n",
		     nv_encoder->dcb->dpconf.link_nr,
		     nv_encoder->dcb->dpconf.link_bw);

	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
		nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
		nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;

	NV_DEBUG(drm, "maximum: %dx%d\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);

	nouveau_dp_probe_oui(dev, auxch, dpcd);

	return true;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2009 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
760285e7	25	#include <drm/drmP.h>
612a9aab	26	#include <drm/drm_dp_helper.h>
b01f0608	27
77145f1c	28	#include "nouveau_drm.h"
b01f0608	29	#include "nouveau_connector.h"
6ee73861	30	#include "nouveau_encoder.h"
27a45987	31	#include "nouveau_crtc.h"
6ee73861	32
6c8e4633 BS	33	#include <core/class.h>
6c8e4633 BS	34
77145f1c BS	35	#include <subdev/gpio.h>
77145f1c BS	36	#include <subdev/i2c.h>
43720133	37
27a45987 BS	38	/******************************************************************************
	39	* link training
	40	*****************************************************************************/
	41	struct dp_state {
4196faa8	42	struct nouveau_i2c_port *auxch;
6c8e4633	43	struct nouveau_object *core;
cb75d97e	44	struct dcb_output *dcb;
27a45987	45	int crtc;
52e0d0ec	46	u8 *dpcd;
27a45987 BS	47	int link_nr;
	48	u32 link_bw;
	49	u8 stat[6];
	50	u8 conf[4];
	51	};
6ee73861	52
27a45987 BS	53	static void
27a45987 BS	54	dp_set_link_config(struct drm_device dev, struct dp_state dp)
6ee73861	55	{
77145f1c	56	struct nouveau_drm *drm = nouveau_drm(dev);
6c8e4633 BS	57	struct dcb_output *dcb = dp->dcb;
	58	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	59	const u32 moff = (dp->crtc << 3) \| (link << 2) \| or;
8663bc7c	60	u8 sink[2];
6c8e4633	61	u32 data;
6ee73861	62
77145f1c	63	NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
6ee73861	64
8663bc7c	65	/* set desired link configuration on the source */
6c8e4633 BS	66	data = ((dp->link_bw / 27000) << 8) \| dp->link_nr;
	67	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
	68	data \|= NV94_DISP_SOR_DP_LNKCTL_FRAME_ENH;
	69
	70	nv_call(dp->core, NV94_DISP_SOR_DP_LNKCTL + moff, data);
28e2d124	71
8663bc7c BS	72	/* inform the sink of the new configuration */
8663bc7c BS	73	sink[0] = dp->link_bw / 27000;
27a45987	74	sink[1] = dp->link_nr;
8663bc7c	75	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
27a45987	76	sink[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
6ee73861	77
77145f1c	78	nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
6ee73861 BS	79	}
6ee73861 BS	80
27a45987	81	static void
8663bc7c	82	dp_set_training_pattern(struct drm_device dev, struct dp_state dp, u8 pattern)
6ee73861	83	{
77145f1c	84	struct nouveau_drm *drm = nouveau_drm(dev);
6c8e4633 BS	85	struct dcb_output *dcb = dp->dcb;
	86	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	87	const u32 moff = (dp->crtc << 3) \| (link << 2) \| or;
5b3eb95f BS	88	u8 sink_tp;
5b3eb95f BS	89
77145f1c	90	NV_DEBUG(drm, "training pattern %d\n", pattern);
5b3eb95f	91
6c8e4633	92	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, pattern);
5b3eb95f	93
77145f1c	94	nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
5b3eb95f	95	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
8663bc7c	96	sink_tp \|= pattern;
77145f1c	97	nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
6ee73861 BS	98	}
	99
	100	static int
27a45987	101	dp_link_train_commit(struct drm_device dev, struct dp_state dp)
6ee73861	102	{
77145f1c	103	struct nouveau_drm *drm = nouveau_drm(dev);
6c8e4633 BS	104	struct dcb_output *dcb = dp->dcb;
	105	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	106	const u32 moff = (dp->crtc << 3) \| (link << 2) \| or;
27a45987 BS	107	int i;
27a45987 BS	108
27a45987	109	for (i = 0; i < dp->link_nr; i++) {
c16a3a35 BS	110	u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
	111	u8 lpre = (lane & 0x0c) >> 2;
	112	u8 lvsw = (lane & 0x03) >> 0;
6ee73861	113
c16a3a35 BS	114	dp->conf[i] = (lpre << 3) \| lvsw;
c16a3a35 BS	115	if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
27a45987	116	dp->conf[i] \|= DP_TRAIN_MAX_SWING_REACHED;
44ab8cc5	117	if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
27a45987	118	dp->conf[i] \|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
6ee73861	119
77145f1c	120	NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
6c8e4633 BS	121
6c8e4633 BS	122	nv_call(dp->core, NV94_DISP_SOR_DP_DRVCTL(i) + moff, (lvsw << 8) \| lpre);
6ee73861 BS	123	}
6ee73861 BS	124
77145f1c	125	return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
6ee73861 BS	126	}
6ee73861 BS	127
27a45987 BS	128	static int
27a45987 BS	129	dp_link_train_update(struct drm_device dev, struct dp_state dp, u32 delay)
6ee73861	130	{
77145f1c	131	struct nouveau_drm *drm = nouveau_drm(dev);
27a45987	132	int ret;
6ee73861	133
27a45987	134	udelay(delay);
6ee73861	135
77145f1c	136	ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
6ee73861	137	if (ret)
27a45987	138	return ret;
6ee73861	139
268d2837	140	NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
27a45987 BS	141	return 0;
27a45987 BS	142	}
6ee73861	143
27a45987 BS	144	static int
	145	dp_link_train_cr(struct drm_device dev, struct dp_state dp)
	146	{
	147	bool cr_done = false, abort = false;
	148	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	149	int tries = 0, i;
6ee73861	150
27a45987	151	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
6ee73861	152
27a45987 BS	153	do {
	154	if (dp_link_train_commit(dev, dp) \|\|
	155	dp_link_train_update(dev, dp, 100))
	156	break;
6ee73861	157
27a45987 BS	158	cr_done = true;
	159	for (i = 0; i < dp->link_nr; i++) {
	160	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	161	if (!(lane & DP_LANE_CR_DONE)) {
	162	cr_done = false;
	163	if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
	164	abort = true;
	165	break;
	166	}
	167	}
6ee73861	168
27a45987 BS	169	if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
	170	voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	171	tries = 0;
	172	}
	173	} while (!cr_done && !abort && ++tries < 5);
6ee73861	174
27a45987	175	return cr_done ? 0 : -1;
6ee73861 BS	176	}
6ee73861 BS	177
27a45987 BS	178	static int
27a45987 BS	179	dp_link_train_eq(struct drm_device dev, struct dp_state dp)
6ee73861	180	{
27a45987 BS	181	bool eq_done, cr_done = true;
27a45987 BS	182	int tries = 0, i;
6ee73861	183
27a45987	184	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
6ee73861	185
27a45987 BS	186	do {
27a45987 BS	187	if (dp_link_train_update(dev, dp, 400))
6ee73861	188	break;
6ee73861	189
27a45987 BS	190	eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
	191	for (i = 0; i < dp->link_nr && eq_done; i++) {
	192	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	193	if (!(lane & DP_LANE_CR_DONE))
	194	cr_done = false;
	195	if (!(lane & DP_LANE_CHANNEL_EQ_DONE) \|\|
	196	!(lane & DP_LANE_SYMBOL_LOCKED))
	197	eq_done = false;
	198	}
6ee73861	199
27a45987 BS	200	if (dp_link_train_commit(dev, dp))
	201	break;
	202	} while (!eq_done && cr_done && ++tries <= 5);
	203
	204	return eq_done ? 0 : -1;
6ee73861 BS	205	}
6ee73861 BS	206
8c1dcb65	207	static void
8f2abc25	208	dp_link_train_init(struct drm_device dev, struct dp_state dp, bool spread)
8c1dcb65	209	{
8f2abc25 BS	210	struct dcb_output *dcb = dp->dcb;
	211	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	212	const u32 moff = (dp->crtc << 3) \| (link << 2) \| or;
8c1dcb65	213
8f2abc25 BS	214	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff, (spread ?
	215	NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_ON :
	216	NV94_DISP_SOR_DP_TRAIN_INIT_SPREAD_OFF) \|
	217	NV94_DISP_SOR_DP_TRAIN_OP_INIT);
8c1dcb65 BS	218	}
	219
	220	static void
	221	dp_link_train_fini(struct drm_device dev, struct dp_state dp)
	222	{
8f2abc25 BS	223	struct dcb_output *dcb = dp->dcb;
	224	const u32 or = ffs(dcb->or) - 1, link = !(dcb->sorconf.link & 1);
	225	const u32 moff = (dp->crtc << 3) \| (link << 2) \| or;
8c1dcb65	226
8f2abc25 BS	227	nv_call(dp->core, NV94_DISP_SOR_DP_TRAIN + moff,
8f2abc25 BS	228	NV94_DISP_SOR_DP_TRAIN_OP_FINI);
8c1dcb65 BS	229	}
8c1dcb65 BS	230
5b8a43ae	231	static bool
8663bc7c	232	nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
6c8e4633	233	struct nouveau_object *core)
6ee73861	234	{
6ee73861	235	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
27a45987 BS	236	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	237	struct nouveau_connector *nv_connector =
	238	nouveau_encoder_connector_get(nv_encoder);
	239	struct drm_device *dev = encoder->dev;
77145f1c BS	240	struct nouveau_drm *drm = nouveau_drm(dev);
	241	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	242	struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
27a45987 BS	243	const u32 bw_list[] = { 270000, 162000, 0 };
	244	const u32 *link_bw = bw_list;
	245	struct dp_state dp;
6ee73861	246
77145f1c	247	dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
4196faa8	248	if (!dp.auxch)
6ee73861 BS	249	return false;
6ee73861 BS	250
6c8e4633	251	dp.core = core;
27a45987 BS	252	dp.dcb = nv_encoder->dcb;
27a45987 BS	253	dp.crtc = nv_crtc->index;
52e0d0ec	254	dp.dpcd = nv_encoder->dp.dpcd;
6ee73861	255
6860dc82 BS	256	/* adjust required bandwidth for 8B/10B coding overhead */
	257	datarate = (datarate / 8) * 10;
	258
27a45987 BS	259	/* some sinks toggle hotplug in response to some of the actions
	260	* we take during link training (DP_SET_POWER is one), we need
	261	* to ignore them for the moment to avoid races.
	262	*/
77145f1c	263	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);
6ee73861	264
8f2abc25 BS	265	/* enable down-spreading and execute pre-train script from vbios */
8f2abc25 BS	266	dp_link_train_init(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
6ee73861	267
27a45987	268	/* start off at highest link rate supported by encoder and display */
75a1fccf	269	while (*link_bw > nv_encoder->dp.link_bw)
27a45987	270	link_bw++;
6ee73861	271
27a45987 BS	272	while (link_bw[0]) {
	273	/* find minimum required lane count at this link rate */
	274	dp.link_nr = nv_encoder->dp.link_nr;
	275	while ((dp.link_nr >> 1) * link_bw[0] > datarate)
	276	dp.link_nr >>= 1;
6ee73861	277
27a45987 BS	278	/* drop link rate to minimum with this lane count */
	279	while ((link_bw[1] * dp.link_nr) > datarate)
	280	link_bw++;
	281	dp.link_bw = link_bw[0];
6ee73861	282
27a45987 BS	283	/* program selected link configuration */
27a45987 BS	284	dp_set_link_config(dev, &dp);
6ee73861	285
27a45987 BS	286	/* attempt to train the link at this configuration */
	287	memset(dp.stat, 0x00, sizeof(dp.stat));
	288	if (!dp_link_train_cr(dev, &dp) &&
	289	!dp_link_train_eq(dev, &dp))
6ee73861 BS	290	break;
6ee73861 BS	291
27a45987 BS	292	/* retry at lower rate */
27a45987 BS	293	link_bw++;
6ee73861 BS	294	}
6ee73861 BS	295
27a45987 BS	296	/* finish link training */
27a45987 BS	297	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
6ee73861	298
27a45987	299	/* execute post-train script from vbios */
8c1dcb65	300	dp_link_train_fini(dev, &dp);
ea4718d1	301
b01f0608	302	/* re-enable hotplug detect */
77145f1c	303	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
27a45987	304	return true;
6ee73861 BS	305	}
6ee73861 BS	306
f14d9a4d BS	307	void
f14d9a4d BS	308	nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
6c8e4633	309	struct nouveau_object *core)
f14d9a4d BS	310	{
f14d9a4d BS	311	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
77145f1c BS	312	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
77145f1c BS	313	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
4196faa8	314	struct nouveau_i2c_port *auxch;
f14d9a4d BS	315	u8 status;
f14d9a4d BS	316
77145f1c	317	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
f14d9a4d BS	318	if (!auxch)
	319	return;
	320
	321	if (mode == DRM_MODE_DPMS_ON)
	322	status = DP_SET_POWER_D0;
	323	else
	324	status = DP_SET_POWER_D3;
	325
77145f1c	326	nv_wraux(auxch, DP_SET_POWER, &status, 1);
f14d9a4d BS	327
f14d9a4d BS	328	if (mode == DRM_MODE_DPMS_ON)
6c8e4633	329	nouveau_dp_link_train(encoder, datarate, core);
f14d9a4d BS	330	}
f14d9a4d BS	331
6225ee05	332	static void
4196faa8	333	nouveau_dp_probe_oui(struct drm_device dev, struct nouveau_i2c_port auxch,
6225ee05 AJ	334	u8 *dpcd)
6225ee05 AJ	335	{
77145f1c	336	struct nouveau_drm *drm = nouveau_drm(dev);
6225ee05 AJ	337	u8 buf[3];
	338
	339	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
	340	return;
	341
77145f1c BS	342	if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
77145f1c BS	343	NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
6225ee05 AJ	344	buf[0], buf[1], buf[2]);
6225ee05 AJ	345
77145f1c BS	346	if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
77145f1c BS	347	NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
6225ee05 AJ	348	buf[0], buf[1], buf[2]);
	349
	350	}
	351
6ee73861 BS	352	bool
	353	nouveau_dp_detect(struct drm_encoder *encoder)
	354	{
	355	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	356	struct drm_device *dev = encoder->dev;
77145f1c BS	357	struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c BS	358	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
4196faa8	359	struct nouveau_i2c_port *auxch;
52e0d0ec	360	u8 *dpcd = nv_encoder->dp.dpcd;
6ee73861 BS	361	int ret;
6ee73861 BS	362
77145f1c	363	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
52e0d0ec BS	364	if (!auxch)
	365	return false;
	366
77145f1c	367	ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
6ee73861 BS	368	if (ret)
	369	return false;
	370
75a1fccf BS	371	nv_encoder->dp.link_bw = 27000 * dpcd[1];
75a1fccf BS	372	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
6ee73861	373
77145f1c	374	NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
75a1fccf	375	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
77145f1c	376	NV_DEBUG(drm, "encoder: %dx%d\n",
75a1fccf BS	377	nv_encoder->dcb->dpconf.link_nr,
75a1fccf BS	378	nv_encoder->dcb->dpconf.link_bw);
6ee73861	379
75a1fccf	380	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
6ee73861	381	nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
75a1fccf BS	382	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
75a1fccf BS	383	nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
6ee73861	384
77145f1c	385	NV_DEBUG(drm, "maximum: %dx%d\n",
75a1fccf	386	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
fe224bb7	387
6225ee05 AJ	388	nouveau_dp_probe_oui(dev, auxch, dpcd);
6225ee05 AJ	389
6ee73861 BS	390	return true;
6ee73861 BS	391	}