[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / nouveau / nouveau_dp.c

/*
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <drm/drmP.h>

#include "nouveau_drv.h"
#include "nouveau_i2c.h"
#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"
#include "nouveau_gpio.h"

/******************************************************************************
 * aux channel util functions
 *****************************************************************************/
#define AUX_DBG(fmt, args...) do {                                             \
	if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) {                     \
		NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args);     \
	}                                                                      \
} while (0)
#define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)

static void
auxch_fini(struct drm_device *dev, int ch)
{
	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
}

static int
auxch_init(struct drm_device *dev, int ch)
{
	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
	const u32 urep = unksel ? 0x01000000 : 0x02000000;
	u32 ctrl, timeout;

	/* wait up to 1ms for any previous transaction to be done... */
	timeout = 1000;
	do {
		ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("begin idle timeout 0x%08x", ctrl);
			return -EBUSY;
		}
	} while (ctrl & 0x03010000);

	/* set some magic, and wait up to 1ms for it to appear */
	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
	timeout = 1000;
	do {
		ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
		udelay(1);
		if (!timeout--) {
			AUX_ERR("magic wait 0x%08x\n", ctrl);
			auxch_fini(dev, ch);
			return -EBUSY;
		}
	} while ((ctrl & 0x03000000) != urep);

	return 0;
}

static int
auxch_tx(struct drm_device *dev, int ch, u8 type, u32 addr, u8 *data, u8 size)
{
	u32 ctrl, stat, timeout, retries;
	u32 xbuf[4] = {};
	int ret, i;

	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);

	ret = auxch_init(dev, ch);
	if (ret)
		goto out;

	stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
	if (!(stat & 0x10000000)) {
		AUX_DBG("sink not detected\n");
		ret = -ENXIO;
		goto out;
	}

	if (!(type & 1)) {
		memcpy(xbuf, data, size);
		for (i = 0; i < 16; i += 4) {
			AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
			nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
		}
	}

	ctrl  = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
	ctrl &= ~0x0001f0ff;
	ctrl |= type << 12;
	ctrl |= size - 1;
	nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);

	/* retry transaction a number of times on failure... */
	ret = -EREMOTEIO;
	for (retries = 0; retries < 32; retries++) {
		/* reset, and delay a while if this is a retry */
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 | ctrl);
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 | ctrl);
		if (retries)
			udelay(400);

		/* transaction request, wait up to 1ms for it to complete */
		nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 | ctrl);

		timeout = 1000;
		do {
			ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
			udelay(1);
			if (!timeout--) {
				AUX_ERR("tx req timeout 0x%08x\n", ctrl);
				goto out;
			}
		} while (ctrl & 0x00010000);

		/* read status, and check if transaction completed ok */
		stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
		if (!(stat & 0x000f0f00)) {
			ret = 0;
			break;
		}

		AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
	}

	if (type & 1) {
		for (i = 0; i < 16; i += 4) {
			xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
			AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
		}
		memcpy(data, xbuf, size);
	}

out:
	auxch_fini(dev, ch);
	return ret;
}

u8 *
nouveau_dp_bios_data(struct drm_device *dev, struct dcb_entry *dcb, u8 **entry)
{
	struct bit_entry d;
	u8 *table;
	int i;

	if (bit_table(dev, 'd', &d)) {
		NV_ERROR(dev, "BIT 'd' table not found\n");
		return NULL;
	}

	if (d.version != 1) {
		NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
		return NULL;
	}

	table = ROMPTR(dev, d.data[0]);
	if (!table) {
		NV_ERROR(dev, "displayport table pointer invalid\n");
		return NULL;
	}

	switch (table[0]) {
	case 0x20:
	case 0x21:
	case 0x30:
	case 0x40:
		break;
	default:
		NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
		return NULL;
	}

	for (i = 0; i < table[3]; i++) {
		*entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
		if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
			return table;
	}

	NV_ERROR(dev, "displayport encoder table not found\n");
	return NULL;
}

/******************************************************************************
 * link training
 *****************************************************************************/
struct dp_state {
	struct dp_train_func *func;
	struct dcb_entry *dcb;
	int auxch;
	int crtc;
	u8 *dpcd;
	int link_nr;
	u32 link_bw;
	u8  stat[6];
	u8  conf[4];
};

static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
{
	u8 sink[2];

	NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);

	/* set desired link configuration on the source */
	dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
			   dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);

	/* inform the sink of the new configuration */
	sink[0] = dp->link_bw / 27000;
	sink[1] = dp->link_nr;
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
		sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
}

static void
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
{
	u8 sink_tp;

	NV_DEBUG_KMS(dev, "training pattern %d\n", pattern);

	dp->func->train_set(dev, dp->dcb, pattern);

	auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
	sink_tp |= pattern;
	auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
}

static int
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
{
	int i;

	for (i = 0; i < dp->link_nr; i++) {
		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 lpre = (lane & 0x0c) >> 2;
		u8 lvsw = (lane & 0x03) >> 0;

		dp->conf[i] = (lpre << 3) | lvsw;
		if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
			dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
		if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
			dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

		NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
		dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
	}

	return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
}

static int
dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
{
	int ret;

	udelay(delay);

	ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
	if (ret)
		return ret;

	NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
		     dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
		     dp->stat[4], dp->stat[5]);
	return 0;
}

static int
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
{
	bool cr_done = false, abort = false;
	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);

	do {
		if (dp_link_train_commit(dev, dp) ||
		    dp_link_train_update(dev, dp, 100))
			break;

		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE)) {
				cr_done = false;
				if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
					abort = true;
				break;
			}
		}

		if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
			voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
			tries = 0;
		}
	} while (!cr_done && !abort && ++tries < 5);

	return cr_done ? 0 : -1;
}

static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
{
	bool eq_done, cr_done = true;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);

	do {
		if (dp_link_train_update(dev, dp, 400))
			break;

		eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE))
				cr_done = false;
			if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
			    !(lane & DP_LANE_SYMBOL_LOCKED))
				eq_done = false;
		}

		if (dp_link_train_commit(dev, dp))
			break;
	} while (!eq_done && cr_done && ++tries <= 5);

	return eq_done ? 0 : -1;
}

static void
dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30) {
			if (enable) script = ROM16(entry[12]);
			else        script = ROM16(entry[14]);
		} else
		if (table[0] == 0x40) {
			if (enable) script = ROM16(entry[11]);
			else        script = ROM16(entry[13]);
		}
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[6]);
		else
		if (table[0] == 0x40)
			script = ROM16(entry[5]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[8]);
		else
		if (table[0] == 0x40)
			script = ROM16(entry[7]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

bool
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
		      struct dp_train_func *func)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector =
		nouveau_encoder_connector_get(nv_encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_i2c_chan *auxch;
	const u32 bw_list[] = { 270000, 162000, 0 };
	const u32 *link_bw = bw_list;
	struct dp_state dp;

	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return false;

	dp.func = func;
	dp.dcb = nv_encoder->dcb;
	dp.crtc = nv_crtc->index;
	dp.auxch = auxch->drive;
	dp.dpcd = nv_encoder->dp.dpcd;

	/* adjust required bandwidth for 8B/10B coding overhead */
	datarate = (datarate / 8) * 10;

	/* some sinks toggle hotplug in response to some of the actions
	 * we take during link training (DP_SET_POWER is one), we need
	 * to ignore them for the moment to avoid races.
	 */
	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);

	/* enable down-spreading, if possible */
	dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);

	/* execute pre-train script from vbios */
	dp_link_train_init(dev, &dp);

	/* start off at highest link rate supported by encoder and display */
	while (*link_bw > nv_encoder->dp.link_bw)
		link_bw++;

	while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp.link_nr = nv_encoder->dp.link_nr;
		while ((dp.link_nr >> 1) * link_bw[0] > datarate)
			dp.link_nr >>= 1;

		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp.link_nr) > datarate)
			link_bw++;
		dp.link_bw = link_bw[0];

		/* program selected link configuration */
		dp_set_link_config(dev, &dp);

		/* attempt to train the link at this configuration */
		memset(dp.stat, 0x00, sizeof(dp.stat));
		if (!dp_link_train_cr(dev, &dp) &&
		    !dp_link_train_eq(dev, &dp))
			break;

		/* retry at lower rate */
		link_bw++;
	}

	/* finish link training */
	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);

	/* execute post-train script from vbios */
	dp_link_train_fini(dev, &dp);

	/* re-enable hotplug detect */
	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
	return true;
}

void
nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
		struct dp_train_func *func)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_i2c_chan *auxch;
	u8 status;

	auxch = nouveau_i2c_find(encoder->dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return;

	if (mode == DRM_MODE_DPMS_ON)
		status = DP_SET_POWER_D0;
	else
		status = DP_SET_POWER_D3;

	nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);

	if (mode == DRM_MODE_DPMS_ON)
		nouveau_dp_link_train(encoder, datarate, func);
}

static void
nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_chan *auxch,
		     u8 *dpcd)
{
	u8 buf[3];

	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

	if (!auxch_tx(dev, auxch->drive, 9, DP_SINK_OUI, buf, 3))
		NV_DEBUG_KMS(dev, "Sink OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

	if (!auxch_tx(dev, auxch->drive, 9, DP_BRANCH_OUI, buf, 3))
		NV_DEBUG_KMS(dev, "Branch OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

}

bool
nouveau_dp_detect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_i2c_chan *auxch;
	u8 *dpcd = nv_encoder->dp.dpcd;
	int ret;

	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return false;

	ret = auxch_tx(dev, auxch->drive, 9, DP_DPCD_REV, dpcd, 8);
	if (ret)
		return false;

	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;

	NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
		     nv_encoder->dcb->dpconf.link_nr,
		     nv_encoder->dcb->dpconf.link_bw);

	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
		nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
		nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;

	NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);

	nouveau_dp_probe_oui(dev, auxch, dpcd);

	return true;
}

int
nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
		 uint8_t *data, int data_nr)
{
	return auxch_tx(auxch->dev, auxch->drive, cmd, addr, data, data_nr);
}

static int
nouveau_dp_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
{
	struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adap;
	struct i2c_msg *msg = msgs;
	int ret, mcnt = num;

	while (mcnt--) {
		u8 remaining = msg->len;
		u8 *ptr = msg->buf;

		while (remaining) {
			u8 cnt = (remaining > 16) ? 16 : remaining;
			u8 cmd;

			if (msg->flags & I2C_M_RD)
				cmd = AUX_I2C_READ;
			else
				cmd = AUX_I2C_WRITE;

			if (mcnt || remaining > 16)
				cmd |= AUX_I2C_MOT;

			ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
			if (ret < 0)
				return ret;

			ptr += cnt;
			remaining -= cnt;
		}

		msg++;
	}

	return num;
}

static u32
nouveau_dp_i2c_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
}

const struct i2c_algorithm nouveau_dp_i2c_algo = {
	.master_xfer = nouveau_dp_i2c_xfer,
	.functionality = nouveau_dp_i2c_func
};
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2009 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
760285e7	25	#include <drm/drmP.h>
b01f0608	26
6ee73861 BS	27	#include "nouveau_drv.h"
6ee73861 BS	28	#include "nouveau_i2c.h"
b01f0608	29	#include "nouveau_connector.h"
6ee73861	30	#include "nouveau_encoder.h"
27a45987	31	#include "nouveau_crtc.h"
a0b25635	32	#include "nouveau_gpio.h"
6ee73861	33
43720133 BS	34	/******************************************************************************
	35	* aux channel util functions
	36	*****************************************************************************/
	37	#define AUX_DBG(fmt, args...) do { \
	38	if (nouveau_reg_debug & NOUVEAU_REG_DEBUG_AUXCH) { \
	39	NV_PRINTK(KERN_DEBUG, dev, "AUXCH(%d): " fmt, ch, ##args); \
	40	} \
	41	} while (0)
	42	#define AUX_ERR(fmt, args...) NV_ERROR(dev, "AUXCH(%d): " fmt, ch, ##args)
	43
	44	static void
	45	auxch_fini(struct drm_device *dev, int ch)
	46	{
	47	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00310000, 0x00000000);
	48	}
	49
	50	static int
	51	auxch_init(struct drm_device *dev, int ch)
	52	{
	53	const u32 unksel = 1; /* nfi which to use, or if it matters.. */
	54	const u32 ureq = unksel ? 0x00100000 : 0x00200000;
	55	const u32 urep = unksel ? 0x01000000 : 0x02000000;
	56	u32 ctrl, timeout;
	57
	58	/* wait up to 1ms for any previous transaction to be done... */
	59	timeout = 1000;
	60	do {
	61	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
	62	udelay(1);
	63	if (!timeout--) {
	64	AUX_ERR("begin idle timeout 0x%08x", ctrl);
	65	return -EBUSY;
	66	}
	67	} while (ctrl & 0x03010000);
	68
	69	/* set some magic, and wait up to 1ms for it to appear */
	70	nv_mask(dev, 0x00e4e4 + (ch * 0x50), 0x00300000, ureq);
	71	timeout = 1000;
	72	do {
	73	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
	74	udelay(1);
	75	if (!timeout--) {
	76	AUX_ERR("magic wait 0x%08x\n", ctrl);
	77	auxch_fini(dev, ch);
	78	return -EBUSY;
	79	}
	80	} while ((ctrl & 0x03000000) != urep);
	81
	82	return 0;
	83	}
	84
	85	static int
	86	auxch_tx(struct drm_device dev, int ch, u8 type, u32 addr, u8 data, u8 size)
	87	{
	88	u32 ctrl, stat, timeout, retries;
	89	u32 xbuf[4] = {};
	90	int ret, i;
	91
	92	AUX_DBG("%d: 0x%08x %d\n", type, addr, size);
	93
	94	ret = auxch_init(dev, ch);
	95	if (ret)
	96	goto out;
	97
98	stat = nv_rd32(dev, 0x00e4e8 + (ch * 0x50));
99	if (!(stat & 0x10000000)) {
100	AUX_DBG("sink not detected\n");
101	ret = -ENXIO;
102	goto out;
103	}
104
105	if (!(type & 1)) {
106	memcpy(xbuf, data, size);
107	for (i = 0; i < 16; i += 4) {
108	AUX_DBG("wr 0x%08x\n", xbuf[i / 4]);
109	nv_wr32(dev, 0x00e4c0 + (ch * 0x50) + i, xbuf[i / 4]);
110	}
111	}
112
113	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
114	ctrl &= ~0x0001f0ff;
115	ctrl \|= type << 12;
116	ctrl \|= size - 1;
117	nv_wr32(dev, 0x00e4e0 + (ch * 0x50), addr);
118
119	/* retry transaction a number of times on failure... */
120	ret = -EREMOTEIO;
121	for (retries = 0; retries < 32; retries++) {
122	/* reset, and delay a while if this is a retry */
123	nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x80000000 \| ctrl);
124	nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00000000 \| ctrl);
125	if (retries)
126	udelay(400);
127
128	/* transaction request, wait up to 1ms for it to complete */
129	nv_wr32(dev, 0x00e4e4 + (ch * 0x50), 0x00010000 \| ctrl);
130
131	timeout = 1000;
132	do {
133	ctrl = nv_rd32(dev, 0x00e4e4 + (ch * 0x50));
134	udelay(1);
135	if (!timeout--) {
136	AUX_ERR("tx req timeout 0x%08x\n", ctrl);
137	goto out;
138	}
139	} while (ctrl & 0x00010000);
140
141	/* read status, and check if transaction completed ok */
142	stat = nv_mask(dev, 0x00e4e8 + (ch * 0x50), 0, 0);
143	if (!(stat & 0x000f0f00)) {
144	ret = 0;
145	break;
146	}
147
148	AUX_DBG("%02d 0x%08x 0x%08x\n", retries, ctrl, stat);
149	}
150
151	if (type & 1) {
152	for (i = 0; i < 16; i += 4) {
153	xbuf[i / 4] = nv_rd32(dev, 0x00e4d0 + (ch * 0x50) + i);
154	AUX_DBG("rd 0x%08x\n", xbuf[i / 4]);
155	}
156	memcpy(data, xbuf, size);
157	}
158
159	out:
160	auxch_fini(dev, ch);
161	return ret;
162	}
163
5f1800bd BS	164	u8 *
	165	nouveau_dp_bios_data(struct drm_device dev, struct dcb_entry dcb, u8 **entry)
	166	{
5f1800bd BS	167	struct bit_entry d;
	168	u8 *table;
	169	int i;
	170
	171	if (bit_table(dev, 'd', &d)) {
	172	NV_ERROR(dev, "BIT 'd' table not found\n");
	173	return NULL;
	174	}
	175
	176	if (d.version != 1) {
	177	NV_ERROR(dev, "BIT 'd' table version %d unknown\n", d.version);
	178	return NULL;
	179	}
	180
f9f9f536	181	table = ROMPTR(dev, d.data[0]);
5f1800bd BS	182	if (!table) {
	183	NV_ERROR(dev, "displayport table pointer invalid\n");
	184	return NULL;
	185	}
	186
	187	switch (table[0]) {
	188	case 0x20:
	189	case 0x21:
c16a3a35	190	case 0x30:
65445992	191	case 0x40:
5f1800bd BS	192	break;
	193	default:
	194	NV_ERROR(dev, "displayport table 0x%02x unknown\n", table[0]);
	195	return NULL;
	196	}
	197
	198	for (i = 0; i < table[3]; i++) {
f9f9f536	199	entry = ROMPTR(dev, table[table[1] + (i table[2])]);
5f1800bd BS	200	if (entry && bios_encoder_match(dcb, ROM32((entry)[0])))
	201	return table;
	202	}
	203
	204	NV_ERROR(dev, "displayport encoder table not found\n");
	205	return NULL;
	206	}
	207
27a45987 BS	208	/******************************************************************************
	209	* link training
	210	*****************************************************************************/
	211	struct dp_state {
8663bc7c	212	struct dp_train_func *func;
27a45987 BS	213	struct dcb_entry *dcb;
	214	int auxch;
	215	int crtc;
52e0d0ec	216	u8 *dpcd;
27a45987 BS	217	int link_nr;
	218	u32 link_bw;
	219	u8 stat[6];
	220	u8 conf[4];
	221	};
6ee73861	222
27a45987 BS	223	static void
27a45987 BS	224	dp_set_link_config(struct drm_device dev, struct dp_state dp)
6ee73861	225	{
8663bc7c	226	u8 sink[2];
6ee73861	227
27a45987	228	NV_DEBUG_KMS(dev, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
6ee73861	229
8663bc7c BS	230	/* set desired link configuration on the source */
	231	dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
	232	dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
28e2d124	233
8663bc7c BS	234	/* inform the sink of the new configuration */
8663bc7c BS	235	sink[0] = dp->link_bw / 27000;
27a45987	236	sink[1] = dp->link_nr;
8663bc7c	237	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
27a45987	238	sink[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
6ee73861	239
27a45987	240	auxch_tx(dev, dp->auxch, 8, DP_LINK_BW_SET, sink, 2);
6ee73861 BS	241	}
6ee73861 BS	242
27a45987	243	static void
8663bc7c	244	dp_set_training_pattern(struct drm_device dev, struct dp_state dp, u8 pattern)
6ee73861	245	{
5b3eb95f BS	246	u8 sink_tp;
5b3eb95f BS	247
8663bc7c	248	NV_DEBUG_KMS(dev, "training pattern %d\n", pattern);
5b3eb95f	249
8663bc7c	250	dp->func->train_set(dev, dp->dcb, pattern);
5b3eb95f BS	251
	252	auxch_tx(dev, dp->auxch, 9, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
	253	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
8663bc7c	254	sink_tp \|= pattern;
5b3eb95f	255	auxch_tx(dev, dp->auxch, 8, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
6ee73861 BS	256	}
	257
	258	static int
27a45987	259	dp_link_train_commit(struct drm_device dev, struct dp_state dp)
6ee73861	260	{
27a45987 BS	261	int i;
27a45987 BS	262
27a45987	263	for (i = 0; i < dp->link_nr; i++) {
c16a3a35 BS	264	u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
	265	u8 lpre = (lane & 0x0c) >> 2;
	266	u8 lvsw = (lane & 0x03) >> 0;
6ee73861	267
c16a3a35 BS	268	dp->conf[i] = (lpre << 3) \| lvsw;
c16a3a35 BS	269	if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
27a45987	270	dp->conf[i] \|= DP_TRAIN_MAX_SWING_REACHED;
44ab8cc5	271	if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
27a45987	272	dp->conf[i] \|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
6ee73861	273
27a45987	274	NV_DEBUG_KMS(dev, "config lane %d %02x\n", i, dp->conf[i]);
8663bc7c	275	dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
6ee73861 BS	276	}
6ee73861 BS	277
27a45987	278	return auxch_tx(dev, dp->auxch, 8, DP_TRAINING_LANE0_SET, dp->conf, 4);
6ee73861 BS	279	}
6ee73861 BS	280
27a45987 BS	281	static int
27a45987 BS	282	dp_link_train_update(struct drm_device dev, struct dp_state dp, u32 delay)
6ee73861	283	{
27a45987	284	int ret;
6ee73861	285
27a45987	286	udelay(delay);
6ee73861	287
27a45987	288	ret = auxch_tx(dev, dp->auxch, 9, DP_LANE0_1_STATUS, dp->stat, 6);
6ee73861	289	if (ret)
27a45987	290	return ret;
6ee73861	291
27a45987 BS	292	NV_DEBUG_KMS(dev, "status %02x %02x %02x %02x %02x %02x\n",
	293	dp->stat[0], dp->stat[1], dp->stat[2], dp->stat[3],
	294	dp->stat[4], dp->stat[5]);
	295	return 0;
	296	}
6ee73861	297
27a45987 BS	298	static int
	299	dp_link_train_cr(struct drm_device dev, struct dp_state dp)
	300	{
	301	bool cr_done = false, abort = false;
	302	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	303	int tries = 0, i;
6ee73861	304
27a45987	305	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
6ee73861	306
27a45987 BS	307	do {
	308	if (dp_link_train_commit(dev, dp) \|\|
	309	dp_link_train_update(dev, dp, 100))
	310	break;
6ee73861	311
27a45987 BS	312	cr_done = true;
	313	for (i = 0; i < dp->link_nr; i++) {
	314	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	315	if (!(lane & DP_LANE_CR_DONE)) {
	316	cr_done = false;
	317	if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
	318	abort = true;
	319	break;
	320	}
	321	}
6ee73861	322
27a45987 BS	323	if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
	324	voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	325	tries = 0;
	326	}
	327	} while (!cr_done && !abort && ++tries < 5);
6ee73861	328
27a45987	329	return cr_done ? 0 : -1;
6ee73861 BS	330	}
6ee73861 BS	331
27a45987 BS	332	static int
27a45987 BS	333	dp_link_train_eq(struct drm_device dev, struct dp_state dp)
6ee73861	334	{
27a45987 BS	335	bool eq_done, cr_done = true;
27a45987 BS	336	int tries = 0, i;
6ee73861	337
27a45987	338	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
6ee73861	339
27a45987 BS	340	do {
27a45987 BS	341	if (dp_link_train_update(dev, dp, 400))
6ee73861	342	break;
6ee73861	343
27a45987 BS	344	eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
	345	for (i = 0; i < dp->link_nr && eq_done; i++) {
	346	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	347	if (!(lane & DP_LANE_CR_DONE))
	348	cr_done = false;
	349	if (!(lane & DP_LANE_CHANNEL_EQ_DONE) \|\|
	350	!(lane & DP_LANE_SYMBOL_LOCKED))
	351	eq_done = false;
	352	}
6ee73861	353
27a45987 BS	354	if (dp_link_train_commit(dev, dp))
	355	break;
	356	} while (!eq_done && cr_done && ++tries <= 5);
	357
	358	return eq_done ? 0 : -1;
6ee73861 BS	359	}
6ee73861 BS	360
8c1dcb65 BS	361	static void
	362	dp_set_downspread(struct drm_device dev, struct dp_state dp, bool enable)
	363	{
	364	u16 script = 0x0000;
	365	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	366	if (table) {
	367	if (table[0] >= 0x20 && table[0] <= 0x30) {
6e83fda2 BS	368	if (enable) script = ROM16(entry[12]);
6e83fda2 BS	369	else script = ROM16(entry[14]);
65445992 BS	370	} else
	371	if (table[0] == 0x40) {
	372	if (enable) script = ROM16(entry[11]);
	373	else script = ROM16(entry[13]);
8c1dcb65 BS	374	}
	375	}
	376
	377	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	378	}
	379
	380	static void
	381	dp_link_train_init(struct drm_device dev, struct dp_state dp)
	382	{
	383	u16 script = 0x0000;
	384	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	385	if (table) {
	386	if (table[0] >= 0x20 && table[0] <= 0x30)
	387	script = ROM16(entry[6]);
65445992 BS	388	else
	389	if (table[0] == 0x40)
	390	script = ROM16(entry[5]);
8c1dcb65 BS	391	}
	392
	393	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	394	}
	395
	396	static void
	397	dp_link_train_fini(struct drm_device dev, struct dp_state dp)
	398	{
	399	u16 script = 0x0000;
	400	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	401	if (table) {
	402	if (table[0] >= 0x20 && table[0] <= 0x30)
	403	script = ROM16(entry[8]);
65445992 BS	404	else
	405	if (table[0] == 0x40)
	406	script = ROM16(entry[7]);
8c1dcb65 BS	407	}
	408
	409	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	410	}
	411
6ee73861	412	bool
8663bc7c BS	413	nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
8663bc7c BS	414	struct dp_train_func *func)
6ee73861	415	{
6ee73861	416	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
27a45987 BS	417	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	418	struct nouveau_connector *nv_connector =
	419	nouveau_encoder_connector_get(nv_encoder);
	420	struct drm_device *dev = encoder->dev;
	421	struct nouveau_i2c_chan *auxch;
	422	const u32 bw_list[] = { 270000, 162000, 0 };
	423	const u32 *link_bw = bw_list;
	424	struct dp_state dp;
6ee73861	425
27a45987 BS	426	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
27a45987 BS	427	if (!auxch)
6ee73861 BS	428	return false;
6ee73861 BS	429
8663bc7c	430	dp.func = func;
27a45987 BS	431	dp.dcb = nv_encoder->dcb;
27a45987 BS	432	dp.crtc = nv_crtc->index;
2bdb06e3	433	dp.auxch = auxch->drive;
52e0d0ec	434	dp.dpcd = nv_encoder->dp.dpcd;
6ee73861	435
6860dc82 BS	436	/* adjust required bandwidth for 8B/10B coding overhead */
	437	datarate = (datarate / 8) * 10;
	438
27a45987 BS	439	/* some sinks toggle hotplug in response to some of the actions
	440	* we take during link training (DP_SET_POWER is one), we need
	441	* to ignore them for the moment to avoid races.
	442	*/
a0b25635	443	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, false);
6ee73861	444
52e0d0ec	445	/* enable down-spreading, if possible */
8c1dcb65	446	dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
52e0d0ec	447
27a45987	448	/* execute pre-train script from vbios */
8c1dcb65	449	dp_link_train_init(dev, &dp);
6ee73861	450
27a45987	451	/* start off at highest link rate supported by encoder and display */
75a1fccf	452	while (*link_bw > nv_encoder->dp.link_bw)
27a45987	453	link_bw++;
6ee73861	454
27a45987 BS	455	while (link_bw[0]) {
	456	/* find minimum required lane count at this link rate */
	457	dp.link_nr = nv_encoder->dp.link_nr;
	458	while ((dp.link_nr >> 1) * link_bw[0] > datarate)
	459	dp.link_nr >>= 1;
6ee73861	460
27a45987 BS	461	/* drop link rate to minimum with this lane count */
	462	while ((link_bw[1] * dp.link_nr) > datarate)
	463	link_bw++;
	464	dp.link_bw = link_bw[0];
6ee73861	465
27a45987 BS	466	/* program selected link configuration */
27a45987 BS	467	dp_set_link_config(dev, &dp);
6ee73861	468
27a45987 BS	469	/* attempt to train the link at this configuration */
	470	memset(dp.stat, 0x00, sizeof(dp.stat));
	471	if (!dp_link_train_cr(dev, &dp) &&
	472	!dp_link_train_eq(dev, &dp))
6ee73861 BS	473	break;
6ee73861 BS	474
27a45987 BS	475	/* retry at lower rate */
27a45987 BS	476	link_bw++;
6ee73861 BS	477	}
6ee73861 BS	478
27a45987 BS	479	/* finish link training */
27a45987 BS	480	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
6ee73861	481
27a45987	482	/* execute post-train script from vbios */
8c1dcb65	483	dp_link_train_fini(dev, &dp);
ea4718d1	484
b01f0608	485	/* re-enable hotplug detect */
a0b25635	486	nouveau_gpio_irq(dev, 0, nv_connector->hpd, 0xff, true);
27a45987	487	return true;
6ee73861 BS	488	}
6ee73861 BS	489
f14d9a4d BS	490	void
	491	nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
	492	struct dp_train_func *func)
	493	{
	494	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	495	struct nouveau_i2c_chan *auxch;
	496	u8 status;
	497
	498	auxch = nouveau_i2c_find(encoder->dev, nv_encoder->dcb->i2c_index);
	499	if (!auxch)
	500	return;
	501
	502	if (mode == DRM_MODE_DPMS_ON)
	503	status = DP_SET_POWER_D0;
	504	else
	505	status = DP_SET_POWER_D3;
	506
	507	nouveau_dp_auxch(auxch, 8, DP_SET_POWER, &status, 1);
	508
	509	if (mode == DRM_MODE_DPMS_ON)
	510	nouveau_dp_link_train(encoder, datarate, func);
	511	}
	512
6225ee05 AJ	513	static void
	514	nouveau_dp_probe_oui(struct drm_device dev, struct nouveau_i2c_chan auxch,
	515	u8 *dpcd)
	516	{
	517	u8 buf[3];
	518
	519	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
	520	return;
	521
	522	if (!auxch_tx(dev, auxch->drive, 9, DP_SINK_OUI, buf, 3))
	523	NV_DEBUG_KMS(dev, "Sink OUI: %02hx%02hx%02hx\n",
	524	buf[0], buf[1], buf[2]);
	525
	526	if (!auxch_tx(dev, auxch->drive, 9, DP_BRANCH_OUI, buf, 3))
	527	NV_DEBUG_KMS(dev, "Branch OUI: %02hx%02hx%02hx\n",
	528	buf[0], buf[1], buf[2]);
	529
	530	}
	531
6ee73861 BS	532	bool
	533	nouveau_dp_detect(struct drm_encoder *encoder)
	534	{
	535	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	536	struct drm_device *dev = encoder->dev;
52e0d0ec BS	537	struct nouveau_i2c_chan *auxch;
52e0d0ec BS	538	u8 *dpcd = nv_encoder->dp.dpcd;
6ee73861 BS	539	int ret;
6ee73861 BS	540
52e0d0ec BS	541	auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
	542	if (!auxch)
	543	return false;
	544
2bdb06e3	545	ret = auxch_tx(dev, auxch->drive, 9, DP_DPCD_REV, dpcd, 8);
6ee73861 BS	546	if (ret)
	547	return false;
	548
75a1fccf BS	549	nv_encoder->dp.link_bw = 27000 * dpcd[1];
75a1fccf BS	550	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
6ee73861	551
75a1fccf BS	552	NV_DEBUG_KMS(dev, "display: %dx%d dpcd 0x%02x\n",
	553	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	554	NV_DEBUG_KMS(dev, "encoder: %dx%d\n",
	555	nv_encoder->dcb->dpconf.link_nr,
	556	nv_encoder->dcb->dpconf.link_bw);
6ee73861	557
75a1fccf	558	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
6ee73861	559	nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
75a1fccf BS	560	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
75a1fccf BS	561	nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
6ee73861	562
75a1fccf BS	563	NV_DEBUG_KMS(dev, "maximum: %dx%d\n",
75a1fccf BS	564	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
fe224bb7	565
6225ee05 AJ	566	nouveau_dp_probe_oui(dev, auxch, dpcd);
6225ee05 AJ	567
6ee73861 BS	568	return true;
	569	}
	570
	571	int
	572	nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
	573	uint8_t *data, int data_nr)
	574	{
2bdb06e3	575	return auxch_tx(auxch->dev, auxch->drive, cmd, addr, data, data_nr);
6ee73861 BS	576	}
6ee73861 BS	577
c020c9a8 BS	578	static int
c020c9a8 BS	579	nouveau_dp_i2c_xfer(struct i2c_adapter adap, struct i2c_msg msgs, int num)
6ee73861	580	{
c020c9a8	581	struct nouveau_i2c_chan auxch = (struct nouveau_i2c_chan )adap;
c020c9a8 BS	582	struct i2c_msg *msg = msgs;
c020c9a8 BS	583	int ret, mcnt = num;
6ee73861	584
c020c9a8 BS	585	while (mcnt--) {
	586	u8 remaining = msg->len;
	587	u8 *ptr = msg->buf;
6ee73861	588
c020c9a8 BS	589	while (remaining) {
	590	u8 cnt = (remaining > 16) ? 16 : remaining;
	591	u8 cmd;
6ee73861	592
c020c9a8 BS	593	if (msg->flags & I2C_M_RD)
	594	cmd = AUX_I2C_READ;
	595	else
	596	cmd = AUX_I2C_WRITE;
	597
	598	if (mcnt \|\| remaining > 16)
	599	cmd \|= AUX_I2C_MOT;
	600
	601	ret = nouveau_dp_auxch(auxch, cmd, msg->addr, ptr, cnt);
	602	if (ret < 0)
	603	return ret;
	604
c020c9a8 BS	605	ptr += cnt;
c020c9a8 BS	606	remaining -= cnt;
6ee73861	607	}
c020c9a8 BS	608
c020c9a8 BS	609	msg++;
6ee73861	610	}
c020c9a8 BS	611
	612	return num;
	613	}
	614
	615	static u32
	616	nouveau_dp_i2c_func(struct i2c_adapter *adap)
	617	{
	618	return I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL;
6ee73861 BS	619	}
6ee73861 BS	620
c020c9a8 BS	621	const struct i2c_algorithm nouveau_dp_i2c_algo = {
	622	.master_xfer = nouveau_dp_i2c_xfer,
	623	.functionality = nouveau_dp_i2c_func
	624	};