[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nouveau_dp.c

/*
 * Copyright 2009 Red Hat Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Authors: Ben Skeggs
 */

#include <drm/drmP.h>
#include <drm/drm_dp_helper.h>

#include "nouveau_drm.h"
#include "nouveau_connector.h"
#include "nouveau_encoder.h"
#include "nouveau_crtc.h"

#include <subdev/gpio.h>
#include <subdev/i2c.h>

u8 *
nouveau_dp_bios_data(struct drm_device *dev, struct dcb_output *dcb, u8 **entry)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct bit_entry d;
	u8 *table;
	int i;

	if (bit_table(dev, 'd', &d)) {
		NV_ERROR(drm, "BIT 'd' table not found\n");
		return NULL;
	}

	if (d.version != 1) {
		NV_ERROR(drm, "BIT 'd' table version %d unknown\n", d.version);
		return NULL;
	}

	table = ROMPTR(dev, d.data[0]);
	if (!table) {
		NV_ERROR(drm, "displayport table pointer invalid\n");
		return NULL;
	}

	switch (table[0]) {
	case 0x20:
	case 0x21:
	case 0x30:
	case 0x40:
		break;
	default:
		NV_ERROR(drm, "displayport table 0x%02x unknown\n", table[0]);
		return NULL;
	}

	for (i = 0; i < table[3]; i++) {
		*entry = ROMPTR(dev, table[table[1] + (i * table[2])]);
		if (*entry && bios_encoder_match(dcb, ROM32((*entry)[0])))
			return table;
	}

	NV_ERROR(drm, "displayport encoder table not found\n");
	return NULL;
}

/******************************************************************************
 * link training
 *****************************************************************************/
struct dp_state {
	struct nouveau_i2c_port *auxch;
	struct dp_train_func *func;
	struct dcb_output *dcb;
	int crtc;
	u8 *dpcd;
	int link_nr;
	u32 link_bw;
	u8  stat[6];
	u8  conf[4];
};

static void
dp_set_link_config(struct drm_device *dev, struct dp_state *dp)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	u8 sink[2];

	NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);

	/* set desired link configuration on the source */
	dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
			   dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);

	/* inform the sink of the new configuration */
	sink[0] = dp->link_bw / 27000;
	sink[1] = dp->link_nr;
	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
		sink[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;

	nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
}

static void
dp_set_training_pattern(struct drm_device *dev, struct dp_state *dp, u8 pattern)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	u8 sink_tp;

	NV_DEBUG(drm, "training pattern %d\n", pattern);

	dp->func->train_set(dev, dp->dcb, pattern);

	nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
	sink_tp |= pattern;
	nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
}

static int
dp_link_train_commit(struct drm_device *dev, struct dp_state *dp)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	int i;

	for (i = 0; i < dp->link_nr; i++) {
		u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
		u8 lpre = (lane & 0x0c) >> 2;
		u8 lvsw = (lane & 0x03) >> 0;

		dp->conf[i] = (lpre << 3) | lvsw;
		if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
			dp->conf[i] |= DP_TRAIN_MAX_SWING_REACHED;
		if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
			dp->conf[i] |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;

		NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
		dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
	}

	return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
}

static int
dp_link_train_update(struct drm_device *dev, struct dp_state *dp, u32 delay)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	int ret;

	udelay(delay);

	ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
	if (ret)
		return ret;

	NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
	return 0;
}

static int
dp_link_train_cr(struct drm_device *dev, struct dp_state *dp)
{
	bool cr_done = false, abort = false;
	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);

	do {
		if (dp_link_train_commit(dev, dp) ||
		    dp_link_train_update(dev, dp, 100))
			break;

		cr_done = true;
		for (i = 0; i < dp->link_nr; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE)) {
				cr_done = false;
				if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
					abort = true;
				break;
			}
		}

		if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
			voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
			tries = 0;
		}
	} while (!cr_done && !abort && ++tries < 5);

	return cr_done ? 0 : -1;
}

static int
dp_link_train_eq(struct drm_device *dev, struct dp_state *dp)
{
	bool eq_done, cr_done = true;
	int tries = 0, i;

	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);

	do {
		if (dp_link_train_update(dev, dp, 400))
			break;

		eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
		for (i = 0; i < dp->link_nr && eq_done; i++) {
			u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
			if (!(lane & DP_LANE_CR_DONE))
				cr_done = false;
			if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
			    !(lane & DP_LANE_SYMBOL_LOCKED))
				eq_done = false;
		}

		if (dp_link_train_commit(dev, dp))
			break;
	} while (!eq_done && cr_done && ++tries <= 5);

	return eq_done ? 0 : -1;
}

static void
dp_set_downspread(struct drm_device *dev, struct dp_state *dp, bool enable)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30) {
			if (enable) script = ROM16(entry[12]);
			else        script = ROM16(entry[14]);
		} else
		if (table[0] == 0x40) {
			if (enable) script = ROM16(entry[11]);
			else        script = ROM16(entry[13]);
		}
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_init(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[6]);
		else
		if (table[0] == 0x40)
			script = ROM16(entry[5]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static void
dp_link_train_fini(struct drm_device *dev, struct dp_state *dp)
{
	u16 script = 0x0000;
	u8 *entry, *table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	if (table) {
		if (table[0] >= 0x20 && table[0] <= 0x30)
			script = ROM16(entry[8]);
		else
		if (table[0] == 0x40)
			script = ROM16(entry[7]);
	}

	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
}

static bool
nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
		      struct dp_train_func *func)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	struct nouveau_connector *nv_connector =
		nouveau_encoder_connector_get(nv_encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
	const u32 bw_list[] = { 270000, 162000, 0 };
	const u32 *link_bw = bw_list;
	struct dp_state dp;

	dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
	if (!dp.auxch)
		return false;

	dp.func = func;
	dp.dcb = nv_encoder->dcb;
	dp.crtc = nv_crtc->index;
	dp.dpcd = nv_encoder->dp.dpcd;

	/* adjust required bandwidth for 8B/10B coding overhead */
	datarate = (datarate / 8) * 10;

	/* some sinks toggle hotplug in response to some of the actions
	 * we take during link training (DP_SET_POWER is one), we need
	 * to ignore them for the moment to avoid races.
	 */
	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);

	/* enable down-spreading, if possible */
	dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);

	/* execute pre-train script from vbios */
	dp_link_train_init(dev, &dp);

	/* start off at highest link rate supported by encoder and display */
	while (*link_bw > nv_encoder->dp.link_bw)
		link_bw++;

	while (link_bw[0]) {
		/* find minimum required lane count at this link rate */
		dp.link_nr = nv_encoder->dp.link_nr;
		while ((dp.link_nr >> 1) * link_bw[0] > datarate)
			dp.link_nr >>= 1;

		/* drop link rate to minimum with this lane count */
		while ((link_bw[1] * dp.link_nr) > datarate)
			link_bw++;
		dp.link_bw = link_bw[0];

		/* program selected link configuration */
		dp_set_link_config(dev, &dp);

		/* attempt to train the link at this configuration */
		memset(dp.stat, 0x00, sizeof(dp.stat));
		if (!dp_link_train_cr(dev, &dp) &&
		    !dp_link_train_eq(dev, &dp))
			break;

		/* retry at lower rate */
		link_bw++;
	}

	/* finish link training */
	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);

	/* execute post-train script from vbios */
	dp_link_train_fini(dev, &dp);

	/* re-enable hotplug detect */
	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
	return true;
}

void
nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
		struct dp_train_func *func)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_i2c_port *auxch;
	u8 status;

	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return;

	if (mode == DRM_MODE_DPMS_ON)
		status = DP_SET_POWER_D0;
	else
		status = DP_SET_POWER_D3;

	nv_wraux(auxch, DP_SET_POWER, &status, 1);

	if (mode == DRM_MODE_DPMS_ON)
		nouveau_dp_link_train(encoder, datarate, func);
}

static void
nouveau_dp_probe_oui(struct drm_device *dev, struct nouveau_i2c_port *auxch,
		     u8 *dpcd)
{
	struct nouveau_drm *drm = nouveau_drm(dev);
	u8 buf[3];

	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
		return;

	if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
		NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

	if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
		NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
			     buf[0], buf[1], buf[2]);

}

bool
nouveau_dp_detect(struct drm_encoder *encoder)
{
	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	struct drm_device *dev = encoder->dev;
	struct nouveau_drm *drm = nouveau_drm(dev);
	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	struct nouveau_i2c_port *auxch;
	u8 *dpcd = nv_encoder->dp.dpcd;
	int ret;

	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
	if (!auxch)
		return false;

	ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
	if (ret)
		return false;

	nv_encoder->dp.link_bw = 27000 * dpcd[1];
	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;

	NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
	NV_DEBUG(drm, "encoder: %dx%d\n",
		     nv_encoder->dcb->dpconf.link_nr,
		     nv_encoder->dcb->dpconf.link_bw);

	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
		nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
		nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;

	NV_DEBUG(drm, "maximum: %dx%d\n",
		     nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);

	nouveau_dp_probe_oui(dev, auxch, dpcd);

	return true;
}
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright 2009 Red Hat Inc.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	15	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	17	* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
	18	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
	19	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	20	* OTHER DEALINGS IN THE SOFTWARE.
	21	*
	22	* Authors: Ben Skeggs
	23	*/
	24
760285e7	25	#include <drm/drmP.h>
612a9aab	26	#include <drm/drm_dp_helper.h>
b01f0608	27
77145f1c	28	#include "nouveau_drm.h"
b01f0608	29	#include "nouveau_connector.h"
6ee73861	30	#include "nouveau_encoder.h"
27a45987	31	#include "nouveau_crtc.h"
6ee73861	32
77145f1c BS	33	#include <subdev/gpio.h>
77145f1c BS	34	#include <subdev/i2c.h>
43720133	35
5f1800bd	36	u8 *
cb75d97e	37	nouveau_dp_bios_data(struct drm_device dev, struct dcb_output dcb, u8 **entry)
5f1800bd	38	{
77145f1c	39	struct nouveau_drm *drm = nouveau_drm(dev);
5f1800bd BS	40	struct bit_entry d;
	41	u8 *table;
	42	int i;
	43
	44	if (bit_table(dev, 'd', &d)) {
77145f1c	45	NV_ERROR(drm, "BIT 'd' table not found\n");
5f1800bd BS	46	return NULL;
	47	}
	48
	49	if (d.version != 1) {
77145f1c	50	NV_ERROR(drm, "BIT 'd' table version %d unknown\n", d.version);
5f1800bd BS	51	return NULL;
	52	}
	53
f9f9f536	54	table = ROMPTR(dev, d.data[0]);
5f1800bd	55	if (!table) {
77145f1c	56	NV_ERROR(drm, "displayport table pointer invalid\n");
5f1800bd BS	57	return NULL;
	58	}
	59
	60	switch (table[0]) {
	61	case 0x20:
	62	case 0x21:
c16a3a35	63	case 0x30:
65445992	64	case 0x40:
5f1800bd BS	65	break;
5f1800bd BS	66	default:
77145f1c	67	NV_ERROR(drm, "displayport table 0x%02x unknown\n", table[0]);
5f1800bd BS	68	return NULL;
	69	}
	70
	71	for (i = 0; i < table[3]; i++) {
f9f9f536	72	entry = ROMPTR(dev, table[table[1] + (i table[2])]);
5f1800bd BS	73	if (entry && bios_encoder_match(dcb, ROM32((entry)[0])))
	74	return table;
	75	}
	76
77145f1c	77	NV_ERROR(drm, "displayport encoder table not found\n");
5f1800bd BS	78	return NULL;
	79	}
	80
27a45987 BS	81	/******************************************************************************
	82	* link training
	83	*****************************************************************************/
	84	struct dp_state {
4196faa8	85	struct nouveau_i2c_port *auxch;
8663bc7c	86	struct dp_train_func *func;
cb75d97e	87	struct dcb_output *dcb;
27a45987	88	int crtc;
52e0d0ec	89	u8 *dpcd;
27a45987 BS	90	int link_nr;
	91	u32 link_bw;
	92	u8 stat[6];
	93	u8 conf[4];
	94	};
6ee73861	95
27a45987 BS	96	static void
27a45987 BS	97	dp_set_link_config(struct drm_device dev, struct dp_state dp)
6ee73861	98	{
77145f1c	99	struct nouveau_drm *drm = nouveau_drm(dev);
8663bc7c	100	u8 sink[2];
6ee73861	101
77145f1c	102	NV_DEBUG(drm, "%d lanes at %d KB/s\n", dp->link_nr, dp->link_bw);
6ee73861	103
8663bc7c BS	104	/* set desired link configuration on the source */
	105	dp->func->link_set(dev, dp->dcb, dp->crtc, dp->link_nr, dp->link_bw,
	106	dp->dpcd[2] & DP_ENHANCED_FRAME_CAP);
28e2d124	107
8663bc7c BS	108	/* inform the sink of the new configuration */
8663bc7c BS	109	sink[0] = dp->link_bw / 27000;
27a45987	110	sink[1] = dp->link_nr;
8663bc7c	111	if (dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)
27a45987	112	sink[1] \|= DP_LANE_COUNT_ENHANCED_FRAME_EN;
6ee73861	113
77145f1c	114	nv_wraux(dp->auxch, DP_LINK_BW_SET, sink, 2);
6ee73861 BS	115	}
6ee73861 BS	116
27a45987	117	static void
8663bc7c	118	dp_set_training_pattern(struct drm_device dev, struct dp_state dp, u8 pattern)
6ee73861	119	{
77145f1c	120	struct nouveau_drm *drm = nouveau_drm(dev);
5b3eb95f BS	121	u8 sink_tp;
5b3eb95f BS	122
77145f1c	123	NV_DEBUG(drm, "training pattern %d\n", pattern);
5b3eb95f	124
8663bc7c	125	dp->func->train_set(dev, dp->dcb, pattern);
5b3eb95f	126
77145f1c	127	nv_rdaux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
5b3eb95f	128	sink_tp &= ~DP_TRAINING_PATTERN_MASK;
8663bc7c	129	sink_tp \|= pattern;
77145f1c	130	nv_wraux(dp->auxch, DP_TRAINING_PATTERN_SET, &sink_tp, 1);
6ee73861 BS	131	}
	132
	133	static int
27a45987	134	dp_link_train_commit(struct drm_device dev, struct dp_state dp)
6ee73861	135	{
77145f1c	136	struct nouveau_drm *drm = nouveau_drm(dev);
27a45987 BS	137	int i;
27a45987 BS	138
27a45987	139	for (i = 0; i < dp->link_nr; i++) {
c16a3a35 BS	140	u8 lane = (dp->stat[4 + (i >> 1)] >> ((i & 1) * 4)) & 0xf;
	141	u8 lpre = (lane & 0x0c) >> 2;
	142	u8 lvsw = (lane & 0x03) >> 0;
6ee73861	143
c16a3a35 BS	144	dp->conf[i] = (lpre << 3) \| lvsw;
c16a3a35 BS	145	if (lvsw == DP_TRAIN_VOLTAGE_SWING_1200)
27a45987	146	dp->conf[i] \|= DP_TRAIN_MAX_SWING_REACHED;
44ab8cc5	147	if ((lpre << 3) == DP_TRAIN_PRE_EMPHASIS_9_5)
27a45987	148	dp->conf[i] \|= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
6ee73861	149
77145f1c	150	NV_DEBUG(drm, "config lane %d %02x\n", i, dp->conf[i]);
8663bc7c	151	dp->func->train_adj(dev, dp->dcb, i, lvsw, lpre);
6ee73861 BS	152	}
6ee73861 BS	153
77145f1c	154	return nv_wraux(dp->auxch, DP_TRAINING_LANE0_SET, dp->conf, 4);
6ee73861 BS	155	}
6ee73861 BS	156
27a45987 BS	157	static int
27a45987 BS	158	dp_link_train_update(struct drm_device dev, struct dp_state dp, u32 delay)
6ee73861	159	{
77145f1c	160	struct nouveau_drm *drm = nouveau_drm(dev);
27a45987	161	int ret;
6ee73861	162
27a45987	163	udelay(delay);
6ee73861	164
77145f1c	165	ret = nv_rdaux(dp->auxch, DP_LANE0_1_STATUS, dp->stat, 6);
6ee73861	166	if (ret)
27a45987	167	return ret;
6ee73861	168
268d2837	169	NV_DEBUG(drm, "status %*ph\n", 6, dp->stat);
27a45987 BS	170	return 0;
27a45987 BS	171	}
6ee73861	172
27a45987 BS	173	static int
	174	dp_link_train_cr(struct drm_device dev, struct dp_state dp)
	175	{
	176	bool cr_done = false, abort = false;
	177	int voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	178	int tries = 0, i;
6ee73861	179
27a45987	180	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_1);
6ee73861	181
27a45987 BS	182	do {
	183	if (dp_link_train_commit(dev, dp) \|\|
	184	dp_link_train_update(dev, dp, 100))
	185	break;
6ee73861	186
27a45987 BS	187	cr_done = true;
	188	for (i = 0; i < dp->link_nr; i++) {
	189	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	190	if (!(lane & DP_LANE_CR_DONE)) {
	191	cr_done = false;
	192	if (dp->conf[i] & DP_TRAIN_MAX_SWING_REACHED)
	193	abort = true;
	194	break;
	195	}
	196	}
6ee73861	197
27a45987 BS	198	if ((dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
	199	voltage = dp->conf[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
	200	tries = 0;
	201	}
	202	} while (!cr_done && !abort && ++tries < 5);
6ee73861	203
27a45987	204	return cr_done ? 0 : -1;
6ee73861 BS	205	}
6ee73861 BS	206
27a45987 BS	207	static int
27a45987 BS	208	dp_link_train_eq(struct drm_device dev, struct dp_state dp)
6ee73861	209	{
27a45987 BS	210	bool eq_done, cr_done = true;
27a45987 BS	211	int tries = 0, i;
6ee73861	212
27a45987	213	dp_set_training_pattern(dev, dp, DP_TRAINING_PATTERN_2);
6ee73861	214
27a45987 BS	215	do {
27a45987 BS	216	if (dp_link_train_update(dev, dp, 400))
6ee73861	217	break;
6ee73861	218
27a45987 BS	219	eq_done = !!(dp->stat[2] & DP_INTERLANE_ALIGN_DONE);
	220	for (i = 0; i < dp->link_nr && eq_done; i++) {
	221	u8 lane = (dp->stat[i >> 1] >> ((i & 1) * 4)) & 0xf;
	222	if (!(lane & DP_LANE_CR_DONE))
	223	cr_done = false;
	224	if (!(lane & DP_LANE_CHANNEL_EQ_DONE) \|\|
	225	!(lane & DP_LANE_SYMBOL_LOCKED))
	226	eq_done = false;
	227	}
6ee73861	228
27a45987 BS	229	if (dp_link_train_commit(dev, dp))
	230	break;
	231	} while (!eq_done && cr_done && ++tries <= 5);
	232
	233	return eq_done ? 0 : -1;
6ee73861 BS	234	}
6ee73861 BS	235
8c1dcb65 BS	236	static void
	237	dp_set_downspread(struct drm_device dev, struct dp_state dp, bool enable)
	238	{
	239	u16 script = 0x0000;
	240	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	241	if (table) {
	242	if (table[0] >= 0x20 && table[0] <= 0x30) {
6e83fda2 BS	243	if (enable) script = ROM16(entry[12]);
6e83fda2 BS	244	else script = ROM16(entry[14]);
65445992 BS	245	} else
	246	if (table[0] == 0x40) {
	247	if (enable) script = ROM16(entry[11]);
	248	else script = ROM16(entry[13]);
8c1dcb65 BS	249	}
	250	}
	251
	252	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	253	}
	254
	255	static void
	256	dp_link_train_init(struct drm_device dev, struct dp_state dp)
	257	{
	258	u16 script = 0x0000;
	259	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	260	if (table) {
	261	if (table[0] >= 0x20 && table[0] <= 0x30)
	262	script = ROM16(entry[6]);
65445992 BS	263	else
	264	if (table[0] == 0x40)
	265	script = ROM16(entry[5]);
8c1dcb65 BS	266	}
	267
	268	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	269	}
	270
	271	static void
	272	dp_link_train_fini(struct drm_device dev, struct dp_state dp)
	273	{
	274	u16 script = 0x0000;
	275	u8 entry, table = nouveau_dp_bios_data(dev, dp->dcb, &entry);
	276	if (table) {
	277	if (table[0] >= 0x20 && table[0] <= 0x30)
	278	script = ROM16(entry[8]);
65445992 BS	279	else
	280	if (table[0] == 0x40)
	281	script = ROM16(entry[7]);
8c1dcb65 BS	282	}
	283
	284	nouveau_bios_run_init_table(dev, script, dp->dcb, dp->crtc);
	285	}
	286
5b8a43ae	287	static bool
8663bc7c BS	288	nouveau_dp_link_train(struct drm_encoder *encoder, u32 datarate,
8663bc7c BS	289	struct dp_train_func *func)
6ee73861	290	{
6ee73861	291	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
27a45987 BS	292	struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
	293	struct nouveau_connector *nv_connector =
	294	nouveau_encoder_connector_get(nv_encoder);
	295	struct drm_device *dev = encoder->dev;
77145f1c BS	296	struct nouveau_drm *drm = nouveau_drm(dev);
	297	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
	298	struct nouveau_gpio *gpio = nouveau_gpio(drm->device);
27a45987 BS	299	const u32 bw_list[] = { 270000, 162000, 0 };
	300	const u32 *link_bw = bw_list;
	301	struct dp_state dp;
6ee73861	302
77145f1c	303	dp.auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
4196faa8	304	if (!dp.auxch)
6ee73861 BS	305	return false;
6ee73861 BS	306
8663bc7c	307	dp.func = func;
27a45987 BS	308	dp.dcb = nv_encoder->dcb;
27a45987 BS	309	dp.crtc = nv_crtc->index;
52e0d0ec	310	dp.dpcd = nv_encoder->dp.dpcd;
6ee73861	311
6860dc82 BS	312	/* adjust required bandwidth for 8B/10B coding overhead */
	313	datarate = (datarate / 8) * 10;
	314
27a45987 BS	315	/* some sinks toggle hotplug in response to some of the actions
	316	* we take during link training (DP_SET_POWER is one), we need
	317	* to ignore them for the moment to avoid races.
	318	*/
77145f1c	319	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, false);
6ee73861	320
52e0d0ec	321	/* enable down-spreading, if possible */
8c1dcb65	322	dp_set_downspread(dev, &dp, nv_encoder->dp.dpcd[3] & 1);
52e0d0ec	323
27a45987	324	/* execute pre-train script from vbios */
8c1dcb65	325	dp_link_train_init(dev, &dp);
6ee73861	326
27a45987	327	/* start off at highest link rate supported by encoder and display */
75a1fccf	328	while (*link_bw > nv_encoder->dp.link_bw)
27a45987	329	link_bw++;
6ee73861	330
27a45987 BS	331	while (link_bw[0]) {
	332	/* find minimum required lane count at this link rate */
	333	dp.link_nr = nv_encoder->dp.link_nr;
	334	while ((dp.link_nr >> 1) * link_bw[0] > datarate)
	335	dp.link_nr >>= 1;
6ee73861	336
27a45987 BS	337	/* drop link rate to minimum with this lane count */
	338	while ((link_bw[1] * dp.link_nr) > datarate)
	339	link_bw++;
	340	dp.link_bw = link_bw[0];
6ee73861	341
27a45987 BS	342	/* program selected link configuration */
27a45987 BS	343	dp_set_link_config(dev, &dp);
6ee73861	344
27a45987 BS	345	/* attempt to train the link at this configuration */
	346	memset(dp.stat, 0x00, sizeof(dp.stat));
	347	if (!dp_link_train_cr(dev, &dp) &&
	348	!dp_link_train_eq(dev, &dp))
6ee73861 BS	349	break;
6ee73861 BS	350
27a45987 BS	351	/* retry at lower rate */
27a45987 BS	352	link_bw++;
6ee73861 BS	353	}
6ee73861 BS	354
27a45987 BS	355	/* finish link training */
27a45987 BS	356	dp_set_training_pattern(dev, &dp, DP_TRAINING_PATTERN_DISABLE);
6ee73861	357
27a45987	358	/* execute post-train script from vbios */
8c1dcb65	359	dp_link_train_fini(dev, &dp);
ea4718d1	360
b01f0608	361	/* re-enable hotplug detect */
77145f1c	362	gpio->irq(gpio, 0, nv_connector->hpd, 0xff, true);
27a45987	363	return true;
6ee73861 BS	364	}
6ee73861 BS	365
f14d9a4d BS	366	void
	367	nouveau_dp_dpms(struct drm_encoder *encoder, int mode, u32 datarate,
	368	struct dp_train_func *func)
	369	{
	370	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
77145f1c BS	371	struct nouveau_drm *drm = nouveau_drm(encoder->dev);
77145f1c BS	372	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
4196faa8	373	struct nouveau_i2c_port *auxch;
f14d9a4d BS	374	u8 status;
f14d9a4d BS	375
77145f1c	376	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
f14d9a4d BS	377	if (!auxch)
	378	return;
	379
	380	if (mode == DRM_MODE_DPMS_ON)
	381	status = DP_SET_POWER_D0;
	382	else
	383	status = DP_SET_POWER_D3;
	384
77145f1c	385	nv_wraux(auxch, DP_SET_POWER, &status, 1);
f14d9a4d BS	386
	387	if (mode == DRM_MODE_DPMS_ON)
	388	nouveau_dp_link_train(encoder, datarate, func);
	389	}
	390
6225ee05	391	static void
4196faa8	392	nouveau_dp_probe_oui(struct drm_device dev, struct nouveau_i2c_port auxch,
6225ee05 AJ	393	u8 *dpcd)
6225ee05 AJ	394	{
77145f1c	395	struct nouveau_drm *drm = nouveau_drm(dev);
6225ee05 AJ	396	u8 buf[3];
	397
	398	if (!(dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
	399	return;
	400
77145f1c BS	401	if (!nv_rdaux(auxch, DP_SINK_OUI, buf, 3))
77145f1c BS	402	NV_DEBUG(drm, "Sink OUI: %02hx%02hx%02hx\n",
6225ee05 AJ	403	buf[0], buf[1], buf[2]);
6225ee05 AJ	404
77145f1c BS	405	if (!nv_rdaux(auxch, DP_BRANCH_OUI, buf, 3))
77145f1c BS	406	NV_DEBUG(drm, "Branch OUI: %02hx%02hx%02hx\n",
6225ee05 AJ	407	buf[0], buf[1], buf[2]);
	408
	409	}
	410
6ee73861 BS	411	bool
	412	nouveau_dp_detect(struct drm_encoder *encoder)
	413	{
	414	struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
	415	struct drm_device *dev = encoder->dev;
77145f1c BS	416	struct nouveau_drm *drm = nouveau_drm(dev);
77145f1c BS	417	struct nouveau_i2c *i2c = nouveau_i2c(drm->device);
4196faa8	418	struct nouveau_i2c_port *auxch;
52e0d0ec	419	u8 *dpcd = nv_encoder->dp.dpcd;
6ee73861 BS	420	int ret;
6ee73861 BS	421
77145f1c	422	auxch = i2c->find(i2c, nv_encoder->dcb->i2c_index);
52e0d0ec BS	423	if (!auxch)
	424	return false;
	425
77145f1c	426	ret = nv_rdaux(auxch, DP_DPCD_REV, dpcd, 8);
6ee73861 BS	427	if (ret)
	428	return false;
	429
75a1fccf BS	430	nv_encoder->dp.link_bw = 27000 * dpcd[1];
75a1fccf BS	431	nv_encoder->dp.link_nr = dpcd[2] & DP_MAX_LANE_COUNT_MASK;
6ee73861	432
77145f1c	433	NV_DEBUG(drm, "display: %dx%d dpcd 0x%02x\n",
75a1fccf	434	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw, dpcd[0]);
77145f1c	435	NV_DEBUG(drm, "encoder: %dx%d\n",
75a1fccf BS	436	nv_encoder->dcb->dpconf.link_nr,
75a1fccf BS	437	nv_encoder->dcb->dpconf.link_bw);
6ee73861	438
75a1fccf	439	if (nv_encoder->dcb->dpconf.link_nr < nv_encoder->dp.link_nr)
6ee73861	440	nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
75a1fccf BS	441	if (nv_encoder->dcb->dpconf.link_bw < nv_encoder->dp.link_bw)
75a1fccf BS	442	nv_encoder->dp.link_bw = nv_encoder->dcb->dpconf.link_bw;
6ee73861	443
77145f1c	444	NV_DEBUG(drm, "maximum: %dx%d\n",
75a1fccf	445	nv_encoder->dp.link_nr, nv_encoder->dp.link_bw);
fe224bb7	446
6225ee05 AJ	447	nouveau_dp_probe_oui(dev, auxch, dpcd);
6225ee05 AJ	448
6ee73861 BS	449	return true;
6ee73861 BS	450	}