[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nouveau_dma.h

/*
 * Copyright (C) 2007 Ben Skeggs.
 * All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice (including the
 * next paragraph) shall be included in all copies or substantial
 * portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
 * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
 * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 *
 */

#ifndef __NOUVEAU_DMA_H__
#define __NOUVEAU_DMA_H__

#include "nouveau_bo.h"
#include "nouveau_chan.h"

int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
void nv50_dma_push(struct nouveau_channel *, struct nouveau_bo *,
		   int delta, int length);

/*
 * There's a hw race condition where you can't jump to your PUT offset,
 * to avoid this we jump to offset + SKIPS and fill the difference with
 * NOPs.
 *
 * xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
 * a SKIPS value of 8.  Lets assume that the race condition is to do
 * with writing into the fetch area, we configure a fetch size of 128
 * bytes so we need a larger SKIPS value.
 */
#define NOUVEAU_DMA_SKIPS (128 / 4)

/* Hardcoded object assignments to subchannels (subchannel id). */
enum {
	NvSubCtxSurf2D  = 0,
	NvSubSw		= 1,
	NvSubImageBlit  = 2,
	NvSub2D		= 3,
	NvSubGdiRect    = 3,
	NvSubCopy	= 4,
};

/* Object handles. */
enum {
	NvM2MF		= 0x80000001,
	NvDmaFB		= 0x80000002,
	NvDmaTT		= 0x80000003,
	NvNotify0       = 0x80000006,
	Nv2D		= 0x80000007,
	NvCtxSurf2D	= 0x80000008,
	NvRop		= 0x80000009,
	NvImagePatt	= 0x8000000a,
	NvClipRect	= 0x8000000b,
	NvGdiRect	= 0x8000000c,
	NvImageBlit	= 0x8000000d,
	NvSw		= 0x8000000e,
	NvSema		= 0x8000000f,
	NvEvoSema0	= 0x80000010,
	NvEvoSema1	= 0x80000011,
	NvNotify1       = 0x80000012,

	/* G80+ display objects */
	NvEvoVRAM	= 0x01000000,
	NvEvoFB16	= 0x01000001,
	NvEvoFB32	= 0x01000002,
	NvEvoVRAM_LP	= 0x01000003,
	NvEvoSync	= 0xcafe0000
};

#define NV_MEMORY_TO_MEMORY_FORMAT                                    0x00000039
#define NV_MEMORY_TO_MEMORY_FORMAT_NAME                               0x00000000
#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF                            0x00000050
#define NV_MEMORY_TO_MEMORY_FORMAT_NOP                                0x00000100
#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY                             0x00000104
#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE                 0x00000000
#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN       0x00000001
#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY                         0x00000180
#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE                         0x00000184
#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN                          0x0000030c

#define NV50_MEMORY_TO_MEMORY_FORMAT                                  0x00005039
#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200                           0x00000200
#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C                           0x0000021c
#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH                   0x00000238
#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH                  0x0000023c

static __must_check inline int
RING_SPACE(struct nouveau_channel *chan, int size)
{
	int ret;

	ret = nouveau_dma_wait(chan, 1, size);
	if (ret)
		return ret;

	chan->dma.free -= size;
	return 0;
}

static inline void
OUT_RING(struct nouveau_channel *chan, int data)
{
	nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
}

extern void
OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords);

static inline void
BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
{
	OUT_RING(chan, 0x00000000 | (subc << 13) | (size << 18) | mthd);
}

static inline void
BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size)
{
	OUT_RING(chan, 0x40000000 | (subc << 13) | (size << 18) | mthd);
}

static inline void
BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
{
	OUT_RING(chan, 0x20000000 | (size << 16) | (subc << 13) | (mthd >> 2));
}

static inline void
BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size)
{
	OUT_RING(chan, 0x60000000 | (size << 16) | (subc << 13) | (mthd >> 2));
}

static inline void
BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
{
	OUT_RING(chan, 0x80000000 | (data << 16) | (subc << 13) | (mthd >> 2));
}

#define WRITE_PUT(val) do {                                                    \
	DRM_MEMORYBARRIER();                                                   \
	nouveau_bo_rd32(chan->push.buffer, 0);                                 \
	nv_wo32(chan->object, chan->user_put, ((val) << 2) + chan->push.vma.offset);  \
} while (0)

static inline void
FIRE_RING(struct nouveau_channel *chan)
{
	if (chan->dma.cur == chan->dma.put)
		return;
	chan->accel_done = true;

	if (chan->dma.ib_max) {
		nv50_dma_push(chan, chan->push.buffer, chan->dma.put << 2,
			      (chan->dma.cur - chan->dma.put) << 2);
	} else {
		WRITE_PUT(chan->dma.cur);
	}

	chan->dma.put = chan->dma.cur;
}

static inline void
WIND_RING(struct nouveau_channel *chan)
{
	chan->dma.cur = chan->dma.put;
}

/* FIFO methods */
#define NV01_SUBCHAN_OBJECT                                          0x00000000
#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH                          0x00000010
#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW                           0x00000014
#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE                              0x00000018
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER                               0x0000001c
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL                 0x00000001
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG                    0x00000002
#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL                0x00000004
#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD                         0x00001000
#define NV84_SUBCHAN_NOTIFY_INTR                                     0x00000020
#define NV84_SUBCHAN_WRCACHE_FLUSH                                   0x00000024
#define NV10_SUBCHAN_REF_CNT                                         0x00000050
#define NVSW_SUBCHAN_PAGE_FLIP                                       0x00000054
#define NV11_SUBCHAN_DMA_SEMAPHORE                                   0x00000060
#define NV11_SUBCHAN_SEMAPHORE_OFFSET                                0x00000064
#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE                               0x00000068
#define NV11_SUBCHAN_SEMAPHORE_RELEASE                               0x0000006c
#define NV40_SUBCHAN_YIELD                                           0x00000080

/* NV_SW object class */
#define NV_SW_DMA_VBLSEM                                             0x0000018c
#define NV_SW_VBLSEM_OFFSET                                          0x00000400
#define NV_SW_VBLSEM_RELEASE_VALUE                                   0x00000404
#define NV_SW_VBLSEM_RELEASE                                         0x00000408
#define NV_SW_PAGE_FLIP                                              0x00000500

#endif
Commit	Line	Data
6ee73861 BS	1	/*
	2	* Copyright (C) 2007 Ben Skeggs.
	3	* All Rights Reserved.
	4	*
	5	* Permission is hereby granted, free of charge, to any person obtaining
	6	* a copy of this software and associated documentation files (the
	7	* "Software"), to deal in the Software without restriction, including
	8	* without limitation the rights to use, copy, modify, merge, publish,
	9	* distribute, sublicense, and/or sell copies of the Software, and to
	10	* permit persons to whom the Software is furnished to do so, subject to
	11	* the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the
	14	* next paragraph) shall be included in all copies or substantial
	15	* portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	18	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	19	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
	20	* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
	21	* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
	22	* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
	23	* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
	24	*
	25	*/
	26
	27	#ifndef __NOUVEAU_DMA_H__
	28	#define __NOUVEAU_DMA_H__
	29
ebb945a9 BS	30	#include "nouveau_bo.h"
ebb945a9 BS	31	#include "nouveau_chan.h"
6ee73861	32
ebb945a9	33	int nouveau_dma_wait(struct nouveau_channel *, int slots, int size);
9a391ad8	34	void nv50_dma_push(struct nouveau_channel , struct nouveau_bo ,
a1606a95	35	int delta, int length);
9a391ad8	36
6ee73861 BS	37	/*
	38	* There's a hw race condition where you can't jump to your PUT offset,
	39	* to avoid this we jump to offset + SKIPS and fill the difference with
	40	* NOPs.
	41	*
	42	* xf86-video-nv configures the DMA fetch size to 32 bytes, and uses
	43	* a SKIPS value of 8. Lets assume that the race condition is to do
	44	* with writing into the fetch area, we configure a fetch size of 128
	45	* bytes so we need a larger SKIPS value.
	46	*/
	47	#define NOUVEAU_DMA_SKIPS (128 / 4)
	48
	49	/* Hardcoded object assignments to subchannels (subchannel id). */
	50	enum {
d1b167e1	51	NvSubCtxSurf2D = 0,
acde2d80	52	NvSubSw = 1,
d1b167e1	53	NvSubImageBlit = 2,
f1c65e7c	54	NvSub2D = 3,
f03a314b	55	NvSubGdiRect = 3,
c6b7e895	56	NvSubCopy = 4,
6ee73861 BS	57	};
	58
	59	/* Object handles. */
	60	enum {
	61	NvM2MF = 0x80000001,
	62	NvDmaFB = 0x80000002,
	63	NvDmaTT = 0x80000003,
6ee73861 BS	64	NvNotify0 = 0x80000006,
	65	Nv2D = 0x80000007,
	66	NvCtxSurf2D = 0x80000008,
	67	NvRop = 0x80000009,
	68	NvImagePatt = 0x8000000a,
	69	NvClipRect = 0x8000000b,
	70	NvGdiRect = 0x8000000c,
	71	NvImageBlit = 0x8000000d,
f03a314b	72	NvSw = 0x8000000e,
0c6c1c2f	73	NvSema = 0x8000000f,
cdccc70e BS	74	NvEvoSema0 = 0x80000010,
cdccc70e BS	75	NvEvoSema1 = 0x80000011,
d1b167e1	76	NvNotify1 = 0x80000012,
6ee73861 BS	77
	78	/* G80+ display objects */
	79	NvEvoVRAM = 0x01000000,
	80	NvEvoFB16 = 0x01000001,
6d86951a	81	NvEvoFB32 = 0x01000002,
60f60bf1 BS	82	NvEvoVRAM_LP = 0x01000003,
60f60bf1 BS	83	NvEvoSync = 0xcafe0000
6ee73861 BS	84	};
	85
	86	#define NV_MEMORY_TO_MEMORY_FORMAT 0x00000039
	87	#define NV_MEMORY_TO_MEMORY_FORMAT_NAME 0x00000000
	88	#define NV_MEMORY_TO_MEMORY_FORMAT_SET_REF 0x00000050
	89	#define NV_MEMORY_TO_MEMORY_FORMAT_NOP 0x00000100
	90	#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY 0x00000104
	91	#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE 0x00000000
	92	#define NV_MEMORY_TO_MEMORY_FORMAT_NOTIFY_STYLE_WRITE_LE_AWAKEN 0x00000001
	93	#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY 0x00000180
	94	#define NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE 0x00000184
	95	#define NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN 0x0000030c
	96
	97	#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
	98	#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK200 0x00000200
	99	#define NV50_MEMORY_TO_MEMORY_FORMAT_UNK21C 0x0000021c
	100	#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN_HIGH 0x00000238
	101	#define NV50_MEMORY_TO_MEMORY_FORMAT_OFFSET_OUT_HIGH 0x0000023c
	102
	103	static __must_check inline int
	104	RING_SPACE(struct nouveau_channel *chan, int size)
	105	{
9a391ad8	106	int ret;
6ee73861	107
9a391ad8 BS	108	ret = nouveau_dma_wait(chan, 1, size);
	109	if (ret)
	110	return ret;
6ee73861 BS	111
	112	chan->dma.free -= size;
	113	return 0;
	114	}
	115
	116	static inline void
	117	OUT_RING(struct nouveau_channel *chan, int data)
	118	{
ebb945a9	119	nouveau_bo_wr32(chan->push.buffer, chan->dma.cur++, data);
6ee73861 BS	120	}
	121
	122	extern void
	123	OUT_RINGp(struct nouveau_channel chan, const void data, unsigned nr_dwords);
	124
96545299	125	static inline void
6d597027	126	BEGIN_NV04(struct nouveau_channel *chan, int subc, int mthd, int size)
96545299	127	{
6d597027	128	OUT_RING(chan, 0x00000000 \| (subc << 13) \| (size << 18) \| mthd);
96545299 BS	129	}
96545299 BS	130
6ee73861	131	static inline void
6d597027	132	BEGIN_NI04(struct nouveau_channel *chan, int subc, int mthd, int size)
6ee73861	133	{
6d597027 BS	134	OUT_RING(chan, 0x40000000 \| (subc << 13) \| (size << 18) \| mthd);
	135	}
	136
	137	static inline void
	138	BEGIN_NVC0(struct nouveau_channel *chan, int subc, int mthd, int size)
	139	{
	140	OUT_RING(chan, 0x20000000 \| (size << 16) \| (subc << 13) \| (mthd >> 2));
	141	}
	142
	143	static inline void
	144	BEGIN_NIC0(struct nouveau_channel *chan, int subc, int mthd, int size)
	145	{
	146	OUT_RING(chan, 0x60000000 \| (size << 16) \| (subc << 13) \| (mthd >> 2));
	147	}
	148
	149	static inline void
	150	BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
	151	{
	152	OUT_RING(chan, 0x80000000 \| (data << 16) \| (subc << 13) \| (mthd >> 2));
6ee73861 BS	153	}
	154
	155	#define WRITE_PUT(val) do { \
	156	DRM_MEMORYBARRIER(); \
ebb945a9 BS	157	nouveau_bo_rd32(chan->push.buffer, 0); \
ebb945a9 BS	158	nv_wo32(chan->object, chan->user_put, ((val) << 2) + chan->push.vma.offset); \
6ee73861 BS	159	} while (0)
	160
	161	static inline void
	162	FIRE_RING(struct nouveau_channel *chan)
	163	{
6ee73861 BS	164	if (chan->dma.cur == chan->dma.put)
	165	return;
	166	chan->accel_done = true;
	167
9a391ad8	168	if (chan->dma.ib_max) {
ebb945a9	169	nv50_dma_push(chan, chan->push.buffer, chan->dma.put << 2,
a1606a95	170	(chan->dma.cur - chan->dma.put) << 2);
9a391ad8 BS	171	} else {
	172	WRITE_PUT(chan->dma.cur);
	173	}
	174
6ee73861 BS	175	chan->dma.put = chan->dma.cur;
	176	}
	177
	178	static inline void
	179	WIND_RING(struct nouveau_channel *chan)
	180	{
	181	chan->dma.cur = chan->dma.put;
	182	}
	183
ebb945a9 BS	184	/* FIFO methods */
	185	#define NV01_SUBCHAN_OBJECT 0x00000000
	186	#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_HIGH 0x00000010
	187	#define NV84_SUBCHAN_SEMAPHORE_ADDRESS_LOW 0x00000014
	188	#define NV84_SUBCHAN_SEMAPHORE_SEQUENCE 0x00000018
	189	#define NV84_SUBCHAN_SEMAPHORE_TRIGGER 0x0000001c
	190	#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_EQUAL 0x00000001
	191	#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_WRITE_LONG 0x00000002
	192	#define NV84_SUBCHAN_SEMAPHORE_TRIGGER_ACQUIRE_GEQUAL 0x00000004
	193	#define NVC0_SUBCHAN_SEMAPHORE_TRIGGER_YIELD 0x00001000
	194	#define NV84_SUBCHAN_NOTIFY_INTR 0x00000020
	195	#define NV84_SUBCHAN_WRCACHE_FLUSH 0x00000024
	196	#define NV10_SUBCHAN_REF_CNT 0x00000050
	197	#define NVSW_SUBCHAN_PAGE_FLIP 0x00000054
	198	#define NV11_SUBCHAN_DMA_SEMAPHORE 0x00000060
	199	#define NV11_SUBCHAN_SEMAPHORE_OFFSET 0x00000064
	200	#define NV11_SUBCHAN_SEMAPHORE_ACQUIRE 0x00000068
	201	#define NV11_SUBCHAN_SEMAPHORE_RELEASE 0x0000006c
	202	#define NV40_SUBCHAN_YIELD 0x00000080
	203
	204	/* NV_SW object class */
	205	#define NV_SW_DMA_VBLSEM 0x0000018c
	206	#define NV_SW_VBLSEM_OFFSET 0x00000400
	207	#define NV_SW_VBLSEM_RELEASE_VALUE 0x00000404
	208	#define NV_SW_VBLSEM_RELEASE 0x00000408
	209	#define NV_SW_PAGE_FLIP 0x00000500
	210
6ee73861	211	#endif