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drm/nouveau/disp: parse connector info directly in nouveau_connector.c
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861 30
67eda20e
FJ		 31#include <linux/io-mapping.h>
32
6ee73861
BS		 33/* these defines are made up */
34#define NV_CIO_CRE_44_HEADA 0x0
35#define NV_CIO_CRE_44_HEADB 0x3
36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
6ee73861
BS		 37
38#define EDID1_LEN 128
39
40#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41#define LOG_OLD_VALUE(x)
42
6ee73861
BS		 43struct init_exec {
44 bool execute;
45 bool repeat;
46};
47
48static bool nv_cksum(const uint8_t *data, unsigned int length)
49{
50 /*
51 * There's a few checksums in the BIOS, so here's a generic checking
52 * function.
53 */
54 int i;
55 uint8_t sum = 0;
56
57 for (i = 0; i < length; i++)
58 sum += data[i];
59
60 if (sum)
61 return true;
62
63 return false;
64}
65
66static int
67score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
68{
69 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
70 NV_TRACEWARN(dev, "... BIOS signature not found\n");
71 return 0;
72 }
73
74 if (nv_cksum(data, data[2] * 512)) {
75 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
76 /* if a ro image is somewhat bad, it's probably all rubbish */
77 return writeable ? 2 : 1;
78 } else
79 NV_TRACE(dev, "... appears to be valid\n");
80
81 return 3;
82}
83
84static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
85{
86 struct drm_nouveau_private *dev_priv = dev->dev_private;
87 uint32_t pci_nv_20, save_pci_nv_20;
88 int pcir_ptr;
89 int i;
90
91 if (dev_priv->card_type >= NV_50)
92 pci_nv_20 = 0x88050;
93 else
94 pci_nv_20 = NV_PBUS_PCI_NV_20;
95
96 /* enable ROM access */
97 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
98 nvWriteMC(dev, pci_nv_20,
99 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
100
101 /* bail if no rom signature */
102 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
103 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
104 goto out;
105
106 /* additional check (see note below) - read PCI record header */
107 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
108 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
109 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
110 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
111 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
112 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
113 goto out;
114
115 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
116 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
117 * each byte. we'll hope pramin has something usable instead
118 */
119 for (i = 0; i < NV_PROM_SIZE; i++)
120 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
121
122out:
123 /* disable ROM access */
124 nvWriteMC(dev, pci_nv_20,
125 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
126}
127
128static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
129{
130 struct drm_nouveau_private *dev_priv = dev->dev_private;
131 uint32_t old_bar0_pramin = 0;
132 int i;
133
134 if (dev_priv->card_type >= NV_50) {
9617757f
BS		 135 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
136 if (!addr) {
137 addr = (u64)nv_rd32(dev, 0x1700) << 16;
138 addr += 0xf0000;
139 }
6ee73861
BS		 140
141 old_bar0_pramin = nv_rd32(dev, 0x1700);
9617757f 142 nv_wr32(dev, 0x1700, addr >> 16);
6ee73861
BS		 143 }
144
145 /* bail if no rom signature */
146 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
147 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
148 goto out;
149
150 for (i = 0; i < NV_PROM_SIZE; i++)
151 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
152
153out:
154 if (dev_priv->card_type >= NV_50)
155 nv_wr32(dev, 0x1700, old_bar0_pramin);
156}
157
158static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
159{
160 void __iomem *rom = NULL;
161 size_t rom_len;
162 int ret;
163
164 ret = pci_enable_rom(dev->pdev);
165 if (ret)
166 return;
167
168 rom = pci_map_rom(dev->pdev, &rom_len);
169 if (!rom)
170 goto out;
171 memcpy_fromio(data, rom, rom_len);
172 pci_unmap_rom(dev->pdev, rom);
173
174out:
175 pci_disable_rom(dev->pdev);
176}
177
afeb3e11
DA		 178static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
179{
180 int i;
181 int ret;
182 int size = 64 * 1024;
183
184 if (!nouveau_acpi_rom_supported(dev->pdev))
185 return;
186
187 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
188 ret = nouveau_acpi_get_bios_chunk(data,
189 (i * ROM_BIOS_PAGE),
190 ROM_BIOS_PAGE);
191 if (ret <= 0)
192 break;
193 }
194 return;
195}
196
6ee73861
BS		 197struct methods {
198 const char desc[8];
199 void (*loadbios)(struct drm_device *, uint8_t *);
200 const bool rw;
6ee73861
BS		 201};
202
41090eb4 203static struct methods shadow_methods[] = {
6ee73861
BS		 204 { "PRAMIN", load_vbios_pramin, true },
205 { "PROM", load_vbios_prom, false },
206 { "PCIROM", load_vbios_pci, true },
41090eb4 207 { "ACPI", load_vbios_acpi, true },
6ee73861 208};
eae6192a 209#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
6ee73861
BS		 210
211static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
212{
41090eb4 213 struct methods *methods = shadow_methods;
6ee73861 214 int testscore = 3;
eae6192a 215 int scores[NUM_SHADOW_METHODS], i;
6ee73861
BS		 216
217 if (nouveau_vbios) {
eae6192a 218 for (i = 0; i < NUM_SHADOW_METHODS; i++)
657b6245 219 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 220 break;
6ee73861 221
eae6192a 222 if (i < NUM_SHADOW_METHODS) {
6ee73861 223 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 224 methods[i].desc);
6ee73861 225
657b6245
MK		 226 methods[i].loadbios(dev, data);
227 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 228 return true;
229 }
230
231 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
232 }
233
eae6192a 234 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
6ee73861 235 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 236 methods[i].desc);
6ee73861 237 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 238 methods[i].loadbios(dev, data);
239 scores[i] = score_vbios(dev, data, methods[i].rw);
240 if (scores[i] == testscore)
6ee73861 241 return true;
6ee73861
BS		 242 }
243
244 while (--testscore > 0) {
eae6192a 245 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
657b6245 246 if (scores[i] == testscore) {
6ee73861 247 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 248 methods[i].desc);
249 methods[i].loadbios(dev, data);
6ee73861
BS		 250 return true;
251 }
6ee73861
BS		 252 }
253 }
254
255 NV_ERROR(dev, "No valid BIOS image found\n");
256 return false;
257}
258
259struct init_tbl_entry {
260 char *name;
261 uint8_t id;
9170a824
BS		 262 /* Return:
263 * > 0: success, length of opcode
264 * 0: success, but abort further parsing of table (INIT_DONE etc)
265 * < 0: failure, table parsing will be aborted
266 */
37383650 267 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 268};
269
ec64a408 270static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 271
272#define MACRO_INDEX_SIZE 2
273#define MACRO_SIZE 8
274#define CONDITION_SIZE 12
275#define IO_FLAG_CONDITION_SIZE 9
276#define IO_CONDITION_SIZE 5
277#define MEM_INIT_SIZE 66
278
279static void still_alive(void)
280{
281#if 0
282 sync();
c7ca4d1b 283 mdelay(2);
6ee73861
BS		 284#endif
285}
286
287static uint32_t
288munge_reg(struct nvbios *bios, uint32_t reg)
289{
290 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
291 struct dcb_entry *dcbent = bios->display.output;
292
293 if (dev_priv->card_type < NV_50)
294 return reg;
295
02e4f587
BS		 296 if (reg & 0x80000000) {
297 BUG_ON(bios->display.crtc < 0);
298 reg += bios->display.crtc * 0x800;
299 }
300
6ee73861
BS		 301 if (reg & 0x40000000) {
302 BUG_ON(!dcbent);
303
304 reg += (ffs(dcbent->or) - 1) * 0x800;
305 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
306 reg += 0x00000080;
307 }
308
02e4f587 309 reg &= ~0xe0000000;
6ee73861
BS		 310 return reg;
311}
312
313static int
314valid_reg(struct nvbios *bios, uint32_t reg)
315{
316 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
317 struct drm_device *dev = bios->dev;
318
319 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 320 if (reg & 0x2 ||
04a39c57 321 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 322 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
323
324 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 325 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 326 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
327 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
328 reg);
329
9855e584
BS		 330 if (reg >= (8*1024*1024)) {
331 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
332 return 0;
6ee73861 333 }
9855e584
BS		 334
335 return 1;
6ee73861
BS		 336}
337
338static bool
339valid_idx_port(struct nvbios *bios, uint16_t port)
340{
341 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
342 struct drm_device *dev = bios->dev;
343
344 /*
345 * If adding more ports here, the read/write functions below will need
346 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
347 * used for the port in question
348 */
349 if (dev_priv->card_type < NV_50) {
350 if (port == NV_CIO_CRX__COLOR)
351 return true;
352 if (port == NV_VIO_SRX)
353 return true;
354 } else {
355 if (port == NV_CIO_CRX__COLOR)
356 return true;
357 }
358
359 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
360 port);
361
362 return false;
363}
364
365static bool
366valid_port(struct nvbios *bios, uint16_t port)
367{
368 struct drm_device *dev = bios->dev;
369
370 /*
371 * If adding more ports here, the read/write functions below will need
372 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
373 * used for the port in question
374 */
375 if (port == NV_VIO_VSE2)
376 return true;
377
378 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
379
380 return false;
381}
382
383static uint32_t
384bios_rd32(struct nvbios *bios, uint32_t reg)
385{
386 uint32_t data;
387
388 reg = munge_reg(bios, reg);
389 if (!valid_reg(bios, reg))
390 return 0;
391
392 /*
393 * C51 sometimes uses regs with bit0 set in the address. For these
394 * cases there should exist a translation in a BIOS table to an IO
395 * port address which the BIOS uses for accessing the reg
396 *
397 * These only seem to appear for the power control regs to a flat panel,
398 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
399 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
400 * suspend-resume mmio trace from a C51 will be required to see if this
401 * is true for the power microcode in 0x14.., or whether the direct IO
402 * port access method is needed
403 */
404 if (reg & 0x1)
405 reg &= ~0x1;
406
407 data = nv_rd32(bios->dev, reg);
408
409 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
410
411 return data;
412}
413
414static void
415bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
416{
417 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
418
419 reg = munge_reg(bios, reg);
420 if (!valid_reg(bios, reg))
421 return;
422
423 /* see note in bios_rd32 */
424 if (reg & 0x1)
425 reg &= 0xfffffffe;
426
427 LOG_OLD_VALUE(bios_rd32(bios, reg));
428 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
429
04a39c57 430 if (dev_priv->vbios.execute) {
6ee73861
BS		 431 still_alive();
432 nv_wr32(bios->dev, reg, data);
433 }
434}
435
436static uint8_t
437bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
438{
439 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
440 struct drm_device *dev = bios->dev;
441 uint8_t data;
442
443 if (!valid_idx_port(bios, port))
444 return 0;
445
446 if (dev_priv->card_type < NV_50) {
447 if (port == NV_VIO_SRX)
448 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
449 else /* assume NV_CIO_CRX__COLOR */
450 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
451 } else {
452 uint32_t data32;
453
454 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
455 data = (data32 >> ((index & 3) << 3)) & 0xff;
456 }
457
458 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
459 "Head: 0x%02X, Data: 0x%02X\n",
460 port, index, bios->state.crtchead, data);
461 return data;
462}
463
464static void
465bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
466{
467 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
468 struct drm_device *dev = bios->dev;
469
470 if (!valid_idx_port(bios, port))
471 return;
472
473 /*
474 * The current head is maintained in the nvbios member state.crtchead.
475 * We trap changes to CR44 and update the head variable and hence the
476 * register set written.
477 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
478 * of the write, and to head1 after the write
479 */
480 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
481 data != NV_CIO_CRE_44_HEADB)
482 bios->state.crtchead = 0;
483
484 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
485 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
486 "Head: 0x%02X, Data: 0x%02X\n",
487 port, index, bios->state.crtchead, data);
488
489 if (bios->execute && dev_priv->card_type < NV_50) {
490 still_alive();
491 if (port == NV_VIO_SRX)
492 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
493 else /* assume NV_CIO_CRX__COLOR */
494 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
495 } else
496 if (bios->execute) {
497 uint32_t data32, shift = (index & 3) << 3;
498
499 still_alive();
500
501 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
502 data32 &= ~(0xff << shift);
503 data32 |= (data << shift);
504 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
505 }
506
507 if (port == NV_CIO_CRX__COLOR &&
508 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
509 bios->state.crtchead = 1;
510}
511
512static uint8_t
513bios_port_rd(struct nvbios *bios, uint16_t port)
514{
515 uint8_t data, head = bios->state.crtchead;
516
517 if (!valid_port(bios, port))
518 return 0;
519
520 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
521
522 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
523 port, head, data);
524
525 return data;
526}
527
528static void
529bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
530{
531 int head = bios->state.crtchead;
532
533 if (!valid_port(bios, port))
534 return;
535
536 LOG_OLD_VALUE(bios_port_rd(bios, port));
537 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
538 port, head, data);
539
540 if (!bios->execute)
541 return;
542
543 still_alive();
544 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
545}
546
547static bool
548io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
549{
550 /*
551 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
552 * for the CRTC index; 1 byte for the mask to apply to the value
553 * retrieved from the CRTC; 1 byte for the shift right to apply to the
554 * masked CRTC value; 2 bytes for the offset to the flag array, to
555 * which the shifted value is added; 1 byte for the mask applied to the
556 * value read from the flag array; and 1 byte for the value to compare
557 * against the masked byte from the flag table.
558 */
559
560 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
561 uint16_t crtcport = ROM16(bios->data[condptr]);
562 uint8_t crtcindex = bios->data[condptr + 2];
563 uint8_t mask = bios->data[condptr + 3];
564 uint8_t shift = bios->data[condptr + 4];
565 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
566 uint8_t flagarraymask = bios->data[condptr + 7];
567 uint8_t cmpval = bios->data[condptr + 8];
568 uint8_t data;
569
570 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
571 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
572 "Cmpval: 0x%02X\n",
573 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
574
575 data = bios_idxprt_rd(bios, crtcport, crtcindex);
576
577 data = bios->data[flagarray + ((data & mask) >> shift)];
578 data &= flagarraymask;
579
580 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
581 offset, data, cmpval);
582
583 return (data == cmpval);
584}
585
586static bool
587bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
588{
589 /*
590 * The condition table entry has 4 bytes for the address of the
591 * register to check, 4 bytes for a mask to apply to the register and
592 * 4 for a test comparison value
593 */
594
595 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
596 uint32_t reg = ROM32(bios->data[condptr]);
597 uint32_t mask = ROM32(bios->data[condptr + 4]);
598 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
599 uint32_t data;
600
601 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
602 offset, cond, reg, mask);
603
604 data = bios_rd32(bios, reg) & mask;
605
606 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
607 offset, data, cmpval);
608
609 return (data == cmpval);
610}
611
612static bool
613io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
614{
615 /*
616 * The IO condition entry has 2 bytes for the IO port address; 1 byte
617 * for the index to write to io_port; 1 byte for the mask to apply to
618 * the byte read from io_port+1; and 1 byte for the value to compare
619 * against the masked byte.
620 */
621
622 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
623 uint16_t io_port = ROM16(bios->data[condptr]);
624 uint8_t port_index = bios->data[condptr + 2];
625 uint8_t mask = bios->data[condptr + 3];
626 uint8_t cmpval = bios->data[condptr + 4];
627
628 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
629
630 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
631 offset, data, cmpval);
632
633 return (data == cmpval);
634}
635
636static int
637nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
638{
639 struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861
BS		 640 struct nouveau_pll_vals pll;
641 struct pll_lims pll_limits;
ee9f7ef9 642 u32 ctrl, mask, coef;
6ee73861
BS		 643 int ret;
644
645 ret = get_pll_limits(dev, reg, &pll_limits);
646 if (ret)
647 return ret;
648
649 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
650 if (!clk)
651 return -ERANGE;
652
ee9f7ef9
BS		 653 coef = pll.N1 << 8 | pll.M1;
654 ctrl = pll.log2P << 16;
655 mask = 0x00070000;
656 if (reg == 0x004008) {
657 mask |= 0x01f80000;
658 ctrl |= (pll_limits.log2p_bias << 19);
659 ctrl |= (pll.log2P << 22);
6ee73861
BS		 660 }
661
ee9f7ef9
BS		 662 if (!dev_priv->vbios.execute)
663 return 0;
664
665 nv_mask(dev, reg + 0, mask, ctrl);
666 nv_wr32(dev, reg + 4, coef);
6ee73861
BS		 667 return 0;
668}
669
670static int
671setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
672{
673 struct drm_device *dev = bios->dev;
674 struct drm_nouveau_private *dev_priv = dev->dev_private;
675 /* clk in kHz */
676 struct pll_lims pll_lim;
677 struct nouveau_pll_vals pllvals;
678 int ret;
679
680 if (dev_priv->card_type >= NV_50)
681 return nv50_pll_set(dev, reg, clk);
682
683 /* high regs (such as in the mac g5 table) are not -= 4 */
684 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
685 if (ret)
686 return ret;
687
688 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
689 if (!clk)
690 return -ERANGE;
691
692 if (bios->execute) {
693 still_alive();
694 nouveau_hw_setpll(dev, reg, &pllvals);
695 }
696
697 return 0;
698}
699
700static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
701{
702 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 703 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 704
705 /*
706 * For the results of this function to be correct, CR44 must have been
707 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
708 * and the DCB table parsed, before the script calling the function is
709 * run. run_digital_op_script is example of how to do such setup
710 */
711
712 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
713
7f245b20 714 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 715 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
716 "(%02X)\n", dcb_entry);
717 dcb_entry = 0x7f; /* unused / invalid marker */
718 }
719
720 return dcb_entry;
721}
722
723static struct nouveau_i2c_chan *
724init_i2c_device_find(struct drm_device *dev, int i2c_index)
725{
6ee73861 726 if (i2c_index == 0xff) {
486a45c2
BS		 727 struct drm_nouveau_private *dev_priv = dev->dev_private;
728 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861 729 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
486a45c2 730 int idx = dcb_entry_idx_from_crtchead(dev);
6ee73861 731
486a45c2 732 i2c_index = NV_I2C_DEFAULT(0);
7f245b20 733 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
486a45c2 734 i2c_index = NV_I2C_DEFAULT(1);
f8b0be1a
BS		 735 }
736
6ee73861
BS		 737 return nouveau_i2c_find(dev, i2c_index);
738}
739
7f245b20
BS		 740static uint32_t
741get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 742{
743 /*
744 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
745 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
746 * CR58 for CR57 = 0 to index a table of offsets to the basic
747 * 0x6808b0 address.
748 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
749 * CR58 for CR57 = 0 to index a table of offsets to the basic
750 * 0x6808b0 address, and then flip the offset by 8.
751 */
752
753 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 754 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 755 const int pramdac_offset[13] = {
756 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
757 const uint32_t pramdac_table[4] = {
758 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
759
760 if (mlv >= 0x80) {
761 int dcb_entry, dacoffset;
762
763 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
764 dcb_entry = dcb_entry_idx_from_crtchead(dev);
765 if (dcb_entry == 0x7f)
766 return 0;
7f245b20 767 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 768 if (mlv == 0x81)
769 dacoffset ^= 8;
770 return 0x6808b0 + dacoffset;
771 } else {
df31ef4d 772 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 773 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
774 mlv);
775 return 0;
776 }
777 return pramdac_table[mlv];
778 }
779}
780
37383650 781static int
6ee73861
BS		 782init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
783 struct init_exec *iexec)
784{
785 /*
786 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
787 *
788 * offset (8 bit): opcode
789 * offset + 1 (16 bit): CRTC port
790 * offset + 3 (8 bit): CRTC index
791 * offset + 4 (8 bit): mask
792 * offset + 5 (8 bit): shift
793 * offset + 6 (8 bit): count
794 * offset + 7 (32 bit): register
795 * offset + 11 (32 bit): configuration 1
796 * ...
797 *
798 * Starting at offset + 11 there are "count" 32 bit values.
799 * To find out which value to use read index "CRTC index" on "CRTC
800 * port", AND this value with "mask" and then bit shift right "shift"
801 * bits. Read the appropriate value using this index and write to
802 * "register"
803 */
804
805 uint16_t crtcport = ROM16(bios->data[offset + 1]);
806 uint8_t crtcindex = bios->data[offset + 3];
807 uint8_t mask = bios->data[offset + 4];
808 uint8_t shift = bios->data[offset + 5];
809 uint8_t count = bios->data[offset + 6];
810 uint32_t reg = ROM32(bios->data[offset + 7]);
811 uint8_t config;
812 uint32_t configval;
37383650 813 int len = 11 + count * 4;
6ee73861
BS		 814
815 if (!iexec->execute)
37383650 816 return len;
6ee73861
BS		 817
818 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
819 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
820 offset, crtcport, crtcindex, mask, shift, count, reg);
821
822 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
823 if (config > count) {
824 NV_ERROR(bios->dev,
825 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
826 offset, config, count);
309b8c89 827 return len;
6ee73861
BS		 828 }
829
830 configval = ROM32(bios->data[offset + 11 + config * 4]);
831
832 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
833
834 bios_wr32(bios, reg, configval);
835
37383650 836 return len;
6ee73861
BS		 837}
838
37383650 839static int
6ee73861
BS		 840init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
841{
842 /*
843 * INIT_REPEAT opcode: 0x33 ('3')
844 *
845 * offset (8 bit): opcode
846 * offset + 1 (8 bit): count
847 *
848 * Execute script following this opcode up to INIT_REPEAT_END
849 * "count" times
850 */
851
852 uint8_t count = bios->data[offset + 1];
853 uint8_t i;
854
855 /* no iexec->execute check by design */
856
857 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
858 offset, count);
859
860 iexec->repeat = true;
861
862 /*
863 * count - 1, as the script block will execute once when we leave this
864 * opcode -- this is compatible with bios behaviour as:
865 * a) the block is always executed at least once, even if count == 0
866 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
867 * while we don't
868 */
869 for (i = 0; i < count - 1; i++)
870 parse_init_table(bios, offset + 2, iexec);
871
872 iexec->repeat = false;
873
37383650 874 return 2;
6ee73861
BS		 875}
876
37383650 877static int
6ee73861
BS		 878init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
879 struct init_exec *iexec)
880{
881 /*
882 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
883 *
884 * offset (8 bit): opcode
885 * offset + 1 (16 bit): CRTC port
886 * offset + 3 (8 bit): CRTC index
887 * offset + 4 (8 bit): mask
888 * offset + 5 (8 bit): shift
889 * offset + 6 (8 bit): IO flag condition index
890 * offset + 7 (8 bit): count
891 * offset + 8 (32 bit): register
892 * offset + 12 (16 bit): frequency 1
893 * ...
894 *
895 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
896 * Set PLL register "register" to coefficients for frequency n,
897 * selected by reading index "CRTC index" of "CRTC port" ANDed with
898 * "mask" and shifted right by "shift".
899 *
900 * If "IO flag condition index" > 0, and condition met, double
901 * frequency before setting it.
902 */
903
904 uint16_t crtcport = ROM16(bios->data[offset + 1]);
905 uint8_t crtcindex = bios->data[offset + 3];
906 uint8_t mask = bios->data[offset + 4];
907 uint8_t shift = bios->data[offset + 5];
908 int8_t io_flag_condition_idx = bios->data[offset + 6];
909 uint8_t count = bios->data[offset + 7];
910 uint32_t reg = ROM32(bios->data[offset + 8]);
911 uint8_t config;
912 uint16_t freq;
37383650 913 int len = 12 + count * 2;
6ee73861
BS		 914
915 if (!iexec->execute)
37383650 916 return len;
6ee73861
BS		 917
918 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
919 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
920 "Count: 0x%02X, Reg: 0x%08X\n",
921 offset, crtcport, crtcindex, mask, shift,
922 io_flag_condition_idx, count, reg);
923
924 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
925 if (config > count) {
926 NV_ERROR(bios->dev,
927 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
928 offset, config, count);
309b8c89 929 return len;
6ee73861
BS		 930 }
931
932 freq = ROM16(bios->data[offset + 12 + config * 2]);
933
934 if (io_flag_condition_idx > 0) {
935 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
936 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
937 "frequency doubled\n", offset);
938 freq *= 2;
939 } else
940 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
941 "frequency unchanged\n", offset);
942 }
943
944 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
945 offset, reg, config, freq);
946
947 setPLL(bios, reg, freq * 10);
948
37383650 949 return len;
6ee73861
BS		 950}
951
37383650 952static int
6ee73861
BS		 953init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
954{
955 /*
956 * INIT_END_REPEAT opcode: 0x36 ('6')
957 *
958 * offset (8 bit): opcode
959 *
960 * Marks the end of the block for INIT_REPEAT to repeat
961 */
962
963 /* no iexec->execute check by design */
964
965 /*
966 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
967 * we're not in repeat mode
968 */
969 if (iexec->repeat)
37383650 970 return 0;
6ee73861 971
37383650 972 return 1;
6ee73861
BS		 973}
974
37383650 975static int
6ee73861
BS		 976init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
977{
978 /*
979 * INIT_COPY opcode: 0x37 ('7')
980 *
981 * offset (8 bit): opcode
982 * offset + 1 (32 bit): register
983 * offset + 5 (8 bit): shift
984 * offset + 6 (8 bit): srcmask
985 * offset + 7 (16 bit): CRTC port
986 * offset + 9 (8 bit): CRTC index
987 * offset + 10 (8 bit): mask
988 *
989 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
990 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
991 * port
992 */
993
994 uint32_t reg = ROM32(bios->data[offset + 1]);
995 uint8_t shift = bios->data[offset + 5];
996 uint8_t srcmask = bios->data[offset + 6];
997 uint16_t crtcport = ROM16(bios->data[offset + 7]);
998 uint8_t crtcindex = bios->data[offset + 9];
999 uint8_t mask = bios->data[offset + 10];
1000 uint32_t data;
1001 uint8_t crtcdata;
1002
1003 if (!iexec->execute)
37383650 1004 return 11;
6ee73861
BS		 1005
1006 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1007 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1008 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1009
1010 data = bios_rd32(bios, reg);
1011
1012 if (shift < 0x80)
1013 data >>= shift;
1014 else
1015 data <<= (0x100 - shift);
1016
1017 data &= srcmask;
1018
1019 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1020 crtcdata |= (uint8_t)data;
1021 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1022
37383650 1023 return 11;
6ee73861
BS		 1024}
1025
37383650 1026static int
6ee73861
BS		 1027init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1028{
1029 /*
1030 * INIT_NOT opcode: 0x38 ('8')
1031 *
1032 * offset (8 bit): opcode
1033 *
1034 * Invert the current execute / no-execute condition (i.e. "else")
1035 */
1036 if (iexec->execute)
1037 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1038 else
1039 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1040
1041 iexec->execute = !iexec->execute;
37383650 1042 return 1;
6ee73861
BS		 1043}
1044
37383650 1045static int
6ee73861
BS		 1046init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1047 struct init_exec *iexec)
1048{
1049 /*
1050 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1051 *
1052 * offset (8 bit): opcode
1053 * offset + 1 (8 bit): condition number
1054 *
1055 * Check condition "condition number" in the IO flag condition table.
1056 * If condition not met skip subsequent opcodes until condition is
1057 * inverted (INIT_NOT), or we hit INIT_RESUME
1058 */
1059
1060 uint8_t cond = bios->data[offset + 1];
1061
1062 if (!iexec->execute)
37383650 1063 return 2;
6ee73861
BS		 1064
1065 if (io_flag_condition_met(bios, offset, cond))
1066 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1067 else {
1068 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1069 iexec->execute = false;
1070 }
1071
37383650 1072 return 2;
6ee73861
BS		 1073}
1074
25908b77
BS		 1075static int
1076init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1077{
1078 /*
1079 * INIT_DP_CONDITION opcode: 0x3A ('')
1080 *
1081 * offset (8 bit): opcode
1082 * offset + 1 (8 bit): "sub" opcode
1083 * offset + 2 (8 bit): unknown
1084 *
1085 */
1086
25908b77
BS		 1087 struct dcb_entry *dcb = bios->display.output;
1088 struct drm_device *dev = bios->dev;
1089 uint8_t cond = bios->data[offset + 1];
5f1800bd 1090 uint8_t *table, *entry;
25908b77
BS		 1091
1092 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1093
1094 if (!iexec->execute)
1095 return 3;
1096
5f1800bd
BS		 1097 table = nouveau_dp_bios_data(dev, dcb, &entry);
1098 if (!table)
309b8c89 1099 return 3;
25908b77
BS		 1100
1101 switch (cond) {
1102 case 0:
befb51e9
BS		 1103 entry = dcb_conn(dev, dcb->connector);
1104 if (!entry || entry[0] != DCB_CONNECTOR_eDP)
25908b77 1105 iexec->execute = false;
25908b77
BS		 1106 break;
1107 case 1:
1108 case 2:
5f1800bd 1109 if (!(entry[5] & cond))
25908b77
BS		 1110 iexec->execute = false;
1111 break;
1112 case 5:
1113 {
1114 struct nouveau_i2c_chan *auxch;
1115 int ret;
1116
1117 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
309b8c89
BS		 1118 if (!auxch) {
1119 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1120 return 3;
1121 }
25908b77
BS		 1122
1123 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
309b8c89
BS		 1124 if (ret) {
1125 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1126 return 3;
1127 }
25908b77 1128
64d202b4 1129 if (!(cond & 1))
25908b77
BS		 1130 iexec->execute = false;
1131 }
1132 break;
1133 default:
1134 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1135 break;
1136 }
1137
1138 if (iexec->execute)
1139 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1140 else
1141 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1142
1143 return 3;
1144}
1145
1146static int
1147init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1148{
1149 /*
1150 * INIT_3B opcode: 0x3B ('')
1151 *
1152 * offset (8 bit): opcode
1153 * offset + 1 (8 bit): crtc index
1154 *
1155 */
1156
1157 uint8_t or = ffs(bios->display.output->or) - 1;
1158 uint8_t index = bios->data[offset + 1];
1159 uint8_t data;
1160
1161 if (!iexec->execute)
1162 return 2;
1163
1164 data = bios_idxprt_rd(bios, 0x3d4, index);
1165 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1166 return 2;
1167}
1168
1169static int
1170init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1171{
1172 /*
1173 * INIT_3C opcode: 0x3C ('')
1174 *
1175 * offset (8 bit): opcode
1176 * offset + 1 (8 bit): crtc index
1177 *
1178 */
1179
1180 uint8_t or = ffs(bios->display.output->or) - 1;
1181 uint8_t index = bios->data[offset + 1];
1182 uint8_t data;
1183
1184 if (!iexec->execute)
1185 return 2;
1186
1187 data = bios_idxprt_rd(bios, 0x3d4, index);
1188 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1189 return 2;
1190}
1191
37383650 1192static int
6ee73861
BS		 1193init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1194 struct init_exec *iexec)
1195{
1196 /*
1197 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1198 *
1199 * offset (8 bit): opcode
1200 * offset + 1 (32 bit): control register
1201 * offset + 5 (32 bit): data register
1202 * offset + 9 (32 bit): mask
1203 * offset + 13 (32 bit): data
1204 * offset + 17 (8 bit): count
1205 * offset + 18 (8 bit): address 1
1206 * offset + 19 (8 bit): data 1
1207 * ...
1208 *
1209 * For each of "count" address and data pairs, write "data n" to
1210 * "data register", read the current value of "control register",
1211 * and write it back once ANDed with "mask", ORed with "data",
1212 * and ORed with "address n"
1213 */
1214
1215 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1216 uint32_t datareg = ROM32(bios->data[offset + 5]);
1217 uint32_t mask = ROM32(bios->data[offset + 9]);
1218 uint32_t data = ROM32(bios->data[offset + 13]);
1219 uint8_t count = bios->data[offset + 17];
37383650 1220 int len = 18 + count * 2;
6ee73861
BS		 1221 uint32_t value;
1222 int i;
1223
1224 if (!iexec->execute)
37383650 1225 return len;
6ee73861
BS		 1226
1227 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1228 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1229 offset, controlreg, datareg, mask, data, count);
1230
1231 for (i = 0; i < count; i++) {
1232 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1233 uint8_t instdata = bios->data[offset + 19 + i * 2];
1234
1235 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1236 offset, instaddress, instdata);
1237
1238 bios_wr32(bios, datareg, instdata);
1239 value = bios_rd32(bios, controlreg) & mask;
1240 value |= data;
1241 value |= instaddress;
1242 bios_wr32(bios, controlreg, value);
1243 }
1244
37383650 1245 return len;
6ee73861
BS		 1246}
1247
37383650 1248static int
6ee73861
BS		 1249init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1250 struct init_exec *iexec)
1251{
1252 /*
1253 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1254 *
1255 * offset (8 bit): opcode
1256 * offset + 1 (16 bit): CRTC port
1257 * offset + 3 (8 bit): CRTC index
1258 * offset + 4 (8 bit): mask
1259 * offset + 5 (8 bit): shift
1260 * offset + 6 (8 bit): count
1261 * offset + 7 (32 bit): register
1262 * offset + 11 (32 bit): frequency 1
1263 * ...
1264 *
1265 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1266 * Set PLL register "register" to coefficients for frequency n,
1267 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1268 * "mask" and shifted right by "shift".
1269 */
1270
1271 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1272 uint8_t crtcindex = bios->data[offset + 3];
1273 uint8_t mask = bios->data[offset + 4];
1274 uint8_t shift = bios->data[offset + 5];
1275 uint8_t count = bios->data[offset + 6];
1276 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1277 int len = 11 + count * 4;
6ee73861
BS		 1278 uint8_t config;
1279 uint32_t freq;
1280
1281 if (!iexec->execute)
37383650 1282 return len;
6ee73861
BS		 1283
1284 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1285 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1286 offset, crtcport, crtcindex, mask, shift, count, reg);
1287
1288 if (!reg)
37383650 1289 return len;
6ee73861
BS		 1290
1291 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1292 if (config > count) {
1293 NV_ERROR(bios->dev,
1294 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1295 offset, config, count);
309b8c89 1296 return len;
6ee73861
BS		 1297 }
1298
1299 freq = ROM32(bios->data[offset + 11 + config * 4]);
1300
1301 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1302 offset, reg, config, freq);
1303
1304 setPLL(bios, reg, freq);
1305
37383650 1306 return len;
6ee73861
BS		 1307}
1308
37383650 1309static int
6ee73861
BS		 1310init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1311{
1312 /*
1313 * INIT_PLL2 opcode: 0x4B ('K')
1314 *
1315 * offset (8 bit): opcode
1316 * offset + 1 (32 bit): register
1317 * offset + 5 (32 bit): freq
1318 *
1319 * Set PLL register "register" to coefficients for frequency "freq"
1320 */
1321
1322 uint32_t reg = ROM32(bios->data[offset + 1]);
1323 uint32_t freq = ROM32(bios->data[offset + 5]);
1324
1325 if (!iexec->execute)
37383650 1326 return 9;
6ee73861
BS		 1327
1328 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1329 offset, reg, freq);
1330
1331 setPLL(bios, reg, freq);
37383650 1332 return 9;
6ee73861
BS		 1333}
1334
37383650 1335static int
6ee73861
BS		 1336init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1337{
1338 /*
1339 * INIT_I2C_BYTE opcode: 0x4C ('L')
1340 *
1341 * offset (8 bit): opcode
1342 * offset + 1 (8 bit): DCB I2C table entry index
1343 * offset + 2 (8 bit): I2C slave address
1344 * offset + 3 (8 bit): count
1345 * offset + 4 (8 bit): I2C register 1
1346 * offset + 5 (8 bit): mask 1
1347 * offset + 6 (8 bit): data 1
1348 * ...
1349 *
1350 * For each of "count" registers given by "I2C register n" on the device
1351 * addressed by "I2C slave address" on the I2C bus given by
1352 * "DCB I2C table entry index", read the register, AND the result with
1353 * "mask n" and OR it with "data n" before writing it back to the device
1354 */
1355
309b8c89 1356 struct drm_device *dev = bios->dev;
6ee73861 1357 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1358 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1359 uint8_t count = bios->data[offset + 3];
1360 struct nouveau_i2c_chan *chan;
893887ed
BS		 1361 int len = 4 + count * 3;
1362 int ret, i;
6ee73861
BS		 1363
1364 if (!iexec->execute)
37383650 1365 return len;
6ee73861
BS		 1366
1367 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1368 "Count: 0x%02X\n",
1369 offset, i2c_index, i2c_address, count);
1370
309b8c89
BS		 1371 chan = init_i2c_device_find(dev, i2c_index);
1372 if (!chan) {
1373 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1374 return len;
1375 }
6ee73861
BS		 1376
1377 for (i = 0; i < count; i++) {
893887ed 1378 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1379 uint8_t mask = bios->data[offset + 5 + i * 3];
1380 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1381 union i2c_smbus_data val;
6ee73861 1382
893887ed
BS		 1383 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1384 I2C_SMBUS_READ, reg,
1385 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1386 if (ret < 0) {
1387 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1388 return len;
1389 }
6ee73861
BS		 1390
1391 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1392 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1393 offset, reg, val.byte, mask, data);
6ee73861 1394
893887ed
BS		 1395 if (!bios->execute)
1396 continue;
6ee73861 1397
893887ed
BS		 1398 val.byte &= mask;
1399 val.byte |= data;
1400 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1401 I2C_SMBUS_WRITE, reg,
1402 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1403 if (ret < 0) {
1404 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1405 return len;
1406 }
6ee73861
BS		 1407 }
1408
37383650 1409 return len;
6ee73861
BS		 1410}
1411
37383650 1412static int
6ee73861
BS		 1413init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1414{
1415 /*
1416 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1417 *
1418 * offset (8 bit): opcode
1419 * offset + 1 (8 bit): DCB I2C table entry index
1420 * offset + 2 (8 bit): I2C slave address
1421 * offset + 3 (8 bit): count
1422 * offset + 4 (8 bit): I2C register 1
1423 * offset + 5 (8 bit): data 1
1424 * ...
1425 *
1426 * For each of "count" registers given by "I2C register n" on the device
1427 * addressed by "I2C slave address" on the I2C bus given by
1428 * "DCB I2C table entry index", set the register to "data n"
1429 */
1430
309b8c89 1431 struct drm_device *dev = bios->dev;
6ee73861 1432 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1433 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1434 uint8_t count = bios->data[offset + 3];
1435 struct nouveau_i2c_chan *chan;
893887ed
BS		 1436 int len = 4 + count * 2;
1437 int ret, i;
6ee73861
BS		 1438
1439 if (!iexec->execute)
37383650 1440 return len;
6ee73861
BS		 1441
1442 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1443 "Count: 0x%02X\n",
1444 offset, i2c_index, i2c_address, count);
1445
309b8c89
BS		 1446 chan = init_i2c_device_find(dev, i2c_index);
1447 if (!chan) {
1448 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1449 return len;
1450 }
6ee73861
BS		 1451
1452 for (i = 0; i < count; i++) {
893887ed
BS		 1453 uint8_t reg = bios->data[offset + 4 + i * 2];
1454 union i2c_smbus_data val;
1455
1456 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1457
1458 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1459 offset, reg, val.byte);
1460
1461 if (!bios->execute)
1462 continue;
1463
1464 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1465 I2C_SMBUS_WRITE, reg,
1466 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1467 if (ret < 0) {
1468 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1469 return len;
1470 }
6ee73861
BS		 1471 }
1472
37383650 1473 return len;
6ee73861
BS		 1474}
1475
37383650 1476static int
6ee73861
BS		 1477init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1478{
1479 /*
1480 * INIT_ZM_I2C opcode: 0x4E ('N')
1481 *
1482 * offset (8 bit): opcode
1483 * offset + 1 (8 bit): DCB I2C table entry index
1484 * offset + 2 (8 bit): I2C slave address
1485 * offset + 3 (8 bit): count
1486 * offset + 4 (8 bit): data 1
1487 * ...
1488 *
1489 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1490 * address" on the I2C bus given by "DCB I2C table entry index"
1491 */
1492
309b8c89 1493 struct drm_device *dev = bios->dev;
6ee73861 1494 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1495 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1496 uint8_t count = bios->data[offset + 3];
37383650 1497 int len = 4 + count;
6ee73861
BS		 1498 struct nouveau_i2c_chan *chan;
1499 struct i2c_msg msg;
1500 uint8_t data[256];
309b8c89 1501 int ret, i;
6ee73861
BS		 1502
1503 if (!iexec->execute)
37383650 1504 return len;
6ee73861
BS		 1505
1506 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1507 "Count: 0x%02X\n",
1508 offset, i2c_index, i2c_address, count);
1509
309b8c89
BS		 1510 chan = init_i2c_device_find(dev, i2c_index);
1511 if (!chan) {
1512 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1513 return len;
1514 }
6ee73861
BS		 1515
1516 for (i = 0; i < count; i++) {
1517 data[i] = bios->data[offset + 4 + i];
1518
1519 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1520 }
1521
1522 if (bios->execute) {
1523 msg.addr = i2c_address;
1524 msg.flags = 0;
1525 msg.len = count;
1526 msg.buf = data;
309b8c89
BS		 1527 ret = i2c_transfer(&chan->adapter, &msg, 1);
1528 if (ret != 1) {
1529 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1530 return len;
1531 }
6ee73861
BS		 1532 }
1533
37383650 1534 return len;
6ee73861
BS		 1535}
1536
37383650 1537static int
6ee73861
BS		 1538init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1539{
1540 /*
1541 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1542 *
1543 * offset (8 bit): opcode
1544 * offset + 1 (8 bit): magic lookup value
1545 * offset + 2 (8 bit): TMDS address
1546 * offset + 3 (8 bit): mask
1547 * offset + 4 (8 bit): data
1548 *
1549 * Read the data reg for TMDS address "TMDS address", AND it with mask
1550 * and OR it with data, then write it back
1551 * "magic lookup value" determines which TMDS base address register is
1552 * used -- see get_tmds_index_reg()
1553 */
1554
309b8c89 1555 struct drm_device *dev = bios->dev;
6ee73861
BS		 1556 uint8_t mlv = bios->data[offset + 1];
1557 uint32_t tmdsaddr = bios->data[offset + 2];
1558 uint8_t mask = bios->data[offset + 3];
1559 uint8_t data = bios->data[offset + 4];
1560 uint32_t reg, value;
1561
1562 if (!iexec->execute)
37383650 1563 return 5;
6ee73861
BS		 1564
1565 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1566 "Mask: 0x%02X, Data: 0x%02X\n",
1567 offset, mlv, tmdsaddr, mask, data);
1568
1569 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1570 if (!reg) {
1571 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1572 return 5;
1573 }
6ee73861
BS		 1574
1575 bios_wr32(bios, reg,
1576 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1577 value = (bios_rd32(bios, reg + 4) & mask) | data;
1578 bios_wr32(bios, reg + 4, value);
1579 bios_wr32(bios, reg, tmdsaddr);
1580
37383650 1581 return 5;
6ee73861
BS		 1582}
1583
37383650 1584static int
6ee73861
BS		 1585init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1586 struct init_exec *iexec)
1587{
1588 /*
1589 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1590 *
1591 * offset (8 bit): opcode
1592 * offset + 1 (8 bit): magic lookup value
1593 * offset + 2 (8 bit): count
1594 * offset + 3 (8 bit): addr 1
1595 * offset + 4 (8 bit): data 1
1596 * ...
1597 *
1598 * For each of "count" TMDS address and data pairs write "data n" to
1599 * "addr n". "magic lookup value" determines which TMDS base address
1600 * register is used -- see get_tmds_index_reg()
1601 */
1602
309b8c89 1603 struct drm_device *dev = bios->dev;
6ee73861
BS		 1604 uint8_t mlv = bios->data[offset + 1];
1605 uint8_t count = bios->data[offset + 2];
37383650 1606 int len = 3 + count * 2;
6ee73861
BS		 1607 uint32_t reg;
1608 int i;
1609
1610 if (!iexec->execute)
37383650 1611 return len;
6ee73861
BS		 1612
1613 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1614 offset, mlv, count);
1615
1616 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1617 if (!reg) {
1618 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1619 return len;
1620 }
6ee73861
BS		 1621
1622 for (i = 0; i < count; i++) {
1623 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1624 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1625
1626 bios_wr32(bios, reg + 4, tmdsdata);
1627 bios_wr32(bios, reg, tmdsaddr);
1628 }
1629
37383650 1630 return len;
6ee73861
BS		 1631}
1632
37383650 1633static int
6ee73861
BS		 1634init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1635 struct init_exec *iexec)
1636{
1637 /*
1638 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1639 *
1640 * offset (8 bit): opcode
1641 * offset + 1 (8 bit): CRTC index1
1642 * offset + 2 (8 bit): CRTC index2
1643 * offset + 3 (8 bit): baseaddr
1644 * offset + 4 (8 bit): count
1645 * offset + 5 (8 bit): data 1
1646 * ...
1647 *
1648 * For each of "count" address and data pairs, write "baseaddr + n" to
1649 * "CRTC index1" and "data n" to "CRTC index2"
1650 * Once complete, restore initial value read from "CRTC index1"
1651 */
1652 uint8_t crtcindex1 = bios->data[offset + 1];
1653 uint8_t crtcindex2 = bios->data[offset + 2];
1654 uint8_t baseaddr = bios->data[offset + 3];
1655 uint8_t count = bios->data[offset + 4];
37383650 1656 int len = 5 + count;
6ee73861
BS		 1657 uint8_t oldaddr, data;
1658 int i;
1659
1660 if (!iexec->execute)
37383650 1661 return len;
6ee73861
BS		 1662
1663 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1664 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1665 offset, crtcindex1, crtcindex2, baseaddr, count);
1666
1667 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1668
1669 for (i = 0; i < count; i++) {
1670 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1671 baseaddr + i);
1672 data = bios->data[offset + 5 + i];
1673 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1674 }
1675
1676 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1677
37383650 1678 return len;
6ee73861
BS		 1679}
1680
37383650 1681static int
6ee73861
BS		 1682init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1683{
1684 /*
1685 * INIT_CR opcode: 0x52 ('R')
1686 *
1687 * offset (8 bit): opcode
1688 * offset + 1 (8 bit): CRTC index
1689 * offset + 2 (8 bit): mask
1690 * offset + 3 (8 bit): data
1691 *
1692 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1693 * data back to "CRTC index"
1694 */
1695
1696 uint8_t crtcindex = bios->data[offset + 1];
1697 uint8_t mask = bios->data[offset + 2];
1698 uint8_t data = bios->data[offset + 3];
1699 uint8_t value;
1700
1701 if (!iexec->execute)
37383650 1702 return 4;
6ee73861
BS		 1703
1704 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1705 offset, crtcindex, mask, data);
1706
1707 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1708 value |= data;
1709 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1710
37383650 1711 return 4;
6ee73861
BS		 1712}
1713
37383650 1714static int
6ee73861
BS		 1715init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1716{
1717 /*
1718 * INIT_ZM_CR opcode: 0x53 ('S')
1719 *
1720 * offset (8 bit): opcode
1721 * offset + 1 (8 bit): CRTC index
1722 * offset + 2 (8 bit): value
1723 *
1724 * Assign "value" to CRTC register with index "CRTC index".
1725 */
1726
1727 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1728 uint8_t data = bios->data[offset + 2];
1729
1730 if (!iexec->execute)
37383650 1731 return 3;
6ee73861
BS		 1732
1733 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1734
37383650 1735 return 3;
6ee73861
BS		 1736}
1737
37383650 1738static int
6ee73861
BS		 1739init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1740{
1741 /*
1742 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1743 *
1744 * offset (8 bit): opcode
1745 * offset + 1 (8 bit): count
1746 * offset + 2 (8 bit): CRTC index 1
1747 * offset + 3 (8 bit): value 1
1748 * ...
1749 *
1750 * For "count", assign "value n" to CRTC register with index
1751 * "CRTC index n".
1752 */
1753
1754 uint8_t count = bios->data[offset + 1];
37383650 1755 int len = 2 + count * 2;
6ee73861
BS		 1756 int i;
1757
1758 if (!iexec->execute)
37383650 1759 return len;
6ee73861
BS		 1760
1761 for (i = 0; i < count; i++)
1762 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1763
37383650 1764 return len;
6ee73861
BS		 1765}
1766
37383650 1767static int
6ee73861
BS		 1768init_condition_time(struct nvbios *bios, uint16_t offset,
1769 struct init_exec *iexec)
1770{
1771 /*
1772 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1773 *
1774 * offset (8 bit): opcode
1775 * offset + 1 (8 bit): condition number
1776 * offset + 2 (8 bit): retries / 50
1777 *
1778 * Check condition "condition number" in the condition table.
1779 * Bios code then sleeps for 2ms if the condition is not met, and
1780 * repeats up to "retries" times, but on one C51 this has proved
1781 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1782 * this, and bail after "retries" times, or 2s, whichever is less.
1783 * If still not met after retries, clear execution flag for this table.
1784 */
1785
1786 uint8_t cond = bios->data[offset + 1];
1787 uint16_t retries = bios->data[offset + 2] * 50;
1788 unsigned cnt;
1789
1790 if (!iexec->execute)
37383650 1791 return 3;
6ee73861
BS		 1792
1793 if (retries > 100)
1794 retries = 100;
1795
1796 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1797 offset, cond, retries);
1798
1799 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1800 retries = 1;
1801
1802 for (cnt = 0; cnt < retries; cnt++) {
1803 if (bios_condition_met(bios, offset, cond)) {
1804 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1805 offset);
1806 break;
1807 } else {
1808 BIOSLOG(bios, "0x%04X: "
1809 "Condition not met, sleeping for 20ms\n",
1810 offset);
c7ca4d1b 1811 mdelay(20);
6ee73861
BS		 1812 }
1813 }
1814
1815 if (!bios_condition_met(bios, offset, cond)) {
1816 NV_WARN(bios->dev,
1817 "0x%04X: Condition still not met after %dms, "
1818 "skipping following opcodes\n", offset, 20 * retries);
1819 iexec->execute = false;
1820 }
1821
37383650 1822 return 3;
6ee73861
BS		 1823}
1824
e3a1924f
MK		 1825static int
1826init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1827{
1828 /*
1829 * INIT_LTIME opcode: 0x57 ('V')
1830 *
1831 * offset (8 bit): opcode
1832 * offset + 1 (16 bit): time
1833 *
e8a8b252 1834 * Sleep for "time" milliseconds.
e3a1924f
MK		 1835 */
1836
1837 unsigned time = ROM16(bios->data[offset + 1]);
1838
1839 if (!iexec->execute)
1840 return 3;
1841
e8a8b252 1842 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
e3a1924f
MK		 1843 offset, time);
1844
c7ca4d1b 1845 mdelay(time);
e3a1924f
MK		 1846
1847 return 3;
1848}
1849
37383650 1850static int
6ee73861
BS		 1851init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1852 struct init_exec *iexec)
1853{
1854 /*
1855 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1856 *
1857 * offset (8 bit): opcode
1858 * offset + 1 (32 bit): base register
1859 * offset + 5 (8 bit): count
1860 * offset + 6 (32 bit): value 1
1861 * ...
1862 *
1863 * Starting at offset + 6 there are "count" 32 bit values.
1864 * For "count" iterations set "base register" + 4 * current_iteration
1865 * to "value current_iteration"
1866 */
1867
1868 uint32_t basereg = ROM32(bios->data[offset + 1]);
1869 uint32_t count = bios->data[offset + 5];
37383650 1870 int len = 6 + count * 4;
6ee73861
BS		 1871 int i;
1872
1873 if (!iexec->execute)
37383650 1874 return len;
6ee73861
BS		 1875
1876 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1877 offset, basereg, count);
1878
1879 for (i = 0; i < count; i++) {
1880 uint32_t reg = basereg + i * 4;
1881 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1882
1883 bios_wr32(bios, reg, data);
1884 }
1885
37383650 1886 return len;
6ee73861
BS		 1887}
1888
37383650 1889static int
6ee73861
BS		 1890init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1891{
1892 /*
1893 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1894 *
1895 * offset (8 bit): opcode
1896 * offset + 1 (16 bit): subroutine offset (in bios)
1897 *
1898 * Calls a subroutine that will execute commands until INIT_DONE
1899 * is found.
1900 */
1901
1902 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1903
1904 if (!iexec->execute)
37383650 1905 return 3;
6ee73861
BS		 1906
1907 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
1908 offset, sub_offset);
1909
1910 parse_init_table(bios, sub_offset, iexec);
1911
1912 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
1913
37383650 1914 return 3;
6ee73861
BS		 1915}
1916
ec64a408
BS		 1917static int
1918init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1919{
1920 /*
1921 * INIT_JUMP opcode: 0x5C ('\')
1922 *
1923 * offset (8 bit): opcode
1924 * offset + 1 (16 bit): offset (in bios)
1925 *
1926 * Continue execution of init table from 'offset'
1927 */
1928
1929 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
1930
1931 if (!iexec->execute)
1932 return 3;
1933
1934 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
1935 return jmp_offset - offset;
1936}
1937
b715d640
MK		 1938static int
1939init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1940{
1941 /*
1942 * INIT_I2C_IF opcode: 0x5E ('^')
1943 *
1944 * offset (8 bit): opcode
1945 * offset + 1 (8 bit): DCB I2C table entry index
1946 * offset + 2 (8 bit): I2C slave address
1947 * offset + 3 (8 bit): I2C register
1948 * offset + 4 (8 bit): mask
1949 * offset + 5 (8 bit): data
1950 *
1951 * Read the register given by "I2C register" on the device addressed
1952 * by "I2C slave address" on the I2C bus given by "DCB I2C table
1953 * entry index". Compare the result AND "mask" to "data".
1954 * If they're not equal, skip subsequent opcodes until condition is
1955 * inverted (INIT_NOT), or we hit INIT_RESUME
1956 */
1957
1958 uint8_t i2c_index = bios->data[offset + 1];
1959 uint8_t i2c_address = bios->data[offset + 2] >> 1;
1960 uint8_t reg = bios->data[offset + 3];
1961 uint8_t mask = bios->data[offset + 4];
1962 uint8_t data = bios->data[offset + 5];
1963 struct nouveau_i2c_chan *chan;
1964 union i2c_smbus_data val;
1965 int ret;
1966
1967 /* no execute check by design */
1968
1969 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
1970 offset, i2c_index, i2c_address);
1971
1972 chan = init_i2c_device_find(bios->dev, i2c_index);
1973 if (!chan)
1974 return -ENODEV;
1975
1976 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1977 I2C_SMBUS_READ, reg,
1978 I2C_SMBUS_BYTE_DATA, &val);
1979 if (ret < 0) {
1980 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
1981 "Mask: 0x%02X, Data: 0x%02X\n",
1982 offset, reg, mask, data);
1983 iexec->execute = 0;
1984 return 6;
1985 }
1986
1987 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1988 "Mask: 0x%02X, Data: 0x%02X\n",
1989 offset, reg, val.byte, mask, data);
1990
1991 iexec->execute = ((val.byte & mask) == data);
1992
1993 return 6;
1994}
1995
37383650 1996static int
6ee73861
BS		 1997init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1998{
1999 /*
2000 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2001 *
2002 * offset (8 bit): opcode
2003 * offset + 1 (32 bit): src reg
2004 * offset + 5 (8 bit): shift
2005 * offset + 6 (32 bit): src mask
2006 * offset + 10 (32 bit): xor
2007 * offset + 14 (32 bit): dst reg
2008 * offset + 18 (32 bit): dst mask
2009 *
2010 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2011 * "src mask", then XOR with "xor". Write this OR'd with
2012 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2013 */
2014
2015 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2016 uint8_t shift = bios->data[offset + 5];
2017 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2018 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2019 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2020 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2021 uint32_t srcvalue, dstvalue;
2022
2023 if (!iexec->execute)
37383650 2024 return 22;
6ee73861
BS		 2025
2026 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2027 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2028 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2029
2030 srcvalue = bios_rd32(bios, srcreg);
2031
2032 if (shift < 0x80)
2033 srcvalue >>= shift;
2034 else
2035 srcvalue <<= (0x100 - shift);
2036
2037 srcvalue = (srcvalue & srcmask) ^ xor;
2038
2039 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2040
2041 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2042
37383650 2043 return 22;
6ee73861
BS		 2044}
2045
37383650 2046static int
6ee73861
BS		 2047init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2048{
2049 /*
2050 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2051 *
2052 * offset (8 bit): opcode
2053 * offset + 1 (16 bit): CRTC port
2054 * offset + 3 (8 bit): CRTC index
2055 * offset + 4 (8 bit): data
2056 *
2057 * Write "data" to index "CRTC index" of "CRTC port"
2058 */
2059 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2060 uint8_t crtcindex = bios->data[offset + 3];
2061 uint8_t data = bios->data[offset + 4];
2062
2063 if (!iexec->execute)
37383650 2064 return 5;
6ee73861
BS		 2065
2066 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2067
37383650 2068 return 5;
6ee73861
BS		 2069}
2070
67eda20e
FJ		 2071static inline void
2072bios_md32(struct nvbios *bios, uint32_t reg,
2073 uint32_t mask, uint32_t val)
2074{
2075 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2076}
2077
2078static uint32_t
2079peek_fb(struct drm_device *dev, struct io_mapping *fb,
2080 uint32_t off)
2081{
2082 uint32_t val = 0;
2083
2084 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2085 uint8_t __iomem *p =
3e4d3af5 2086 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2087
0bf9b0e0 2088 val = ioread32(p + (off & ~PAGE_MASK));
67eda20e 2089
3e4d3af5 2090 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2091 }
2092
2093 return val;
2094}
2095
2096static void
2097poke_fb(struct drm_device *dev, struct io_mapping *fb,
2098 uint32_t off, uint32_t val)
2099{
2100 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2101 uint8_t __iomem *p =
3e4d3af5 2102 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2103
0bf9b0e0 2104 iowrite32(val, p + (off & ~PAGE_MASK));
67eda20e
FJ		 2105 wmb();
2106
3e4d3af5 2107 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2108 }
2109}
2110
2111static inline bool
2112read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2113 uint32_t off, uint32_t val)
2114{
2115 poke_fb(dev, fb, off, val);
2116 return val == peek_fb(dev, fb, off);
2117}
2118
2119static int
2120nv04_init_compute_mem(struct nvbios *bios)
2121{
2122 struct drm_device *dev = bios->dev;
2123 uint32_t patt = 0xdeadbeef;
2124 struct io_mapping *fb;
2125 int i;
2126
2127 /* Map the framebuffer aperture */
2128 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2129 pci_resource_len(dev->pdev, 1));
2130 if (!fb)
2131 return -ENOMEM;
2132
2133 /* Sequencer and refresh off */
2134 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2135 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2136
2137 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2138 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2139 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2140 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2141
2142 for (i = 0; i < 4; i++)
2143 poke_fb(dev, fb, 4 * i, patt);
2144
2145 poke_fb(dev, fb, 0x400000, patt + 1);
2146
2147 if (peek_fb(dev, fb, 0) == patt + 1) {
2148 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2149 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2150 bios_md32(bios, NV04_PFB_DEBUG_0,
2151 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2152
2153 for (i = 0; i < 4; i++)
2154 poke_fb(dev, fb, 4 * i, patt);
2155
2156 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2157 bios_md32(bios, NV04_PFB_BOOT_0,
2158 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2159 NV04_PFB_BOOT_0_RAM_AMOUNT,
2160 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2161
2162 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2163 (patt & 0xffff0000)) {
2164 bios_md32(bios, NV04_PFB_BOOT_0,
2165 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2166 NV04_PFB_BOOT_0_RAM_AMOUNT,
2167 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2168
0746b5da 2169 } else if (peek_fb(dev, fb, 0) != patt) {
67eda20e
FJ		 2170 if (read_back_fb(dev, fb, 0x800000, patt))
2171 bios_md32(bios, NV04_PFB_BOOT_0,
2172 NV04_PFB_BOOT_0_RAM_AMOUNT,
2173 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2174 else
2175 bios_md32(bios, NV04_PFB_BOOT_0,
2176 NV04_PFB_BOOT_0_RAM_AMOUNT,
2177 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2178
2179 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2180 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2181
2182 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2183 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2184 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2185
2186 }
2187
2188 /* Refresh on, sequencer on */
2189 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2190 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2191
2192 io_mapping_free(fb);
2193 return 0;
2194}
2195
2196static const uint8_t *
2197nv05_memory_config(struct nvbios *bios)
2198{
2199 /* Defaults for BIOSes lacking a memory config table */
2200 static const uint8_t default_config_tab[][2] = {
2201 { 0x24, 0x00 },
2202 { 0x28, 0x00 },
2203 { 0x24, 0x01 },
2204 { 0x1f, 0x00 },
2205 { 0x0f, 0x00 },
2206 { 0x17, 0x00 },
2207 { 0x06, 0x00 },
2208 { 0x00, 0x00 }
2209 };
2210 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2211 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2212
2213 if (bios->legacy.mem_init_tbl_ptr)
2214 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2215 else
2216 return default_config_tab[i];
2217}
2218
2219static int
2220nv05_init_compute_mem(struct nvbios *bios)
2221{
2222 struct drm_device *dev = bios->dev;
2223 const uint8_t *ramcfg = nv05_memory_config(bios);
2224 uint32_t patt = 0xdeadbeef;
2225 struct io_mapping *fb;
2226 int i, v;
2227
2228 /* Map the framebuffer aperture */
2229 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2230 pci_resource_len(dev->pdev, 1));
2231 if (!fb)
2232 return -ENOMEM;
2233
2234 /* Sequencer off */
2235 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2236
2237 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2238 goto out;
2239
2240 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2241
2242 /* If present load the hardcoded scrambling table */
2243 if (bios->legacy.mem_init_tbl_ptr) {
2244 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2245 bios->legacy.mem_init_tbl_ptr + 0x10];
2246
2247 for (i = 0; i < 8; i++)
2248 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2249 ROM32(scramble_tab[i]));
2250 }
2251
2252 /* Set memory type/width/length defaults depending on the straps */
2253 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2254
2255 if (ramcfg[1] & 0x80)
2256 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2257
2258 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2259 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2260
2261 /* Probe memory bus width */
2262 for (i = 0; i < 4; i++)
2263 poke_fb(dev, fb, 4 * i, patt);
2264
2265 if (peek_fb(dev, fb, 0xc) != patt)
2266 bios_md32(bios, NV04_PFB_BOOT_0,
2267 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2268
2269 /* Probe memory length */
2270 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2271
2272 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2273 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2274 !read_back_fb(dev, fb, 0, ++patt)))
2275 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2276 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2277
2278 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2279 !read_back_fb(dev, fb, 0x800000, ++patt))
2280 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2281 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2282
2283 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2284 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2285 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2286
2287out:
2288 /* Sequencer on */
2289 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2290
2291 io_mapping_free(fb);
2292 return 0;
2293}
2294
2295static int
2296nv10_init_compute_mem(struct nvbios *bios)
2297{
2298 struct drm_device *dev = bios->dev;
2299 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2300 const int mem_width[] = { 0x10, 0x00, 0x20 };
2301 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2302 uint32_t patt = 0xdeadbeef;
2303 struct io_mapping *fb;
2304 int i, j, k;
2305
2306 /* Map the framebuffer aperture */
2307 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2308 pci_resource_len(dev->pdev, 1));
2309 if (!fb)
2310 return -ENOMEM;
2311
2312 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2313
2314 /* Probe memory bus width */
2315 for (i = 0; i < mem_width_count; i++) {
2316 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2317
2318 for (j = 0; j < 4; j++) {
2319 for (k = 0; k < 4; k++)
2320 poke_fb(dev, fb, 0x1c, 0);
2321
2322 poke_fb(dev, fb, 0x1c, patt);
2323 poke_fb(dev, fb, 0x3c, 0);
2324
2325 if (peek_fb(dev, fb, 0x1c) == patt)
2326 goto mem_width_found;
2327 }
2328 }
2329
2330mem_width_found:
2331 patt <<= 1;
2332
2333 /* Probe amount of installed memory */
2334 for (i = 0; i < 4; i++) {
2335 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2336
2337 poke_fb(dev, fb, off, patt);
2338 poke_fb(dev, fb, 0, 0);
2339
2340 peek_fb(dev, fb, 0);
2341 peek_fb(dev, fb, 0);
2342 peek_fb(dev, fb, 0);
2343 peek_fb(dev, fb, 0);
2344
2345 if (peek_fb(dev, fb, off) == patt)
2346 goto amount_found;
2347 }
2348
2349 /* IC missing - disable the upper half memory space. */
2350 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2351
2352amount_found:
2353 io_mapping_free(fb);
2354 return 0;
2355}
2356
2357static int
2358nv20_init_compute_mem(struct nvbios *bios)
2359{
2360 struct drm_device *dev = bios->dev;
2361 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2362 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2363 uint32_t amount, off;
2364 struct io_mapping *fb;
2365
2366 /* Map the framebuffer aperture */
2367 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2368 pci_resource_len(dev->pdev, 1));
2369 if (!fb)
2370 return -ENOMEM;
2371
2372 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2373
2374 /* Allow full addressing */
2375 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2376
2377 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2378 for (off = amount; off > 0x2000000; off -= 0x2000000)
2379 poke_fb(dev, fb, off - 4, off);
2380
2381 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2382 if (amount != peek_fb(dev, fb, amount - 4))
2383 /* IC missing - disable the upper half memory space. */
2384 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2385
2386 io_mapping_free(fb);
2387 return 0;
2388}
2389
37383650 2390static int
6ee73861
BS		 2391init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2392{
2393 /*
2394 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2395 *
2396 * offset (8 bit): opcode
2397 *
67eda20e
FJ		 2398 * This opcode is meant to set the PFB memory config registers
2399 * appropriately so that we can correctly calculate how much VRAM it
2400 * has (on nv10 and better chipsets the amount of installed VRAM is
2401 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
6ee73861 2402 *
67eda20e
FJ		 2403 * The implementation of this opcode in general consists of several
2404 * parts:
6ee73861 2405 *
67eda20e
FJ		 2406 * 1) Determination of memory type and density. Only necessary for
2407 * really old chipsets, the memory type reported by the strap bits
2408 * (0x101000) is assumed to be accurate on nv05 and newer.
6ee73861 2409 *
67eda20e
FJ		 2410 * 2) Determination of the memory bus width. Usually done by a cunning
2411 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2412 * seeing whether the written values are read back correctly.
6ee73861 2413 *
67eda20e
FJ		 2414 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2415 * trust the straps.
6ee73861 2416 *
67eda20e
FJ		 2417 * 3) Determination of how many of the card's RAM pads have ICs
2418 * attached, usually done by a cunning combination of writes to an
2419 * offset slightly less than the maximum memory reported by
2420 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
6ee73861 2421 *
67eda20e
FJ		 2422 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2423 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2424 * card show nothing being done for this opcode. Why is it still listed
2425 * in the table?!
6ee73861
BS		 2426 */
2427
2428 /* no iexec->execute check by design */
2429
6ee73861 2430 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
67eda20e 2431 int ret;
6ee73861 2432
67eda20e
FJ		 2433 if (dev_priv->chipset >= 0x40 ||
2434 dev_priv->chipset == 0x1a ||
2435 dev_priv->chipset == 0x1f)
2436 ret = 0;
2437 else if (dev_priv->chipset >= 0x20 &&
2438 dev_priv->chipset != 0x34)
2439 ret = nv20_init_compute_mem(bios);
2440 else if (dev_priv->chipset >= 0x10)
2441 ret = nv10_init_compute_mem(bios);
2442 else if (dev_priv->chipset >= 0x5)
2443 ret = nv05_init_compute_mem(bios);
2444 else
2445 ret = nv04_init_compute_mem(bios);
6ee73861 2446
67eda20e
FJ		 2447 if (ret)
2448 return ret;
6ee73861 2449
37383650 2450 return 1;
6ee73861
BS		 2451}
2452
37383650 2453static int
6ee73861
BS		 2454init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2455{
2456 /*
2457 * INIT_RESET opcode: 0x65 ('e')
2458 *
2459 * offset (8 bit): opcode
2460 * offset + 1 (32 bit): register
2461 * offset + 5 (32 bit): value1
2462 * offset + 9 (32 bit): value2
2463 *
2464 * Assign "value1" to "register", then assign "value2" to "register"
2465 */
2466
2467 uint32_t reg = ROM32(bios->data[offset + 1]);
2468 uint32_t value1 = ROM32(bios->data[offset + 5]);
2469 uint32_t value2 = ROM32(bios->data[offset + 9]);
2470 uint32_t pci_nv_19, pci_nv_20;
2471
2472 /* no iexec->execute check by design */
2473
2474 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
190a4378
FJ		 2475 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2476
6ee73861
BS		 2477 bios_wr32(bios, reg, value1);
2478
2479 udelay(10);
2480
2481 bios_wr32(bios, reg, value2);
2482 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2483
2484 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2485 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2486 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2487
37383650 2488 return 13;
6ee73861
BS		 2489}
2490
37383650 2491static int
6ee73861
BS		 2492init_configure_mem(struct nvbios *bios, uint16_t offset,
2493 struct init_exec *iexec)
2494{
2495 /*
2496 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2497 *
2498 * offset (8 bit): opcode
2499 *
2500 * Equivalent to INIT_DONE on bios version 3 or greater.
2501 * For early bios versions, sets up the memory registers, using values
2502 * taken from the memory init table
2503 */
2504
2505 /* no iexec->execute check by design */
2506
2507 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2508 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2509 uint32_t reg, data;
2510
2511 if (bios->major_version > 2)
ae55321c 2512 return 0;
6ee73861
BS		 2513
2514 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2515 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2516
2517 if (bios->data[meminitoffs] & 1)
2518 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2519
2520 for (reg = ROM32(bios->data[seqtbloffs]);
2521 reg != 0xffffffff;
2522 reg = ROM32(bios->data[seqtbloffs += 4])) {
2523
2524 switch (reg) {
3c7066bc
FJ		 2525 case NV04_PFB_PRE:
2526 data = NV04_PFB_PRE_CMD_PRECHARGE;
6ee73861 2527 break;
3c7066bc
FJ		 2528 case NV04_PFB_PAD:
2529 data = NV04_PFB_PAD_CKE_NORMAL;
6ee73861 2530 break;
3c7066bc
FJ		 2531 case NV04_PFB_REF:
2532 data = NV04_PFB_REF_CMD_REFRESH;
6ee73861
BS		 2533 break;
2534 default:
2535 data = ROM32(bios->data[meminitdata]);
2536 meminitdata += 4;
2537 if (data == 0xffffffff)
2538 continue;
2539 }
2540
2541 bios_wr32(bios, reg, data);
2542 }
2543
37383650 2544 return 1;
6ee73861
BS		 2545}
2546
37383650 2547static int
6ee73861
BS		 2548init_configure_clk(struct nvbios *bios, uint16_t offset,
2549 struct init_exec *iexec)
2550{
2551 /*
2552 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2553 *
2554 * offset (8 bit): opcode
2555 *
2556 * Equivalent to INIT_DONE on bios version 3 or greater.
2557 * For early bios versions, sets up the NVClk and MClk PLLs, using
2558 * values taken from the memory init table
2559 */
2560
2561 /* no iexec->execute check by design */
2562
2563 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2564 int clock;
2565
2566 if (bios->major_version > 2)
ae55321c 2567 return 0;
6ee73861
BS		 2568
2569 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2570 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2571
2572 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2573 if (bios->data[meminitoffs] & 1) /* DDR */
2574 clock *= 2;
2575 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2576
37383650 2577 return 1;
6ee73861
BS		 2578}
2579
37383650 2580static int
6ee73861
BS		 2581init_configure_preinit(struct nvbios *bios, uint16_t offset,
2582 struct init_exec *iexec)
2583{
2584 /*
2585 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2586 *
2587 * offset (8 bit): opcode
2588 *
2589 * Equivalent to INIT_DONE on bios version 3 or greater.
2590 * For early bios versions, does early init, loading ram and crystal
2591 * configuration from straps into CR3C
2592 */
2593
2594 /* no iexec->execute check by design */
2595
2596 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
3c9b2534 2597 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
6ee73861
BS		 2598
2599 if (bios->major_version > 2)
ae55321c 2600 return 0;
6ee73861
BS		 2601
2602 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2603 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2604
37383650 2605 return 1;
6ee73861
BS		 2606}
2607
37383650 2608static int
6ee73861
BS		 2609init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2610{
2611 /*
2612 * INIT_IO opcode: 0x69 ('i')
2613 *
2614 * offset (8 bit): opcode
2615 * offset + 1 (16 bit): CRTC port
2616 * offset + 3 (8 bit): mask
2617 * offset + 4 (8 bit): data
2618 *
2619 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2620 */
2621
2622 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2623 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2624 uint8_t mask = bios->data[offset + 3];
2625 uint8_t data = bios->data[offset + 4];
2626
2627 if (!iexec->execute)
37383650 2628 return 5;
6ee73861
BS		 2629
2630 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2631 offset, crtcport, mask, data);
2632
2633 /*
2634 * I have no idea what this does, but NVIDIA do this magic sequence
2635 * in the places where this INIT_IO happens..
2636 */
2637 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2638 int i;
2639
2640 bios_wr32(bios, 0x614100, (bios_rd32(
2641 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2642
2643 bios_wr32(bios, 0x00e18c, bios_rd32(
2644 bios, 0x00e18c) | 0x00020000);
2645
2646 bios_wr32(bios, 0x614900, (bios_rd32(
2647 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2648
2649 bios_wr32(bios, 0x000200, bios_rd32(
2650 bios, 0x000200) & ~0x40000000);
2651
2652 mdelay(10);
2653
2654 bios_wr32(bios, 0x00e18c, bios_rd32(
2655 bios, 0x00e18c) & ~0x00020000);
2656
2657 bios_wr32(bios, 0x000200, bios_rd32(
2658 bios, 0x000200) | 0x40000000);
2659
2660 bios_wr32(bios, 0x614100, 0x00800018);
2661 bios_wr32(bios, 0x614900, 0x00800018);
2662
2663 mdelay(10);
2664
2665 bios_wr32(bios, 0x614100, 0x10000018);
2666 bios_wr32(bios, 0x614900, 0x10000018);
2667
2668 for (i = 0; i < 3; i++)
2669 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2670 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2671
2672 for (i = 0; i < 2; i++)
2673 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2674 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2675
2676 for (i = 0; i < 3; i++)
2677 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2678 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2679
2680 for (i = 0; i < 2; i++)
2681 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2682 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2683
2684 for (i = 0; i < 2; i++)
2685 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2686 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2687 return 5;
6ee73861
BS		 2688 }
2689
2690 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2691 data);
37383650 2692 return 5;
6ee73861
BS		 2693}
2694
37383650 2695static int
6ee73861
BS		 2696init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2697{
2698 /*
2699 * INIT_SUB opcode: 0x6B ('k')
2700 *
2701 * offset (8 bit): opcode
2702 * offset + 1 (8 bit): script number
2703 *
2704 * Execute script number "script number", as a subroutine
2705 */
2706
2707 uint8_t sub = bios->data[offset + 1];
2708
2709 if (!iexec->execute)
37383650 2710 return 2;
6ee73861
BS		 2711
2712 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2713
2714 parse_init_table(bios,
2715 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2716 iexec);
2717
2718 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2719
37383650 2720 return 2;
6ee73861
BS		 2721}
2722
37383650 2723static int
6ee73861
BS		 2724init_ram_condition(struct nvbios *bios, uint16_t offset,
2725 struct init_exec *iexec)
2726{
2727 /*
2728 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2729 *
2730 * offset (8 bit): opcode
2731 * offset + 1 (8 bit): mask
2732 * offset + 2 (8 bit): cmpval
2733 *
3c7066bc 2734 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
6ee73861
BS		 2735 * If condition not met skip subsequent opcodes until condition is
2736 * inverted (INIT_NOT), or we hit INIT_RESUME
2737 */
2738
2739 uint8_t mask = bios->data[offset + 1];
2740 uint8_t cmpval = bios->data[offset + 2];
2741 uint8_t data;
2742
2743 if (!iexec->execute)
37383650 2744 return 3;
6ee73861 2745
3c7066bc 2746 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
6ee73861
BS		 2747
2748 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2749 offset, data, cmpval);
2750
2751 if (data == cmpval)
2752 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2753 else {
2754 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2755 iexec->execute = false;
2756 }
2757
37383650 2758 return 3;
6ee73861
BS		 2759}
2760
37383650 2761static int
6ee73861
BS		 2762init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2763{
2764 /*
2765 * INIT_NV_REG opcode: 0x6E ('n')
2766 *
2767 * offset (8 bit): opcode
2768 * offset + 1 (32 bit): register
2769 * offset + 5 (32 bit): mask
2770 * offset + 9 (32 bit): data
2771 *
2772 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2773 */
2774
2775 uint32_t reg = ROM32(bios->data[offset + 1]);
2776 uint32_t mask = ROM32(bios->data[offset + 5]);
2777 uint32_t data = ROM32(bios->data[offset + 9]);
2778
2779 if (!iexec->execute)
37383650 2780 return 13;
6ee73861
BS		 2781
2782 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2783 offset, reg, mask, data);
2784
2785 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2786
37383650 2787 return 13;
6ee73861
BS		 2788}
2789
37383650 2790static int
6ee73861
BS		 2791init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2792{
2793 /*
2794 * INIT_MACRO opcode: 0x6F ('o')
2795 *
2796 * offset (8 bit): opcode
2797 * offset + 1 (8 bit): macro number
2798 *
2799 * Look up macro index "macro number" in the macro index table.
2800 * The macro index table entry has 1 byte for the index in the macro
2801 * table, and 1 byte for the number of times to repeat the macro.
2802 * The macro table entry has 4 bytes for the register address and
2803 * 4 bytes for the value to write to that register
2804 */
2805
2806 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2807 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2808 uint8_t macro_tbl_idx = bios->data[tmp];
2809 uint8_t count = bios->data[tmp + 1];
2810 uint32_t reg, data;
2811 int i;
2812
2813 if (!iexec->execute)
37383650 2814 return 2;
6ee73861
BS		 2815
2816 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2817 "Count: 0x%02X\n",
2818 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2819
2820 for (i = 0; i < count; i++) {
2821 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2822
2823 reg = ROM32(bios->data[macroentryptr]);
2824 data = ROM32(bios->data[macroentryptr + 4]);
2825
2826 bios_wr32(bios, reg, data);
2827 }
2828
37383650 2829 return 2;
6ee73861
BS		 2830}
2831
37383650 2832static int
6ee73861
BS		 2833init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2834{
2835 /*
2836 * INIT_DONE opcode: 0x71 ('q')
2837 *
2838 * offset (8 bit): opcode
2839 *
2840 * End the current script
2841 */
2842
2843 /* mild retval abuse to stop parsing this table */
37383650 2844 return 0;
6ee73861
BS		 2845}
2846
37383650 2847static int
6ee73861
BS		 2848init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2849{
2850 /*
2851 * INIT_RESUME opcode: 0x72 ('r')
2852 *
2853 * offset (8 bit): opcode
2854 *
2855 * End the current execute / no-execute condition
2856 */
2857
2858 if (iexec->execute)
37383650 2859 return 1;
6ee73861
BS		 2860
2861 iexec->execute = true;
2862 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2863
37383650 2864 return 1;
6ee73861
BS		 2865}
2866
37383650 2867static int
6ee73861
BS		 2868init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2869{
2870 /*
2871 * INIT_TIME opcode: 0x74 ('t')
2872 *
2873 * offset (8 bit): opcode
2874 * offset + 1 (16 bit): time
2875 *
2876 * Sleep for "time" microseconds.
2877 */
2878
2879 unsigned time = ROM16(bios->data[offset + 1]);
2880
2881 if (!iexec->execute)
37383650 2882 return 3;
6ee73861
BS		 2883
2884 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2885 offset, time);
2886
2887 if (time < 1000)
2888 udelay(time);
2889 else
c7ca4d1b 2890 mdelay((time + 900) / 1000);
6ee73861 2891
37383650 2892 return 3;
6ee73861
BS		 2893}
2894
37383650 2895static int
6ee73861
BS		 2896init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2897{
2898 /*
2899 * INIT_CONDITION opcode: 0x75 ('u')
2900 *
2901 * offset (8 bit): opcode
2902 * offset + 1 (8 bit): condition number
2903 *
2904 * Check condition "condition number" in the condition table.
2905 * If condition not met skip subsequent opcodes until condition is
2906 * inverted (INIT_NOT), or we hit INIT_RESUME
2907 */
2908
2909 uint8_t cond = bios->data[offset + 1];
2910
2911 if (!iexec->execute)
37383650 2912 return 2;
6ee73861
BS		 2913
2914 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
2915
2916 if (bios_condition_met(bios, offset, cond))
2917 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2918 else {
2919 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2920 iexec->execute = false;
2921 }
2922
37383650 2923 return 2;
6ee73861
BS		 2924}
2925
37383650 2926static int
6ee73861
BS		 2927init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2928{
2929 /*
2930 * INIT_IO_CONDITION opcode: 0x76
2931 *
2932 * offset (8 bit): opcode
2933 * offset + 1 (8 bit): condition number
2934 *
2935 * Check condition "condition number" in the io condition table.
2936 * If condition not met skip subsequent opcodes until condition is
2937 * inverted (INIT_NOT), or we hit INIT_RESUME
2938 */
2939
2940 uint8_t cond = bios->data[offset + 1];
2941
2942 if (!iexec->execute)
37383650 2943 return 2;
6ee73861
BS		 2944
2945 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
2946
2947 if (io_condition_met(bios, offset, cond))
2948 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2949 else {
2950 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2951 iexec->execute = false;
2952 }
2953
37383650 2954 return 2;
6ee73861
BS		 2955}
2956
37383650 2957static int
6ee73861
BS		 2958init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2959{
2960 /*
2961 * INIT_INDEX_IO opcode: 0x78 ('x')
2962 *
2963 * offset (8 bit): opcode
2964 * offset + 1 (16 bit): CRTC port
2965 * offset + 3 (8 bit): CRTC index
2966 * offset + 4 (8 bit): mask
2967 * offset + 5 (8 bit): data
2968 *
2969 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
2970 * OR with "data", write-back
2971 */
2972
2973 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2974 uint8_t crtcindex = bios->data[offset + 3];
2975 uint8_t mask = bios->data[offset + 4];
2976 uint8_t data = bios->data[offset + 5];
2977 uint8_t value;
2978
2979 if (!iexec->execute)
37383650 2980 return 6;
6ee73861
BS		 2981
2982 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
2983 "Data: 0x%02X\n",
2984 offset, crtcport, crtcindex, mask, data);
2985
2986 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
2987 bios_idxprt_wr(bios, crtcport, crtcindex, value);
2988
37383650 2989 return 6;
6ee73861
BS		 2990}
2991
37383650 2992static int
6ee73861
BS		 2993init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2994{
2995 /*
2996 * INIT_PLL opcode: 0x79 ('y')
2997 *
2998 * offset (8 bit): opcode
2999 * offset + 1 (32 bit): register
3000 * offset + 5 (16 bit): freq
3001 *
3002 * Set PLL register "register" to coefficients for frequency (10kHz)
3003 * "freq"
3004 */
3005
3006 uint32_t reg = ROM32(bios->data[offset + 1]);
3007 uint16_t freq = ROM16(bios->data[offset + 5]);
3008
3009 if (!iexec->execute)
37383650 3010 return 7;
6ee73861
BS		 3011
3012 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3013
3014 setPLL(bios, reg, freq * 10);
3015
37383650 3016 return 7;
6ee73861
BS		 3017}
3018
37383650 3019static int
6ee73861
BS		 3020init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3021{
3022 /*
3023 * INIT_ZM_REG opcode: 0x7A ('z')
3024 *
3025 * offset (8 bit): opcode
3026 * offset + 1 (32 bit): register
3027 * offset + 5 (32 bit): value
3028 *
3029 * Assign "value" to "register"
3030 */
3031
3032 uint32_t reg = ROM32(bios->data[offset + 1]);
3033 uint32_t value = ROM32(bios->data[offset + 5]);
3034
3035 if (!iexec->execute)
37383650 3036 return 9;
6ee73861
BS		 3037
3038 if (reg == 0x000200)
3039 value |= 1;
3040
3041 bios_wr32(bios, reg, value);
3042
37383650 3043 return 9;
6ee73861
BS		 3044}
3045
37383650 3046static int
6ee73861
BS		 3047init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3048 struct init_exec *iexec)
3049{
3050 /*
3051 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3052 *
3053 * offset (8 bit): opcode
3054 * offset + 1 (8 bit): PLL type
3055 * offset + 2 (32 bit): frequency 0
3056 *
3057 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3058 * ram_restrict_table_ptr. The value read from there is used to select
3059 * a frequency from the table starting at 'frequency 0' to be
3060 * programmed into the PLL corresponding to 'type'.
3061 *
3062 * The PLL limits table on cards using this opcode has a mapping of
3063 * 'type' to the relevant registers.
3064 */
3065
3066 struct drm_device *dev = bios->dev;
3067 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3068 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3069 uint8_t type = bios->data[offset + 1];
3070 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3071 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 3072 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 3073 int i;
3074
3075 if (!iexec->execute)
37383650 3076 return len;
6ee73861
BS		 3077
3078 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3079 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 3080 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 3081 }
3082
3083 entry = pll_limits + pll_limits[1];
3084 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3085 if (entry[0] == type) {
3086 uint32_t reg = ROM32(entry[3]);
3087
3088 BIOSLOG(bios, "0x%04X: "
3089 "Type %02x Reg 0x%08x Freq %dKHz\n",
3090 offset, type, reg, freq);
3091
3092 setPLL(bios, reg, freq);
37383650 3093 return len;
6ee73861
BS		 3094 }
3095 }
3096
3097 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 3098 return len;
6ee73861
BS		 3099}
3100
37383650 3101static int
6ee73861
BS		 3102init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3103{
3104 /*
3105 * INIT_8C opcode: 0x8C ('')
3106 *
3107 * NOP so far....
3108 *
3109 */
3110
37383650 3111 return 1;
6ee73861
BS		 3112}
3113
37383650 3114static int
6ee73861
BS		 3115init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3116{
3117 /*
3118 * INIT_8D opcode: 0x8D ('')
3119 *
3120 * NOP so far....
3121 *
3122 */
3123
37383650 3124 return 1;
6ee73861
BS		 3125}
3126
75139063
BS		 3127static void
3128init_gpio_unknv50(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3129{
3130 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
3131 u32 r, s, v;
3132
3133 /* Not a clue, needs de-magicing */
3134 r = nv50_gpio_ctl[gpio->line >> 4];
3135 s = (gpio->line & 0x0f);
3136 v = bios_rd32(bios, r) & ~(0x00010001 << s);
3137 switch ((gpio->entry & 0x06000000) >> 25) {
3138 case 1:
3139 v |= (0x00000001 << s);
3140 break;
3141 case 2:
3142 v |= (0x00010000 << s);
3143 break;
3144 default:
3145 break;
3146 }
3147
3148 bios_wr32(bios, r, v);
3149}
3150
3151static void
3152init_gpio_unknvd0(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3153{
3154 u32 v, i;
3155
3156 v = bios_rd32(bios, 0x00d610 + (gpio->line * 4));
3157 v &= 0xffffff00;
3158 v |= (gpio->entry & 0x00ff0000) >> 16;
3159 bios_wr32(bios, 0x00d610 + (gpio->line * 4), v);
3160
3161 i = (gpio->entry & 0x1f000000) >> 24;
3162 if (i) {
3163 v = bios_rd32(bios, 0x00d640 + ((i - 1) * 4));
3164 v &= 0xffffff00;
3165 v |= gpio->line;
3166 bios_wr32(bios, 0x00d640 + ((i - 1) * 4), v);
3167 }
3168}
3169
37383650 3170static int
6ee73861
BS		 3171init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3172{
3173 /*
3174 * INIT_GPIO opcode: 0x8E ('')
3175 *
3176 * offset (8 bit): opcode
3177 *
3178 * Loop over all entries in the DCB GPIO table, and initialise
3179 * each GPIO according to various values listed in each entry
3180 */
3181
2535d71c 3182 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
ee2e0131 3183 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861
BS		 3184 int i;
3185
080feda5 3186 if (dev_priv->card_type < NV_50) {
2535d71c 3187 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
309b8c89 3188 return 1;
6ee73861
BS		 3189 }
3190
2535d71c
BS		 3191 if (!iexec->execute)
3192 return 1;
6ee73861 3193
2535d71c
BS		 3194 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3195 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
6ee73861 3196
2535d71c 3197 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 3198
73db4bed
BS		 3199 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3200 offset, gpio->tag, gpio->state_default);
6ee73861 3201
75139063
BS		 3202 if (!bios->execute)
3203 continue;
3204
3205 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
3206 if (dev_priv->card_type < NV_D0)
3207 init_gpio_unknv50(bios, gpio);
3208 else
3209 init_gpio_unknvd0(bios, gpio);
6ee73861
BS		 3210 }
3211
37383650 3212 return 1;
6ee73861
BS		 3213}
3214
37383650 3215static int
6ee73861
BS		 3216init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3217 struct init_exec *iexec)
3218{
3219 /*
3220 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3221 *
3222 * offset (8 bit): opcode
3223 * offset + 1 (32 bit): reg
3224 * offset + 5 (8 bit): regincrement
3225 * offset + 6 (8 bit): count
3226 * offset + 7 (32 bit): value 1,1
3227 * ...
3228 *
3229 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3230 * ram_restrict_table_ptr. The value read from here is 'n', and
3231 * "value 1,n" gets written to "reg". This repeats "count" times and on
3232 * each iteration 'm', "reg" increases by "regincrement" and
3233 * "value m,n" is used. The extent of n is limited by a number read
3234 * from the 'M' BIT table, herein called "blocklen"
3235 */
3236
3237 uint32_t reg = ROM32(bios->data[offset + 1]);
3238 uint8_t regincrement = bios->data[offset + 5];
3239 uint8_t count = bios->data[offset + 6];
3240 uint32_t strap_ramcfg, data;
37383650
MK		 3241 /* previously set by 'M' BIT table */
3242 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3243 int len = 7 + count * blocklen;
6ee73861
BS		 3244 uint8_t index;
3245 int i;
3246
309b8c89 3247 /* critical! to know the length of the opcode */;
6ee73861
BS		 3248 if (!blocklen) {
3249 NV_ERROR(bios->dev,
3250 "0x%04X: Zero block length - has the M table "
3251 "been parsed?\n", offset);
9170a824 3252 return -EINVAL;
6ee73861
BS		 3253 }
3254
309b8c89
BS		 3255 if (!iexec->execute)
3256 return len;
3257
6ee73861
BS		 3258 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3259 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3260
3261 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3262 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3263 offset, reg, regincrement, count, strap_ramcfg, index);
3264
3265 for (i = 0; i < count; i++) {
3266 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3267
3268 bios_wr32(bios, reg, data);
3269
3270 reg += regincrement;
3271 }
3272
37383650 3273 return len;
6ee73861
BS		 3274}
3275
37383650 3276static int
6ee73861
BS		 3277init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3278{
3279 /*
3280 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3281 *
3282 * offset (8 bit): opcode
3283 * offset + 1 (32 bit): src reg
3284 * offset + 5 (32 bit): dst reg
3285 *
3286 * Put contents of "src reg" into "dst reg"
3287 */
3288
3289 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3290 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3291
3292 if (!iexec->execute)
37383650 3293 return 9;
6ee73861
BS		 3294
3295 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3296
37383650 3297 return 9;
6ee73861
BS		 3298}
3299
37383650 3300static int
6ee73861
BS		 3301init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3302 struct init_exec *iexec)
3303{
3304 /*
3305 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3306 *
3307 * offset (8 bit): opcode
3308 * offset + 1 (32 bit): dst reg
3309 * offset + 5 (8 bit): count
3310 * offset + 6 (32 bit): data 1
3311 * ...
3312 *
3313 * For each of "count" values write "data n" to "dst reg"
3314 */
3315
3316 uint32_t reg = ROM32(bios->data[offset + 1]);
3317 uint8_t count = bios->data[offset + 5];
37383650 3318 int len = 6 + count * 4;
6ee73861
BS		 3319 int i;
3320
3321 if (!iexec->execute)
37383650 3322 return len;
6ee73861
BS		 3323
3324 for (i = 0; i < count; i++) {
3325 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3326 bios_wr32(bios, reg, data);
3327 }
3328
37383650 3329 return len;
6ee73861
BS		 3330}
3331
37383650 3332static int
6ee73861
BS		 3333init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3334{
3335 /*
3336 * INIT_RESERVED opcode: 0x92 ('')
3337 *
3338 * offset (8 bit): opcode
3339 *
3340 * Seemingly does nothing
3341 */
3342
37383650 3343 return 1;
6ee73861
BS		 3344}
3345
37383650 3346static int
6ee73861
BS		 3347init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3348{
3349 /*
3350 * INIT_96 opcode: 0x96 ('')
3351 *
3352 * offset (8 bit): opcode
3353 * offset + 1 (32 bit): sreg
3354 * offset + 5 (8 bit): sshift
3355 * offset + 6 (8 bit): smask
3356 * offset + 7 (8 bit): index
3357 * offset + 8 (32 bit): reg
3358 * offset + 12 (32 bit): mask
3359 * offset + 16 (8 bit): shift
3360 *
3361 */
3362
3363 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3364 uint32_t reg = ROM32(bios->data[offset + 8]);
3365 uint32_t mask = ROM32(bios->data[offset + 12]);
3366 uint32_t val;
3367
3368 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3369 if (bios->data[offset + 5] < 0x80)
3370 val >>= bios->data[offset + 5];
3371 else
3372 val <<= (0x100 - bios->data[offset + 5]);
3373 val &= bios->data[offset + 6];
3374
3375 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3376 val <<= bios->data[offset + 16];
3377
3378 if (!iexec->execute)
37383650 3379 return 17;
6ee73861
BS		 3380
3381 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3382 return 17;
6ee73861
BS		 3383}
3384
37383650 3385static int
6ee73861
BS		 3386init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3387{
3388 /*
3389 * INIT_97 opcode: 0x97 ('')
3390 *
3391 * offset (8 bit): opcode
3392 * offset + 1 (32 bit): register
3393 * offset + 5 (32 bit): mask
3394 * offset + 9 (32 bit): value
3395 *
3396 * Adds "value" to "register" preserving the fields specified
3397 * by "mask"
3398 */
3399
3400 uint32_t reg = ROM32(bios->data[offset + 1]);
3401 uint32_t mask = ROM32(bios->data[offset + 5]);
3402 uint32_t add = ROM32(bios->data[offset + 9]);
3403 uint32_t val;
3404
3405 val = bios_rd32(bios, reg);
3406 val = (val & mask) | ((val + add) & ~mask);
3407
3408 if (!iexec->execute)
37383650 3409 return 13;
6ee73861
BS		 3410
3411 bios_wr32(bios, reg, val);
37383650 3412 return 13;
6ee73861
BS		 3413}
3414
37383650 3415static int
6ee73861
BS		 3416init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3417{
3418 /*
3419 * INIT_AUXCH opcode: 0x98 ('')
3420 *
3421 * offset (8 bit): opcode
3422 * offset + 1 (32 bit): address
3423 * offset + 5 (8 bit): count
3424 * offset + 6 (8 bit): mask 0
3425 * offset + 7 (8 bit): data 0
3426 * ...
3427 *
3428 */
3429
3430 struct drm_device *dev = bios->dev;
3431 struct nouveau_i2c_chan *auxch;
3432 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3433 uint8_t count = bios->data[offset + 5];
3434 int len = 6 + count * 2;
6ee73861
BS		 3435 int ret, i;
3436
3437 if (!bios->display.output) {
3438 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
309b8c89 3439 return len;
6ee73861
BS		 3440 }
3441
3442 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3443 if (!auxch) {
3444 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3445 bios->display.output->i2c_index);
309b8c89 3446 return len;
6ee73861
BS		 3447 }
3448
3449 if (!iexec->execute)
37383650 3450 return len;
6ee73861
BS		 3451
3452 offset += 6;
37383650 3453 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3454 uint8_t data;
3455
3456 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3457 if (ret) {
3458 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
309b8c89 3459 return len;
6ee73861
BS		 3460 }
3461
3462 data &= bios->data[offset + 0];
3463 data |= bios->data[offset + 1];
3464
3465 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3466 if (ret) {
3467 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3468 return len;
6ee73861
BS		 3469 }
3470 }
3471
37383650 3472 return len;
6ee73861
BS		 3473}
3474
37383650 3475static int
6ee73861
BS		 3476init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3477{
3478 /*
3479 * INIT_ZM_AUXCH opcode: 0x99 ('')
3480 *
3481 * offset (8 bit): opcode
3482 * offset + 1 (32 bit): address
3483 * offset + 5 (8 bit): count
3484 * offset + 6 (8 bit): data 0
3485 * ...
3486 *
3487 */
3488
3489 struct drm_device *dev = bios->dev;
3490 struct nouveau_i2c_chan *auxch;
3491 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3492 uint8_t count = bios->data[offset + 5];
3493 int len = 6 + count;
6ee73861
BS		 3494 int ret, i;
3495
3496 if (!bios->display.output) {
3497 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
309b8c89 3498 return len;
6ee73861
BS		 3499 }
3500
3501 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3502 if (!auxch) {
3503 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3504 bios->display.output->i2c_index);
309b8c89 3505 return len;
6ee73861
BS		 3506 }
3507
3508 if (!iexec->execute)
37383650 3509 return len;
6ee73861
BS		 3510
3511 offset += 6;
37383650 3512 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3513 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3514 if (ret) {
3515 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3516 return len;
6ee73861
BS		 3517 }
3518 }
3519
37383650 3520 return len;
6ee73861
BS		 3521}
3522
b715d640
MK		 3523static int
3524init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3525{
3526 /*
3527 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3528 *
3529 * offset (8 bit): opcode
3530 * offset + 1 (8 bit): DCB I2C table entry index
3531 * offset + 2 (8 bit): I2C slave address
3532 * offset + 3 (16 bit): I2C register
3533 * offset + 5 (8 bit): mask
3534 * offset + 6 (8 bit): data
3535 *
3536 * Read the register given by "I2C register" on the device addressed
3537 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3538 * entry index". Compare the result AND "mask" to "data".
3539 * If they're not equal, skip subsequent opcodes until condition is
3540 * inverted (INIT_NOT), or we hit INIT_RESUME
3541 */
3542
3543 uint8_t i2c_index = bios->data[offset + 1];
3544 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3545 uint8_t reglo = bios->data[offset + 3];
3546 uint8_t reghi = bios->data[offset + 4];
3547 uint8_t mask = bios->data[offset + 5];
3548 uint8_t data = bios->data[offset + 6];
3549 struct nouveau_i2c_chan *chan;
3550 uint8_t buf0[2] = { reghi, reglo };
3551 uint8_t buf1[1];
3552 struct i2c_msg msg[2] = {
3553 { i2c_address, 0, 1, buf0 },
3554 { i2c_address, I2C_M_RD, 1, buf1 },
3555 };
3556 int ret;
3557
3558 /* no execute check by design */
3559
3560 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3561 offset, i2c_index, i2c_address);
3562
3563 chan = init_i2c_device_find(bios->dev, i2c_index);
3564 if (!chan)
3565 return -ENODEV;
3566
3567
3568 ret = i2c_transfer(&chan->adapter, msg, 2);
3569 if (ret < 0) {
3570 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3571 "Mask: 0x%02X, Data: 0x%02X\n",
3572 offset, reghi, reglo, mask, data);
3573 iexec->execute = 0;
3574 return 7;
3575 }
3576
3577 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3578 "Mask: 0x%02X, Data: 0x%02X\n",
3579 offset, reghi, reglo, buf1[0], mask, data);
3580
3581 iexec->execute = ((buf1[0] & mask) == data);
3582
3583 return 7;
3584}
3585
6ee73861
BS		 3586static struct init_tbl_entry itbl_entry[] = {
3587 /* command name , id , length , offset , mult , command handler */
3588 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3589 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3590 { "INIT_REPEAT" , 0x33, init_repeat },
3591 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3592 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3593 { "INIT_COPY" , 0x37, init_copy },
3594 { "INIT_NOT" , 0x38, init_not },
3595 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3596 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3597 { "INIT_OP_3B" , 0x3B, init_op_3b },
3598 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3599 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3600 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3601 { "INIT_PLL2" , 0x4B, init_pll2 },
3602 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3603 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3604 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3605 { "INIT_TMDS" , 0x4F, init_tmds },
3606 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3607 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3608 { "INIT_CR" , 0x52, init_cr },
3609 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3610 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3611 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
e3a1924f 3612 { "INIT_LTIME" , 0x57, init_ltime },
37383650 3613 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3614 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650 3615 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
ec64a408 3616 { "INIT_JUMP" , 0x5C, init_jump },
b715d640 3617 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
37383650
MK		 3618 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3619 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3620 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3621 { "INIT_RESET" , 0x65, init_reset },
3622 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3623 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3624 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3625 { "INIT_IO" , 0x69, init_io },
3626 { "INIT_SUB" , 0x6B, init_sub },
3627 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3628 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3629 { "INIT_MACRO" , 0x6F, init_macro },
3630 { "INIT_DONE" , 0x71, init_done },
3631 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3632 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3633 { "INIT_TIME" , 0x74, init_time },
3634 { "INIT_CONDITION" , 0x75, init_condition },
3635 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3636 { "INIT_INDEX_IO" , 0x78, init_index_io },
3637 { "INIT_PLL" , 0x79, init_pll },
3638 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3639 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3640 { "INIT_8C" , 0x8C, init_8c },
3641 { "INIT_8D" , 0x8D, init_8d },
3642 { "INIT_GPIO" , 0x8E, init_gpio },
3643 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3644 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3645 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3646 { "INIT_RESERVED" , 0x92, init_reserved },
3647 { "INIT_96" , 0x96, init_96 },
3648 { "INIT_97" , 0x97, init_97 },
3649 { "INIT_AUXCH" , 0x98, init_auxch },
3650 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
b715d640 3651 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
37383650 3652 { NULL , 0 , NULL }
6ee73861
BS		 3653};
3654
6ee73861
BS		 3655#define MAX_TABLE_OPS 1000
3656
3657static int
ec64a408 3658parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
6ee73861
BS		 3659{
3660 /*
3661 * Parses all commands in an init table.
3662 *
3663 * We start out executing all commands found in the init table. Some
3664 * opcodes may change the status of iexec->execute to SKIP, which will
3665 * cause the following opcodes to perform no operation until the value
3666 * is changed back to EXECUTE.
3667 */
3668
92b96187 3669 int count = 0, i, ret;
6ee73861
BS		 3670 uint8_t id;
3671
a8e415d3
BS		 3672 /* catch NULL script pointers */
3673 if (offset == 0)
3674 return 0;
3675
6ee73861
BS		 3676 /*
3677 * Loop until INIT_DONE causes us to break out of the loop
3678 * (or until offset > bios length just in case... )
3679 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3680 */
3681 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3682 id = bios->data[offset];
3683
3684 /* Find matching id in itbl_entry */
3685 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3686 ;
3687
92b96187 3688 if (!itbl_entry[i].name) {
6ee73861
BS		 3689 NV_ERROR(bios->dev,
3690 "0x%04X: Init table command not found: "
3691 "0x%02X\n", offset, id);
3692 return -ENOENT;
3693 }
92b96187
BS		 3694
3695 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3696 itbl_entry[i].id, itbl_entry[i].name);
3697
3698 /* execute eventual command handler */
3699 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3700 if (ret < 0) {
3701 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3702 "table opcode: %s %d\n", offset,
3703 itbl_entry[i].name, ret);
3704 }
3705
3706 if (ret <= 0)
3707 break;
3708
3709 /*
3710 * Add the offset of the current command including all data
3711 * of that command. The offset will then be pointing on the
3712 * next op code.
3713 */
3714 offset += ret;
6ee73861
BS		 3715 }
3716
3717 if (offset >= bios->length)
3718 NV_WARN(bios->dev,
3719 "Offset 0x%04X greater than known bios image length. "
3720 "Corrupt image?\n", offset);
3721 if (count >= MAX_TABLE_OPS)
3722 NV_WARN(bios->dev,
3723 "More than %d opcodes to a table is unlikely, "
3724 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3725
3726 return 0;
3727}
3728
3729static void
3730parse_init_tables(struct nvbios *bios)
3731{
3732 /* Loops and calls parse_init_table() for each present table. */
3733
3734 int i = 0;
3735 uint16_t table;
3736 struct init_exec iexec = {true, false};
3737
3738 if (bios->old_style_init) {
3739 if (bios->init_script_tbls_ptr)
3740 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3741 if (bios->extra_init_script_tbl_ptr)
3742 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3743
3744 return;
3745 }
3746
3747 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3748 NV_INFO(bios->dev,
3749 "Parsing VBIOS init table %d at offset 0x%04X\n",
3750 i / 2, table);
3751 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3752
3753 parse_init_table(bios, table, &iexec);
3754 i += 2;
3755 }
3756}
3757
3758static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3759{
3760 int compare_record_len, i = 0;
3761 uint16_t compareclk, scriptptr = 0;
3762
3763 if (bios->major_version < 5) /* pre BIT */
3764 compare_record_len = 3;
3765 else
3766 compare_record_len = 4;
3767
3768 do {
3769 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3770 if (pxclk >= compareclk * 10) {
3771 if (bios->major_version < 5) {
3772 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3773 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3774 } else
3775 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3776 break;
3777 }
3778 i++;
3779 } while (compareclk);
3780
3781 return scriptptr;
3782}
3783
3784static void
3785run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3786 struct dcb_entry *dcbent, int head, bool dl)
3787{
3788 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3789 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3790 struct init_exec iexec = {true, false};
3791
3792 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3793 scriptptr);
3794 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3795 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3796 /* note: if dcb entries have been merged, index may be misleading */
3797 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3798 parse_init_table(bios, scriptptr, &iexec);
3799
3800 nv04_dfp_bind_head(dev, dcbent, head, dl);
3801}
3802
3803static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3804{
3805 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3806 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3807 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3808 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3809
3810 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3811 return -EINVAL;
3812
3813 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3814
3815 if (script == LVDS_PANEL_OFF) {
3816 /* off-on delay in ms */
c7ca4d1b 3817 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
6ee73861
BS		 3818 }
3819#ifdef __powerpc__
3820 /* Powerbook specific quirks */
d31e078d
FJ		 3821 if (script == LVDS_RESET &&
3822 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3823 dev->pci_device == 0x0329))
3824 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
6ee73861
BS		 3825#endif
3826
3827 return 0;
3828}
3829
3830static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3831{
3832 /*
3833 * The BIT LVDS table's header has the information to setup the
3834 * necessary registers. Following the standard 4 byte header are:
3835 * A bitmask byte and a dual-link transition pxclk value for use in
3836 * selecting the init script when not using straps; 4 script pointers
3837 * for panel power, selected by output and on/off; and 8 table pointers
3838 * for panel init, the needed one determined by output, and bits in the
3839 * conf byte. These tables are similar to the TMDS tables, consisting
3840 * of a list of pxclks and script pointers.
3841 */
3842 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3843 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3844 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3845 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3846
3847 /*
3848 * For now we assume version 3.0 table - g80 support will need some
3849 * changes
3850 */
3851
3852 switch (script) {
3853 case LVDS_INIT:
3854 return -ENOSYS;
3855 case LVDS_BACKLIGHT_ON:
3856 case LVDS_PANEL_ON:
3857 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3858 break;
3859 case LVDS_BACKLIGHT_OFF:
3860 case LVDS_PANEL_OFF:
3861 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3862 break;
3863 case LVDS_RESET:
f3bbb9cc
BS		 3864 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3865 if (dcbent->or == 4)
3866 clktable += 8;
3867
6ee73861
BS		 3868 if (dcbent->lvdsconf.use_straps_for_mode) {
3869 if (bios->fp.dual_link)
f3bbb9cc
BS		 3870 clktable += 4;
3871 if (bios->fp.if_is_24bit)
3872 clktable += 2;
6ee73861
BS		 3873 } else {
3874 /* using EDID */
f3bbb9cc 3875 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3876
3877 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3878 clktable += 4;
3879 cmpval_24bit <<= 1;
6ee73861 3880 }
f3bbb9cc
BS		 3881
3882 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3883 clktable += 2;
6ee73861
BS		 3884 }
3885
f3bbb9cc 3886 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3887 if (!clktable) {
3888 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3889 return -ENOENT;
3890 }
3891 scriptptr = clkcmptable(bios, clktable, pxclk);
3892 }
3893
3894 if (!scriptptr) {
3895 NV_ERROR(dev, "LVDS output init script not found\n");
3896 return -ENOENT;
3897 }
3898 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3899
3900 return 0;
3901}
3902
3903int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3904{
3905 /*
3906 * LVDS operations are multiplexed in an effort to present a single API
3907 * which works with two vastly differing underlying structures.
3908 * This acts as the demux
3909 */
3910
3911 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3912 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3913 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3914 uint32_t sel_clk_binding, sel_clk;
3915 int ret;
3916
3917 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3918 (lvds_ver >= 0x30 && script == LVDS_INIT))
3919 return 0;
3920
3921 if (!bios->fp.lvds_init_run) {
3922 bios->fp.lvds_init_run = true;
3923 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3924 }
3925
3926 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3927 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3928 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3929 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3930
3931 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3932
3933 /* don't let script change pll->head binding */
3934 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3935
3936 if (lvds_ver < 0x30)
3937 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
3938 else
3939 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
3940
3941 bios->fp.last_script_invoc = (script << 1 | head);
3942
3943 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
3944 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
3945 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
3946 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
3947
3948 return ret;
3949}
3950
3951struct lvdstableheader {
3952 uint8_t lvds_ver, headerlen, recordlen;
3953};
3954
3955static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
3956{
3957 /*
3958 * BMP version (0xa) LVDS table has a simple header of version and
3959 * record length. The BIT LVDS table has the typical BIT table header:
3960 * version byte, header length byte, record length byte, and a byte for
3961 * the maximum number of records that can be held in the table.
3962 */
3963
3964 uint8_t lvds_ver, headerlen, recordlen;
3965
3966 memset(lth, 0, sizeof(struct lvdstableheader));
3967
3968 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
3969 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
3970 return -EINVAL;
3971 }
3972
3973 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3974
3975 switch (lvds_ver) {
3976 case 0x0a: /* pre NV40 */
3977 headerlen = 2;
3978 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3979 break;
3980 case 0x30: /* NV4x */
3981 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3982 if (headerlen < 0x1f) {
3983 NV_ERROR(dev, "LVDS table header not understood\n");
3984 return -EINVAL;
3985 }
3986 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3987 break;
3988 case 0x40: /* G80/G90 */
3989 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
3990 if (headerlen < 0x7) {
3991 NV_ERROR(dev, "LVDS table header not understood\n");
3992 return -EINVAL;
3993 }
3994 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
3995 break;
3996 default:
3997 NV_ERROR(dev,
3998 "LVDS table revision %d.%d not currently supported\n",
3999 lvds_ver >> 4, lvds_ver & 0xf);
4000 return -ENOSYS;
4001 }
4002
4003 lth->lvds_ver = lvds_ver;
4004 lth->headerlen = headerlen;
4005 lth->recordlen = recordlen;
4006
4007 return 0;
4008}
4009
4010static int
4011get_fp_strap(struct drm_device *dev, struct nvbios *bios)
4012{
4013 struct drm_nouveau_private *dev_priv = dev->dev_private;
4014
4015 /*
4016 * The fp strap is normally dictated by the "User Strap" in
4017 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4018 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4019 * by the PCI subsystem ID during POST, but not before the previous user
4020 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4021 * read and used instead
4022 */
4023
4024 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4025 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4026
4027 if (dev_priv->card_type >= NV_50)
4028 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4029 else
4030 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4031}
4032
4033static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4034{
4035 uint8_t *fptable;
4036 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4037 int ret, ofs, fpstrapping;
4038 struct lvdstableheader lth;
4039
4040 if (bios->fp.fptablepointer == 0x0) {
4041 /* Apple cards don't have the fp table; the laptops use DDC */
4042 /* The table is also missing on some x86 IGPs */
4043#ifndef __powerpc__
4044 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4045#endif
04a39c57 4046 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4047 return 0;
4048 }
4049
4050 fptable = &bios->data[bios->fp.fptablepointer];
4051 fptable_ver = fptable[0];
4052
4053 switch (fptable_ver) {
4054 /*
4055 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4056 * version field, and miss one of the spread spectrum/PWM bytes.
4057 * This could affect early GF2Go parts (not seen any appropriate ROMs
4058 * though). Here we assume that a version of 0x05 matches this case
4059 * (combining with a BMP version check would be better), as the
4060 * common case for the panel type field is 0x0005, and that is in
4061 * fact what we are reading the first byte of.
4062 */
4063 case 0x05: /* some NV10, 11, 15, 16 */
4064 recordlen = 42;
4065 ofs = -1;
4066 break;
4067 case 0x10: /* some NV15/16, and NV11+ */
4068 recordlen = 44;
4069 ofs = 0;
4070 break;
4071 case 0x20: /* NV40+ */
4072 headerlen = fptable[1];
4073 recordlen = fptable[2];
4074 fpentries = fptable[3];
4075 /*
4076 * fptable[4] is the minimum
4077 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4078 */
04a39c57 4079 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 4080 ofs = -7;
4081 break;
4082 default:
4083 NV_ERROR(dev,
4084 "FP table revision %d.%d not currently supported\n",
4085 fptable_ver >> 4, fptable_ver & 0xf);
4086 return -ENOSYS;
4087 }
4088
4089 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4090 return 0;
4091
4092 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4093 if (ret)
4094 return ret;
4095
4096 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4097 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4098 lth.headerlen + 1;
4099 bios->fp.xlatwidth = lth.recordlen;
4100 }
4101 if (bios->fp.fpxlatetableptr == 0x0) {
4102 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4103 return -EINVAL;
4104 }
4105
4106 fpstrapping = get_fp_strap(dev, bios);
4107
4108 fpindex = bios->data[bios->fp.fpxlatetableptr +
4109 fpstrapping * bios->fp.xlatwidth];
4110
4111 if (fpindex > fpentries) {
4112 NV_ERROR(dev, "Bad flat panel table index\n");
4113 return -ENOENT;
4114 }
4115
4116 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4117 if (lth.lvds_ver > 0x10)
04a39c57 4118 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 4119
4120 /*
4121 * If either the strap or xlated fpindex value are 0xf there is no
4122 * panel using a strap-derived bios mode present. this condition
4123 * includes, but is different from, the DDC panel indicator above
4124 */
4125 if (fpstrapping == 0xf || fpindex == 0xf)
4126 return 0;
4127
4128 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4129 recordlen * fpindex + ofs;
4130
4131 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4132 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4133 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4134 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4135
4136 return 0;
4137}
4138
4139bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4140{
4141 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4142 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4143 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4144
4145 if (!mode) /* just checking whether we can produce a mode */
4146 return bios->fp.mode_ptr;
4147
4148 memset(mode, 0, sizeof(struct drm_display_mode));
4149 /*
4150 * For version 1.0 (version in byte 0):
4151 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4152 * single/dual link, and type (TFT etc.)
4153 * bytes 3-6 are bits per colour in RGBX
4154 */
4155 mode->clock = ROM16(mode_entry[7]) * 10;
4156 /* bytes 9-10 is HActive */
4157 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4158 /*
4159 * bytes 13-14 is HValid Start
4160 * bytes 15-16 is HValid End
4161 */
4162 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4163 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4164 mode->htotal = ROM16(mode_entry[21]) + 1;
4165 /* bytes 23-24, 27-30 similarly, but vertical */
4166 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4167 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4168 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4169 mode->vtotal = ROM16(mode_entry[35]) + 1;
4170 mode->flags |= (mode_entry[37] & 0x10) ?
4171 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4172 mode->flags |= (mode_entry[37] & 0x1) ?
4173 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4174 /*
4175 * bytes 38-39 relate to spread spectrum settings
4176 * bytes 40-43 are something to do with PWM
4177 */
4178
4179 mode->status = MODE_OK;
4180 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4181 drm_mode_set_name(mode);
4182 return bios->fp.mode_ptr;
4183}
4184
4185int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4186{
4187 /*
4188 * The LVDS table header is (mostly) described in
4189 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4190 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4191 * straps are not being used for the panel, this specifies the frequency
4192 * at which modes should be set up in the dual link style.
4193 *
4194 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 4195 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 4196 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4197 * numbers for use by INIT_SUB which controlled panel init and power,
4198 * and finally a dword of ms to sleep between power off and on
4199 * operations.
4200 *
4201 * In the BIT versions, the table following the header serves as an
4202 * integrated config and xlat table: the records in the table are
4203 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4204 * two bytes - the first as a config byte, the second for indexing the
4205 * fp mode table pointed to by the BIT 'D' table
4206 *
4207 * DDC is not used until after card init, so selecting the correct table
4208 * entry and setting the dual link flag for EDID equipped panels,
4209 * requiring tests against the native-mode pixel clock, cannot be done
4210 * until later, when this function should be called with non-zero pxclk
4211 */
4212 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4213 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4214 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4215 struct lvdstableheader lth;
4216 uint16_t lvdsofs;
04a39c57 4217 int ret, chip_version = bios->chip_version;
6ee73861
BS		 4218
4219 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4220 if (ret)
4221 return ret;
4222
4223 switch (lth.lvds_ver) {
4224 case 0x0a: /* pre NV40 */
4225 lvdsmanufacturerindex = bios->data[
4226 bios->fp.fpxlatemanufacturertableptr +
4227 fpstrapping];
4228
4229 /* we're done if this isn't the EDID panel case */
4230 if (!pxclk)
4231 break;
4232
4233 if (chip_version < 0x25) {
4234 /* nv17 behaviour
4235 *
4236 * It seems the old style lvds script pointer is reused
4237 * to select 18/24 bit colour depth for EDID panels.
4238 */
4239 lvdsmanufacturerindex =
4240 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4241 2 : 0;
4242 if (pxclk >= bios->fp.duallink_transition_clk)
4243 lvdsmanufacturerindex++;
4244 } else if (chip_version < 0x30) {
4245 /* nv28 behaviour (off-chip encoder)
4246 *
4247 * nv28 does a complex dance of first using byte 121 of
4248 * the EDID to choose the lvdsmanufacturerindex, then
4249 * later attempting to match the EDID manufacturer and
4250 * product IDs in a table (signature 'pidt' (panel id
4251 * table?)), setting an lvdsmanufacturerindex of 0 and
4252 * an fp strap of the match index (or 0xf if none)
4253 */
4254 lvdsmanufacturerindex = 0;
4255 } else {
4256 /* nv31, nv34 behaviour */
4257 lvdsmanufacturerindex = 0;
4258 if (pxclk >= bios->fp.duallink_transition_clk)
4259 lvdsmanufacturerindex = 2;
4260 if (pxclk >= 140000)
4261 lvdsmanufacturerindex = 3;
4262 }
4263
4264 /*
4265 * nvidia set the high nibble of (cr57=f, cr58) to
4266 * lvdsmanufacturerindex in this case; we don't
4267 */
4268 break;
4269 case 0x30: /* NV4x */
4270 case 0x40: /* G80/G90 */
4271 lvdsmanufacturerindex = fpstrapping;
4272 break;
4273 default:
4274 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4275 return -ENOSYS;
4276 }
4277
4278 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4279 switch (lth.lvds_ver) {
4280 case 0x0a:
4281 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4282 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4283 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4284 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4285 *if_is_24bit = bios->data[lvdsofs] & 16;
4286 break;
4287 case 0x30:
f3bbb9cc 4288 case 0x40:
6ee73861
BS		 4289 /*
4290 * No sign of the "power off for reset" or "reset for panel
4291 * on" bits, but it's safer to assume we should
4292 */
4293 bios->fp.power_off_for_reset = true;
4294 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 4295
6ee73861
BS		 4296 /*
4297 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 4298 * over-written, and if_is_24bit isn't used
6ee73861
BS		 4299 */
4300 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 4301 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4302 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4303 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4304 break;
4305 }
4306
2eb92c80
BS		 4307 /* Dell Latitude D620 reports a too-high value for the dual-link
4308 * transition freq, causing us to program the panel incorrectly.
4309 *
4310 * It doesn't appear the VBIOS actually uses its transition freq
4311 * (90000kHz), instead it uses the "Number of LVDS channels" field
4312 * out of the panel ID structure (http://www.spwg.org/).
4313 *
4314 * For the moment, a quirk will do :)
4315 */
acae116c 4316 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
2eb92c80 4317 bios->fp.duallink_transition_clk = 80000;
2eb92c80 4318
6ee73861
BS		 4319 /* set dual_link flag for EDID case */
4320 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4321 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4322
4323 *dl = bios->fp.dual_link;
4324
4325 return 0;
4326}
4327
721b0821
BS		 4328/* BIT 'U'/'d' table encoder subtables have hashes matching them to
4329 * a particular set of encoders.
4330 *
4331 * This function returns true if a particular DCB entry matches.
4332 */
4333bool
4334bios_encoder_match(struct dcb_entry *dcb, u32 hash)
6ee73861 4335{
721b0821
BS		 4336 if ((hash & 0x000000f0) != (dcb->location << 4))
4337 return false;
4338 if ((hash & 0x0000000f) != dcb->type)
4339 return false;
4340 if (!(hash & (dcb->or << 16)))
4341 return false;
4342
4343 switch (dcb->type) {
1eb38100
BS		 4344 case OUTPUT_TMDS:
4345 case OUTPUT_LVDS:
4346 case OUTPUT_DP:
721b0821
BS		 4347 if (hash & 0x00c00000) {
4348 if (!(hash & (dcb->sorconf.link << 22)))
4349 return false;
1eb38100 4350 }
721b0821
BS		 4351 default:
4352 return true;
6ee73861 4353 }
6ee73861
BS		 4354}
4355
6ee73861 4356int
02e4f587
BS		 4357nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4358 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 4359{
4360 /*
4361 * The display script table is located by the BIT 'U' table.
4362 *
4363 * It contains an array of pointers to various tables describing
4364 * a particular output type. The first 32-bits of the output
4365 * tables contains similar information to a DCB entry, and is
4366 * used to decide whether that particular table is suitable for
4367 * the output you want to access.
4368 *
4369 * The "record header length" field here seems to indicate the
4370 * offset of the first configuration entry in the output tables.
4371 * This is 10 on most cards I've seen, but 12 has been witnessed
4372 * on DP cards, and there's another script pointer within the
4373 * header.
4374 *
4375 * offset + 0 ( 8 bits): version
4376 * offset + 1 ( 8 bits): header length
4377 * offset + 2 ( 8 bits): record length
4378 * offset + 3 ( 8 bits): number of records
4379 * offset + 4 ( 8 bits): record header length
4380 * offset + 5 (16 bits): pointer to first output script table
4381 */
4382
4383 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4384 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4385 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4386 uint8_t *otable = NULL;
4387 uint16_t script;
721b0821 4388 int i;
6ee73861
BS		 4389
4390 if (!bios->display.script_table_ptr) {
4391 NV_ERROR(dev, "No pointer to output script table\n");
4392 return 1;
4393 }
4394
4395 /*
4396 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4397 * so until they are, we really don't need to care.
4398 */
4399 if (table[0] < 0x20)
4400 return 1;
4401
4402 if (table[0] != 0x20 && table[0] != 0x21) {
4403 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4404 table[0]);
4405 return 1;
4406 }
4407
4408 /*
4409 * The output script tables describing a particular output type
4410 * look as follows:
4411 *
4412 * offset + 0 (32 bits): output this table matches (hash of DCB)
4413 * offset + 4 ( 8 bits): unknown
4414 * offset + 5 ( 8 bits): number of configurations
4415 * offset + 6 (16 bits): pointer to some script
4416 * offset + 8 (16 bits): pointer to some script
4417 *
4418 * headerlen == 10
4419 * offset + 10 : configuration 0
4420 *
4421 * headerlen == 12
4422 * offset + 10 : pointer to some script
4423 * offset + 12 : configuration 0
4424 *
4425 * Each config entry is as follows:
4426 *
4427 * offset + 0 (16 bits): unknown, assumed to be a match value
4428 * offset + 2 (16 bits): pointer to script table (clock set?)
4429 * offset + 4 (16 bits): pointer to script table (reset?)
4430 *
4431 * There doesn't appear to be a count value to say how many
4432 * entries exist in each script table, instead, a 0 value in
4433 * the first 16-bit word seems to indicate both the end of the
4434 * list and the default entry. The second 16-bit word in the
4435 * script tables is a pointer to the script to execute.
4436 */
4437
ef2bb506 4438 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861 4439 dcbent->type, dcbent->location, dcbent->or);
721b0821 4440 for (i = 0; i < table[3]; i++) {
f9f9f536 4441 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
721b0821
BS		 4442 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4443 break;
4444 }
4445
6ee73861 4446 if (!otable) {
54bf67de 4447 NV_DEBUG_KMS(dev, "failed to match any output table\n");
6ee73861
BS		 4448 return 1;
4449 }
4450
02e4f587 4451 if (pclk < -2 || pclk > 0) {
6ee73861
BS		 4452 /* Try to find matching script table entry */
4453 for (i = 0; i < otable[5]; i++) {
02e4f587 4454 if (ROM16(otable[table[4] + i*6]) == type)
6ee73861
BS		 4455 break;
4456 }
4457
4458 if (i == otable[5]) {
4459 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4460 "using first\n",
02e4f587 4461 type, dcbent->type, dcbent->or);
6ee73861
BS		 4462 i = 0;
4463 }
4464 }
4465
02e4f587 4466 if (pclk == 0) {
6ee73861
BS		 4467 script = ROM16(otable[6]);
4468 if (!script) {
ef2bb506 4469 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4470 return 1;
4471 }
4472
45a68a07 4473 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
02e4f587 4474 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4475 } else
02e4f587 4476 if (pclk == -1) {
6ee73861
BS		 4477 script = ROM16(otable[8]);
4478 if (!script) {
ef2bb506 4479 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4480 return 1;
4481 }
4482
45a68a07 4483 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
02e4f587 4484 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4485 } else
02e4f587 4486 if (pclk == -2) {
6ee73861
BS		 4487 if (table[4] >= 12)
4488 script = ROM16(otable[10]);
4489 else
4490 script = 0;
4491 if (!script) {
ef2bb506 4492 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4493 return 1;
4494 }
4495
45a68a07 4496 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
02e4f587 4497 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4498 } else
02e4f587 4499 if (pclk > 0) {
6ee73861
BS		 4500 script = ROM16(otable[table[4] + i*6 + 2]);
4501 if (script)
02e4f587 4502 script = clkcmptable(bios, script, pclk);
6ee73861 4503 if (!script) {
54bf67de 4504 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
6ee73861
BS		 4505 return 1;
4506 }
4507
45a68a07 4508 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
02e4f587 4509 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4510 } else
02e4f587 4511 if (pclk < 0) {
6ee73861
BS		 4512 script = ROM16(otable[table[4] + i*6 + 4]);
4513 if (script)
02e4f587 4514 script = clkcmptable(bios, script, -pclk);
6ee73861 4515 if (!script) {
ef2bb506 4516 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4517 return 1;
4518 }
4519
45a68a07 4520 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
02e4f587 4521 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861
BS		 4522 }
4523
4524 return 0;
4525}
4526
4527
4528int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4529{
4530 /*
4531 * the pxclk parameter is in kHz
4532 *
4533 * This runs the TMDS regs setting code found on BIT bios cards
4534 *
4535 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4536 * ffs(or) == 3, use the second.
4537 */
4538
4539 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4540 struct nvbios *bios = &dev_priv->vbios;
4541 int cv = bios->chip_version;
6ee73861
BS		 4542 uint16_t clktable = 0, scriptptr;
4543 uint32_t sel_clk_binding, sel_clk;
4544
4545 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4546 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4547 dcbent->location != DCB_LOC_ON_CHIP)
4548 return 0;
4549
4550 switch (ffs(dcbent->or)) {
4551 case 1:
4552 clktable = bios->tmds.output0_script_ptr;
4553 break;
4554 case 2:
4555 case 3:
4556 clktable = bios->tmds.output1_script_ptr;
4557 break;
4558 }
4559
4560 if (!clktable) {
4561 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4562 return -EINVAL;
4563 }
4564
4565 scriptptr = clkcmptable(bios, clktable, pxclk);
4566
4567 if (!scriptptr) {
4568 NV_ERROR(dev, "TMDS output init script not found\n");
4569 return -ENOENT;
4570 }
4571
4572 /* don't let script change pll->head binding */
4573 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4574 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4575 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4576 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4577
4578 return 0;
4579}
4580
855a95e4
BS		 4581struct pll_mapping {
4582 u8 type;
4583 u32 reg;
4584};
4585
4586static struct pll_mapping nv04_pll_mapping[] = {
4587 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4588 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4589 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4590 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4591 {}
4592};
4593
4594static struct pll_mapping nv40_pll_mapping[] = {
4595 { PLL_CORE , 0x004000 },
4596 { PLL_MEMORY, 0x004020 },
4597 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4598 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4599 {}
4600};
4601
4602static struct pll_mapping nv50_pll_mapping[] = {
4603 { PLL_CORE , 0x004028 },
4604 { PLL_SHADER, 0x004020 },
4605 { PLL_UNK03 , 0x004000 },
4606 { PLL_MEMORY, 0x004008 },
4607 { PLL_UNK40 , 0x00e810 },
4608 { PLL_UNK41 , 0x00e818 },
4609 { PLL_UNK42 , 0x00e824 },
4610 { PLL_VPLL0 , 0x614100 },
4611 { PLL_VPLL1 , 0x614900 },
4612 {}
4613};
4614
4615static struct pll_mapping nv84_pll_mapping[] = {
4616 { PLL_CORE , 0x004028 },
4617 { PLL_SHADER, 0x004020 },
4618 { PLL_MEMORY, 0x004008 },
d4cca9e1 4619 { PLL_VDEC , 0x004030 },
855a95e4
BS		 4620 { PLL_UNK41 , 0x00e818 },
4621 { PLL_VPLL0 , 0x614100 },
4622 { PLL_VPLL1 , 0x614900 },
4623 {}
4624};
4625
4626u32
4627get_pll_register(struct drm_device *dev, enum pll_types type)
4628{
4629 struct drm_nouveau_private *dev_priv = dev->dev_private;
4630 struct nvbios *bios = &dev_priv->vbios;
4631 struct pll_mapping *map;
4632 int i;
4633
4634 if (dev_priv->card_type < NV_40)
4635 map = nv04_pll_mapping;
4636 else
4637 if (dev_priv->card_type < NV_50)
4638 map = nv40_pll_mapping;
4639 else {
4640 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4641
56edd964 4642 if (plim[0] >= 0x30) {
855a95e4
BS		 4643 u8 *entry = plim + plim[1];
4644 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4645 if (entry[0] == type)
4646 return ROM32(entry[3]);
4647 }
4648
4649 return 0;
4650 }
4651
4652 if (dev_priv->chipset == 0x50)
4653 map = nv50_pll_mapping;
4654 else
4655 map = nv84_pll_mapping;
4656 }
4657
4658 while (map->reg) {
4659 if (map->type == type)
4660 return map->reg;
4661 map++;
4662 }
4663
4664 return 0;
4665}
4666
6ee73861
BS		 4667int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4668{
4669 /*
4670 * PLL limits table
4671 *
4672 * Version 0x10: NV30, NV31
4673 * One byte header (version), one record of 24 bytes
4674 * Version 0x11: NV36 - Not implemented
4675 * Seems to have same record style as 0x10, but 3 records rather than 1
4676 * Version 0x20: Found on Geforce 6 cards
4677 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4678 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4679 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4680 * length in general, some (integrated) have an extra configuration byte
4681 * Version 0x30: Found on Geforce 8, separates the register mapping
4682 * from the limits tables.
4683 */
4684
4685 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4686 struct nvbios *bios = &dev_priv->vbios;
4687 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4688 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4689 uint32_t crystal_strap_mask, crystal_straps;
4690
4691 if (!bios->pll_limit_tbl_ptr) {
4692 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4693 cv >= 0x40) {
4694 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4695 return -EINVAL;
4696 }
4697 } else
4698 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4699
4700 crystal_strap_mask = 1 << 6;
4701 /* open coded dev->twoHeads test */
4702 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4703 crystal_strap_mask |= 1 << 22;
4704 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4705 crystal_strap_mask;
4706
4707 switch (pll_lim_ver) {
4708 /*
4709 * We use version 0 to indicate a pre limit table bios (single stage
4710 * pll) and load the hard coded limits instead.
4711 */
4712 case 0:
4713 break;
4714 case 0x10:
4715 case 0x11:
4716 /*
4717 * Strictly v0x11 has 3 entries, but the last two don't seem
4718 * to get used.
4719 */
4720 headerlen = 1;
4721 recordlen = 0x18;
4722 entries = 1;
4723 pllindex = 0;
4724 break;
4725 case 0x20:
4726 case 0x21:
4727 case 0x30:
4728 case 0x40:
4729 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4730 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4731 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4732 break;
4733 default:
4734 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4735 "supported\n", pll_lim_ver);
4736 return -ENOSYS;
4737 }
4738
4739 /* initialize all members to zero */
4740 memset(pll_lim, 0, sizeof(struct pll_lims));
4741
855a95e4
BS		 4742 /* if we were passed a type rather than a register, figure
4743 * out the register and store it
4744 */
4745 if (limit_match > PLL_MAX)
4746 pll_lim->reg = limit_match;
6f876986 4747 else {
855a95e4 4748 pll_lim->reg = get_pll_register(dev, limit_match);
6f876986
BS		 4749 if (!pll_lim->reg)
4750 return -ENOENT;
4751 }
855a95e4 4752
6ee73861
BS		 4753 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4754 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4755
4756 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4757 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4758 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4759 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4760 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4761 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4762 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4763
4764 /* these values taken from nv30/31/36 */
4765 pll_lim->vco1.min_n = 0x1;
4766 if (cv == 0x36)
4767 pll_lim->vco1.min_n = 0x5;
4768 pll_lim->vco1.max_n = 0xff;
4769 pll_lim->vco1.min_m = 0x1;
4770 pll_lim->vco1.max_m = 0xd;
4771 pll_lim->vco2.min_n = 0x4;
4772 /*
4773 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4774 * table version (apart from nv35)), N2 is compared to
4775 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4776 * save a comparison
4777 */
4778 pll_lim->vco2.max_n = 0x28;
4779 if (cv == 0x30 || cv == 0x35)
4780 /* only 5 bits available for N2 on nv30/35 */
4781 pll_lim->vco2.max_n = 0x1f;
4782 pll_lim->vco2.min_m = 0x1;
4783 pll_lim->vco2.max_m = 0x4;
4784 pll_lim->max_log2p = 0x7;
4785 pll_lim->max_usable_log2p = 0x6;
4786 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4787 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
6ee73861
BS		 4788 uint8_t *pll_rec;
4789 int i;
4790
4791 /*
4792 * First entry is default match, if nothing better. warn if
4793 * reg field nonzero
4794 */
4795 if (ROM32(bios->data[plloffs]))
4796 NV_WARN(dev, "Default PLL limit entry has non-zero "
4797 "register field\n");
4798
6ee73861 4799 for (i = 1; i < entries; i++)
855a95e4 4800 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
6ee73861
BS		 4801 pllindex = i;
4802 break;
4803 }
4804
eadc69cc
EV		 4805 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4806 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4807 "limits table", pll_lim->reg);
4808 return -ENOENT;
4809 }
4810
6ee73861
BS		 4811 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4812
4813 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
855a95e4 4814 pllindex ? pll_lim->reg : 0);
6ee73861
BS		 4815
4816 /*
4817 * Frequencies are stored in tables in MHz, kHz are more
4818 * useful, so we convert.
4819 */
4820
4821 /* What output frequencies can each VCO generate? */
4822 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4823 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4824 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4825 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4826
4827 /* What input frequencies they accept (past the m-divider)? */
4828 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4829 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4830 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4831 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4832
4833 /* What values are accepted as multiplier and divider? */
4834 pll_lim->vco1.min_n = pll_rec[20];
4835 pll_lim->vco1.max_n = pll_rec[21];
4836 pll_lim->vco1.min_m = pll_rec[22];
4837 pll_lim->vco1.max_m = pll_rec[23];
4838 pll_lim->vco2.min_n = pll_rec[24];
4839 pll_lim->vco2.max_n = pll_rec[25];
4840 pll_lim->vco2.min_m = pll_rec[26];
4841 pll_lim->vco2.max_m = pll_rec[27];
4842
4843 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4844 if (pll_lim->max_log2p > 0x7)
4845 /* pll decoding in nv_hw.c assumes never > 7 */
4846 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4847 pll_lim->max_log2p);
4848 if (cv < 0x60)
4849 pll_lim->max_usable_log2p = 0x6;
4850 pll_lim->log2p_bias = pll_rec[30];
4851
4852 if (recordlen > 0x22)
4853 pll_lim->refclk = ROM32(pll_rec[31]);
4854
4855 if (recordlen > 0x23 && pll_rec[35])
4856 NV_WARN(dev,
4857 "Bits set in PLL configuration byte (%x)\n",
4858 pll_rec[35]);
4859
4860 /* C51 special not seen elsewhere */
4861 if (cv == 0x51 && !pll_lim->refclk) {
4862 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4863
855a95e4
BS		 4864 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4865 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
6ee73861
BS		 4866 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4867 pll_lim->refclk = 200000;
4868 else
4869 pll_lim->refclk = 25000;
4870 }
4871 }
4872 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4873 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4874 uint8_t *record = NULL;
4875 int i;
4876
4877 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 4878 pll_lim->reg);
6ee73861
BS		 4879
4880 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 4881 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 4882 record = &bios->data[ROM16(entry[1])];
4883 break;
4884 }
4885 }
4886
4887 if (!record) {
4888 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 4889 "limits table", pll_lim->reg);
6ee73861
BS		 4890 return -ENOENT;
4891 }
4892
4893 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4894 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4895 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4896 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4897 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4898 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4899 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
4900 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
4901 pll_lim->vco1.min_n = record[16];
4902 pll_lim->vco1.max_n = record[17];
4903 pll_lim->vco1.min_m = record[18];
4904 pll_lim->vco1.max_m = record[19];
4905 pll_lim->vco2.min_n = record[20];
4906 pll_lim->vco2.max_n = record[21];
4907 pll_lim->vco2.min_m = record[22];
4908 pll_lim->vco2.max_m = record[23];
4909 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
4910 pll_lim->log2p_bias = record[27];
4911 pll_lim->refclk = ROM32(record[28]);
4912 } else if (pll_lim_ver) { /* ver 0x40 */
4913 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4914 uint8_t *record = NULL;
4915 int i;
4916
4917 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 4918 pll_lim->reg);
6ee73861
BS		 4919
4920 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 4921 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 4922 record = &bios->data[ROM16(entry[1])];
4923 break;
4924 }
4925 }
4926
4927 if (!record) {
4928 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 4929 "limits table", pll_lim->reg);
6ee73861
BS		 4930 return -ENOENT;
4931 }
4932
4933 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4934 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4935 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
4936 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
4937 pll_lim->vco1.min_m = record[8];
4938 pll_lim->vco1.max_m = record[9];
4939 pll_lim->vco1.min_n = record[10];
4940 pll_lim->vco1.max_n = record[11];
4941 pll_lim->min_p = record[12];
4942 pll_lim->max_p = record[13];
ce521846 4943 pll_lim->refclk = ROM16(entry[9]) * 1000;
6ee73861
BS		 4944 }
4945
4946 /*
4947 * By now any valid limit table ought to have set a max frequency for
4948 * vco1, so if it's zero it's either a pre limit table bios, or one
4949 * with an empty limit table (seen on nv18)
4950 */
4951 if (!pll_lim->vco1.maxfreq) {
4952 pll_lim->vco1.minfreq = bios->fminvco;
4953 pll_lim->vco1.maxfreq = bios->fmaxvco;
4954 pll_lim->vco1.min_inputfreq = 0;
4955 pll_lim->vco1.max_inputfreq = INT_MAX;
4956 pll_lim->vco1.min_n = 0x1;
4957 pll_lim->vco1.max_n = 0xff;
4958 pll_lim->vco1.min_m = 0x1;
4959 if (crystal_straps == 0) {
4960 /* nv05 does this, nv11 doesn't, nv10 unknown */
4961 if (cv < 0x11)
4962 pll_lim->vco1.min_m = 0x7;
4963 pll_lim->vco1.max_m = 0xd;
4964 } else {
4965 if (cv < 0x11)
4966 pll_lim->vco1.min_m = 0x8;
4967 pll_lim->vco1.max_m = 0xe;
4968 }
4969 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
4970 pll_lim->max_log2p = 4;
4971 else
4972 pll_lim->max_log2p = 5;
4973 pll_lim->max_usable_log2p = pll_lim->max_log2p;
4974 }
4975
4976 if (!pll_lim->refclk)
4977 switch (crystal_straps) {
4978 case 0:
4979 pll_lim->refclk = 13500;
4980 break;
4981 case (1 << 6):
4982 pll_lim->refclk = 14318;
4983 break;
4984 case (1 << 22):
4985 pll_lim->refclk = 27000;
4986 break;
4987 case (1 << 22 | 1 << 6):
4988 pll_lim->refclk = 25000;
4989 break;
4990 }
4991
4c389f00
BS		 4992 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
4993 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
4994 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
4995 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
4996 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
4997 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
4998 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
4999 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
5000 if (pll_lim->vco2.maxfreq) {
5001 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
5002 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
5003 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
5004 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
5005 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
5006 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
5007 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
5008 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
5009 }
5010 if (!pll_lim->max_p) {
5011 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
5012 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
5013 } else {
5014 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
5015 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
5016 }
5017 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 5018
5019 return 0;
5020}
5021
5022static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
5023{
5024 /*
5025 * offset + 0 (8 bits): Micro version
5026 * offset + 1 (8 bits): Minor version
5027 * offset + 2 (8 bits): Chip version
5028 * offset + 3 (8 bits): Major version
5029 */
5030
5031 bios->major_version = bios->data[offset + 3];
04a39c57 5032 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 5033 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5034 bios->data[offset + 3], bios->data[offset + 2],
5035 bios->data[offset + 1], bios->data[offset]);
5036}
5037
5038static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5039{
5040 /*
5041 * Parses the init table segment for pointers used in script execution.
5042 *
5043 * offset + 0 (16 bits): init script tables pointer
5044 * offset + 2 (16 bits): macro index table pointer
5045 * offset + 4 (16 bits): macro table pointer
5046 * offset + 6 (16 bits): condition table pointer
5047 * offset + 8 (16 bits): io condition table pointer
5048 * offset + 10 (16 bits): io flag condition table pointer
5049 * offset + 12 (16 bits): init function table pointer
5050 */
5051
5052 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5053 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5054 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5055 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5056 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5057 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5058 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5059}
5060
5061static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5062{
5063 /*
5064 * Parses the load detect values for g80 cards.
5065 *
5066 * offset + 0 (16 bits): loadval table pointer
5067 */
5068
5069 uint16_t load_table_ptr;
5070 uint8_t version, headerlen, entrylen, num_entries;
5071
5072 if (bitentry->length != 3) {
5073 NV_ERROR(dev, "Do not understand BIT A table\n");
5074 return -EINVAL;
5075 }
5076
5077 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5078
5079 if (load_table_ptr == 0x0) {
1562ffde 5080 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
6ee73861
BS		 5081 return -EINVAL;
5082 }
5083
5084 version = bios->data[load_table_ptr];
5085
5086 if (version != 0x10) {
5087 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5088 version >> 4, version & 0xF);
5089 return -ENOSYS;
5090 }
5091
5092 headerlen = bios->data[load_table_ptr + 1];
5093 entrylen = bios->data[load_table_ptr + 2];
5094 num_entries = bios->data[load_table_ptr + 3];
5095
5096 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5097 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5098 return -EINVAL;
5099 }
5100
5101 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 5102 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 5103
5104 return 0;
5105}
5106
5107static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5108{
5109 /*
5110 * offset + 8 (16 bits): PLL limits table pointer
5111 *
5112 * There's more in here, but that's unknown.
5113 */
5114
5115 if (bitentry->length < 10) {
5116 NV_ERROR(dev, "Do not understand BIT C table\n");
5117 return -EINVAL;
5118 }
5119
5120 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5121
5122 return 0;
5123}
5124
5125static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5126{
5127 /*
5128 * Parses the flat panel table segment that the bit entry points to.
5129 * Starting at bitentry->offset:
5130 *
5131 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5132 * records beginning with a freq.
5133 * offset + 2 (16 bits): mode table pointer
5134 */
5135
5136 if (bitentry->length != 4) {
5137 NV_ERROR(dev, "Do not understand BIT display table\n");
5138 return -EINVAL;
5139 }
5140
5141 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5142
5143 return 0;
5144}
5145
5146static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5147{
5148 /*
5149 * Parses the init table segment that the bit entry points to.
5150 *
5151 * See parse_script_table_pointers for layout
5152 */
5153
5154 if (bitentry->length < 14) {
5155 NV_ERROR(dev, "Do not understand init table\n");
5156 return -EINVAL;
5157 }
5158
5159 parse_script_table_pointers(bios, bitentry->offset);
5160
5161 if (bitentry->length >= 16)
5162 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5163 if (bitentry->length >= 18)
5164 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5165
5166 return 0;
5167}
5168
5169static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5170{
5171 /*
5172 * BIT 'i' (info?) table
5173 *
5174 * offset + 0 (32 bits): BIOS version dword (as in B table)
5175 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5176 * offset + 13 (16 bits): pointer to table containing DAC load
5177 * detection comparison values
5178 *
5179 * There's other things in the table, purpose unknown
5180 */
5181
5182 uint16_t daccmpoffset;
5183 uint8_t dacver, dacheaderlen;
5184
5185 if (bitentry->length < 6) {
5186 NV_ERROR(dev, "BIT i table too short for needed information\n");
5187 return -EINVAL;
5188 }
5189
5190 parse_bios_version(dev, bios, bitentry->offset);
5191
5192 /*
5193 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5194 * Quadro identity crisis), other bits possibly as for BMP feature byte
5195 */
5196 bios->feature_byte = bios->data[bitentry->offset + 5];
5197 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5198
5199 if (bitentry->length < 15) {
5200 NV_WARN(dev, "BIT i table not long enough for DAC load "
5201 "detection comparison table\n");
5202 return -EINVAL;
5203 }
5204
5205 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5206
5207 /* doesn't exist on g80 */
5208 if (!daccmpoffset)
5209 return 0;
5210
5211 /*
5212 * The first value in the table, following the header, is the
5213 * comparison value, the second entry is a comparison value for
5214 * TV load detection.
5215 */
5216
5217 dacver = bios->data[daccmpoffset];
5218 dacheaderlen = bios->data[daccmpoffset + 1];
5219
5220 if (dacver != 0x00 && dacver != 0x10) {
5221 NV_WARN(dev, "DAC load detection comparison table version "
5222 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5223 return -ENOSYS;
5224 }
5225
04a39c57
BS		 5226 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5227 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 5228
5229 return 0;
5230}
5231
5232static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5233{
5234 /*
5235 * Parses the LVDS table segment that the bit entry points to.
5236 * Starting at bitentry->offset:
5237 *
5238 * offset + 0 (16 bits): LVDS strap xlate table pointer
5239 */
5240
5241 if (bitentry->length != 2) {
5242 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5243 return -EINVAL;
5244 }
5245
5246 /*
5247 * No idea if it's still called the LVDS manufacturer table, but
5248 * the concept's close enough.
5249 */
5250 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5251
5252 return 0;
5253}
5254
5255static int
5256parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5257 struct bit_entry *bitentry)
5258{
5259 /*
5260 * offset + 2 (8 bits): number of options in an
5261 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5262 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5263 * restrict option selection
5264 *
5265 * There's a bunch of bits in this table other than the RAM restrict
5266 * stuff that we don't use - their use currently unknown
5267 */
5268
6ee73861
BS		 5269 /*
5270 * Older bios versions don't have a sufficiently long table for
5271 * what we want
5272 */
5273 if (bitentry->length < 0x5)
5274 return 0;
5275
4709bff0 5276 if (bitentry->version < 2) {
37383650
MK		 5277 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5278 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 5279 } else {
37383650
MK		 5280 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5281 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 5282 }
5283
6ee73861
BS		 5284 return 0;
5285}
5286
5287static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5288{
5289 /*
5290 * Parses the pointer to the TMDS table
5291 *
5292 * Starting at bitentry->offset:
5293 *
5294 * offset + 0 (16 bits): TMDS table pointer
5295 *
5296 * The TMDS table is typically found just before the DCB table, with a
5297 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5298 * length?)
5299 *
5300 * At offset +7 is a pointer to a script, which I don't know how to
5301 * run yet.
5302 * At offset +9 is a pointer to another script, likewise
5303 * Offset +11 has a pointer to a table where the first word is a pxclk
5304 * frequency and the second word a pointer to a script, which should be
5305 * run if the comparison pxclk frequency is less than the pxclk desired.
5306 * This repeats for decreasing comparison frequencies
5307 * Offset +13 has a pointer to a similar table
5308 * The selection of table (and possibly +7/+9 script) is dictated by
5309 * "or" from the DCB.
5310 */
5311
5312 uint16_t tmdstableptr, script1, script2;
5313
5314 if (bitentry->length != 2) {
5315 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5316 return -EINVAL;
5317 }
5318
5319 tmdstableptr = ROM16(bios->data[bitentry->offset]);
98720bf4 5320 if (!tmdstableptr) {
6ee73861
BS		 5321 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5322 return -EINVAL;
5323 }
5324
98720bf4
BS		 5325 NV_INFO(dev, "TMDS table version %d.%d\n",
5326 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5327
6ee73861 5328 /* nv50+ has v2.0, but we don't parse it atm */
98720bf4 5329 if (bios->data[tmdstableptr] != 0x11)
6ee73861 5330 return -ENOSYS;
6ee73861
BS		 5331
5332 /*
5333 * These two scripts are odd: they don't seem to get run even when
5334 * they are not stubbed.
5335 */
5336 script1 = ROM16(bios->data[tmdstableptr + 7]);
5337 script2 = ROM16(bios->data[tmdstableptr + 9]);
5338 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5339 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5340
5341 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5342 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5343
5344 return 0;
5345}
5346
5347static int
5348parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5349 struct bit_entry *bitentry)
5350{
5351 /*
5352 * Parses the pointer to the G80 output script tables
5353 *
5354 * Starting at bitentry->offset:
5355 *
5356 * offset + 0 (16 bits): output script table pointer
5357 */
5358
5359 uint16_t outputscripttableptr;
5360
5361 if (bitentry->length != 3) {
5362 NV_ERROR(dev, "Do not understand BIT U table\n");
5363 return -EINVAL;
5364 }
5365
5366 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5367 bios->display.script_table_ptr = outputscripttableptr;
5368 return 0;
5369}
5370
6ee73861
BS		 5371struct bit_table {
5372 const char id;
5373 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5374};
5375
5376#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5377
4709bff0
BS		 5378int
5379bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5380{
5381 struct drm_nouveau_private *dev_priv = dev->dev_private;
5382 struct nvbios *bios = &dev_priv->vbios;
5383 u8 entries, *entry;
5384
5385 entries = bios->data[bios->offset + 10];
5386 entry = &bios->data[bios->offset + 12];
5387 while (entries--) {
5388 if (entry[0] == id) {
5389 bit->id = entry[0];
5390 bit->version = entry[1];
5391 bit->length = ROM16(entry[2]);
5392 bit->offset = ROM16(entry[4]);
f9f9f536 5393 bit->data = ROMPTR(dev, entry[4]);
4709bff0
BS		 5394 return 0;
5395 }
5396
5397 entry += bios->data[bios->offset + 9];
5398 }
5399
5400 return -ENOENT;
5401}
5402
6ee73861
BS		 5403static int
5404parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5405 struct bit_table *table)
5406{
5407 struct drm_device *dev = bios->dev;
6ee73861
BS		 5408 struct bit_entry bitentry;
5409
4709bff0 5410 if (bit_table(dev, table->id, &bitentry) == 0)
6ee73861 5411 return table->parse_fn(dev, bios, &bitentry);
6ee73861
BS		 5412
5413 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5414 return -ENOSYS;
5415}
5416
5417static int
5418parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5419{
5420 int ret;
5421
5422 /*
5423 * The only restriction on parsing order currently is having 'i' first
5424 * for use of bios->*_version or bios->feature_byte while parsing;
5425 * functions shouldn't be actually *doing* anything apart from pulling
5426 * data from the image into the bios struct, thus no interdependencies
5427 */
5428 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5429 if (ret) /* info? */
5430 return ret;
5431 if (bios->major_version >= 0x60) /* g80+ */
5432 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5433 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5434 if (ret)
5435 return ret;
5436 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5437 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5438 if (ret)
5439 return ret;
5440 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5441 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5442 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5443 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
6ee73861
BS		 5444
5445 return 0;
5446}
5447
5448static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5449{
5450 /*
5451 * Parses the BMP structure for useful things, but does not act on them
5452 *
5453 * offset + 5: BMP major version
5454 * offset + 6: BMP minor version
5455 * offset + 9: BMP feature byte
5456 * offset + 10: BCD encoded BIOS version
5457 *
5458 * offset + 18: init script table pointer (for bios versions < 5.10h)
5459 * offset + 20: extra init script table pointer (for bios
5460 * versions < 5.10h)
5461 *
5462 * offset + 24: memory init table pointer (used on early bios versions)
5463 * offset + 26: SDR memory sequencing setup data table
5464 * offset + 28: DDR memory sequencing setup data table
5465 *
5466 * offset + 54: index of I2C CRTC pair to use for CRT output
5467 * offset + 55: index of I2C CRTC pair to use for TV output
5468 * offset + 56: index of I2C CRTC pair to use for flat panel output
5469 * offset + 58: write CRTC index for I2C pair 0
5470 * offset + 59: read CRTC index for I2C pair 0
5471 * offset + 60: write CRTC index for I2C pair 1
5472 * offset + 61: read CRTC index for I2C pair 1
5473 *
5474 * offset + 67: maximum internal PLL frequency (single stage PLL)
5475 * offset + 71: minimum internal PLL frequency (single stage PLL)
5476 *
5477 * offset + 75: script table pointers, as described in
5478 * parse_script_table_pointers
5479 *
5480 * offset + 89: TMDS single link output A table pointer
5481 * offset + 91: TMDS single link output B table pointer
5482 * offset + 95: LVDS single link output A table pointer
5483 * offset + 105: flat panel timings table pointer
5484 * offset + 107: flat panel strapping translation table pointer
5485 * offset + 117: LVDS manufacturer panel config table pointer
5486 * offset + 119: LVDS manufacturer strapping translation table pointer
5487 *
5488 * offset + 142: PLL limits table pointer
5489 *
5490 * offset + 156: minimum pixel clock for LVDS dual link
5491 */
5492
5493 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5494 uint16_t bmplength;
5495 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5496
5497 /* load needed defaults in case we can't parse this info */
04a39c57 5498 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5499 bios->fmaxvco = 256000;
5500 bios->fminvco = 128000;
5501 bios->fp.duallink_transition_clk = 90000;
5502
5503 bmp_version_major = bmp[5];
5504 bmp_version_minor = bmp[6];
5505
5506 NV_TRACE(dev, "BMP version %d.%d\n",
5507 bmp_version_major, bmp_version_minor);
5508
5509 /*
5510 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5511 * pointer on early versions
5512 */
5513 if (bmp_version_major < 5)
5514 *(uint16_t *)&bios->data[0x36] = 0;
5515
5516 /*
5517 * Seems that the minor version was 1 for all major versions prior
5518 * to 5. Version 6 could theoretically exist, but I suspect BIT
5519 * happened instead.
5520 */
5521 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5522 NV_ERROR(dev, "You have an unsupported BMP version. "
5523 "Please send in your bios\n");
5524 return -ENOSYS;
5525 }
5526
5527 if (bmp_version_major == 0)
5528 /* nothing that's currently useful in this version */
5529 return 0;
5530 else if (bmp_version_major == 1)
5531 bmplength = 44; /* exact for 1.01 */
5532 else if (bmp_version_major == 2)
5533 bmplength = 48; /* exact for 2.01 */
5534 else if (bmp_version_major == 3)
5535 bmplength = 54;
5536 /* guessed - mem init tables added in this version */
5537 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5538 /* don't know if 5.0 exists... */
5539 bmplength = 62;
5540 /* guessed - BMP I2C indices added in version 4*/
5541 else if (bmp_version_minor < 0x6)
5542 bmplength = 67; /* exact for 5.01 */
5543 else if (bmp_version_minor < 0x10)
5544 bmplength = 75; /* exact for 5.06 */
5545 else if (bmp_version_minor == 0x10)
5546 bmplength = 89; /* exact for 5.10h */
5547 else if (bmp_version_minor < 0x14)
5548 bmplength = 118; /* exact for 5.11h */
5549 else if (bmp_version_minor < 0x24)
5550 /*
5551 * Not sure of version where pll limits came in;
5552 * certainly exist by 0x24 though.
5553 */
5554 /* length not exact: this is long enough to get lvds members */
5555 bmplength = 123;
5556 else if (bmp_version_minor < 0x27)
5557 /*
5558 * Length not exact: this is long enough to get pll limit
5559 * member
5560 */
5561 bmplength = 144;
5562 else
5563 /*
5564 * Length not exact: this is long enough to get dual link
5565 * transition clock.
5566 */
5567 bmplength = 158;
5568
5569 /* checksum */
5570 if (nv_cksum(bmp, 8)) {
5571 NV_ERROR(dev, "Bad BMP checksum\n");
5572 return -EINVAL;
5573 }
5574
5575 /*
5576 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5577 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5578 * (not nv10gl), bit 5 that the flat panel tables are present, and
5579 * bit 6 a tv bios.
5580 */
5581 bios->feature_byte = bmp[9];
5582
5583 parse_bios_version(dev, bios, offset + 10);
5584
5585 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5586 bios->old_style_init = true;
5587 legacy_scripts_offset = 18;
5588 if (bmp_version_major < 2)
5589 legacy_scripts_offset -= 4;
5590 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5591 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5592
5593 if (bmp_version_major > 2) { /* appears in BMP 3 */
5594 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5595 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5596 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5597 }
5598
5599 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5600 if (bmplength > 61)
5601 legacy_i2c_offset = offset + 54;
5602 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5603 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5604 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
6ee73861
BS		 5605
5606 if (bmplength > 74) {
5607 bios->fmaxvco = ROM32(bmp[67]);
5608 bios->fminvco = ROM32(bmp[71]);
5609 }
5610 if (bmplength > 88)
5611 parse_script_table_pointers(bios, offset + 75);
5612 if (bmplength > 94) {
5613 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5614 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5615 /*
5616 * Never observed in use with lvds scripts, but is reused for
5617 * 18/24 bit panel interface default for EDID equipped panels
5618 * (if_is_24bit not set directly to avoid any oscillation).
5619 */
5620 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5621 }
5622 if (bmplength > 108) {
5623 bios->fp.fptablepointer = ROM16(bmp[105]);
5624 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5625 bios->fp.xlatwidth = 1;
5626 }
5627 if (bmplength > 120) {
5628 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5629 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5630 }
5631 if (bmplength > 143)
5632 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5633
5634 if (bmplength > 157)
5635 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5636
5637 return 0;
5638}
5639
5640static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5641{
5642 int i, j;
5643
5644 for (i = 0; i <= (n - len); i++) {
5645 for (j = 0; j < len; j++)
5646 if (data[i + j] != str[j])
5647 break;
5648 if (j == len)
5649 return i;
5650 }
5651
5652 return 0;
5653}
5654
6ee73861
BS		 5655static struct dcb_gpio_entry *
5656new_gpio_entry(struct nvbios *bios)
5657{
e49f70f7 5658 struct drm_device *dev = bios->dev;
7f245b20 5659 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861 5660
e49f70f7
BS		 5661 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) {
5662 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n");
5663 return NULL;
5664 }
5665
6ee73861
BS		 5666 return &gpio->entry[gpio->entries++];
5667}
5668
5669struct dcb_gpio_entry *
5670nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5671{
5672 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5673 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5674 int i;
5675
7f245b20
BS		 5676 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5677 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5678 continue;
5679
7f245b20 5680 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5681 }
5682
5683 return NULL;
5684}
5685
6ee73861
BS		 5686static void
5687parse_dcb_gpio_table(struct nvbios *bios)
5688{
5689 struct drm_device *dev = bios->dev;
e49f70f7
BS		 5690 struct dcb_gpio_entry *e;
5691 u8 headerlen, entries, recordlen;
5692 u8 *dcb, *gpio = NULL, *entry;
6ee73861
BS		 5693 int i;
5694
f9f9f536 5695 dcb = ROMPTR(dev, bios->data[0x36]);
e49f70f7 5696 if (dcb[0] >= 0x30) {
f9f9f536 5697 gpio = ROMPTR(dev, dcb[10]);
e49f70f7
BS		 5698 if (!gpio)
5699 goto no_table;
6ee73861 5700
e49f70f7
BS		 5701 headerlen = gpio[1];
5702 entries = gpio[2];
5703 recordlen = gpio[3];
5704 } else
5e6a7443 5705 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) {
f9f9f536 5706 gpio = ROMPTR(dev, dcb[-15]);
e49f70f7
BS		 5707 if (!gpio)
5708 goto no_table;
5709
5710 headerlen = 3;
5711 entries = gpio[2];
5712 recordlen = gpio[1];
5e6a7443
FJ		 5713 } else
5714 if (dcb[0] >= 0x22) {
5715 /* No GPIO table present, parse the TVDAC GPIO data. */
5716 uint8_t *tvdac_gpio = &dcb[-5];
6ee73861 5717
5e6a7443
FJ		 5718 if (tvdac_gpio[0] & 1) {
5719 e = new_gpio_entry(bios);
5720 e->tag = DCB_GPIO_TVDAC0;
5721 e->line = tvdac_gpio[1] >> 4;
85a2a365
BS		 5722 e->state[0] = !!(tvdac_gpio[0] & 2);
5723 e->state[1] = !e->state[0];
6ee73861
BS		 5724 }
5725
5e6a7443 5726 goto no_table;
e49f70f7
BS		 5727 } else {
5728 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]);
5729 goto no_table;
5730 }
6ee73861 5731
e49f70f7
BS		 5732 entry = gpio + headerlen;
5733 for (i = 0; i < entries; i++, entry += recordlen) {
5734 e = new_gpio_entry(bios);
5735 if (!e)
5736 break;
6ee73861 5737
e49f70f7
BS		 5738 if (gpio[0] < 0x40) {
5739 e->entry = ROM16(entry[0]);
5740 e->tag = (e->entry & 0x07e0) >> 5;
5741 if (e->tag == 0x3f) {
5742 bios->dcb.gpio.entries--;
5743 continue;
5744 }
20d66daf 5745
e49f70f7 5746 e->line = (e->entry & 0x001f);
85a2a365
BS		 5747 e->state[0] = ((e->entry & 0xf800) >> 11) != 4;
5748 e->state[1] = !e->state[0];
e49f70f7
BS		 5749 } else {
5750 e->entry = ROM32(entry[0]);
5751 e->tag = (e->entry & 0x0000ff00) >> 8;
5752 if (e->tag == 0xff) {
5753 bios->dcb.gpio.entries--;
5754 continue;
5755 }
20d66daf 5756
e49f70f7 5757 e->line = (e->entry & 0x0000001f) >> 0;
d7f8172c
BS		 5758 if (gpio[0] == 0x40) {
5759 e->state_default = (e->entry & 0x01000000) >> 24;
5760 e->state[0] = (e->entry & 0x18000000) >> 27;
5761 e->state[1] = (e->entry & 0x60000000) >> 29;
5762 } else {
5763 e->state_default = (e->entry & 0x00000080) >> 7;
5764 e->state[0] = (entry[4] >> 4) & 3;
5765 e->state[1] = (entry[4] >> 6) & 3;
5766 }
20d66daf 5767 }
6ee73861
BS		 5768 }
5769
e49f70f7
BS		 5770no_table:
5771 /* Apple iMac G4 NV18 */
5772 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5773 e = new_gpio_entry(bios);
5774 if (e) {
5775 e->tag = DCB_GPIO_TVDAC0;
5776 e->line = 4;
5777 }
6ee73861 5778 }
6ee73861
BS		 5779}
5780
6b5a81a2
BS		 5781void *
5782dcb_table(struct drm_device *dev)
5783{
5784 struct drm_nouveau_private *dev_priv = dev->dev_private;
5785 u8 *dcb = NULL;
5786
5787 if (dev_priv->card_type > NV_04)
5788 dcb = ROMPTR(dev, dev_priv->vbios.data[0x36]);
5789 if (!dcb) {
5790 NV_WARNONCE(dev, "No DCB data found in VBIOS\n");
5791 return NULL;
5792 }
5793
5794 if (dcb[0] >= 0x41) {
5795 NV_WARNONCE(dev, "DCB version 0x%02x unknown\n", dcb[0]);
5796 return NULL;
5797 } else
5798 if (dcb[0] >= 0x30) {
5799 if (ROM32(dcb[6]) == 0x4edcbdcb)
5800 return dcb;
5801 } else
5802 if (dcb[0] >= 0x20) {
5803 if (ROM32(dcb[4]) == 0x4edcbdcb)
5804 return dcb;
5805 } else
5806 if (dcb[0] >= 0x15) {
5807 if (!memcmp(&dcb[-7], "DEV_REC", 7))
5808 return dcb;
5809 } else {
5810 /*
5811 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but
5812 * always has the same single (crt) entry, even when tv-out
5813 * present, so the conclusion is this version cannot really
5814 * be used.
5815 *
5816 * v1.2 tables (some NV6/10, and NV15+) normally have the
5817 * same 5 entries, which are not specific to the card and so
5818 * no use.
5819 *
5820 * v1.2 does have an I2C table that read_dcb_i2c_table can
5821 * handle, but cards exist (nv11 in #14821) with a bad i2c
5822 * table pointer, so use the indices parsed in
5823 * parse_bmp_structure.
5824 *
5825 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
5826 */
5827 NV_WARNONCE(dev, "No useful DCB data in VBIOS\n");
5828 return NULL;
5829 }
5830
5831 NV_WARNONCE(dev, "DCB header validation failed\n");
5832 return NULL;
5833}
5834
5835u8 *
5836dcb_outp(struct drm_device *dev, u8 idx)
5837{
5838 u8 *dcb = dcb_table(dev);
5839 if (dcb && dcb[0] >= 0x30) {
5840 if (idx < dcb[2])
5841 return dcb + dcb[1] + (idx * dcb[3]);
5842 } else
5843 if (dcb && dcb[0] >= 0x20) {
5844 u8 *i2c = ROMPTR(dev, dcb[2]);
5845 u8 *ent = dcb + 8 + (idx * 8);
5846 if (i2c && ent < i2c)
5847 return ent;
5848 } else
5849 if (dcb && dcb[0] >= 0x15) {
5850 u8 *i2c = ROMPTR(dev, dcb[2]);
5851 u8 *ent = dcb + 4 + (idx * 10);
5852 if (i2c && ent < i2c)
5853 return ent;
5854 }
5855
5856 return NULL;
5857}
5858
5859int
5860dcb_outp_foreach(struct drm_device *dev, void *data,
5861 int (*exec)(struct drm_device *, void *, int idx, u8 *outp))
5862{
5863 int ret, idx = -1;
5864 u8 *outp = NULL;
5865 while ((outp = dcb_outp(dev, ++idx))) {
5866 if (ROM32(outp[0]) == 0x00000000)
5867 break; /* seen on an NV11 with DCB v1.5 */
5868 if (ROM32(outp[0]) == 0xffffffff)
5869 break; /* seen on an NV17 with DCB v2.0 */
5870
5871 if ((outp[0] & 0x0f) == OUTPUT_UNUSED)
5872 continue;
5873 if ((outp[0] & 0x0f) == OUTPUT_EOL)
5874 break;
5875
5876 ret = exec(dev, data, idx, outp);
5877 if (ret)
5878 return ret;
5879 }
5880
5881 return 0;
5882}
5883
befb51e9
BS		 5884u8 *
5885dcb_conntab(struct drm_device *dev)
5886{
5887 u8 *dcb = dcb_table(dev);
5888 if (dcb && dcb[0] >= 0x30 && dcb[1] >= 0x16) {
5889 u8 *conntab = ROMPTR(dev, dcb[0x14]);
5890 if (conntab && conntab[0] >= 0x30 && conntab[0] <= 0x40)
5891 return conntab;
5892 }
5893 return NULL;
5894}
5895
5896u8 *
5897dcb_conn(struct drm_device *dev, u8 idx)
5898{
5899 u8 *conntab = dcb_conntab(dev);
5900 if (conntab && idx < conntab[2])
5901 return conntab + conntab[1] + (idx * conntab[3]);
5902 return NULL;
5903}
5904
7f245b20 5905static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 5906{
5907 struct dcb_entry *entry = &dcb->entry[dcb->entries];
5908
5909 memset(entry, 0, sizeof(struct dcb_entry));
5910 entry->index = dcb->entries++;
5911
5912 return entry;
5913}
5914
2e5702af
FJ		 5915static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
5916 int heads, int or)
6ee73861
BS		 5917{
5918 struct dcb_entry *entry = new_dcb_entry(dcb);
5919
2e5702af 5920 entry->type = type;
6ee73861
BS		 5921 entry->i2c_index = i2c;
5922 entry->heads = heads;
2e5702af
FJ		 5923 if (type != OUTPUT_ANALOG)
5924 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
5925 entry->or = or;
6ee73861
BS		 5926}
5927
5928static bool
7f245b20 5929parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 5930 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
5931{
5932 entry->type = conn & 0xf;
5933 entry->i2c_index = (conn >> 4) & 0xf;
5934 entry->heads = (conn >> 8) & 0xf;
befb51e9 5935 entry->connector = (conn >> 12) & 0xf;
6ee73861
BS		 5936 entry->bus = (conn >> 16) & 0xf;
5937 entry->location = (conn >> 20) & 0x3;
5938 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 5939
5940 switch (entry->type) {
5941 case OUTPUT_ANALOG:
5942 /*
5943 * Although the rest of a CRT conf dword is usually
5944 * zeros, mac biosen have stuff there so we must mask
5945 */
7f245b20 5946 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 5947 (conf & 0xffff) * 10 :
5948 (conf & 0xff) * 10000;
5949 break;
5950 case OUTPUT_LVDS:
5951 {
5952 uint32_t mask;
5953 if (conf & 0x1)
5954 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 5955 if (dcb->version < 0x22) {
6ee73861
BS		 5956 mask = ~0xd;
5957 /*
5958 * The laptop in bug 14567 lies and claims to not use
5959 * straps when it does, so assume all DCB 2.0 laptops
5960 * use straps, until a broken EDID using one is produced
5961 */
5962 entry->lvdsconf.use_straps_for_mode = true;
5963 /*
5964 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
5965 * mean the same thing (probably wrong, but might work)
5966 */
5967 if (conf & 0x4 || conf & 0x8)
5968 entry->lvdsconf.use_power_scripts = true;
5969 } else {
a6ed76d7
BS		 5970 mask = ~0x7;
5971 if (conf & 0x2)
5972 entry->lvdsconf.use_acpi_for_edid = true;
6ee73861
BS		 5973 if (conf & 0x4)
5974 entry->lvdsconf.use_power_scripts = true;
c5875470 5975 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6ee73861
BS		 5976 }
5977 if (conf & mask) {
5978 /*
5979 * Until we even try to use these on G8x, it's
5980 * useless reporting unknown bits. They all are.
5981 */
7f245b20 5982 if (dcb->version >= 0x40)
6ee73861
BS		 5983 break;
5984
5985 NV_ERROR(dev, "Unknown LVDS configuration bits, "
5986 "please report\n");
5987 }
5988 break;
5989 }
5990 case OUTPUT_TV:
5991 {
7f245b20 5992 if (dcb->version >= 0x30)
6ee73861
BS		 5993 entry->tvconf.has_component_output = conf & (0x8 << 4);
5994 else
5995 entry->tvconf.has_component_output = false;
5996
5997 break;
5998 }
5999 case OUTPUT_DP:
6000 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
75a1fccf
BS		 6001 switch ((conf & 0x00e00000) >> 21) {
6002 case 0:
6003 entry->dpconf.link_bw = 162000;
6004 break;
6005 default:
6006 entry->dpconf.link_bw = 270000;
6007 break;
6008 }
6ee73861
BS		 6009 switch ((conf & 0x0f000000) >> 24) {
6010 case 0xf:
6011 entry->dpconf.link_nr = 4;
6012 break;
6013 case 0x3:
6014 entry->dpconf.link_nr = 2;
6015 break;
6016 default:
6017 entry->dpconf.link_nr = 1;
6018 break;
6019 }
6020 break;
6021 case OUTPUT_TMDS:
27d50fcc
FJ		 6022 if (dcb->version >= 0x40)
6023 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
4a9f822f
FJ		 6024 else if (dcb->version >= 0x30)
6025 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
27d50fcc
FJ		 6026 else if (dcb->version >= 0x22)
6027 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
4a9f822f 6028
6ee73861 6029 break;
44a1246f 6030 case OUTPUT_EOL:
6ee73861 6031 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 6032 dcb->entries--;
6ee73861 6033 return false;
e7cc51c5
BS		 6034 default:
6035 break;
6ee73861
BS		 6036 }
6037
23484874
BS		 6038 if (dcb->version < 0x40) {
6039 /* Normal entries consist of a single bit, but dual link has
6040 * the next most significant bit set too
6041 */
6042 entry->duallink_possible =
6043 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6044 } else {
6045 entry->duallink_possible = (entry->sorconf.link == 3);
6046 }
6047
6ee73861
BS		 6048 /* unsure what DCB version introduces this, 3.0? */
6049 if (conf & 0x100000)
6050 entry->i2c_upper_default = true;
6051
6052 return true;
6053}
6054
6055static bool
7f245b20 6056parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6057 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6058{
b0d2de86
BS		 6059 switch (conn & 0x0000000f) {
6060 case 0:
6061 entry->type = OUTPUT_ANALOG;
6062 break;
6063 case 1:
6064 entry->type = OUTPUT_TV;
6065 break;
6066 case 2:
b0d2de86 6067 case 4:
fba67528 6068 if (conn & 0x10)
b0d2de86 6069 entry->type = OUTPUT_LVDS;
fba67528
FJ		 6070 else
6071 entry->type = OUTPUT_TMDS;
6072 break;
6073 case 3:
6074 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 6075 break;
6076 default:
6077 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6078 return false;
6ee73861 6079 }
b0d2de86
BS		 6080
6081 entry->i2c_index = (conn & 0x0003c000) >> 14;
6082 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6083 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6084 entry->location = (conn & 0x01e00000) >> 21;
6085 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 6086 entry->duallink_possible = false;
6087
6088 switch (entry->type) {
6089 case OUTPUT_ANALOG:
6090 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6091 break;
b0d2de86
BS		 6092 case OUTPUT_TV:
6093 entry->tvconf.has_component_output = false;
6ee73861 6094 break;
b0d2de86 6095 case OUTPUT_LVDS:
77b1d5dc 6096 if ((conn & 0x00003f00) >> 8 != 0x10)
b0d2de86
BS		 6097 entry->lvdsconf.use_straps_for_mode = true;
6098 entry->lvdsconf.use_power_scripts = true;
6099 break;
6100 default:
6ee73861
BS		 6101 break;
6102 }
6103
6104 return true;
6105}
6106
6ee73861 6107static
7f245b20 6108void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 6109{
6110 /*
6111 * DCB v2.0 lists each output combination separately.
6112 * Here we merge compatible entries to have fewer outputs, with
6113 * more options
6114 */
6115
6116 int i, newentries = 0;
6117
6118 for (i = 0; i < dcb->entries; i++) {
6119 struct dcb_entry *ient = &dcb->entry[i];
6120 int j;
6121
6122 for (j = i + 1; j < dcb->entries; j++) {
6123 struct dcb_entry *jent = &dcb->entry[j];
6124
6125 if (jent->type == 100) /* already merged entry */
6126 continue;
6127
6128 /* merge heads field when all other fields the same */
6129 if (jent->i2c_index == ient->i2c_index &&
6130 jent->type == ient->type &&
6131 jent->location == ient->location &&
6132 jent->or == ient->or) {
6133 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6134 i, j);
6135 ient->heads |= jent->heads;
6136 jent->type = 100; /* dummy value */
6137 }
6138 }
6139 }
6140
6141 /* Compact entries merged into others out of dcb */
6142 for (i = 0; i < dcb->entries; i++) {
6143 if (dcb->entry[i].type == 100)
6144 continue;
6145
6146 if (newentries != i) {
6147 dcb->entry[newentries] = dcb->entry[i];
6148 dcb->entry[newentries].index = newentries;
6149 }
6150 newentries++;
6151 }
6152
6153 dcb->entries = newentries;
6154}
6155
df4cf1b7
BS		 6156static bool
6157apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6158{
670820c0
FJ		 6159 struct drm_nouveau_private *dev_priv = dev->dev_private;
6160 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6161
df4cf1b7
BS		 6162 /* Dell Precision M6300
6163 * DCB entry 2: 02025312 00000010
6164 * DCB entry 3: 02026312 00000020
6165 *
6166 * Identical, except apparently a different connector on a
6167 * different SOR link. Not a clue how we're supposed to know
6168 * which one is in use if it even shares an i2c line...
6169 *
6170 * Ignore the connector on the second SOR link to prevent
6171 * nasty problems until this is sorted (assuming it's not a
6172 * VBIOS bug).
6173 */
acae116c 6174 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
df4cf1b7
BS		 6175 if (*conn == 0x02026312 && *conf == 0x00000020)
6176 return false;
6177 }
6178
670820c0
FJ		 6179 /* GeForce3 Ti 200
6180 *
6181 * DCB reports an LVDS output that should be TMDS:
6182 * DCB entry 1: f2005014 ffffffff
6183 */
6184 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6185 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6186 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6187 return false;
6188 }
6189 }
6190
c0929b49
BS		 6191 /* XFX GT-240X-YA
6192 *
6193 * So many things wrong here, replace the entire encoder table..
6194 */
6195 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6196 if (idx == 0) {
6197 *conn = 0x02001300; /* VGA, connector 1 */
6198 *conf = 0x00000028;
6199 } else
6200 if (idx == 1) {
6201 *conn = 0x01010312; /* DVI, connector 0 */
6202 *conf = 0x00020030;
6203 } else
6204 if (idx == 2) {
6205 *conn = 0x01010310; /* VGA, connector 0 */
6206 *conf = 0x00000028;
6207 } else
6208 if (idx == 3) {
6209 *conn = 0x02022362; /* HDMI, connector 2 */
6210 *conf = 0x00020010;
6211 } else {
6212 *conn = 0x0000000e; /* EOL */
6213 *conf = 0x00000000;
6214 }
6215 }
6216
e540afc3
BS		 6217 /* Some other twisted XFX board (rhbz#694914)
6218 *
6219 * The DVI/VGA encoder combo that's supposed to represent the
6220 * DVI-I connector actually point at two different ones, and
6221 * the HDMI connector ends up paired with the VGA instead.
6222 *
6223 * Connector table is missing anything for VGA at all, pointing it
6224 * an invalid conntab entry 2 so we figure it out ourself.
6225 */
6226 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6227 if (idx == 0) {
6228 *conn = 0x02002300; /* VGA, connector 2 */
6229 *conf = 0x00000028;
6230 } else
6231 if (idx == 1) {
6232 *conn = 0x01010312; /* DVI, connector 0 */
6233 *conf = 0x00020030;
6234 } else
6235 if (idx == 2) {
6236 *conn = 0x04020310; /* VGA, connector 0 */
6237 *conf = 0x00000028;
6238 } else
6239 if (idx == 3) {
6240 *conn = 0x02021322; /* HDMI, connector 1 */
6241 *conf = 0x00020010;
6242 } else {
6243 *conn = 0x0000000e; /* EOL */
6244 *conf = 0x00000000;
6245 }
6246 }
6247
df4cf1b7
BS		 6248 return true;
6249}
6250
2e5702af
FJ		 6251static void
6252fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6253{
6254 struct dcb_table *dcb = &bios->dcb;
6255 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6256
6257#ifdef __powerpc__
6258 /* Apple iMac G4 NV17 */
6259 if (of_machine_is_compatible("PowerMac4,5")) {
6260 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6261 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6262 return;
6263 }
6264#endif
6265
6266 /* Make up some sane defaults */
0f8067c7
BS		 6267 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
6268 bios->legacy.i2c_indices.crt, 1, 1);
2e5702af
FJ		 6269
6270 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
0f8067c7
BS		 6271 fabricate_dcb_output(dcb, OUTPUT_TV,
6272 bios->legacy.i2c_indices.tv,
2e5702af
FJ		 6273 all_heads, 0);
6274
6275 else if (bios->tmds.output0_script_ptr ||
6276 bios->tmds.output1_script_ptr)
0f8067c7
BS		 6277 fabricate_dcb_output(dcb, OUTPUT_TMDS,
6278 bios->legacy.i2c_indices.panel,
2e5702af
FJ		 6279 all_heads, 1);
6280}
6281
ed42f824 6282static int
6b5a81a2 6283parse_dcb_entry(struct drm_device *dev, void *data, int idx, u8 *outp)
6ee73861 6284{
ed42f824 6285 struct drm_nouveau_private *dev_priv = dev->dev_private;
6b5a81a2
BS		 6286 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6287 u32 conf = (dcb->version >= 0x20) ? ROM32(outp[4]) : ROM32(outp[6]);
6288 u32 conn = ROM32(outp[0]);
6289 bool ret;
6ee73861 6290
6b5a81a2
BS		 6291 if (apply_dcb_encoder_quirks(dev, idx, &conn, &conf)) {
6292 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861 6293
befb51e9 6294 NV_TRACEWARN(dev, "DCB outp %02d: %08x %08x\n", idx, conn, conf);
6ee73861 6295
6b5a81a2
BS		 6296 if (dcb->version >= 0x20)
6297 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6298 else
6299 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6300 if (!ret)
6301 return 1; /* stop parsing */
befb51e9
BS		 6302
6303 /* Ignore the I2C index for on-chip TV-out, as there
6304 * are cards with bogus values (nv31m in bug 23212),
6305 * and it's otherwise useless.
6306 */
6307 if (entry->type == OUTPUT_TV &&
6308 entry->location == DCB_LOC_ON_CHIP)
6309 entry->i2c_index = 0x0f;
6b5a81a2 6310 }
6ee73861 6311
6b5a81a2
BS		 6312 return 0;
6313}
6ee73861 6314
befb51e9
BS		 6315static void
6316dcb_fake_connectors(struct nvbios *bios)
6317{
6318 struct dcb_table *dcbt = &bios->dcb;
6319 u8 map[16] = { };
6320 int i, idx = 0;
6321
6322 /* heuristic: if we ever get a non-zero connector field, assume
6323 * that all the indices are valid and we don't need fake them.
6324 */
6325 for (i = 0; i < dcbt->entries; i++) {
6326 if (dcbt->entry[i].connector)
6327 return;
6328 }
6329
6330 /* no useful connector info available, we need to make it up
6331 * ourselves. the rule here is: anything on the same i2c bus
6332 * is considered to be on the same connector. any output
6333 * without an associated i2c bus is assigned its own unique
6334 * connector index.
6335 */
6336 for (i = 0; i < dcbt->entries; i++) {
6337 u8 i2c = dcbt->entry[i].i2c_index;
6338 if (i2c == 0x0f) {
6339 dcbt->entry[i].connector = idx++;
6340 } else {
6341 if (!map[i2c])
6342 map[i2c] = ++idx;
6343 dcbt->entry[i].connector = map[i2c] - 1;
6344 }
6345 }
6346
6347 /* if we created more than one connector, destroy the connector
6348 * table - just in case it has random, rather than stub, entries.
6349 */
6350 if (i > 1) {
6351 u8 *conntab = dcb_conntab(bios->dev);
6352 if (conntab)
6353 conntab[0] = 0x00;
6354 }
6355}
6356
6b5a81a2
BS		 6357static int
6358parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6359{
6360 struct dcb_table *dcb = &bios->dcb;
befb51e9
BS		 6361 u8 *dcbt, *conn;
6362 int idx;
6b5a81a2
BS		 6363
6364 dcbt = dcb_table(dev);
6365 if (!dcbt) {
6366 /* handle pre-DCB boards */
6367 if (bios->type == NVBIOS_BMP) {
6368 fabricate_dcb_encoder_table(dev, bios);
6369 return 0;
6ee73861
BS		 6370 }
6371
6b5a81a2
BS		 6372 return -EINVAL;
6373 }
6ee73861 6374
6b5a81a2 6375 NV_TRACE(dev, "DCB version %d.%d\n", dcbt[0] >> 4, dcbt[0] & 0xf);
6ee73861 6376
6b5a81a2 6377 dcb->version = dcbt[0];
befb51e9 6378 if (dcb->version >= 0x30)
6b5a81a2 6379 dcb->gpio_table_ptr = ROM16(dcbt[10]);
6ee73861 6380
6b5a81a2 6381 dcb_outp_foreach(dev, NULL, parse_dcb_entry);
6ee73861
BS		 6382
6383 /*
6384 * apart for v2.1+ not being known for requiring merging, this
6385 * guarantees dcbent->index is the index of the entry in the rom image
6386 */
7f245b20 6387 if (dcb->version < 0x21)
6ee73861
BS		 6388 merge_like_dcb_entries(dev, dcb);
6389
54abb5dd
BS		 6390 if (!dcb->entries)
6391 return -ENXIO;
6392
befb51e9
BS		 6393 /* dump connector table entries to log, if any exist */
6394 idx = -1;
6395 while ((conn = dcb_conn(dev, ++idx))) {
6396 if (conn[0] != 0xff) {
6397 NV_TRACE(dev, "DCB conn %02d: ", idx);
6398 if (dcb_conntab(dev)[3] < 4)
6399 printk("%04x\n", ROM16(conn[0]));
6400 else
6401 printk("%08x\n", ROM32(conn[0]));
6ee73861 6402 }
6ee73861 6403 }
befb51e9 6404 dcb_fake_connectors(bios);
6ee73861 6405
befb51e9
BS		 6406 parse_dcb_gpio_table(bios);
6407 return 0;
6ee73861
BS		 6408}
6409
6ee73861
BS		 6410static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6411{
6412 /*
6413 * The header following the "HWSQ" signature has the number of entries,
6414 * and the entry size
6415 *
6416 * An entry consists of a dword to write to the sequencer control reg
6417 * (0x00001304), followed by the ucode bytes, written sequentially,
6418 * starting at reg 0x00001400
6419 */
6420
6421 uint8_t bytes_to_write;
6422 uint16_t hwsq_entry_offset;
6423 int i;
6424
6425 if (bios->data[hwsq_offset] <= entry) {
6426 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6427 "requested entry\n");
6428 return -ENOENT;
6429 }
6430
6431 bytes_to_write = bios->data[hwsq_offset + 1];
6432
6433 if (bytes_to_write != 36) {
6434 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6435 return -EINVAL;
6436 }
6437
6438 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6439
6440 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6441
6442 /* set sequencer control */
6443 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6444 bytes_to_write -= 4;
6445
6446 /* write ucode */
6447 for (i = 0; i < bytes_to_write; i += 4)
6448 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6449
6450 /* twiddle NV_PBUS_DEBUG_4 */
6451 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6452
6453 return 0;
6454}
6455
6456static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6457 struct nvbios *bios)
6458{
6459 /*
6460 * BMP based cards, from NV17, need a microcode loading to correctly
6461 * control the GPIO etc for LVDS panels
6462 *
6463 * BIT based cards seem to do this directly in the init scripts
6464 *
6465 * The microcode entries are found by the "HWSQ" signature.
6466 */
6467
6468 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6469 const int sz = sizeof(hwsq_signature);
6470 int hwsq_offset;
6471
6472 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6473 if (!hwsq_offset)
6474 return 0;
6475
6476 /* always use entry 0? */
6477 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6478}
6479
6480uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6481{
6482 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6483 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6484 const uint8_t edid_sig[] = {
6485 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6486 uint16_t offset = 0;
6487 uint16_t newoffset;
6488 int searchlen = NV_PROM_SIZE;
6489
6490 if (bios->fp.edid)
6491 return bios->fp.edid;
6492
6493 while (searchlen) {
6494 newoffset = findstr(&bios->data[offset], searchlen,
6495 edid_sig, 8);
6496 if (!newoffset)
6497 return NULL;
6498 offset += newoffset;
6499 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6500 break;
6501
6502 searchlen -= offset;
6503 offset++;
6504 }
6505
6506 NV_TRACE(dev, "Found EDID in BIOS\n");
6507
6508 return bios->fp.edid = &bios->data[offset];
6509}
6510
6511void
6512nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
02e4f587 6513 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 6514{
6515 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6516 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6517 struct init_exec iexec = { true, false };
6518
c7ca4d1b 6519 spin_lock_bh(&bios->lock);
6ee73861 6520 bios->display.output = dcbent;
02e4f587 6521 bios->display.crtc = crtc;
6ee73861
BS		 6522 parse_init_table(bios, table, &iexec);
6523 bios->display.output = NULL;
c7ca4d1b 6524 spin_unlock_bh(&bios->lock);
6ee73861
BS		 6525}
6526
59ef9742
BS		 6527void
6528nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6529{
6530 struct drm_nouveau_private *dev_priv = dev->dev_private;
6531 struct nvbios *bios = &dev_priv->vbios;
6532 struct init_exec iexec = { true, false };
6533
6534 parse_init_table(bios, table, &iexec);
6535}
6536
6ee73861
BS		 6537static bool NVInitVBIOS(struct drm_device *dev)
6538{
6539 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6540 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6541
6542 memset(bios, 0, sizeof(struct nvbios));
c7ca4d1b 6543 spin_lock_init(&bios->lock);
6ee73861
BS		 6544 bios->dev = dev;
6545
6546 if (!NVShadowVBIOS(dev, bios->data))
6547 return false;
6548
6549 bios->length = NV_PROM_SIZE;
6550 return true;
6551}
6552
6553static int nouveau_parse_vbios_struct(struct drm_device *dev)
6554{
6555 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6556 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6557 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6558 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6559 int offset;
6560
6561 offset = findstr(bios->data, bios->length,
6562 bit_signature, sizeof(bit_signature));
6563 if (offset) {
6564 NV_TRACE(dev, "BIT BIOS found\n");
4709bff0
BS		 6565 bios->type = NVBIOS_BIT;
6566 bios->offset = offset;
6ee73861
BS		 6567 return parse_bit_structure(bios, offset + 6);
6568 }
6569
6570 offset = findstr(bios->data, bios->length,
6571 bmp_signature, sizeof(bmp_signature));
6572 if (offset) {
6573 NV_TRACE(dev, "BMP BIOS found\n");
4709bff0
BS		 6574 bios->type = NVBIOS_BMP;
6575 bios->offset = offset;
6ee73861
BS		 6576 return parse_bmp_structure(dev, bios, offset);
6577 }
6578
6579 NV_ERROR(dev, "No known BIOS signature found\n");
6580 return -ENODEV;
6581}
6582
6583int
6584nouveau_run_vbios_init(struct drm_device *dev)
6585{
6586 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6587 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6588 int i, ret = 0;
6589
946fd35f
FJ		 6590 /* Reset the BIOS head to 0. */
6591 bios->state.crtchead = 0;
6ee73861
BS		 6592
6593 if (bios->major_version < 5) /* BMP only */
6594 load_nv17_hw_sequencer_ucode(dev, bios);
6595
6596 if (bios->execute) {
6597 bios->fp.last_script_invoc = 0;
6598 bios->fp.lvds_init_run = false;
6599 }
6600
6601 parse_init_tables(bios);
6602
6603 /*
6604 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6605 * parser will run this right after the init tables, the binary
6606 * driver appears to run it at some point later.
6607 */
6608 if (bios->some_script_ptr) {
6609 struct init_exec iexec = {true, false};
6610
6611 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6612 bios->some_script_ptr);
6613 parse_init_table(bios, bios->some_script_ptr, &iexec);
6614 }
6615
6616 if (dev_priv->card_type >= NV_50) {
7f245b20 6617 for (i = 0; i < bios->dcb.entries; i++) {
02e4f587
BS		 6618 nouveau_bios_run_display_table(dev, 0, 0,
6619 &bios->dcb.entry[i], -1);
6ee73861
BS		 6620 }
6621 }
6622
6ee73861
BS		 6623 return ret;
6624}
6625
d13102c6
BS		 6626static bool
6627nouveau_bios_posted(struct drm_device *dev)
6628{
6629 struct drm_nouveau_private *dev_priv = dev->dev_private;
d13102c6
BS		 6630 unsigned htotal;
6631
c1b60ece 6632 if (dev_priv->card_type >= NV_50) {
d13102c6
BS		 6633 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6634 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6635 return false;
6636 return true;
6637 }
6638
d13102c6
BS		 6639 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6640 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6641 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6642 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6643 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
03cd06ca 6644
d13102c6
BS		 6645 return (htotal != 0);
6646}
6647
6ee73861
BS		 6648int
6649nouveau_bios_init(struct drm_device *dev)
6650{
6651 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6652 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6653 int ret;
6654
6ee73861
BS		 6655 if (!NVInitVBIOS(dev))
6656 return -ENODEV;
6657
6658 ret = nouveau_parse_vbios_struct(dev);
6659 if (ret)
6660 return ret;
6661
486a45c2
BS		 6662 ret = nouveau_i2c_init(dev);
6663 if (ret)
6664 return ret;
6665
2e5702af 6666 ret = parse_dcb_table(dev, bios);
6ee73861
BS		 6667 if (ret)
6668 return ret;
6669
6ee73861
BS		 6670 if (!bios->major_version) /* we don't run version 0 bios */
6671 return 0;
6672
6ee73861
BS		 6673 /* init script execution disabled */
6674 bios->execute = false;
6675
6676 /* ... unless card isn't POSTed already */
d13102c6 6677 if (!nouveau_bios_posted(dev)) {
67eda20e
FJ		 6678 NV_INFO(dev, "Adaptor not initialised, "
6679 "running VBIOS init tables.\n");
6ee73861
BS		 6680 bios->execute = true;
6681 }
0cba1b76
MK		 6682 if (nouveau_force_post)
6683 bios->execute = true;
6ee73861 6684
6ee73861 6685 ret = nouveau_run_vbios_init(dev);
04a39c57 6686 if (ret)
6ee73861 6687 return ret;
6ee73861
BS		 6688
6689 /* feature_byte on BMP is poor, but init always sets CR4B */
6ee73861
BS		 6690 if (bios->major_version < 5)
6691 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6692
6693 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6694 if (bios->is_mobile || bios->major_version >= 5)
6695 ret = parse_fp_mode_table(dev, bios);
6ee73861
BS		 6696
6697 /* allow subsequent scripts to execute */
6698 bios->execute = true;
6699
6700 return 0;
6701}
6702
6703void
6704nouveau_bios_takedown(struct drm_device *dev)
6705{
486a45c2 6706 nouveau_i2c_fini(dev);
6ee73861 6707}