projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/nouveau: log if accel is disabled by default on a chipset
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861 30
67eda20e
FJ		 31#include <linux/io-mapping.h>
32
6ee73861
BS		 33/* these defines are made up */
34#define NV_CIO_CRE_44_HEADA 0x0
35#define NV_CIO_CRE_44_HEADB 0x3
36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
37#define LEGACY_I2C_CRT 0x80
38#define LEGACY_I2C_PANEL 0x81
39#define LEGACY_I2C_TV 0x82
40
41#define EDID1_LEN 128
42
43#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
44#define LOG_OLD_VALUE(x)
45
6ee73861
BS		 46struct init_exec {
47 bool execute;
48 bool repeat;
49};
50
51static bool nv_cksum(const uint8_t *data, unsigned int length)
52{
53 /*
54 * There's a few checksums in the BIOS, so here's a generic checking
55 * function.
56 */
57 int i;
58 uint8_t sum = 0;
59
60 for (i = 0; i < length; i++)
61 sum += data[i];
62
63 if (sum)
64 return true;
65
66 return false;
67}
68
69static int
70score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
71{
72 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
73 NV_TRACEWARN(dev, "... BIOS signature not found\n");
74 return 0;
75 }
76
77 if (nv_cksum(data, data[2] * 512)) {
78 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
79 /* if a ro image is somewhat bad, it's probably all rubbish */
80 return writeable ? 2 : 1;
81 } else
82 NV_TRACE(dev, "... appears to be valid\n");
83
84 return 3;
85}
86
87static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
88{
89 struct drm_nouveau_private *dev_priv = dev->dev_private;
90 uint32_t pci_nv_20, save_pci_nv_20;
91 int pcir_ptr;
92 int i;
93
94 if (dev_priv->card_type >= NV_50)
95 pci_nv_20 = 0x88050;
96 else
97 pci_nv_20 = NV_PBUS_PCI_NV_20;
98
99 /* enable ROM access */
100 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
101 nvWriteMC(dev, pci_nv_20,
102 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
103
104 /* bail if no rom signature */
105 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
106 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
107 goto out;
108
109 /* additional check (see note below) - read PCI record header */
110 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
111 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
112 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
113 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
114 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
115 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
116 goto out;
117
118 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
119 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
120 * each byte. we'll hope pramin has something usable instead
121 */
122 for (i = 0; i < NV_PROM_SIZE; i++)
123 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
124
125out:
126 /* disable ROM access */
127 nvWriteMC(dev, pci_nv_20,
128 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
129}
130
131static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
132{
133 struct drm_nouveau_private *dev_priv = dev->dev_private;
134 uint32_t old_bar0_pramin = 0;
135 int i;
136
137 if (dev_priv->card_type >= NV_50) {
138 uint32_t vbios_vram = (nv_rd32(dev, 0x619f04) & ~0xff) << 8;
139
140 if (!vbios_vram)
141 vbios_vram = (nv_rd32(dev, 0x1700) << 16) + 0xf0000;
142
143 old_bar0_pramin = nv_rd32(dev, 0x1700);
144 nv_wr32(dev, 0x1700, vbios_vram >> 16);
145 }
146
147 /* bail if no rom signature */
148 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
149 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
150 goto out;
151
152 for (i = 0; i < NV_PROM_SIZE; i++)
153 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
154
155out:
156 if (dev_priv->card_type >= NV_50)
157 nv_wr32(dev, 0x1700, old_bar0_pramin);
158}
159
160static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
161{
162 void __iomem *rom = NULL;
163 size_t rom_len;
164 int ret;
165
166 ret = pci_enable_rom(dev->pdev);
167 if (ret)
168 return;
169
170 rom = pci_map_rom(dev->pdev, &rom_len);
171 if (!rom)
172 goto out;
173 memcpy_fromio(data, rom, rom_len);
174 pci_unmap_rom(dev->pdev, rom);
175
176out:
177 pci_disable_rom(dev->pdev);
178}
179
afeb3e11
DA		 180static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
181{
182 int i;
183 int ret;
184 int size = 64 * 1024;
185
186 if (!nouveau_acpi_rom_supported(dev->pdev))
187 return;
188
189 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
190 ret = nouveau_acpi_get_bios_chunk(data,
191 (i * ROM_BIOS_PAGE),
192 ROM_BIOS_PAGE);
193 if (ret <= 0)
194 break;
195 }
196 return;
197}
198
6ee73861
BS		 199struct methods {
200 const char desc[8];
201 void (*loadbios)(struct drm_device *, uint8_t *);
202 const bool rw;
6ee73861
BS		 203};
204
41090eb4 205static struct methods shadow_methods[] = {
6ee73861
BS		 206 { "PRAMIN", load_vbios_pramin, true },
207 { "PROM", load_vbios_prom, false },
208 { "PCIROM", load_vbios_pci, true },
41090eb4 209 { "ACPI", load_vbios_acpi, true },
6ee73861 210};
eae6192a 211#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
6ee73861
BS		 212
213static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
214{
41090eb4 215 struct methods *methods = shadow_methods;
6ee73861 216 int testscore = 3;
eae6192a 217 int scores[NUM_SHADOW_METHODS], i;
6ee73861
BS		 218
219 if (nouveau_vbios) {
eae6192a 220 for (i = 0; i < NUM_SHADOW_METHODS; i++)
657b6245 221 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 222 break;
6ee73861 223
eae6192a 224 if (i < NUM_SHADOW_METHODS) {
6ee73861 225 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 226 methods[i].desc);
6ee73861 227
657b6245
MK		 228 methods[i].loadbios(dev, data);
229 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 230 return true;
231 }
232
233 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
234 }
235
eae6192a 236 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
6ee73861 237 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 238 methods[i].desc);
6ee73861 239 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 240 methods[i].loadbios(dev, data);
241 scores[i] = score_vbios(dev, data, methods[i].rw);
242 if (scores[i] == testscore)
6ee73861 243 return true;
6ee73861
BS		 244 }
245
246 while (--testscore > 0) {
eae6192a 247 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
657b6245 248 if (scores[i] == testscore) {
6ee73861 249 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 250 methods[i].desc);
251 methods[i].loadbios(dev, data);
6ee73861
BS		 252 return true;
253 }
6ee73861
BS		 254 }
255 }
256
257 NV_ERROR(dev, "No valid BIOS image found\n");
258 return false;
259}
260
261struct init_tbl_entry {
262 char *name;
263 uint8_t id;
9170a824
BS		 264 /* Return:
265 * > 0: success, length of opcode
266 * 0: success, but abort further parsing of table (INIT_DONE etc)
267 * < 0: failure, table parsing will be aborted
268 */
37383650 269 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 270};
271
ec64a408 272static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 273
274#define MACRO_INDEX_SIZE 2
275#define MACRO_SIZE 8
276#define CONDITION_SIZE 12
277#define IO_FLAG_CONDITION_SIZE 9
278#define IO_CONDITION_SIZE 5
279#define MEM_INIT_SIZE 66
280
281static void still_alive(void)
282{
283#if 0
284 sync();
c7ca4d1b 285 mdelay(2);
6ee73861
BS		 286#endif
287}
288
289static uint32_t
290munge_reg(struct nvbios *bios, uint32_t reg)
291{
292 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
293 struct dcb_entry *dcbent = bios->display.output;
294
295 if (dev_priv->card_type < NV_50)
296 return reg;
297
298 if (reg & 0x40000000) {
299 BUG_ON(!dcbent);
300
301 reg += (ffs(dcbent->or) - 1) * 0x800;
302 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
303 reg += 0x00000080;
304 }
305
306 reg &= ~0x60000000;
307 return reg;
308}
309
310static int
311valid_reg(struct nvbios *bios, uint32_t reg)
312{
313 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
314 struct drm_device *dev = bios->dev;
315
316 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 317 if (reg & 0x2 ||
04a39c57 318 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 319 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
320
321 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 322 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 323 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
324 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
325 reg);
326
9855e584
BS		 327 if (reg >= (8*1024*1024)) {
328 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
329 return 0;
6ee73861 330 }
9855e584
BS		 331
332 return 1;
6ee73861
BS		 333}
334
335static bool
336valid_idx_port(struct nvbios *bios, uint16_t port)
337{
338 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
339 struct drm_device *dev = bios->dev;
340
341 /*
342 * If adding more ports here, the read/write functions below will need
343 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
344 * used for the port in question
345 */
346 if (dev_priv->card_type < NV_50) {
347 if (port == NV_CIO_CRX__COLOR)
348 return true;
349 if (port == NV_VIO_SRX)
350 return true;
351 } else {
352 if (port == NV_CIO_CRX__COLOR)
353 return true;
354 }
355
356 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
357 port);
358
359 return false;
360}
361
362static bool
363valid_port(struct nvbios *bios, uint16_t port)
364{
365 struct drm_device *dev = bios->dev;
366
367 /*
368 * If adding more ports here, the read/write functions below will need
369 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
370 * used for the port in question
371 */
372 if (port == NV_VIO_VSE2)
373 return true;
374
375 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
376
377 return false;
378}
379
380static uint32_t
381bios_rd32(struct nvbios *bios, uint32_t reg)
382{
383 uint32_t data;
384
385 reg = munge_reg(bios, reg);
386 if (!valid_reg(bios, reg))
387 return 0;
388
389 /*
390 * C51 sometimes uses regs with bit0 set in the address. For these
391 * cases there should exist a translation in a BIOS table to an IO
392 * port address which the BIOS uses for accessing the reg
393 *
394 * These only seem to appear for the power control regs to a flat panel,
395 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
396 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
397 * suspend-resume mmio trace from a C51 will be required to see if this
398 * is true for the power microcode in 0x14.., or whether the direct IO
399 * port access method is needed
400 */
401 if (reg & 0x1)
402 reg &= ~0x1;
403
404 data = nv_rd32(bios->dev, reg);
405
406 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
407
408 return data;
409}
410
411static void
412bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
413{
414 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
415
416 reg = munge_reg(bios, reg);
417 if (!valid_reg(bios, reg))
418 return;
419
420 /* see note in bios_rd32 */
421 if (reg & 0x1)
422 reg &= 0xfffffffe;
423
424 LOG_OLD_VALUE(bios_rd32(bios, reg));
425 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
426
04a39c57 427 if (dev_priv->vbios.execute) {
6ee73861
BS		 428 still_alive();
429 nv_wr32(bios->dev, reg, data);
430 }
431}
432
433static uint8_t
434bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
435{
436 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
437 struct drm_device *dev = bios->dev;
438 uint8_t data;
439
440 if (!valid_idx_port(bios, port))
441 return 0;
442
443 if (dev_priv->card_type < NV_50) {
444 if (port == NV_VIO_SRX)
445 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
446 else /* assume NV_CIO_CRX__COLOR */
447 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
448 } else {
449 uint32_t data32;
450
451 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
452 data = (data32 >> ((index & 3) << 3)) & 0xff;
453 }
454
455 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
456 "Head: 0x%02X, Data: 0x%02X\n",
457 port, index, bios->state.crtchead, data);
458 return data;
459}
460
461static void
462bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
463{
464 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
465 struct drm_device *dev = bios->dev;
466
467 if (!valid_idx_port(bios, port))
468 return;
469
470 /*
471 * The current head is maintained in the nvbios member state.crtchead.
472 * We trap changes to CR44 and update the head variable and hence the
473 * register set written.
474 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
475 * of the write, and to head1 after the write
476 */
477 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
478 data != NV_CIO_CRE_44_HEADB)
479 bios->state.crtchead = 0;
480
481 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
482 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
483 "Head: 0x%02X, Data: 0x%02X\n",
484 port, index, bios->state.crtchead, data);
485
486 if (bios->execute && dev_priv->card_type < NV_50) {
487 still_alive();
488 if (port == NV_VIO_SRX)
489 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
490 else /* assume NV_CIO_CRX__COLOR */
491 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
492 } else
493 if (bios->execute) {
494 uint32_t data32, shift = (index & 3) << 3;
495
496 still_alive();
497
498 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
499 data32 &= ~(0xff << shift);
500 data32 |= (data << shift);
501 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
502 }
503
504 if (port == NV_CIO_CRX__COLOR &&
505 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
506 bios->state.crtchead = 1;
507}
508
509static uint8_t
510bios_port_rd(struct nvbios *bios, uint16_t port)
511{
512 uint8_t data, head = bios->state.crtchead;
513
514 if (!valid_port(bios, port))
515 return 0;
516
517 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
518
519 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
520 port, head, data);
521
522 return data;
523}
524
525static void
526bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
527{
528 int head = bios->state.crtchead;
529
530 if (!valid_port(bios, port))
531 return;
532
533 LOG_OLD_VALUE(bios_port_rd(bios, port));
534 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
535 port, head, data);
536
537 if (!bios->execute)
538 return;
539
540 still_alive();
541 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
542}
543
544static bool
545io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
546{
547 /*
548 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
549 * for the CRTC index; 1 byte for the mask to apply to the value
550 * retrieved from the CRTC; 1 byte for the shift right to apply to the
551 * masked CRTC value; 2 bytes for the offset to the flag array, to
552 * which the shifted value is added; 1 byte for the mask applied to the
553 * value read from the flag array; and 1 byte for the value to compare
554 * against the masked byte from the flag table.
555 */
556
557 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
558 uint16_t crtcport = ROM16(bios->data[condptr]);
559 uint8_t crtcindex = bios->data[condptr + 2];
560 uint8_t mask = bios->data[condptr + 3];
561 uint8_t shift = bios->data[condptr + 4];
562 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
563 uint8_t flagarraymask = bios->data[condptr + 7];
564 uint8_t cmpval = bios->data[condptr + 8];
565 uint8_t data;
566
567 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
568 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
569 "Cmpval: 0x%02X\n",
570 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
571
572 data = bios_idxprt_rd(bios, crtcport, crtcindex);
573
574 data = bios->data[flagarray + ((data & mask) >> shift)];
575 data &= flagarraymask;
576
577 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
578 offset, data, cmpval);
579
580 return (data == cmpval);
581}
582
583static bool
584bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
585{
586 /*
587 * The condition table entry has 4 bytes for the address of the
588 * register to check, 4 bytes for a mask to apply to the register and
589 * 4 for a test comparison value
590 */
591
592 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
593 uint32_t reg = ROM32(bios->data[condptr]);
594 uint32_t mask = ROM32(bios->data[condptr + 4]);
595 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
596 uint32_t data;
597
598 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
599 offset, cond, reg, mask);
600
601 data = bios_rd32(bios, reg) & mask;
602
603 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
604 offset, data, cmpval);
605
606 return (data == cmpval);
607}
608
609static bool
610io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
611{
612 /*
613 * The IO condition entry has 2 bytes for the IO port address; 1 byte
614 * for the index to write to io_port; 1 byte for the mask to apply to
615 * the byte read from io_port+1; and 1 byte for the value to compare
616 * against the masked byte.
617 */
618
619 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
620 uint16_t io_port = ROM16(bios->data[condptr]);
621 uint8_t port_index = bios->data[condptr + 2];
622 uint8_t mask = bios->data[condptr + 3];
623 uint8_t cmpval = bios->data[condptr + 4];
624
625 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
626
627 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
628 offset, data, cmpval);
629
630 return (data == cmpval);
631}
632
633static int
634nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
635{
636 struct drm_nouveau_private *dev_priv = dev->dev_private;
637 uint32_t reg0 = nv_rd32(dev, reg + 0);
638 uint32_t reg1 = nv_rd32(dev, reg + 4);
639 struct nouveau_pll_vals pll;
640 struct pll_lims pll_limits;
641 int ret;
642
643 ret = get_pll_limits(dev, reg, &pll_limits);
644 if (ret)
645 return ret;
646
647 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
648 if (!clk)
649 return -ERANGE;
650
651 reg0 = (reg0 & 0xfff8ffff) | (pll.log2P << 16);
652 reg1 = (reg1 & 0xffff0000) | (pll.N1 << 8) | pll.M1;
653
04a39c57 654 if (dev_priv->vbios.execute) {
6ee73861
BS		 655 still_alive();
656 nv_wr32(dev, reg + 4, reg1);
657 nv_wr32(dev, reg + 0, reg0);
658 }
659
660 return 0;
661}
662
663static int
664setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
665{
666 struct drm_device *dev = bios->dev;
667 struct drm_nouveau_private *dev_priv = dev->dev_private;
668 /* clk in kHz */
669 struct pll_lims pll_lim;
670 struct nouveau_pll_vals pllvals;
671 int ret;
672
673 if (dev_priv->card_type >= NV_50)
674 return nv50_pll_set(dev, reg, clk);
675
676 /* high regs (such as in the mac g5 table) are not -= 4 */
677 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
678 if (ret)
679 return ret;
680
681 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
682 if (!clk)
683 return -ERANGE;
684
685 if (bios->execute) {
686 still_alive();
687 nouveau_hw_setpll(dev, reg, &pllvals);
688 }
689
690 return 0;
691}
692
693static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
694{
695 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 696 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 697
698 /*
699 * For the results of this function to be correct, CR44 must have been
700 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
701 * and the DCB table parsed, before the script calling the function is
702 * run. run_digital_op_script is example of how to do such setup
703 */
704
705 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
706
7f245b20 707 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 708 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
709 "(%02X)\n", dcb_entry);
710 dcb_entry = 0x7f; /* unused / invalid marker */
711 }
712
713 return dcb_entry;
714}
715
f8b0be1a
BS		 716static int
717read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
718{
719 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
720 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
721 int recordoffset = 0, rdofs = 1, wrofs = 0;
722 uint8_t port_type = 0;
723
724 if (!i2ctable)
725 return -EINVAL;
726
727 if (dcb_version >= 0x30) {
728 if (i2ctable[0] != dcb_version) /* necessary? */
729 NV_WARN(dev,
730 "DCB I2C table version mismatch (%02X vs %02X)\n",
731 i2ctable[0], dcb_version);
732 dcb_i2c_ver = i2ctable[0];
733 headerlen = i2ctable[1];
734 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
735 i2c_entries = i2ctable[2];
736 else
737 NV_WARN(dev,
738 "DCB I2C table has more entries than indexable "
739 "(%d entries, max %d)\n", i2ctable[2],
740 DCB_MAX_NUM_I2C_ENTRIES);
741 entry_len = i2ctable[3];
742 /* [4] is i2c_default_indices, read in parse_dcb_table() */
743 }
744 /*
745 * It's your own fault if you call this function on a DCB 1.1 BIOS --
746 * the test below is for DCB 1.2
747 */
748 if (dcb_version < 0x14) {
749 recordoffset = 2;
750 rdofs = 0;
751 wrofs = 1;
752 }
753
754 if (index == 0xf)
755 return 0;
756 if (index >= i2c_entries) {
757 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
758 index, i2ctable[2]);
759 return -ENOENT;
760 }
761 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
762 NV_ERROR(dev, "DCB I2C entry invalid\n");
763 return -EINVAL;
764 }
765
766 if (dcb_i2c_ver >= 0x30) {
767 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
768
769 /*
770 * Fixup for chips using same address offset for read and
771 * write.
772 */
773 if (port_type == 4) /* seen on C51 */
774 rdofs = wrofs = 1;
775 if (port_type >= 5) /* G80+ */
776 rdofs = wrofs = 0;
777 }
778
779 if (dcb_i2c_ver >= 0x40) {
780 if (port_type != 5 && port_type != 6)
781 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
782
783 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
784 }
785
786 i2c->port_type = port_type;
787 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
788 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
789
790 return 0;
791}
792
6ee73861
BS		 793static struct nouveau_i2c_chan *
794init_i2c_device_find(struct drm_device *dev, int i2c_index)
795{
796 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 797 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 798
799 if (i2c_index == 0xff) {
800 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
801 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 802 int default_indices = dcb->i2c_default_indices;
6ee73861 803
7f245b20 804 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 805 shift = 4;
806
807 i2c_index = (default_indices >> shift) & 0xf;
808 }
809 if (i2c_index == 0x80) /* g80+ */
7f245b20 810 i2c_index = dcb->i2c_default_indices & 0xf;
04f542c0
BS		 811 else
812 if (i2c_index == 0x81)
813 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
6ee73861 814
75047944 815 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
f8b0be1a
BS		 816 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
817 return NULL;
818 }
819
820 /* Make sure i2c table entry has been parsed, it may not
821 * have been if this is a bus not referenced by a DCB encoder
822 */
823 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
824 i2c_index, &dcb->i2c[i2c_index]);
825
6ee73861
BS		 826 return nouveau_i2c_find(dev, i2c_index);
827}
828
7f245b20
BS		 829static uint32_t
830get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 831{
832 /*
833 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
834 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
835 * CR58 for CR57 = 0 to index a table of offsets to the basic
836 * 0x6808b0 address.
837 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
838 * CR58 for CR57 = 0 to index a table of offsets to the basic
839 * 0x6808b0 address, and then flip the offset by 8.
840 */
841
842 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 843 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 844 const int pramdac_offset[13] = {
845 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
846 const uint32_t pramdac_table[4] = {
847 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
848
849 if (mlv >= 0x80) {
850 int dcb_entry, dacoffset;
851
852 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
853 dcb_entry = dcb_entry_idx_from_crtchead(dev);
854 if (dcb_entry == 0x7f)
855 return 0;
7f245b20 856 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 857 if (mlv == 0x81)
858 dacoffset ^= 8;
859 return 0x6808b0 + dacoffset;
860 } else {
df31ef4d 861 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 862 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
863 mlv);
864 return 0;
865 }
866 return pramdac_table[mlv];
867 }
868}
869
37383650 870static int
6ee73861
BS		 871init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
872 struct init_exec *iexec)
873{
874 /*
875 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
876 *
877 * offset (8 bit): opcode
878 * offset + 1 (16 bit): CRTC port
879 * offset + 3 (8 bit): CRTC index
880 * offset + 4 (8 bit): mask
881 * offset + 5 (8 bit): shift
882 * offset + 6 (8 bit): count
883 * offset + 7 (32 bit): register
884 * offset + 11 (32 bit): configuration 1
885 * ...
886 *
887 * Starting at offset + 11 there are "count" 32 bit values.
888 * To find out which value to use read index "CRTC index" on "CRTC
889 * port", AND this value with "mask" and then bit shift right "shift"
890 * bits. Read the appropriate value using this index and write to
891 * "register"
892 */
893
894 uint16_t crtcport = ROM16(bios->data[offset + 1]);
895 uint8_t crtcindex = bios->data[offset + 3];
896 uint8_t mask = bios->data[offset + 4];
897 uint8_t shift = bios->data[offset + 5];
898 uint8_t count = bios->data[offset + 6];
899 uint32_t reg = ROM32(bios->data[offset + 7]);
900 uint8_t config;
901 uint32_t configval;
37383650 902 int len = 11 + count * 4;
6ee73861
BS		 903
904 if (!iexec->execute)
37383650 905 return len;
6ee73861
BS		 906
907 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
908 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
909 offset, crtcport, crtcindex, mask, shift, count, reg);
910
911 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
912 if (config > count) {
913 NV_ERROR(bios->dev,
914 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
915 offset, config, count);
309b8c89 916 return len;
6ee73861
BS		 917 }
918
919 configval = ROM32(bios->data[offset + 11 + config * 4]);
920
921 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
922
923 bios_wr32(bios, reg, configval);
924
37383650 925 return len;
6ee73861
BS		 926}
927
37383650 928static int
6ee73861
BS		 929init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
930{
931 /*
932 * INIT_REPEAT opcode: 0x33 ('3')
933 *
934 * offset (8 bit): opcode
935 * offset + 1 (8 bit): count
936 *
937 * Execute script following this opcode up to INIT_REPEAT_END
938 * "count" times
939 */
940
941 uint8_t count = bios->data[offset + 1];
942 uint8_t i;
943
944 /* no iexec->execute check by design */
945
946 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
947 offset, count);
948
949 iexec->repeat = true;
950
951 /*
952 * count - 1, as the script block will execute once when we leave this
953 * opcode -- this is compatible with bios behaviour as:
954 * a) the block is always executed at least once, even if count == 0
955 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
956 * while we don't
957 */
958 for (i = 0; i < count - 1; i++)
959 parse_init_table(bios, offset + 2, iexec);
960
961 iexec->repeat = false;
962
37383650 963 return 2;
6ee73861
BS		 964}
965
37383650 966static int
6ee73861
BS		 967init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
968 struct init_exec *iexec)
969{
970 /*
971 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
972 *
973 * offset (8 bit): opcode
974 * offset + 1 (16 bit): CRTC port
975 * offset + 3 (8 bit): CRTC index
976 * offset + 4 (8 bit): mask
977 * offset + 5 (8 bit): shift
978 * offset + 6 (8 bit): IO flag condition index
979 * offset + 7 (8 bit): count
980 * offset + 8 (32 bit): register
981 * offset + 12 (16 bit): frequency 1
982 * ...
983 *
984 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
985 * Set PLL register "register" to coefficients for frequency n,
986 * selected by reading index "CRTC index" of "CRTC port" ANDed with
987 * "mask" and shifted right by "shift".
988 *
989 * If "IO flag condition index" > 0, and condition met, double
990 * frequency before setting it.
991 */
992
993 uint16_t crtcport = ROM16(bios->data[offset + 1]);
994 uint8_t crtcindex = bios->data[offset + 3];
995 uint8_t mask = bios->data[offset + 4];
996 uint8_t shift = bios->data[offset + 5];
997 int8_t io_flag_condition_idx = bios->data[offset + 6];
998 uint8_t count = bios->data[offset + 7];
999 uint32_t reg = ROM32(bios->data[offset + 8]);
1000 uint8_t config;
1001 uint16_t freq;
37383650 1002 int len = 12 + count * 2;
6ee73861
BS		 1003
1004 if (!iexec->execute)
37383650 1005 return len;
6ee73861
BS		 1006
1007 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1008 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1009 "Count: 0x%02X, Reg: 0x%08X\n",
1010 offset, crtcport, crtcindex, mask, shift,
1011 io_flag_condition_idx, count, reg);
1012
1013 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1014 if (config > count) {
1015 NV_ERROR(bios->dev,
1016 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1017 offset, config, count);
309b8c89 1018 return len;
6ee73861
BS		 1019 }
1020
1021 freq = ROM16(bios->data[offset + 12 + config * 2]);
1022
1023 if (io_flag_condition_idx > 0) {
1024 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1025 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1026 "frequency doubled\n", offset);
1027 freq *= 2;
1028 } else
1029 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1030 "frequency unchanged\n", offset);
1031 }
1032
1033 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1034 offset, reg, config, freq);
1035
1036 setPLL(bios, reg, freq * 10);
1037
37383650 1038 return len;
6ee73861
BS		 1039}
1040
37383650 1041static int
6ee73861
BS		 1042init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1043{
1044 /*
1045 * INIT_END_REPEAT opcode: 0x36 ('6')
1046 *
1047 * offset (8 bit): opcode
1048 *
1049 * Marks the end of the block for INIT_REPEAT to repeat
1050 */
1051
1052 /* no iexec->execute check by design */
1053
1054 /*
1055 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1056 * we're not in repeat mode
1057 */
1058 if (iexec->repeat)
37383650 1059 return 0;
6ee73861 1060
37383650 1061 return 1;
6ee73861
BS		 1062}
1063
37383650 1064static int
6ee73861
BS		 1065init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1066{
1067 /*
1068 * INIT_COPY opcode: 0x37 ('7')
1069 *
1070 * offset (8 bit): opcode
1071 * offset + 1 (32 bit): register
1072 * offset + 5 (8 bit): shift
1073 * offset + 6 (8 bit): srcmask
1074 * offset + 7 (16 bit): CRTC port
1075 * offset + 9 (8 bit): CRTC index
1076 * offset + 10 (8 bit): mask
1077 *
1078 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1079 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1080 * port
1081 */
1082
1083 uint32_t reg = ROM32(bios->data[offset + 1]);
1084 uint8_t shift = bios->data[offset + 5];
1085 uint8_t srcmask = bios->data[offset + 6];
1086 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1087 uint8_t crtcindex = bios->data[offset + 9];
1088 uint8_t mask = bios->data[offset + 10];
1089 uint32_t data;
1090 uint8_t crtcdata;
1091
1092 if (!iexec->execute)
37383650 1093 return 11;
6ee73861
BS		 1094
1095 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1096 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1097 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1098
1099 data = bios_rd32(bios, reg);
1100
1101 if (shift < 0x80)
1102 data >>= shift;
1103 else
1104 data <<= (0x100 - shift);
1105
1106 data &= srcmask;
1107
1108 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1109 crtcdata |= (uint8_t)data;
1110 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1111
37383650 1112 return 11;
6ee73861
BS		 1113}
1114
37383650 1115static int
6ee73861
BS		 1116init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1117{
1118 /*
1119 * INIT_NOT opcode: 0x38 ('8')
1120 *
1121 * offset (8 bit): opcode
1122 *
1123 * Invert the current execute / no-execute condition (i.e. "else")
1124 */
1125 if (iexec->execute)
1126 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1127 else
1128 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1129
1130 iexec->execute = !iexec->execute;
37383650 1131 return 1;
6ee73861
BS		 1132}
1133
37383650 1134static int
6ee73861
BS		 1135init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1136 struct init_exec *iexec)
1137{
1138 /*
1139 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1140 *
1141 * offset (8 bit): opcode
1142 * offset + 1 (8 bit): condition number
1143 *
1144 * Check condition "condition number" in the IO flag condition table.
1145 * If condition not met skip subsequent opcodes until condition is
1146 * inverted (INIT_NOT), or we hit INIT_RESUME
1147 */
1148
1149 uint8_t cond = bios->data[offset + 1];
1150
1151 if (!iexec->execute)
37383650 1152 return 2;
6ee73861
BS		 1153
1154 if (io_flag_condition_met(bios, offset, cond))
1155 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1156 else {
1157 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1158 iexec->execute = false;
1159 }
1160
37383650 1161 return 2;
6ee73861
BS		 1162}
1163
25908b77
BS		 1164static int
1165init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1166{
1167 /*
1168 * INIT_DP_CONDITION opcode: 0x3A ('')
1169 *
1170 * offset (8 bit): opcode
1171 * offset + 1 (8 bit): "sub" opcode
1172 * offset + 2 (8 bit): unknown
1173 *
1174 */
1175
1176 struct bit_displayport_encoder_table *dpe = NULL;
1177 struct dcb_entry *dcb = bios->display.output;
1178 struct drm_device *dev = bios->dev;
1179 uint8_t cond = bios->data[offset + 1];
1180 int dummy;
1181
1182 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1183
1184 if (!iexec->execute)
1185 return 3;
1186
1187 dpe = nouveau_bios_dp_table(dev, dcb, &dummy);
1188 if (!dpe) {
1189 NV_ERROR(dev, "0x%04X: INIT_3A: no encoder table!!\n", offset);
309b8c89 1190 return 3;
25908b77
BS		 1191 }
1192
1193 switch (cond) {
1194 case 0:
1195 {
1196 struct dcb_connector_table_entry *ent =
1197 &bios->dcb.connector.entry[dcb->connector];
1198
1199 if (ent->type != DCB_CONNECTOR_eDP)
1200 iexec->execute = false;
1201 }
1202 break;
1203 case 1:
1204 case 2:
1205 if (!(dpe->unknown & cond))
1206 iexec->execute = false;
1207 break;
1208 case 5:
1209 {
1210 struct nouveau_i2c_chan *auxch;
1211 int ret;
1212
1213 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
309b8c89
BS		 1214 if (!auxch) {
1215 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1216 return 3;
1217 }
25908b77
BS		 1218
1219 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
309b8c89
BS		 1220 if (ret) {
1221 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1222 return 3;
1223 }
25908b77 1224
64d202b4 1225 if (!(cond & 1))
25908b77
BS		 1226 iexec->execute = false;
1227 }
1228 break;
1229 default:
1230 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1231 break;
1232 }
1233
1234 if (iexec->execute)
1235 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1236 else
1237 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1238
1239 return 3;
1240}
1241
1242static int
1243init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1244{
1245 /*
1246 * INIT_3B opcode: 0x3B ('')
1247 *
1248 * offset (8 bit): opcode
1249 * offset + 1 (8 bit): crtc index
1250 *
1251 */
1252
1253 uint8_t or = ffs(bios->display.output->or) - 1;
1254 uint8_t index = bios->data[offset + 1];
1255 uint8_t data;
1256
1257 if (!iexec->execute)
1258 return 2;
1259
1260 data = bios_idxprt_rd(bios, 0x3d4, index);
1261 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1262 return 2;
1263}
1264
1265static int
1266init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1267{
1268 /*
1269 * INIT_3C opcode: 0x3C ('')
1270 *
1271 * offset (8 bit): opcode
1272 * offset + 1 (8 bit): crtc index
1273 *
1274 */
1275
1276 uint8_t or = ffs(bios->display.output->or) - 1;
1277 uint8_t index = bios->data[offset + 1];
1278 uint8_t data;
1279
1280 if (!iexec->execute)
1281 return 2;
1282
1283 data = bios_idxprt_rd(bios, 0x3d4, index);
1284 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1285 return 2;
1286}
1287
37383650 1288static int
6ee73861
BS		 1289init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1290 struct init_exec *iexec)
1291{
1292 /*
1293 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1294 *
1295 * offset (8 bit): opcode
1296 * offset + 1 (32 bit): control register
1297 * offset + 5 (32 bit): data register
1298 * offset + 9 (32 bit): mask
1299 * offset + 13 (32 bit): data
1300 * offset + 17 (8 bit): count
1301 * offset + 18 (8 bit): address 1
1302 * offset + 19 (8 bit): data 1
1303 * ...
1304 *
1305 * For each of "count" address and data pairs, write "data n" to
1306 * "data register", read the current value of "control register",
1307 * and write it back once ANDed with "mask", ORed with "data",
1308 * and ORed with "address n"
1309 */
1310
1311 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1312 uint32_t datareg = ROM32(bios->data[offset + 5]);
1313 uint32_t mask = ROM32(bios->data[offset + 9]);
1314 uint32_t data = ROM32(bios->data[offset + 13]);
1315 uint8_t count = bios->data[offset + 17];
37383650 1316 int len = 18 + count * 2;
6ee73861
BS		 1317 uint32_t value;
1318 int i;
1319
1320 if (!iexec->execute)
37383650 1321 return len;
6ee73861
BS		 1322
1323 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1324 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1325 offset, controlreg, datareg, mask, data, count);
1326
1327 for (i = 0; i < count; i++) {
1328 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1329 uint8_t instdata = bios->data[offset + 19 + i * 2];
1330
1331 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1332 offset, instaddress, instdata);
1333
1334 bios_wr32(bios, datareg, instdata);
1335 value = bios_rd32(bios, controlreg) & mask;
1336 value |= data;
1337 value |= instaddress;
1338 bios_wr32(bios, controlreg, value);
1339 }
1340
37383650 1341 return len;
6ee73861
BS		 1342}
1343
37383650 1344static int
6ee73861
BS		 1345init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1346 struct init_exec *iexec)
1347{
1348 /*
1349 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1350 *
1351 * offset (8 bit): opcode
1352 * offset + 1 (16 bit): CRTC port
1353 * offset + 3 (8 bit): CRTC index
1354 * offset + 4 (8 bit): mask
1355 * offset + 5 (8 bit): shift
1356 * offset + 6 (8 bit): count
1357 * offset + 7 (32 bit): register
1358 * offset + 11 (32 bit): frequency 1
1359 * ...
1360 *
1361 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1362 * Set PLL register "register" to coefficients for frequency n,
1363 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1364 * "mask" and shifted right by "shift".
1365 */
1366
1367 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1368 uint8_t crtcindex = bios->data[offset + 3];
1369 uint8_t mask = bios->data[offset + 4];
1370 uint8_t shift = bios->data[offset + 5];
1371 uint8_t count = bios->data[offset + 6];
1372 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1373 int len = 11 + count * 4;
6ee73861
BS		 1374 uint8_t config;
1375 uint32_t freq;
1376
1377 if (!iexec->execute)
37383650 1378 return len;
6ee73861
BS		 1379
1380 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1381 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1382 offset, crtcport, crtcindex, mask, shift, count, reg);
1383
1384 if (!reg)
37383650 1385 return len;
6ee73861
BS		 1386
1387 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1388 if (config > count) {
1389 NV_ERROR(bios->dev,
1390 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1391 offset, config, count);
309b8c89 1392 return len;
6ee73861
BS		 1393 }
1394
1395 freq = ROM32(bios->data[offset + 11 + config * 4]);
1396
1397 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1398 offset, reg, config, freq);
1399
1400 setPLL(bios, reg, freq);
1401
37383650 1402 return len;
6ee73861
BS		 1403}
1404
37383650 1405static int
6ee73861
BS		 1406init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1407{
1408 /*
1409 * INIT_PLL2 opcode: 0x4B ('K')
1410 *
1411 * offset (8 bit): opcode
1412 * offset + 1 (32 bit): register
1413 * offset + 5 (32 bit): freq
1414 *
1415 * Set PLL register "register" to coefficients for frequency "freq"
1416 */
1417
1418 uint32_t reg = ROM32(bios->data[offset + 1]);
1419 uint32_t freq = ROM32(bios->data[offset + 5]);
1420
1421 if (!iexec->execute)
37383650 1422 return 9;
6ee73861
BS		 1423
1424 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1425 offset, reg, freq);
1426
1427 setPLL(bios, reg, freq);
37383650 1428 return 9;
6ee73861
BS		 1429}
1430
37383650 1431static int
6ee73861
BS		 1432init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1433{
1434 /*
1435 * INIT_I2C_BYTE opcode: 0x4C ('L')
1436 *
1437 * offset (8 bit): opcode
1438 * offset + 1 (8 bit): DCB I2C table entry index
1439 * offset + 2 (8 bit): I2C slave address
1440 * offset + 3 (8 bit): count
1441 * offset + 4 (8 bit): I2C register 1
1442 * offset + 5 (8 bit): mask 1
1443 * offset + 6 (8 bit): data 1
1444 * ...
1445 *
1446 * For each of "count" registers given by "I2C register n" on the device
1447 * addressed by "I2C slave address" on the I2C bus given by
1448 * "DCB I2C table entry index", read the register, AND the result with
1449 * "mask n" and OR it with "data n" before writing it back to the device
1450 */
1451
309b8c89 1452 struct drm_device *dev = bios->dev;
6ee73861 1453 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1454 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1455 uint8_t count = bios->data[offset + 3];
1456 struct nouveau_i2c_chan *chan;
893887ed
BS		 1457 int len = 4 + count * 3;
1458 int ret, i;
6ee73861
BS		 1459
1460 if (!iexec->execute)
37383650 1461 return len;
6ee73861
BS		 1462
1463 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1464 "Count: 0x%02X\n",
1465 offset, i2c_index, i2c_address, count);
1466
309b8c89
BS		 1467 chan = init_i2c_device_find(dev, i2c_index);
1468 if (!chan) {
1469 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1470 return len;
1471 }
6ee73861
BS		 1472
1473 for (i = 0; i < count; i++) {
893887ed 1474 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1475 uint8_t mask = bios->data[offset + 5 + i * 3];
1476 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1477 union i2c_smbus_data val;
6ee73861 1478
893887ed
BS		 1479 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1480 I2C_SMBUS_READ, reg,
1481 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1482 if (ret < 0) {
1483 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1484 return len;
1485 }
6ee73861
BS		 1486
1487 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1488 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1489 offset, reg, val.byte, mask, data);
6ee73861 1490
893887ed
BS		 1491 if (!bios->execute)
1492 continue;
6ee73861 1493
893887ed
BS		 1494 val.byte &= mask;
1495 val.byte |= data;
1496 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1497 I2C_SMBUS_WRITE, reg,
1498 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1499 if (ret < 0) {
1500 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1501 return len;
1502 }
6ee73861
BS		 1503 }
1504
37383650 1505 return len;
6ee73861
BS		 1506}
1507
37383650 1508static int
6ee73861
BS		 1509init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1510{
1511 /*
1512 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1513 *
1514 * offset (8 bit): opcode
1515 * offset + 1 (8 bit): DCB I2C table entry index
1516 * offset + 2 (8 bit): I2C slave address
1517 * offset + 3 (8 bit): count
1518 * offset + 4 (8 bit): I2C register 1
1519 * offset + 5 (8 bit): data 1
1520 * ...
1521 *
1522 * For each of "count" registers given by "I2C register n" on the device
1523 * addressed by "I2C slave address" on the I2C bus given by
1524 * "DCB I2C table entry index", set the register to "data n"
1525 */
1526
309b8c89 1527 struct drm_device *dev = bios->dev;
6ee73861 1528 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1529 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1530 uint8_t count = bios->data[offset + 3];
1531 struct nouveau_i2c_chan *chan;
893887ed
BS		 1532 int len = 4 + count * 2;
1533 int ret, i;
6ee73861
BS		 1534
1535 if (!iexec->execute)
37383650 1536 return len;
6ee73861
BS		 1537
1538 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1539 "Count: 0x%02X\n",
1540 offset, i2c_index, i2c_address, count);
1541
309b8c89
BS		 1542 chan = init_i2c_device_find(dev, i2c_index);
1543 if (!chan) {
1544 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1545 return len;
1546 }
6ee73861
BS		 1547
1548 for (i = 0; i < count; i++) {
893887ed
BS		 1549 uint8_t reg = bios->data[offset + 4 + i * 2];
1550 union i2c_smbus_data val;
1551
1552 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1553
1554 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1555 offset, reg, val.byte);
1556
1557 if (!bios->execute)
1558 continue;
1559
1560 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1561 I2C_SMBUS_WRITE, reg,
1562 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1563 if (ret < 0) {
1564 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1565 return len;
1566 }
6ee73861
BS		 1567 }
1568
37383650 1569 return len;
6ee73861
BS		 1570}
1571
37383650 1572static int
6ee73861
BS		 1573init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1574{
1575 /*
1576 * INIT_ZM_I2C opcode: 0x4E ('N')
1577 *
1578 * offset (8 bit): opcode
1579 * offset + 1 (8 bit): DCB I2C table entry index
1580 * offset + 2 (8 bit): I2C slave address
1581 * offset + 3 (8 bit): count
1582 * offset + 4 (8 bit): data 1
1583 * ...
1584 *
1585 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1586 * address" on the I2C bus given by "DCB I2C table entry index"
1587 */
1588
309b8c89 1589 struct drm_device *dev = bios->dev;
6ee73861 1590 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1591 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1592 uint8_t count = bios->data[offset + 3];
37383650 1593 int len = 4 + count;
6ee73861
BS		 1594 struct nouveau_i2c_chan *chan;
1595 struct i2c_msg msg;
1596 uint8_t data[256];
309b8c89 1597 int ret, i;
6ee73861
BS		 1598
1599 if (!iexec->execute)
37383650 1600 return len;
6ee73861
BS		 1601
1602 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1603 "Count: 0x%02X\n",
1604 offset, i2c_index, i2c_address, count);
1605
309b8c89
BS		 1606 chan = init_i2c_device_find(dev, i2c_index);
1607 if (!chan) {
1608 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1609 return len;
1610 }
6ee73861
BS		 1611
1612 for (i = 0; i < count; i++) {
1613 data[i] = bios->data[offset + 4 + i];
1614
1615 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1616 }
1617
1618 if (bios->execute) {
1619 msg.addr = i2c_address;
1620 msg.flags = 0;
1621 msg.len = count;
1622 msg.buf = data;
309b8c89
BS		 1623 ret = i2c_transfer(&chan->adapter, &msg, 1);
1624 if (ret != 1) {
1625 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1626 return len;
1627 }
6ee73861
BS		 1628 }
1629
37383650 1630 return len;
6ee73861
BS		 1631}
1632
37383650 1633static int
6ee73861
BS		 1634init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1635{
1636 /*
1637 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1638 *
1639 * offset (8 bit): opcode
1640 * offset + 1 (8 bit): magic lookup value
1641 * offset + 2 (8 bit): TMDS address
1642 * offset + 3 (8 bit): mask
1643 * offset + 4 (8 bit): data
1644 *
1645 * Read the data reg for TMDS address "TMDS address", AND it with mask
1646 * and OR it with data, then write it back
1647 * "magic lookup value" determines which TMDS base address register is
1648 * used -- see get_tmds_index_reg()
1649 */
1650
309b8c89 1651 struct drm_device *dev = bios->dev;
6ee73861
BS		 1652 uint8_t mlv = bios->data[offset + 1];
1653 uint32_t tmdsaddr = bios->data[offset + 2];
1654 uint8_t mask = bios->data[offset + 3];
1655 uint8_t data = bios->data[offset + 4];
1656 uint32_t reg, value;
1657
1658 if (!iexec->execute)
37383650 1659 return 5;
6ee73861
BS		 1660
1661 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1662 "Mask: 0x%02X, Data: 0x%02X\n",
1663 offset, mlv, tmdsaddr, mask, data);
1664
1665 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1666 if (!reg) {
1667 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1668 return 5;
1669 }
6ee73861
BS		 1670
1671 bios_wr32(bios, reg,
1672 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1673 value = (bios_rd32(bios, reg + 4) & mask) | data;
1674 bios_wr32(bios, reg + 4, value);
1675 bios_wr32(bios, reg, tmdsaddr);
1676
37383650 1677 return 5;
6ee73861
BS		 1678}
1679
37383650 1680static int
6ee73861
BS		 1681init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1682 struct init_exec *iexec)
1683{
1684 /*
1685 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1686 *
1687 * offset (8 bit): opcode
1688 * offset + 1 (8 bit): magic lookup value
1689 * offset + 2 (8 bit): count
1690 * offset + 3 (8 bit): addr 1
1691 * offset + 4 (8 bit): data 1
1692 * ...
1693 *
1694 * For each of "count" TMDS address and data pairs write "data n" to
1695 * "addr n". "magic lookup value" determines which TMDS base address
1696 * register is used -- see get_tmds_index_reg()
1697 */
1698
309b8c89 1699 struct drm_device *dev = bios->dev;
6ee73861
BS		 1700 uint8_t mlv = bios->data[offset + 1];
1701 uint8_t count = bios->data[offset + 2];
37383650 1702 int len = 3 + count * 2;
6ee73861
BS		 1703 uint32_t reg;
1704 int i;
1705
1706 if (!iexec->execute)
37383650 1707 return len;
6ee73861
BS		 1708
1709 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1710 offset, mlv, count);
1711
1712 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1713 if (!reg) {
1714 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1715 return len;
1716 }
6ee73861
BS		 1717
1718 for (i = 0; i < count; i++) {
1719 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1720 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1721
1722 bios_wr32(bios, reg + 4, tmdsdata);
1723 bios_wr32(bios, reg, tmdsaddr);
1724 }
1725
37383650 1726 return len;
6ee73861
BS		 1727}
1728
37383650 1729static int
6ee73861
BS		 1730init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1731 struct init_exec *iexec)
1732{
1733 /*
1734 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1735 *
1736 * offset (8 bit): opcode
1737 * offset + 1 (8 bit): CRTC index1
1738 * offset + 2 (8 bit): CRTC index2
1739 * offset + 3 (8 bit): baseaddr
1740 * offset + 4 (8 bit): count
1741 * offset + 5 (8 bit): data 1
1742 * ...
1743 *
1744 * For each of "count" address and data pairs, write "baseaddr + n" to
1745 * "CRTC index1" and "data n" to "CRTC index2"
1746 * Once complete, restore initial value read from "CRTC index1"
1747 */
1748 uint8_t crtcindex1 = bios->data[offset + 1];
1749 uint8_t crtcindex2 = bios->data[offset + 2];
1750 uint8_t baseaddr = bios->data[offset + 3];
1751 uint8_t count = bios->data[offset + 4];
37383650 1752 int len = 5 + count;
6ee73861
BS		 1753 uint8_t oldaddr, data;
1754 int i;
1755
1756 if (!iexec->execute)
37383650 1757 return len;
6ee73861
BS		 1758
1759 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1760 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1761 offset, crtcindex1, crtcindex2, baseaddr, count);
1762
1763 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1764
1765 for (i = 0; i < count; i++) {
1766 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1767 baseaddr + i);
1768 data = bios->data[offset + 5 + i];
1769 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1770 }
1771
1772 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1773
37383650 1774 return len;
6ee73861
BS		 1775}
1776
37383650 1777static int
6ee73861
BS		 1778init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1779{
1780 /*
1781 * INIT_CR opcode: 0x52 ('R')
1782 *
1783 * offset (8 bit): opcode
1784 * offset + 1 (8 bit): CRTC index
1785 * offset + 2 (8 bit): mask
1786 * offset + 3 (8 bit): data
1787 *
1788 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1789 * data back to "CRTC index"
1790 */
1791
1792 uint8_t crtcindex = bios->data[offset + 1];
1793 uint8_t mask = bios->data[offset + 2];
1794 uint8_t data = bios->data[offset + 3];
1795 uint8_t value;
1796
1797 if (!iexec->execute)
37383650 1798 return 4;
6ee73861
BS		 1799
1800 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1801 offset, crtcindex, mask, data);
1802
1803 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1804 value |= data;
1805 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1806
37383650 1807 return 4;
6ee73861
BS		 1808}
1809
37383650 1810static int
6ee73861
BS		 1811init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1812{
1813 /*
1814 * INIT_ZM_CR opcode: 0x53 ('S')
1815 *
1816 * offset (8 bit): opcode
1817 * offset + 1 (8 bit): CRTC index
1818 * offset + 2 (8 bit): value
1819 *
1820 * Assign "value" to CRTC register with index "CRTC index".
1821 */
1822
1823 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1824 uint8_t data = bios->data[offset + 2];
1825
1826 if (!iexec->execute)
37383650 1827 return 3;
6ee73861
BS		 1828
1829 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1830
37383650 1831 return 3;
6ee73861
BS		 1832}
1833
37383650 1834static int
6ee73861
BS		 1835init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1836{
1837 /*
1838 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1839 *
1840 * offset (8 bit): opcode
1841 * offset + 1 (8 bit): count
1842 * offset + 2 (8 bit): CRTC index 1
1843 * offset + 3 (8 bit): value 1
1844 * ...
1845 *
1846 * For "count", assign "value n" to CRTC register with index
1847 * "CRTC index n".
1848 */
1849
1850 uint8_t count = bios->data[offset + 1];
37383650 1851 int len = 2 + count * 2;
6ee73861
BS		 1852 int i;
1853
1854 if (!iexec->execute)
37383650 1855 return len;
6ee73861
BS		 1856
1857 for (i = 0; i < count; i++)
1858 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1859
37383650 1860 return len;
6ee73861
BS		 1861}
1862
37383650 1863static int
6ee73861
BS		 1864init_condition_time(struct nvbios *bios, uint16_t offset,
1865 struct init_exec *iexec)
1866{
1867 /*
1868 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1869 *
1870 * offset (8 bit): opcode
1871 * offset + 1 (8 bit): condition number
1872 * offset + 2 (8 bit): retries / 50
1873 *
1874 * Check condition "condition number" in the condition table.
1875 * Bios code then sleeps for 2ms if the condition is not met, and
1876 * repeats up to "retries" times, but on one C51 this has proved
1877 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1878 * this, and bail after "retries" times, or 2s, whichever is less.
1879 * If still not met after retries, clear execution flag for this table.
1880 */
1881
1882 uint8_t cond = bios->data[offset + 1];
1883 uint16_t retries = bios->data[offset + 2] * 50;
1884 unsigned cnt;
1885
1886 if (!iexec->execute)
37383650 1887 return 3;
6ee73861
BS		 1888
1889 if (retries > 100)
1890 retries = 100;
1891
1892 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1893 offset, cond, retries);
1894
1895 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1896 retries = 1;
1897
1898 for (cnt = 0; cnt < retries; cnt++) {
1899 if (bios_condition_met(bios, offset, cond)) {
1900 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1901 offset);
1902 break;
1903 } else {
1904 BIOSLOG(bios, "0x%04X: "
1905 "Condition not met, sleeping for 20ms\n",
1906 offset);
c7ca4d1b 1907 mdelay(20);
6ee73861
BS		 1908 }
1909 }
1910
1911 if (!bios_condition_met(bios, offset, cond)) {
1912 NV_WARN(bios->dev,
1913 "0x%04X: Condition still not met after %dms, "
1914 "skipping following opcodes\n", offset, 20 * retries);
1915 iexec->execute = false;
1916 }
1917
37383650 1918 return 3;
6ee73861
BS		 1919}
1920
e3a1924f
MK		 1921static int
1922init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1923{
1924 /*
1925 * INIT_LTIME opcode: 0x57 ('V')
1926 *
1927 * offset (8 bit): opcode
1928 * offset + 1 (16 bit): time
1929 *
e8a8b252 1930 * Sleep for "time" milliseconds.
e3a1924f
MK		 1931 */
1932
1933 unsigned time = ROM16(bios->data[offset + 1]);
1934
1935 if (!iexec->execute)
1936 return 3;
1937
e8a8b252 1938 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
e3a1924f
MK		 1939 offset, time);
1940
c7ca4d1b 1941 mdelay(time);
e3a1924f
MK		 1942
1943 return 3;
1944}
1945
37383650 1946static int
6ee73861
BS		 1947init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1948 struct init_exec *iexec)
1949{
1950 /*
1951 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1952 *
1953 * offset (8 bit): opcode
1954 * offset + 1 (32 bit): base register
1955 * offset + 5 (8 bit): count
1956 * offset + 6 (32 bit): value 1
1957 * ...
1958 *
1959 * Starting at offset + 6 there are "count" 32 bit values.
1960 * For "count" iterations set "base register" + 4 * current_iteration
1961 * to "value current_iteration"
1962 */
1963
1964 uint32_t basereg = ROM32(bios->data[offset + 1]);
1965 uint32_t count = bios->data[offset + 5];
37383650 1966 int len = 6 + count * 4;
6ee73861
BS		 1967 int i;
1968
1969 if (!iexec->execute)
37383650 1970 return len;
6ee73861
BS		 1971
1972 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1973 offset, basereg, count);
1974
1975 for (i = 0; i < count; i++) {
1976 uint32_t reg = basereg + i * 4;
1977 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1978
1979 bios_wr32(bios, reg, data);
1980 }
1981
37383650 1982 return len;
6ee73861
BS		 1983}
1984
37383650 1985static int
6ee73861
BS		 1986init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1987{
1988 /*
1989 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1990 *
1991 * offset (8 bit): opcode
1992 * offset + 1 (16 bit): subroutine offset (in bios)
1993 *
1994 * Calls a subroutine that will execute commands until INIT_DONE
1995 * is found.
1996 */
1997
1998 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
1999
2000 if (!iexec->execute)
37383650 2001 return 3;
6ee73861
BS		 2002
2003 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
2004 offset, sub_offset);
2005
2006 parse_init_table(bios, sub_offset, iexec);
2007
2008 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
2009
37383650 2010 return 3;
6ee73861
BS		 2011}
2012
ec64a408
BS		 2013static int
2014init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2015{
2016 /*
2017 * INIT_JUMP opcode: 0x5C ('\')
2018 *
2019 * offset (8 bit): opcode
2020 * offset + 1 (16 bit): offset (in bios)
2021 *
2022 * Continue execution of init table from 'offset'
2023 */
2024
2025 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
2026
2027 if (!iexec->execute)
2028 return 3;
2029
2030 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
2031 return jmp_offset - offset;
2032}
2033
b715d640
MK		 2034static int
2035init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2036{
2037 /*
2038 * INIT_I2C_IF opcode: 0x5E ('^')
2039 *
2040 * offset (8 bit): opcode
2041 * offset + 1 (8 bit): DCB I2C table entry index
2042 * offset + 2 (8 bit): I2C slave address
2043 * offset + 3 (8 bit): I2C register
2044 * offset + 4 (8 bit): mask
2045 * offset + 5 (8 bit): data
2046 *
2047 * Read the register given by "I2C register" on the device addressed
2048 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2049 * entry index". Compare the result AND "mask" to "data".
2050 * If they're not equal, skip subsequent opcodes until condition is
2051 * inverted (INIT_NOT), or we hit INIT_RESUME
2052 */
2053
2054 uint8_t i2c_index = bios->data[offset + 1];
2055 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2056 uint8_t reg = bios->data[offset + 3];
2057 uint8_t mask = bios->data[offset + 4];
2058 uint8_t data = bios->data[offset + 5];
2059 struct nouveau_i2c_chan *chan;
2060 union i2c_smbus_data val;
2061 int ret;
2062
2063 /* no execute check by design */
2064
2065 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2066 offset, i2c_index, i2c_address);
2067
2068 chan = init_i2c_device_find(bios->dev, i2c_index);
2069 if (!chan)
2070 return -ENODEV;
2071
2072 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2073 I2C_SMBUS_READ, reg,
2074 I2C_SMBUS_BYTE_DATA, &val);
2075 if (ret < 0) {
2076 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2077 "Mask: 0x%02X, Data: 0x%02X\n",
2078 offset, reg, mask, data);
2079 iexec->execute = 0;
2080 return 6;
2081 }
2082
2083 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2084 "Mask: 0x%02X, Data: 0x%02X\n",
2085 offset, reg, val.byte, mask, data);
2086
2087 iexec->execute = ((val.byte & mask) == data);
2088
2089 return 6;
2090}
2091
37383650 2092static int
6ee73861
BS		 2093init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2094{
2095 /*
2096 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2097 *
2098 * offset (8 bit): opcode
2099 * offset + 1 (32 bit): src reg
2100 * offset + 5 (8 bit): shift
2101 * offset + 6 (32 bit): src mask
2102 * offset + 10 (32 bit): xor
2103 * offset + 14 (32 bit): dst reg
2104 * offset + 18 (32 bit): dst mask
2105 *
2106 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2107 * "src mask", then XOR with "xor". Write this OR'd with
2108 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2109 */
2110
2111 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2112 uint8_t shift = bios->data[offset + 5];
2113 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2114 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2115 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2116 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2117 uint32_t srcvalue, dstvalue;
2118
2119 if (!iexec->execute)
37383650 2120 return 22;
6ee73861
BS		 2121
2122 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2123 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2124 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2125
2126 srcvalue = bios_rd32(bios, srcreg);
2127
2128 if (shift < 0x80)
2129 srcvalue >>= shift;
2130 else
2131 srcvalue <<= (0x100 - shift);
2132
2133 srcvalue = (srcvalue & srcmask) ^ xor;
2134
2135 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2136
2137 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2138
37383650 2139 return 22;
6ee73861
BS		 2140}
2141
37383650 2142static int
6ee73861
BS		 2143init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2144{
2145 /*
2146 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2147 *
2148 * offset (8 bit): opcode
2149 * offset + 1 (16 bit): CRTC port
2150 * offset + 3 (8 bit): CRTC index
2151 * offset + 4 (8 bit): data
2152 *
2153 * Write "data" to index "CRTC index" of "CRTC port"
2154 */
2155 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2156 uint8_t crtcindex = bios->data[offset + 3];
2157 uint8_t data = bios->data[offset + 4];
2158
2159 if (!iexec->execute)
37383650 2160 return 5;
6ee73861
BS		 2161
2162 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2163
37383650 2164 return 5;
6ee73861
BS		 2165}
2166
67eda20e
FJ		 2167static inline void
2168bios_md32(struct nvbios *bios, uint32_t reg,
2169 uint32_t mask, uint32_t val)
2170{
2171 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2172}
2173
2174static uint32_t
2175peek_fb(struct drm_device *dev, struct io_mapping *fb,
2176 uint32_t off)
2177{
2178 uint32_t val = 0;
2179
2180 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2181 uint8_t __iomem *p =
3e4d3af5 2182 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2183
0bf9b0e0 2184 val = ioread32(p + (off & ~PAGE_MASK));
67eda20e 2185
3e4d3af5 2186 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2187 }
2188
2189 return val;
2190}
2191
2192static void
2193poke_fb(struct drm_device *dev, struct io_mapping *fb,
2194 uint32_t off, uint32_t val)
2195{
2196 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2197 uint8_t __iomem *p =
3e4d3af5 2198 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2199
0bf9b0e0 2200 iowrite32(val, p + (off & ~PAGE_MASK));
67eda20e
FJ		 2201 wmb();
2202
3e4d3af5 2203 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2204 }
2205}
2206
2207static inline bool
2208read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2209 uint32_t off, uint32_t val)
2210{
2211 poke_fb(dev, fb, off, val);
2212 return val == peek_fb(dev, fb, off);
2213}
2214
2215static int
2216nv04_init_compute_mem(struct nvbios *bios)
2217{
2218 struct drm_device *dev = bios->dev;
2219 uint32_t patt = 0xdeadbeef;
2220 struct io_mapping *fb;
2221 int i;
2222
2223 /* Map the framebuffer aperture */
2224 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2225 pci_resource_len(dev->pdev, 1));
2226 if (!fb)
2227 return -ENOMEM;
2228
2229 /* Sequencer and refresh off */
2230 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2231 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2232
2233 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2234 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2235 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2236 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2237
2238 for (i = 0; i < 4; i++)
2239 poke_fb(dev, fb, 4 * i, patt);
2240
2241 poke_fb(dev, fb, 0x400000, patt + 1);
2242
2243 if (peek_fb(dev, fb, 0) == patt + 1) {
2244 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2245 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2246 bios_md32(bios, NV04_PFB_DEBUG_0,
2247 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2248
2249 for (i = 0; i < 4; i++)
2250 poke_fb(dev, fb, 4 * i, patt);
2251
2252 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2253 bios_md32(bios, NV04_PFB_BOOT_0,
2254 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2255 NV04_PFB_BOOT_0_RAM_AMOUNT,
2256 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2257
2258 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2259 (patt & 0xffff0000)) {
2260 bios_md32(bios, NV04_PFB_BOOT_0,
2261 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2262 NV04_PFB_BOOT_0_RAM_AMOUNT,
2263 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2264
0746b5da 2265 } else if (peek_fb(dev, fb, 0) != patt) {
67eda20e
FJ		 2266 if (read_back_fb(dev, fb, 0x800000, patt))
2267 bios_md32(bios, NV04_PFB_BOOT_0,
2268 NV04_PFB_BOOT_0_RAM_AMOUNT,
2269 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2270 else
2271 bios_md32(bios, NV04_PFB_BOOT_0,
2272 NV04_PFB_BOOT_0_RAM_AMOUNT,
2273 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2274
2275 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2276 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2277
2278 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2279 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2280 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2281
2282 }
2283
2284 /* Refresh on, sequencer on */
2285 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2286 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2287
2288 io_mapping_free(fb);
2289 return 0;
2290}
2291
2292static const uint8_t *
2293nv05_memory_config(struct nvbios *bios)
2294{
2295 /* Defaults for BIOSes lacking a memory config table */
2296 static const uint8_t default_config_tab[][2] = {
2297 { 0x24, 0x00 },
2298 { 0x28, 0x00 },
2299 { 0x24, 0x01 },
2300 { 0x1f, 0x00 },
2301 { 0x0f, 0x00 },
2302 { 0x17, 0x00 },
2303 { 0x06, 0x00 },
2304 { 0x00, 0x00 }
2305 };
2306 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2307 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2308
2309 if (bios->legacy.mem_init_tbl_ptr)
2310 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2311 else
2312 return default_config_tab[i];
2313}
2314
2315static int
2316nv05_init_compute_mem(struct nvbios *bios)
2317{
2318 struct drm_device *dev = bios->dev;
2319 const uint8_t *ramcfg = nv05_memory_config(bios);
2320 uint32_t patt = 0xdeadbeef;
2321 struct io_mapping *fb;
2322 int i, v;
2323
2324 /* Map the framebuffer aperture */
2325 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2326 pci_resource_len(dev->pdev, 1));
2327 if (!fb)
2328 return -ENOMEM;
2329
2330 /* Sequencer off */
2331 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2332
2333 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2334 goto out;
2335
2336 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2337
2338 /* If present load the hardcoded scrambling table */
2339 if (bios->legacy.mem_init_tbl_ptr) {
2340 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2341 bios->legacy.mem_init_tbl_ptr + 0x10];
2342
2343 for (i = 0; i < 8; i++)
2344 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2345 ROM32(scramble_tab[i]));
2346 }
2347
2348 /* Set memory type/width/length defaults depending on the straps */
2349 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2350
2351 if (ramcfg[1] & 0x80)
2352 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2353
2354 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2355 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2356
2357 /* Probe memory bus width */
2358 for (i = 0; i < 4; i++)
2359 poke_fb(dev, fb, 4 * i, patt);
2360
2361 if (peek_fb(dev, fb, 0xc) != patt)
2362 bios_md32(bios, NV04_PFB_BOOT_0,
2363 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2364
2365 /* Probe memory length */
2366 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2367
2368 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2369 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2370 !read_back_fb(dev, fb, 0, ++patt)))
2371 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2372 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2373
2374 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2375 !read_back_fb(dev, fb, 0x800000, ++patt))
2376 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2377 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2378
2379 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2380 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2381 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2382
2383out:
2384 /* Sequencer on */
2385 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2386
2387 io_mapping_free(fb);
2388 return 0;
2389}
2390
2391static int
2392nv10_init_compute_mem(struct nvbios *bios)
2393{
2394 struct drm_device *dev = bios->dev;
2395 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2396 const int mem_width[] = { 0x10, 0x00, 0x20 };
2397 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2398 uint32_t patt = 0xdeadbeef;
2399 struct io_mapping *fb;
2400 int i, j, k;
2401
2402 /* Map the framebuffer aperture */
2403 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2404 pci_resource_len(dev->pdev, 1));
2405 if (!fb)
2406 return -ENOMEM;
2407
2408 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2409
2410 /* Probe memory bus width */
2411 for (i = 0; i < mem_width_count; i++) {
2412 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2413
2414 for (j = 0; j < 4; j++) {
2415 for (k = 0; k < 4; k++)
2416 poke_fb(dev, fb, 0x1c, 0);
2417
2418 poke_fb(dev, fb, 0x1c, patt);
2419 poke_fb(dev, fb, 0x3c, 0);
2420
2421 if (peek_fb(dev, fb, 0x1c) == patt)
2422 goto mem_width_found;
2423 }
2424 }
2425
2426mem_width_found:
2427 patt <<= 1;
2428
2429 /* Probe amount of installed memory */
2430 for (i = 0; i < 4; i++) {
2431 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2432
2433 poke_fb(dev, fb, off, patt);
2434 poke_fb(dev, fb, 0, 0);
2435
2436 peek_fb(dev, fb, 0);
2437 peek_fb(dev, fb, 0);
2438 peek_fb(dev, fb, 0);
2439 peek_fb(dev, fb, 0);
2440
2441 if (peek_fb(dev, fb, off) == patt)
2442 goto amount_found;
2443 }
2444
2445 /* IC missing - disable the upper half memory space. */
2446 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2447
2448amount_found:
2449 io_mapping_free(fb);
2450 return 0;
2451}
2452
2453static int
2454nv20_init_compute_mem(struct nvbios *bios)
2455{
2456 struct drm_device *dev = bios->dev;
2457 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2458 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2459 uint32_t amount, off;
2460 struct io_mapping *fb;
2461
2462 /* Map the framebuffer aperture */
2463 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2464 pci_resource_len(dev->pdev, 1));
2465 if (!fb)
2466 return -ENOMEM;
2467
2468 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2469
2470 /* Allow full addressing */
2471 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2472
2473 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2474 for (off = amount; off > 0x2000000; off -= 0x2000000)
2475 poke_fb(dev, fb, off - 4, off);
2476
2477 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2478 if (amount != peek_fb(dev, fb, amount - 4))
2479 /* IC missing - disable the upper half memory space. */
2480 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2481
2482 io_mapping_free(fb);
2483 return 0;
2484}
2485
37383650 2486static int
6ee73861
BS		 2487init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2488{
2489 /*
2490 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2491 *
2492 * offset (8 bit): opcode
2493 *
67eda20e
FJ		 2494 * This opcode is meant to set the PFB memory config registers
2495 * appropriately so that we can correctly calculate how much VRAM it
2496 * has (on nv10 and better chipsets the amount of installed VRAM is
2497 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
6ee73861 2498 *
67eda20e
FJ		 2499 * The implementation of this opcode in general consists of several
2500 * parts:
6ee73861 2501 *
67eda20e
FJ		 2502 * 1) Determination of memory type and density. Only necessary for
2503 * really old chipsets, the memory type reported by the strap bits
2504 * (0x101000) is assumed to be accurate on nv05 and newer.
6ee73861 2505 *
67eda20e
FJ		 2506 * 2) Determination of the memory bus width. Usually done by a cunning
2507 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2508 * seeing whether the written values are read back correctly.
6ee73861 2509 *
67eda20e
FJ		 2510 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2511 * trust the straps.
6ee73861 2512 *
67eda20e
FJ		 2513 * 3) Determination of how many of the card's RAM pads have ICs
2514 * attached, usually done by a cunning combination of writes to an
2515 * offset slightly less than the maximum memory reported by
2516 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
6ee73861 2517 *
67eda20e
FJ		 2518 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2519 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2520 * card show nothing being done for this opcode. Why is it still listed
2521 * in the table?!
6ee73861
BS		 2522 */
2523
2524 /* no iexec->execute check by design */
2525
6ee73861 2526 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
67eda20e 2527 int ret;
6ee73861 2528
67eda20e
FJ		 2529 if (dev_priv->chipset >= 0x40 ||
2530 dev_priv->chipset == 0x1a ||
2531 dev_priv->chipset == 0x1f)
2532 ret = 0;
2533 else if (dev_priv->chipset >= 0x20 &&
2534 dev_priv->chipset != 0x34)
2535 ret = nv20_init_compute_mem(bios);
2536 else if (dev_priv->chipset >= 0x10)
2537 ret = nv10_init_compute_mem(bios);
2538 else if (dev_priv->chipset >= 0x5)
2539 ret = nv05_init_compute_mem(bios);
2540 else
2541 ret = nv04_init_compute_mem(bios);
6ee73861 2542
67eda20e
FJ		 2543 if (ret)
2544 return ret;
6ee73861 2545
37383650 2546 return 1;
6ee73861
BS		 2547}
2548
37383650 2549static int
6ee73861
BS		 2550init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2551{
2552 /*
2553 * INIT_RESET opcode: 0x65 ('e')
2554 *
2555 * offset (8 bit): opcode
2556 * offset + 1 (32 bit): register
2557 * offset + 5 (32 bit): value1
2558 * offset + 9 (32 bit): value2
2559 *
2560 * Assign "value1" to "register", then assign "value2" to "register"
2561 */
2562
2563 uint32_t reg = ROM32(bios->data[offset + 1]);
2564 uint32_t value1 = ROM32(bios->data[offset + 5]);
2565 uint32_t value2 = ROM32(bios->data[offset + 9]);
2566 uint32_t pci_nv_19, pci_nv_20;
2567
2568 /* no iexec->execute check by design */
2569
2570 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
190a4378
FJ		 2571 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2572
6ee73861
BS		 2573 bios_wr32(bios, reg, value1);
2574
2575 udelay(10);
2576
2577 bios_wr32(bios, reg, value2);
2578 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2579
2580 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2581 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2582 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2583
37383650 2584 return 13;
6ee73861
BS		 2585}
2586
37383650 2587static int
6ee73861
BS		 2588init_configure_mem(struct nvbios *bios, uint16_t offset,
2589 struct init_exec *iexec)
2590{
2591 /*
2592 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2593 *
2594 * offset (8 bit): opcode
2595 *
2596 * Equivalent to INIT_DONE on bios version 3 or greater.
2597 * For early bios versions, sets up the memory registers, using values
2598 * taken from the memory init table
2599 */
2600
2601 /* no iexec->execute check by design */
2602
2603 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2604 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2605 uint32_t reg, data;
2606
2607 if (bios->major_version > 2)
ae55321c 2608 return 0;
6ee73861
BS		 2609
2610 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2611 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2612
2613 if (bios->data[meminitoffs] & 1)
2614 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2615
2616 for (reg = ROM32(bios->data[seqtbloffs]);
2617 reg != 0xffffffff;
2618 reg = ROM32(bios->data[seqtbloffs += 4])) {
2619
2620 switch (reg) {
3c7066bc
FJ		 2621 case NV04_PFB_PRE:
2622 data = NV04_PFB_PRE_CMD_PRECHARGE;
6ee73861 2623 break;
3c7066bc
FJ		 2624 case NV04_PFB_PAD:
2625 data = NV04_PFB_PAD_CKE_NORMAL;
6ee73861 2626 break;
3c7066bc
FJ		 2627 case NV04_PFB_REF:
2628 data = NV04_PFB_REF_CMD_REFRESH;
6ee73861
BS		 2629 break;
2630 default:
2631 data = ROM32(bios->data[meminitdata]);
2632 meminitdata += 4;
2633 if (data == 0xffffffff)
2634 continue;
2635 }
2636
2637 bios_wr32(bios, reg, data);
2638 }
2639
37383650 2640 return 1;
6ee73861
BS		 2641}
2642
37383650 2643static int
6ee73861
BS		 2644init_configure_clk(struct nvbios *bios, uint16_t offset,
2645 struct init_exec *iexec)
2646{
2647 /*
2648 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2649 *
2650 * offset (8 bit): opcode
2651 *
2652 * Equivalent to INIT_DONE on bios version 3 or greater.
2653 * For early bios versions, sets up the NVClk and MClk PLLs, using
2654 * values taken from the memory init table
2655 */
2656
2657 /* no iexec->execute check by design */
2658
2659 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2660 int clock;
2661
2662 if (bios->major_version > 2)
ae55321c 2663 return 0;
6ee73861
BS		 2664
2665 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2666 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2667
2668 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2669 if (bios->data[meminitoffs] & 1) /* DDR */
2670 clock *= 2;
2671 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2672
37383650 2673 return 1;
6ee73861
BS		 2674}
2675
37383650 2676static int
6ee73861
BS		 2677init_configure_preinit(struct nvbios *bios, uint16_t offset,
2678 struct init_exec *iexec)
2679{
2680 /*
2681 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2682 *
2683 * offset (8 bit): opcode
2684 *
2685 * Equivalent to INIT_DONE on bios version 3 or greater.
2686 * For early bios versions, does early init, loading ram and crystal
2687 * configuration from straps into CR3C
2688 */
2689
2690 /* no iexec->execute check by design */
2691
2692 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
3c9b2534 2693 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
6ee73861
BS		 2694
2695 if (bios->major_version > 2)
ae55321c 2696 return 0;
6ee73861
BS		 2697
2698 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2699 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2700
37383650 2701 return 1;
6ee73861
BS		 2702}
2703
37383650 2704static int
6ee73861
BS		 2705init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2706{
2707 /*
2708 * INIT_IO opcode: 0x69 ('i')
2709 *
2710 * offset (8 bit): opcode
2711 * offset + 1 (16 bit): CRTC port
2712 * offset + 3 (8 bit): mask
2713 * offset + 4 (8 bit): data
2714 *
2715 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2716 */
2717
2718 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2719 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2720 uint8_t mask = bios->data[offset + 3];
2721 uint8_t data = bios->data[offset + 4];
2722
2723 if (!iexec->execute)
37383650 2724 return 5;
6ee73861
BS		 2725
2726 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2727 offset, crtcport, mask, data);
2728
2729 /*
2730 * I have no idea what this does, but NVIDIA do this magic sequence
2731 * in the places where this INIT_IO happens..
2732 */
2733 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2734 int i;
2735
2736 bios_wr32(bios, 0x614100, (bios_rd32(
2737 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2738
2739 bios_wr32(bios, 0x00e18c, bios_rd32(
2740 bios, 0x00e18c) | 0x00020000);
2741
2742 bios_wr32(bios, 0x614900, (bios_rd32(
2743 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2744
2745 bios_wr32(bios, 0x000200, bios_rd32(
2746 bios, 0x000200) & ~0x40000000);
2747
2748 mdelay(10);
2749
2750 bios_wr32(bios, 0x00e18c, bios_rd32(
2751 bios, 0x00e18c) & ~0x00020000);
2752
2753 bios_wr32(bios, 0x000200, bios_rd32(
2754 bios, 0x000200) | 0x40000000);
2755
2756 bios_wr32(bios, 0x614100, 0x00800018);
2757 bios_wr32(bios, 0x614900, 0x00800018);
2758
2759 mdelay(10);
2760
2761 bios_wr32(bios, 0x614100, 0x10000018);
2762 bios_wr32(bios, 0x614900, 0x10000018);
2763
2764 for (i = 0; i < 3; i++)
2765 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2766 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2767
2768 for (i = 0; i < 2; i++)
2769 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2770 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2771
2772 for (i = 0; i < 3; i++)
2773 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2774 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2775
2776 for (i = 0; i < 2; i++)
2777 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2778 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2779
2780 for (i = 0; i < 2; i++)
2781 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2782 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2783 return 5;
6ee73861
BS		 2784 }
2785
2786 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2787 data);
37383650 2788 return 5;
6ee73861
BS		 2789}
2790
37383650 2791static int
6ee73861
BS		 2792init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2793{
2794 /*
2795 * INIT_SUB opcode: 0x6B ('k')
2796 *
2797 * offset (8 bit): opcode
2798 * offset + 1 (8 bit): script number
2799 *
2800 * Execute script number "script number", as a subroutine
2801 */
2802
2803 uint8_t sub = bios->data[offset + 1];
2804
2805 if (!iexec->execute)
37383650 2806 return 2;
6ee73861
BS		 2807
2808 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2809
2810 parse_init_table(bios,
2811 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2812 iexec);
2813
2814 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2815
37383650 2816 return 2;
6ee73861
BS		 2817}
2818
37383650 2819static int
6ee73861
BS		 2820init_ram_condition(struct nvbios *bios, uint16_t offset,
2821 struct init_exec *iexec)
2822{
2823 /*
2824 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2825 *
2826 * offset (8 bit): opcode
2827 * offset + 1 (8 bit): mask
2828 * offset + 2 (8 bit): cmpval
2829 *
3c7066bc 2830 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
6ee73861
BS		 2831 * If condition not met skip subsequent opcodes until condition is
2832 * inverted (INIT_NOT), or we hit INIT_RESUME
2833 */
2834
2835 uint8_t mask = bios->data[offset + 1];
2836 uint8_t cmpval = bios->data[offset + 2];
2837 uint8_t data;
2838
2839 if (!iexec->execute)
37383650 2840 return 3;
6ee73861 2841
3c7066bc 2842 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
6ee73861
BS		 2843
2844 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2845 offset, data, cmpval);
2846
2847 if (data == cmpval)
2848 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2849 else {
2850 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2851 iexec->execute = false;
2852 }
2853
37383650 2854 return 3;
6ee73861
BS		 2855}
2856
37383650 2857static int
6ee73861
BS		 2858init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2859{
2860 /*
2861 * INIT_NV_REG opcode: 0x6E ('n')
2862 *
2863 * offset (8 bit): opcode
2864 * offset + 1 (32 bit): register
2865 * offset + 5 (32 bit): mask
2866 * offset + 9 (32 bit): data
2867 *
2868 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2869 */
2870
2871 uint32_t reg = ROM32(bios->data[offset + 1]);
2872 uint32_t mask = ROM32(bios->data[offset + 5]);
2873 uint32_t data = ROM32(bios->data[offset + 9]);
2874
2875 if (!iexec->execute)
37383650 2876 return 13;
6ee73861
BS		 2877
2878 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2879 offset, reg, mask, data);
2880
2881 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2882
37383650 2883 return 13;
6ee73861
BS		 2884}
2885
37383650 2886static int
6ee73861
BS		 2887init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2888{
2889 /*
2890 * INIT_MACRO opcode: 0x6F ('o')
2891 *
2892 * offset (8 bit): opcode
2893 * offset + 1 (8 bit): macro number
2894 *
2895 * Look up macro index "macro number" in the macro index table.
2896 * The macro index table entry has 1 byte for the index in the macro
2897 * table, and 1 byte for the number of times to repeat the macro.
2898 * The macro table entry has 4 bytes for the register address and
2899 * 4 bytes for the value to write to that register
2900 */
2901
2902 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2903 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2904 uint8_t macro_tbl_idx = bios->data[tmp];
2905 uint8_t count = bios->data[tmp + 1];
2906 uint32_t reg, data;
2907 int i;
2908
2909 if (!iexec->execute)
37383650 2910 return 2;
6ee73861
BS		 2911
2912 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2913 "Count: 0x%02X\n",
2914 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2915
2916 for (i = 0; i < count; i++) {
2917 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2918
2919 reg = ROM32(bios->data[macroentryptr]);
2920 data = ROM32(bios->data[macroentryptr + 4]);
2921
2922 bios_wr32(bios, reg, data);
2923 }
2924
37383650 2925 return 2;
6ee73861
BS		 2926}
2927
37383650 2928static int
6ee73861
BS		 2929init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2930{
2931 /*
2932 * INIT_DONE opcode: 0x71 ('q')
2933 *
2934 * offset (8 bit): opcode
2935 *
2936 * End the current script
2937 */
2938
2939 /* mild retval abuse to stop parsing this table */
37383650 2940 return 0;
6ee73861
BS		 2941}
2942
37383650 2943static int
6ee73861
BS		 2944init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2945{
2946 /*
2947 * INIT_RESUME opcode: 0x72 ('r')
2948 *
2949 * offset (8 bit): opcode
2950 *
2951 * End the current execute / no-execute condition
2952 */
2953
2954 if (iexec->execute)
37383650 2955 return 1;
6ee73861
BS		 2956
2957 iexec->execute = true;
2958 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2959
37383650 2960 return 1;
6ee73861
BS		 2961}
2962
37383650 2963static int
6ee73861
BS		 2964init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2965{
2966 /*
2967 * INIT_TIME opcode: 0x74 ('t')
2968 *
2969 * offset (8 bit): opcode
2970 * offset + 1 (16 bit): time
2971 *
2972 * Sleep for "time" microseconds.
2973 */
2974
2975 unsigned time = ROM16(bios->data[offset + 1]);
2976
2977 if (!iexec->execute)
37383650 2978 return 3;
6ee73861
BS		 2979
2980 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2981 offset, time);
2982
2983 if (time < 1000)
2984 udelay(time);
2985 else
c7ca4d1b 2986 mdelay((time + 900) / 1000);
6ee73861 2987
37383650 2988 return 3;
6ee73861
BS		 2989}
2990
37383650 2991static int
6ee73861
BS		 2992init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2993{
2994 /*
2995 * INIT_CONDITION opcode: 0x75 ('u')
2996 *
2997 * offset (8 bit): opcode
2998 * offset + 1 (8 bit): condition number
2999 *
3000 * Check condition "condition number" in the condition table.
3001 * If condition not met skip subsequent opcodes until condition is
3002 * inverted (INIT_NOT), or we hit INIT_RESUME
3003 */
3004
3005 uint8_t cond = bios->data[offset + 1];
3006
3007 if (!iexec->execute)
37383650 3008 return 2;
6ee73861
BS		 3009
3010 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
3011
3012 if (bios_condition_met(bios, offset, cond))
3013 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3014 else {
3015 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3016 iexec->execute = false;
3017 }
3018
37383650 3019 return 2;
6ee73861
BS		 3020}
3021
37383650 3022static int
6ee73861
BS		 3023init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3024{
3025 /*
3026 * INIT_IO_CONDITION opcode: 0x76
3027 *
3028 * offset (8 bit): opcode
3029 * offset + 1 (8 bit): condition number
3030 *
3031 * Check condition "condition number" in the io condition table.
3032 * If condition not met skip subsequent opcodes until condition is
3033 * inverted (INIT_NOT), or we hit INIT_RESUME
3034 */
3035
3036 uint8_t cond = bios->data[offset + 1];
3037
3038 if (!iexec->execute)
37383650 3039 return 2;
6ee73861
BS		 3040
3041 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
3042
3043 if (io_condition_met(bios, offset, cond))
3044 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3045 else {
3046 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3047 iexec->execute = false;
3048 }
3049
37383650 3050 return 2;
6ee73861
BS		 3051}
3052
37383650 3053static int
6ee73861
BS		 3054init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3055{
3056 /*
3057 * INIT_INDEX_IO opcode: 0x78 ('x')
3058 *
3059 * offset (8 bit): opcode
3060 * offset + 1 (16 bit): CRTC port
3061 * offset + 3 (8 bit): CRTC index
3062 * offset + 4 (8 bit): mask
3063 * offset + 5 (8 bit): data
3064 *
3065 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3066 * OR with "data", write-back
3067 */
3068
3069 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3070 uint8_t crtcindex = bios->data[offset + 3];
3071 uint8_t mask = bios->data[offset + 4];
3072 uint8_t data = bios->data[offset + 5];
3073 uint8_t value;
3074
3075 if (!iexec->execute)
37383650 3076 return 6;
6ee73861
BS		 3077
3078 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3079 "Data: 0x%02X\n",
3080 offset, crtcport, crtcindex, mask, data);
3081
3082 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3083 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3084
37383650 3085 return 6;
6ee73861
BS		 3086}
3087
37383650 3088static int
6ee73861
BS		 3089init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3090{
3091 /*
3092 * INIT_PLL opcode: 0x79 ('y')
3093 *
3094 * offset (8 bit): opcode
3095 * offset + 1 (32 bit): register
3096 * offset + 5 (16 bit): freq
3097 *
3098 * Set PLL register "register" to coefficients for frequency (10kHz)
3099 * "freq"
3100 */
3101
3102 uint32_t reg = ROM32(bios->data[offset + 1]);
3103 uint16_t freq = ROM16(bios->data[offset + 5]);
3104
3105 if (!iexec->execute)
37383650 3106 return 7;
6ee73861
BS		 3107
3108 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3109
3110 setPLL(bios, reg, freq * 10);
3111
37383650 3112 return 7;
6ee73861
BS		 3113}
3114
37383650 3115static int
6ee73861
BS		 3116init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3117{
3118 /*
3119 * INIT_ZM_REG opcode: 0x7A ('z')
3120 *
3121 * offset (8 bit): opcode
3122 * offset + 1 (32 bit): register
3123 * offset + 5 (32 bit): value
3124 *
3125 * Assign "value" to "register"
3126 */
3127
3128 uint32_t reg = ROM32(bios->data[offset + 1]);
3129 uint32_t value = ROM32(bios->data[offset + 5]);
3130
3131 if (!iexec->execute)
37383650 3132 return 9;
6ee73861
BS		 3133
3134 if (reg == 0x000200)
3135 value |= 1;
3136
3137 bios_wr32(bios, reg, value);
3138
37383650 3139 return 9;
6ee73861
BS		 3140}
3141
37383650 3142static int
6ee73861
BS		 3143init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3144 struct init_exec *iexec)
3145{
3146 /*
3147 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3148 *
3149 * offset (8 bit): opcode
3150 * offset + 1 (8 bit): PLL type
3151 * offset + 2 (32 bit): frequency 0
3152 *
3153 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3154 * ram_restrict_table_ptr. The value read from there is used to select
3155 * a frequency from the table starting at 'frequency 0' to be
3156 * programmed into the PLL corresponding to 'type'.
3157 *
3158 * The PLL limits table on cards using this opcode has a mapping of
3159 * 'type' to the relevant registers.
3160 */
3161
3162 struct drm_device *dev = bios->dev;
3163 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3164 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3165 uint8_t type = bios->data[offset + 1];
3166 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3167 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 3168 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 3169 int i;
3170
3171 if (!iexec->execute)
37383650 3172 return len;
6ee73861
BS		 3173
3174 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3175 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 3176 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 3177 }
3178
3179 entry = pll_limits + pll_limits[1];
3180 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3181 if (entry[0] == type) {
3182 uint32_t reg = ROM32(entry[3]);
3183
3184 BIOSLOG(bios, "0x%04X: "
3185 "Type %02x Reg 0x%08x Freq %dKHz\n",
3186 offset, type, reg, freq);
3187
3188 setPLL(bios, reg, freq);
37383650 3189 return len;
6ee73861
BS		 3190 }
3191 }
3192
3193 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 3194 return len;
6ee73861
BS		 3195}
3196
37383650 3197static int
6ee73861
BS		 3198init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3199{
3200 /*
3201 * INIT_8C opcode: 0x8C ('')
3202 *
3203 * NOP so far....
3204 *
3205 */
3206
37383650 3207 return 1;
6ee73861
BS		 3208}
3209
37383650 3210static int
6ee73861
BS		 3211init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3212{
3213 /*
3214 * INIT_8D opcode: 0x8D ('')
3215 *
3216 * NOP so far....
3217 *
3218 */
3219
37383650 3220 return 1;
6ee73861
BS		 3221}
3222
37383650 3223static int
6ee73861
BS		 3224init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3225{
3226 /*
3227 * INIT_GPIO opcode: 0x8E ('')
3228 *
3229 * offset (8 bit): opcode
3230 *
3231 * Loop over all entries in the DCB GPIO table, and initialise
3232 * each GPIO according to various values listed in each entry
3233 */
3234
2535d71c 3235 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
ee2e0131 3236 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861 3237 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
6ee73861
BS		 3238 int i;
3239
080feda5 3240 if (dev_priv->card_type < NV_50) {
2535d71c 3241 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
309b8c89 3242 return 1;
6ee73861
BS		 3243 }
3244
2535d71c
BS		 3245 if (!iexec->execute)
3246 return 1;
6ee73861 3247
2535d71c
BS		 3248 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3249 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
3250 uint32_t r, s, v;
6ee73861 3251
2535d71c 3252 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 3253
73db4bed
BS		 3254 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3255 offset, gpio->tag, gpio->state_default);
3256 if (bios->execute)
ee2e0131 3257 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
6ee73861 3258
45284162
BS		 3259 /* The NVIDIA binary driver doesn't appear to actually do
3260 * any of this, my VBIOS does however.
3261 */
3262 /* Not a clue, needs de-magicing */
2535d71c
BS		 3263 r = nv50_gpio_ctl[gpio->line >> 4];
3264 s = (gpio->line & 0x0f);
6ee73861 3265 v = bios_rd32(bios, r) & ~(0x00010001 << s);
2535d71c 3266 switch ((gpio->entry & 0x06000000) >> 25) {
6ee73861
BS		 3267 case 1:
3268 v |= (0x00000001 << s);
3269 break;
3270 case 2:
3271 v |= (0x00010000 << s);
3272 break;
3273 default:
3274 break;
3275 }
3276 bios_wr32(bios, r, v);
3277 }
3278
37383650 3279 return 1;
6ee73861
BS		 3280}
3281
37383650 3282static int
6ee73861
BS		 3283init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3284 struct init_exec *iexec)
3285{
3286 /*
3287 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3288 *
3289 * offset (8 bit): opcode
3290 * offset + 1 (32 bit): reg
3291 * offset + 5 (8 bit): regincrement
3292 * offset + 6 (8 bit): count
3293 * offset + 7 (32 bit): value 1,1
3294 * ...
3295 *
3296 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3297 * ram_restrict_table_ptr. The value read from here is 'n', and
3298 * "value 1,n" gets written to "reg". This repeats "count" times and on
3299 * each iteration 'm', "reg" increases by "regincrement" and
3300 * "value m,n" is used. The extent of n is limited by a number read
3301 * from the 'M' BIT table, herein called "blocklen"
3302 */
3303
3304 uint32_t reg = ROM32(bios->data[offset + 1]);
3305 uint8_t regincrement = bios->data[offset + 5];
3306 uint8_t count = bios->data[offset + 6];
3307 uint32_t strap_ramcfg, data;
37383650
MK		 3308 /* previously set by 'M' BIT table */
3309 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3310 int len = 7 + count * blocklen;
6ee73861
BS		 3311 uint8_t index;
3312 int i;
3313
309b8c89 3314 /* critical! to know the length of the opcode */;
6ee73861
BS		 3315 if (!blocklen) {
3316 NV_ERROR(bios->dev,
3317 "0x%04X: Zero block length - has the M table "
3318 "been parsed?\n", offset);
9170a824 3319 return -EINVAL;
6ee73861
BS		 3320 }
3321
309b8c89
BS		 3322 if (!iexec->execute)
3323 return len;
3324
6ee73861
BS		 3325 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3326 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3327
3328 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3329 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3330 offset, reg, regincrement, count, strap_ramcfg, index);
3331
3332 for (i = 0; i < count; i++) {
3333 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3334
3335 bios_wr32(bios, reg, data);
3336
3337 reg += regincrement;
3338 }
3339
37383650 3340 return len;
6ee73861
BS		 3341}
3342
37383650 3343static int
6ee73861
BS		 3344init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3345{
3346 /*
3347 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3348 *
3349 * offset (8 bit): opcode
3350 * offset + 1 (32 bit): src reg
3351 * offset + 5 (32 bit): dst reg
3352 *
3353 * Put contents of "src reg" into "dst reg"
3354 */
3355
3356 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3357 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3358
3359 if (!iexec->execute)
37383650 3360 return 9;
6ee73861
BS		 3361
3362 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3363
37383650 3364 return 9;
6ee73861
BS		 3365}
3366
37383650 3367static int
6ee73861
BS		 3368init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3369 struct init_exec *iexec)
3370{
3371 /*
3372 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3373 *
3374 * offset (8 bit): opcode
3375 * offset + 1 (32 bit): dst reg
3376 * offset + 5 (8 bit): count
3377 * offset + 6 (32 bit): data 1
3378 * ...
3379 *
3380 * For each of "count" values write "data n" to "dst reg"
3381 */
3382
3383 uint32_t reg = ROM32(bios->data[offset + 1]);
3384 uint8_t count = bios->data[offset + 5];
37383650 3385 int len = 6 + count * 4;
6ee73861
BS		 3386 int i;
3387
3388 if (!iexec->execute)
37383650 3389 return len;
6ee73861
BS		 3390
3391 for (i = 0; i < count; i++) {
3392 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3393 bios_wr32(bios, reg, data);
3394 }
3395
37383650 3396 return len;
6ee73861
BS		 3397}
3398
37383650 3399static int
6ee73861
BS		 3400init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3401{
3402 /*
3403 * INIT_RESERVED opcode: 0x92 ('')
3404 *
3405 * offset (8 bit): opcode
3406 *
3407 * Seemingly does nothing
3408 */
3409
37383650 3410 return 1;
6ee73861
BS		 3411}
3412
37383650 3413static int
6ee73861
BS		 3414init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3415{
3416 /*
3417 * INIT_96 opcode: 0x96 ('')
3418 *
3419 * offset (8 bit): opcode
3420 * offset + 1 (32 bit): sreg
3421 * offset + 5 (8 bit): sshift
3422 * offset + 6 (8 bit): smask
3423 * offset + 7 (8 bit): index
3424 * offset + 8 (32 bit): reg
3425 * offset + 12 (32 bit): mask
3426 * offset + 16 (8 bit): shift
3427 *
3428 */
3429
3430 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3431 uint32_t reg = ROM32(bios->data[offset + 8]);
3432 uint32_t mask = ROM32(bios->data[offset + 12]);
3433 uint32_t val;
3434
3435 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3436 if (bios->data[offset + 5] < 0x80)
3437 val >>= bios->data[offset + 5];
3438 else
3439 val <<= (0x100 - bios->data[offset + 5]);
3440 val &= bios->data[offset + 6];
3441
3442 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3443 val <<= bios->data[offset + 16];
3444
3445 if (!iexec->execute)
37383650 3446 return 17;
6ee73861
BS		 3447
3448 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3449 return 17;
6ee73861
BS		 3450}
3451
37383650 3452static int
6ee73861
BS		 3453init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3454{
3455 /*
3456 * INIT_97 opcode: 0x97 ('')
3457 *
3458 * offset (8 bit): opcode
3459 * offset + 1 (32 bit): register
3460 * offset + 5 (32 bit): mask
3461 * offset + 9 (32 bit): value
3462 *
3463 * Adds "value" to "register" preserving the fields specified
3464 * by "mask"
3465 */
3466
3467 uint32_t reg = ROM32(bios->data[offset + 1]);
3468 uint32_t mask = ROM32(bios->data[offset + 5]);
3469 uint32_t add = ROM32(bios->data[offset + 9]);
3470 uint32_t val;
3471
3472 val = bios_rd32(bios, reg);
3473 val = (val & mask) | ((val + add) & ~mask);
3474
3475 if (!iexec->execute)
37383650 3476 return 13;
6ee73861
BS		 3477
3478 bios_wr32(bios, reg, val);
37383650 3479 return 13;
6ee73861
BS		 3480}
3481
37383650 3482static int
6ee73861
BS		 3483init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3484{
3485 /*
3486 * INIT_AUXCH opcode: 0x98 ('')
3487 *
3488 * offset (8 bit): opcode
3489 * offset + 1 (32 bit): address
3490 * offset + 5 (8 bit): count
3491 * offset + 6 (8 bit): mask 0
3492 * offset + 7 (8 bit): data 0
3493 * ...
3494 *
3495 */
3496
3497 struct drm_device *dev = bios->dev;
3498 struct nouveau_i2c_chan *auxch;
3499 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3500 uint8_t count = bios->data[offset + 5];
3501 int len = 6 + count * 2;
6ee73861
BS		 3502 int ret, i;
3503
3504 if (!bios->display.output) {
3505 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
309b8c89 3506 return len;
6ee73861
BS		 3507 }
3508
3509 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3510 if (!auxch) {
3511 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3512 bios->display.output->i2c_index);
309b8c89 3513 return len;
6ee73861
BS		 3514 }
3515
3516 if (!iexec->execute)
37383650 3517 return len;
6ee73861
BS		 3518
3519 offset += 6;
37383650 3520 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3521 uint8_t data;
3522
3523 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3524 if (ret) {
3525 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
309b8c89 3526 return len;
6ee73861
BS		 3527 }
3528
3529 data &= bios->data[offset + 0];
3530 data |= bios->data[offset + 1];
3531
3532 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3533 if (ret) {
3534 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3535 return len;
6ee73861
BS		 3536 }
3537 }
3538
37383650 3539 return len;
6ee73861
BS		 3540}
3541
37383650 3542static int
6ee73861
BS		 3543init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3544{
3545 /*
3546 * INIT_ZM_AUXCH opcode: 0x99 ('')
3547 *
3548 * offset (8 bit): opcode
3549 * offset + 1 (32 bit): address
3550 * offset + 5 (8 bit): count
3551 * offset + 6 (8 bit): data 0
3552 * ...
3553 *
3554 */
3555
3556 struct drm_device *dev = bios->dev;
3557 struct nouveau_i2c_chan *auxch;
3558 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3559 uint8_t count = bios->data[offset + 5];
3560 int len = 6 + count;
6ee73861
BS		 3561 int ret, i;
3562
3563 if (!bios->display.output) {
3564 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
309b8c89 3565 return len;
6ee73861
BS		 3566 }
3567
3568 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3569 if (!auxch) {
3570 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3571 bios->display.output->i2c_index);
309b8c89 3572 return len;
6ee73861
BS		 3573 }
3574
3575 if (!iexec->execute)
37383650 3576 return len;
6ee73861
BS		 3577
3578 offset += 6;
37383650 3579 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3580 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3581 if (ret) {
3582 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3583 return len;
6ee73861
BS		 3584 }
3585 }
3586
37383650 3587 return len;
6ee73861
BS		 3588}
3589
b715d640
MK		 3590static int
3591init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3592{
3593 /*
3594 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3595 *
3596 * offset (8 bit): opcode
3597 * offset + 1 (8 bit): DCB I2C table entry index
3598 * offset + 2 (8 bit): I2C slave address
3599 * offset + 3 (16 bit): I2C register
3600 * offset + 5 (8 bit): mask
3601 * offset + 6 (8 bit): data
3602 *
3603 * Read the register given by "I2C register" on the device addressed
3604 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3605 * entry index". Compare the result AND "mask" to "data".
3606 * If they're not equal, skip subsequent opcodes until condition is
3607 * inverted (INIT_NOT), or we hit INIT_RESUME
3608 */
3609
3610 uint8_t i2c_index = bios->data[offset + 1];
3611 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3612 uint8_t reglo = bios->data[offset + 3];
3613 uint8_t reghi = bios->data[offset + 4];
3614 uint8_t mask = bios->data[offset + 5];
3615 uint8_t data = bios->data[offset + 6];
3616 struct nouveau_i2c_chan *chan;
3617 uint8_t buf0[2] = { reghi, reglo };
3618 uint8_t buf1[1];
3619 struct i2c_msg msg[2] = {
3620 { i2c_address, 0, 1, buf0 },
3621 { i2c_address, I2C_M_RD, 1, buf1 },
3622 };
3623 int ret;
3624
3625 /* no execute check by design */
3626
3627 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3628 offset, i2c_index, i2c_address);
3629
3630 chan = init_i2c_device_find(bios->dev, i2c_index);
3631 if (!chan)
3632 return -ENODEV;
3633
3634
3635 ret = i2c_transfer(&chan->adapter, msg, 2);
3636 if (ret < 0) {
3637 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3638 "Mask: 0x%02X, Data: 0x%02X\n",
3639 offset, reghi, reglo, mask, data);
3640 iexec->execute = 0;
3641 return 7;
3642 }
3643
3644 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3645 "Mask: 0x%02X, Data: 0x%02X\n",
3646 offset, reghi, reglo, buf1[0], mask, data);
3647
3648 iexec->execute = ((buf1[0] & mask) == data);
3649
3650 return 7;
3651}
3652
6ee73861
BS		 3653static struct init_tbl_entry itbl_entry[] = {
3654 /* command name , id , length , offset , mult , command handler */
3655 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3656 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3657 { "INIT_REPEAT" , 0x33, init_repeat },
3658 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3659 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3660 { "INIT_COPY" , 0x37, init_copy },
3661 { "INIT_NOT" , 0x38, init_not },
3662 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3663 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3664 { "INIT_OP_3B" , 0x3B, init_op_3b },
3665 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3666 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3667 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3668 { "INIT_PLL2" , 0x4B, init_pll2 },
3669 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3670 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3671 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3672 { "INIT_TMDS" , 0x4F, init_tmds },
3673 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3674 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3675 { "INIT_CR" , 0x52, init_cr },
3676 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3677 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3678 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
e3a1924f 3679 { "INIT_LTIME" , 0x57, init_ltime },
37383650 3680 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3681 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650 3682 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
ec64a408 3683 { "INIT_JUMP" , 0x5C, init_jump },
b715d640 3684 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
37383650
MK		 3685 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3686 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3687 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3688 { "INIT_RESET" , 0x65, init_reset },
3689 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3690 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3691 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3692 { "INIT_IO" , 0x69, init_io },
3693 { "INIT_SUB" , 0x6B, init_sub },
3694 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3695 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3696 { "INIT_MACRO" , 0x6F, init_macro },
3697 { "INIT_DONE" , 0x71, init_done },
3698 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3699 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3700 { "INIT_TIME" , 0x74, init_time },
3701 { "INIT_CONDITION" , 0x75, init_condition },
3702 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3703 { "INIT_INDEX_IO" , 0x78, init_index_io },
3704 { "INIT_PLL" , 0x79, init_pll },
3705 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3706 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3707 { "INIT_8C" , 0x8C, init_8c },
3708 { "INIT_8D" , 0x8D, init_8d },
3709 { "INIT_GPIO" , 0x8E, init_gpio },
3710 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3711 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3712 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3713 { "INIT_RESERVED" , 0x92, init_reserved },
3714 { "INIT_96" , 0x96, init_96 },
3715 { "INIT_97" , 0x97, init_97 },
3716 { "INIT_AUXCH" , 0x98, init_auxch },
3717 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
b715d640 3718 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
37383650 3719 { NULL , 0 , NULL }
6ee73861
BS		 3720};
3721
6ee73861
BS		 3722#define MAX_TABLE_OPS 1000
3723
3724static int
ec64a408 3725parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
6ee73861
BS		 3726{
3727 /*
3728 * Parses all commands in an init table.
3729 *
3730 * We start out executing all commands found in the init table. Some
3731 * opcodes may change the status of iexec->execute to SKIP, which will
3732 * cause the following opcodes to perform no operation until the value
3733 * is changed back to EXECUTE.
3734 */
3735
92b96187 3736 int count = 0, i, ret;
6ee73861
BS		 3737 uint8_t id;
3738
3739 /*
3740 * Loop until INIT_DONE causes us to break out of the loop
3741 * (or until offset > bios length just in case... )
3742 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3743 */
3744 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3745 id = bios->data[offset];
3746
3747 /* Find matching id in itbl_entry */
3748 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3749 ;
3750
92b96187 3751 if (!itbl_entry[i].name) {
6ee73861
BS		 3752 NV_ERROR(bios->dev,
3753 "0x%04X: Init table command not found: "
3754 "0x%02X\n", offset, id);
3755 return -ENOENT;
3756 }
92b96187
BS		 3757
3758 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3759 itbl_entry[i].id, itbl_entry[i].name);
3760
3761 /* execute eventual command handler */
3762 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3763 if (ret < 0) {
3764 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3765 "table opcode: %s %d\n", offset,
3766 itbl_entry[i].name, ret);
3767 }
3768
3769 if (ret <= 0)
3770 break;
3771
3772 /*
3773 * Add the offset of the current command including all data
3774 * of that command. The offset will then be pointing on the
3775 * next op code.
3776 */
3777 offset += ret;
6ee73861
BS		 3778 }
3779
3780 if (offset >= bios->length)
3781 NV_WARN(bios->dev,
3782 "Offset 0x%04X greater than known bios image length. "
3783 "Corrupt image?\n", offset);
3784 if (count >= MAX_TABLE_OPS)
3785 NV_WARN(bios->dev,
3786 "More than %d opcodes to a table is unlikely, "
3787 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3788
3789 return 0;
3790}
3791
3792static void
3793parse_init_tables(struct nvbios *bios)
3794{
3795 /* Loops and calls parse_init_table() for each present table. */
3796
3797 int i = 0;
3798 uint16_t table;
3799 struct init_exec iexec = {true, false};
3800
3801 if (bios->old_style_init) {
3802 if (bios->init_script_tbls_ptr)
3803 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3804 if (bios->extra_init_script_tbl_ptr)
3805 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3806
3807 return;
3808 }
3809
3810 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3811 NV_INFO(bios->dev,
3812 "Parsing VBIOS init table %d at offset 0x%04X\n",
3813 i / 2, table);
3814 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3815
3816 parse_init_table(bios, table, &iexec);
3817 i += 2;
3818 }
3819}
3820
3821static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3822{
3823 int compare_record_len, i = 0;
3824 uint16_t compareclk, scriptptr = 0;
3825
3826 if (bios->major_version < 5) /* pre BIT */
3827 compare_record_len = 3;
3828 else
3829 compare_record_len = 4;
3830
3831 do {
3832 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3833 if (pxclk >= compareclk * 10) {
3834 if (bios->major_version < 5) {
3835 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3836 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3837 } else
3838 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3839 break;
3840 }
3841 i++;
3842 } while (compareclk);
3843
3844 return scriptptr;
3845}
3846
3847static void
3848run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3849 struct dcb_entry *dcbent, int head, bool dl)
3850{
3851 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3852 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3853 struct init_exec iexec = {true, false};
3854
3855 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3856 scriptptr);
3857 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3858 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3859 /* note: if dcb entries have been merged, index may be misleading */
3860 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3861 parse_init_table(bios, scriptptr, &iexec);
3862
3863 nv04_dfp_bind_head(dev, dcbent, head, dl);
3864}
3865
3866static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3867{
3868 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3869 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3870 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3871 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3872
3873 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3874 return -EINVAL;
3875
3876 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3877
3878 if (script == LVDS_PANEL_OFF) {
3879 /* off-on delay in ms */
c7ca4d1b 3880 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
6ee73861
BS		 3881 }
3882#ifdef __powerpc__
3883 /* Powerbook specific quirks */
d31e078d
FJ		 3884 if (script == LVDS_RESET &&
3885 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3886 dev->pci_device == 0x0329))
3887 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
6ee73861
BS		 3888#endif
3889
3890 return 0;
3891}
3892
3893static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3894{
3895 /*
3896 * The BIT LVDS table's header has the information to setup the
3897 * necessary registers. Following the standard 4 byte header are:
3898 * A bitmask byte and a dual-link transition pxclk value for use in
3899 * selecting the init script when not using straps; 4 script pointers
3900 * for panel power, selected by output and on/off; and 8 table pointers
3901 * for panel init, the needed one determined by output, and bits in the
3902 * conf byte. These tables are similar to the TMDS tables, consisting
3903 * of a list of pxclks and script pointers.
3904 */
3905 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3906 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3907 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3908 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3909
3910 /*
3911 * For now we assume version 3.0 table - g80 support will need some
3912 * changes
3913 */
3914
3915 switch (script) {
3916 case LVDS_INIT:
3917 return -ENOSYS;
3918 case LVDS_BACKLIGHT_ON:
3919 case LVDS_PANEL_ON:
3920 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3921 break;
3922 case LVDS_BACKLIGHT_OFF:
3923 case LVDS_PANEL_OFF:
3924 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3925 break;
3926 case LVDS_RESET:
f3bbb9cc
BS		 3927 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3928 if (dcbent->or == 4)
3929 clktable += 8;
3930
6ee73861
BS		 3931 if (dcbent->lvdsconf.use_straps_for_mode) {
3932 if (bios->fp.dual_link)
f3bbb9cc
BS		 3933 clktable += 4;
3934 if (bios->fp.if_is_24bit)
3935 clktable += 2;
6ee73861
BS		 3936 } else {
3937 /* using EDID */
f3bbb9cc 3938 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3939
3940 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3941 clktable += 4;
3942 cmpval_24bit <<= 1;
6ee73861 3943 }
f3bbb9cc
BS		 3944
3945 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3946 clktable += 2;
6ee73861
BS		 3947 }
3948
f3bbb9cc 3949 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3950 if (!clktable) {
3951 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3952 return -ENOENT;
3953 }
3954 scriptptr = clkcmptable(bios, clktable, pxclk);
3955 }
3956
3957 if (!scriptptr) {
3958 NV_ERROR(dev, "LVDS output init script not found\n");
3959 return -ENOENT;
3960 }
3961 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3962
3963 return 0;
3964}
3965
3966int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3967{
3968 /*
3969 * LVDS operations are multiplexed in an effort to present a single API
3970 * which works with two vastly differing underlying structures.
3971 * This acts as the demux
3972 */
3973
3974 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3975 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3976 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
3977 uint32_t sel_clk_binding, sel_clk;
3978 int ret;
3979
3980 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
3981 (lvds_ver >= 0x30 && script == LVDS_INIT))
3982 return 0;
3983
3984 if (!bios->fp.lvds_init_run) {
3985 bios->fp.lvds_init_run = true;
3986 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
3987 }
3988
3989 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
3990 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
3991 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
3992 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
3993
3994 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
3995
3996 /* don't let script change pll->head binding */
3997 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
3998
3999 if (lvds_ver < 0x30)
4000 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
4001 else
4002 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
4003
4004 bios->fp.last_script_invoc = (script << 1 | head);
4005
4006 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4007 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4008 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
4009 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
4010
4011 return ret;
4012}
4013
4014struct lvdstableheader {
4015 uint8_t lvds_ver, headerlen, recordlen;
4016};
4017
4018static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
4019{
4020 /*
4021 * BMP version (0xa) LVDS table has a simple header of version and
4022 * record length. The BIT LVDS table has the typical BIT table header:
4023 * version byte, header length byte, record length byte, and a byte for
4024 * the maximum number of records that can be held in the table.
4025 */
4026
4027 uint8_t lvds_ver, headerlen, recordlen;
4028
4029 memset(lth, 0, sizeof(struct lvdstableheader));
4030
4031 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
4032 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
4033 return -EINVAL;
4034 }
4035
4036 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4037
4038 switch (lvds_ver) {
4039 case 0x0a: /* pre NV40 */
4040 headerlen = 2;
4041 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4042 break;
4043 case 0x30: /* NV4x */
4044 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4045 if (headerlen < 0x1f) {
4046 NV_ERROR(dev, "LVDS table header not understood\n");
4047 return -EINVAL;
4048 }
4049 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4050 break;
4051 case 0x40: /* G80/G90 */
4052 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4053 if (headerlen < 0x7) {
4054 NV_ERROR(dev, "LVDS table header not understood\n");
4055 return -EINVAL;
4056 }
4057 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4058 break;
4059 default:
4060 NV_ERROR(dev,
4061 "LVDS table revision %d.%d not currently supported\n",
4062 lvds_ver >> 4, lvds_ver & 0xf);
4063 return -ENOSYS;
4064 }
4065
4066 lth->lvds_ver = lvds_ver;
4067 lth->headerlen = headerlen;
4068 lth->recordlen = recordlen;
4069
4070 return 0;
4071}
4072
4073static int
4074get_fp_strap(struct drm_device *dev, struct nvbios *bios)
4075{
4076 struct drm_nouveau_private *dev_priv = dev->dev_private;
4077
4078 /*
4079 * The fp strap is normally dictated by the "User Strap" in
4080 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4081 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4082 * by the PCI subsystem ID during POST, but not before the previous user
4083 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4084 * read and used instead
4085 */
4086
4087 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4088 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4089
4090 if (dev_priv->card_type >= NV_50)
4091 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4092 else
4093 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4094}
4095
4096static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4097{
4098 uint8_t *fptable;
4099 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4100 int ret, ofs, fpstrapping;
4101 struct lvdstableheader lth;
4102
4103 if (bios->fp.fptablepointer == 0x0) {
4104 /* Apple cards don't have the fp table; the laptops use DDC */
4105 /* The table is also missing on some x86 IGPs */
4106#ifndef __powerpc__
4107 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4108#endif
04a39c57 4109 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4110 return 0;
4111 }
4112
4113 fptable = &bios->data[bios->fp.fptablepointer];
4114 fptable_ver = fptable[0];
4115
4116 switch (fptable_ver) {
4117 /*
4118 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4119 * version field, and miss one of the spread spectrum/PWM bytes.
4120 * This could affect early GF2Go parts (not seen any appropriate ROMs
4121 * though). Here we assume that a version of 0x05 matches this case
4122 * (combining with a BMP version check would be better), as the
4123 * common case for the panel type field is 0x0005, and that is in
4124 * fact what we are reading the first byte of.
4125 */
4126 case 0x05: /* some NV10, 11, 15, 16 */
4127 recordlen = 42;
4128 ofs = -1;
4129 break;
4130 case 0x10: /* some NV15/16, and NV11+ */
4131 recordlen = 44;
4132 ofs = 0;
4133 break;
4134 case 0x20: /* NV40+ */
4135 headerlen = fptable[1];
4136 recordlen = fptable[2];
4137 fpentries = fptable[3];
4138 /*
4139 * fptable[4] is the minimum
4140 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4141 */
04a39c57 4142 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 4143 ofs = -7;
4144 break;
4145 default:
4146 NV_ERROR(dev,
4147 "FP table revision %d.%d not currently supported\n",
4148 fptable_ver >> 4, fptable_ver & 0xf);
4149 return -ENOSYS;
4150 }
4151
4152 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4153 return 0;
4154
4155 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4156 if (ret)
4157 return ret;
4158
4159 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4160 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4161 lth.headerlen + 1;
4162 bios->fp.xlatwidth = lth.recordlen;
4163 }
4164 if (bios->fp.fpxlatetableptr == 0x0) {
4165 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4166 return -EINVAL;
4167 }
4168
4169 fpstrapping = get_fp_strap(dev, bios);
4170
4171 fpindex = bios->data[bios->fp.fpxlatetableptr +
4172 fpstrapping * bios->fp.xlatwidth];
4173
4174 if (fpindex > fpentries) {
4175 NV_ERROR(dev, "Bad flat panel table index\n");
4176 return -ENOENT;
4177 }
4178
4179 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4180 if (lth.lvds_ver > 0x10)
04a39c57 4181 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 4182
4183 /*
4184 * If either the strap or xlated fpindex value are 0xf there is no
4185 * panel using a strap-derived bios mode present. this condition
4186 * includes, but is different from, the DDC panel indicator above
4187 */
4188 if (fpstrapping == 0xf || fpindex == 0xf)
4189 return 0;
4190
4191 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4192 recordlen * fpindex + ofs;
4193
4194 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4195 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4196 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4197 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4198
4199 return 0;
4200}
4201
4202bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4203{
4204 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4205 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4206 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4207
4208 if (!mode) /* just checking whether we can produce a mode */
4209 return bios->fp.mode_ptr;
4210
4211 memset(mode, 0, sizeof(struct drm_display_mode));
4212 /*
4213 * For version 1.0 (version in byte 0):
4214 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4215 * single/dual link, and type (TFT etc.)
4216 * bytes 3-6 are bits per colour in RGBX
4217 */
4218 mode->clock = ROM16(mode_entry[7]) * 10;
4219 /* bytes 9-10 is HActive */
4220 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4221 /*
4222 * bytes 13-14 is HValid Start
4223 * bytes 15-16 is HValid End
4224 */
4225 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4226 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4227 mode->htotal = ROM16(mode_entry[21]) + 1;
4228 /* bytes 23-24, 27-30 similarly, but vertical */
4229 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4230 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4231 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4232 mode->vtotal = ROM16(mode_entry[35]) + 1;
4233 mode->flags |= (mode_entry[37] & 0x10) ?
4234 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4235 mode->flags |= (mode_entry[37] & 0x1) ?
4236 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4237 /*
4238 * bytes 38-39 relate to spread spectrum settings
4239 * bytes 40-43 are something to do with PWM
4240 */
4241
4242 mode->status = MODE_OK;
4243 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4244 drm_mode_set_name(mode);
4245 return bios->fp.mode_ptr;
4246}
4247
4248int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4249{
4250 /*
4251 * The LVDS table header is (mostly) described in
4252 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4253 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4254 * straps are not being used for the panel, this specifies the frequency
4255 * at which modes should be set up in the dual link style.
4256 *
4257 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 4258 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 4259 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4260 * numbers for use by INIT_SUB which controlled panel init and power,
4261 * and finally a dword of ms to sleep between power off and on
4262 * operations.
4263 *
4264 * In the BIT versions, the table following the header serves as an
4265 * integrated config and xlat table: the records in the table are
4266 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4267 * two bytes - the first as a config byte, the second for indexing the
4268 * fp mode table pointed to by the BIT 'D' table
4269 *
4270 * DDC is not used until after card init, so selecting the correct table
4271 * entry and setting the dual link flag for EDID equipped panels,
4272 * requiring tests against the native-mode pixel clock, cannot be done
4273 * until later, when this function should be called with non-zero pxclk
4274 */
4275 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4276 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4277 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4278 struct lvdstableheader lth;
4279 uint16_t lvdsofs;
04a39c57 4280 int ret, chip_version = bios->chip_version;
6ee73861
BS		 4281
4282 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4283 if (ret)
4284 return ret;
4285
4286 switch (lth.lvds_ver) {
4287 case 0x0a: /* pre NV40 */
4288 lvdsmanufacturerindex = bios->data[
4289 bios->fp.fpxlatemanufacturertableptr +
4290 fpstrapping];
4291
4292 /* we're done if this isn't the EDID panel case */
4293 if (!pxclk)
4294 break;
4295
4296 if (chip_version < 0x25) {
4297 /* nv17 behaviour
4298 *
4299 * It seems the old style lvds script pointer is reused
4300 * to select 18/24 bit colour depth for EDID panels.
4301 */
4302 lvdsmanufacturerindex =
4303 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4304 2 : 0;
4305 if (pxclk >= bios->fp.duallink_transition_clk)
4306 lvdsmanufacturerindex++;
4307 } else if (chip_version < 0x30) {
4308 /* nv28 behaviour (off-chip encoder)
4309 *
4310 * nv28 does a complex dance of first using byte 121 of
4311 * the EDID to choose the lvdsmanufacturerindex, then
4312 * later attempting to match the EDID manufacturer and
4313 * product IDs in a table (signature 'pidt' (panel id
4314 * table?)), setting an lvdsmanufacturerindex of 0 and
4315 * an fp strap of the match index (or 0xf if none)
4316 */
4317 lvdsmanufacturerindex = 0;
4318 } else {
4319 /* nv31, nv34 behaviour */
4320 lvdsmanufacturerindex = 0;
4321 if (pxclk >= bios->fp.duallink_transition_clk)
4322 lvdsmanufacturerindex = 2;
4323 if (pxclk >= 140000)
4324 lvdsmanufacturerindex = 3;
4325 }
4326
4327 /*
4328 * nvidia set the high nibble of (cr57=f, cr58) to
4329 * lvdsmanufacturerindex in this case; we don't
4330 */
4331 break;
4332 case 0x30: /* NV4x */
4333 case 0x40: /* G80/G90 */
4334 lvdsmanufacturerindex = fpstrapping;
4335 break;
4336 default:
4337 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4338 return -ENOSYS;
4339 }
4340
4341 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4342 switch (lth.lvds_ver) {
4343 case 0x0a:
4344 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4345 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4346 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4347 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4348 *if_is_24bit = bios->data[lvdsofs] & 16;
4349 break;
4350 case 0x30:
f3bbb9cc 4351 case 0x40:
6ee73861
BS		 4352 /*
4353 * No sign of the "power off for reset" or "reset for panel
4354 * on" bits, but it's safer to assume we should
4355 */
4356 bios->fp.power_off_for_reset = true;
4357 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 4358
6ee73861
BS		 4359 /*
4360 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 4361 * over-written, and if_is_24bit isn't used
6ee73861
BS		 4362 */
4363 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 4364 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4365 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4366 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4367 break;
4368 }
4369
2eb92c80
BS		 4370 /* Dell Latitude D620 reports a too-high value for the dual-link
4371 * transition freq, causing us to program the panel incorrectly.
4372 *
4373 * It doesn't appear the VBIOS actually uses its transition freq
4374 * (90000kHz), instead it uses the "Number of LVDS channels" field
4375 * out of the panel ID structure (http://www.spwg.org/).
4376 *
4377 * For the moment, a quirk will do :)
4378 */
acae116c 4379 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
2eb92c80 4380 bios->fp.duallink_transition_clk = 80000;
2eb92c80 4381
6ee73861
BS		 4382 /* set dual_link flag for EDID case */
4383 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4384 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4385
4386 *dl = bios->fp.dual_link;
4387
4388 return 0;
4389}
4390
4391static uint8_t *
4392bios_output_config_match(struct drm_device *dev, struct dcb_entry *dcbent,
1eb38100
BS		 4393 uint16_t record, int record_len, int record_nr,
4394 bool match_link)
6ee73861
BS		 4395{
4396 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4397 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4398 uint32_t entry;
4399 uint16_t table;
4400 int i, v;
4401
1eb38100
BS		 4402 switch (dcbent->type) {
4403 case OUTPUT_TMDS:
4404 case OUTPUT_LVDS:
4405 case OUTPUT_DP:
4406 break;
4407 default:
4408 match_link = false;
4409 break;
4410 }
4411
6ee73861
BS		 4412 for (i = 0; i < record_nr; i++, record += record_len) {
4413 table = ROM16(bios->data[record]);
4414 if (!table)
4415 continue;
4416 entry = ROM32(bios->data[table]);
4417
1eb38100
BS		 4418 if (match_link) {
4419 v = (entry & 0x00c00000) >> 22;
4420 if (!(v & dcbent->sorconf.link))
4421 continue;
4422 }
4423
6ee73861
BS		 4424 v = (entry & 0x000f0000) >> 16;
4425 if (!(v & dcbent->or))
4426 continue;
4427
4428 v = (entry & 0x000000f0) >> 4;
4429 if (v != dcbent->location)
4430 continue;
4431
4432 v = (entry & 0x0000000f);
4433 if (v != dcbent->type)
4434 continue;
4435
4436 return &bios->data[table];
4437 }
4438
4439 return NULL;
4440}
4441
4442void *
4443nouveau_bios_dp_table(struct drm_device *dev, struct dcb_entry *dcbent,
4444 int *length)
4445{
4446 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4447 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4448 uint8_t *table;
4449
4450 if (!bios->display.dp_table_ptr) {
4451 NV_ERROR(dev, "No pointer to DisplayPort table\n");
4452 return NULL;
4453 }
4454 table = &bios->data[bios->display.dp_table_ptr];
4455
c52e53fd 4456 if (table[0] != 0x20 && table[0] != 0x21) {
6ee73861
BS		 4457 NV_ERROR(dev, "DisplayPort table version 0x%02x unknown\n",
4458 table[0]);
4459 return NULL;
4460 }
4461
4462 *length = table[4];
4463 return bios_output_config_match(dev, dcbent,
4464 bios->display.dp_table_ptr + table[1],
1eb38100 4465 table[2], table[3], table[0] >= 0x21);
6ee73861
BS		 4466}
4467
4468int
4469nouveau_bios_run_display_table(struct drm_device *dev, struct dcb_entry *dcbent,
4470 uint32_t sub, int pxclk)
4471{
4472 /*
4473 * The display script table is located by the BIT 'U' table.
4474 *
4475 * It contains an array of pointers to various tables describing
4476 * a particular output type. The first 32-bits of the output
4477 * tables contains similar information to a DCB entry, and is
4478 * used to decide whether that particular table is suitable for
4479 * the output you want to access.
4480 *
4481 * The "record header length" field here seems to indicate the
4482 * offset of the first configuration entry in the output tables.
4483 * This is 10 on most cards I've seen, but 12 has been witnessed
4484 * on DP cards, and there's another script pointer within the
4485 * header.
4486 *
4487 * offset + 0 ( 8 bits): version
4488 * offset + 1 ( 8 bits): header length
4489 * offset + 2 ( 8 bits): record length
4490 * offset + 3 ( 8 bits): number of records
4491 * offset + 4 ( 8 bits): record header length
4492 * offset + 5 (16 bits): pointer to first output script table
4493 */
4494
4495 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4496 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4497 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4498 uint8_t *otable = NULL;
4499 uint16_t script;
4500 int i = 0;
4501
4502 if (!bios->display.script_table_ptr) {
4503 NV_ERROR(dev, "No pointer to output script table\n");
4504 return 1;
4505 }
4506
4507 /*
4508 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4509 * so until they are, we really don't need to care.
4510 */
4511 if (table[0] < 0x20)
4512 return 1;
4513
4514 if (table[0] != 0x20 && table[0] != 0x21) {
4515 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4516 table[0]);
4517 return 1;
4518 }
4519
4520 /*
4521 * The output script tables describing a particular output type
4522 * look as follows:
4523 *
4524 * offset + 0 (32 bits): output this table matches (hash of DCB)
4525 * offset + 4 ( 8 bits): unknown
4526 * offset + 5 ( 8 bits): number of configurations
4527 * offset + 6 (16 bits): pointer to some script
4528 * offset + 8 (16 bits): pointer to some script
4529 *
4530 * headerlen == 10
4531 * offset + 10 : configuration 0
4532 *
4533 * headerlen == 12
4534 * offset + 10 : pointer to some script
4535 * offset + 12 : configuration 0
4536 *
4537 * Each config entry is as follows:
4538 *
4539 * offset + 0 (16 bits): unknown, assumed to be a match value
4540 * offset + 2 (16 bits): pointer to script table (clock set?)
4541 * offset + 4 (16 bits): pointer to script table (reset?)
4542 *
4543 * There doesn't appear to be a count value to say how many
4544 * entries exist in each script table, instead, a 0 value in
4545 * the first 16-bit word seems to indicate both the end of the
4546 * list and the default entry. The second 16-bit word in the
4547 * script tables is a pointer to the script to execute.
4548 */
4549
ef2bb506 4550 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861
BS		 4551 dcbent->type, dcbent->location, dcbent->or);
4552 otable = bios_output_config_match(dev, dcbent, table[1] +
4553 bios->display.script_table_ptr,
1eb38100 4554 table[2], table[3], table[0] >= 0x21);
6ee73861 4555 if (!otable) {
54bf67de 4556 NV_DEBUG_KMS(dev, "failed to match any output table\n");
6ee73861
BS		 4557 return 1;
4558 }
4559
4560 if (pxclk < -2 || pxclk > 0) {
4561 /* Try to find matching script table entry */
4562 for (i = 0; i < otable[5]; i++) {
4563 if (ROM16(otable[table[4] + i*6]) == sub)
4564 break;
4565 }
4566
4567 if (i == otable[5]) {
4568 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4569 "using first\n",
4570 sub, dcbent->type, dcbent->or);
4571 i = 0;
4572 }
4573 }
4574
6ee73861
BS		 4575 if (pxclk == 0) {
4576 script = ROM16(otable[6]);
4577 if (!script) {
ef2bb506 4578 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4579 return 1;
4580 }
4581
45a68a07 4582 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
39c9bfb4 4583 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4584 } else
4585 if (pxclk == -1) {
4586 script = ROM16(otable[8]);
4587 if (!script) {
ef2bb506 4588 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4589 return 1;
4590 }
4591
45a68a07 4592 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
39c9bfb4 4593 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4594 } else
4595 if (pxclk == -2) {
4596 if (table[4] >= 12)
4597 script = ROM16(otable[10]);
4598 else
4599 script = 0;
4600 if (!script) {
ef2bb506 4601 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4602 return 1;
4603 }
4604
45a68a07 4605 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
39c9bfb4 4606 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4607 } else
4608 if (pxclk > 0) {
4609 script = ROM16(otable[table[4] + i*6 + 2]);
4610 if (script)
4611 script = clkcmptable(bios, script, pxclk);
4612 if (!script) {
54bf67de 4613 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
6ee73861
BS		 4614 return 1;
4615 }
4616
45a68a07 4617 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
39c9bfb4 4618 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4619 } else
4620 if (pxclk < 0) {
4621 script = ROM16(otable[table[4] + i*6 + 4]);
4622 if (script)
4623 script = clkcmptable(bios, script, -pxclk);
4624 if (!script) {
ef2bb506 4625 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4626 return 1;
4627 }
4628
45a68a07 4629 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
39c9bfb4 4630 nouveau_bios_run_init_table(dev, script, dcbent);
6ee73861
BS		 4631 }
4632
4633 return 0;
4634}
4635
4636
4637int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4638{
4639 /*
4640 * the pxclk parameter is in kHz
4641 *
4642 * This runs the TMDS regs setting code found on BIT bios cards
4643 *
4644 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4645 * ffs(or) == 3, use the second.
4646 */
4647
4648 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4649 struct nvbios *bios = &dev_priv->vbios;
4650 int cv = bios->chip_version;
6ee73861
BS		 4651 uint16_t clktable = 0, scriptptr;
4652 uint32_t sel_clk_binding, sel_clk;
4653
4654 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4655 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4656 dcbent->location != DCB_LOC_ON_CHIP)
4657 return 0;
4658
4659 switch (ffs(dcbent->or)) {
4660 case 1:
4661 clktable = bios->tmds.output0_script_ptr;
4662 break;
4663 case 2:
4664 case 3:
4665 clktable = bios->tmds.output1_script_ptr;
4666 break;
4667 }
4668
4669 if (!clktable) {
4670 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4671 return -EINVAL;
4672 }
4673
4674 scriptptr = clkcmptable(bios, clktable, pxclk);
4675
4676 if (!scriptptr) {
4677 NV_ERROR(dev, "TMDS output init script not found\n");
4678 return -ENOENT;
4679 }
4680
4681 /* don't let script change pll->head binding */
4682 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4683 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4684 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4685 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4686
4687 return 0;
4688}
4689
855a95e4
BS		 4690struct pll_mapping {
4691 u8 type;
4692 u32 reg;
4693};
4694
4695static struct pll_mapping nv04_pll_mapping[] = {
4696 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4697 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4698 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4699 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4700 {}
4701};
4702
4703static struct pll_mapping nv40_pll_mapping[] = {
4704 { PLL_CORE , 0x004000 },
4705 { PLL_MEMORY, 0x004020 },
4706 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4707 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4708 {}
4709};
4710
4711static struct pll_mapping nv50_pll_mapping[] = {
4712 { PLL_CORE , 0x004028 },
4713 { PLL_SHADER, 0x004020 },
4714 { PLL_UNK03 , 0x004000 },
4715 { PLL_MEMORY, 0x004008 },
4716 { PLL_UNK40 , 0x00e810 },
4717 { PLL_UNK41 , 0x00e818 },
4718 { PLL_UNK42 , 0x00e824 },
4719 { PLL_VPLL0 , 0x614100 },
4720 { PLL_VPLL1 , 0x614900 },
4721 {}
4722};
4723
4724static struct pll_mapping nv84_pll_mapping[] = {
4725 { PLL_CORE , 0x004028 },
4726 { PLL_SHADER, 0x004020 },
4727 { PLL_MEMORY, 0x004008 },
4728 { PLL_UNK05 , 0x004030 },
4729 { PLL_UNK41 , 0x00e818 },
4730 { PLL_VPLL0 , 0x614100 },
4731 { PLL_VPLL1 , 0x614900 },
4732 {}
4733};
4734
4735u32
4736get_pll_register(struct drm_device *dev, enum pll_types type)
4737{
4738 struct drm_nouveau_private *dev_priv = dev->dev_private;
4739 struct nvbios *bios = &dev_priv->vbios;
4740 struct pll_mapping *map;
4741 int i;
4742
4743 if (dev_priv->card_type < NV_40)
4744 map = nv04_pll_mapping;
4745 else
4746 if (dev_priv->card_type < NV_50)
4747 map = nv40_pll_mapping;
4748 else {
4749 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4750
56edd964 4751 if (plim[0] >= 0x30) {
855a95e4
BS		 4752 u8 *entry = plim + plim[1];
4753 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4754 if (entry[0] == type)
4755 return ROM32(entry[3]);
4756 }
4757
4758 return 0;
4759 }
4760
4761 if (dev_priv->chipset == 0x50)
4762 map = nv50_pll_mapping;
4763 else
4764 map = nv84_pll_mapping;
4765 }
4766
4767 while (map->reg) {
4768 if (map->type == type)
4769 return map->reg;
4770 map++;
4771 }
4772
4773 return 0;
4774}
4775
6ee73861
BS		 4776int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4777{
4778 /*
4779 * PLL limits table
4780 *
4781 * Version 0x10: NV30, NV31
4782 * One byte header (version), one record of 24 bytes
4783 * Version 0x11: NV36 - Not implemented
4784 * Seems to have same record style as 0x10, but 3 records rather than 1
4785 * Version 0x20: Found on Geforce 6 cards
4786 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4787 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4788 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4789 * length in general, some (integrated) have an extra configuration byte
4790 * Version 0x30: Found on Geforce 8, separates the register mapping
4791 * from the limits tables.
4792 */
4793
4794 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4795 struct nvbios *bios = &dev_priv->vbios;
4796 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4797 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4798 uint32_t crystal_strap_mask, crystal_straps;
4799
4800 if (!bios->pll_limit_tbl_ptr) {
4801 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4802 cv >= 0x40) {
4803 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4804 return -EINVAL;
4805 }
4806 } else
4807 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4808
4809 crystal_strap_mask = 1 << 6;
4810 /* open coded dev->twoHeads test */
4811 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4812 crystal_strap_mask |= 1 << 22;
4813 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4814 crystal_strap_mask;
4815
4816 switch (pll_lim_ver) {
4817 /*
4818 * We use version 0 to indicate a pre limit table bios (single stage
4819 * pll) and load the hard coded limits instead.
4820 */
4821 case 0:
4822 break;
4823 case 0x10:
4824 case 0x11:
4825 /*
4826 * Strictly v0x11 has 3 entries, but the last two don't seem
4827 * to get used.
4828 */
4829 headerlen = 1;
4830 recordlen = 0x18;
4831 entries = 1;
4832 pllindex = 0;
4833 break;
4834 case 0x20:
4835 case 0x21:
4836 case 0x30:
4837 case 0x40:
4838 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4839 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4840 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4841 break;
4842 default:
4843 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4844 "supported\n", pll_lim_ver);
4845 return -ENOSYS;
4846 }
4847
4848 /* initialize all members to zero */
4849 memset(pll_lim, 0, sizeof(struct pll_lims));
4850
855a95e4
BS		 4851 /* if we were passed a type rather than a register, figure
4852 * out the register and store it
4853 */
4854 if (limit_match > PLL_MAX)
4855 pll_lim->reg = limit_match;
6f876986 4856 else {
855a95e4 4857 pll_lim->reg = get_pll_register(dev, limit_match);
6f876986
BS		 4858 if (!pll_lim->reg)
4859 return -ENOENT;
4860 }
855a95e4 4861
6ee73861
BS		 4862 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4863 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4864
4865 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4866 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4867 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4868 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4869 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4870 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4871 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4872
4873 /* these values taken from nv30/31/36 */
4874 pll_lim->vco1.min_n = 0x1;
4875 if (cv == 0x36)
4876 pll_lim->vco1.min_n = 0x5;
4877 pll_lim->vco1.max_n = 0xff;
4878 pll_lim->vco1.min_m = 0x1;
4879 pll_lim->vco1.max_m = 0xd;
4880 pll_lim->vco2.min_n = 0x4;
4881 /*
4882 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4883 * table version (apart from nv35)), N2 is compared to
4884 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4885 * save a comparison
4886 */
4887 pll_lim->vco2.max_n = 0x28;
4888 if (cv == 0x30 || cv == 0x35)
4889 /* only 5 bits available for N2 on nv30/35 */
4890 pll_lim->vco2.max_n = 0x1f;
4891 pll_lim->vco2.min_m = 0x1;
4892 pll_lim->vco2.max_m = 0x4;
4893 pll_lim->max_log2p = 0x7;
4894 pll_lim->max_usable_log2p = 0x6;
4895 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4896 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
6ee73861
BS		 4897 uint8_t *pll_rec;
4898 int i;
4899
4900 /*
4901 * First entry is default match, if nothing better. warn if
4902 * reg field nonzero
4903 */
4904 if (ROM32(bios->data[plloffs]))
4905 NV_WARN(dev, "Default PLL limit entry has non-zero "
4906 "register field\n");
4907
6ee73861 4908 for (i = 1; i < entries; i++)
855a95e4 4909 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
6ee73861
BS		 4910 pllindex = i;
4911 break;
4912 }
4913
eadc69cc
EV		 4914 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4915 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4916 "limits table", pll_lim->reg);
4917 return -ENOENT;
4918 }
4919
6ee73861
BS		 4920 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4921
4922 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
855a95e4 4923 pllindex ? pll_lim->reg : 0);
6ee73861
BS		 4924
4925 /*
4926 * Frequencies are stored in tables in MHz, kHz are more
4927 * useful, so we convert.
4928 */
4929
4930 /* What output frequencies can each VCO generate? */
4931 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4932 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4933 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4934 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4935
4936 /* What input frequencies they accept (past the m-divider)? */
4937 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4938 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4939 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4940 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4941
4942 /* What values are accepted as multiplier and divider? */
4943 pll_lim->vco1.min_n = pll_rec[20];
4944 pll_lim->vco1.max_n = pll_rec[21];
4945 pll_lim->vco1.min_m = pll_rec[22];
4946 pll_lim->vco1.max_m = pll_rec[23];
4947 pll_lim->vco2.min_n = pll_rec[24];
4948 pll_lim->vco2.max_n = pll_rec[25];
4949 pll_lim->vco2.min_m = pll_rec[26];
4950 pll_lim->vco2.max_m = pll_rec[27];
4951
4952 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4953 if (pll_lim->max_log2p > 0x7)
4954 /* pll decoding in nv_hw.c assumes never > 7 */
4955 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4956 pll_lim->max_log2p);
4957 if (cv < 0x60)
4958 pll_lim->max_usable_log2p = 0x6;
4959 pll_lim->log2p_bias = pll_rec[30];
4960
4961 if (recordlen > 0x22)
4962 pll_lim->refclk = ROM32(pll_rec[31]);
4963
4964 if (recordlen > 0x23 && pll_rec[35])
4965 NV_WARN(dev,
4966 "Bits set in PLL configuration byte (%x)\n",
4967 pll_rec[35]);
4968
4969 /* C51 special not seen elsewhere */
4970 if (cv == 0x51 && !pll_lim->refclk) {
4971 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4972
855a95e4
BS		 4973 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4974 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
6ee73861
BS		 4975 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4976 pll_lim->refclk = 200000;
4977 else
4978 pll_lim->refclk = 25000;
4979 }
4980 }
4981 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4982 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4983 uint8_t *record = NULL;
4984 int i;
4985
4986 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 4987 pll_lim->reg);
6ee73861
BS		 4988
4989 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 4990 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 4991 record = &bios->data[ROM16(entry[1])];
4992 break;
4993 }
4994 }
4995
4996 if (!record) {
4997 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 4998 "limits table", pll_lim->reg);
6ee73861
BS		 4999 return -ENOENT;
5000 }
5001
5002 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
5003 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
5004 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
5005 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
5006 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
5007 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
5008 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
5009 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
5010 pll_lim->vco1.min_n = record[16];
5011 pll_lim->vco1.max_n = record[17];
5012 pll_lim->vco1.min_m = record[18];
5013 pll_lim->vco1.max_m = record[19];
5014 pll_lim->vco2.min_n = record[20];
5015 pll_lim->vco2.max_n = record[21];
5016 pll_lim->vco2.min_m = record[22];
5017 pll_lim->vco2.max_m = record[23];
5018 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
5019 pll_lim->log2p_bias = record[27];
5020 pll_lim->refclk = ROM32(record[28]);
5021 } else if (pll_lim_ver) { /* ver 0x40 */
5022 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
5023 uint8_t *record = NULL;
5024 int i;
5025
5026 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 5027 pll_lim->reg);
6ee73861
BS		 5028
5029 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 5030 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 5031 record = &bios->data[ROM16(entry[1])];
5032 break;
5033 }
5034 }
5035
5036 if (!record) {
5037 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 5038 "limits table", pll_lim->reg);
6ee73861
BS		 5039 return -ENOENT;
5040 }
5041
5042 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
5043 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
5044 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
5045 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
5046 pll_lim->vco1.min_m = record[8];
5047 pll_lim->vco1.max_m = record[9];
5048 pll_lim->vco1.min_n = record[10];
5049 pll_lim->vco1.max_n = record[11];
5050 pll_lim->min_p = record[12];
5051 pll_lim->max_p = record[13];
ce521846 5052 pll_lim->refclk = ROM16(entry[9]) * 1000;
6ee73861
BS		 5053 }
5054
5055 /*
5056 * By now any valid limit table ought to have set a max frequency for
5057 * vco1, so if it's zero it's either a pre limit table bios, or one
5058 * with an empty limit table (seen on nv18)
5059 */
5060 if (!pll_lim->vco1.maxfreq) {
5061 pll_lim->vco1.minfreq = bios->fminvco;
5062 pll_lim->vco1.maxfreq = bios->fmaxvco;
5063 pll_lim->vco1.min_inputfreq = 0;
5064 pll_lim->vco1.max_inputfreq = INT_MAX;
5065 pll_lim->vco1.min_n = 0x1;
5066 pll_lim->vco1.max_n = 0xff;
5067 pll_lim->vco1.min_m = 0x1;
5068 if (crystal_straps == 0) {
5069 /* nv05 does this, nv11 doesn't, nv10 unknown */
5070 if (cv < 0x11)
5071 pll_lim->vco1.min_m = 0x7;
5072 pll_lim->vco1.max_m = 0xd;
5073 } else {
5074 if (cv < 0x11)
5075 pll_lim->vco1.min_m = 0x8;
5076 pll_lim->vco1.max_m = 0xe;
5077 }
5078 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
5079 pll_lim->max_log2p = 4;
5080 else
5081 pll_lim->max_log2p = 5;
5082 pll_lim->max_usable_log2p = pll_lim->max_log2p;
5083 }
5084
5085 if (!pll_lim->refclk)
5086 switch (crystal_straps) {
5087 case 0:
5088 pll_lim->refclk = 13500;
5089 break;
5090 case (1 << 6):
5091 pll_lim->refclk = 14318;
5092 break;
5093 case (1 << 22):
5094 pll_lim->refclk = 27000;
5095 break;
5096 case (1 << 22 | 1 << 6):
5097 pll_lim->refclk = 25000;
5098 break;
5099 }
5100
4c389f00
BS		 5101 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
5102 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
5103 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
5104 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
5105 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
5106 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
5107 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
5108 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
5109 if (pll_lim->vco2.maxfreq) {
5110 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
5111 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
5112 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
5113 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
5114 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
5115 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
5116 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
5117 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
5118 }
5119 if (!pll_lim->max_p) {
5120 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
5121 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
5122 } else {
5123 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
5124 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
5125 }
5126 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 5127
5128 return 0;
5129}
5130
5131static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
5132{
5133 /*
5134 * offset + 0 (8 bits): Micro version
5135 * offset + 1 (8 bits): Minor version
5136 * offset + 2 (8 bits): Chip version
5137 * offset + 3 (8 bits): Major version
5138 */
5139
5140 bios->major_version = bios->data[offset + 3];
04a39c57 5141 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 5142 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5143 bios->data[offset + 3], bios->data[offset + 2],
5144 bios->data[offset + 1], bios->data[offset]);
5145}
5146
5147static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5148{
5149 /*
5150 * Parses the init table segment for pointers used in script execution.
5151 *
5152 * offset + 0 (16 bits): init script tables pointer
5153 * offset + 2 (16 bits): macro index table pointer
5154 * offset + 4 (16 bits): macro table pointer
5155 * offset + 6 (16 bits): condition table pointer
5156 * offset + 8 (16 bits): io condition table pointer
5157 * offset + 10 (16 bits): io flag condition table pointer
5158 * offset + 12 (16 bits): init function table pointer
5159 */
5160
5161 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5162 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5163 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5164 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5165 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5166 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5167 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5168}
5169
5170static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5171{
5172 /*
5173 * Parses the load detect values for g80 cards.
5174 *
5175 * offset + 0 (16 bits): loadval table pointer
5176 */
5177
5178 uint16_t load_table_ptr;
5179 uint8_t version, headerlen, entrylen, num_entries;
5180
5181 if (bitentry->length != 3) {
5182 NV_ERROR(dev, "Do not understand BIT A table\n");
5183 return -EINVAL;
5184 }
5185
5186 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5187
5188 if (load_table_ptr == 0x0) {
5189 NV_ERROR(dev, "Pointer to BIT loadval table invalid\n");
5190 return -EINVAL;
5191 }
5192
5193 version = bios->data[load_table_ptr];
5194
5195 if (version != 0x10) {
5196 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5197 version >> 4, version & 0xF);
5198 return -ENOSYS;
5199 }
5200
5201 headerlen = bios->data[load_table_ptr + 1];
5202 entrylen = bios->data[load_table_ptr + 2];
5203 num_entries = bios->data[load_table_ptr + 3];
5204
5205 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5206 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5207 return -EINVAL;
5208 }
5209
5210 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 5211 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 5212
5213 return 0;
5214}
5215
5216static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5217{
5218 /*
5219 * offset + 8 (16 bits): PLL limits table pointer
5220 *
5221 * There's more in here, but that's unknown.
5222 */
5223
5224 if (bitentry->length < 10) {
5225 NV_ERROR(dev, "Do not understand BIT C table\n");
5226 return -EINVAL;
5227 }
5228
5229 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5230
5231 return 0;
5232}
5233
5234static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5235{
5236 /*
5237 * Parses the flat panel table segment that the bit entry points to.
5238 * Starting at bitentry->offset:
5239 *
5240 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5241 * records beginning with a freq.
5242 * offset + 2 (16 bits): mode table pointer
5243 */
5244
5245 if (bitentry->length != 4) {
5246 NV_ERROR(dev, "Do not understand BIT display table\n");
5247 return -EINVAL;
5248 }
5249
5250 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5251
5252 return 0;
5253}
5254
5255static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5256{
5257 /*
5258 * Parses the init table segment that the bit entry points to.
5259 *
5260 * See parse_script_table_pointers for layout
5261 */
5262
5263 if (bitentry->length < 14) {
5264 NV_ERROR(dev, "Do not understand init table\n");
5265 return -EINVAL;
5266 }
5267
5268 parse_script_table_pointers(bios, bitentry->offset);
5269
5270 if (bitentry->length >= 16)
5271 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5272 if (bitentry->length >= 18)
5273 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5274
5275 return 0;
5276}
5277
5278static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5279{
5280 /*
5281 * BIT 'i' (info?) table
5282 *
5283 * offset + 0 (32 bits): BIOS version dword (as in B table)
5284 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5285 * offset + 13 (16 bits): pointer to table containing DAC load
5286 * detection comparison values
5287 *
5288 * There's other things in the table, purpose unknown
5289 */
5290
5291 uint16_t daccmpoffset;
5292 uint8_t dacver, dacheaderlen;
5293
5294 if (bitentry->length < 6) {
5295 NV_ERROR(dev, "BIT i table too short for needed information\n");
5296 return -EINVAL;
5297 }
5298
5299 parse_bios_version(dev, bios, bitentry->offset);
5300
5301 /*
5302 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5303 * Quadro identity crisis), other bits possibly as for BMP feature byte
5304 */
5305 bios->feature_byte = bios->data[bitentry->offset + 5];
5306 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5307
5308 if (bitentry->length < 15) {
5309 NV_WARN(dev, "BIT i table not long enough for DAC load "
5310 "detection comparison table\n");
5311 return -EINVAL;
5312 }
5313
5314 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5315
5316 /* doesn't exist on g80 */
5317 if (!daccmpoffset)
5318 return 0;
5319
5320 /*
5321 * The first value in the table, following the header, is the
5322 * comparison value, the second entry is a comparison value for
5323 * TV load detection.
5324 */
5325
5326 dacver = bios->data[daccmpoffset];
5327 dacheaderlen = bios->data[daccmpoffset + 1];
5328
5329 if (dacver != 0x00 && dacver != 0x10) {
5330 NV_WARN(dev, "DAC load detection comparison table version "
5331 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5332 return -ENOSYS;
5333 }
5334
04a39c57
BS		 5335 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5336 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 5337
5338 return 0;
5339}
5340
5341static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5342{
5343 /*
5344 * Parses the LVDS table segment that the bit entry points to.
5345 * Starting at bitentry->offset:
5346 *
5347 * offset + 0 (16 bits): LVDS strap xlate table pointer
5348 */
5349
5350 if (bitentry->length != 2) {
5351 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5352 return -EINVAL;
5353 }
5354
5355 /*
5356 * No idea if it's still called the LVDS manufacturer table, but
5357 * the concept's close enough.
5358 */
5359 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5360
5361 return 0;
5362}
5363
5364static int
5365parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5366 struct bit_entry *bitentry)
5367{
5368 /*
5369 * offset + 2 (8 bits): number of options in an
5370 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5371 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5372 * restrict option selection
5373 *
5374 * There's a bunch of bits in this table other than the RAM restrict
5375 * stuff that we don't use - their use currently unknown
5376 */
5377
6ee73861
BS		 5378 /*
5379 * Older bios versions don't have a sufficiently long table for
5380 * what we want
5381 */
5382 if (bitentry->length < 0x5)
5383 return 0;
5384
4709bff0 5385 if (bitentry->version < 2) {
37383650
MK		 5386 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5387 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 5388 } else {
37383650
MK		 5389 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5390 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 5391 }
5392
6ee73861
BS		 5393 return 0;
5394}
5395
5396static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5397{
5398 /*
5399 * Parses the pointer to the TMDS table
5400 *
5401 * Starting at bitentry->offset:
5402 *
5403 * offset + 0 (16 bits): TMDS table pointer
5404 *
5405 * The TMDS table is typically found just before the DCB table, with a
5406 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5407 * length?)
5408 *
5409 * At offset +7 is a pointer to a script, which I don't know how to
5410 * run yet.
5411 * At offset +9 is a pointer to another script, likewise
5412 * Offset +11 has a pointer to a table where the first word is a pxclk
5413 * frequency and the second word a pointer to a script, which should be
5414 * run if the comparison pxclk frequency is less than the pxclk desired.
5415 * This repeats for decreasing comparison frequencies
5416 * Offset +13 has a pointer to a similar table
5417 * The selection of table (and possibly +7/+9 script) is dictated by
5418 * "or" from the DCB.
5419 */
5420
5421 uint16_t tmdstableptr, script1, script2;
5422
5423 if (bitentry->length != 2) {
5424 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5425 return -EINVAL;
5426 }
5427
5428 tmdstableptr = ROM16(bios->data[bitentry->offset]);
98720bf4 5429 if (!tmdstableptr) {
6ee73861
BS		 5430 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5431 return -EINVAL;
5432 }
5433
98720bf4
BS		 5434 NV_INFO(dev, "TMDS table version %d.%d\n",
5435 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5436
6ee73861 5437 /* nv50+ has v2.0, but we don't parse it atm */
98720bf4 5438 if (bios->data[tmdstableptr] != 0x11)
6ee73861 5439 return -ENOSYS;
6ee73861
BS		 5440
5441 /*
5442 * These two scripts are odd: they don't seem to get run even when
5443 * they are not stubbed.
5444 */
5445 script1 = ROM16(bios->data[tmdstableptr + 7]);
5446 script2 = ROM16(bios->data[tmdstableptr + 9]);
5447 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5448 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5449
5450 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5451 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5452
5453 return 0;
5454}
5455
5456static int
5457parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5458 struct bit_entry *bitentry)
5459{
5460 /*
5461 * Parses the pointer to the G80 output script tables
5462 *
5463 * Starting at bitentry->offset:
5464 *
5465 * offset + 0 (16 bits): output script table pointer
5466 */
5467
5468 uint16_t outputscripttableptr;
5469
5470 if (bitentry->length != 3) {
5471 NV_ERROR(dev, "Do not understand BIT U table\n");
5472 return -EINVAL;
5473 }
5474
5475 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5476 bios->display.script_table_ptr = outputscripttableptr;
5477 return 0;
5478}
5479
5480static int
5481parse_bit_displayport_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5482 struct bit_entry *bitentry)
5483{
5484 bios->display.dp_table_ptr = ROM16(bios->data[bitentry->offset]);
5485 return 0;
5486}
5487
5488struct bit_table {
5489 const char id;
5490 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5491};
5492
5493#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5494
4709bff0
BS		 5495int
5496bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5497{
5498 struct drm_nouveau_private *dev_priv = dev->dev_private;
5499 struct nvbios *bios = &dev_priv->vbios;
5500 u8 entries, *entry;
5501
5502 entries = bios->data[bios->offset + 10];
5503 entry = &bios->data[bios->offset + 12];
5504 while (entries--) {
5505 if (entry[0] == id) {
5506 bit->id = entry[0];
5507 bit->version = entry[1];
5508 bit->length = ROM16(entry[2]);
5509 bit->offset = ROM16(entry[4]);
5510 bit->data = ROMPTR(bios, entry[4]);
5511 return 0;
5512 }
5513
5514 entry += bios->data[bios->offset + 9];
5515 }
5516
5517 return -ENOENT;
5518}
5519
6ee73861
BS		 5520static int
5521parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5522 struct bit_table *table)
5523{
5524 struct drm_device *dev = bios->dev;
6ee73861
BS		 5525 struct bit_entry bitentry;
5526
4709bff0 5527 if (bit_table(dev, table->id, &bitentry) == 0)
6ee73861 5528 return table->parse_fn(dev, bios, &bitentry);
6ee73861
BS		 5529
5530 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5531 return -ENOSYS;
5532}
5533
5534static int
5535parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5536{
5537 int ret;
5538
5539 /*
5540 * The only restriction on parsing order currently is having 'i' first
5541 * for use of bios->*_version or bios->feature_byte while parsing;
5542 * functions shouldn't be actually *doing* anything apart from pulling
5543 * data from the image into the bios struct, thus no interdependencies
5544 */
5545 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5546 if (ret) /* info? */
5547 return ret;
5548 if (bios->major_version >= 0x60) /* g80+ */
5549 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5550 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5551 if (ret)
5552 return ret;
5553 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5554 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5555 if (ret)
5556 return ret;
5557 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5558 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5559 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5560 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
5561 parse_bit_table(bios, bitoffset, &BIT_TABLE('d', displayport));
5562
5563 return 0;
5564}
5565
5566static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5567{
5568 /*
5569 * Parses the BMP structure for useful things, but does not act on them
5570 *
5571 * offset + 5: BMP major version
5572 * offset + 6: BMP minor version
5573 * offset + 9: BMP feature byte
5574 * offset + 10: BCD encoded BIOS version
5575 *
5576 * offset + 18: init script table pointer (for bios versions < 5.10h)
5577 * offset + 20: extra init script table pointer (for bios
5578 * versions < 5.10h)
5579 *
5580 * offset + 24: memory init table pointer (used on early bios versions)
5581 * offset + 26: SDR memory sequencing setup data table
5582 * offset + 28: DDR memory sequencing setup data table
5583 *
5584 * offset + 54: index of I2C CRTC pair to use for CRT output
5585 * offset + 55: index of I2C CRTC pair to use for TV output
5586 * offset + 56: index of I2C CRTC pair to use for flat panel output
5587 * offset + 58: write CRTC index for I2C pair 0
5588 * offset + 59: read CRTC index for I2C pair 0
5589 * offset + 60: write CRTC index for I2C pair 1
5590 * offset + 61: read CRTC index for I2C pair 1
5591 *
5592 * offset + 67: maximum internal PLL frequency (single stage PLL)
5593 * offset + 71: minimum internal PLL frequency (single stage PLL)
5594 *
5595 * offset + 75: script table pointers, as described in
5596 * parse_script_table_pointers
5597 *
5598 * offset + 89: TMDS single link output A table pointer
5599 * offset + 91: TMDS single link output B table pointer
5600 * offset + 95: LVDS single link output A table pointer
5601 * offset + 105: flat panel timings table pointer
5602 * offset + 107: flat panel strapping translation table pointer
5603 * offset + 117: LVDS manufacturer panel config table pointer
5604 * offset + 119: LVDS manufacturer strapping translation table pointer
5605 *
5606 * offset + 142: PLL limits table pointer
5607 *
5608 * offset + 156: minimum pixel clock for LVDS dual link
5609 */
5610
5611 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5612 uint16_t bmplength;
5613 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5614
5615 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 5616 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5617 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5618 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5619 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 5620 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5621 bios->fmaxvco = 256000;
5622 bios->fminvco = 128000;
5623 bios->fp.duallink_transition_clk = 90000;
5624
5625 bmp_version_major = bmp[5];
5626 bmp_version_minor = bmp[6];
5627
5628 NV_TRACE(dev, "BMP version %d.%d\n",
5629 bmp_version_major, bmp_version_minor);
5630
5631 /*
5632 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5633 * pointer on early versions
5634 */
5635 if (bmp_version_major < 5)
5636 *(uint16_t *)&bios->data[0x36] = 0;
5637
5638 /*
5639 * Seems that the minor version was 1 for all major versions prior
5640 * to 5. Version 6 could theoretically exist, but I suspect BIT
5641 * happened instead.
5642 */
5643 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5644 NV_ERROR(dev, "You have an unsupported BMP version. "
5645 "Please send in your bios\n");
5646 return -ENOSYS;
5647 }
5648
5649 if (bmp_version_major == 0)
5650 /* nothing that's currently useful in this version */
5651 return 0;
5652 else if (bmp_version_major == 1)
5653 bmplength = 44; /* exact for 1.01 */
5654 else if (bmp_version_major == 2)
5655 bmplength = 48; /* exact for 2.01 */
5656 else if (bmp_version_major == 3)
5657 bmplength = 54;
5658 /* guessed - mem init tables added in this version */
5659 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5660 /* don't know if 5.0 exists... */
5661 bmplength = 62;
5662 /* guessed - BMP I2C indices added in version 4*/
5663 else if (bmp_version_minor < 0x6)
5664 bmplength = 67; /* exact for 5.01 */
5665 else if (bmp_version_minor < 0x10)
5666 bmplength = 75; /* exact for 5.06 */
5667 else if (bmp_version_minor == 0x10)
5668 bmplength = 89; /* exact for 5.10h */
5669 else if (bmp_version_minor < 0x14)
5670 bmplength = 118; /* exact for 5.11h */
5671 else if (bmp_version_minor < 0x24)
5672 /*
5673 * Not sure of version where pll limits came in;
5674 * certainly exist by 0x24 though.
5675 */
5676 /* length not exact: this is long enough to get lvds members */
5677 bmplength = 123;
5678 else if (bmp_version_minor < 0x27)
5679 /*
5680 * Length not exact: this is long enough to get pll limit
5681 * member
5682 */
5683 bmplength = 144;
5684 else
5685 /*
5686 * Length not exact: this is long enough to get dual link
5687 * transition clock.
5688 */
5689 bmplength = 158;
5690
5691 /* checksum */
5692 if (nv_cksum(bmp, 8)) {
5693 NV_ERROR(dev, "Bad BMP checksum\n");
5694 return -EINVAL;
5695 }
5696
5697 /*
5698 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5699 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5700 * (not nv10gl), bit 5 that the flat panel tables are present, and
5701 * bit 6 a tv bios.
5702 */
5703 bios->feature_byte = bmp[9];
5704
5705 parse_bios_version(dev, bios, offset + 10);
5706
5707 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5708 bios->old_style_init = true;
5709 legacy_scripts_offset = 18;
5710 if (bmp_version_major < 2)
5711 legacy_scripts_offset -= 4;
5712 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5713 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5714
5715 if (bmp_version_major > 2) { /* appears in BMP 3 */
5716 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5717 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5718 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5719 }
5720
5721 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5722 if (bmplength > 61)
5723 legacy_i2c_offset = offset + 54;
5724 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5725 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5726 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3af76454
FJ		 5727 if (bios->data[legacy_i2c_offset + 4])
5728 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5729 if (bios->data[legacy_i2c_offset + 5])
5730 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5731 if (bios->data[legacy_i2c_offset + 6])
5732 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5733 if (bios->data[legacy_i2c_offset + 7])
5734 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5735
5736 if (bmplength > 74) {
5737 bios->fmaxvco = ROM32(bmp[67]);
5738 bios->fminvco = ROM32(bmp[71]);
5739 }
5740 if (bmplength > 88)
5741 parse_script_table_pointers(bios, offset + 75);
5742 if (bmplength > 94) {
5743 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5744 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5745 /*
5746 * Never observed in use with lvds scripts, but is reused for
5747 * 18/24 bit panel interface default for EDID equipped panels
5748 * (if_is_24bit not set directly to avoid any oscillation).
5749 */
5750 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5751 }
5752 if (bmplength > 108) {
5753 bios->fp.fptablepointer = ROM16(bmp[105]);
5754 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5755 bios->fp.xlatwidth = 1;
5756 }
5757 if (bmplength > 120) {
5758 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5759 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5760 }
5761 if (bmplength > 143)
5762 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5763
5764 if (bmplength > 157)
5765 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5766
5767 return 0;
5768}
5769
5770static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5771{
5772 int i, j;
5773
5774 for (i = 0; i <= (n - len); i++) {
5775 for (j = 0; j < len; j++)
5776 if (data[i + j] != str[j])
5777 break;
5778 if (j == len)
5779 return i;
5780 }
5781
5782 return 0;
5783}
5784
6ee73861
BS		 5785static struct dcb_gpio_entry *
5786new_gpio_entry(struct nvbios *bios)
5787{
e49f70f7 5788 struct drm_device *dev = bios->dev;
7f245b20 5789 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861 5790
e49f70f7
BS		 5791 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) {
5792 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n");
5793 return NULL;
5794 }
5795
6ee73861
BS		 5796 return &gpio->entry[gpio->entries++];
5797}
5798
5799struct dcb_gpio_entry *
5800nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5801{
5802 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5803 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5804 int i;
5805
7f245b20
BS		 5806 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5807 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5808 continue;
5809
7f245b20 5810 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5811 }
5812
5813 return NULL;
5814}
5815
6ee73861
BS		 5816static void
5817parse_dcb_gpio_table(struct nvbios *bios)
5818{
5819 struct drm_device *dev = bios->dev;
e49f70f7
BS		 5820 struct dcb_gpio_entry *e;
5821 u8 headerlen, entries, recordlen;
5822 u8 *dcb, *gpio = NULL, *entry;
6ee73861
BS		 5823 int i;
5824
e49f70f7
BS		 5825 dcb = ROMPTR(bios, bios->data[0x36]);
5826 if (dcb[0] >= 0x30) {
5827 gpio = ROMPTR(bios, dcb[10]);
5828 if (!gpio)
5829 goto no_table;
6ee73861 5830
e49f70f7
BS		 5831 headerlen = gpio[1];
5832 entries = gpio[2];
5833 recordlen = gpio[3];
5834 } else
5e6a7443 5835 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) {
e49f70f7
BS		 5836 gpio = ROMPTR(bios, dcb[-15]);
5837 if (!gpio)
5838 goto no_table;
5839
5840 headerlen = 3;
5841 entries = gpio[2];
5842 recordlen = gpio[1];
5e6a7443
FJ		 5843 } else
5844 if (dcb[0] >= 0x22) {
5845 /* No GPIO table present, parse the TVDAC GPIO data. */
5846 uint8_t *tvdac_gpio = &dcb[-5];
6ee73861 5847
5e6a7443
FJ		 5848 if (tvdac_gpio[0] & 1) {
5849 e = new_gpio_entry(bios);
5850 e->tag = DCB_GPIO_TVDAC0;
5851 e->line = tvdac_gpio[1] >> 4;
5852 e->invert = tvdac_gpio[0] & 2;
6ee73861
BS		 5853 }
5854
5e6a7443 5855 goto no_table;
e49f70f7
BS		 5856 } else {
5857 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]);
5858 goto no_table;
5859 }
6ee73861 5860
e49f70f7
BS		 5861 entry = gpio + headerlen;
5862 for (i = 0; i < entries; i++, entry += recordlen) {
5863 e = new_gpio_entry(bios);
5864 if (!e)
5865 break;
6ee73861 5866
e49f70f7
BS		 5867 if (gpio[0] < 0x40) {
5868 e->entry = ROM16(entry[0]);
5869 e->tag = (e->entry & 0x07e0) >> 5;
5870 if (e->tag == 0x3f) {
5871 bios->dcb.gpio.entries--;
5872 continue;
5873 }
20d66daf 5874
e49f70f7
BS		 5875 e->line = (e->entry & 0x001f);
5876 e->invert = ((e->entry & 0xf800) >> 11) != 4;
5877 } else {
5878 e->entry = ROM32(entry[0]);
5879 e->tag = (e->entry & 0x0000ff00) >> 8;
5880 if (e->tag == 0xff) {
5881 bios->dcb.gpio.entries--;
5882 continue;
5883 }
20d66daf 5884
e49f70f7
BS		 5885 e->line = (e->entry & 0x0000001f) >> 0;
5886 e->state_default = (e->entry & 0x01000000) >> 24;
5887 e->state[0] = (e->entry & 0x18000000) >> 27;
5888 e->state[1] = (e->entry & 0x60000000) >> 29;
20d66daf 5889 }
6ee73861
BS		 5890 }
5891
e49f70f7
BS		 5892no_table:
5893 /* Apple iMac G4 NV18 */
5894 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5895 e = new_gpio_entry(bios);
5896 if (e) {
5897 e->tag = DCB_GPIO_TVDAC0;
5898 e->line = 4;
5899 }
6ee73861 5900 }
6ee73861
BS		 5901}
5902
5903struct dcb_connector_table_entry *
5904nouveau_bios_connector_entry(struct drm_device *dev, int index)
5905{
5906 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5907 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5908 struct dcb_connector_table_entry *cte;
5909
7f245b20 5910 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5911 return NULL;
5912
7f245b20 5913 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5914 if (cte->type == 0xff)
5915 return NULL;
5916
5917 return cte;
5918}
5919
f66fa771
BS		 5920static enum dcb_connector_type
5921divine_connector_type(struct nvbios *bios, int index)
5922{
5923 struct dcb_table *dcb = &bios->dcb;
5924 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5925 int i;
5926
5927 for (i = 0; i < dcb->entries; i++) {
5928 if (dcb->entry[i].connector == index)
5929 encoders |= (1 << dcb->entry[i].type);
5930 }
5931
5932 if (encoders & (1 << OUTPUT_DP)) {
5933 if (encoders & (1 << OUTPUT_TMDS))
5934 type = DCB_CONNECTOR_DP;
5935 else
5936 type = DCB_CONNECTOR_eDP;
5937 } else
5938 if (encoders & (1 << OUTPUT_TMDS)) {
5939 if (encoders & (1 << OUTPUT_ANALOG))
5940 type = DCB_CONNECTOR_DVI_I;
5941 else
5942 type = DCB_CONNECTOR_DVI_D;
5943 } else
5944 if (encoders & (1 << OUTPUT_ANALOG)) {
5945 type = DCB_CONNECTOR_VGA;
5946 } else
5947 if (encoders & (1 << OUTPUT_LVDS)) {
5948 type = DCB_CONNECTOR_LVDS;
5949 } else
5950 if (encoders & (1 << OUTPUT_TV)) {
5951 type = DCB_CONNECTOR_TV_0;
5952 }
5953
5954 return type;
5955}
5956
53c44c3a
BS		 5957static void
5958apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5959{
5960 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5961 struct drm_device *dev = bios->dev;
5962
5963 /* Gigabyte NX85T */
acae116c 5964 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
53c44c3a
BS		 5965 if (cte->type == DCB_CONNECTOR_HDMI_1)
5966 cte->type = DCB_CONNECTOR_DVI_I;
5967 }
5968}
5969
a589e87f
BS		 5970static const u8 hpd_gpio[16] = {
5971 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff,
5972 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0x5f, 0x60,
5973};
5974
6ee73861
BS		 5975static void
5976parse_dcb_connector_table(struct nvbios *bios)
5977{
5978 struct drm_device *dev = bios->dev;
7f245b20 5979 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5980 struct dcb_connector_table_entry *cte;
7f245b20 5981 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5982 uint8_t *entry;
5983 int i;
5984
7f245b20 5985 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5986 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5987 return;
5988 }
5989
5990 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5991 conntab[0], conntab[1], conntab[2], conntab[3]);
5992 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5993 (conntab[3] != 2 && conntab[3] != 4)) {
5994 NV_ERROR(dev, " Unknown! Please report.\n");
5995 return;
5996 }
5997
5998 ct->entries = conntab[2];
5999
6000 entry = conntab + conntab[1];
6001 cte = &ct->entry[0];
6002 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 6003 cte->index = i;
6ee73861
BS		 6004 if (conntab[3] == 2)
6005 cte->entry = ROM16(entry[0]);
6006 else
6007 cte->entry = ROM32(entry[0]);
f66fa771 6008
6ee73861 6009 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 6010 cte->index2 = (cte->entry & 0x00000f00) >> 8;
a589e87f
BS		 6011
6012 cte->gpio_tag = ffs((cte->entry & 0x07033000) >> 12);
6013 cte->gpio_tag = hpd_gpio[cte->gpio_tag];
6ee73861
BS		 6014
6015 if (cte->type == 0xff)
6016 continue;
6017
53c44c3a
BS		 6018 apply_dcb_connector_quirks(bios, i);
6019
6ee73861
BS		 6020 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
6021 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 6022
6023 /* check for known types, fallback to guessing the type
6024 * from attached encoders if we hit an unknown.
6025 */
6026 switch (cte->type) {
6027 case DCB_CONNECTOR_VGA:
6028 case DCB_CONNECTOR_TV_0:
6029 case DCB_CONNECTOR_TV_1:
6030 case DCB_CONNECTOR_TV_3:
6031 case DCB_CONNECTOR_DVI_I:
6032 case DCB_CONNECTOR_DVI_D:
6033 case DCB_CONNECTOR_LVDS:
8c3f6bb9 6034 case DCB_CONNECTOR_LVDS_SPWG:
f66fa771
BS		 6035 case DCB_CONNECTOR_DP:
6036 case DCB_CONNECTOR_eDP:
6037 case DCB_CONNECTOR_HDMI_0:
6038 case DCB_CONNECTOR_HDMI_1:
6039 break;
6040 default:
6041 cte->type = divine_connector_type(bios, cte->index);
da647d5b 6042 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 6043 break;
6044 }
6045
da647d5b
BS		 6046 if (nouveau_override_conntype) {
6047 int type = divine_connector_type(bios, cte->index);
6048 if (type != cte->type)
6049 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
6050 }
6051
6ee73861
BS		 6052 }
6053}
6054
7f245b20 6055static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 6056{
6057 struct dcb_entry *entry = &dcb->entry[dcb->entries];
6058
6059 memset(entry, 0, sizeof(struct dcb_entry));
6060 entry->index = dcb->entries++;
6061
6062 return entry;
6063}
6064
2e5702af
FJ		 6065static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
6066 int heads, int or)
6ee73861
BS		 6067{
6068 struct dcb_entry *entry = new_dcb_entry(dcb);
6069
2e5702af 6070 entry->type = type;
6ee73861
BS		 6071 entry->i2c_index = i2c;
6072 entry->heads = heads;
2e5702af
FJ		 6073 if (type != OUTPUT_ANALOG)
6074 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
6075 entry->or = or;
6ee73861
BS		 6076}
6077
6078static bool
7f245b20 6079parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6080 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6081{
6082 entry->type = conn & 0xf;
6083 entry->i2c_index = (conn >> 4) & 0xf;
6084 entry->heads = (conn >> 8) & 0xf;
7f245b20 6085 if (dcb->version >= 0x40)
6ee73861
BS		 6086 entry->connector = (conn >> 12) & 0xf;
6087 entry->bus = (conn >> 16) & 0xf;
6088 entry->location = (conn >> 20) & 0x3;
6089 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 6090
6091 switch (entry->type) {
6092 case OUTPUT_ANALOG:
6093 /*
6094 * Although the rest of a CRT conf dword is usually
6095 * zeros, mac biosen have stuff there so we must mask
6096 */
7f245b20 6097 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 6098 (conf & 0xffff) * 10 :
6099 (conf & 0xff) * 10000;
6100 break;
6101 case OUTPUT_LVDS:
6102 {
6103 uint32_t mask;
6104 if (conf & 0x1)
6105 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 6106 if (dcb->version < 0x22) {
6ee73861
BS		 6107 mask = ~0xd;
6108 /*
6109 * The laptop in bug 14567 lies and claims to not use
6110 * straps when it does, so assume all DCB 2.0 laptops
6111 * use straps, until a broken EDID using one is produced
6112 */
6113 entry->lvdsconf.use_straps_for_mode = true;
6114 /*
6115 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
6116 * mean the same thing (probably wrong, but might work)
6117 */
6118 if (conf & 0x4 || conf & 0x8)
6119 entry->lvdsconf.use_power_scripts = true;
6120 } else {
a6ed76d7
BS		 6121 mask = ~0x7;
6122 if (conf & 0x2)
6123 entry->lvdsconf.use_acpi_for_edid = true;
6ee73861
BS		 6124 if (conf & 0x4)
6125 entry->lvdsconf.use_power_scripts = true;
c5875470 6126 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6ee73861
BS		 6127 }
6128 if (conf & mask) {
6129 /*
6130 * Until we even try to use these on G8x, it's
6131 * useless reporting unknown bits. They all are.
6132 */
7f245b20 6133 if (dcb->version >= 0x40)
6ee73861
BS		 6134 break;
6135
6136 NV_ERROR(dev, "Unknown LVDS configuration bits, "
6137 "please report\n");
6138 }
6139 break;
6140 }
6141 case OUTPUT_TV:
6142 {
7f245b20 6143 if (dcb->version >= 0x30)
6ee73861
BS		 6144 entry->tvconf.has_component_output = conf & (0x8 << 4);
6145 else
6146 entry->tvconf.has_component_output = false;
6147
6148 break;
6149 }
6150 case OUTPUT_DP:
6151 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
6152 entry->dpconf.link_bw = (conf & 0x00e00000) >> 21;
6153 switch ((conf & 0x0f000000) >> 24) {
6154 case 0xf:
6155 entry->dpconf.link_nr = 4;
6156 break;
6157 case 0x3:
6158 entry->dpconf.link_nr = 2;
6159 break;
6160 default:
6161 entry->dpconf.link_nr = 1;
6162 break;
6163 }
6164 break;
6165 case OUTPUT_TMDS:
27d50fcc
FJ		 6166 if (dcb->version >= 0x40)
6167 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
4a9f822f
FJ		 6168 else if (dcb->version >= 0x30)
6169 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
27d50fcc
FJ		 6170 else if (dcb->version >= 0x22)
6171 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
4a9f822f 6172
6ee73861 6173 break;
44a1246f 6174 case OUTPUT_EOL:
6ee73861 6175 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 6176 dcb->entries--;
6ee73861 6177 return false;
e7cc51c5
BS		 6178 default:
6179 break;
6ee73861
BS		 6180 }
6181
23484874
BS		 6182 if (dcb->version < 0x40) {
6183 /* Normal entries consist of a single bit, but dual link has
6184 * the next most significant bit set too
6185 */
6186 entry->duallink_possible =
6187 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6188 } else {
6189 entry->duallink_possible = (entry->sorconf.link == 3);
6190 }
6191
6ee73861
BS		 6192 /* unsure what DCB version introduces this, 3.0? */
6193 if (conf & 0x100000)
6194 entry->i2c_upper_default = true;
6195
6196 return true;
6197}
6198
6199static bool
7f245b20 6200parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6201 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6202{
b0d2de86
BS		 6203 switch (conn & 0x0000000f) {
6204 case 0:
6205 entry->type = OUTPUT_ANALOG;
6206 break;
6207 case 1:
6208 entry->type = OUTPUT_TV;
6209 break;
6210 case 2:
b0d2de86 6211 case 4:
fba67528 6212 if (conn & 0x10)
b0d2de86 6213 entry->type = OUTPUT_LVDS;
fba67528
FJ		 6214 else
6215 entry->type = OUTPUT_TMDS;
6216 break;
6217 case 3:
6218 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 6219 break;
6220 default:
6221 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6222 return false;
6ee73861 6223 }
b0d2de86
BS		 6224
6225 entry->i2c_index = (conn & 0x0003c000) >> 14;
6226 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6227 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6228 entry->location = (conn & 0x01e00000) >> 21;
6229 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 6230 entry->duallink_possible = false;
6231
6232 switch (entry->type) {
6233 case OUTPUT_ANALOG:
6234 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6235 break;
b0d2de86
BS		 6236 case OUTPUT_TV:
6237 entry->tvconf.has_component_output = false;
6ee73861 6238 break;
b0d2de86 6239 case OUTPUT_LVDS:
77b1d5dc 6240 if ((conn & 0x00003f00) >> 8 != 0x10)
b0d2de86
BS		 6241 entry->lvdsconf.use_straps_for_mode = true;
6242 entry->lvdsconf.use_power_scripts = true;
6243 break;
6244 default:
6ee73861
BS		 6245 break;
6246 }
6247
6248 return true;
6249}
6250
7f245b20 6251static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6252 uint32_t conn, uint32_t conf)
6253{
7f245b20 6254 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 6255 bool ret;
6256
7f245b20
BS		 6257 if (dcb->version >= 0x20)
6258 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 6259 else
7f245b20 6260 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 6261 if (!ret)
6262 return ret;
6263
7f245b20
BS		 6264 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6265 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 6266
6267 return true;
6268}
6269
6270static
7f245b20 6271void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 6272{
6273 /*
6274 * DCB v2.0 lists each output combination separately.
6275 * Here we merge compatible entries to have fewer outputs, with
6276 * more options
6277 */
6278
6279 int i, newentries = 0;
6280
6281 for (i = 0; i < dcb->entries; i++) {
6282 struct dcb_entry *ient = &dcb->entry[i];
6283 int j;
6284
6285 for (j = i + 1; j < dcb->entries; j++) {
6286 struct dcb_entry *jent = &dcb->entry[j];
6287
6288 if (jent->type == 100) /* already merged entry */
6289 continue;
6290
6291 /* merge heads field when all other fields the same */
6292 if (jent->i2c_index == ient->i2c_index &&
6293 jent->type == ient->type &&
6294 jent->location == ient->location &&
6295 jent->or == ient->or) {
6296 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6297 i, j);
6298 ient->heads |= jent->heads;
6299 jent->type = 100; /* dummy value */
6300 }
6301 }
6302 }
6303
6304 /* Compact entries merged into others out of dcb */
6305 for (i = 0; i < dcb->entries; i++) {
6306 if (dcb->entry[i].type == 100)
6307 continue;
6308
6309 if (newentries != i) {
6310 dcb->entry[newentries] = dcb->entry[i];
6311 dcb->entry[newentries].index = newentries;
6312 }
6313 newentries++;
6314 }
6315
6316 dcb->entries = newentries;
6317}
6318
df4cf1b7
BS		 6319static bool
6320apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6321{
670820c0
FJ		 6322 struct drm_nouveau_private *dev_priv = dev->dev_private;
6323 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6324
df4cf1b7
BS		 6325 /* Dell Precision M6300
6326 * DCB entry 2: 02025312 00000010
6327 * DCB entry 3: 02026312 00000020
6328 *
6329 * Identical, except apparently a different connector on a
6330 * different SOR link. Not a clue how we're supposed to know
6331 * which one is in use if it even shares an i2c line...
6332 *
6333 * Ignore the connector on the second SOR link to prevent
6334 * nasty problems until this is sorted (assuming it's not a
6335 * VBIOS bug).
6336 */
acae116c 6337 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
df4cf1b7
BS		 6338 if (*conn == 0x02026312 && *conf == 0x00000020)
6339 return false;
6340 }
6341
670820c0
FJ		 6342 /* GeForce3 Ti 200
6343 *
6344 * DCB reports an LVDS output that should be TMDS:
6345 * DCB entry 1: f2005014 ffffffff
6346 */
6347 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6348 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6349 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6350 return false;
6351 }
6352 }
6353
c0929b49
BS		 6354 /* XFX GT-240X-YA
6355 *
6356 * So many things wrong here, replace the entire encoder table..
6357 */
6358 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6359 if (idx == 0) {
6360 *conn = 0x02001300; /* VGA, connector 1 */
6361 *conf = 0x00000028;
6362 } else
6363 if (idx == 1) {
6364 *conn = 0x01010312; /* DVI, connector 0 */
6365 *conf = 0x00020030;
6366 } else
6367 if (idx == 2) {
6368 *conn = 0x01010310; /* VGA, connector 0 */
6369 *conf = 0x00000028;
6370 } else
6371 if (idx == 3) {
6372 *conn = 0x02022362; /* HDMI, connector 2 */
6373 *conf = 0x00020010;
6374 } else {
6375 *conn = 0x0000000e; /* EOL */
6376 *conf = 0x00000000;
6377 }
6378 }
6379
df4cf1b7
BS		 6380 return true;
6381}
6382
2e5702af
FJ		 6383static void
6384fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6385{
6386 struct dcb_table *dcb = &bios->dcb;
6387 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6388
6389#ifdef __powerpc__
6390 /* Apple iMac G4 NV17 */
6391 if (of_machine_is_compatible("PowerMac4,5")) {
6392 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6393 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6394 return;
6395 }
6396#endif
6397
6398 /* Make up some sane defaults */
6399 fabricate_dcb_output(dcb, OUTPUT_ANALOG, LEGACY_I2C_CRT, 1, 1);
6400
6401 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
6402 fabricate_dcb_output(dcb, OUTPUT_TV, LEGACY_I2C_TV,
6403 all_heads, 0);
6404
6405 else if (bios->tmds.output0_script_ptr ||
6406 bios->tmds.output1_script_ptr)
6407 fabricate_dcb_output(dcb, OUTPUT_TMDS, LEGACY_I2C_PANEL,
6408 all_heads, 1);
6409}
6410
ed42f824 6411static int
2e5702af 6412parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6ee73861 6413{
ed42f824 6414 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 6415 struct dcb_table *dcb = &bios->dcb;
ed42f824 6416 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 6417 uint8_t *dcbtable;
6418 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
6419 bool configblock = true;
6420 int recordlength = 8, confofs = 4;
6421 int i;
6422
6ee73861 6423 /* get the offset from 0x36 */
ed42f824
BS		 6424 if (dev_priv->card_type > NV_04) {
6425 dcbptr = ROM16(bios->data[0x36]);
6426 if (dcbptr == 0x0000)
6427 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
6428 }
6ee73861 6429
ed42f824 6430 /* this situation likely means a really old card, pre DCB */
6ee73861 6431 if (dcbptr == 0x0) {
2e5702af 6432 fabricate_dcb_encoder_table(dev, bios);
6ee73861
BS		 6433 return 0;
6434 }
6435
6436 dcbtable = &bios->data[dcbptr];
6437
6438 /* get DCB version */
7f245b20 6439 dcb->version = dcbtable[0];
6ee73861 6440 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 6441 dcb->version >> 4, dcb->version & 0xf);
6ee73861 6442
7f245b20 6443 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 6444 uint32_t sig;
6445
7f245b20 6446 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 6447 headerlen = dcbtable[1];
6448 entries = dcbtable[2];
6449 recordlength = dcbtable[3];
6450 i2ctabptr = ROM16(dcbtable[4]);
6451 sig = ROM32(dcbtable[6]);
7f245b20
BS		 6452 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
6453 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 6454 } else {
6455 i2ctabptr = ROM16(dcbtable[2]);
6456 sig = ROM32(dcbtable[4]);
6457 headerlen = 8;
6458 }
6459
6460 if (sig != 0x4edcbdcb) {
6461 NV_ERROR(dev, "Bad Display Configuration Block "
6462 "signature (%08X)\n", sig);
6463 return -EINVAL;
6464 }
7f245b20 6465 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 6466 char sig[8] = { 0 };
6467
6468 strncpy(sig, (char *)&dcbtable[-7], 7);
6469 i2ctabptr = ROM16(dcbtable[2]);
6470 recordlength = 10;
6471 confofs = 6;
6472
6473 if (strcmp(sig, "DEV_REC")) {
6474 NV_ERROR(dev, "Bad Display Configuration Block "
6475 "signature (%s)\n", sig);
6476 return -EINVAL;
6477 }
6478 } else {
6479 /*
6480 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6481 * has the same single (crt) entry, even when tv-out present, so
6482 * the conclusion is this version cannot really be used.
6483 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6484 * 5 entries, which are not specific to the card and so no use.
6485 * v1.2 does have an I2C table that read_dcb_i2c_table can
6486 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6487 * pointer, so use the indices parsed in parse_bmp_structure.
6488 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6489 */
6490 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
6491 "adding all possible outputs\n");
2e5702af 6492 fabricate_dcb_encoder_table(dev, bios);
6ee73861
BS		 6493 return 0;
6494 }
6495
6496 if (!i2ctabptr)
6497 NV_WARN(dev, "No pointer to DCB I2C port table\n");
6498 else {
7f245b20
BS		 6499 dcb->i2c_table = &bios->data[i2ctabptr];
6500 if (dcb->version >= 0x30)
6501 dcb->i2c_default_indices = dcb->i2c_table[4];
4a9f822f
FJ		 6502
6503 /*
6504 * Parse the "management" I2C bus, used for hardware
6505 * monitoring and some external TMDS transmitters.
6506 */
6507 if (dcb->version >= 0x22) {
6508 int idx = (dcb->version >= 0x40 ?
6509 dcb->i2c_default_indices & 0xf :
6510 2);
6511
6512 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6513 idx, &dcb->i2c[idx]);
6514 }
6ee73861
BS		 6515 }
6516
6ee73861
BS		 6517 if (entries > DCB_MAX_NUM_ENTRIES)
6518 entries = DCB_MAX_NUM_ENTRIES;
6519
6520 for (i = 0; i < entries; i++) {
6521 uint32_t connection, config = 0;
6522
6523 connection = ROM32(dcbtable[headerlen + recordlength * i]);
6524 if (configblock)
6525 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
6526
6527 /* seen on an NV11 with DCB v1.5 */
6528 if (connection == 0x00000000)
6529 break;
6530
6531 /* seen on an NV17 with DCB v2.0 */
6532 if (connection == 0xffffffff)
6533 break;
6534
6535 if ((connection & 0x0000000f) == 0x0000000f)
6536 continue;
6537
df4cf1b7
BS		 6538 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config))
6539 continue;
6540
6ee73861
BS		 6541 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
6542 dcb->entries, connection, config);
6543
7f245b20 6544 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 6545 break;
6546 }
6547
6548 /*
6549 * apart for v2.1+ not being known for requiring merging, this
6550 * guarantees dcbent->index is the index of the entry in the rom image
6551 */
7f245b20 6552 if (dcb->version < 0x21)
6ee73861
BS		 6553 merge_like_dcb_entries(dev, dcb);
6554
54abb5dd
BS		 6555 if (!dcb->entries)
6556 return -ENXIO;
6557
6558 parse_dcb_gpio_table(bios);
6559 parse_dcb_connector_table(bios);
6560 return 0;
6ee73861
BS		 6561}
6562
6563static void
6564fixup_legacy_connector(struct nvbios *bios)
6565{
7f245b20 6566 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 6567 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 6568
6569 /*
6570 * DCB 3.0 also has the table in most cases, but there are some cards
6571 * where the table is filled with stub entries, and the DCB entriy
6572 * indices are all 0. We don't need the connector indices on pre-G80
6573 * chips (yet?) so limit the use to DCB 4.0 and above.
6574 */
7f245b20 6575 if (dcb->version >= 0x40)
6ee73861
BS		 6576 return;
6577
dc5bc4ed
BS		 6578 dcb->connector.entries = 0;
6579
6ee73861
BS		 6580 /*
6581 * No known connector info before v3.0, so make it up. the rule here
6582 * is: anything on the same i2c bus is considered to be on the same
6583 * connector. any output without an associated i2c bus is assigned
6584 * its own unique connector index.
6585 */
6586 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 6587 /*
6588 * Ignore the I2C index for on-chip TV-out, as there
6589 * are cards with bogus values (nv31m in bug 23212),
6590 * and it's otherwise useless.
6591 */
6592 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 6593 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 6594 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 6595 i2c = dcb->entry[i].i2c_index;
6596
6597 if (i2c_conn[i2c]) {
6598 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 6599 continue;
6600 }
6601
dc5bc4ed
BS		 6602 dcb->entry[i].connector = dcb->connector.entries++;
6603 if (i2c != 0xf)
6604 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 6605 }
6606
dc5bc4ed
BS		 6607 /* Fake the connector table as well as just connector indices */
6608 for (i = 0; i < dcb->connector.entries; i++) {
6609 dcb->connector.entry[i].index = i;
6610 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6611 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 6612 }
6613}
6614
6615static void
6616fixup_legacy_i2c(struct nvbios *bios)
6617{
7f245b20 6618 struct dcb_table *dcb = &bios->dcb;
6ee73861
BS		 6619 int i;
6620
6621 for (i = 0; i < dcb->entries; i++) {
6622 if (dcb->entry[i].i2c_index == LEGACY_I2C_CRT)
6623 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.crt;
6624 if (dcb->entry[i].i2c_index == LEGACY_I2C_PANEL)
6625 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.panel;
6626 if (dcb->entry[i].i2c_index == LEGACY_I2C_TV)
6627 dcb->entry[i].i2c_index = bios->legacy.i2c_indices.tv;
6628 }
6629}
6630
6631static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6632{
6633 /*
6634 * The header following the "HWSQ" signature has the number of entries,
6635 * and the entry size
6636 *
6637 * An entry consists of a dword to write to the sequencer control reg
6638 * (0x00001304), followed by the ucode bytes, written sequentially,
6639 * starting at reg 0x00001400
6640 */
6641
6642 uint8_t bytes_to_write;
6643 uint16_t hwsq_entry_offset;
6644 int i;
6645
6646 if (bios->data[hwsq_offset] <= entry) {
6647 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6648 "requested entry\n");
6649 return -ENOENT;
6650 }
6651
6652 bytes_to_write = bios->data[hwsq_offset + 1];
6653
6654 if (bytes_to_write != 36) {
6655 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6656 return -EINVAL;
6657 }
6658
6659 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6660
6661 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6662
6663 /* set sequencer control */
6664 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6665 bytes_to_write -= 4;
6666
6667 /* write ucode */
6668 for (i = 0; i < bytes_to_write; i += 4)
6669 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6670
6671 /* twiddle NV_PBUS_DEBUG_4 */
6672 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6673
6674 return 0;
6675}
6676
6677static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6678 struct nvbios *bios)
6679{
6680 /*
6681 * BMP based cards, from NV17, need a microcode loading to correctly
6682 * control the GPIO etc for LVDS panels
6683 *
6684 * BIT based cards seem to do this directly in the init scripts
6685 *
6686 * The microcode entries are found by the "HWSQ" signature.
6687 */
6688
6689 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6690 const int sz = sizeof(hwsq_signature);
6691 int hwsq_offset;
6692
6693 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6694 if (!hwsq_offset)
6695 return 0;
6696
6697 /* always use entry 0? */
6698 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6699}
6700
6701uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6702{
6703 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6704 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6705 const uint8_t edid_sig[] = {
6706 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6707 uint16_t offset = 0;
6708 uint16_t newoffset;
6709 int searchlen = NV_PROM_SIZE;
6710
6711 if (bios->fp.edid)
6712 return bios->fp.edid;
6713
6714 while (searchlen) {
6715 newoffset = findstr(&bios->data[offset], searchlen,
6716 edid_sig, 8);
6717 if (!newoffset)
6718 return NULL;
6719 offset += newoffset;
6720 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6721 break;
6722
6723 searchlen -= offset;
6724 offset++;
6725 }
6726
6727 NV_TRACE(dev, "Found EDID in BIOS\n");
6728
6729 return bios->fp.edid = &bios->data[offset];
6730}
6731
6732void
6733nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
6734 struct dcb_entry *dcbent)
6735{
6736 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6737 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6738 struct init_exec iexec = { true, false };
6739
c7ca4d1b 6740 spin_lock_bh(&bios->lock);
6ee73861
BS		 6741 bios->display.output = dcbent;
6742 parse_init_table(bios, table, &iexec);
6743 bios->display.output = NULL;
c7ca4d1b 6744 spin_unlock_bh(&bios->lock);
6ee73861
BS		 6745}
6746
6747static bool NVInitVBIOS(struct drm_device *dev)
6748{
6749 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6750 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6751
6752 memset(bios, 0, sizeof(struct nvbios));
c7ca4d1b 6753 spin_lock_init(&bios->lock);
6ee73861
BS		 6754 bios->dev = dev;
6755
6756 if (!NVShadowVBIOS(dev, bios->data))
6757 return false;
6758
6759 bios->length = NV_PROM_SIZE;
6760 return true;
6761}
6762
6763static int nouveau_parse_vbios_struct(struct drm_device *dev)
6764{
6765 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6766 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6767 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6768 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6769 int offset;
6770
6771 offset = findstr(bios->data, bios->length,
6772 bit_signature, sizeof(bit_signature));
6773 if (offset) {
6774 NV_TRACE(dev, "BIT BIOS found\n");
4709bff0
BS		 6775 bios->type = NVBIOS_BIT;
6776 bios->offset = offset;
6ee73861
BS		 6777 return parse_bit_structure(bios, offset + 6);
6778 }
6779
6780 offset = findstr(bios->data, bios->length,
6781 bmp_signature, sizeof(bmp_signature));
6782 if (offset) {
6783 NV_TRACE(dev, "BMP BIOS found\n");
4709bff0
BS		 6784 bios->type = NVBIOS_BMP;
6785 bios->offset = offset;
6ee73861
BS		 6786 return parse_bmp_structure(dev, bios, offset);
6787 }
6788
6789 NV_ERROR(dev, "No known BIOS signature found\n");
6790 return -ENODEV;
6791}
6792
6793int
6794nouveau_run_vbios_init(struct drm_device *dev)
6795{
6796 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6797 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6798 int i, ret = 0;
6799
946fd35f
FJ		 6800 /* Reset the BIOS head to 0. */
6801 bios->state.crtchead = 0;
6ee73861
BS		 6802
6803 if (bios->major_version < 5) /* BMP only */
6804 load_nv17_hw_sequencer_ucode(dev, bios);
6805
6806 if (bios->execute) {
6807 bios->fp.last_script_invoc = 0;
6808 bios->fp.lvds_init_run = false;
6809 }
6810
6811 parse_init_tables(bios);
6812
6813 /*
6814 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6815 * parser will run this right after the init tables, the binary
6816 * driver appears to run it at some point later.
6817 */
6818 if (bios->some_script_ptr) {
6819 struct init_exec iexec = {true, false};
6820
6821 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6822 bios->some_script_ptr);
6823 parse_init_table(bios, bios->some_script_ptr, &iexec);
6824 }
6825
6826 if (dev_priv->card_type >= NV_50) {
7f245b20 6827 for (i = 0; i < bios->dcb.entries; i++) {
6ee73861 6828 nouveau_bios_run_display_table(dev,
7f245b20 6829 &bios->dcb.entry[i],
6ee73861
BS		 6830 0, 0);
6831 }
6832 }
6833
6ee73861
BS		 6834 return ret;
6835}
6836
6837static void
6838nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6839{
6840 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6841 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6842 struct dcb_i2c_entry *entry;
6843 int i;
6844
7f245b20 6845 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6846 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6847 nouveau_i2c_fini(dev, entry);
6848}
6849
d13102c6
BS		 6850static bool
6851nouveau_bios_posted(struct drm_device *dev)
6852{
6853 struct drm_nouveau_private *dev_priv = dev->dev_private;
d13102c6
BS		 6854 unsigned htotal;
6855
c1b60ece 6856 if (dev_priv->card_type >= NV_50) {
d13102c6
BS		 6857 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6858 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6859 return false;
6860 return true;
6861 }
6862
d13102c6
BS		 6863 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6864 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6865 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6866 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6867 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
03cd06ca 6868
d13102c6
BS		 6869 return (htotal != 0);
6870}
6871
6ee73861
BS		 6872int
6873nouveau_bios_init(struct drm_device *dev)
6874{
6875 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6876 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6877 int ret;
6878
6ee73861
BS		 6879 if (!NVInitVBIOS(dev))
6880 return -ENODEV;
6881
6882 ret = nouveau_parse_vbios_struct(dev);
6883 if (ret)
6884 return ret;
6885
2e5702af 6886 ret = parse_dcb_table(dev, bios);
6ee73861
BS		 6887 if (ret)
6888 return ret;
6889
6890 fixup_legacy_i2c(bios);
6891 fixup_legacy_connector(bios);
6892
6893 if (!bios->major_version) /* we don't run version 0 bios */
6894 return 0;
6895
6ee73861
BS		 6896 /* init script execution disabled */
6897 bios->execute = false;
6898
6899 /* ... unless card isn't POSTed already */
d13102c6 6900 if (!nouveau_bios_posted(dev)) {
67eda20e
FJ		 6901 NV_INFO(dev, "Adaptor not initialised, "
6902 "running VBIOS init tables.\n");
6ee73861
BS		 6903 bios->execute = true;
6904 }
0cba1b76
MK		 6905 if (nouveau_force_post)
6906 bios->execute = true;
6ee73861 6907
6ee73861 6908 ret = nouveau_run_vbios_init(dev);
04a39c57 6909 if (ret)
6ee73861 6910 return ret;
6ee73861
BS		 6911
6912 /* feature_byte on BMP is poor, but init always sets CR4B */
6ee73861
BS		 6913 if (bios->major_version < 5)
6914 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6915
6916 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6917 if (bios->is_mobile || bios->major_version >= 5)
6918 ret = parse_fp_mode_table(dev, bios);
6ee73861
BS		 6919
6920 /* allow subsequent scripts to execute */
6921 bios->execute = true;
6922
6923 return 0;
6924}
6925
6926void
6927nouveau_bios_takedown(struct drm_device *dev)
6928{
6929 nouveau_bios_i2c_devices_takedown(dev);
6930}