projects / GitHub / exynos8895 / android_kernel_samsung_universal8895.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/nouveau/bios: fold fixup_legacy_i2c
[GitHub/exynos8895/android_kernel_samsung_universal8895.git] / drivers / gpu / drm / nouveau / nouveau_bios.c
CommitLineData
6ee73861
BS		 1/*
2 * Copyright 2005-2006 Erik Waling
3 * Copyright 2006 Stephane Marchesin
4 * Copyright 2007-2009 Stuart Bennett
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
20 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
21 * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 */
24
25#include "drmP.h"
26#define NV_DEBUG_NOTRACE
27#include "nouveau_drv.h"
28#include "nouveau_hw.h"
25908b77 29#include "nouveau_encoder.h"
6ee73861 30
67eda20e
FJ		 31#include <linux/io-mapping.h>
32
6ee73861
BS		 33/* these defines are made up */
34#define NV_CIO_CRE_44_HEADA 0x0
35#define NV_CIO_CRE_44_HEADB 0x3
36#define FEATURE_MOBILE 0x10 /* also FEATURE_QUADRO for BMP */
6ee73861
BS		 37
38#define EDID1_LEN 128
39
40#define BIOSLOG(sip, fmt, arg...) NV_DEBUG(sip->dev, fmt, ##arg)
41#define LOG_OLD_VALUE(x)
42
6ee73861
BS		 43struct init_exec {
44 bool execute;
45 bool repeat;
46};
47
48static bool nv_cksum(const uint8_t *data, unsigned int length)
49{
50 /*
51 * There's a few checksums in the BIOS, so here's a generic checking
52 * function.
53 */
54 int i;
55 uint8_t sum = 0;
56
57 for (i = 0; i < length; i++)
58 sum += data[i];
59
60 if (sum)
61 return true;
62
63 return false;
64}
65
66static int
67score_vbios(struct drm_device *dev, const uint8_t *data, const bool writeable)
68{
69 if (!(data[0] == 0x55 && data[1] == 0xAA)) {
70 NV_TRACEWARN(dev, "... BIOS signature not found\n");
71 return 0;
72 }
73
74 if (nv_cksum(data, data[2] * 512)) {
75 NV_TRACEWARN(dev, "... BIOS checksum invalid\n");
76 /* if a ro image is somewhat bad, it's probably all rubbish */
77 return writeable ? 2 : 1;
78 } else
79 NV_TRACE(dev, "... appears to be valid\n");
80
81 return 3;
82}
83
84static void load_vbios_prom(struct drm_device *dev, uint8_t *data)
85{
86 struct drm_nouveau_private *dev_priv = dev->dev_private;
87 uint32_t pci_nv_20, save_pci_nv_20;
88 int pcir_ptr;
89 int i;
90
91 if (dev_priv->card_type >= NV_50)
92 pci_nv_20 = 0x88050;
93 else
94 pci_nv_20 = NV_PBUS_PCI_NV_20;
95
96 /* enable ROM access */
97 save_pci_nv_20 = nvReadMC(dev, pci_nv_20);
98 nvWriteMC(dev, pci_nv_20,
99 save_pci_nv_20 & ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
100
101 /* bail if no rom signature */
102 if (nv_rd08(dev, NV_PROM_OFFSET) != 0x55 ||
103 nv_rd08(dev, NV_PROM_OFFSET + 1) != 0xaa)
104 goto out;
105
106 /* additional check (see note below) - read PCI record header */
107 pcir_ptr = nv_rd08(dev, NV_PROM_OFFSET + 0x18) |
108 nv_rd08(dev, NV_PROM_OFFSET + 0x19) << 8;
109 if (nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr) != 'P' ||
110 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 1) != 'C' ||
111 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 2) != 'I' ||
112 nv_rd08(dev, NV_PROM_OFFSET + pcir_ptr + 3) != 'R')
113 goto out;
114
115 /* on some 6600GT/6800LE prom reads are messed up. nvclock alleges a
116 * a good read may be obtained by waiting or re-reading (cargocult: 5x)
117 * each byte. we'll hope pramin has something usable instead
118 */
119 for (i = 0; i < NV_PROM_SIZE; i++)
120 data[i] = nv_rd08(dev, NV_PROM_OFFSET + i);
121
122out:
123 /* disable ROM access */
124 nvWriteMC(dev, pci_nv_20,
125 save_pci_nv_20 | NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED);
126}
127
128static void load_vbios_pramin(struct drm_device *dev, uint8_t *data)
129{
130 struct drm_nouveau_private *dev_priv = dev->dev_private;
131 uint32_t old_bar0_pramin = 0;
132 int i;
133
134 if (dev_priv->card_type >= NV_50) {
9617757f
BS		 135 u64 addr = (u64)(nv_rd32(dev, 0x619f04) & 0xffffff00) << 8;
136 if (!addr) {
137 addr = (u64)nv_rd32(dev, 0x1700) << 16;
138 addr += 0xf0000;
139 }
6ee73861
BS		 140
141 old_bar0_pramin = nv_rd32(dev, 0x1700);
9617757f 142 nv_wr32(dev, 0x1700, addr >> 16);
6ee73861
BS		 143 }
144
145 /* bail if no rom signature */
146 if (nv_rd08(dev, NV_PRAMIN_OFFSET) != 0x55 ||
147 nv_rd08(dev, NV_PRAMIN_OFFSET + 1) != 0xaa)
148 goto out;
149
150 for (i = 0; i < NV_PROM_SIZE; i++)
151 data[i] = nv_rd08(dev, NV_PRAMIN_OFFSET + i);
152
153out:
154 if (dev_priv->card_type >= NV_50)
155 nv_wr32(dev, 0x1700, old_bar0_pramin);
156}
157
158static void load_vbios_pci(struct drm_device *dev, uint8_t *data)
159{
160 void __iomem *rom = NULL;
161 size_t rom_len;
162 int ret;
163
164 ret = pci_enable_rom(dev->pdev);
165 if (ret)
166 return;
167
168 rom = pci_map_rom(dev->pdev, &rom_len);
169 if (!rom)
170 goto out;
171 memcpy_fromio(data, rom, rom_len);
172 pci_unmap_rom(dev->pdev, rom);
173
174out:
175 pci_disable_rom(dev->pdev);
176}
177
afeb3e11
DA		 178static void load_vbios_acpi(struct drm_device *dev, uint8_t *data)
179{
180 int i;
181 int ret;
182 int size = 64 * 1024;
183
184 if (!nouveau_acpi_rom_supported(dev->pdev))
185 return;
186
187 for (i = 0; i < (size / ROM_BIOS_PAGE); i++) {
188 ret = nouveau_acpi_get_bios_chunk(data,
189 (i * ROM_BIOS_PAGE),
190 ROM_BIOS_PAGE);
191 if (ret <= 0)
192 break;
193 }
194 return;
195}
196
6ee73861
BS		 197struct methods {
198 const char desc[8];
199 void (*loadbios)(struct drm_device *, uint8_t *);
200 const bool rw;
6ee73861
BS		 201};
202
41090eb4 203static struct methods shadow_methods[] = {
6ee73861
BS		 204 { "PRAMIN", load_vbios_pramin, true },
205 { "PROM", load_vbios_prom, false },
206 { "PCIROM", load_vbios_pci, true },
41090eb4 207 { "ACPI", load_vbios_acpi, true },
6ee73861 208};
eae6192a 209#define NUM_SHADOW_METHODS ARRAY_SIZE(shadow_methods)
6ee73861
BS		 210
211static bool NVShadowVBIOS(struct drm_device *dev, uint8_t *data)
212{
41090eb4 213 struct methods *methods = shadow_methods;
6ee73861 214 int testscore = 3;
eae6192a 215 int scores[NUM_SHADOW_METHODS], i;
6ee73861
BS		 216
217 if (nouveau_vbios) {
eae6192a 218 for (i = 0; i < NUM_SHADOW_METHODS; i++)
657b6245 219 if (!strcasecmp(nouveau_vbios, methods[i].desc))
6ee73861 220 break;
6ee73861 221
eae6192a 222 if (i < NUM_SHADOW_METHODS) {
6ee73861 223 NV_INFO(dev, "Attempting to use BIOS image from %s\n",
657b6245 224 methods[i].desc);
6ee73861 225
657b6245
MK		 226 methods[i].loadbios(dev, data);
227 if (score_vbios(dev, data, methods[i].rw))
6ee73861
BS		 228 return true;
229 }
230
231 NV_ERROR(dev, "VBIOS source \'%s\' invalid\n", nouveau_vbios);
232 }
233
eae6192a 234 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
6ee73861 235 NV_TRACE(dev, "Attempting to load BIOS image from %s\n",
657b6245 236 methods[i].desc);
6ee73861 237 data[0] = data[1] = 0; /* avoid reuse of previous image */
657b6245
MK		 238 methods[i].loadbios(dev, data);
239 scores[i] = score_vbios(dev, data, methods[i].rw);
240 if (scores[i] == testscore)
6ee73861 241 return true;
6ee73861
BS		 242 }
243
244 while (--testscore > 0) {
eae6192a 245 for (i = 0; i < NUM_SHADOW_METHODS; i++) {
657b6245 246 if (scores[i] == testscore) {
6ee73861 247 NV_TRACE(dev, "Using BIOS image from %s\n",
657b6245
MK		 248 methods[i].desc);
249 methods[i].loadbios(dev, data);
6ee73861
BS		 250 return true;
251 }
6ee73861
BS		 252 }
253 }
254
255 NV_ERROR(dev, "No valid BIOS image found\n");
256 return false;
257}
258
259struct init_tbl_entry {
260 char *name;
261 uint8_t id;
9170a824
BS		 262 /* Return:
263 * > 0: success, length of opcode
264 * 0: success, but abort further parsing of table (INIT_DONE etc)
265 * < 0: failure, table parsing will be aborted
266 */
37383650 267 int (*handler)(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 268};
269
ec64a408 270static int parse_init_table(struct nvbios *, uint16_t, struct init_exec *);
6ee73861
BS		 271
272#define MACRO_INDEX_SIZE 2
273#define MACRO_SIZE 8
274#define CONDITION_SIZE 12
275#define IO_FLAG_CONDITION_SIZE 9
276#define IO_CONDITION_SIZE 5
277#define MEM_INIT_SIZE 66
278
279static void still_alive(void)
280{
281#if 0
282 sync();
c7ca4d1b 283 mdelay(2);
6ee73861
BS		 284#endif
285}
286
287static uint32_t
288munge_reg(struct nvbios *bios, uint32_t reg)
289{
290 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
291 struct dcb_entry *dcbent = bios->display.output;
292
293 if (dev_priv->card_type < NV_50)
294 return reg;
295
02e4f587
BS		 296 if (reg & 0x80000000) {
297 BUG_ON(bios->display.crtc < 0);
298 reg += bios->display.crtc * 0x800;
299 }
300
6ee73861
BS		 301 if (reg & 0x40000000) {
302 BUG_ON(!dcbent);
303
304 reg += (ffs(dcbent->or) - 1) * 0x800;
305 if ((reg & 0x20000000) && !(dcbent->sorconf.link & 1))
306 reg += 0x00000080;
307 }
308
02e4f587 309 reg &= ~0xe0000000;
6ee73861
BS		 310 return reg;
311}
312
313static int
314valid_reg(struct nvbios *bios, uint32_t reg)
315{
316 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
317 struct drm_device *dev = bios->dev;
318
319 /* C51 has misaligned regs on purpose. Marvellous */
9855e584 320 if (reg & 0x2 ||
04a39c57 321 (reg & 0x1 && dev_priv->vbios.chip_version != 0x51))
9855e584
BS		 322 NV_ERROR(dev, "======= misaligned reg 0x%08X =======\n", reg);
323
324 /* warn on C51 regs that haven't been verified accessible in tracing */
04a39c57 325 if (reg & 0x1 && dev_priv->vbios.chip_version == 0x51 &&
6ee73861
BS		 326 reg != 0x130d && reg != 0x1311 && reg != 0x60081d)
327 NV_WARN(dev, "=== C51 misaligned reg 0x%08X not verified ===\n",
328 reg);
329
9855e584
BS		 330 if (reg >= (8*1024*1024)) {
331 NV_ERROR(dev, "=== reg 0x%08x out of mapped bounds ===\n", reg);
332 return 0;
6ee73861 333 }
9855e584
BS		 334
335 return 1;
6ee73861
BS		 336}
337
338static bool
339valid_idx_port(struct nvbios *bios, uint16_t port)
340{
341 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
342 struct drm_device *dev = bios->dev;
343
344 /*
345 * If adding more ports here, the read/write functions below will need
346 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
347 * used for the port in question
348 */
349 if (dev_priv->card_type < NV_50) {
350 if (port == NV_CIO_CRX__COLOR)
351 return true;
352 if (port == NV_VIO_SRX)
353 return true;
354 } else {
355 if (port == NV_CIO_CRX__COLOR)
356 return true;
357 }
358
359 NV_ERROR(dev, "========== unknown indexed io port 0x%04X ==========\n",
360 port);
361
362 return false;
363}
364
365static bool
366valid_port(struct nvbios *bios, uint16_t port)
367{
368 struct drm_device *dev = bios->dev;
369
370 /*
371 * If adding more ports here, the read/write functions below will need
372 * updating so that the correct mmio range (PRMCIO, PRMDIO, PRMVIO) is
373 * used for the port in question
374 */
375 if (port == NV_VIO_VSE2)
376 return true;
377
378 NV_ERROR(dev, "========== unknown io port 0x%04X ==========\n", port);
379
380 return false;
381}
382
383static uint32_t
384bios_rd32(struct nvbios *bios, uint32_t reg)
385{
386 uint32_t data;
387
388 reg = munge_reg(bios, reg);
389 if (!valid_reg(bios, reg))
390 return 0;
391
392 /*
393 * C51 sometimes uses regs with bit0 set in the address. For these
394 * cases there should exist a translation in a BIOS table to an IO
395 * port address which the BIOS uses for accessing the reg
396 *
397 * These only seem to appear for the power control regs to a flat panel,
398 * and the GPIO regs at 0x60081*. In C51 mmio traces the normal regs
399 * for 0x1308 and 0x1310 are used - hence the mask below. An S3
400 * suspend-resume mmio trace from a C51 will be required to see if this
401 * is true for the power microcode in 0x14.., or whether the direct IO
402 * port access method is needed
403 */
404 if (reg & 0x1)
405 reg &= ~0x1;
406
407 data = nv_rd32(bios->dev, reg);
408
409 BIOSLOG(bios, " Read: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
410
411 return data;
412}
413
414static void
415bios_wr32(struct nvbios *bios, uint32_t reg, uint32_t data)
416{
417 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
418
419 reg = munge_reg(bios, reg);
420 if (!valid_reg(bios, reg))
421 return;
422
423 /* see note in bios_rd32 */
424 if (reg & 0x1)
425 reg &= 0xfffffffe;
426
427 LOG_OLD_VALUE(bios_rd32(bios, reg));
428 BIOSLOG(bios, " Write: Reg: 0x%08X, Data: 0x%08X\n", reg, data);
429
04a39c57 430 if (dev_priv->vbios.execute) {
6ee73861
BS		 431 still_alive();
432 nv_wr32(bios->dev, reg, data);
433 }
434}
435
436static uint8_t
437bios_idxprt_rd(struct nvbios *bios, uint16_t port, uint8_t index)
438{
439 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
440 struct drm_device *dev = bios->dev;
441 uint8_t data;
442
443 if (!valid_idx_port(bios, port))
444 return 0;
445
446 if (dev_priv->card_type < NV_50) {
447 if (port == NV_VIO_SRX)
448 data = NVReadVgaSeq(dev, bios->state.crtchead, index);
449 else /* assume NV_CIO_CRX__COLOR */
450 data = NVReadVgaCrtc(dev, bios->state.crtchead, index);
451 } else {
452 uint32_t data32;
453
454 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
455 data = (data32 >> ((index & 3) << 3)) & 0xff;
456 }
457
458 BIOSLOG(bios, " Indexed IO read: Port: 0x%04X, Index: 0x%02X, "
459 "Head: 0x%02X, Data: 0x%02X\n",
460 port, index, bios->state.crtchead, data);
461 return data;
462}
463
464static void
465bios_idxprt_wr(struct nvbios *bios, uint16_t port, uint8_t index, uint8_t data)
466{
467 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
468 struct drm_device *dev = bios->dev;
469
470 if (!valid_idx_port(bios, port))
471 return;
472
473 /*
474 * The current head is maintained in the nvbios member state.crtchead.
475 * We trap changes to CR44 and update the head variable and hence the
476 * register set written.
477 * As CR44 only exists on CRTC0, we update crtchead to head0 in advance
478 * of the write, and to head1 after the write
479 */
480 if (port == NV_CIO_CRX__COLOR && index == NV_CIO_CRE_44 &&
481 data != NV_CIO_CRE_44_HEADB)
482 bios->state.crtchead = 0;
483
484 LOG_OLD_VALUE(bios_idxprt_rd(bios, port, index));
485 BIOSLOG(bios, " Indexed IO write: Port: 0x%04X, Index: 0x%02X, "
486 "Head: 0x%02X, Data: 0x%02X\n",
487 port, index, bios->state.crtchead, data);
488
489 if (bios->execute && dev_priv->card_type < NV_50) {
490 still_alive();
491 if (port == NV_VIO_SRX)
492 NVWriteVgaSeq(dev, bios->state.crtchead, index, data);
493 else /* assume NV_CIO_CRX__COLOR */
494 NVWriteVgaCrtc(dev, bios->state.crtchead, index, data);
495 } else
496 if (bios->execute) {
497 uint32_t data32, shift = (index & 3) << 3;
498
499 still_alive();
500
501 data32 = bios_rd32(bios, NV50_PDISPLAY_VGACRTC(index & ~3));
502 data32 &= ~(0xff << shift);
503 data32 |= (data << shift);
504 bios_wr32(bios, NV50_PDISPLAY_VGACRTC(index & ~3), data32);
505 }
506
507 if (port == NV_CIO_CRX__COLOR &&
508 index == NV_CIO_CRE_44 && data == NV_CIO_CRE_44_HEADB)
509 bios->state.crtchead = 1;
510}
511
512static uint8_t
513bios_port_rd(struct nvbios *bios, uint16_t port)
514{
515 uint8_t data, head = bios->state.crtchead;
516
517 if (!valid_port(bios, port))
518 return 0;
519
520 data = NVReadPRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port);
521
522 BIOSLOG(bios, " IO read: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
523 port, head, data);
524
525 return data;
526}
527
528static void
529bios_port_wr(struct nvbios *bios, uint16_t port, uint8_t data)
530{
531 int head = bios->state.crtchead;
532
533 if (!valid_port(bios, port))
534 return;
535
536 LOG_OLD_VALUE(bios_port_rd(bios, port));
537 BIOSLOG(bios, " IO write: Port: 0x%04X, Head: 0x%02X, Data: 0x%02X\n",
538 port, head, data);
539
540 if (!bios->execute)
541 return;
542
543 still_alive();
544 NVWritePRMVIO(bios->dev, head, NV_PRMVIO0_OFFSET + port, data);
545}
546
547static bool
548io_flag_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
549{
550 /*
551 * The IO flag condition entry has 2 bytes for the CRTC port; 1 byte
552 * for the CRTC index; 1 byte for the mask to apply to the value
553 * retrieved from the CRTC; 1 byte for the shift right to apply to the
554 * masked CRTC value; 2 bytes for the offset to the flag array, to
555 * which the shifted value is added; 1 byte for the mask applied to the
556 * value read from the flag array; and 1 byte for the value to compare
557 * against the masked byte from the flag table.
558 */
559
560 uint16_t condptr = bios->io_flag_condition_tbl_ptr + cond * IO_FLAG_CONDITION_SIZE;
561 uint16_t crtcport = ROM16(bios->data[condptr]);
562 uint8_t crtcindex = bios->data[condptr + 2];
563 uint8_t mask = bios->data[condptr + 3];
564 uint8_t shift = bios->data[condptr + 4];
565 uint16_t flagarray = ROM16(bios->data[condptr + 5]);
566 uint8_t flagarraymask = bios->data[condptr + 7];
567 uint8_t cmpval = bios->data[condptr + 8];
568 uint8_t data;
569
570 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
571 "Shift: 0x%02X, FlagArray: 0x%04X, FAMask: 0x%02X, "
572 "Cmpval: 0x%02X\n",
573 offset, crtcport, crtcindex, mask, shift, flagarray, flagarraymask, cmpval);
574
575 data = bios_idxprt_rd(bios, crtcport, crtcindex);
576
577 data = bios->data[flagarray + ((data & mask) >> shift)];
578 data &= flagarraymask;
579
580 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
581 offset, data, cmpval);
582
583 return (data == cmpval);
584}
585
586static bool
587bios_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
588{
589 /*
590 * The condition table entry has 4 bytes for the address of the
591 * register to check, 4 bytes for a mask to apply to the register and
592 * 4 for a test comparison value
593 */
594
595 uint16_t condptr = bios->condition_tbl_ptr + cond * CONDITION_SIZE;
596 uint32_t reg = ROM32(bios->data[condptr]);
597 uint32_t mask = ROM32(bios->data[condptr + 4]);
598 uint32_t cmpval = ROM32(bios->data[condptr + 8]);
599 uint32_t data;
600
601 BIOSLOG(bios, "0x%04X: Cond: 0x%02X, Reg: 0x%08X, Mask: 0x%08X\n",
602 offset, cond, reg, mask);
603
604 data = bios_rd32(bios, reg) & mask;
605
606 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
607 offset, data, cmpval);
608
609 return (data == cmpval);
610}
611
612static bool
613io_condition_met(struct nvbios *bios, uint16_t offset, uint8_t cond)
614{
615 /*
616 * The IO condition entry has 2 bytes for the IO port address; 1 byte
617 * for the index to write to io_port; 1 byte for the mask to apply to
618 * the byte read from io_port+1; and 1 byte for the value to compare
619 * against the masked byte.
620 */
621
622 uint16_t condptr = bios->io_condition_tbl_ptr + cond * IO_CONDITION_SIZE;
623 uint16_t io_port = ROM16(bios->data[condptr]);
624 uint8_t port_index = bios->data[condptr + 2];
625 uint8_t mask = bios->data[condptr + 3];
626 uint8_t cmpval = bios->data[condptr + 4];
627
628 uint8_t data = bios_idxprt_rd(bios, io_port, port_index) & mask;
629
630 BIOSLOG(bios, "0x%04X: Checking if 0x%02X equals 0x%02X\n",
631 offset, data, cmpval);
632
633 return (data == cmpval);
634}
635
636static int
637nv50_pll_set(struct drm_device *dev, uint32_t reg, uint32_t clk)
638{
639 struct drm_nouveau_private *dev_priv = dev->dev_private;
6ee73861
BS		 640 struct nouveau_pll_vals pll;
641 struct pll_lims pll_limits;
ee9f7ef9 642 u32 ctrl, mask, coef;
6ee73861
BS		 643 int ret;
644
645 ret = get_pll_limits(dev, reg, &pll_limits);
646 if (ret)
647 return ret;
648
649 clk = nouveau_calc_pll_mnp(dev, &pll_limits, clk, &pll);
650 if (!clk)
651 return -ERANGE;
652
ee9f7ef9
BS		 653 coef = pll.N1 << 8 | pll.M1;
654 ctrl = pll.log2P << 16;
655 mask = 0x00070000;
656 if (reg == 0x004008) {
657 mask |= 0x01f80000;
658 ctrl |= (pll_limits.log2p_bias << 19);
659 ctrl |= (pll.log2P << 22);
6ee73861
BS		 660 }
661
ee9f7ef9
BS		 662 if (!dev_priv->vbios.execute)
663 return 0;
664
665 nv_mask(dev, reg + 0, mask, ctrl);
666 nv_wr32(dev, reg + 4, coef);
6ee73861
BS		 667 return 0;
668}
669
670static int
671setPLL(struct nvbios *bios, uint32_t reg, uint32_t clk)
672{
673 struct drm_device *dev = bios->dev;
674 struct drm_nouveau_private *dev_priv = dev->dev_private;
675 /* clk in kHz */
676 struct pll_lims pll_lim;
677 struct nouveau_pll_vals pllvals;
678 int ret;
679
680 if (dev_priv->card_type >= NV_50)
681 return nv50_pll_set(dev, reg, clk);
682
683 /* high regs (such as in the mac g5 table) are not -= 4 */
684 ret = get_pll_limits(dev, reg > 0x405c ? reg : reg - 4, &pll_lim);
685 if (ret)
686 return ret;
687
688 clk = nouveau_calc_pll_mnp(dev, &pll_lim, clk, &pllvals);
689 if (!clk)
690 return -ERANGE;
691
692 if (bios->execute) {
693 still_alive();
694 nouveau_hw_setpll(dev, reg, &pllvals);
695 }
696
697 return 0;
698}
699
700static int dcb_entry_idx_from_crtchead(struct drm_device *dev)
701{
702 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 703 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 704
705 /*
706 * For the results of this function to be correct, CR44 must have been
707 * set (using bios_idxprt_wr to set crtchead), CR58 set for CR57 = 0,
708 * and the DCB table parsed, before the script calling the function is
709 * run. run_digital_op_script is example of how to do such setup
710 */
711
712 uint8_t dcb_entry = NVReadVgaCrtc5758(dev, bios->state.crtchead, 0);
713
7f245b20 714 if (dcb_entry > bios->dcb.entries) {
6ee73861
BS		 715 NV_ERROR(dev, "CR58 doesn't have a valid DCB entry currently "
716 "(%02X)\n", dcb_entry);
717 dcb_entry = 0x7f; /* unused / invalid marker */
718 }
719
720 return dcb_entry;
721}
722
f8b0be1a
BS		 723static int
724read_dcb_i2c_entry(struct drm_device *dev, int dcb_version, uint8_t *i2ctable, int index, struct dcb_i2c_entry *i2c)
725{
726 uint8_t dcb_i2c_ver = dcb_version, headerlen = 0, entry_len = 4;
727 int i2c_entries = DCB_MAX_NUM_I2C_ENTRIES;
728 int recordoffset = 0, rdofs = 1, wrofs = 0;
729 uint8_t port_type = 0;
730
731 if (!i2ctable)
732 return -EINVAL;
733
734 if (dcb_version >= 0x30) {
735 if (i2ctable[0] != dcb_version) /* necessary? */
736 NV_WARN(dev,
737 "DCB I2C table version mismatch (%02X vs %02X)\n",
738 i2ctable[0], dcb_version);
739 dcb_i2c_ver = i2ctable[0];
740 headerlen = i2ctable[1];
741 if (i2ctable[2] <= DCB_MAX_NUM_I2C_ENTRIES)
742 i2c_entries = i2ctable[2];
743 else
744 NV_WARN(dev,
745 "DCB I2C table has more entries than indexable "
746 "(%d entries, max %d)\n", i2ctable[2],
747 DCB_MAX_NUM_I2C_ENTRIES);
748 entry_len = i2ctable[3];
749 /* [4] is i2c_default_indices, read in parse_dcb_table() */
750 }
751 /*
752 * It's your own fault if you call this function on a DCB 1.1 BIOS --
753 * the test below is for DCB 1.2
754 */
755 if (dcb_version < 0x14) {
756 recordoffset = 2;
757 rdofs = 0;
758 wrofs = 1;
759 }
760
761 if (index == 0xf)
762 return 0;
763 if (index >= i2c_entries) {
764 NV_ERROR(dev, "DCB I2C index too big (%d >= %d)\n",
765 index, i2ctable[2]);
766 return -ENOENT;
767 }
768 if (i2ctable[headerlen + entry_len * index + 3] == 0xff) {
769 NV_ERROR(dev, "DCB I2C entry invalid\n");
770 return -EINVAL;
771 }
772
773 if (dcb_i2c_ver >= 0x30) {
774 port_type = i2ctable[headerlen + recordoffset + 3 + entry_len * index];
775
776 /*
777 * Fixup for chips using same address offset for read and
778 * write.
779 */
780 if (port_type == 4) /* seen on C51 */
781 rdofs = wrofs = 1;
782 if (port_type >= 5) /* G80+ */
783 rdofs = wrofs = 0;
784 }
785
786 if (dcb_i2c_ver >= 0x40) {
787 if (port_type != 5 && port_type != 6)
788 NV_WARN(dev, "DCB I2C table has port type %d\n", port_type);
789
790 i2c->entry = ROM32(i2ctable[headerlen + recordoffset + entry_len * index]);
791 }
792
793 i2c->port_type = port_type;
794 i2c->read = i2ctable[headerlen + recordoffset + rdofs + entry_len * index];
795 i2c->write = i2ctable[headerlen + recordoffset + wrofs + entry_len * index];
796
797 return 0;
798}
799
6ee73861
BS		 800static struct nouveau_i2c_chan *
801init_i2c_device_find(struct drm_device *dev, int i2c_index)
802{
803 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 804 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6ee73861
BS		 805
806 if (i2c_index == 0xff) {
807 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
808 int idx = dcb_entry_idx_from_crtchead(dev), shift = 0;
7f245b20 809 int default_indices = dcb->i2c_default_indices;
6ee73861 810
7f245b20 811 if (idx != 0x7f && dcb->entry[idx].i2c_upper_default)
6ee73861
BS		 812 shift = 4;
813
814 i2c_index = (default_indices >> shift) & 0xf;
815 }
816 if (i2c_index == 0x80) /* g80+ */
7f245b20 817 i2c_index = dcb->i2c_default_indices & 0xf;
04f542c0
BS		 818 else
819 if (i2c_index == 0x81)
820 i2c_index = (dcb->i2c_default_indices & 0xf0) >> 4;
6ee73861 821
75047944 822 if (i2c_index >= DCB_MAX_NUM_I2C_ENTRIES) {
f8b0be1a
BS		 823 NV_ERROR(dev, "invalid i2c_index 0x%x\n", i2c_index);
824 return NULL;
825 }
826
827 /* Make sure i2c table entry has been parsed, it may not
828 * have been if this is a bus not referenced by a DCB encoder
829 */
830 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
831 i2c_index, &dcb->i2c[i2c_index]);
832
6ee73861
BS		 833 return nouveau_i2c_find(dev, i2c_index);
834}
835
7f245b20
BS		 836static uint32_t
837get_tmds_index_reg(struct drm_device *dev, uint8_t mlv)
6ee73861
BS		 838{
839 /*
840 * For mlv < 0x80, it is an index into a table of TMDS base addresses.
841 * For mlv == 0x80 use the "or" value of the dcb_entry indexed by
842 * CR58 for CR57 = 0 to index a table of offsets to the basic
843 * 0x6808b0 address.
844 * For mlv == 0x81 use the "or" value of the dcb_entry indexed by
845 * CR58 for CR57 = 0 to index a table of offsets to the basic
846 * 0x6808b0 address, and then flip the offset by 8.
847 */
848
849 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 850 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 851 const int pramdac_offset[13] = {
852 0, 0, 0x8, 0, 0x2000, 0, 0, 0, 0x2008, 0, 0, 0, 0x2000 };
853 const uint32_t pramdac_table[4] = {
854 0x6808b0, 0x6808b8, 0x6828b0, 0x6828b8 };
855
856 if (mlv >= 0x80) {
857 int dcb_entry, dacoffset;
858
859 /* note: dcb_entry_idx_from_crtchead needs pre-script set-up */
860 dcb_entry = dcb_entry_idx_from_crtchead(dev);
861 if (dcb_entry == 0x7f)
862 return 0;
7f245b20 863 dacoffset = pramdac_offset[bios->dcb.entry[dcb_entry].or];
6ee73861
BS		 864 if (mlv == 0x81)
865 dacoffset ^= 8;
866 return 0x6808b0 + dacoffset;
867 } else {
df31ef4d 868 if (mlv >= ARRAY_SIZE(pramdac_table)) {
6ee73861
BS		 869 NV_ERROR(dev, "Magic Lookup Value too big (%02X)\n",
870 mlv);
871 return 0;
872 }
873 return pramdac_table[mlv];
874 }
875}
876
37383650 877static int
6ee73861
BS		 878init_io_restrict_prog(struct nvbios *bios, uint16_t offset,
879 struct init_exec *iexec)
880{
881 /*
882 * INIT_IO_RESTRICT_PROG opcode: 0x32 ('2')
883 *
884 * offset (8 bit): opcode
885 * offset + 1 (16 bit): CRTC port
886 * offset + 3 (8 bit): CRTC index
887 * offset + 4 (8 bit): mask
888 * offset + 5 (8 bit): shift
889 * offset + 6 (8 bit): count
890 * offset + 7 (32 bit): register
891 * offset + 11 (32 bit): configuration 1
892 * ...
893 *
894 * Starting at offset + 11 there are "count" 32 bit values.
895 * To find out which value to use read index "CRTC index" on "CRTC
896 * port", AND this value with "mask" and then bit shift right "shift"
897 * bits. Read the appropriate value using this index and write to
898 * "register"
899 */
900
901 uint16_t crtcport = ROM16(bios->data[offset + 1]);
902 uint8_t crtcindex = bios->data[offset + 3];
903 uint8_t mask = bios->data[offset + 4];
904 uint8_t shift = bios->data[offset + 5];
905 uint8_t count = bios->data[offset + 6];
906 uint32_t reg = ROM32(bios->data[offset + 7]);
907 uint8_t config;
908 uint32_t configval;
37383650 909 int len = 11 + count * 4;
6ee73861
BS		 910
911 if (!iexec->execute)
37383650 912 return len;
6ee73861
BS		 913
914 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
915 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
916 offset, crtcport, crtcindex, mask, shift, count, reg);
917
918 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
919 if (config > count) {
920 NV_ERROR(bios->dev,
921 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
922 offset, config, count);
309b8c89 923 return len;
6ee73861
BS		 924 }
925
926 configval = ROM32(bios->data[offset + 11 + config * 4]);
927
928 BIOSLOG(bios, "0x%04X: Writing config %02X\n", offset, config);
929
930 bios_wr32(bios, reg, configval);
931
37383650 932 return len;
6ee73861
BS		 933}
934
37383650 935static int
6ee73861
BS		 936init_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
937{
938 /*
939 * INIT_REPEAT opcode: 0x33 ('3')
940 *
941 * offset (8 bit): opcode
942 * offset + 1 (8 bit): count
943 *
944 * Execute script following this opcode up to INIT_REPEAT_END
945 * "count" times
946 */
947
948 uint8_t count = bios->data[offset + 1];
949 uint8_t i;
950
951 /* no iexec->execute check by design */
952
953 BIOSLOG(bios, "0x%04X: Repeating following segment %d times\n",
954 offset, count);
955
956 iexec->repeat = true;
957
958 /*
959 * count - 1, as the script block will execute once when we leave this
960 * opcode -- this is compatible with bios behaviour as:
961 * a) the block is always executed at least once, even if count == 0
962 * b) the bios interpreter skips to the op following INIT_END_REPEAT,
963 * while we don't
964 */
965 for (i = 0; i < count - 1; i++)
966 parse_init_table(bios, offset + 2, iexec);
967
968 iexec->repeat = false;
969
37383650 970 return 2;
6ee73861
BS		 971}
972
37383650 973static int
6ee73861
BS		 974init_io_restrict_pll(struct nvbios *bios, uint16_t offset,
975 struct init_exec *iexec)
976{
977 /*
978 * INIT_IO_RESTRICT_PLL opcode: 0x34 ('4')
979 *
980 * offset (8 bit): opcode
981 * offset + 1 (16 bit): CRTC port
982 * offset + 3 (8 bit): CRTC index
983 * offset + 4 (8 bit): mask
984 * offset + 5 (8 bit): shift
985 * offset + 6 (8 bit): IO flag condition index
986 * offset + 7 (8 bit): count
987 * offset + 8 (32 bit): register
988 * offset + 12 (16 bit): frequency 1
989 * ...
990 *
991 * Starting at offset + 12 there are "count" 16 bit frequencies (10kHz).
992 * Set PLL register "register" to coefficients for frequency n,
993 * selected by reading index "CRTC index" of "CRTC port" ANDed with
994 * "mask" and shifted right by "shift".
995 *
996 * If "IO flag condition index" > 0, and condition met, double
997 * frequency before setting it.
998 */
999
1000 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1001 uint8_t crtcindex = bios->data[offset + 3];
1002 uint8_t mask = bios->data[offset + 4];
1003 uint8_t shift = bios->data[offset + 5];
1004 int8_t io_flag_condition_idx = bios->data[offset + 6];
1005 uint8_t count = bios->data[offset + 7];
1006 uint32_t reg = ROM32(bios->data[offset + 8]);
1007 uint8_t config;
1008 uint16_t freq;
37383650 1009 int len = 12 + count * 2;
6ee73861
BS		 1010
1011 if (!iexec->execute)
37383650 1012 return len;
6ee73861
BS		 1013
1014 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1015 "Shift: 0x%02X, IO Flag Condition: 0x%02X, "
1016 "Count: 0x%02X, Reg: 0x%08X\n",
1017 offset, crtcport, crtcindex, mask, shift,
1018 io_flag_condition_idx, count, reg);
1019
1020 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1021 if (config > count) {
1022 NV_ERROR(bios->dev,
1023 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1024 offset, config, count);
309b8c89 1025 return len;
6ee73861
BS		 1026 }
1027
1028 freq = ROM16(bios->data[offset + 12 + config * 2]);
1029
1030 if (io_flag_condition_idx > 0) {
1031 if (io_flag_condition_met(bios, offset, io_flag_condition_idx)) {
1032 BIOSLOG(bios, "0x%04X: Condition fulfilled -- "
1033 "frequency doubled\n", offset);
1034 freq *= 2;
1035 } else
1036 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- "
1037 "frequency unchanged\n", offset);
1038 }
1039
1040 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %d0kHz\n",
1041 offset, reg, config, freq);
1042
1043 setPLL(bios, reg, freq * 10);
1044
37383650 1045 return len;
6ee73861
BS		 1046}
1047
37383650 1048static int
6ee73861
BS		 1049init_end_repeat(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1050{
1051 /*
1052 * INIT_END_REPEAT opcode: 0x36 ('6')
1053 *
1054 * offset (8 bit): opcode
1055 *
1056 * Marks the end of the block for INIT_REPEAT to repeat
1057 */
1058
1059 /* no iexec->execute check by design */
1060
1061 /*
1062 * iexec->repeat flag necessary to go past INIT_END_REPEAT opcode when
1063 * we're not in repeat mode
1064 */
1065 if (iexec->repeat)
37383650 1066 return 0;
6ee73861 1067
37383650 1068 return 1;
6ee73861
BS		 1069}
1070
37383650 1071static int
6ee73861
BS		 1072init_copy(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1073{
1074 /*
1075 * INIT_COPY opcode: 0x37 ('7')
1076 *
1077 * offset (8 bit): opcode
1078 * offset + 1 (32 bit): register
1079 * offset + 5 (8 bit): shift
1080 * offset + 6 (8 bit): srcmask
1081 * offset + 7 (16 bit): CRTC port
1082 * offset + 9 (8 bit): CRTC index
1083 * offset + 10 (8 bit): mask
1084 *
1085 * Read index "CRTC index" on "CRTC port", AND with "mask", OR with
1086 * (REGVAL("register") >> "shift" & "srcmask") and write-back to CRTC
1087 * port
1088 */
1089
1090 uint32_t reg = ROM32(bios->data[offset + 1]);
1091 uint8_t shift = bios->data[offset + 5];
1092 uint8_t srcmask = bios->data[offset + 6];
1093 uint16_t crtcport = ROM16(bios->data[offset + 7]);
1094 uint8_t crtcindex = bios->data[offset + 9];
1095 uint8_t mask = bios->data[offset + 10];
1096 uint32_t data;
1097 uint8_t crtcdata;
1098
1099 if (!iexec->execute)
37383650 1100 return 11;
6ee73861
BS		 1101
1102 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%02X, "
1103 "Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X\n",
1104 offset, reg, shift, srcmask, crtcport, crtcindex, mask);
1105
1106 data = bios_rd32(bios, reg);
1107
1108 if (shift < 0x80)
1109 data >>= shift;
1110 else
1111 data <<= (0x100 - shift);
1112
1113 data &= srcmask;
1114
1115 crtcdata = bios_idxprt_rd(bios, crtcport, crtcindex) & mask;
1116 crtcdata |= (uint8_t)data;
1117 bios_idxprt_wr(bios, crtcport, crtcindex, crtcdata);
1118
37383650 1119 return 11;
6ee73861
BS		 1120}
1121
37383650 1122static int
6ee73861
BS		 1123init_not(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1124{
1125 /*
1126 * INIT_NOT opcode: 0x38 ('8')
1127 *
1128 * offset (8 bit): opcode
1129 *
1130 * Invert the current execute / no-execute condition (i.e. "else")
1131 */
1132 if (iexec->execute)
1133 BIOSLOG(bios, "0x%04X: ------ Skipping following commands ------\n", offset);
1134 else
1135 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", offset);
1136
1137 iexec->execute = !iexec->execute;
37383650 1138 return 1;
6ee73861
BS		 1139}
1140
37383650 1141static int
6ee73861
BS		 1142init_io_flag_condition(struct nvbios *bios, uint16_t offset,
1143 struct init_exec *iexec)
1144{
1145 /*
1146 * INIT_IO_FLAG_CONDITION opcode: 0x39 ('9')
1147 *
1148 * offset (8 bit): opcode
1149 * offset + 1 (8 bit): condition number
1150 *
1151 * Check condition "condition number" in the IO flag condition table.
1152 * If condition not met skip subsequent opcodes until condition is
1153 * inverted (INIT_NOT), or we hit INIT_RESUME
1154 */
1155
1156 uint8_t cond = bios->data[offset + 1];
1157
1158 if (!iexec->execute)
37383650 1159 return 2;
6ee73861
BS		 1160
1161 if (io_flag_condition_met(bios, offset, cond))
1162 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
1163 else {
1164 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
1165 iexec->execute = false;
1166 }
1167
37383650 1168 return 2;
6ee73861
BS		 1169}
1170
25908b77
BS		 1171static int
1172init_dp_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1173{
1174 /*
1175 * INIT_DP_CONDITION opcode: 0x3A ('')
1176 *
1177 * offset (8 bit): opcode
1178 * offset + 1 (8 bit): "sub" opcode
1179 * offset + 2 (8 bit): unknown
1180 *
1181 */
1182
25908b77
BS		 1183 struct dcb_entry *dcb = bios->display.output;
1184 struct drm_device *dev = bios->dev;
1185 uint8_t cond = bios->data[offset + 1];
5f1800bd 1186 uint8_t *table, *entry;
25908b77
BS		 1187
1188 BIOSLOG(bios, "0x%04X: subop 0x%02X\n", offset, cond);
1189
1190 if (!iexec->execute)
1191 return 3;
1192
5f1800bd
BS		 1193 table = nouveau_dp_bios_data(dev, dcb, &entry);
1194 if (!table)
309b8c89 1195 return 3;
25908b77
BS		 1196
1197 switch (cond) {
1198 case 0:
1199 {
1200 struct dcb_connector_table_entry *ent =
1201 &bios->dcb.connector.entry[dcb->connector];
1202
1203 if (ent->type != DCB_CONNECTOR_eDP)
1204 iexec->execute = false;
1205 }
1206 break;
1207 case 1:
1208 case 2:
5f1800bd 1209 if (!(entry[5] & cond))
25908b77
BS		 1210 iexec->execute = false;
1211 break;
1212 case 5:
1213 {
1214 struct nouveau_i2c_chan *auxch;
1215 int ret;
1216
1217 auxch = nouveau_i2c_find(dev, bios->display.output->i2c_index);
309b8c89
BS		 1218 if (!auxch) {
1219 NV_ERROR(dev, "0x%04X: couldn't get auxch\n", offset);
1220 return 3;
1221 }
25908b77
BS		 1222
1223 ret = nouveau_dp_auxch(auxch, 9, 0xd, &cond, 1);
309b8c89
BS		 1224 if (ret) {
1225 NV_ERROR(dev, "0x%04X: auxch rd fail: %d\n", offset, ret);
1226 return 3;
1227 }
25908b77 1228
64d202b4 1229 if (!(cond & 1))
25908b77
BS		 1230 iexec->execute = false;
1231 }
1232 break;
1233 default:
1234 NV_WARN(dev, "0x%04X: unknown INIT_3A op: %d\n", offset, cond);
1235 break;
1236 }
1237
1238 if (iexec->execute)
1239 BIOSLOG(bios, "0x%04X: continuing to execute\n", offset);
1240 else
1241 BIOSLOG(bios, "0x%04X: skipping following commands\n", offset);
1242
1243 return 3;
1244}
1245
1246static int
1247init_op_3b(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1248{
1249 /*
1250 * INIT_3B opcode: 0x3B ('')
1251 *
1252 * offset (8 bit): opcode
1253 * offset + 1 (8 bit): crtc index
1254 *
1255 */
1256
1257 uint8_t or = ffs(bios->display.output->or) - 1;
1258 uint8_t index = bios->data[offset + 1];
1259 uint8_t data;
1260
1261 if (!iexec->execute)
1262 return 2;
1263
1264 data = bios_idxprt_rd(bios, 0x3d4, index);
1265 bios_idxprt_wr(bios, 0x3d4, index, data & ~(1 << or));
1266 return 2;
1267}
1268
1269static int
1270init_op_3c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1271{
1272 /*
1273 * INIT_3C opcode: 0x3C ('')
1274 *
1275 * offset (8 bit): opcode
1276 * offset + 1 (8 bit): crtc index
1277 *
1278 */
1279
1280 uint8_t or = ffs(bios->display.output->or) - 1;
1281 uint8_t index = bios->data[offset + 1];
1282 uint8_t data;
1283
1284 if (!iexec->execute)
1285 return 2;
1286
1287 data = bios_idxprt_rd(bios, 0x3d4, index);
1288 bios_idxprt_wr(bios, 0x3d4, index, data | (1 << or));
1289 return 2;
1290}
1291
37383650 1292static int
6ee73861
BS		 1293init_idx_addr_latched(struct nvbios *bios, uint16_t offset,
1294 struct init_exec *iexec)
1295{
1296 /*
1297 * INIT_INDEX_ADDRESS_LATCHED opcode: 0x49 ('I')
1298 *
1299 * offset (8 bit): opcode
1300 * offset + 1 (32 bit): control register
1301 * offset + 5 (32 bit): data register
1302 * offset + 9 (32 bit): mask
1303 * offset + 13 (32 bit): data
1304 * offset + 17 (8 bit): count
1305 * offset + 18 (8 bit): address 1
1306 * offset + 19 (8 bit): data 1
1307 * ...
1308 *
1309 * For each of "count" address and data pairs, write "data n" to
1310 * "data register", read the current value of "control register",
1311 * and write it back once ANDed with "mask", ORed with "data",
1312 * and ORed with "address n"
1313 */
1314
1315 uint32_t controlreg = ROM32(bios->data[offset + 1]);
1316 uint32_t datareg = ROM32(bios->data[offset + 5]);
1317 uint32_t mask = ROM32(bios->data[offset + 9]);
1318 uint32_t data = ROM32(bios->data[offset + 13]);
1319 uint8_t count = bios->data[offset + 17];
37383650 1320 int len = 18 + count * 2;
6ee73861
BS		 1321 uint32_t value;
1322 int i;
1323
1324 if (!iexec->execute)
37383650 1325 return len;
6ee73861
BS		 1326
1327 BIOSLOG(bios, "0x%04X: ControlReg: 0x%08X, DataReg: 0x%08X, "
1328 "Mask: 0x%08X, Data: 0x%08X, Count: 0x%02X\n",
1329 offset, controlreg, datareg, mask, data, count);
1330
1331 for (i = 0; i < count; i++) {
1332 uint8_t instaddress = bios->data[offset + 18 + i * 2];
1333 uint8_t instdata = bios->data[offset + 19 + i * 2];
1334
1335 BIOSLOG(bios, "0x%04X: Address: 0x%02X, Data: 0x%02X\n",
1336 offset, instaddress, instdata);
1337
1338 bios_wr32(bios, datareg, instdata);
1339 value = bios_rd32(bios, controlreg) & mask;
1340 value |= data;
1341 value |= instaddress;
1342 bios_wr32(bios, controlreg, value);
1343 }
1344
37383650 1345 return len;
6ee73861
BS		 1346}
1347
37383650 1348static int
6ee73861
BS		 1349init_io_restrict_pll2(struct nvbios *bios, uint16_t offset,
1350 struct init_exec *iexec)
1351{
1352 /*
1353 * INIT_IO_RESTRICT_PLL2 opcode: 0x4A ('J')
1354 *
1355 * offset (8 bit): opcode
1356 * offset + 1 (16 bit): CRTC port
1357 * offset + 3 (8 bit): CRTC index
1358 * offset + 4 (8 bit): mask
1359 * offset + 5 (8 bit): shift
1360 * offset + 6 (8 bit): count
1361 * offset + 7 (32 bit): register
1362 * offset + 11 (32 bit): frequency 1
1363 * ...
1364 *
1365 * Starting at offset + 11 there are "count" 32 bit frequencies (kHz).
1366 * Set PLL register "register" to coefficients for frequency n,
1367 * selected by reading index "CRTC index" of "CRTC port" ANDed with
1368 * "mask" and shifted right by "shift".
1369 */
1370
1371 uint16_t crtcport = ROM16(bios->data[offset + 1]);
1372 uint8_t crtcindex = bios->data[offset + 3];
1373 uint8_t mask = bios->data[offset + 4];
1374 uint8_t shift = bios->data[offset + 5];
1375 uint8_t count = bios->data[offset + 6];
1376 uint32_t reg = ROM32(bios->data[offset + 7]);
37383650 1377 int len = 11 + count * 4;
6ee73861
BS		 1378 uint8_t config;
1379 uint32_t freq;
1380
1381 if (!iexec->execute)
37383650 1382 return len;
6ee73861
BS		 1383
1384 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
1385 "Shift: 0x%02X, Count: 0x%02X, Reg: 0x%08X\n",
1386 offset, crtcport, crtcindex, mask, shift, count, reg);
1387
1388 if (!reg)
37383650 1389 return len;
6ee73861
BS		 1390
1391 config = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) >> shift;
1392 if (config > count) {
1393 NV_ERROR(bios->dev,
1394 "0x%04X: Config 0x%02X exceeds maximal bound 0x%02X\n",
1395 offset, config, count);
309b8c89 1396 return len;
6ee73861
BS		 1397 }
1398
1399 freq = ROM32(bios->data[offset + 11 + config * 4]);
1400
1401 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Config: 0x%02X, Freq: %dkHz\n",
1402 offset, reg, config, freq);
1403
1404 setPLL(bios, reg, freq);
1405
37383650 1406 return len;
6ee73861
BS		 1407}
1408
37383650 1409static int
6ee73861
BS		 1410init_pll2(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1411{
1412 /*
1413 * INIT_PLL2 opcode: 0x4B ('K')
1414 *
1415 * offset (8 bit): opcode
1416 * offset + 1 (32 bit): register
1417 * offset + 5 (32 bit): freq
1418 *
1419 * Set PLL register "register" to coefficients for frequency "freq"
1420 */
1421
1422 uint32_t reg = ROM32(bios->data[offset + 1]);
1423 uint32_t freq = ROM32(bios->data[offset + 5]);
1424
1425 if (!iexec->execute)
37383650 1426 return 9;
6ee73861
BS		 1427
1428 BIOSLOG(bios, "0x%04X: Reg: 0x%04X, Freq: %dkHz\n",
1429 offset, reg, freq);
1430
1431 setPLL(bios, reg, freq);
37383650 1432 return 9;
6ee73861
BS		 1433}
1434
37383650 1435static int
6ee73861
BS		 1436init_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1437{
1438 /*
1439 * INIT_I2C_BYTE opcode: 0x4C ('L')
1440 *
1441 * offset (8 bit): opcode
1442 * offset + 1 (8 bit): DCB I2C table entry index
1443 * offset + 2 (8 bit): I2C slave address
1444 * offset + 3 (8 bit): count
1445 * offset + 4 (8 bit): I2C register 1
1446 * offset + 5 (8 bit): mask 1
1447 * offset + 6 (8 bit): data 1
1448 * ...
1449 *
1450 * For each of "count" registers given by "I2C register n" on the device
1451 * addressed by "I2C slave address" on the I2C bus given by
1452 * "DCB I2C table entry index", read the register, AND the result with
1453 * "mask n" and OR it with "data n" before writing it back to the device
1454 */
1455
309b8c89 1456 struct drm_device *dev = bios->dev;
6ee73861 1457 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1458 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1459 uint8_t count = bios->data[offset + 3];
1460 struct nouveau_i2c_chan *chan;
893887ed
BS		 1461 int len = 4 + count * 3;
1462 int ret, i;
6ee73861
BS		 1463
1464 if (!iexec->execute)
37383650 1465 return len;
6ee73861
BS		 1466
1467 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1468 "Count: 0x%02X\n",
1469 offset, i2c_index, i2c_address, count);
1470
309b8c89
BS		 1471 chan = init_i2c_device_find(dev, i2c_index);
1472 if (!chan) {
1473 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1474 return len;
1475 }
6ee73861
BS		 1476
1477 for (i = 0; i < count; i++) {
893887ed 1478 uint8_t reg = bios->data[offset + 4 + i * 3];
6ee73861
BS		 1479 uint8_t mask = bios->data[offset + 5 + i * 3];
1480 uint8_t data = bios->data[offset + 6 + i * 3];
893887ed 1481 union i2c_smbus_data val;
6ee73861 1482
893887ed
BS		 1483 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1484 I2C_SMBUS_READ, reg,
1485 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1486 if (ret < 0) {
1487 NV_ERROR(dev, "0x%04X: i2c rd fail: %d\n", offset, ret);
1488 return len;
1489 }
6ee73861
BS		 1490
1491 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
1492 "Mask: 0x%02X, Data: 0x%02X\n",
893887ed 1493 offset, reg, val.byte, mask, data);
6ee73861 1494
893887ed
BS		 1495 if (!bios->execute)
1496 continue;
6ee73861 1497
893887ed
BS		 1498 val.byte &= mask;
1499 val.byte |= data;
1500 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1501 I2C_SMBUS_WRITE, reg,
1502 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1503 if (ret < 0) {
1504 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1505 return len;
1506 }
6ee73861
BS		 1507 }
1508
37383650 1509 return len;
6ee73861
BS		 1510}
1511
37383650 1512static int
6ee73861
BS		 1513init_zm_i2c_byte(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1514{
1515 /*
1516 * INIT_ZM_I2C_BYTE opcode: 0x4D ('M')
1517 *
1518 * offset (8 bit): opcode
1519 * offset + 1 (8 bit): DCB I2C table entry index
1520 * offset + 2 (8 bit): I2C slave address
1521 * offset + 3 (8 bit): count
1522 * offset + 4 (8 bit): I2C register 1
1523 * offset + 5 (8 bit): data 1
1524 * ...
1525 *
1526 * For each of "count" registers given by "I2C register n" on the device
1527 * addressed by "I2C slave address" on the I2C bus given by
1528 * "DCB I2C table entry index", set the register to "data n"
1529 */
1530
309b8c89 1531 struct drm_device *dev = bios->dev;
6ee73861 1532 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1533 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861
BS		 1534 uint8_t count = bios->data[offset + 3];
1535 struct nouveau_i2c_chan *chan;
893887ed
BS		 1536 int len = 4 + count * 2;
1537 int ret, i;
6ee73861
BS		 1538
1539 if (!iexec->execute)
37383650 1540 return len;
6ee73861
BS		 1541
1542 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1543 "Count: 0x%02X\n",
1544 offset, i2c_index, i2c_address, count);
1545
309b8c89
BS		 1546 chan = init_i2c_device_find(dev, i2c_index);
1547 if (!chan) {
1548 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1549 return len;
1550 }
6ee73861
BS		 1551
1552 for (i = 0; i < count; i++) {
893887ed
BS		 1553 uint8_t reg = bios->data[offset + 4 + i * 2];
1554 union i2c_smbus_data val;
1555
1556 val.byte = bios->data[offset + 5 + i * 2];
6ee73861
BS		 1557
1558 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Data: 0x%02X\n",
893887ed
BS		 1559 offset, reg, val.byte);
1560
1561 if (!bios->execute)
1562 continue;
1563
1564 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
1565 I2C_SMBUS_WRITE, reg,
1566 I2C_SMBUS_BYTE_DATA, &val);
309b8c89
BS		 1567 if (ret < 0) {
1568 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1569 return len;
1570 }
6ee73861
BS		 1571 }
1572
37383650 1573 return len;
6ee73861
BS		 1574}
1575
37383650 1576static int
6ee73861
BS		 1577init_zm_i2c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1578{
1579 /*
1580 * INIT_ZM_I2C opcode: 0x4E ('N')
1581 *
1582 * offset (8 bit): opcode
1583 * offset + 1 (8 bit): DCB I2C table entry index
1584 * offset + 2 (8 bit): I2C slave address
1585 * offset + 3 (8 bit): count
1586 * offset + 4 (8 bit): data 1
1587 * ...
1588 *
1589 * Send "count" bytes ("data n") to the device addressed by "I2C slave
1590 * address" on the I2C bus given by "DCB I2C table entry index"
1591 */
1592
309b8c89 1593 struct drm_device *dev = bios->dev;
6ee73861 1594 uint8_t i2c_index = bios->data[offset + 1];
893887ed 1595 uint8_t i2c_address = bios->data[offset + 2] >> 1;
6ee73861 1596 uint8_t count = bios->data[offset + 3];
37383650 1597 int len = 4 + count;
6ee73861
BS		 1598 struct nouveau_i2c_chan *chan;
1599 struct i2c_msg msg;
1600 uint8_t data[256];
309b8c89 1601 int ret, i;
6ee73861
BS		 1602
1603 if (!iexec->execute)
37383650 1604 return len;
6ee73861
BS		 1605
1606 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X, "
1607 "Count: 0x%02X\n",
1608 offset, i2c_index, i2c_address, count);
1609
309b8c89
BS		 1610 chan = init_i2c_device_find(dev, i2c_index);
1611 if (!chan) {
1612 NV_ERROR(dev, "0x%04X: i2c bus not found\n", offset);
1613 return len;
1614 }
6ee73861
BS		 1615
1616 for (i = 0; i < count; i++) {
1617 data[i] = bios->data[offset + 4 + i];
1618
1619 BIOSLOG(bios, "0x%04X: Data: 0x%02X\n", offset, data[i]);
1620 }
1621
1622 if (bios->execute) {
1623 msg.addr = i2c_address;
1624 msg.flags = 0;
1625 msg.len = count;
1626 msg.buf = data;
309b8c89
BS		 1627 ret = i2c_transfer(&chan->adapter, &msg, 1);
1628 if (ret != 1) {
1629 NV_ERROR(dev, "0x%04X: i2c wr fail: %d\n", offset, ret);
1630 return len;
1631 }
6ee73861
BS		 1632 }
1633
37383650 1634 return len;
6ee73861
BS		 1635}
1636
37383650 1637static int
6ee73861
BS		 1638init_tmds(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1639{
1640 /*
1641 * INIT_TMDS opcode: 0x4F ('O') (non-canon name)
1642 *
1643 * offset (8 bit): opcode
1644 * offset + 1 (8 bit): magic lookup value
1645 * offset + 2 (8 bit): TMDS address
1646 * offset + 3 (8 bit): mask
1647 * offset + 4 (8 bit): data
1648 *
1649 * Read the data reg for TMDS address "TMDS address", AND it with mask
1650 * and OR it with data, then write it back
1651 * "magic lookup value" determines which TMDS base address register is
1652 * used -- see get_tmds_index_reg()
1653 */
1654
309b8c89 1655 struct drm_device *dev = bios->dev;
6ee73861
BS		 1656 uint8_t mlv = bios->data[offset + 1];
1657 uint32_t tmdsaddr = bios->data[offset + 2];
1658 uint8_t mask = bios->data[offset + 3];
1659 uint8_t data = bios->data[offset + 4];
1660 uint32_t reg, value;
1661
1662 if (!iexec->execute)
37383650 1663 return 5;
6ee73861
BS		 1664
1665 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, TMDSAddr: 0x%02X, "
1666 "Mask: 0x%02X, Data: 0x%02X\n",
1667 offset, mlv, tmdsaddr, mask, data);
1668
1669 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1670 if (!reg) {
1671 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1672 return 5;
1673 }
6ee73861
BS		 1674
1675 bios_wr32(bios, reg,
1676 tmdsaddr | NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE);
1677 value = (bios_rd32(bios, reg + 4) & mask) | data;
1678 bios_wr32(bios, reg + 4, value);
1679 bios_wr32(bios, reg, tmdsaddr);
1680
37383650 1681 return 5;
6ee73861
BS		 1682}
1683
37383650 1684static int
6ee73861
BS		 1685init_zm_tmds_group(struct nvbios *bios, uint16_t offset,
1686 struct init_exec *iexec)
1687{
1688 /*
1689 * INIT_ZM_TMDS_GROUP opcode: 0x50 ('P') (non-canon name)
1690 *
1691 * offset (8 bit): opcode
1692 * offset + 1 (8 bit): magic lookup value
1693 * offset + 2 (8 bit): count
1694 * offset + 3 (8 bit): addr 1
1695 * offset + 4 (8 bit): data 1
1696 * ...
1697 *
1698 * For each of "count" TMDS address and data pairs write "data n" to
1699 * "addr n". "magic lookup value" determines which TMDS base address
1700 * register is used -- see get_tmds_index_reg()
1701 */
1702
309b8c89 1703 struct drm_device *dev = bios->dev;
6ee73861
BS		 1704 uint8_t mlv = bios->data[offset + 1];
1705 uint8_t count = bios->data[offset + 2];
37383650 1706 int len = 3 + count * 2;
6ee73861
BS		 1707 uint32_t reg;
1708 int i;
1709
1710 if (!iexec->execute)
37383650 1711 return len;
6ee73861
BS		 1712
1713 BIOSLOG(bios, "0x%04X: MagicLookupValue: 0x%02X, Count: 0x%02X\n",
1714 offset, mlv, count);
1715
1716 reg = get_tmds_index_reg(bios->dev, mlv);
309b8c89
BS		 1717 if (!reg) {
1718 NV_ERROR(dev, "0x%04X: no tmds_index_reg\n", offset);
1719 return len;
1720 }
6ee73861
BS		 1721
1722 for (i = 0; i < count; i++) {
1723 uint8_t tmdsaddr = bios->data[offset + 3 + i * 2];
1724 uint8_t tmdsdata = bios->data[offset + 4 + i * 2];
1725
1726 bios_wr32(bios, reg + 4, tmdsdata);
1727 bios_wr32(bios, reg, tmdsaddr);
1728 }
1729
37383650 1730 return len;
6ee73861
BS		 1731}
1732
37383650 1733static int
6ee73861
BS		 1734init_cr_idx_adr_latch(struct nvbios *bios, uint16_t offset,
1735 struct init_exec *iexec)
1736{
1737 /*
1738 * INIT_CR_INDEX_ADDRESS_LATCHED opcode: 0x51 ('Q')
1739 *
1740 * offset (8 bit): opcode
1741 * offset + 1 (8 bit): CRTC index1
1742 * offset + 2 (8 bit): CRTC index2
1743 * offset + 3 (8 bit): baseaddr
1744 * offset + 4 (8 bit): count
1745 * offset + 5 (8 bit): data 1
1746 * ...
1747 *
1748 * For each of "count" address and data pairs, write "baseaddr + n" to
1749 * "CRTC index1" and "data n" to "CRTC index2"
1750 * Once complete, restore initial value read from "CRTC index1"
1751 */
1752 uint8_t crtcindex1 = bios->data[offset + 1];
1753 uint8_t crtcindex2 = bios->data[offset + 2];
1754 uint8_t baseaddr = bios->data[offset + 3];
1755 uint8_t count = bios->data[offset + 4];
37383650 1756 int len = 5 + count;
6ee73861
BS		 1757 uint8_t oldaddr, data;
1758 int i;
1759
1760 if (!iexec->execute)
37383650 1761 return len;
6ee73861
BS		 1762
1763 BIOSLOG(bios, "0x%04X: Index1: 0x%02X, Index2: 0x%02X, "
1764 "BaseAddr: 0x%02X, Count: 0x%02X\n",
1765 offset, crtcindex1, crtcindex2, baseaddr, count);
1766
1767 oldaddr = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex1);
1768
1769 for (i = 0; i < count; i++) {
1770 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1,
1771 baseaddr + i);
1772 data = bios->data[offset + 5 + i];
1773 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex2, data);
1774 }
1775
1776 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex1, oldaddr);
1777
37383650 1778 return len;
6ee73861
BS		 1779}
1780
37383650 1781static int
6ee73861
BS		 1782init_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1783{
1784 /*
1785 * INIT_CR opcode: 0x52 ('R')
1786 *
1787 * offset (8 bit): opcode
1788 * offset + 1 (8 bit): CRTC index
1789 * offset + 2 (8 bit): mask
1790 * offset + 3 (8 bit): data
1791 *
1792 * Assign the value of at "CRTC index" ANDed with mask and ORed with
1793 * data back to "CRTC index"
1794 */
1795
1796 uint8_t crtcindex = bios->data[offset + 1];
1797 uint8_t mask = bios->data[offset + 2];
1798 uint8_t data = bios->data[offset + 3];
1799 uint8_t value;
1800
1801 if (!iexec->execute)
37383650 1802 return 4;
6ee73861
BS		 1803
1804 BIOSLOG(bios, "0x%04X: Index: 0x%02X, Mask: 0x%02X, Data: 0x%02X\n",
1805 offset, crtcindex, mask, data);
1806
1807 value = bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, crtcindex) & mask;
1808 value |= data;
1809 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, value);
1810
37383650 1811 return 4;
6ee73861
BS		 1812}
1813
37383650 1814static int
6ee73861
BS		 1815init_zm_cr(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1816{
1817 /*
1818 * INIT_ZM_CR opcode: 0x53 ('S')
1819 *
1820 * offset (8 bit): opcode
1821 * offset + 1 (8 bit): CRTC index
1822 * offset + 2 (8 bit): value
1823 *
1824 * Assign "value" to CRTC register with index "CRTC index".
1825 */
1826
1827 uint8_t crtcindex = ROM32(bios->data[offset + 1]);
1828 uint8_t data = bios->data[offset + 2];
1829
1830 if (!iexec->execute)
37383650 1831 return 3;
6ee73861
BS		 1832
1833 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, crtcindex, data);
1834
37383650 1835 return 3;
6ee73861
BS		 1836}
1837
37383650 1838static int
6ee73861
BS		 1839init_zm_cr_group(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1840{
1841 /*
1842 * INIT_ZM_CR_GROUP opcode: 0x54 ('T')
1843 *
1844 * offset (8 bit): opcode
1845 * offset + 1 (8 bit): count
1846 * offset + 2 (8 bit): CRTC index 1
1847 * offset + 3 (8 bit): value 1
1848 * ...
1849 *
1850 * For "count", assign "value n" to CRTC register with index
1851 * "CRTC index n".
1852 */
1853
1854 uint8_t count = bios->data[offset + 1];
37383650 1855 int len = 2 + count * 2;
6ee73861
BS		 1856 int i;
1857
1858 if (!iexec->execute)
37383650 1859 return len;
6ee73861
BS		 1860
1861 for (i = 0; i < count; i++)
1862 init_zm_cr(bios, offset + 2 + 2 * i - 1, iexec);
1863
37383650 1864 return len;
6ee73861
BS		 1865}
1866
37383650 1867static int
6ee73861
BS		 1868init_condition_time(struct nvbios *bios, uint16_t offset,
1869 struct init_exec *iexec)
1870{
1871 /*
1872 * INIT_CONDITION_TIME opcode: 0x56 ('V')
1873 *
1874 * offset (8 bit): opcode
1875 * offset + 1 (8 bit): condition number
1876 * offset + 2 (8 bit): retries / 50
1877 *
1878 * Check condition "condition number" in the condition table.
1879 * Bios code then sleeps for 2ms if the condition is not met, and
1880 * repeats up to "retries" times, but on one C51 this has proved
1881 * insufficient. In mmiotraces the driver sleeps for 20ms, so we do
1882 * this, and bail after "retries" times, or 2s, whichever is less.
1883 * If still not met after retries, clear execution flag for this table.
1884 */
1885
1886 uint8_t cond = bios->data[offset + 1];
1887 uint16_t retries = bios->data[offset + 2] * 50;
1888 unsigned cnt;
1889
1890 if (!iexec->execute)
37383650 1891 return 3;
6ee73861
BS		 1892
1893 if (retries > 100)
1894 retries = 100;
1895
1896 BIOSLOG(bios, "0x%04X: Condition: 0x%02X, Retries: 0x%02X\n",
1897 offset, cond, retries);
1898
1899 if (!bios->execute) /* avoid 2s delays when "faking" execution */
1900 retries = 1;
1901
1902 for (cnt = 0; cnt < retries; cnt++) {
1903 if (bios_condition_met(bios, offset, cond)) {
1904 BIOSLOG(bios, "0x%04X: Condition met, continuing\n",
1905 offset);
1906 break;
1907 } else {
1908 BIOSLOG(bios, "0x%04X: "
1909 "Condition not met, sleeping for 20ms\n",
1910 offset);
c7ca4d1b 1911 mdelay(20);
6ee73861
BS		 1912 }
1913 }
1914
1915 if (!bios_condition_met(bios, offset, cond)) {
1916 NV_WARN(bios->dev,
1917 "0x%04X: Condition still not met after %dms, "
1918 "skipping following opcodes\n", offset, 20 * retries);
1919 iexec->execute = false;
1920 }
1921
37383650 1922 return 3;
6ee73861
BS		 1923}
1924
e3a1924f
MK		 1925static int
1926init_ltime(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1927{
1928 /*
1929 * INIT_LTIME opcode: 0x57 ('V')
1930 *
1931 * offset (8 bit): opcode
1932 * offset + 1 (16 bit): time
1933 *
e8a8b252 1934 * Sleep for "time" milliseconds.
e3a1924f
MK		 1935 */
1936
1937 unsigned time = ROM16(bios->data[offset + 1]);
1938
1939 if (!iexec->execute)
1940 return 3;
1941
e8a8b252 1942 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X milliseconds\n",
e3a1924f
MK		 1943 offset, time);
1944
c7ca4d1b 1945 mdelay(time);
e3a1924f
MK		 1946
1947 return 3;
1948}
1949
37383650 1950static int
6ee73861
BS		 1951init_zm_reg_sequence(struct nvbios *bios, uint16_t offset,
1952 struct init_exec *iexec)
1953{
1954 /*
1955 * INIT_ZM_REG_SEQUENCE opcode: 0x58 ('X')
1956 *
1957 * offset (8 bit): opcode
1958 * offset + 1 (32 bit): base register
1959 * offset + 5 (8 bit): count
1960 * offset + 6 (32 bit): value 1
1961 * ...
1962 *
1963 * Starting at offset + 6 there are "count" 32 bit values.
1964 * For "count" iterations set "base register" + 4 * current_iteration
1965 * to "value current_iteration"
1966 */
1967
1968 uint32_t basereg = ROM32(bios->data[offset + 1]);
1969 uint32_t count = bios->data[offset + 5];
37383650 1970 int len = 6 + count * 4;
6ee73861
BS		 1971 int i;
1972
1973 if (!iexec->execute)
37383650 1974 return len;
6ee73861
BS		 1975
1976 BIOSLOG(bios, "0x%04X: BaseReg: 0x%08X, Count: 0x%02X\n",
1977 offset, basereg, count);
1978
1979 for (i = 0; i < count; i++) {
1980 uint32_t reg = basereg + i * 4;
1981 uint32_t data = ROM32(bios->data[offset + 6 + i * 4]);
1982
1983 bios_wr32(bios, reg, data);
1984 }
1985
37383650 1986 return len;
6ee73861
BS		 1987}
1988
37383650 1989static int
6ee73861
BS		 1990init_sub_direct(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
1991{
1992 /*
1993 * INIT_SUB_DIRECT opcode: 0x5B ('[')
1994 *
1995 * offset (8 bit): opcode
1996 * offset + 1 (16 bit): subroutine offset (in bios)
1997 *
1998 * Calls a subroutine that will execute commands until INIT_DONE
1999 * is found.
2000 */
2001
2002 uint16_t sub_offset = ROM16(bios->data[offset + 1]);
2003
2004 if (!iexec->execute)
37383650 2005 return 3;
6ee73861
BS		 2006
2007 BIOSLOG(bios, "0x%04X: Executing subroutine at 0x%04X\n",
2008 offset, sub_offset);
2009
2010 parse_init_table(bios, sub_offset, iexec);
2011
2012 BIOSLOG(bios, "0x%04X: End of 0x%04X subroutine\n", offset, sub_offset);
2013
37383650 2014 return 3;
6ee73861
BS		 2015}
2016
ec64a408
BS		 2017static int
2018init_jump(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2019{
2020 /*
2021 * INIT_JUMP opcode: 0x5C ('\')
2022 *
2023 * offset (8 bit): opcode
2024 * offset + 1 (16 bit): offset (in bios)
2025 *
2026 * Continue execution of init table from 'offset'
2027 */
2028
2029 uint16_t jmp_offset = ROM16(bios->data[offset + 1]);
2030
2031 if (!iexec->execute)
2032 return 3;
2033
2034 BIOSLOG(bios, "0x%04X: Jump to 0x%04X\n", offset, jmp_offset);
2035 return jmp_offset - offset;
2036}
2037
b715d640
MK		 2038static int
2039init_i2c_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2040{
2041 /*
2042 * INIT_I2C_IF opcode: 0x5E ('^')
2043 *
2044 * offset (8 bit): opcode
2045 * offset + 1 (8 bit): DCB I2C table entry index
2046 * offset + 2 (8 bit): I2C slave address
2047 * offset + 3 (8 bit): I2C register
2048 * offset + 4 (8 bit): mask
2049 * offset + 5 (8 bit): data
2050 *
2051 * Read the register given by "I2C register" on the device addressed
2052 * by "I2C slave address" on the I2C bus given by "DCB I2C table
2053 * entry index". Compare the result AND "mask" to "data".
2054 * If they're not equal, skip subsequent opcodes until condition is
2055 * inverted (INIT_NOT), or we hit INIT_RESUME
2056 */
2057
2058 uint8_t i2c_index = bios->data[offset + 1];
2059 uint8_t i2c_address = bios->data[offset + 2] >> 1;
2060 uint8_t reg = bios->data[offset + 3];
2061 uint8_t mask = bios->data[offset + 4];
2062 uint8_t data = bios->data[offset + 5];
2063 struct nouveau_i2c_chan *chan;
2064 union i2c_smbus_data val;
2065 int ret;
2066
2067 /* no execute check by design */
2068
2069 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
2070 offset, i2c_index, i2c_address);
2071
2072 chan = init_i2c_device_find(bios->dev, i2c_index);
2073 if (!chan)
2074 return -ENODEV;
2075
2076 ret = i2c_smbus_xfer(&chan->adapter, i2c_address, 0,
2077 I2C_SMBUS_READ, reg,
2078 I2C_SMBUS_BYTE_DATA, &val);
2079 if (ret < 0) {
2080 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: [no device], "
2081 "Mask: 0x%02X, Data: 0x%02X\n",
2082 offset, reg, mask, data);
2083 iexec->execute = 0;
2084 return 6;
2085 }
2086
2087 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X, Value: 0x%02X, "
2088 "Mask: 0x%02X, Data: 0x%02X\n",
2089 offset, reg, val.byte, mask, data);
2090
2091 iexec->execute = ((val.byte & mask) == data);
2092
2093 return 6;
2094}
2095
37383650 2096static int
6ee73861
BS		 2097init_copy_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2098{
2099 /*
2100 * INIT_COPY_NV_REG opcode: 0x5F ('_')
2101 *
2102 * offset (8 bit): opcode
2103 * offset + 1 (32 bit): src reg
2104 * offset + 5 (8 bit): shift
2105 * offset + 6 (32 bit): src mask
2106 * offset + 10 (32 bit): xor
2107 * offset + 14 (32 bit): dst reg
2108 * offset + 18 (32 bit): dst mask
2109 *
2110 * Shift REGVAL("src reg") right by (signed) "shift", AND result with
2111 * "src mask", then XOR with "xor". Write this OR'd with
2112 * (REGVAL("dst reg") AND'd with "dst mask") to "dst reg"
2113 */
2114
2115 uint32_t srcreg = *((uint32_t *)(&bios->data[offset + 1]));
2116 uint8_t shift = bios->data[offset + 5];
2117 uint32_t srcmask = *((uint32_t *)(&bios->data[offset + 6]));
2118 uint32_t xor = *((uint32_t *)(&bios->data[offset + 10]));
2119 uint32_t dstreg = *((uint32_t *)(&bios->data[offset + 14]));
2120 uint32_t dstmask = *((uint32_t *)(&bios->data[offset + 18]));
2121 uint32_t srcvalue, dstvalue;
2122
2123 if (!iexec->execute)
37383650 2124 return 22;
6ee73861
BS		 2125
2126 BIOSLOG(bios, "0x%04X: SrcReg: 0x%08X, Shift: 0x%02X, SrcMask: 0x%08X, "
2127 "Xor: 0x%08X, DstReg: 0x%08X, DstMask: 0x%08X\n",
2128 offset, srcreg, shift, srcmask, xor, dstreg, dstmask);
2129
2130 srcvalue = bios_rd32(bios, srcreg);
2131
2132 if (shift < 0x80)
2133 srcvalue >>= shift;
2134 else
2135 srcvalue <<= (0x100 - shift);
2136
2137 srcvalue = (srcvalue & srcmask) ^ xor;
2138
2139 dstvalue = bios_rd32(bios, dstreg) & dstmask;
2140
2141 bios_wr32(bios, dstreg, dstvalue | srcvalue);
2142
37383650 2143 return 22;
6ee73861
BS		 2144}
2145
37383650 2146static int
6ee73861
BS		 2147init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2148{
2149 /*
2150 * INIT_ZM_INDEX_IO opcode: 0x62 ('b')
2151 *
2152 * offset (8 bit): opcode
2153 * offset + 1 (16 bit): CRTC port
2154 * offset + 3 (8 bit): CRTC index
2155 * offset + 4 (8 bit): data
2156 *
2157 * Write "data" to index "CRTC index" of "CRTC port"
2158 */
2159 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2160 uint8_t crtcindex = bios->data[offset + 3];
2161 uint8_t data = bios->data[offset + 4];
2162
2163 if (!iexec->execute)
37383650 2164 return 5;
6ee73861
BS		 2165
2166 bios_idxprt_wr(bios, crtcport, crtcindex, data);
2167
37383650 2168 return 5;
6ee73861
BS		 2169}
2170
67eda20e
FJ		 2171static inline void
2172bios_md32(struct nvbios *bios, uint32_t reg,
2173 uint32_t mask, uint32_t val)
2174{
2175 bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
2176}
2177
2178static uint32_t
2179peek_fb(struct drm_device *dev, struct io_mapping *fb,
2180 uint32_t off)
2181{
2182 uint32_t val = 0;
2183
2184 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2185 uint8_t __iomem *p =
3e4d3af5 2186 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2187
0bf9b0e0 2188 val = ioread32(p + (off & ~PAGE_MASK));
67eda20e 2189
3e4d3af5 2190 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2191 }
2192
2193 return val;
2194}
2195
2196static void
2197poke_fb(struct drm_device *dev, struct io_mapping *fb,
2198 uint32_t off, uint32_t val)
2199{
2200 if (off < pci_resource_len(dev->pdev, 1)) {
625db6b7 2201 uint8_t __iomem *p =
3e4d3af5 2202 io_mapping_map_atomic_wc(fb, off & PAGE_MASK);
67eda20e 2203
0bf9b0e0 2204 iowrite32(val, p + (off & ~PAGE_MASK));
67eda20e
FJ		 2205 wmb();
2206
3e4d3af5 2207 io_mapping_unmap_atomic(p);
67eda20e
FJ		 2208 }
2209}
2210
2211static inline bool
2212read_back_fb(struct drm_device *dev, struct io_mapping *fb,
2213 uint32_t off, uint32_t val)
2214{
2215 poke_fb(dev, fb, off, val);
2216 return val == peek_fb(dev, fb, off);
2217}
2218
2219static int
2220nv04_init_compute_mem(struct nvbios *bios)
2221{
2222 struct drm_device *dev = bios->dev;
2223 uint32_t patt = 0xdeadbeef;
2224 struct io_mapping *fb;
2225 int i;
2226
2227 /* Map the framebuffer aperture */
2228 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2229 pci_resource_len(dev->pdev, 1));
2230 if (!fb)
2231 return -ENOMEM;
2232
2233 /* Sequencer and refresh off */
2234 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2235 bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
2236
2237 bios_md32(bios, NV04_PFB_BOOT_0, ~0,
2238 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
2239 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2240 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
2241
2242 for (i = 0; i < 4; i++)
2243 poke_fb(dev, fb, 4 * i, patt);
2244
2245 poke_fb(dev, fb, 0x400000, patt + 1);
2246
2247 if (peek_fb(dev, fb, 0) == patt + 1) {
2248 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2249 NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
2250 bios_md32(bios, NV04_PFB_DEBUG_0,
2251 NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2252
2253 for (i = 0; i < 4; i++)
2254 poke_fb(dev, fb, 4 * i, patt);
2255
2256 if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
2257 bios_md32(bios, NV04_PFB_BOOT_0,
2258 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2259 NV04_PFB_BOOT_0_RAM_AMOUNT,
2260 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2261
2262 } else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
2263 (patt & 0xffff0000)) {
2264 bios_md32(bios, NV04_PFB_BOOT_0,
2265 NV04_PFB_BOOT_0_RAM_WIDTH_128 |
2266 NV04_PFB_BOOT_0_RAM_AMOUNT,
2267 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2268
0746b5da 2269 } else if (peek_fb(dev, fb, 0) != patt) {
67eda20e
FJ		 2270 if (read_back_fb(dev, fb, 0x800000, patt))
2271 bios_md32(bios, NV04_PFB_BOOT_0,
2272 NV04_PFB_BOOT_0_RAM_AMOUNT,
2273 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2274 else
2275 bios_md32(bios, NV04_PFB_BOOT_0,
2276 NV04_PFB_BOOT_0_RAM_AMOUNT,
2277 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2278
2279 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
2280 NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
2281
2282 } else if (!read_back_fb(dev, fb, 0x800000, patt)) {
2283 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2284 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2285
2286 }
2287
2288 /* Refresh on, sequencer on */
2289 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2290 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2291
2292 io_mapping_free(fb);
2293 return 0;
2294}
2295
2296static const uint8_t *
2297nv05_memory_config(struct nvbios *bios)
2298{
2299 /* Defaults for BIOSes lacking a memory config table */
2300 static const uint8_t default_config_tab[][2] = {
2301 { 0x24, 0x00 },
2302 { 0x28, 0x00 },
2303 { 0x24, 0x01 },
2304 { 0x1f, 0x00 },
2305 { 0x0f, 0x00 },
2306 { 0x17, 0x00 },
2307 { 0x06, 0x00 },
2308 { 0x00, 0x00 }
2309 };
2310 int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
2311 NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
2312
2313 if (bios->legacy.mem_init_tbl_ptr)
2314 return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
2315 else
2316 return default_config_tab[i];
2317}
2318
2319static int
2320nv05_init_compute_mem(struct nvbios *bios)
2321{
2322 struct drm_device *dev = bios->dev;
2323 const uint8_t *ramcfg = nv05_memory_config(bios);
2324 uint32_t patt = 0xdeadbeef;
2325 struct io_mapping *fb;
2326 int i, v;
2327
2328 /* Map the framebuffer aperture */
2329 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2330 pci_resource_len(dev->pdev, 1));
2331 if (!fb)
2332 return -ENOMEM;
2333
2334 /* Sequencer off */
2335 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
2336
2337 if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
2338 goto out;
2339
2340 bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
2341
2342 /* If present load the hardcoded scrambling table */
2343 if (bios->legacy.mem_init_tbl_ptr) {
2344 uint32_t *scramble_tab = (uint32_t *)&bios->data[
2345 bios->legacy.mem_init_tbl_ptr + 0x10];
2346
2347 for (i = 0; i < 8; i++)
2348 bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
2349 ROM32(scramble_tab[i]));
2350 }
2351
2352 /* Set memory type/width/length defaults depending on the straps */
2353 bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
2354
2355 if (ramcfg[1] & 0x80)
2356 bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
2357
2358 bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
2359 bios_md32(bios, NV04_PFB_CFG1, 0, 1);
2360
2361 /* Probe memory bus width */
2362 for (i = 0; i < 4; i++)
2363 poke_fb(dev, fb, 4 * i, patt);
2364
2365 if (peek_fb(dev, fb, 0xc) != patt)
2366 bios_md32(bios, NV04_PFB_BOOT_0,
2367 NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
2368
2369 /* Probe memory length */
2370 v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
2371
2372 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
2373 (!read_back_fb(dev, fb, 0x1000000, ++patt) ||
2374 !read_back_fb(dev, fb, 0, ++patt)))
2375 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2376 NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
2377
2378 if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
2379 !read_back_fb(dev, fb, 0x800000, ++patt))
2380 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2381 NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
2382
2383 if (!read_back_fb(dev, fb, 0x400000, ++patt))
2384 bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
2385 NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
2386
2387out:
2388 /* Sequencer on */
2389 NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
2390
2391 io_mapping_free(fb);
2392 return 0;
2393}
2394
2395static int
2396nv10_init_compute_mem(struct nvbios *bios)
2397{
2398 struct drm_device *dev = bios->dev;
2399 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2400 const int mem_width[] = { 0x10, 0x00, 0x20 };
2401 const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
2402 uint32_t patt = 0xdeadbeef;
2403 struct io_mapping *fb;
2404 int i, j, k;
2405
2406 /* Map the framebuffer aperture */
2407 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2408 pci_resource_len(dev->pdev, 1));
2409 if (!fb)
2410 return -ENOMEM;
2411
2412 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2413
2414 /* Probe memory bus width */
2415 for (i = 0; i < mem_width_count; i++) {
2416 bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
2417
2418 for (j = 0; j < 4; j++) {
2419 for (k = 0; k < 4; k++)
2420 poke_fb(dev, fb, 0x1c, 0);
2421
2422 poke_fb(dev, fb, 0x1c, patt);
2423 poke_fb(dev, fb, 0x3c, 0);
2424
2425 if (peek_fb(dev, fb, 0x1c) == patt)
2426 goto mem_width_found;
2427 }
2428 }
2429
2430mem_width_found:
2431 patt <<= 1;
2432
2433 /* Probe amount of installed memory */
2434 for (i = 0; i < 4; i++) {
2435 int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
2436
2437 poke_fb(dev, fb, off, patt);
2438 poke_fb(dev, fb, 0, 0);
2439
2440 peek_fb(dev, fb, 0);
2441 peek_fb(dev, fb, 0);
2442 peek_fb(dev, fb, 0);
2443 peek_fb(dev, fb, 0);
2444
2445 if (peek_fb(dev, fb, off) == patt)
2446 goto amount_found;
2447 }
2448
2449 /* IC missing - disable the upper half memory space. */
2450 bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
2451
2452amount_found:
2453 io_mapping_free(fb);
2454 return 0;
2455}
2456
2457static int
2458nv20_init_compute_mem(struct nvbios *bios)
2459{
2460 struct drm_device *dev = bios->dev;
2461 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2462 uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
2463 uint32_t amount, off;
2464 struct io_mapping *fb;
2465
2466 /* Map the framebuffer aperture */
2467 fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
2468 pci_resource_len(dev->pdev, 1));
2469 if (!fb)
2470 return -ENOMEM;
2471
2472 bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
2473
2474 /* Allow full addressing */
2475 bios_md32(bios, NV04_PFB_CFG0, 0, mask);
2476
2477 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2478 for (off = amount; off > 0x2000000; off -= 0x2000000)
2479 poke_fb(dev, fb, off - 4, off);
2480
2481 amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
2482 if (amount != peek_fb(dev, fb, amount - 4))
2483 /* IC missing - disable the upper half memory space. */
2484 bios_md32(bios, NV04_PFB_CFG0, mask, 0);
2485
2486 io_mapping_free(fb);
2487 return 0;
2488}
2489
37383650 2490static int
6ee73861
BS		 2491init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2492{
2493 /*
2494 * INIT_COMPUTE_MEM opcode: 0x63 ('c')
2495 *
2496 * offset (8 bit): opcode
2497 *
67eda20e
FJ		 2498 * This opcode is meant to set the PFB memory config registers
2499 * appropriately so that we can correctly calculate how much VRAM it
2500 * has (on nv10 and better chipsets the amount of installed VRAM is
2501 * subsequently reported in NV_PFB_CSTATUS (0x10020C)).
6ee73861 2502 *
67eda20e
FJ		 2503 * The implementation of this opcode in general consists of several
2504 * parts:
6ee73861 2505 *
67eda20e
FJ		 2506 * 1) Determination of memory type and density. Only necessary for
2507 * really old chipsets, the memory type reported by the strap bits
2508 * (0x101000) is assumed to be accurate on nv05 and newer.
6ee73861 2509 *
67eda20e
FJ		 2510 * 2) Determination of the memory bus width. Usually done by a cunning
2511 * combination of writes to offsets 0x1c and 0x3c in the fb, and
2512 * seeing whether the written values are read back correctly.
6ee73861 2513 *
67eda20e
FJ		 2514 * Only necessary on nv0x-nv1x and nv34, on the other cards we can
2515 * trust the straps.
6ee73861 2516 *
67eda20e
FJ		 2517 * 3) Determination of how many of the card's RAM pads have ICs
2518 * attached, usually done by a cunning combination of writes to an
2519 * offset slightly less than the maximum memory reported by
2520 * NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
6ee73861 2521 *
67eda20e
FJ		 2522 * This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
2523 * logs of the VBIOS and kmmio traces of the binary driver POSTing the
2524 * card show nothing being done for this opcode. Why is it still listed
2525 * in the table?!
6ee73861
BS		 2526 */
2527
2528 /* no iexec->execute check by design */
2529
6ee73861 2530 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
67eda20e 2531 int ret;
6ee73861 2532
67eda20e
FJ		 2533 if (dev_priv->chipset >= 0x40 ||
2534 dev_priv->chipset == 0x1a ||
2535 dev_priv->chipset == 0x1f)
2536 ret = 0;
2537 else if (dev_priv->chipset >= 0x20 &&
2538 dev_priv->chipset != 0x34)
2539 ret = nv20_init_compute_mem(bios);
2540 else if (dev_priv->chipset >= 0x10)
2541 ret = nv10_init_compute_mem(bios);
2542 else if (dev_priv->chipset >= 0x5)
2543 ret = nv05_init_compute_mem(bios);
2544 else
2545 ret = nv04_init_compute_mem(bios);
6ee73861 2546
67eda20e
FJ		 2547 if (ret)
2548 return ret;
6ee73861 2549
37383650 2550 return 1;
6ee73861
BS		 2551}
2552
37383650 2553static int
6ee73861
BS		 2554init_reset(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2555{
2556 /*
2557 * INIT_RESET opcode: 0x65 ('e')
2558 *
2559 * offset (8 bit): opcode
2560 * offset + 1 (32 bit): register
2561 * offset + 5 (32 bit): value1
2562 * offset + 9 (32 bit): value2
2563 *
2564 * Assign "value1" to "register", then assign "value2" to "register"
2565 */
2566
2567 uint32_t reg = ROM32(bios->data[offset + 1]);
2568 uint32_t value1 = ROM32(bios->data[offset + 5]);
2569 uint32_t value2 = ROM32(bios->data[offset + 9]);
2570 uint32_t pci_nv_19, pci_nv_20;
2571
2572 /* no iexec->execute check by design */
2573
2574 pci_nv_19 = bios_rd32(bios, NV_PBUS_PCI_NV_19);
190a4378
FJ		 2575 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19 & ~0xf00);
2576
6ee73861
BS		 2577 bios_wr32(bios, reg, value1);
2578
2579 udelay(10);
2580
2581 bios_wr32(bios, reg, value2);
2582 bios_wr32(bios, NV_PBUS_PCI_NV_19, pci_nv_19);
2583
2584 pci_nv_20 = bios_rd32(bios, NV_PBUS_PCI_NV_20);
2585 pci_nv_20 &= ~NV_PBUS_PCI_NV_20_ROM_SHADOW_ENABLED; /* 0xfffffffe */
2586 bios_wr32(bios, NV_PBUS_PCI_NV_20, pci_nv_20);
2587
37383650 2588 return 13;
6ee73861
BS		 2589}
2590
37383650 2591static int
6ee73861
BS		 2592init_configure_mem(struct nvbios *bios, uint16_t offset,
2593 struct init_exec *iexec)
2594{
2595 /*
2596 * INIT_CONFIGURE_MEM opcode: 0x66 ('f')
2597 *
2598 * offset (8 bit): opcode
2599 *
2600 * Equivalent to INIT_DONE on bios version 3 or greater.
2601 * For early bios versions, sets up the memory registers, using values
2602 * taken from the memory init table
2603 */
2604
2605 /* no iexec->execute check by design */
2606
2607 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2608 uint16_t seqtbloffs = bios->legacy.sdr_seq_tbl_ptr, meminitdata = meminitoffs + 6;
2609 uint32_t reg, data;
2610
2611 if (bios->major_version > 2)
ae55321c 2612 return 0;
6ee73861
BS		 2613
2614 bios_idxprt_wr(bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX, bios_idxprt_rd(
2615 bios, NV_VIO_SRX, NV_VIO_SR_CLOCK_INDEX) | 0x20);
2616
2617 if (bios->data[meminitoffs] & 1)
2618 seqtbloffs = bios->legacy.ddr_seq_tbl_ptr;
2619
2620 for (reg = ROM32(bios->data[seqtbloffs]);
2621 reg != 0xffffffff;
2622 reg = ROM32(bios->data[seqtbloffs += 4])) {
2623
2624 switch (reg) {
3c7066bc
FJ		 2625 case NV04_PFB_PRE:
2626 data = NV04_PFB_PRE_CMD_PRECHARGE;
6ee73861 2627 break;
3c7066bc
FJ		 2628 case NV04_PFB_PAD:
2629 data = NV04_PFB_PAD_CKE_NORMAL;
6ee73861 2630 break;
3c7066bc
FJ		 2631 case NV04_PFB_REF:
2632 data = NV04_PFB_REF_CMD_REFRESH;
6ee73861
BS		 2633 break;
2634 default:
2635 data = ROM32(bios->data[meminitdata]);
2636 meminitdata += 4;
2637 if (data == 0xffffffff)
2638 continue;
2639 }
2640
2641 bios_wr32(bios, reg, data);
2642 }
2643
37383650 2644 return 1;
6ee73861
BS		 2645}
2646
37383650 2647static int
6ee73861
BS		 2648init_configure_clk(struct nvbios *bios, uint16_t offset,
2649 struct init_exec *iexec)
2650{
2651 /*
2652 * INIT_CONFIGURE_CLK opcode: 0x67 ('g')
2653 *
2654 * offset (8 bit): opcode
2655 *
2656 * Equivalent to INIT_DONE on bios version 3 or greater.
2657 * For early bios versions, sets up the NVClk and MClk PLLs, using
2658 * values taken from the memory init table
2659 */
2660
2661 /* no iexec->execute check by design */
2662
2663 uint16_t meminitoffs = bios->legacy.mem_init_tbl_ptr + MEM_INIT_SIZE * (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_SCRATCH4__INDEX) >> 4);
2664 int clock;
2665
2666 if (bios->major_version > 2)
ae55321c 2667 return 0;
6ee73861
BS		 2668
2669 clock = ROM16(bios->data[meminitoffs + 4]) * 10;
2670 setPLL(bios, NV_PRAMDAC_NVPLL_COEFF, clock);
2671
2672 clock = ROM16(bios->data[meminitoffs + 2]) * 10;
2673 if (bios->data[meminitoffs] & 1) /* DDR */
2674 clock *= 2;
2675 setPLL(bios, NV_PRAMDAC_MPLL_COEFF, clock);
2676
37383650 2677 return 1;
6ee73861
BS		 2678}
2679
37383650 2680static int
6ee73861
BS		 2681init_configure_preinit(struct nvbios *bios, uint16_t offset,
2682 struct init_exec *iexec)
2683{
2684 /*
2685 * INIT_CONFIGURE_PREINIT opcode: 0x68 ('h')
2686 *
2687 * offset (8 bit): opcode
2688 *
2689 * Equivalent to INIT_DONE on bios version 3 or greater.
2690 * For early bios versions, does early init, loading ram and crystal
2691 * configuration from straps into CR3C
2692 */
2693
2694 /* no iexec->execute check by design */
2695
2696 uint32_t straps = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
3c9b2534 2697 uint8_t cr3c = ((straps << 2) & 0xf0) | (straps & 0x40) >> 6;
6ee73861
BS		 2698
2699 if (bios->major_version > 2)
ae55321c 2700 return 0;
6ee73861
BS		 2701
2702 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR,
2703 NV_CIO_CRE_SCRATCH4__INDEX, cr3c);
2704
37383650 2705 return 1;
6ee73861
BS		 2706}
2707
37383650 2708static int
6ee73861
BS		 2709init_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2710{
2711 /*
2712 * INIT_IO opcode: 0x69 ('i')
2713 *
2714 * offset (8 bit): opcode
2715 * offset + 1 (16 bit): CRTC port
2716 * offset + 3 (8 bit): mask
2717 * offset + 4 (8 bit): data
2718 *
2719 * Assign ((IOVAL("crtc port") & "mask") | "data") to "crtc port"
2720 */
2721
2722 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
2723 uint16_t crtcport = ROM16(bios->data[offset + 1]);
2724 uint8_t mask = bios->data[offset + 3];
2725 uint8_t data = bios->data[offset + 4];
2726
2727 if (!iexec->execute)
37383650 2728 return 5;
6ee73861
BS		 2729
2730 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Mask: 0x%02X, Data: 0x%02X\n",
2731 offset, crtcport, mask, data);
2732
2733 /*
2734 * I have no idea what this does, but NVIDIA do this magic sequence
2735 * in the places where this INIT_IO happens..
2736 */
2737 if (dev_priv->card_type >= NV_50 && crtcport == 0x3c3 && data == 1) {
2738 int i;
2739
2740 bios_wr32(bios, 0x614100, (bios_rd32(
2741 bios, 0x614100) & 0x0fffffff) | 0x00800000);
2742
2743 bios_wr32(bios, 0x00e18c, bios_rd32(
2744 bios, 0x00e18c) | 0x00020000);
2745
2746 bios_wr32(bios, 0x614900, (bios_rd32(
2747 bios, 0x614900) & 0x0fffffff) | 0x00800000);
2748
2749 bios_wr32(bios, 0x000200, bios_rd32(
2750 bios, 0x000200) & ~0x40000000);
2751
2752 mdelay(10);
2753
2754 bios_wr32(bios, 0x00e18c, bios_rd32(
2755 bios, 0x00e18c) & ~0x00020000);
2756
2757 bios_wr32(bios, 0x000200, bios_rd32(
2758 bios, 0x000200) | 0x40000000);
2759
2760 bios_wr32(bios, 0x614100, 0x00800018);
2761 bios_wr32(bios, 0x614900, 0x00800018);
2762
2763 mdelay(10);
2764
2765 bios_wr32(bios, 0x614100, 0x10000018);
2766 bios_wr32(bios, 0x614900, 0x10000018);
2767
2768 for (i = 0; i < 3; i++)
2769 bios_wr32(bios, 0x614280 + (i*0x800), bios_rd32(
2770 bios, 0x614280 + (i*0x800)) & 0xf0f0f0f0);
2771
2772 for (i = 0; i < 2; i++)
2773 bios_wr32(bios, 0x614300 + (i*0x800), bios_rd32(
2774 bios, 0x614300 + (i*0x800)) & 0xfffff0f0);
2775
2776 for (i = 0; i < 3; i++)
2777 bios_wr32(bios, 0x614380 + (i*0x800), bios_rd32(
2778 bios, 0x614380 + (i*0x800)) & 0xfffff0f0);
2779
2780 for (i = 0; i < 2; i++)
2781 bios_wr32(bios, 0x614200 + (i*0x800), bios_rd32(
2782 bios, 0x614200 + (i*0x800)) & 0xfffffff0);
2783
2784 for (i = 0; i < 2; i++)
2785 bios_wr32(bios, 0x614108 + (i*0x800), bios_rd32(
2786 bios, 0x614108 + (i*0x800)) & 0x0fffffff);
37383650 2787 return 5;
6ee73861
BS		 2788 }
2789
2790 bios_port_wr(bios, crtcport, (bios_port_rd(bios, crtcport) & mask) |
2791 data);
37383650 2792 return 5;
6ee73861
BS		 2793}
2794
37383650 2795static int
6ee73861
BS		 2796init_sub(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2797{
2798 /*
2799 * INIT_SUB opcode: 0x6B ('k')
2800 *
2801 * offset (8 bit): opcode
2802 * offset + 1 (8 bit): script number
2803 *
2804 * Execute script number "script number", as a subroutine
2805 */
2806
2807 uint8_t sub = bios->data[offset + 1];
2808
2809 if (!iexec->execute)
37383650 2810 return 2;
6ee73861
BS		 2811
2812 BIOSLOG(bios, "0x%04X: Calling script %d\n", offset, sub);
2813
2814 parse_init_table(bios,
2815 ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]),
2816 iexec);
2817
2818 BIOSLOG(bios, "0x%04X: End of script %d\n", offset, sub);
2819
37383650 2820 return 2;
6ee73861
BS		 2821}
2822
37383650 2823static int
6ee73861
BS		 2824init_ram_condition(struct nvbios *bios, uint16_t offset,
2825 struct init_exec *iexec)
2826{
2827 /*
2828 * INIT_RAM_CONDITION opcode: 0x6D ('m')
2829 *
2830 * offset (8 bit): opcode
2831 * offset + 1 (8 bit): mask
2832 * offset + 2 (8 bit): cmpval
2833 *
3c7066bc 2834 * Test if (NV04_PFB_BOOT_0 & "mask") equals "cmpval".
6ee73861
BS		 2835 * If condition not met skip subsequent opcodes until condition is
2836 * inverted (INIT_NOT), or we hit INIT_RESUME
2837 */
2838
2839 uint8_t mask = bios->data[offset + 1];
2840 uint8_t cmpval = bios->data[offset + 2];
2841 uint8_t data;
2842
2843 if (!iexec->execute)
37383650 2844 return 3;
6ee73861 2845
3c7066bc 2846 data = bios_rd32(bios, NV04_PFB_BOOT_0) & mask;
6ee73861
BS		 2847
2848 BIOSLOG(bios, "0x%04X: Checking if 0x%08X equals 0x%08X\n",
2849 offset, data, cmpval);
2850
2851 if (data == cmpval)
2852 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
2853 else {
2854 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
2855 iexec->execute = false;
2856 }
2857
37383650 2858 return 3;
6ee73861
BS		 2859}
2860
37383650 2861static int
6ee73861
BS		 2862init_nv_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2863{
2864 /*
2865 * INIT_NV_REG opcode: 0x6E ('n')
2866 *
2867 * offset (8 bit): opcode
2868 * offset + 1 (32 bit): register
2869 * offset + 5 (32 bit): mask
2870 * offset + 9 (32 bit): data
2871 *
2872 * Assign ((REGVAL("register") & "mask") | "data") to "register"
2873 */
2874
2875 uint32_t reg = ROM32(bios->data[offset + 1]);
2876 uint32_t mask = ROM32(bios->data[offset + 5]);
2877 uint32_t data = ROM32(bios->data[offset + 9]);
2878
2879 if (!iexec->execute)
37383650 2880 return 13;
6ee73861
BS		 2881
2882 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Mask: 0x%08X, Data: 0x%08X\n",
2883 offset, reg, mask, data);
2884
2885 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | data);
2886
37383650 2887 return 13;
6ee73861
BS		 2888}
2889
37383650 2890static int
6ee73861
BS		 2891init_macro(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2892{
2893 /*
2894 * INIT_MACRO opcode: 0x6F ('o')
2895 *
2896 * offset (8 bit): opcode
2897 * offset + 1 (8 bit): macro number
2898 *
2899 * Look up macro index "macro number" in the macro index table.
2900 * The macro index table entry has 1 byte for the index in the macro
2901 * table, and 1 byte for the number of times to repeat the macro.
2902 * The macro table entry has 4 bytes for the register address and
2903 * 4 bytes for the value to write to that register
2904 */
2905
2906 uint8_t macro_index_tbl_idx = bios->data[offset + 1];
2907 uint16_t tmp = bios->macro_index_tbl_ptr + (macro_index_tbl_idx * MACRO_INDEX_SIZE);
2908 uint8_t macro_tbl_idx = bios->data[tmp];
2909 uint8_t count = bios->data[tmp + 1];
2910 uint32_t reg, data;
2911 int i;
2912
2913 if (!iexec->execute)
37383650 2914 return 2;
6ee73861
BS		 2915
2916 BIOSLOG(bios, "0x%04X: Macro: 0x%02X, MacroTableIndex: 0x%02X, "
2917 "Count: 0x%02X\n",
2918 offset, macro_index_tbl_idx, macro_tbl_idx, count);
2919
2920 for (i = 0; i < count; i++) {
2921 uint16_t macroentryptr = bios->macro_tbl_ptr + (macro_tbl_idx + i) * MACRO_SIZE;
2922
2923 reg = ROM32(bios->data[macroentryptr]);
2924 data = ROM32(bios->data[macroentryptr + 4]);
2925
2926 bios_wr32(bios, reg, data);
2927 }
2928
37383650 2929 return 2;
6ee73861
BS		 2930}
2931
37383650 2932static int
6ee73861
BS		 2933init_done(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2934{
2935 /*
2936 * INIT_DONE opcode: 0x71 ('q')
2937 *
2938 * offset (8 bit): opcode
2939 *
2940 * End the current script
2941 */
2942
2943 /* mild retval abuse to stop parsing this table */
37383650 2944 return 0;
6ee73861
BS		 2945}
2946
37383650 2947static int
6ee73861
BS		 2948init_resume(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2949{
2950 /*
2951 * INIT_RESUME opcode: 0x72 ('r')
2952 *
2953 * offset (8 bit): opcode
2954 *
2955 * End the current execute / no-execute condition
2956 */
2957
2958 if (iexec->execute)
37383650 2959 return 1;
6ee73861
BS		 2960
2961 iexec->execute = true;
2962 BIOSLOG(bios, "0x%04X: ---- Executing following commands ----\n", offset);
2963
37383650 2964 return 1;
6ee73861
BS		 2965}
2966
37383650 2967static int
6ee73861
BS		 2968init_time(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2969{
2970 /*
2971 * INIT_TIME opcode: 0x74 ('t')
2972 *
2973 * offset (8 bit): opcode
2974 * offset + 1 (16 bit): time
2975 *
2976 * Sleep for "time" microseconds.
2977 */
2978
2979 unsigned time = ROM16(bios->data[offset + 1]);
2980
2981 if (!iexec->execute)
37383650 2982 return 3;
6ee73861
BS		 2983
2984 BIOSLOG(bios, "0x%04X: Sleeping for 0x%04X microseconds\n",
2985 offset, time);
2986
2987 if (time < 1000)
2988 udelay(time);
2989 else
c7ca4d1b 2990 mdelay((time + 900) / 1000);
6ee73861 2991
37383650 2992 return 3;
6ee73861
BS		 2993}
2994
37383650 2995static int
6ee73861
BS		 2996init_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
2997{
2998 /*
2999 * INIT_CONDITION opcode: 0x75 ('u')
3000 *
3001 * offset (8 bit): opcode
3002 * offset + 1 (8 bit): condition number
3003 *
3004 * Check condition "condition number" in the condition table.
3005 * If condition not met skip subsequent opcodes until condition is
3006 * inverted (INIT_NOT), or we hit INIT_RESUME
3007 */
3008
3009 uint8_t cond = bios->data[offset + 1];
3010
3011 if (!iexec->execute)
37383650 3012 return 2;
6ee73861
BS		 3013
3014 BIOSLOG(bios, "0x%04X: Condition: 0x%02X\n", offset, cond);
3015
3016 if (bios_condition_met(bios, offset, cond))
3017 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3018 else {
3019 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3020 iexec->execute = false;
3021 }
3022
37383650 3023 return 2;
6ee73861
BS		 3024}
3025
37383650 3026static int
6ee73861
BS		 3027init_io_condition(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3028{
3029 /*
3030 * INIT_IO_CONDITION opcode: 0x76
3031 *
3032 * offset (8 bit): opcode
3033 * offset + 1 (8 bit): condition number
3034 *
3035 * Check condition "condition number" in the io condition table.
3036 * If condition not met skip subsequent opcodes until condition is
3037 * inverted (INIT_NOT), or we hit INIT_RESUME
3038 */
3039
3040 uint8_t cond = bios->data[offset + 1];
3041
3042 if (!iexec->execute)
37383650 3043 return 2;
6ee73861
BS		 3044
3045 BIOSLOG(bios, "0x%04X: IO condition: 0x%02X\n", offset, cond);
3046
3047 if (io_condition_met(bios, offset, cond))
3048 BIOSLOG(bios, "0x%04X: Condition fulfilled -- continuing to execute\n", offset);
3049 else {
3050 BIOSLOG(bios, "0x%04X: Condition not fulfilled -- skipping following commands\n", offset);
3051 iexec->execute = false;
3052 }
3053
37383650 3054 return 2;
6ee73861
BS		 3055}
3056
37383650 3057static int
6ee73861
BS		 3058init_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3059{
3060 /*
3061 * INIT_INDEX_IO opcode: 0x78 ('x')
3062 *
3063 * offset (8 bit): opcode
3064 * offset + 1 (16 bit): CRTC port
3065 * offset + 3 (8 bit): CRTC index
3066 * offset + 4 (8 bit): mask
3067 * offset + 5 (8 bit): data
3068 *
3069 * Read value at index "CRTC index" on "CRTC port", AND with "mask",
3070 * OR with "data", write-back
3071 */
3072
3073 uint16_t crtcport = ROM16(bios->data[offset + 1]);
3074 uint8_t crtcindex = bios->data[offset + 3];
3075 uint8_t mask = bios->data[offset + 4];
3076 uint8_t data = bios->data[offset + 5];
3077 uint8_t value;
3078
3079 if (!iexec->execute)
37383650 3080 return 6;
6ee73861
BS		 3081
3082 BIOSLOG(bios, "0x%04X: Port: 0x%04X, Index: 0x%02X, Mask: 0x%02X, "
3083 "Data: 0x%02X\n",
3084 offset, crtcport, crtcindex, mask, data);
3085
3086 value = (bios_idxprt_rd(bios, crtcport, crtcindex) & mask) | data;
3087 bios_idxprt_wr(bios, crtcport, crtcindex, value);
3088
37383650 3089 return 6;
6ee73861
BS		 3090}
3091
37383650 3092static int
6ee73861
BS		 3093init_pll(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3094{
3095 /*
3096 * INIT_PLL opcode: 0x79 ('y')
3097 *
3098 * offset (8 bit): opcode
3099 * offset + 1 (32 bit): register
3100 * offset + 5 (16 bit): freq
3101 *
3102 * Set PLL register "register" to coefficients for frequency (10kHz)
3103 * "freq"
3104 */
3105
3106 uint32_t reg = ROM32(bios->data[offset + 1]);
3107 uint16_t freq = ROM16(bios->data[offset + 5]);
3108
3109 if (!iexec->execute)
37383650 3110 return 7;
6ee73861
BS		 3111
3112 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, Freq: %d0kHz\n", offset, reg, freq);
3113
3114 setPLL(bios, reg, freq * 10);
3115
37383650 3116 return 7;
6ee73861
BS		 3117}
3118
37383650 3119static int
6ee73861
BS		 3120init_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3121{
3122 /*
3123 * INIT_ZM_REG opcode: 0x7A ('z')
3124 *
3125 * offset (8 bit): opcode
3126 * offset + 1 (32 bit): register
3127 * offset + 5 (32 bit): value
3128 *
3129 * Assign "value" to "register"
3130 */
3131
3132 uint32_t reg = ROM32(bios->data[offset + 1]);
3133 uint32_t value = ROM32(bios->data[offset + 5]);
3134
3135 if (!iexec->execute)
37383650 3136 return 9;
6ee73861
BS		 3137
3138 if (reg == 0x000200)
3139 value |= 1;
3140
3141 bios_wr32(bios, reg, value);
3142
37383650 3143 return 9;
6ee73861
BS		 3144}
3145
37383650 3146static int
6ee73861
BS		 3147init_ram_restrict_pll(struct nvbios *bios, uint16_t offset,
3148 struct init_exec *iexec)
3149{
3150 /*
3151 * INIT_RAM_RESTRICT_PLL opcode: 0x87 ('')
3152 *
3153 * offset (8 bit): opcode
3154 * offset + 1 (8 bit): PLL type
3155 * offset + 2 (32 bit): frequency 0
3156 *
3157 * Uses the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3158 * ram_restrict_table_ptr. The value read from there is used to select
3159 * a frequency from the table starting at 'frequency 0' to be
3160 * programmed into the PLL corresponding to 'type'.
3161 *
3162 * The PLL limits table on cards using this opcode has a mapping of
3163 * 'type' to the relevant registers.
3164 */
3165
3166 struct drm_device *dev = bios->dev;
3167 uint32_t strap = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
3168 uint8_t index = bios->data[bios->ram_restrict_tbl_ptr + strap];
3169 uint8_t type = bios->data[offset + 1];
3170 uint32_t freq = ROM32(bios->data[offset + 2 + (index * 4)]);
3171 uint8_t *pll_limits = &bios->data[bios->pll_limit_tbl_ptr], *entry;
37383650 3172 int len = 2 + bios->ram_restrict_group_count * 4;
6ee73861
BS		 3173 int i;
3174
3175 if (!iexec->execute)
37383650 3176 return len;
6ee73861
BS		 3177
3178 if (!bios->pll_limit_tbl_ptr || (pll_limits[0] & 0xf0) != 0x30) {
3179 NV_ERROR(dev, "PLL limits table not version 3.x\n");
37383650 3180 return len; /* deliberate, allow default clocks to remain */
6ee73861
BS		 3181 }
3182
3183 entry = pll_limits + pll_limits[1];
3184 for (i = 0; i < pll_limits[3]; i++, entry += pll_limits[2]) {
3185 if (entry[0] == type) {
3186 uint32_t reg = ROM32(entry[3]);
3187
3188 BIOSLOG(bios, "0x%04X: "
3189 "Type %02x Reg 0x%08x Freq %dKHz\n",
3190 offset, type, reg, freq);
3191
3192 setPLL(bios, reg, freq);
37383650 3193 return len;
6ee73861
BS		 3194 }
3195 }
3196
3197 NV_ERROR(dev, "PLL type 0x%02x not found in PLL limits table", type);
37383650 3198 return len;
6ee73861
BS		 3199}
3200
37383650 3201static int
6ee73861
BS		 3202init_8c(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3203{
3204 /*
3205 * INIT_8C opcode: 0x8C ('')
3206 *
3207 * NOP so far....
3208 *
3209 */
3210
37383650 3211 return 1;
6ee73861
BS		 3212}
3213
37383650 3214static int
6ee73861
BS		 3215init_8d(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3216{
3217 /*
3218 * INIT_8D opcode: 0x8D ('')
3219 *
3220 * NOP so far....
3221 *
3222 */
3223
37383650 3224 return 1;
6ee73861
BS		 3225}
3226
75139063
BS		 3227static void
3228init_gpio_unknv50(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3229{
3230 const uint32_t nv50_gpio_ctl[2] = { 0xe100, 0xe28c };
3231 u32 r, s, v;
3232
3233 /* Not a clue, needs de-magicing */
3234 r = nv50_gpio_ctl[gpio->line >> 4];
3235 s = (gpio->line & 0x0f);
3236 v = bios_rd32(bios, r) & ~(0x00010001 << s);
3237 switch ((gpio->entry & 0x06000000) >> 25) {
3238 case 1:
3239 v |= (0x00000001 << s);
3240 break;
3241 case 2:
3242 v |= (0x00010000 << s);
3243 break;
3244 default:
3245 break;
3246 }
3247
3248 bios_wr32(bios, r, v);
3249}
3250
3251static void
3252init_gpio_unknvd0(struct nvbios *bios, struct dcb_gpio_entry *gpio)
3253{
3254 u32 v, i;
3255
3256 v = bios_rd32(bios, 0x00d610 + (gpio->line * 4));
3257 v &= 0xffffff00;
3258 v |= (gpio->entry & 0x00ff0000) >> 16;
3259 bios_wr32(bios, 0x00d610 + (gpio->line * 4), v);
3260
3261 i = (gpio->entry & 0x1f000000) >> 24;
3262 if (i) {
3263 v = bios_rd32(bios, 0x00d640 + ((i - 1) * 4));
3264 v &= 0xffffff00;
3265 v |= gpio->line;
3266 bios_wr32(bios, 0x00d640 + ((i - 1) * 4), v);
3267 }
3268}
3269
37383650 3270static int
6ee73861
BS		 3271init_gpio(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3272{
3273 /*
3274 * INIT_GPIO opcode: 0x8E ('')
3275 *
3276 * offset (8 bit): opcode
3277 *
3278 * Loop over all entries in the DCB GPIO table, and initialise
3279 * each GPIO according to various values listed in each entry
3280 */
3281
2535d71c 3282 struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
ee2e0131 3283 struct nouveau_gpio_engine *pgpio = &dev_priv->engine.gpio;
6ee73861
BS		 3284 int i;
3285
080feda5 3286 if (dev_priv->card_type < NV_50) {
2535d71c 3287 NV_ERROR(bios->dev, "INIT_GPIO on unsupported chipset\n");
309b8c89 3288 return 1;
6ee73861
BS		 3289 }
3290
2535d71c
BS		 3291 if (!iexec->execute)
3292 return 1;
6ee73861 3293
2535d71c
BS		 3294 for (i = 0; i < bios->dcb.gpio.entries; i++) {
3295 struct dcb_gpio_entry *gpio = &bios->dcb.gpio.entry[i];
6ee73861 3296
2535d71c 3297 BIOSLOG(bios, "0x%04X: Entry: 0x%08X\n", offset, gpio->entry);
6ee73861 3298
73db4bed
BS		 3299 BIOSLOG(bios, "0x%04X: set gpio 0x%02x, state %d\n",
3300 offset, gpio->tag, gpio->state_default);
6ee73861 3301
75139063
BS		 3302 if (!bios->execute)
3303 continue;
3304
3305 pgpio->set(bios->dev, gpio->tag, gpio->state_default);
3306 if (dev_priv->card_type < NV_D0)
3307 init_gpio_unknv50(bios, gpio);
3308 else
3309 init_gpio_unknvd0(bios, gpio);
6ee73861
BS		 3310 }
3311
37383650 3312 return 1;
6ee73861
BS		 3313}
3314
37383650 3315static int
6ee73861
BS		 3316init_ram_restrict_zm_reg_group(struct nvbios *bios, uint16_t offset,
3317 struct init_exec *iexec)
3318{
3319 /*
3320 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode: 0x8F ('')
3321 *
3322 * offset (8 bit): opcode
3323 * offset + 1 (32 bit): reg
3324 * offset + 5 (8 bit): regincrement
3325 * offset + 6 (8 bit): count
3326 * offset + 7 (32 bit): value 1,1
3327 * ...
3328 *
3329 * Use the RAMCFG strap of PEXTDEV_BOOT as an index into the table at
3330 * ram_restrict_table_ptr. The value read from here is 'n', and
3331 * "value 1,n" gets written to "reg". This repeats "count" times and on
3332 * each iteration 'm', "reg" increases by "regincrement" and
3333 * "value m,n" is used. The extent of n is limited by a number read
3334 * from the 'M' BIT table, herein called "blocklen"
3335 */
3336
3337 uint32_t reg = ROM32(bios->data[offset + 1]);
3338 uint8_t regincrement = bios->data[offset + 5];
3339 uint8_t count = bios->data[offset + 6];
3340 uint32_t strap_ramcfg, data;
37383650
MK		 3341 /* previously set by 'M' BIT table */
3342 uint16_t blocklen = bios->ram_restrict_group_count * 4;
3343 int len = 7 + count * blocklen;
6ee73861
BS		 3344 uint8_t index;
3345 int i;
3346
309b8c89 3347 /* critical! to know the length of the opcode */;
6ee73861
BS		 3348 if (!blocklen) {
3349 NV_ERROR(bios->dev,
3350 "0x%04X: Zero block length - has the M table "
3351 "been parsed?\n", offset);
9170a824 3352 return -EINVAL;
6ee73861
BS		 3353 }
3354
309b8c89
BS		 3355 if (!iexec->execute)
3356 return len;
3357
6ee73861
BS		 3358 strap_ramcfg = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 2) & 0xf;
3359 index = bios->data[bios->ram_restrict_tbl_ptr + strap_ramcfg];
3360
3361 BIOSLOG(bios, "0x%04X: Reg: 0x%08X, RegIncrement: 0x%02X, "
3362 "Count: 0x%02X, StrapRamCfg: 0x%02X, Index: 0x%02X\n",
3363 offset, reg, regincrement, count, strap_ramcfg, index);
3364
3365 for (i = 0; i < count; i++) {
3366 data = ROM32(bios->data[offset + 7 + index * 4 + blocklen * i]);
3367
3368 bios_wr32(bios, reg, data);
3369
3370 reg += regincrement;
3371 }
3372
37383650 3373 return len;
6ee73861
BS		 3374}
3375
37383650 3376static int
6ee73861
BS		 3377init_copy_zm_reg(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3378{
3379 /*
3380 * INIT_COPY_ZM_REG opcode: 0x90 ('')
3381 *
3382 * offset (8 bit): opcode
3383 * offset + 1 (32 bit): src reg
3384 * offset + 5 (32 bit): dst reg
3385 *
3386 * Put contents of "src reg" into "dst reg"
3387 */
3388
3389 uint32_t srcreg = ROM32(bios->data[offset + 1]);
3390 uint32_t dstreg = ROM32(bios->data[offset + 5]);
3391
3392 if (!iexec->execute)
37383650 3393 return 9;
6ee73861
BS		 3394
3395 bios_wr32(bios, dstreg, bios_rd32(bios, srcreg));
3396
37383650 3397 return 9;
6ee73861
BS		 3398}
3399
37383650 3400static int
6ee73861
BS		 3401init_zm_reg_group_addr_latched(struct nvbios *bios, uint16_t offset,
3402 struct init_exec *iexec)
3403{
3404 /*
3405 * INIT_ZM_REG_GROUP_ADDRESS_LATCHED opcode: 0x91 ('')
3406 *
3407 * offset (8 bit): opcode
3408 * offset + 1 (32 bit): dst reg
3409 * offset + 5 (8 bit): count
3410 * offset + 6 (32 bit): data 1
3411 * ...
3412 *
3413 * For each of "count" values write "data n" to "dst reg"
3414 */
3415
3416 uint32_t reg = ROM32(bios->data[offset + 1]);
3417 uint8_t count = bios->data[offset + 5];
37383650 3418 int len = 6 + count * 4;
6ee73861
BS		 3419 int i;
3420
3421 if (!iexec->execute)
37383650 3422 return len;
6ee73861
BS		 3423
3424 for (i = 0; i < count; i++) {
3425 uint32_t data = ROM32(bios->data[offset + 6 + 4 * i]);
3426 bios_wr32(bios, reg, data);
3427 }
3428
37383650 3429 return len;
6ee73861
BS		 3430}
3431
37383650 3432static int
6ee73861
BS		 3433init_reserved(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3434{
3435 /*
3436 * INIT_RESERVED opcode: 0x92 ('')
3437 *
3438 * offset (8 bit): opcode
3439 *
3440 * Seemingly does nothing
3441 */
3442
37383650 3443 return 1;
6ee73861
BS		 3444}
3445
37383650 3446static int
6ee73861
BS		 3447init_96(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3448{
3449 /*
3450 * INIT_96 opcode: 0x96 ('')
3451 *
3452 * offset (8 bit): opcode
3453 * offset + 1 (32 bit): sreg
3454 * offset + 5 (8 bit): sshift
3455 * offset + 6 (8 bit): smask
3456 * offset + 7 (8 bit): index
3457 * offset + 8 (32 bit): reg
3458 * offset + 12 (32 bit): mask
3459 * offset + 16 (8 bit): shift
3460 *
3461 */
3462
3463 uint16_t xlatptr = bios->init96_tbl_ptr + (bios->data[offset + 7] * 2);
3464 uint32_t reg = ROM32(bios->data[offset + 8]);
3465 uint32_t mask = ROM32(bios->data[offset + 12]);
3466 uint32_t val;
3467
3468 val = bios_rd32(bios, ROM32(bios->data[offset + 1]));
3469 if (bios->data[offset + 5] < 0x80)
3470 val >>= bios->data[offset + 5];
3471 else
3472 val <<= (0x100 - bios->data[offset + 5]);
3473 val &= bios->data[offset + 6];
3474
3475 val = bios->data[ROM16(bios->data[xlatptr]) + val];
3476 val <<= bios->data[offset + 16];
3477
3478 if (!iexec->execute)
37383650 3479 return 17;
6ee73861
BS		 3480
3481 bios_wr32(bios, reg, (bios_rd32(bios, reg) & mask) | val);
37383650 3482 return 17;
6ee73861
BS		 3483}
3484
37383650 3485static int
6ee73861
BS		 3486init_97(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3487{
3488 /*
3489 * INIT_97 opcode: 0x97 ('')
3490 *
3491 * offset (8 bit): opcode
3492 * offset + 1 (32 bit): register
3493 * offset + 5 (32 bit): mask
3494 * offset + 9 (32 bit): value
3495 *
3496 * Adds "value" to "register" preserving the fields specified
3497 * by "mask"
3498 */
3499
3500 uint32_t reg = ROM32(bios->data[offset + 1]);
3501 uint32_t mask = ROM32(bios->data[offset + 5]);
3502 uint32_t add = ROM32(bios->data[offset + 9]);
3503 uint32_t val;
3504
3505 val = bios_rd32(bios, reg);
3506 val = (val & mask) | ((val + add) & ~mask);
3507
3508 if (!iexec->execute)
37383650 3509 return 13;
6ee73861
BS		 3510
3511 bios_wr32(bios, reg, val);
37383650 3512 return 13;
6ee73861
BS		 3513}
3514
37383650 3515static int
6ee73861
BS		 3516init_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3517{
3518 /*
3519 * INIT_AUXCH opcode: 0x98 ('')
3520 *
3521 * offset (8 bit): opcode
3522 * offset + 1 (32 bit): address
3523 * offset + 5 (8 bit): count
3524 * offset + 6 (8 bit): mask 0
3525 * offset + 7 (8 bit): data 0
3526 * ...
3527 *
3528 */
3529
3530 struct drm_device *dev = bios->dev;
3531 struct nouveau_i2c_chan *auxch;
3532 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3533 uint8_t count = bios->data[offset + 5];
3534 int len = 6 + count * 2;
6ee73861
BS		 3535 int ret, i;
3536
3537 if (!bios->display.output) {
3538 NV_ERROR(dev, "INIT_AUXCH: no active output\n");
309b8c89 3539 return len;
6ee73861
BS		 3540 }
3541
3542 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3543 if (!auxch) {
3544 NV_ERROR(dev, "INIT_AUXCH: couldn't get auxch %d\n",
3545 bios->display.output->i2c_index);
309b8c89 3546 return len;
6ee73861
BS		 3547 }
3548
3549 if (!iexec->execute)
37383650 3550 return len;
6ee73861
BS		 3551
3552 offset += 6;
37383650 3553 for (i = 0; i < count; i++, offset += 2) {
6ee73861
BS		 3554 uint8_t data;
3555
3556 ret = nouveau_dp_auxch(auxch, 9, addr, &data, 1);
3557 if (ret) {
3558 NV_ERROR(dev, "INIT_AUXCH: rd auxch fail %d\n", ret);
309b8c89 3559 return len;
6ee73861
BS		 3560 }
3561
3562 data &= bios->data[offset + 0];
3563 data |= bios->data[offset + 1];
3564
3565 ret = nouveau_dp_auxch(auxch, 8, addr, &data, 1);
3566 if (ret) {
3567 NV_ERROR(dev, "INIT_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3568 return len;
6ee73861
BS		 3569 }
3570 }
3571
37383650 3572 return len;
6ee73861
BS		 3573}
3574
37383650 3575static int
6ee73861
BS		 3576init_zm_auxch(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3577{
3578 /*
3579 * INIT_ZM_AUXCH opcode: 0x99 ('')
3580 *
3581 * offset (8 bit): opcode
3582 * offset + 1 (32 bit): address
3583 * offset + 5 (8 bit): count
3584 * offset + 6 (8 bit): data 0
3585 * ...
3586 *
3587 */
3588
3589 struct drm_device *dev = bios->dev;
3590 struct nouveau_i2c_chan *auxch;
3591 uint32_t addr = ROM32(bios->data[offset + 1]);
37383650
MK		 3592 uint8_t count = bios->data[offset + 5];
3593 int len = 6 + count;
6ee73861
BS		 3594 int ret, i;
3595
3596 if (!bios->display.output) {
3597 NV_ERROR(dev, "INIT_ZM_AUXCH: no active output\n");
309b8c89 3598 return len;
6ee73861
BS		 3599 }
3600
3601 auxch = init_i2c_device_find(dev, bios->display.output->i2c_index);
3602 if (!auxch) {
3603 NV_ERROR(dev, "INIT_ZM_AUXCH: couldn't get auxch %d\n",
3604 bios->display.output->i2c_index);
309b8c89 3605 return len;
6ee73861
BS		 3606 }
3607
3608 if (!iexec->execute)
37383650 3609 return len;
6ee73861
BS		 3610
3611 offset += 6;
37383650 3612 for (i = 0; i < count; i++, offset++) {
6ee73861
BS		 3613 ret = nouveau_dp_auxch(auxch, 8, addr, &bios->data[offset], 1);
3614 if (ret) {
3615 NV_ERROR(dev, "INIT_ZM_AUXCH: wr auxch fail %d\n", ret);
309b8c89 3616 return len;
6ee73861
BS		 3617 }
3618 }
3619
37383650 3620 return len;
6ee73861
BS		 3621}
3622
b715d640
MK		 3623static int
3624init_i2c_long_if(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
3625{
3626 /*
3627 * INIT_I2C_LONG_IF opcode: 0x9A ('')
3628 *
3629 * offset (8 bit): opcode
3630 * offset + 1 (8 bit): DCB I2C table entry index
3631 * offset + 2 (8 bit): I2C slave address
3632 * offset + 3 (16 bit): I2C register
3633 * offset + 5 (8 bit): mask
3634 * offset + 6 (8 bit): data
3635 *
3636 * Read the register given by "I2C register" on the device addressed
3637 * by "I2C slave address" on the I2C bus given by "DCB I2C table
3638 * entry index". Compare the result AND "mask" to "data".
3639 * If they're not equal, skip subsequent opcodes until condition is
3640 * inverted (INIT_NOT), or we hit INIT_RESUME
3641 */
3642
3643 uint8_t i2c_index = bios->data[offset + 1];
3644 uint8_t i2c_address = bios->data[offset + 2] >> 1;
3645 uint8_t reglo = bios->data[offset + 3];
3646 uint8_t reghi = bios->data[offset + 4];
3647 uint8_t mask = bios->data[offset + 5];
3648 uint8_t data = bios->data[offset + 6];
3649 struct nouveau_i2c_chan *chan;
3650 uint8_t buf0[2] = { reghi, reglo };
3651 uint8_t buf1[1];
3652 struct i2c_msg msg[2] = {
3653 { i2c_address, 0, 1, buf0 },
3654 { i2c_address, I2C_M_RD, 1, buf1 },
3655 };
3656 int ret;
3657
3658 /* no execute check by design */
3659
3660 BIOSLOG(bios, "0x%04X: DCBI2CIndex: 0x%02X, I2CAddress: 0x%02X\n",
3661 offset, i2c_index, i2c_address);
3662
3663 chan = init_i2c_device_find(bios->dev, i2c_index);
3664 if (!chan)
3665 return -ENODEV;
3666
3667
3668 ret = i2c_transfer(&chan->adapter, msg, 2);
3669 if (ret < 0) {
3670 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: [no device], "
3671 "Mask: 0x%02X, Data: 0x%02X\n",
3672 offset, reghi, reglo, mask, data);
3673 iexec->execute = 0;
3674 return 7;
3675 }
3676
3677 BIOSLOG(bios, "0x%04X: I2CReg: 0x%02X:0x%02X, Value: 0x%02X, "
3678 "Mask: 0x%02X, Data: 0x%02X\n",
3679 offset, reghi, reglo, buf1[0], mask, data);
3680
3681 iexec->execute = ((buf1[0] & mask) == data);
3682
3683 return 7;
3684}
3685
6ee73861
BS		 3686static struct init_tbl_entry itbl_entry[] = {
3687 /* command name , id , length , offset , mult , command handler */
3688 /* INIT_PROG (0x31, 15, 10, 4) removed due to no example of use */
37383650
MK		 3689 { "INIT_IO_RESTRICT_PROG" , 0x32, init_io_restrict_prog },
3690 { "INIT_REPEAT" , 0x33, init_repeat },
3691 { "INIT_IO_RESTRICT_PLL" , 0x34, init_io_restrict_pll },
3692 { "INIT_END_REPEAT" , 0x36, init_end_repeat },
3693 { "INIT_COPY" , 0x37, init_copy },
3694 { "INIT_NOT" , 0x38, init_not },
3695 { "INIT_IO_FLAG_CONDITION" , 0x39, init_io_flag_condition },
25908b77
BS		 3696 { "INIT_DP_CONDITION" , 0x3A, init_dp_condition },
3697 { "INIT_OP_3B" , 0x3B, init_op_3b },
3698 { "INIT_OP_3C" , 0x3C, init_op_3c },
37383650
MK		 3699 { "INIT_INDEX_ADDRESS_LATCHED" , 0x49, init_idx_addr_latched },
3700 { "INIT_IO_RESTRICT_PLL2" , 0x4A, init_io_restrict_pll2 },
3701 { "INIT_PLL2" , 0x4B, init_pll2 },
3702 { "INIT_I2C_BYTE" , 0x4C, init_i2c_byte },
3703 { "INIT_ZM_I2C_BYTE" , 0x4D, init_zm_i2c_byte },
3704 { "INIT_ZM_I2C" , 0x4E, init_zm_i2c },
3705 { "INIT_TMDS" , 0x4F, init_tmds },
3706 { "INIT_ZM_TMDS_GROUP" , 0x50, init_zm_tmds_group },
3707 { "INIT_CR_INDEX_ADDRESS_LATCHED" , 0x51, init_cr_idx_adr_latch },
3708 { "INIT_CR" , 0x52, init_cr },
3709 { "INIT_ZM_CR" , 0x53, init_zm_cr },
3710 { "INIT_ZM_CR_GROUP" , 0x54, init_zm_cr_group },
3711 { "INIT_CONDITION_TIME" , 0x56, init_condition_time },
e3a1924f 3712 { "INIT_LTIME" , 0x57, init_ltime },
37383650 3713 { "INIT_ZM_REG_SEQUENCE" , 0x58, init_zm_reg_sequence },
6ee73861 3714 /* INIT_INDIRECT_REG (0x5A, 7, 0, 0) removed due to no example of use */
37383650 3715 { "INIT_SUB_DIRECT" , 0x5B, init_sub_direct },
ec64a408 3716 { "INIT_JUMP" , 0x5C, init_jump },
b715d640 3717 { "INIT_I2C_IF" , 0x5E, init_i2c_if },
37383650
MK		 3718 { "INIT_COPY_NV_REG" , 0x5F, init_copy_nv_reg },
3719 { "INIT_ZM_INDEX_IO" , 0x62, init_zm_index_io },
3720 { "INIT_COMPUTE_MEM" , 0x63, init_compute_mem },
3721 { "INIT_RESET" , 0x65, init_reset },
3722 { "INIT_CONFIGURE_MEM" , 0x66, init_configure_mem },
3723 { "INIT_CONFIGURE_CLK" , 0x67, init_configure_clk },
3724 { "INIT_CONFIGURE_PREINIT" , 0x68, init_configure_preinit },
3725 { "INIT_IO" , 0x69, init_io },
3726 { "INIT_SUB" , 0x6B, init_sub },
3727 { "INIT_RAM_CONDITION" , 0x6D, init_ram_condition },
3728 { "INIT_NV_REG" , 0x6E, init_nv_reg },
3729 { "INIT_MACRO" , 0x6F, init_macro },
3730 { "INIT_DONE" , 0x71, init_done },
3731 { "INIT_RESUME" , 0x72, init_resume },
6ee73861 3732 /* INIT_RAM_CONDITION2 (0x73, 9, 0, 0) removed due to no example of use */
37383650
MK		 3733 { "INIT_TIME" , 0x74, init_time },
3734 { "INIT_CONDITION" , 0x75, init_condition },
3735 { "INIT_IO_CONDITION" , 0x76, init_io_condition },
3736 { "INIT_INDEX_IO" , 0x78, init_index_io },
3737 { "INIT_PLL" , 0x79, init_pll },
3738 { "INIT_ZM_REG" , 0x7A, init_zm_reg },
3739 { "INIT_RAM_RESTRICT_PLL" , 0x87, init_ram_restrict_pll },
3740 { "INIT_8C" , 0x8C, init_8c },
3741 { "INIT_8D" , 0x8D, init_8d },
3742 { "INIT_GPIO" , 0x8E, init_gpio },
3743 { "INIT_RAM_RESTRICT_ZM_REG_GROUP" , 0x8F, init_ram_restrict_zm_reg_group },
3744 { "INIT_COPY_ZM_REG" , 0x90, init_copy_zm_reg },
3745 { "INIT_ZM_REG_GROUP_ADDRESS_LATCHED" , 0x91, init_zm_reg_group_addr_latched },
3746 { "INIT_RESERVED" , 0x92, init_reserved },
3747 { "INIT_96" , 0x96, init_96 },
3748 { "INIT_97" , 0x97, init_97 },
3749 { "INIT_AUXCH" , 0x98, init_auxch },
3750 { "INIT_ZM_AUXCH" , 0x99, init_zm_auxch },
b715d640 3751 { "INIT_I2C_LONG_IF" , 0x9A, init_i2c_long_if },
37383650 3752 { NULL , 0 , NULL }
6ee73861
BS		 3753};
3754
6ee73861
BS		 3755#define MAX_TABLE_OPS 1000
3756
3757static int
ec64a408 3758parse_init_table(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
6ee73861
BS		 3759{
3760 /*
3761 * Parses all commands in an init table.
3762 *
3763 * We start out executing all commands found in the init table. Some
3764 * opcodes may change the status of iexec->execute to SKIP, which will
3765 * cause the following opcodes to perform no operation until the value
3766 * is changed back to EXECUTE.
3767 */
3768
92b96187 3769 int count = 0, i, ret;
6ee73861
BS		 3770 uint8_t id;
3771
a8e415d3
BS		 3772 /* catch NULL script pointers */
3773 if (offset == 0)
3774 return 0;
3775
6ee73861
BS		 3776 /*
3777 * Loop until INIT_DONE causes us to break out of the loop
3778 * (or until offset > bios length just in case... )
3779 * (and no more than MAX_TABLE_OPS iterations, just in case... )
3780 */
3781 while ((offset < bios->length) && (count++ < MAX_TABLE_OPS)) {
3782 id = bios->data[offset];
3783
3784 /* Find matching id in itbl_entry */
3785 for (i = 0; itbl_entry[i].name && (itbl_entry[i].id != id); i++)
3786 ;
3787
92b96187 3788 if (!itbl_entry[i].name) {
6ee73861
BS		 3789 NV_ERROR(bios->dev,
3790 "0x%04X: Init table command not found: "
3791 "0x%02X\n", offset, id);
3792 return -ENOENT;
3793 }
92b96187
BS		 3794
3795 BIOSLOG(bios, "0x%04X: [ (0x%02X) - %s ]\n", offset,
3796 itbl_entry[i].id, itbl_entry[i].name);
3797
3798 /* execute eventual command handler */
3799 ret = (*itbl_entry[i].handler)(bios, offset, iexec);
3800 if (ret < 0) {
3801 NV_ERROR(bios->dev, "0x%04X: Failed parsing init "
3802 "table opcode: %s %d\n", offset,
3803 itbl_entry[i].name, ret);
3804 }
3805
3806 if (ret <= 0)
3807 break;
3808
3809 /*
3810 * Add the offset of the current command including all data
3811 * of that command. The offset will then be pointing on the
3812 * next op code.
3813 */
3814 offset += ret;
6ee73861
BS		 3815 }
3816
3817 if (offset >= bios->length)
3818 NV_WARN(bios->dev,
3819 "Offset 0x%04X greater than known bios image length. "
3820 "Corrupt image?\n", offset);
3821 if (count >= MAX_TABLE_OPS)
3822 NV_WARN(bios->dev,
3823 "More than %d opcodes to a table is unlikely, "
3824 "is the bios image corrupt?\n", MAX_TABLE_OPS);
3825
3826 return 0;
3827}
3828
3829static void
3830parse_init_tables(struct nvbios *bios)
3831{
3832 /* Loops and calls parse_init_table() for each present table. */
3833
3834 int i = 0;
3835 uint16_t table;
3836 struct init_exec iexec = {true, false};
3837
3838 if (bios->old_style_init) {
3839 if (bios->init_script_tbls_ptr)
3840 parse_init_table(bios, bios->init_script_tbls_ptr, &iexec);
3841 if (bios->extra_init_script_tbl_ptr)
3842 parse_init_table(bios, bios->extra_init_script_tbl_ptr, &iexec);
3843
3844 return;
3845 }
3846
3847 while ((table = ROM16(bios->data[bios->init_script_tbls_ptr + i]))) {
3848 NV_INFO(bios->dev,
3849 "Parsing VBIOS init table %d at offset 0x%04X\n",
3850 i / 2, table);
3851 BIOSLOG(bios, "0x%04X: ------ Executing following commands ------\n", table);
3852
3853 parse_init_table(bios, table, &iexec);
3854 i += 2;
3855 }
3856}
3857
3858static uint16_t clkcmptable(struct nvbios *bios, uint16_t clktable, int pxclk)
3859{
3860 int compare_record_len, i = 0;
3861 uint16_t compareclk, scriptptr = 0;
3862
3863 if (bios->major_version < 5) /* pre BIT */
3864 compare_record_len = 3;
3865 else
3866 compare_record_len = 4;
3867
3868 do {
3869 compareclk = ROM16(bios->data[clktable + compare_record_len * i]);
3870 if (pxclk >= compareclk * 10) {
3871 if (bios->major_version < 5) {
3872 uint8_t tmdssub = bios->data[clktable + 2 + compare_record_len * i];
3873 scriptptr = ROM16(bios->data[bios->init_script_tbls_ptr + tmdssub * 2]);
3874 } else
3875 scriptptr = ROM16(bios->data[clktable + 2 + compare_record_len * i]);
3876 break;
3877 }
3878 i++;
3879 } while (compareclk);
3880
3881 return scriptptr;
3882}
3883
3884static void
3885run_digital_op_script(struct drm_device *dev, uint16_t scriptptr,
3886 struct dcb_entry *dcbent, int head, bool dl)
3887{
3888 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3889 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3890 struct init_exec iexec = {true, false};
3891
3892 NV_TRACE(dev, "0x%04X: Parsing digital output script table\n",
3893 scriptptr);
3894 bios_idxprt_wr(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_44,
3895 head ? NV_CIO_CRE_44_HEADB : NV_CIO_CRE_44_HEADA);
3896 /* note: if dcb entries have been merged, index may be misleading */
3897 NVWriteVgaCrtc5758(dev, head, 0, dcbent->index);
3898 parse_init_table(bios, scriptptr, &iexec);
3899
3900 nv04_dfp_bind_head(dev, dcbent, head, dl);
3901}
3902
3903static int call_lvds_manufacturer_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script)
3904{
3905 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3906 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3907 uint8_t sub = bios->data[bios->fp.xlated_entry + script] + (bios->fp.link_c_increment && dcbent->or & OUTPUT_C ? 1 : 0);
3908 uint16_t scriptofs = ROM16(bios->data[bios->init_script_tbls_ptr + sub * 2]);
3909
3910 if (!bios->fp.xlated_entry || !sub || !scriptofs)
3911 return -EINVAL;
3912
3913 run_digital_op_script(dev, scriptofs, dcbent, head, bios->fp.dual_link);
3914
3915 if (script == LVDS_PANEL_OFF) {
3916 /* off-on delay in ms */
c7ca4d1b 3917 mdelay(ROM16(bios->data[bios->fp.xlated_entry + 7]));
6ee73861
BS		 3918 }
3919#ifdef __powerpc__
3920 /* Powerbook specific quirks */
d31e078d
FJ		 3921 if (script == LVDS_RESET &&
3922 (dev->pci_device == 0x0179 || dev->pci_device == 0x0189 ||
3923 dev->pci_device == 0x0329))
3924 nv_write_tmds(dev, dcbent->or, 0, 0x02, 0x72);
6ee73861
BS		 3925#endif
3926
3927 return 0;
3928}
3929
3930static int run_lvds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
3931{
3932 /*
3933 * The BIT LVDS table's header has the information to setup the
3934 * necessary registers. Following the standard 4 byte header are:
3935 * A bitmask byte and a dual-link transition pxclk value for use in
3936 * selecting the init script when not using straps; 4 script pointers
3937 * for panel power, selected by output and on/off; and 8 table pointers
3938 * for panel init, the needed one determined by output, and bits in the
3939 * conf byte. These tables are similar to the TMDS tables, consisting
3940 * of a list of pxclks and script pointers.
3941 */
3942 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 3943 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 3944 unsigned int outputset = (dcbent->or == 4) ? 1 : 0;
3945 uint16_t scriptptr = 0, clktable;
6ee73861
BS		 3946
3947 /*
3948 * For now we assume version 3.0 table - g80 support will need some
3949 * changes
3950 */
3951
3952 switch (script) {
3953 case LVDS_INIT:
3954 return -ENOSYS;
3955 case LVDS_BACKLIGHT_ON:
3956 case LVDS_PANEL_ON:
3957 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 7 + outputset * 2]);
3958 break;
3959 case LVDS_BACKLIGHT_OFF:
3960 case LVDS_PANEL_OFF:
3961 scriptptr = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 11 + outputset * 2]);
3962 break;
3963 case LVDS_RESET:
f3bbb9cc
BS		 3964 clktable = bios->fp.lvdsmanufacturerpointer + 15;
3965 if (dcbent->or == 4)
3966 clktable += 8;
3967
6ee73861
BS		 3968 if (dcbent->lvdsconf.use_straps_for_mode) {
3969 if (bios->fp.dual_link)
f3bbb9cc
BS		 3970 clktable += 4;
3971 if (bios->fp.if_is_24bit)
3972 clktable += 2;
6ee73861
BS		 3973 } else {
3974 /* using EDID */
f3bbb9cc 3975 int cmpval_24bit = (dcbent->or == 4) ? 4 : 1;
6ee73861
BS		 3976
3977 if (bios->fp.dual_link) {
f3bbb9cc
BS		 3978 clktable += 4;
3979 cmpval_24bit <<= 1;
6ee73861 3980 }
f3bbb9cc
BS		 3981
3982 if (bios->fp.strapless_is_24bit & cmpval_24bit)
3983 clktable += 2;
6ee73861
BS		 3984 }
3985
f3bbb9cc 3986 clktable = ROM16(bios->data[clktable]);
6ee73861
BS		 3987 if (!clktable) {
3988 NV_ERROR(dev, "Pixel clock comparison table not found\n");
3989 return -ENOENT;
3990 }
3991 scriptptr = clkcmptable(bios, clktable, pxclk);
3992 }
3993
3994 if (!scriptptr) {
3995 NV_ERROR(dev, "LVDS output init script not found\n");
3996 return -ENOENT;
3997 }
3998 run_digital_op_script(dev, scriptptr, dcbent, head, bios->fp.dual_link);
3999
4000 return 0;
4001}
4002
4003int call_lvds_script(struct drm_device *dev, struct dcb_entry *dcbent, int head, enum LVDS_script script, int pxclk)
4004{
4005 /*
4006 * LVDS operations are multiplexed in an effort to present a single API
4007 * which works with two vastly differing underlying structures.
4008 * This acts as the demux
4009 */
4010
4011 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4012 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4013 uint8_t lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4014 uint32_t sel_clk_binding, sel_clk;
4015 int ret;
4016
4017 if (bios->fp.last_script_invoc == (script << 1 | head) || !lvds_ver ||
4018 (lvds_ver >= 0x30 && script == LVDS_INIT))
4019 return 0;
4020
4021 if (!bios->fp.lvds_init_run) {
4022 bios->fp.lvds_init_run = true;
4023 call_lvds_script(dev, dcbent, head, LVDS_INIT, pxclk);
4024 }
4025
4026 if (script == LVDS_PANEL_ON && bios->fp.reset_after_pclk_change)
4027 call_lvds_script(dev, dcbent, head, LVDS_RESET, pxclk);
4028 if (script == LVDS_RESET && bios->fp.power_off_for_reset)
4029 call_lvds_script(dev, dcbent, head, LVDS_PANEL_OFF, pxclk);
4030
4031 NV_TRACE(dev, "Calling LVDS script %d:\n", script);
4032
4033 /* don't let script change pll->head binding */
4034 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4035
4036 if (lvds_ver < 0x30)
4037 ret = call_lvds_manufacturer_script(dev, dcbent, head, script);
4038 else
4039 ret = run_lvds_table(dev, dcbent, head, script, pxclk);
4040
4041 bios->fp.last_script_invoc = (script << 1 | head);
4042
4043 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4044 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4045 /* some scripts set a value in NV_PBUS_POWERCTRL_2 and break video overlay */
4046 nvWriteMC(dev, NV_PBUS_POWERCTRL_2, 0);
4047
4048 return ret;
4049}
4050
4051struct lvdstableheader {
4052 uint8_t lvds_ver, headerlen, recordlen;
4053};
4054
4055static int parse_lvds_manufacturer_table_header(struct drm_device *dev, struct nvbios *bios, struct lvdstableheader *lth)
4056{
4057 /*
4058 * BMP version (0xa) LVDS table has a simple header of version and
4059 * record length. The BIT LVDS table has the typical BIT table header:
4060 * version byte, header length byte, record length byte, and a byte for
4061 * the maximum number of records that can be held in the table.
4062 */
4063
4064 uint8_t lvds_ver, headerlen, recordlen;
4065
4066 memset(lth, 0, sizeof(struct lvdstableheader));
4067
4068 if (bios->fp.lvdsmanufacturerpointer == 0x0) {
4069 NV_ERROR(dev, "Pointer to LVDS manufacturer table invalid\n");
4070 return -EINVAL;
4071 }
4072
4073 lvds_ver = bios->data[bios->fp.lvdsmanufacturerpointer];
4074
4075 switch (lvds_ver) {
4076 case 0x0a: /* pre NV40 */
4077 headerlen = 2;
4078 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4079 break;
4080 case 0x30: /* NV4x */
4081 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4082 if (headerlen < 0x1f) {
4083 NV_ERROR(dev, "LVDS table header not understood\n");
4084 return -EINVAL;
4085 }
4086 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4087 break;
4088 case 0x40: /* G80/G90 */
4089 headerlen = bios->data[bios->fp.lvdsmanufacturerpointer + 1];
4090 if (headerlen < 0x7) {
4091 NV_ERROR(dev, "LVDS table header not understood\n");
4092 return -EINVAL;
4093 }
4094 recordlen = bios->data[bios->fp.lvdsmanufacturerpointer + 2];
4095 break;
4096 default:
4097 NV_ERROR(dev,
4098 "LVDS table revision %d.%d not currently supported\n",
4099 lvds_ver >> 4, lvds_ver & 0xf);
4100 return -ENOSYS;
4101 }
4102
4103 lth->lvds_ver = lvds_ver;
4104 lth->headerlen = headerlen;
4105 lth->recordlen = recordlen;
4106
4107 return 0;
4108}
4109
4110static int
4111get_fp_strap(struct drm_device *dev, struct nvbios *bios)
4112{
4113 struct drm_nouveau_private *dev_priv = dev->dev_private;
4114
4115 /*
4116 * The fp strap is normally dictated by the "User Strap" in
4117 * PEXTDEV_BOOT_0[20:16], but on BMP cards when bit 2 of the
4118 * Internal_Flags struct at 0x48 is set, the user strap gets overriden
4119 * by the PCI subsystem ID during POST, but not before the previous user
4120 * strap has been committed to CR58 for CR57=0xf on head A, which may be
4121 * read and used instead
4122 */
4123
4124 if (bios->major_version < 5 && bios->data[0x48] & 0x4)
4125 return NVReadVgaCrtc5758(dev, 0, 0xf) & 0xf;
4126
4127 if (dev_priv->card_type >= NV_50)
4128 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 24) & 0xf;
4129 else
4130 return (bios_rd32(bios, NV_PEXTDEV_BOOT_0) >> 16) & 0xf;
4131}
4132
4133static int parse_fp_mode_table(struct drm_device *dev, struct nvbios *bios)
4134{
4135 uint8_t *fptable;
4136 uint8_t fptable_ver, headerlen = 0, recordlen, fpentries = 0xf, fpindex;
4137 int ret, ofs, fpstrapping;
4138 struct lvdstableheader lth;
4139
4140 if (bios->fp.fptablepointer == 0x0) {
4141 /* Apple cards don't have the fp table; the laptops use DDC */
4142 /* The table is also missing on some x86 IGPs */
4143#ifndef __powerpc__
4144 NV_ERROR(dev, "Pointer to flat panel table invalid\n");
4145#endif
04a39c57 4146 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 4147 return 0;
4148 }
4149
4150 fptable = &bios->data[bios->fp.fptablepointer];
4151 fptable_ver = fptable[0];
4152
4153 switch (fptable_ver) {
4154 /*
4155 * BMP version 0x5.0x11 BIOSen have version 1 like tables, but no
4156 * version field, and miss one of the spread spectrum/PWM bytes.
4157 * This could affect early GF2Go parts (not seen any appropriate ROMs
4158 * though). Here we assume that a version of 0x05 matches this case
4159 * (combining with a BMP version check would be better), as the
4160 * common case for the panel type field is 0x0005, and that is in
4161 * fact what we are reading the first byte of.
4162 */
4163 case 0x05: /* some NV10, 11, 15, 16 */
4164 recordlen = 42;
4165 ofs = -1;
4166 break;
4167 case 0x10: /* some NV15/16, and NV11+ */
4168 recordlen = 44;
4169 ofs = 0;
4170 break;
4171 case 0x20: /* NV40+ */
4172 headerlen = fptable[1];
4173 recordlen = fptable[2];
4174 fpentries = fptable[3];
4175 /*
4176 * fptable[4] is the minimum
4177 * RAMDAC_FP_HCRTC -> RAMDAC_FP_HSYNC_START gap
4178 */
04a39c57 4179 bios->digital_min_front_porch = fptable[4];
6ee73861
BS		 4180 ofs = -7;
4181 break;
4182 default:
4183 NV_ERROR(dev,
4184 "FP table revision %d.%d not currently supported\n",
4185 fptable_ver >> 4, fptable_ver & 0xf);
4186 return -ENOSYS;
4187 }
4188
4189 if (!bios->is_mobile) /* !mobile only needs digital_min_front_porch */
4190 return 0;
4191
4192 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4193 if (ret)
4194 return ret;
4195
4196 if (lth.lvds_ver == 0x30 || lth.lvds_ver == 0x40) {
4197 bios->fp.fpxlatetableptr = bios->fp.lvdsmanufacturerpointer +
4198 lth.headerlen + 1;
4199 bios->fp.xlatwidth = lth.recordlen;
4200 }
4201 if (bios->fp.fpxlatetableptr == 0x0) {
4202 NV_ERROR(dev, "Pointer to flat panel xlat table invalid\n");
4203 return -EINVAL;
4204 }
4205
4206 fpstrapping = get_fp_strap(dev, bios);
4207
4208 fpindex = bios->data[bios->fp.fpxlatetableptr +
4209 fpstrapping * bios->fp.xlatwidth];
4210
4211 if (fpindex > fpentries) {
4212 NV_ERROR(dev, "Bad flat panel table index\n");
4213 return -ENOENT;
4214 }
4215
4216 /* nv4x cards need both a strap value and fpindex of 0xf to use DDC */
4217 if (lth.lvds_ver > 0x10)
04a39c57 4218 bios->fp_no_ddc = fpstrapping != 0xf || fpindex != 0xf;
6ee73861
BS		 4219
4220 /*
4221 * If either the strap or xlated fpindex value are 0xf there is no
4222 * panel using a strap-derived bios mode present. this condition
4223 * includes, but is different from, the DDC panel indicator above
4224 */
4225 if (fpstrapping == 0xf || fpindex == 0xf)
4226 return 0;
4227
4228 bios->fp.mode_ptr = bios->fp.fptablepointer + headerlen +
4229 recordlen * fpindex + ofs;
4230
4231 NV_TRACE(dev, "BIOS FP mode: %dx%d (%dkHz pixel clock)\n",
4232 ROM16(bios->data[bios->fp.mode_ptr + 11]) + 1,
4233 ROM16(bios->data[bios->fp.mode_ptr + 25]) + 1,
4234 ROM16(bios->data[bios->fp.mode_ptr + 7]) * 10);
4235
4236 return 0;
4237}
4238
4239bool nouveau_bios_fp_mode(struct drm_device *dev, struct drm_display_mode *mode)
4240{
4241 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4242 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4243 uint8_t *mode_entry = &bios->data[bios->fp.mode_ptr];
4244
4245 if (!mode) /* just checking whether we can produce a mode */
4246 return bios->fp.mode_ptr;
4247
4248 memset(mode, 0, sizeof(struct drm_display_mode));
4249 /*
4250 * For version 1.0 (version in byte 0):
4251 * bytes 1-2 are "panel type", including bits on whether Colour/mono,
4252 * single/dual link, and type (TFT etc.)
4253 * bytes 3-6 are bits per colour in RGBX
4254 */
4255 mode->clock = ROM16(mode_entry[7]) * 10;
4256 /* bytes 9-10 is HActive */
4257 mode->hdisplay = ROM16(mode_entry[11]) + 1;
4258 /*
4259 * bytes 13-14 is HValid Start
4260 * bytes 15-16 is HValid End
4261 */
4262 mode->hsync_start = ROM16(mode_entry[17]) + 1;
4263 mode->hsync_end = ROM16(mode_entry[19]) + 1;
4264 mode->htotal = ROM16(mode_entry[21]) + 1;
4265 /* bytes 23-24, 27-30 similarly, but vertical */
4266 mode->vdisplay = ROM16(mode_entry[25]) + 1;
4267 mode->vsync_start = ROM16(mode_entry[31]) + 1;
4268 mode->vsync_end = ROM16(mode_entry[33]) + 1;
4269 mode->vtotal = ROM16(mode_entry[35]) + 1;
4270 mode->flags |= (mode_entry[37] & 0x10) ?
4271 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC;
4272 mode->flags |= (mode_entry[37] & 0x1) ?
4273 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC;
4274 /*
4275 * bytes 38-39 relate to spread spectrum settings
4276 * bytes 40-43 are something to do with PWM
4277 */
4278
4279 mode->status = MODE_OK;
4280 mode->type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
4281 drm_mode_set_name(mode);
4282 return bios->fp.mode_ptr;
4283}
4284
4285int nouveau_bios_parse_lvds_table(struct drm_device *dev, int pxclk, bool *dl, bool *if_is_24bit)
4286{
4287 /*
4288 * The LVDS table header is (mostly) described in
4289 * parse_lvds_manufacturer_table_header(): the BIT header additionally
4290 * contains the dual-link transition pxclk (in 10s kHz), at byte 5 - if
4291 * straps are not being used for the panel, this specifies the frequency
4292 * at which modes should be set up in the dual link style.
4293 *
4294 * Following the header, the BMP (ver 0xa) table has several records,
3ad2f3fb 4295 * indexed by a separate xlat table, indexed in turn by the fp strap in
6ee73861
BS		 4296 * EXTDEV_BOOT. Each record had a config byte, followed by 6 script
4297 * numbers for use by INIT_SUB which controlled panel init and power,
4298 * and finally a dword of ms to sleep between power off and on
4299 * operations.
4300 *
4301 * In the BIT versions, the table following the header serves as an
4302 * integrated config and xlat table: the records in the table are
4303 * indexed by the FP strap nibble in EXTDEV_BOOT, and each record has
4304 * two bytes - the first as a config byte, the second for indexing the
4305 * fp mode table pointed to by the BIT 'D' table
4306 *
4307 * DDC is not used until after card init, so selecting the correct table
4308 * entry and setting the dual link flag for EDID equipped panels,
4309 * requiring tests against the native-mode pixel clock, cannot be done
4310 * until later, when this function should be called with non-zero pxclk
4311 */
4312 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4313 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4314 int fpstrapping = get_fp_strap(dev, bios), lvdsmanufacturerindex = 0;
4315 struct lvdstableheader lth;
4316 uint16_t lvdsofs;
04a39c57 4317 int ret, chip_version = bios->chip_version;
6ee73861
BS		 4318
4319 ret = parse_lvds_manufacturer_table_header(dev, bios, &lth);
4320 if (ret)
4321 return ret;
4322
4323 switch (lth.lvds_ver) {
4324 case 0x0a: /* pre NV40 */
4325 lvdsmanufacturerindex = bios->data[
4326 bios->fp.fpxlatemanufacturertableptr +
4327 fpstrapping];
4328
4329 /* we're done if this isn't the EDID panel case */
4330 if (!pxclk)
4331 break;
4332
4333 if (chip_version < 0x25) {
4334 /* nv17 behaviour
4335 *
4336 * It seems the old style lvds script pointer is reused
4337 * to select 18/24 bit colour depth for EDID panels.
4338 */
4339 lvdsmanufacturerindex =
4340 (bios->legacy.lvds_single_a_script_ptr & 1) ?
4341 2 : 0;
4342 if (pxclk >= bios->fp.duallink_transition_clk)
4343 lvdsmanufacturerindex++;
4344 } else if (chip_version < 0x30) {
4345 /* nv28 behaviour (off-chip encoder)
4346 *
4347 * nv28 does a complex dance of first using byte 121 of
4348 * the EDID to choose the lvdsmanufacturerindex, then
4349 * later attempting to match the EDID manufacturer and
4350 * product IDs in a table (signature 'pidt' (panel id
4351 * table?)), setting an lvdsmanufacturerindex of 0 and
4352 * an fp strap of the match index (or 0xf if none)
4353 */
4354 lvdsmanufacturerindex = 0;
4355 } else {
4356 /* nv31, nv34 behaviour */
4357 lvdsmanufacturerindex = 0;
4358 if (pxclk >= bios->fp.duallink_transition_clk)
4359 lvdsmanufacturerindex = 2;
4360 if (pxclk >= 140000)
4361 lvdsmanufacturerindex = 3;
4362 }
4363
4364 /*
4365 * nvidia set the high nibble of (cr57=f, cr58) to
4366 * lvdsmanufacturerindex in this case; we don't
4367 */
4368 break;
4369 case 0x30: /* NV4x */
4370 case 0x40: /* G80/G90 */
4371 lvdsmanufacturerindex = fpstrapping;
4372 break;
4373 default:
4374 NV_ERROR(dev, "LVDS table revision not currently supported\n");
4375 return -ENOSYS;
4376 }
4377
4378 lvdsofs = bios->fp.xlated_entry = bios->fp.lvdsmanufacturerpointer + lth.headerlen + lth.recordlen * lvdsmanufacturerindex;
4379 switch (lth.lvds_ver) {
4380 case 0x0a:
4381 bios->fp.power_off_for_reset = bios->data[lvdsofs] & 1;
4382 bios->fp.reset_after_pclk_change = bios->data[lvdsofs] & 2;
4383 bios->fp.dual_link = bios->data[lvdsofs] & 4;
4384 bios->fp.link_c_increment = bios->data[lvdsofs] & 8;
4385 *if_is_24bit = bios->data[lvdsofs] & 16;
4386 break;
4387 case 0x30:
f3bbb9cc 4388 case 0x40:
6ee73861
BS		 4389 /*
4390 * No sign of the "power off for reset" or "reset for panel
4391 * on" bits, but it's safer to assume we should
4392 */
4393 bios->fp.power_off_for_reset = true;
4394 bios->fp.reset_after_pclk_change = true;
f3bbb9cc 4395
6ee73861
BS		 4396 /*
4397 * It's ok lvdsofs is wrong for nv4x edid case; dual_link is
f3bbb9cc 4398 * over-written, and if_is_24bit isn't used
6ee73861
BS		 4399 */
4400 bios->fp.dual_link = bios->data[lvdsofs] & 1;
6ee73861
BS		 4401 bios->fp.if_is_24bit = bios->data[lvdsofs] & 2;
4402 bios->fp.strapless_is_24bit = bios->data[bios->fp.lvdsmanufacturerpointer + 4];
4403 bios->fp.duallink_transition_clk = ROM16(bios->data[bios->fp.lvdsmanufacturerpointer + 5]) * 10;
4404 break;
4405 }
4406
2eb92c80
BS		 4407 /* Dell Latitude D620 reports a too-high value for the dual-link
4408 * transition freq, causing us to program the panel incorrectly.
4409 *
4410 * It doesn't appear the VBIOS actually uses its transition freq
4411 * (90000kHz), instead it uses the "Number of LVDS channels" field
4412 * out of the panel ID structure (http://www.spwg.org/).
4413 *
4414 * For the moment, a quirk will do :)
4415 */
acae116c 4416 if (nv_match_device(dev, 0x01d7, 0x1028, 0x01c2))
2eb92c80 4417 bios->fp.duallink_transition_clk = 80000;
2eb92c80 4418
6ee73861
BS		 4419 /* set dual_link flag for EDID case */
4420 if (pxclk && (chip_version < 0x25 || chip_version > 0x28))
4421 bios->fp.dual_link = (pxclk >= bios->fp.duallink_transition_clk);
4422
4423 *dl = bios->fp.dual_link;
4424
4425 return 0;
4426}
4427
721b0821
BS		 4428/* BIT 'U'/'d' table encoder subtables have hashes matching them to
4429 * a particular set of encoders.
4430 *
4431 * This function returns true if a particular DCB entry matches.
4432 */
4433bool
4434bios_encoder_match(struct dcb_entry *dcb, u32 hash)
6ee73861 4435{
721b0821
BS		 4436 if ((hash & 0x000000f0) != (dcb->location << 4))
4437 return false;
4438 if ((hash & 0x0000000f) != dcb->type)
4439 return false;
4440 if (!(hash & (dcb->or << 16)))
4441 return false;
4442
4443 switch (dcb->type) {
1eb38100
BS		 4444 case OUTPUT_TMDS:
4445 case OUTPUT_LVDS:
4446 case OUTPUT_DP:
721b0821
BS		 4447 if (hash & 0x00c00000) {
4448 if (!(hash & (dcb->sorconf.link << 22)))
4449 return false;
1eb38100 4450 }
721b0821
BS		 4451 default:
4452 return true;
6ee73861 4453 }
6ee73861
BS		 4454}
4455
6ee73861 4456int
02e4f587
BS		 4457nouveau_bios_run_display_table(struct drm_device *dev, u16 type, int pclk,
4458 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 4459{
4460 /*
4461 * The display script table is located by the BIT 'U' table.
4462 *
4463 * It contains an array of pointers to various tables describing
4464 * a particular output type. The first 32-bits of the output
4465 * tables contains similar information to a DCB entry, and is
4466 * used to decide whether that particular table is suitable for
4467 * the output you want to access.
4468 *
4469 * The "record header length" field here seems to indicate the
4470 * offset of the first configuration entry in the output tables.
4471 * This is 10 on most cards I've seen, but 12 has been witnessed
4472 * on DP cards, and there's another script pointer within the
4473 * header.
4474 *
4475 * offset + 0 ( 8 bits): version
4476 * offset + 1 ( 8 bits): header length
4477 * offset + 2 ( 8 bits): record length
4478 * offset + 3 ( 8 bits): number of records
4479 * offset + 4 ( 8 bits): record header length
4480 * offset + 5 (16 bits): pointer to first output script table
4481 */
4482
4483 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 4484 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 4485 uint8_t *table = &bios->data[bios->display.script_table_ptr];
4486 uint8_t *otable = NULL;
4487 uint16_t script;
721b0821 4488 int i;
6ee73861
BS		 4489
4490 if (!bios->display.script_table_ptr) {
4491 NV_ERROR(dev, "No pointer to output script table\n");
4492 return 1;
4493 }
4494
4495 /*
4496 * Nothing useful has been in any of the pre-2.0 tables I've seen,
4497 * so until they are, we really don't need to care.
4498 */
4499 if (table[0] < 0x20)
4500 return 1;
4501
4502 if (table[0] != 0x20 && table[0] != 0x21) {
4503 NV_ERROR(dev, "Output script table version 0x%02x unknown\n",
4504 table[0]);
4505 return 1;
4506 }
4507
4508 /*
4509 * The output script tables describing a particular output type
4510 * look as follows:
4511 *
4512 * offset + 0 (32 bits): output this table matches (hash of DCB)
4513 * offset + 4 ( 8 bits): unknown
4514 * offset + 5 ( 8 bits): number of configurations
4515 * offset + 6 (16 bits): pointer to some script
4516 * offset + 8 (16 bits): pointer to some script
4517 *
4518 * headerlen == 10
4519 * offset + 10 : configuration 0
4520 *
4521 * headerlen == 12
4522 * offset + 10 : pointer to some script
4523 * offset + 12 : configuration 0
4524 *
4525 * Each config entry is as follows:
4526 *
4527 * offset + 0 (16 bits): unknown, assumed to be a match value
4528 * offset + 2 (16 bits): pointer to script table (clock set?)
4529 * offset + 4 (16 bits): pointer to script table (reset?)
4530 *
4531 * There doesn't appear to be a count value to say how many
4532 * entries exist in each script table, instead, a 0 value in
4533 * the first 16-bit word seems to indicate both the end of the
4534 * list and the default entry. The second 16-bit word in the
4535 * script tables is a pointer to the script to execute.
4536 */
4537
ef2bb506 4538 NV_DEBUG_KMS(dev, "Searching for output entry for %d %d %d\n",
6ee73861 4539 dcbent->type, dcbent->location, dcbent->or);
721b0821 4540 for (i = 0; i < table[3]; i++) {
f9f9f536 4541 otable = ROMPTR(dev, table[table[1] + (i * table[2])]);
721b0821
BS		 4542 if (otable && bios_encoder_match(dcbent, ROM32(otable[0])))
4543 break;
4544 }
4545
6ee73861 4546 if (!otable) {
54bf67de 4547 NV_DEBUG_KMS(dev, "failed to match any output table\n");
6ee73861
BS		 4548 return 1;
4549 }
4550
02e4f587 4551 if (pclk < -2 || pclk > 0) {
6ee73861
BS		 4552 /* Try to find matching script table entry */
4553 for (i = 0; i < otable[5]; i++) {
02e4f587 4554 if (ROM16(otable[table[4] + i*6]) == type)
6ee73861
BS		 4555 break;
4556 }
4557
4558 if (i == otable[5]) {
4559 NV_ERROR(dev, "Table 0x%04x not found for %d/%d, "
4560 "using first\n",
02e4f587 4561 type, dcbent->type, dcbent->or);
6ee73861
BS		 4562 i = 0;
4563 }
4564 }
4565
02e4f587 4566 if (pclk == 0) {
6ee73861
BS		 4567 script = ROM16(otable[6]);
4568 if (!script) {
ef2bb506 4569 NV_DEBUG_KMS(dev, "output script 0 not found\n");
6ee73861
BS		 4570 return 1;
4571 }
4572
45a68a07 4573 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 0\n", script);
02e4f587 4574 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4575 } else
02e4f587 4576 if (pclk == -1) {
6ee73861
BS		 4577 script = ROM16(otable[8]);
4578 if (!script) {
ef2bb506 4579 NV_DEBUG_KMS(dev, "output script 1 not found\n");
6ee73861
BS		 4580 return 1;
4581 }
4582
45a68a07 4583 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 1\n", script);
02e4f587 4584 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4585 } else
02e4f587 4586 if (pclk == -2) {
6ee73861
BS		 4587 if (table[4] >= 12)
4588 script = ROM16(otable[10]);
4589 else
4590 script = 0;
4591 if (!script) {
ef2bb506 4592 NV_DEBUG_KMS(dev, "output script 2 not found\n");
6ee73861
BS		 4593 return 1;
4594 }
4595
45a68a07 4596 NV_DEBUG_KMS(dev, "0x%04X: parsing output script 2\n", script);
02e4f587 4597 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4598 } else
02e4f587 4599 if (pclk > 0) {
6ee73861
BS		 4600 script = ROM16(otable[table[4] + i*6 + 2]);
4601 if (script)
02e4f587 4602 script = clkcmptable(bios, script, pclk);
6ee73861 4603 if (!script) {
54bf67de 4604 NV_DEBUG_KMS(dev, "clock script 0 not found\n");
6ee73861
BS		 4605 return 1;
4606 }
4607
45a68a07 4608 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 0\n", script);
02e4f587 4609 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861 4610 } else
02e4f587 4611 if (pclk < 0) {
6ee73861
BS		 4612 script = ROM16(otable[table[4] + i*6 + 4]);
4613 if (script)
02e4f587 4614 script = clkcmptable(bios, script, -pclk);
6ee73861 4615 if (!script) {
ef2bb506 4616 NV_DEBUG_KMS(dev, "clock script 1 not found\n");
6ee73861
BS		 4617 return 1;
4618 }
4619
45a68a07 4620 NV_DEBUG_KMS(dev, "0x%04X: parsing clock script 1\n", script);
02e4f587 4621 nouveau_bios_run_init_table(dev, script, dcbent, crtc);
6ee73861
BS		 4622 }
4623
4624 return 0;
4625}
4626
4627
4628int run_tmds_table(struct drm_device *dev, struct dcb_entry *dcbent, int head, int pxclk)
4629{
4630 /*
4631 * the pxclk parameter is in kHz
4632 *
4633 * This runs the TMDS regs setting code found on BIT bios cards
4634 *
4635 * For ffs(or) == 1 use the first table, for ffs(or) == 2 and
4636 * ffs(or) == 3, use the second.
4637 */
4638
4639 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4640 struct nvbios *bios = &dev_priv->vbios;
4641 int cv = bios->chip_version;
6ee73861
BS		 4642 uint16_t clktable = 0, scriptptr;
4643 uint32_t sel_clk_binding, sel_clk;
4644
4645 /* pre-nv17 off-chip tmds uses scripts, post nv17 doesn't */
4646 if (cv >= 0x17 && cv != 0x1a && cv != 0x20 &&
4647 dcbent->location != DCB_LOC_ON_CHIP)
4648 return 0;
4649
4650 switch (ffs(dcbent->or)) {
4651 case 1:
4652 clktable = bios->tmds.output0_script_ptr;
4653 break;
4654 case 2:
4655 case 3:
4656 clktable = bios->tmds.output1_script_ptr;
4657 break;
4658 }
4659
4660 if (!clktable) {
4661 NV_ERROR(dev, "Pixel clock comparison table not found\n");
4662 return -EINVAL;
4663 }
4664
4665 scriptptr = clkcmptable(bios, clktable, pxclk);
4666
4667 if (!scriptptr) {
4668 NV_ERROR(dev, "TMDS output init script not found\n");
4669 return -ENOENT;
4670 }
4671
4672 /* don't let script change pll->head binding */
4673 sel_clk_binding = bios_rd32(bios, NV_PRAMDAC_SEL_CLK) & 0x50000;
4674 run_digital_op_script(dev, scriptptr, dcbent, head, pxclk >= 165000);
4675 sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK) & ~0x50000;
4676 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, sel_clk | sel_clk_binding);
4677
4678 return 0;
4679}
4680
855a95e4
BS		 4681struct pll_mapping {
4682 u8 type;
4683 u32 reg;
4684};
4685
4686static struct pll_mapping nv04_pll_mapping[] = {
4687 { PLL_CORE , NV_PRAMDAC_NVPLL_COEFF },
4688 { PLL_MEMORY, NV_PRAMDAC_MPLL_COEFF },
4689 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4690 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4691 {}
4692};
4693
4694static struct pll_mapping nv40_pll_mapping[] = {
4695 { PLL_CORE , 0x004000 },
4696 { PLL_MEMORY, 0x004020 },
4697 { PLL_VPLL0 , NV_PRAMDAC_VPLL_COEFF },
4698 { PLL_VPLL1 , NV_RAMDAC_VPLL2 },
4699 {}
4700};
4701
4702static struct pll_mapping nv50_pll_mapping[] = {
4703 { PLL_CORE , 0x004028 },
4704 { PLL_SHADER, 0x004020 },
4705 { PLL_UNK03 , 0x004000 },
4706 { PLL_MEMORY, 0x004008 },
4707 { PLL_UNK40 , 0x00e810 },
4708 { PLL_UNK41 , 0x00e818 },
4709 { PLL_UNK42 , 0x00e824 },
4710 { PLL_VPLL0 , 0x614100 },
4711 { PLL_VPLL1 , 0x614900 },
4712 {}
4713};
4714
4715static struct pll_mapping nv84_pll_mapping[] = {
4716 { PLL_CORE , 0x004028 },
4717 { PLL_SHADER, 0x004020 },
4718 { PLL_MEMORY, 0x004008 },
d4cca9e1 4719 { PLL_VDEC , 0x004030 },
855a95e4
BS		 4720 { PLL_UNK41 , 0x00e818 },
4721 { PLL_VPLL0 , 0x614100 },
4722 { PLL_VPLL1 , 0x614900 },
4723 {}
4724};
4725
4726u32
4727get_pll_register(struct drm_device *dev, enum pll_types type)
4728{
4729 struct drm_nouveau_private *dev_priv = dev->dev_private;
4730 struct nvbios *bios = &dev_priv->vbios;
4731 struct pll_mapping *map;
4732 int i;
4733
4734 if (dev_priv->card_type < NV_40)
4735 map = nv04_pll_mapping;
4736 else
4737 if (dev_priv->card_type < NV_50)
4738 map = nv40_pll_mapping;
4739 else {
4740 u8 *plim = &bios->data[bios->pll_limit_tbl_ptr];
4741
56edd964 4742 if (plim[0] >= 0x30) {
855a95e4
BS		 4743 u8 *entry = plim + plim[1];
4744 for (i = 0; i < plim[3]; i++, entry += plim[2]) {
4745 if (entry[0] == type)
4746 return ROM32(entry[3]);
4747 }
4748
4749 return 0;
4750 }
4751
4752 if (dev_priv->chipset == 0x50)
4753 map = nv50_pll_mapping;
4754 else
4755 map = nv84_pll_mapping;
4756 }
4757
4758 while (map->reg) {
4759 if (map->type == type)
4760 return map->reg;
4761 map++;
4762 }
4763
4764 return 0;
4765}
4766
6ee73861
BS		 4767int get_pll_limits(struct drm_device *dev, uint32_t limit_match, struct pll_lims *pll_lim)
4768{
4769 /*
4770 * PLL limits table
4771 *
4772 * Version 0x10: NV30, NV31
4773 * One byte header (version), one record of 24 bytes
4774 * Version 0x11: NV36 - Not implemented
4775 * Seems to have same record style as 0x10, but 3 records rather than 1
4776 * Version 0x20: Found on Geforce 6 cards
4777 * Trivial 4 byte BIT header. 31 (0x1f) byte record length
4778 * Version 0x21: Found on Geforce 7, 8 and some Geforce 6 cards
4779 * 5 byte header, fifth byte of unknown purpose. 35 (0x23) byte record
4780 * length in general, some (integrated) have an extra configuration byte
4781 * Version 0x30: Found on Geforce 8, separates the register mapping
4782 * from the limits tables.
4783 */
4784
4785 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57
BS		 4786 struct nvbios *bios = &dev_priv->vbios;
4787 int cv = bios->chip_version, pllindex = 0;
6ee73861
BS		 4788 uint8_t pll_lim_ver = 0, headerlen = 0, recordlen = 0, entries = 0;
4789 uint32_t crystal_strap_mask, crystal_straps;
4790
4791 if (!bios->pll_limit_tbl_ptr) {
4792 if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
4793 cv >= 0x40) {
4794 NV_ERROR(dev, "Pointer to PLL limits table invalid\n");
4795 return -EINVAL;
4796 }
4797 } else
4798 pll_lim_ver = bios->data[bios->pll_limit_tbl_ptr];
4799
4800 crystal_strap_mask = 1 << 6;
4801 /* open coded dev->twoHeads test */
4802 if (cv > 0x10 && cv != 0x15 && cv != 0x1a && cv != 0x20)
4803 crystal_strap_mask |= 1 << 22;
4804 crystal_straps = nvReadEXTDEV(dev, NV_PEXTDEV_BOOT_0) &
4805 crystal_strap_mask;
4806
4807 switch (pll_lim_ver) {
4808 /*
4809 * We use version 0 to indicate a pre limit table bios (single stage
4810 * pll) and load the hard coded limits instead.
4811 */
4812 case 0:
4813 break;
4814 case 0x10:
4815 case 0x11:
4816 /*
4817 * Strictly v0x11 has 3 entries, but the last two don't seem
4818 * to get used.
4819 */
4820 headerlen = 1;
4821 recordlen = 0x18;
4822 entries = 1;
4823 pllindex = 0;
4824 break;
4825 case 0x20:
4826 case 0x21:
4827 case 0x30:
4828 case 0x40:
4829 headerlen = bios->data[bios->pll_limit_tbl_ptr + 1];
4830 recordlen = bios->data[bios->pll_limit_tbl_ptr + 2];
4831 entries = bios->data[bios->pll_limit_tbl_ptr + 3];
4832 break;
4833 default:
4834 NV_ERROR(dev, "PLL limits table revision 0x%X not currently "
4835 "supported\n", pll_lim_ver);
4836 return -ENOSYS;
4837 }
4838
4839 /* initialize all members to zero */
4840 memset(pll_lim, 0, sizeof(struct pll_lims));
4841
855a95e4
BS		 4842 /* if we were passed a type rather than a register, figure
4843 * out the register and store it
4844 */
4845 if (limit_match > PLL_MAX)
4846 pll_lim->reg = limit_match;
6f876986 4847 else {
855a95e4 4848 pll_lim->reg = get_pll_register(dev, limit_match);
6f876986
BS		 4849 if (!pll_lim->reg)
4850 return -ENOENT;
4851 }
855a95e4 4852
6ee73861
BS		 4853 if (pll_lim_ver == 0x10 || pll_lim_ver == 0x11) {
4854 uint8_t *pll_rec = &bios->data[bios->pll_limit_tbl_ptr + headerlen + recordlen * pllindex];
4855
4856 pll_lim->vco1.minfreq = ROM32(pll_rec[0]);
4857 pll_lim->vco1.maxfreq = ROM32(pll_rec[4]);
4858 pll_lim->vco2.minfreq = ROM32(pll_rec[8]);
4859 pll_lim->vco2.maxfreq = ROM32(pll_rec[12]);
4860 pll_lim->vco1.min_inputfreq = ROM32(pll_rec[16]);
4861 pll_lim->vco2.min_inputfreq = ROM32(pll_rec[20]);
4862 pll_lim->vco1.max_inputfreq = pll_lim->vco2.max_inputfreq = INT_MAX;
4863
4864 /* these values taken from nv30/31/36 */
4865 pll_lim->vco1.min_n = 0x1;
4866 if (cv == 0x36)
4867 pll_lim->vco1.min_n = 0x5;
4868 pll_lim->vco1.max_n = 0xff;
4869 pll_lim->vco1.min_m = 0x1;
4870 pll_lim->vco1.max_m = 0xd;
4871 pll_lim->vco2.min_n = 0x4;
4872 /*
4873 * On nv30, 31, 36 (i.e. all cards with two stage PLLs with this
4874 * table version (apart from nv35)), N2 is compared to
4875 * maxN2 (0x46) and 10 * maxM2 (0x4), so set maxN2 to 0x28 and
4876 * save a comparison
4877 */
4878 pll_lim->vco2.max_n = 0x28;
4879 if (cv == 0x30 || cv == 0x35)
4880 /* only 5 bits available for N2 on nv30/35 */
4881 pll_lim->vco2.max_n = 0x1f;
4882 pll_lim->vco2.min_m = 0x1;
4883 pll_lim->vco2.max_m = 0x4;
4884 pll_lim->max_log2p = 0x7;
4885 pll_lim->max_usable_log2p = 0x6;
4886 } else if (pll_lim_ver == 0x20 || pll_lim_ver == 0x21) {
4887 uint16_t plloffs = bios->pll_limit_tbl_ptr + headerlen;
6ee73861
BS		 4888 uint8_t *pll_rec;
4889 int i;
4890
4891 /*
4892 * First entry is default match, if nothing better. warn if
4893 * reg field nonzero
4894 */
4895 if (ROM32(bios->data[plloffs]))
4896 NV_WARN(dev, "Default PLL limit entry has non-zero "
4897 "register field\n");
4898
6ee73861 4899 for (i = 1; i < entries; i++)
855a95e4 4900 if (ROM32(bios->data[plloffs + recordlen * i]) == pll_lim->reg) {
6ee73861
BS		 4901 pllindex = i;
4902 break;
4903 }
4904
eadc69cc
EV		 4905 if ((dev_priv->card_type >= NV_50) && (pllindex == 0)) {
4906 NV_ERROR(dev, "Register 0x%08x not found in PLL "
4907 "limits table", pll_lim->reg);
4908 return -ENOENT;
4909 }
4910
6ee73861
BS		 4911 pll_rec = &bios->data[plloffs + recordlen * pllindex];
4912
4913 BIOSLOG(bios, "Loading PLL limits for reg 0x%08x\n",
855a95e4 4914 pllindex ? pll_lim->reg : 0);
6ee73861
BS		 4915
4916 /*
4917 * Frequencies are stored in tables in MHz, kHz are more
4918 * useful, so we convert.
4919 */
4920
4921 /* What output frequencies can each VCO generate? */
4922 pll_lim->vco1.minfreq = ROM16(pll_rec[4]) * 1000;
4923 pll_lim->vco1.maxfreq = ROM16(pll_rec[6]) * 1000;
4924 pll_lim->vco2.minfreq = ROM16(pll_rec[8]) * 1000;
4925 pll_lim->vco2.maxfreq = ROM16(pll_rec[10]) * 1000;
4926
4927 /* What input frequencies they accept (past the m-divider)? */
4928 pll_lim->vco1.min_inputfreq = ROM16(pll_rec[12]) * 1000;
4929 pll_lim->vco2.min_inputfreq = ROM16(pll_rec[14]) * 1000;
4930 pll_lim->vco1.max_inputfreq = ROM16(pll_rec[16]) * 1000;
4931 pll_lim->vco2.max_inputfreq = ROM16(pll_rec[18]) * 1000;
4932
4933 /* What values are accepted as multiplier and divider? */
4934 pll_lim->vco1.min_n = pll_rec[20];
4935 pll_lim->vco1.max_n = pll_rec[21];
4936 pll_lim->vco1.min_m = pll_rec[22];
4937 pll_lim->vco1.max_m = pll_rec[23];
4938 pll_lim->vco2.min_n = pll_rec[24];
4939 pll_lim->vco2.max_n = pll_rec[25];
4940 pll_lim->vco2.min_m = pll_rec[26];
4941 pll_lim->vco2.max_m = pll_rec[27];
4942
4943 pll_lim->max_usable_log2p = pll_lim->max_log2p = pll_rec[29];
4944 if (pll_lim->max_log2p > 0x7)
4945 /* pll decoding in nv_hw.c assumes never > 7 */
4946 NV_WARN(dev, "Max log2 P value greater than 7 (%d)\n",
4947 pll_lim->max_log2p);
4948 if (cv < 0x60)
4949 pll_lim->max_usable_log2p = 0x6;
4950 pll_lim->log2p_bias = pll_rec[30];
4951
4952 if (recordlen > 0x22)
4953 pll_lim->refclk = ROM32(pll_rec[31]);
4954
4955 if (recordlen > 0x23 && pll_rec[35])
4956 NV_WARN(dev,
4957 "Bits set in PLL configuration byte (%x)\n",
4958 pll_rec[35]);
4959
4960 /* C51 special not seen elsewhere */
4961 if (cv == 0x51 && !pll_lim->refclk) {
4962 uint32_t sel_clk = bios_rd32(bios, NV_PRAMDAC_SEL_CLK);
4963
855a95e4
BS		 4964 if ((pll_lim->reg == NV_PRAMDAC_VPLL_COEFF && sel_clk & 0x20) ||
4965 (pll_lim->reg == NV_RAMDAC_VPLL2 && sel_clk & 0x80)) {
6ee73861
BS		 4966 if (bios_idxprt_rd(bios, NV_CIO_CRX__COLOR, NV_CIO_CRE_CHIP_ID_INDEX) < 0xa3)
4967 pll_lim->refclk = 200000;
4968 else
4969 pll_lim->refclk = 25000;
4970 }
4971 }
4972 } else if (pll_lim_ver == 0x30) { /* ver 0x30 */
4973 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
4974 uint8_t *record = NULL;
4975 int i;
4976
4977 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 4978 pll_lim->reg);
6ee73861
BS		 4979
4980 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 4981 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 4982 record = &bios->data[ROM16(entry[1])];
4983 break;
4984 }
4985 }
4986
4987 if (!record) {
4988 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 4989 "limits table", pll_lim->reg);
6ee73861
BS		 4990 return -ENOENT;
4991 }
4992
4993 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
4994 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
4995 pll_lim->vco2.minfreq = ROM16(record[4]) * 1000;
4996 pll_lim->vco2.maxfreq = ROM16(record[6]) * 1000;
4997 pll_lim->vco1.min_inputfreq = ROM16(record[8]) * 1000;
4998 pll_lim->vco2.min_inputfreq = ROM16(record[10]) * 1000;
4999 pll_lim->vco1.max_inputfreq = ROM16(record[12]) * 1000;
5000 pll_lim->vco2.max_inputfreq = ROM16(record[14]) * 1000;
5001 pll_lim->vco1.min_n = record[16];
5002 pll_lim->vco1.max_n = record[17];
5003 pll_lim->vco1.min_m = record[18];
5004 pll_lim->vco1.max_m = record[19];
5005 pll_lim->vco2.min_n = record[20];
5006 pll_lim->vco2.max_n = record[21];
5007 pll_lim->vco2.min_m = record[22];
5008 pll_lim->vco2.max_m = record[23];
5009 pll_lim->max_usable_log2p = pll_lim->max_log2p = record[25];
5010 pll_lim->log2p_bias = record[27];
5011 pll_lim->refclk = ROM32(record[28]);
5012 } else if (pll_lim_ver) { /* ver 0x40 */
5013 uint8_t *entry = &bios->data[bios->pll_limit_tbl_ptr + headerlen];
5014 uint8_t *record = NULL;
5015 int i;
5016
5017 BIOSLOG(bios, "Loading PLL limits for register 0x%08x\n",
855a95e4 5018 pll_lim->reg);
6ee73861
BS		 5019
5020 for (i = 0; i < entries; i++, entry += recordlen) {
855a95e4 5021 if (ROM32(entry[3]) == pll_lim->reg) {
6ee73861
BS		 5022 record = &bios->data[ROM16(entry[1])];
5023 break;
5024 }
5025 }
5026
5027 if (!record) {
5028 NV_ERROR(dev, "Register 0x%08x not found in PLL "
855a95e4 5029 "limits table", pll_lim->reg);
6ee73861
BS		 5030 return -ENOENT;
5031 }
5032
5033 pll_lim->vco1.minfreq = ROM16(record[0]) * 1000;
5034 pll_lim->vco1.maxfreq = ROM16(record[2]) * 1000;
5035 pll_lim->vco1.min_inputfreq = ROM16(record[4]) * 1000;
5036 pll_lim->vco1.max_inputfreq = ROM16(record[6]) * 1000;
5037 pll_lim->vco1.min_m = record[8];
5038 pll_lim->vco1.max_m = record[9];
5039 pll_lim->vco1.min_n = record[10];
5040 pll_lim->vco1.max_n = record[11];
5041 pll_lim->min_p = record[12];
5042 pll_lim->max_p = record[13];
ce521846 5043 pll_lim->refclk = ROM16(entry[9]) * 1000;
6ee73861
BS		 5044 }
5045
5046 /*
5047 * By now any valid limit table ought to have set a max frequency for
5048 * vco1, so if it's zero it's either a pre limit table bios, or one
5049 * with an empty limit table (seen on nv18)
5050 */
5051 if (!pll_lim->vco1.maxfreq) {
5052 pll_lim->vco1.minfreq = bios->fminvco;
5053 pll_lim->vco1.maxfreq = bios->fmaxvco;
5054 pll_lim->vco1.min_inputfreq = 0;
5055 pll_lim->vco1.max_inputfreq = INT_MAX;
5056 pll_lim->vco1.min_n = 0x1;
5057 pll_lim->vco1.max_n = 0xff;
5058 pll_lim->vco1.min_m = 0x1;
5059 if (crystal_straps == 0) {
5060 /* nv05 does this, nv11 doesn't, nv10 unknown */
5061 if (cv < 0x11)
5062 pll_lim->vco1.min_m = 0x7;
5063 pll_lim->vco1.max_m = 0xd;
5064 } else {
5065 if (cv < 0x11)
5066 pll_lim->vco1.min_m = 0x8;
5067 pll_lim->vco1.max_m = 0xe;
5068 }
5069 if (cv < 0x17 || cv == 0x1a || cv == 0x20)
5070 pll_lim->max_log2p = 4;
5071 else
5072 pll_lim->max_log2p = 5;
5073 pll_lim->max_usable_log2p = pll_lim->max_log2p;
5074 }
5075
5076 if (!pll_lim->refclk)
5077 switch (crystal_straps) {
5078 case 0:
5079 pll_lim->refclk = 13500;
5080 break;
5081 case (1 << 6):
5082 pll_lim->refclk = 14318;
5083 break;
5084 case (1 << 22):
5085 pll_lim->refclk = 27000;
5086 break;
5087 case (1 << 22 | 1 << 6):
5088 pll_lim->refclk = 25000;
5089 break;
5090 }
5091
4c389f00
BS		 5092 NV_DEBUG(dev, "pll.vco1.minfreq: %d\n", pll_lim->vco1.minfreq);
5093 NV_DEBUG(dev, "pll.vco1.maxfreq: %d\n", pll_lim->vco1.maxfreq);
5094 NV_DEBUG(dev, "pll.vco1.min_inputfreq: %d\n", pll_lim->vco1.min_inputfreq);
5095 NV_DEBUG(dev, "pll.vco1.max_inputfreq: %d\n", pll_lim->vco1.max_inputfreq);
5096 NV_DEBUG(dev, "pll.vco1.min_n: %d\n", pll_lim->vco1.min_n);
5097 NV_DEBUG(dev, "pll.vco1.max_n: %d\n", pll_lim->vco1.max_n);
5098 NV_DEBUG(dev, "pll.vco1.min_m: %d\n", pll_lim->vco1.min_m);
5099 NV_DEBUG(dev, "pll.vco1.max_m: %d\n", pll_lim->vco1.max_m);
5100 if (pll_lim->vco2.maxfreq) {
5101 NV_DEBUG(dev, "pll.vco2.minfreq: %d\n", pll_lim->vco2.minfreq);
5102 NV_DEBUG(dev, "pll.vco2.maxfreq: %d\n", pll_lim->vco2.maxfreq);
5103 NV_DEBUG(dev, "pll.vco2.min_inputfreq: %d\n", pll_lim->vco2.min_inputfreq);
5104 NV_DEBUG(dev, "pll.vco2.max_inputfreq: %d\n", pll_lim->vco2.max_inputfreq);
5105 NV_DEBUG(dev, "pll.vco2.min_n: %d\n", pll_lim->vco2.min_n);
5106 NV_DEBUG(dev, "pll.vco2.max_n: %d\n", pll_lim->vco2.max_n);
5107 NV_DEBUG(dev, "pll.vco2.min_m: %d\n", pll_lim->vco2.min_m);
5108 NV_DEBUG(dev, "pll.vco2.max_m: %d\n", pll_lim->vco2.max_m);
5109 }
5110 if (!pll_lim->max_p) {
5111 NV_DEBUG(dev, "pll.max_log2p: %d\n", pll_lim->max_log2p);
5112 NV_DEBUG(dev, "pll.log2p_bias: %d\n", pll_lim->log2p_bias);
5113 } else {
5114 NV_DEBUG(dev, "pll.min_p: %d\n", pll_lim->min_p);
5115 NV_DEBUG(dev, "pll.max_p: %d\n", pll_lim->max_p);
5116 }
5117 NV_DEBUG(dev, "pll.refclk: %d\n", pll_lim->refclk);
6ee73861
BS		 5118
5119 return 0;
5120}
5121
5122static void parse_bios_version(struct drm_device *dev, struct nvbios *bios, uint16_t offset)
5123{
5124 /*
5125 * offset + 0 (8 bits): Micro version
5126 * offset + 1 (8 bits): Minor version
5127 * offset + 2 (8 bits): Chip version
5128 * offset + 3 (8 bits): Major version
5129 */
5130
5131 bios->major_version = bios->data[offset + 3];
04a39c57 5132 bios->chip_version = bios->data[offset + 2];
6ee73861
BS		 5133 NV_TRACE(dev, "Bios version %02x.%02x.%02x.%02x\n",
5134 bios->data[offset + 3], bios->data[offset + 2],
5135 bios->data[offset + 1], bios->data[offset]);
5136}
5137
5138static void parse_script_table_pointers(struct nvbios *bios, uint16_t offset)
5139{
5140 /*
5141 * Parses the init table segment for pointers used in script execution.
5142 *
5143 * offset + 0 (16 bits): init script tables pointer
5144 * offset + 2 (16 bits): macro index table pointer
5145 * offset + 4 (16 bits): macro table pointer
5146 * offset + 6 (16 bits): condition table pointer
5147 * offset + 8 (16 bits): io condition table pointer
5148 * offset + 10 (16 bits): io flag condition table pointer
5149 * offset + 12 (16 bits): init function table pointer
5150 */
5151
5152 bios->init_script_tbls_ptr = ROM16(bios->data[offset]);
5153 bios->macro_index_tbl_ptr = ROM16(bios->data[offset + 2]);
5154 bios->macro_tbl_ptr = ROM16(bios->data[offset + 4]);
5155 bios->condition_tbl_ptr = ROM16(bios->data[offset + 6]);
5156 bios->io_condition_tbl_ptr = ROM16(bios->data[offset + 8]);
5157 bios->io_flag_condition_tbl_ptr = ROM16(bios->data[offset + 10]);
5158 bios->init_function_tbl_ptr = ROM16(bios->data[offset + 12]);
5159}
5160
5161static int parse_bit_A_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5162{
5163 /*
5164 * Parses the load detect values for g80 cards.
5165 *
5166 * offset + 0 (16 bits): loadval table pointer
5167 */
5168
5169 uint16_t load_table_ptr;
5170 uint8_t version, headerlen, entrylen, num_entries;
5171
5172 if (bitentry->length != 3) {
5173 NV_ERROR(dev, "Do not understand BIT A table\n");
5174 return -EINVAL;
5175 }
5176
5177 load_table_ptr = ROM16(bios->data[bitentry->offset]);
5178
5179 if (load_table_ptr == 0x0) {
1562ffde 5180 NV_DEBUG(dev, "Pointer to BIT loadval table invalid\n");
6ee73861
BS		 5181 return -EINVAL;
5182 }
5183
5184 version = bios->data[load_table_ptr];
5185
5186 if (version != 0x10) {
5187 NV_ERROR(dev, "BIT loadval table version %d.%d not supported\n",
5188 version >> 4, version & 0xF);
5189 return -ENOSYS;
5190 }
5191
5192 headerlen = bios->data[load_table_ptr + 1];
5193 entrylen = bios->data[load_table_ptr + 2];
5194 num_entries = bios->data[load_table_ptr + 3];
5195
5196 if (headerlen != 4 || entrylen != 4 || num_entries != 2) {
5197 NV_ERROR(dev, "Do not understand BIT loadval table\n");
5198 return -EINVAL;
5199 }
5200
5201 /* First entry is normal dac, 2nd tv-out perhaps? */
04a39c57 5202 bios->dactestval = ROM32(bios->data[load_table_ptr + headerlen]) & 0x3ff;
6ee73861
BS		 5203
5204 return 0;
5205}
5206
5207static int parse_bit_C_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5208{
5209 /*
5210 * offset + 8 (16 bits): PLL limits table pointer
5211 *
5212 * There's more in here, but that's unknown.
5213 */
5214
5215 if (bitentry->length < 10) {
5216 NV_ERROR(dev, "Do not understand BIT C table\n");
5217 return -EINVAL;
5218 }
5219
5220 bios->pll_limit_tbl_ptr = ROM16(bios->data[bitentry->offset + 8]);
5221
5222 return 0;
5223}
5224
5225static int parse_bit_display_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5226{
5227 /*
5228 * Parses the flat panel table segment that the bit entry points to.
5229 * Starting at bitentry->offset:
5230 *
5231 * offset + 0 (16 bits): ??? table pointer - seems to have 18 byte
5232 * records beginning with a freq.
5233 * offset + 2 (16 bits): mode table pointer
5234 */
5235
5236 if (bitentry->length != 4) {
5237 NV_ERROR(dev, "Do not understand BIT display table\n");
5238 return -EINVAL;
5239 }
5240
5241 bios->fp.fptablepointer = ROM16(bios->data[bitentry->offset + 2]);
5242
5243 return 0;
5244}
5245
5246static int parse_bit_init_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5247{
5248 /*
5249 * Parses the init table segment that the bit entry points to.
5250 *
5251 * See parse_script_table_pointers for layout
5252 */
5253
5254 if (bitentry->length < 14) {
5255 NV_ERROR(dev, "Do not understand init table\n");
5256 return -EINVAL;
5257 }
5258
5259 parse_script_table_pointers(bios, bitentry->offset);
5260
5261 if (bitentry->length >= 16)
5262 bios->some_script_ptr = ROM16(bios->data[bitentry->offset + 14]);
5263 if (bitentry->length >= 18)
5264 bios->init96_tbl_ptr = ROM16(bios->data[bitentry->offset + 16]);
5265
5266 return 0;
5267}
5268
5269static int parse_bit_i_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5270{
5271 /*
5272 * BIT 'i' (info?) table
5273 *
5274 * offset + 0 (32 bits): BIOS version dword (as in B table)
5275 * offset + 5 (8 bits): BIOS feature byte (same as for BMP?)
5276 * offset + 13 (16 bits): pointer to table containing DAC load
5277 * detection comparison values
5278 *
5279 * There's other things in the table, purpose unknown
5280 */
5281
5282 uint16_t daccmpoffset;
5283 uint8_t dacver, dacheaderlen;
5284
5285 if (bitentry->length < 6) {
5286 NV_ERROR(dev, "BIT i table too short for needed information\n");
5287 return -EINVAL;
5288 }
5289
5290 parse_bios_version(dev, bios, bitentry->offset);
5291
5292 /*
5293 * bit 4 seems to indicate a mobile bios (doesn't suffer from BMP's
5294 * Quadro identity crisis), other bits possibly as for BMP feature byte
5295 */
5296 bios->feature_byte = bios->data[bitentry->offset + 5];
5297 bios->is_mobile = bios->feature_byte & FEATURE_MOBILE;
5298
5299 if (bitentry->length < 15) {
5300 NV_WARN(dev, "BIT i table not long enough for DAC load "
5301 "detection comparison table\n");
5302 return -EINVAL;
5303 }
5304
5305 daccmpoffset = ROM16(bios->data[bitentry->offset + 13]);
5306
5307 /* doesn't exist on g80 */
5308 if (!daccmpoffset)
5309 return 0;
5310
5311 /*
5312 * The first value in the table, following the header, is the
5313 * comparison value, the second entry is a comparison value for
5314 * TV load detection.
5315 */
5316
5317 dacver = bios->data[daccmpoffset];
5318 dacheaderlen = bios->data[daccmpoffset + 1];
5319
5320 if (dacver != 0x00 && dacver != 0x10) {
5321 NV_WARN(dev, "DAC load detection comparison table version "
5322 "%d.%d not known\n", dacver >> 4, dacver & 0xf);
5323 return -ENOSYS;
5324 }
5325
04a39c57
BS		 5326 bios->dactestval = ROM32(bios->data[daccmpoffset + dacheaderlen]);
5327 bios->tvdactestval = ROM32(bios->data[daccmpoffset + dacheaderlen + 4]);
6ee73861
BS		 5328
5329 return 0;
5330}
5331
5332static int parse_bit_lvds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5333{
5334 /*
5335 * Parses the LVDS table segment that the bit entry points to.
5336 * Starting at bitentry->offset:
5337 *
5338 * offset + 0 (16 bits): LVDS strap xlate table pointer
5339 */
5340
5341 if (bitentry->length != 2) {
5342 NV_ERROR(dev, "Do not understand BIT LVDS table\n");
5343 return -EINVAL;
5344 }
5345
5346 /*
5347 * No idea if it's still called the LVDS manufacturer table, but
5348 * the concept's close enough.
5349 */
5350 bios->fp.lvdsmanufacturerpointer = ROM16(bios->data[bitentry->offset]);
5351
5352 return 0;
5353}
5354
5355static int
5356parse_bit_M_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5357 struct bit_entry *bitentry)
5358{
5359 /*
5360 * offset + 2 (8 bits): number of options in an
5361 * INIT_RAM_RESTRICT_ZM_REG_GROUP opcode option set
5362 * offset + 3 (16 bits): pointer to strap xlate table for RAM
5363 * restrict option selection
5364 *
5365 * There's a bunch of bits in this table other than the RAM restrict
5366 * stuff that we don't use - their use currently unknown
5367 */
5368
6ee73861
BS		 5369 /*
5370 * Older bios versions don't have a sufficiently long table for
5371 * what we want
5372 */
5373 if (bitentry->length < 0x5)
5374 return 0;
5375
4709bff0 5376 if (bitentry->version < 2) {
37383650
MK		 5377 bios->ram_restrict_group_count = bios->data[bitentry->offset + 2];
5378 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 3]);
6ee73861 5379 } else {
37383650
MK		 5380 bios->ram_restrict_group_count = bios->data[bitentry->offset + 0];
5381 bios->ram_restrict_tbl_ptr = ROM16(bios->data[bitentry->offset + 1]);
6ee73861
BS		 5382 }
5383
6ee73861
BS		 5384 return 0;
5385}
5386
5387static int parse_bit_tmds_tbl_entry(struct drm_device *dev, struct nvbios *bios, struct bit_entry *bitentry)
5388{
5389 /*
5390 * Parses the pointer to the TMDS table
5391 *
5392 * Starting at bitentry->offset:
5393 *
5394 * offset + 0 (16 bits): TMDS table pointer
5395 *
5396 * The TMDS table is typically found just before the DCB table, with a
5397 * characteristic signature of 0x11,0x13 (1.1 being version, 0x13 being
5398 * length?)
5399 *
5400 * At offset +7 is a pointer to a script, which I don't know how to
5401 * run yet.
5402 * At offset +9 is a pointer to another script, likewise
5403 * Offset +11 has a pointer to a table where the first word is a pxclk
5404 * frequency and the second word a pointer to a script, which should be
5405 * run if the comparison pxclk frequency is less than the pxclk desired.
5406 * This repeats for decreasing comparison frequencies
5407 * Offset +13 has a pointer to a similar table
5408 * The selection of table (and possibly +7/+9 script) is dictated by
5409 * "or" from the DCB.
5410 */
5411
5412 uint16_t tmdstableptr, script1, script2;
5413
5414 if (bitentry->length != 2) {
5415 NV_ERROR(dev, "Do not understand BIT TMDS table\n");
5416 return -EINVAL;
5417 }
5418
5419 tmdstableptr = ROM16(bios->data[bitentry->offset]);
98720bf4 5420 if (!tmdstableptr) {
6ee73861
BS		 5421 NV_ERROR(dev, "Pointer to TMDS table invalid\n");
5422 return -EINVAL;
5423 }
5424
98720bf4
BS		 5425 NV_INFO(dev, "TMDS table version %d.%d\n",
5426 bios->data[tmdstableptr] >> 4, bios->data[tmdstableptr] & 0xf);
5427
6ee73861 5428 /* nv50+ has v2.0, but we don't parse it atm */
98720bf4 5429 if (bios->data[tmdstableptr] != 0x11)
6ee73861 5430 return -ENOSYS;
6ee73861
BS		 5431
5432 /*
5433 * These two scripts are odd: they don't seem to get run even when
5434 * they are not stubbed.
5435 */
5436 script1 = ROM16(bios->data[tmdstableptr + 7]);
5437 script2 = ROM16(bios->data[tmdstableptr + 9]);
5438 if (bios->data[script1] != 'q' || bios->data[script2] != 'q')
5439 NV_WARN(dev, "TMDS table script pointers not stubbed\n");
5440
5441 bios->tmds.output0_script_ptr = ROM16(bios->data[tmdstableptr + 11]);
5442 bios->tmds.output1_script_ptr = ROM16(bios->data[tmdstableptr + 13]);
5443
5444 return 0;
5445}
5446
5447static int
5448parse_bit_U_tbl_entry(struct drm_device *dev, struct nvbios *bios,
5449 struct bit_entry *bitentry)
5450{
5451 /*
5452 * Parses the pointer to the G80 output script tables
5453 *
5454 * Starting at bitentry->offset:
5455 *
5456 * offset + 0 (16 bits): output script table pointer
5457 */
5458
5459 uint16_t outputscripttableptr;
5460
5461 if (bitentry->length != 3) {
5462 NV_ERROR(dev, "Do not understand BIT U table\n");
5463 return -EINVAL;
5464 }
5465
5466 outputscripttableptr = ROM16(bios->data[bitentry->offset]);
5467 bios->display.script_table_ptr = outputscripttableptr;
5468 return 0;
5469}
5470
6ee73861
BS		 5471struct bit_table {
5472 const char id;
5473 int (* const parse_fn)(struct drm_device *, struct nvbios *, struct bit_entry *);
5474};
5475
5476#define BIT_TABLE(id, funcid) ((struct bit_table){ id, parse_bit_##funcid##_tbl_entry })
5477
4709bff0
BS		 5478int
5479bit_table(struct drm_device *dev, u8 id, struct bit_entry *bit)
5480{
5481 struct drm_nouveau_private *dev_priv = dev->dev_private;
5482 struct nvbios *bios = &dev_priv->vbios;
5483 u8 entries, *entry;
5484
5485 entries = bios->data[bios->offset + 10];
5486 entry = &bios->data[bios->offset + 12];
5487 while (entries--) {
5488 if (entry[0] == id) {
5489 bit->id = entry[0];
5490 bit->version = entry[1];
5491 bit->length = ROM16(entry[2]);
5492 bit->offset = ROM16(entry[4]);
f9f9f536 5493 bit->data = ROMPTR(dev, entry[4]);
4709bff0
BS		 5494 return 0;
5495 }
5496
5497 entry += bios->data[bios->offset + 9];
5498 }
5499
5500 return -ENOENT;
5501}
5502
6ee73861
BS		 5503static int
5504parse_bit_table(struct nvbios *bios, const uint16_t bitoffset,
5505 struct bit_table *table)
5506{
5507 struct drm_device *dev = bios->dev;
6ee73861
BS		 5508 struct bit_entry bitentry;
5509
4709bff0 5510 if (bit_table(dev, table->id, &bitentry) == 0)
6ee73861 5511 return table->parse_fn(dev, bios, &bitentry);
6ee73861
BS		 5512
5513 NV_INFO(dev, "BIT table '%c' not found\n", table->id);
5514 return -ENOSYS;
5515}
5516
5517static int
5518parse_bit_structure(struct nvbios *bios, const uint16_t bitoffset)
5519{
5520 int ret;
5521
5522 /*
5523 * The only restriction on parsing order currently is having 'i' first
5524 * for use of bios->*_version or bios->feature_byte while parsing;
5525 * functions shouldn't be actually *doing* anything apart from pulling
5526 * data from the image into the bios struct, thus no interdependencies
5527 */
5528 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('i', i));
5529 if (ret) /* info? */
5530 return ret;
5531 if (bios->major_version >= 0x60) /* g80+ */
5532 parse_bit_table(bios, bitoffset, &BIT_TABLE('A', A));
5533 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('C', C));
5534 if (ret)
5535 return ret;
5536 parse_bit_table(bios, bitoffset, &BIT_TABLE('D', display));
5537 ret = parse_bit_table(bios, bitoffset, &BIT_TABLE('I', init));
5538 if (ret)
5539 return ret;
5540 parse_bit_table(bios, bitoffset, &BIT_TABLE('M', M)); /* memory? */
5541 parse_bit_table(bios, bitoffset, &BIT_TABLE('L', lvds));
5542 parse_bit_table(bios, bitoffset, &BIT_TABLE('T', tmds));
5543 parse_bit_table(bios, bitoffset, &BIT_TABLE('U', U));
6ee73861
BS		 5544
5545 return 0;
5546}
5547
5548static int parse_bmp_structure(struct drm_device *dev, struct nvbios *bios, unsigned int offset)
5549{
5550 /*
5551 * Parses the BMP structure for useful things, but does not act on them
5552 *
5553 * offset + 5: BMP major version
5554 * offset + 6: BMP minor version
5555 * offset + 9: BMP feature byte
5556 * offset + 10: BCD encoded BIOS version
5557 *
5558 * offset + 18: init script table pointer (for bios versions < 5.10h)
5559 * offset + 20: extra init script table pointer (for bios
5560 * versions < 5.10h)
5561 *
5562 * offset + 24: memory init table pointer (used on early bios versions)
5563 * offset + 26: SDR memory sequencing setup data table
5564 * offset + 28: DDR memory sequencing setup data table
5565 *
5566 * offset + 54: index of I2C CRTC pair to use for CRT output
5567 * offset + 55: index of I2C CRTC pair to use for TV output
5568 * offset + 56: index of I2C CRTC pair to use for flat panel output
5569 * offset + 58: write CRTC index for I2C pair 0
5570 * offset + 59: read CRTC index for I2C pair 0
5571 * offset + 60: write CRTC index for I2C pair 1
5572 * offset + 61: read CRTC index for I2C pair 1
5573 *
5574 * offset + 67: maximum internal PLL frequency (single stage PLL)
5575 * offset + 71: minimum internal PLL frequency (single stage PLL)
5576 *
5577 * offset + 75: script table pointers, as described in
5578 * parse_script_table_pointers
5579 *
5580 * offset + 89: TMDS single link output A table pointer
5581 * offset + 91: TMDS single link output B table pointer
5582 * offset + 95: LVDS single link output A table pointer
5583 * offset + 105: flat panel timings table pointer
5584 * offset + 107: flat panel strapping translation table pointer
5585 * offset + 117: LVDS manufacturer panel config table pointer
5586 * offset + 119: LVDS manufacturer strapping translation table pointer
5587 *
5588 * offset + 142: PLL limits table pointer
5589 *
5590 * offset + 156: minimum pixel clock for LVDS dual link
5591 */
5592
5593 uint8_t *bmp = &bios->data[offset], bmp_version_major, bmp_version_minor;
5594 uint16_t bmplength;
5595 uint16_t legacy_scripts_offset, legacy_i2c_offset;
5596
5597 /* load needed defaults in case we can't parse this info */
7f245b20
BS		 5598 bios->dcb.i2c[0].write = NV_CIO_CRE_DDC_WR__INDEX;
5599 bios->dcb.i2c[0].read = NV_CIO_CRE_DDC_STATUS__INDEX;
5600 bios->dcb.i2c[1].write = NV_CIO_CRE_DDC0_WR__INDEX;
5601 bios->dcb.i2c[1].read = NV_CIO_CRE_DDC0_STATUS__INDEX;
04a39c57 5602 bios->digital_min_front_porch = 0x4b;
6ee73861
BS		 5603 bios->fmaxvco = 256000;
5604 bios->fminvco = 128000;
5605 bios->fp.duallink_transition_clk = 90000;
5606
5607 bmp_version_major = bmp[5];
5608 bmp_version_minor = bmp[6];
5609
5610 NV_TRACE(dev, "BMP version %d.%d\n",
5611 bmp_version_major, bmp_version_minor);
5612
5613 /*
5614 * Make sure that 0x36 is blank and can't be mistaken for a DCB
5615 * pointer on early versions
5616 */
5617 if (bmp_version_major < 5)
5618 *(uint16_t *)&bios->data[0x36] = 0;
5619
5620 /*
5621 * Seems that the minor version was 1 for all major versions prior
5622 * to 5. Version 6 could theoretically exist, but I suspect BIT
5623 * happened instead.
5624 */
5625 if ((bmp_version_major < 5 && bmp_version_minor != 1) || bmp_version_major > 5) {
5626 NV_ERROR(dev, "You have an unsupported BMP version. "
5627 "Please send in your bios\n");
5628 return -ENOSYS;
5629 }
5630
5631 if (bmp_version_major == 0)
5632 /* nothing that's currently useful in this version */
5633 return 0;
5634 else if (bmp_version_major == 1)
5635 bmplength = 44; /* exact for 1.01 */
5636 else if (bmp_version_major == 2)
5637 bmplength = 48; /* exact for 2.01 */
5638 else if (bmp_version_major == 3)
5639 bmplength = 54;
5640 /* guessed - mem init tables added in this version */
5641 else if (bmp_version_major == 4 || bmp_version_minor < 0x1)
5642 /* don't know if 5.0 exists... */
5643 bmplength = 62;
5644 /* guessed - BMP I2C indices added in version 4*/
5645 else if (bmp_version_minor < 0x6)
5646 bmplength = 67; /* exact for 5.01 */
5647 else if (bmp_version_minor < 0x10)
5648 bmplength = 75; /* exact for 5.06 */
5649 else if (bmp_version_minor == 0x10)
5650 bmplength = 89; /* exact for 5.10h */
5651 else if (bmp_version_minor < 0x14)
5652 bmplength = 118; /* exact for 5.11h */
5653 else if (bmp_version_minor < 0x24)
5654 /*
5655 * Not sure of version where pll limits came in;
5656 * certainly exist by 0x24 though.
5657 */
5658 /* length not exact: this is long enough to get lvds members */
5659 bmplength = 123;
5660 else if (bmp_version_minor < 0x27)
5661 /*
5662 * Length not exact: this is long enough to get pll limit
5663 * member
5664 */
5665 bmplength = 144;
5666 else
5667 /*
5668 * Length not exact: this is long enough to get dual link
5669 * transition clock.
5670 */
5671 bmplength = 158;
5672
5673 /* checksum */
5674 if (nv_cksum(bmp, 8)) {
5675 NV_ERROR(dev, "Bad BMP checksum\n");
5676 return -EINVAL;
5677 }
5678
5679 /*
5680 * Bit 4 seems to indicate either a mobile bios or a quadro card --
5681 * mobile behaviour consistent (nv11+), quadro only seen nv18gl-nv36gl
5682 * (not nv10gl), bit 5 that the flat panel tables are present, and
5683 * bit 6 a tv bios.
5684 */
5685 bios->feature_byte = bmp[9];
5686
5687 parse_bios_version(dev, bios, offset + 10);
5688
5689 if (bmp_version_major < 5 || bmp_version_minor < 0x10)
5690 bios->old_style_init = true;
5691 legacy_scripts_offset = 18;
5692 if (bmp_version_major < 2)
5693 legacy_scripts_offset -= 4;
5694 bios->init_script_tbls_ptr = ROM16(bmp[legacy_scripts_offset]);
5695 bios->extra_init_script_tbl_ptr = ROM16(bmp[legacy_scripts_offset + 2]);
5696
5697 if (bmp_version_major > 2) { /* appears in BMP 3 */
5698 bios->legacy.mem_init_tbl_ptr = ROM16(bmp[24]);
5699 bios->legacy.sdr_seq_tbl_ptr = ROM16(bmp[26]);
5700 bios->legacy.ddr_seq_tbl_ptr = ROM16(bmp[28]);
5701 }
5702
5703 legacy_i2c_offset = 0x48; /* BMP version 2 & 3 */
5704 if (bmplength > 61)
5705 legacy_i2c_offset = offset + 54;
5706 bios->legacy.i2c_indices.crt = bios->data[legacy_i2c_offset];
5707 bios->legacy.i2c_indices.tv = bios->data[legacy_i2c_offset + 1];
5708 bios->legacy.i2c_indices.panel = bios->data[legacy_i2c_offset + 2];
3af76454
FJ		 5709 if (bios->data[legacy_i2c_offset + 4])
5710 bios->dcb.i2c[0].write = bios->data[legacy_i2c_offset + 4];
5711 if (bios->data[legacy_i2c_offset + 5])
5712 bios->dcb.i2c[0].read = bios->data[legacy_i2c_offset + 5];
5713 if (bios->data[legacy_i2c_offset + 6])
5714 bios->dcb.i2c[1].write = bios->data[legacy_i2c_offset + 6];
5715 if (bios->data[legacy_i2c_offset + 7])
5716 bios->dcb.i2c[1].read = bios->data[legacy_i2c_offset + 7];
6ee73861
BS		 5717
5718 if (bmplength > 74) {
5719 bios->fmaxvco = ROM32(bmp[67]);
5720 bios->fminvco = ROM32(bmp[71]);
5721 }
5722 if (bmplength > 88)
5723 parse_script_table_pointers(bios, offset + 75);
5724 if (bmplength > 94) {
5725 bios->tmds.output0_script_ptr = ROM16(bmp[89]);
5726 bios->tmds.output1_script_ptr = ROM16(bmp[91]);
5727 /*
5728 * Never observed in use with lvds scripts, but is reused for
5729 * 18/24 bit panel interface default for EDID equipped panels
5730 * (if_is_24bit not set directly to avoid any oscillation).
5731 */
5732 bios->legacy.lvds_single_a_script_ptr = ROM16(bmp[95]);
5733 }
5734 if (bmplength > 108) {
5735 bios->fp.fptablepointer = ROM16(bmp[105]);
5736 bios->fp.fpxlatetableptr = ROM16(bmp[107]);
5737 bios->fp.xlatwidth = 1;
5738 }
5739 if (bmplength > 120) {
5740 bios->fp.lvdsmanufacturerpointer = ROM16(bmp[117]);
5741 bios->fp.fpxlatemanufacturertableptr = ROM16(bmp[119]);
5742 }
5743 if (bmplength > 143)
5744 bios->pll_limit_tbl_ptr = ROM16(bmp[142]);
5745
5746 if (bmplength > 157)
5747 bios->fp.duallink_transition_clk = ROM16(bmp[156]) * 10;
5748
5749 return 0;
5750}
5751
5752static uint16_t findstr(uint8_t *data, int n, const uint8_t *str, int len)
5753{
5754 int i, j;
5755
5756 for (i = 0; i <= (n - len); i++) {
5757 for (j = 0; j < len; j++)
5758 if (data[i + j] != str[j])
5759 break;
5760 if (j == len)
5761 return i;
5762 }
5763
5764 return 0;
5765}
5766
6ee73861
BS		 5767static struct dcb_gpio_entry *
5768new_gpio_entry(struct nvbios *bios)
5769{
e49f70f7 5770 struct drm_device *dev = bios->dev;
7f245b20 5771 struct dcb_gpio_table *gpio = &bios->dcb.gpio;
6ee73861 5772
e49f70f7
BS		 5773 if (gpio->entries >= DCB_MAX_NUM_GPIO_ENTRIES) {
5774 NV_ERROR(dev, "exceeded maximum number of gpio entries!!\n");
5775 return NULL;
5776 }
5777
6ee73861
BS		 5778 return &gpio->entry[gpio->entries++];
5779}
5780
5781struct dcb_gpio_entry *
5782nouveau_bios_gpio_entry(struct drm_device *dev, enum dcb_gpio_tag tag)
5783{
5784 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5785 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5786 int i;
5787
7f245b20
BS		 5788 for (i = 0; i < bios->dcb.gpio.entries; i++) {
5789 if (bios->dcb.gpio.entry[i].tag != tag)
6ee73861
BS		 5790 continue;
5791
7f245b20 5792 return &bios->dcb.gpio.entry[i];
6ee73861
BS		 5793 }
5794
5795 return NULL;
5796}
5797
6ee73861
BS		 5798static void
5799parse_dcb_gpio_table(struct nvbios *bios)
5800{
5801 struct drm_device *dev = bios->dev;
e49f70f7
BS		 5802 struct dcb_gpio_entry *e;
5803 u8 headerlen, entries, recordlen;
5804 u8 *dcb, *gpio = NULL, *entry;
6ee73861
BS		 5805 int i;
5806
f9f9f536 5807 dcb = ROMPTR(dev, bios->data[0x36]);
e49f70f7 5808 if (dcb[0] >= 0x30) {
f9f9f536 5809 gpio = ROMPTR(dev, dcb[10]);
e49f70f7
BS		 5810 if (!gpio)
5811 goto no_table;
6ee73861 5812
e49f70f7
BS		 5813 headerlen = gpio[1];
5814 entries = gpio[2];
5815 recordlen = gpio[3];
5816 } else
5e6a7443 5817 if (dcb[0] >= 0x22 && dcb[-1] >= 0x13) {
f9f9f536 5818 gpio = ROMPTR(dev, dcb[-15]);
e49f70f7
BS		 5819 if (!gpio)
5820 goto no_table;
5821
5822 headerlen = 3;
5823 entries = gpio[2];
5824 recordlen = gpio[1];
5e6a7443
FJ		 5825 } else
5826 if (dcb[0] >= 0x22) {
5827 /* No GPIO table present, parse the TVDAC GPIO data. */
5828 uint8_t *tvdac_gpio = &dcb[-5];
6ee73861 5829
5e6a7443
FJ		 5830 if (tvdac_gpio[0] & 1) {
5831 e = new_gpio_entry(bios);
5832 e->tag = DCB_GPIO_TVDAC0;
5833 e->line = tvdac_gpio[1] >> 4;
85a2a365
BS		 5834 e->state[0] = !!(tvdac_gpio[0] & 2);
5835 e->state[1] = !e->state[0];
6ee73861
BS		 5836 }
5837
5e6a7443 5838 goto no_table;
e49f70f7
BS		 5839 } else {
5840 NV_DEBUG(dev, "no/unknown gpio table on DCB 0x%02x\n", dcb[0]);
5841 goto no_table;
5842 }
6ee73861 5843
e49f70f7
BS		 5844 entry = gpio + headerlen;
5845 for (i = 0; i < entries; i++, entry += recordlen) {
5846 e = new_gpio_entry(bios);
5847 if (!e)
5848 break;
6ee73861 5849
e49f70f7
BS		 5850 if (gpio[0] < 0x40) {
5851 e->entry = ROM16(entry[0]);
5852 e->tag = (e->entry & 0x07e0) >> 5;
5853 if (e->tag == 0x3f) {
5854 bios->dcb.gpio.entries--;
5855 continue;
5856 }
20d66daf 5857
e49f70f7 5858 e->line = (e->entry & 0x001f);
85a2a365
BS		 5859 e->state[0] = ((e->entry & 0xf800) >> 11) != 4;
5860 e->state[1] = !e->state[0];
e49f70f7
BS		 5861 } else {
5862 e->entry = ROM32(entry[0]);
5863 e->tag = (e->entry & 0x0000ff00) >> 8;
5864 if (e->tag == 0xff) {
5865 bios->dcb.gpio.entries--;
5866 continue;
5867 }
20d66daf 5868
e49f70f7 5869 e->line = (e->entry & 0x0000001f) >> 0;
d7f8172c
BS		 5870 if (gpio[0] == 0x40) {
5871 e->state_default = (e->entry & 0x01000000) >> 24;
5872 e->state[0] = (e->entry & 0x18000000) >> 27;
5873 e->state[1] = (e->entry & 0x60000000) >> 29;
5874 } else {
5875 e->state_default = (e->entry & 0x00000080) >> 7;
5876 e->state[0] = (entry[4] >> 4) & 3;
5877 e->state[1] = (entry[4] >> 6) & 3;
5878 }
20d66daf 5879 }
6ee73861
BS		 5880 }
5881
e49f70f7
BS		 5882no_table:
5883 /* Apple iMac G4 NV18 */
5884 if (nv_match_device(dev, 0x0189, 0x10de, 0x0010)) {
5885 e = new_gpio_entry(bios);
5886 if (e) {
5887 e->tag = DCB_GPIO_TVDAC0;
5888 e->line = 4;
5889 }
6ee73861 5890 }
6ee73861
BS		 5891}
5892
5893struct dcb_connector_table_entry *
5894nouveau_bios_connector_entry(struct drm_device *dev, int index)
5895{
5896 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 5897 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 5898 struct dcb_connector_table_entry *cte;
5899
7f245b20 5900 if (index >= bios->dcb.connector.entries)
6ee73861
BS		 5901 return NULL;
5902
7f245b20 5903 cte = &bios->dcb.connector.entry[index];
6ee73861
BS		 5904 if (cte->type == 0xff)
5905 return NULL;
5906
5907 return cte;
5908}
5909
f66fa771
BS		 5910static enum dcb_connector_type
5911divine_connector_type(struct nvbios *bios, int index)
5912{
5913 struct dcb_table *dcb = &bios->dcb;
5914 unsigned encoders = 0, type = DCB_CONNECTOR_NONE;
5915 int i;
5916
5917 for (i = 0; i < dcb->entries; i++) {
5918 if (dcb->entry[i].connector == index)
5919 encoders |= (1 << dcb->entry[i].type);
5920 }
5921
5922 if (encoders & (1 << OUTPUT_DP)) {
5923 if (encoders & (1 << OUTPUT_TMDS))
5924 type = DCB_CONNECTOR_DP;
5925 else
5926 type = DCB_CONNECTOR_eDP;
5927 } else
5928 if (encoders & (1 << OUTPUT_TMDS)) {
5929 if (encoders & (1 << OUTPUT_ANALOG))
5930 type = DCB_CONNECTOR_DVI_I;
5931 else
5932 type = DCB_CONNECTOR_DVI_D;
5933 } else
5934 if (encoders & (1 << OUTPUT_ANALOG)) {
5935 type = DCB_CONNECTOR_VGA;
5936 } else
5937 if (encoders & (1 << OUTPUT_LVDS)) {
5938 type = DCB_CONNECTOR_LVDS;
5939 } else
5940 if (encoders & (1 << OUTPUT_TV)) {
5941 type = DCB_CONNECTOR_TV_0;
5942 }
5943
5944 return type;
5945}
5946
53c44c3a
BS		 5947static void
5948apply_dcb_connector_quirks(struct nvbios *bios, int idx)
5949{
5950 struct dcb_connector_table_entry *cte = &bios->dcb.connector.entry[idx];
5951 struct drm_device *dev = bios->dev;
5952
5953 /* Gigabyte NX85T */
acae116c 5954 if (nv_match_device(dev, 0x0421, 0x1458, 0x344c)) {
53c44c3a
BS		 5955 if (cte->type == DCB_CONNECTOR_HDMI_1)
5956 cte->type = DCB_CONNECTOR_DVI_I;
5957 }
f0d07d6e
EV		 5958
5959 /* Gigabyte GV-NX86T512H */
5960 if (nv_match_device(dev, 0x0402, 0x1458, 0x3455)) {
5961 if (cte->type == DCB_CONNECTOR_HDMI_1)
5962 cte->type = DCB_CONNECTOR_DVI_I;
5963 }
53c44c3a
BS		 5964}
5965
a589e87f
BS		 5966static const u8 hpd_gpio[16] = {
5967 0xff, 0x07, 0x08, 0xff, 0xff, 0x51, 0x52, 0xff,
5968 0xff, 0xff, 0xff, 0xff, 0xff, 0x5e, 0x5f, 0x60,
5969};
5970
6ee73861
BS		 5971static void
5972parse_dcb_connector_table(struct nvbios *bios)
5973{
5974 struct drm_device *dev = bios->dev;
7f245b20 5975 struct dcb_connector_table *ct = &bios->dcb.connector;
6ee73861 5976 struct dcb_connector_table_entry *cte;
7f245b20 5977 uint8_t *conntab = &bios->data[bios->dcb.connector_table_ptr];
6ee73861
BS		 5978 uint8_t *entry;
5979 int i;
5980
7f245b20 5981 if (!bios->dcb.connector_table_ptr) {
ef2bb506 5982 NV_DEBUG_KMS(dev, "No DCB connector table present\n");
6ee73861
BS		 5983 return;
5984 }
5985
5986 NV_INFO(dev, "DCB connector table: VHER 0x%02x %d %d %d\n",
5987 conntab[0], conntab[1], conntab[2], conntab[3]);
5988 if ((conntab[0] != 0x30 && conntab[0] != 0x40) ||
5989 (conntab[3] != 2 && conntab[3] != 4)) {
5990 NV_ERROR(dev, " Unknown! Please report.\n");
5991 return;
5992 }
5993
5994 ct->entries = conntab[2];
5995
5996 entry = conntab + conntab[1];
5997 cte = &ct->entry[0];
5998 for (i = 0; i < conntab[2]; i++, entry += conntab[3], cte++) {
d544d623 5999 cte->index = i;
6ee73861
BS		 6000 if (conntab[3] == 2)
6001 cte->entry = ROM16(entry[0]);
6002 else
6003 cte->entry = ROM32(entry[0]);
f66fa771 6004
6ee73861 6005 cte->type = (cte->entry & 0x000000ff) >> 0;
d544d623 6006 cte->index2 = (cte->entry & 0x00000f00) >> 8;
a589e87f
BS		 6007
6008 cte->gpio_tag = ffs((cte->entry & 0x07033000) >> 12);
6009 cte->gpio_tag = hpd_gpio[cte->gpio_tag];
6ee73861
BS		 6010
6011 if (cte->type == 0xff)
6012 continue;
6013
53c44c3a
BS		 6014 apply_dcb_connector_quirks(bios, i);
6015
6ee73861
BS		 6016 NV_INFO(dev, " %d: 0x%08x: type 0x%02x idx %d tag 0x%02x\n",
6017 i, cte->entry, cte->type, cte->index, cte->gpio_tag);
f66fa771
BS		 6018
6019 /* check for known types, fallback to guessing the type
6020 * from attached encoders if we hit an unknown.
6021 */
6022 switch (cte->type) {
6023 case DCB_CONNECTOR_VGA:
6024 case DCB_CONNECTOR_TV_0:
6025 case DCB_CONNECTOR_TV_1:
6026 case DCB_CONNECTOR_TV_3:
6027 case DCB_CONNECTOR_DVI_I:
6028 case DCB_CONNECTOR_DVI_D:
6029 case DCB_CONNECTOR_LVDS:
8c3f6bb9 6030 case DCB_CONNECTOR_LVDS_SPWG:
f66fa771
BS		 6031 case DCB_CONNECTOR_DP:
6032 case DCB_CONNECTOR_eDP:
6033 case DCB_CONNECTOR_HDMI_0:
6034 case DCB_CONNECTOR_HDMI_1:
6035 break;
6036 default:
6037 cte->type = divine_connector_type(bios, cte->index);
da647d5b 6038 NV_WARN(dev, "unknown type, using 0x%02x\n", cte->type);
f66fa771
BS		 6039 break;
6040 }
6041
da647d5b
BS		 6042 if (nouveau_override_conntype) {
6043 int type = divine_connector_type(bios, cte->index);
6044 if (type != cte->type)
6045 NV_WARN(dev, " -> type 0x%02x\n", cte->type);
6046 }
6047
6ee73861
BS		 6048 }
6049}
6050
7f245b20 6051static struct dcb_entry *new_dcb_entry(struct dcb_table *dcb)
6ee73861
BS		 6052{
6053 struct dcb_entry *entry = &dcb->entry[dcb->entries];
6054
6055 memset(entry, 0, sizeof(struct dcb_entry));
6056 entry->index = dcb->entries++;
6057
6058 return entry;
6059}
6060
2e5702af
FJ		 6061static void fabricate_dcb_output(struct dcb_table *dcb, int type, int i2c,
6062 int heads, int or)
6ee73861
BS		 6063{
6064 struct dcb_entry *entry = new_dcb_entry(dcb);
6065
2e5702af 6066 entry->type = type;
6ee73861
BS		 6067 entry->i2c_index = i2c;
6068 entry->heads = heads;
2e5702af
FJ		 6069 if (type != OUTPUT_ANALOG)
6070 entry->location = !DCB_LOC_ON_CHIP; /* ie OFF CHIP */
6071 entry->or = or;
6ee73861
BS		 6072}
6073
6074static bool
7f245b20 6075parse_dcb20_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6076 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6077{
6078 entry->type = conn & 0xf;
6079 entry->i2c_index = (conn >> 4) & 0xf;
6080 entry->heads = (conn >> 8) & 0xf;
7f245b20 6081 if (dcb->version >= 0x40)
6ee73861
BS		 6082 entry->connector = (conn >> 12) & 0xf;
6083 entry->bus = (conn >> 16) & 0xf;
6084 entry->location = (conn >> 20) & 0x3;
6085 entry->or = (conn >> 24) & 0xf;
6ee73861
BS		 6086
6087 switch (entry->type) {
6088 case OUTPUT_ANALOG:
6089 /*
6090 * Although the rest of a CRT conf dword is usually
6091 * zeros, mac biosen have stuff there so we must mask
6092 */
7f245b20 6093 entry->crtconf.maxfreq = (dcb->version < 0x30) ?
6ee73861
BS		 6094 (conf & 0xffff) * 10 :
6095 (conf & 0xff) * 10000;
6096 break;
6097 case OUTPUT_LVDS:
6098 {
6099 uint32_t mask;
6100 if (conf & 0x1)
6101 entry->lvdsconf.use_straps_for_mode = true;
7f245b20 6102 if (dcb->version < 0x22) {
6ee73861
BS		 6103 mask = ~0xd;
6104 /*
6105 * The laptop in bug 14567 lies and claims to not use
6106 * straps when it does, so assume all DCB 2.0 laptops
6107 * use straps, until a broken EDID using one is produced
6108 */
6109 entry->lvdsconf.use_straps_for_mode = true;
6110 /*
6111 * Both 0x4 and 0x8 show up in v2.0 tables; assume they
6112 * mean the same thing (probably wrong, but might work)
6113 */
6114 if (conf & 0x4 || conf & 0x8)
6115 entry->lvdsconf.use_power_scripts = true;
6116 } else {
a6ed76d7
BS		 6117 mask = ~0x7;
6118 if (conf & 0x2)
6119 entry->lvdsconf.use_acpi_for_edid = true;
6ee73861
BS		 6120 if (conf & 0x4)
6121 entry->lvdsconf.use_power_scripts = true;
c5875470 6122 entry->lvdsconf.sor.link = (conf & 0x00000030) >> 4;
6ee73861
BS		 6123 }
6124 if (conf & mask) {
6125 /*
6126 * Until we even try to use these on G8x, it's
6127 * useless reporting unknown bits. They all are.
6128 */
7f245b20 6129 if (dcb->version >= 0x40)
6ee73861
BS		 6130 break;
6131
6132 NV_ERROR(dev, "Unknown LVDS configuration bits, "
6133 "please report\n");
6134 }
6135 break;
6136 }
6137 case OUTPUT_TV:
6138 {
7f245b20 6139 if (dcb->version >= 0x30)
6ee73861
BS		 6140 entry->tvconf.has_component_output = conf & (0x8 << 4);
6141 else
6142 entry->tvconf.has_component_output = false;
6143
6144 break;
6145 }
6146 case OUTPUT_DP:
6147 entry->dpconf.sor.link = (conf & 0x00000030) >> 4;
75a1fccf
BS		 6148 switch ((conf & 0x00e00000) >> 21) {
6149 case 0:
6150 entry->dpconf.link_bw = 162000;
6151 break;
6152 default:
6153 entry->dpconf.link_bw = 270000;
6154 break;
6155 }
6ee73861
BS		 6156 switch ((conf & 0x0f000000) >> 24) {
6157 case 0xf:
6158 entry->dpconf.link_nr = 4;
6159 break;
6160 case 0x3:
6161 entry->dpconf.link_nr = 2;
6162 break;
6163 default:
6164 entry->dpconf.link_nr = 1;
6165 break;
6166 }
6167 break;
6168 case OUTPUT_TMDS:
27d50fcc
FJ		 6169 if (dcb->version >= 0x40)
6170 entry->tmdsconf.sor.link = (conf & 0x00000030) >> 4;
4a9f822f
FJ		 6171 else if (dcb->version >= 0x30)
6172 entry->tmdsconf.slave_addr = (conf & 0x00000700) >> 8;
27d50fcc
FJ		 6173 else if (dcb->version >= 0x22)
6174 entry->tmdsconf.slave_addr = (conf & 0x00000070) >> 4;
4a9f822f 6175
6ee73861 6176 break;
44a1246f 6177 case OUTPUT_EOL:
6ee73861 6178 /* weird g80 mobile type that "nv" treats as a terminator */
7f245b20 6179 dcb->entries--;
6ee73861 6180 return false;
e7cc51c5
BS		 6181 default:
6182 break;
6ee73861
BS		 6183 }
6184
23484874
BS		 6185 if (dcb->version < 0x40) {
6186 /* Normal entries consist of a single bit, but dual link has
6187 * the next most significant bit set too
6188 */
6189 entry->duallink_possible =
6190 ((1 << (ffs(entry->or) - 1)) * 3 == entry->or);
6191 } else {
6192 entry->duallink_possible = (entry->sorconf.link == 3);
6193 }
6194
6ee73861
BS		 6195 /* unsure what DCB version introduces this, 3.0? */
6196 if (conf & 0x100000)
6197 entry->i2c_upper_default = true;
6198
6199 return true;
6200}
6201
6202static bool
7f245b20 6203parse_dcb15_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6204 uint32_t conn, uint32_t conf, struct dcb_entry *entry)
6205{
b0d2de86
BS		 6206 switch (conn & 0x0000000f) {
6207 case 0:
6208 entry->type = OUTPUT_ANALOG;
6209 break;
6210 case 1:
6211 entry->type = OUTPUT_TV;
6212 break;
6213 case 2:
b0d2de86 6214 case 4:
fba67528 6215 if (conn & 0x10)
b0d2de86 6216 entry->type = OUTPUT_LVDS;
fba67528
FJ		 6217 else
6218 entry->type = OUTPUT_TMDS;
6219 break;
6220 case 3:
6221 entry->type = OUTPUT_LVDS;
b0d2de86
BS		 6222 break;
6223 default:
6224 NV_ERROR(dev, "Unknown DCB type %d\n", conn & 0x0000000f);
6225 return false;
6ee73861 6226 }
b0d2de86
BS		 6227
6228 entry->i2c_index = (conn & 0x0003c000) >> 14;
6229 entry->heads = ((conn & 0x001c0000) >> 18) + 1;
6230 entry->or = entry->heads; /* same as heads, hopefully safe enough */
6231 entry->location = (conn & 0x01e00000) >> 21;
6232 entry->bus = (conn & 0x0e000000) >> 25;
6ee73861
BS		 6233 entry->duallink_possible = false;
6234
6235 switch (entry->type) {
6236 case OUTPUT_ANALOG:
6237 entry->crtconf.maxfreq = (conf & 0xffff) * 10;
6238 break;
b0d2de86
BS		 6239 case OUTPUT_TV:
6240 entry->tvconf.has_component_output = false;
6ee73861 6241 break;
b0d2de86 6242 case OUTPUT_LVDS:
77b1d5dc 6243 if ((conn & 0x00003f00) >> 8 != 0x10)
b0d2de86
BS		 6244 entry->lvdsconf.use_straps_for_mode = true;
6245 entry->lvdsconf.use_power_scripts = true;
6246 break;
6247 default:
6ee73861
BS		 6248 break;
6249 }
6250
6251 return true;
6252}
6253
7f245b20 6254static bool parse_dcb_entry(struct drm_device *dev, struct dcb_table *dcb,
6ee73861
BS		 6255 uint32_t conn, uint32_t conf)
6256{
7f245b20 6257 struct dcb_entry *entry = new_dcb_entry(dcb);
6ee73861
BS		 6258 bool ret;
6259
7f245b20
BS		 6260 if (dcb->version >= 0x20)
6261 ret = parse_dcb20_entry(dev, dcb, conn, conf, entry);
6ee73861 6262 else
7f245b20 6263 ret = parse_dcb15_entry(dev, dcb, conn, conf, entry);
6ee73861
BS		 6264 if (!ret)
6265 return ret;
6266
7f245b20
BS		 6267 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6268 entry->i2c_index, &dcb->i2c[entry->i2c_index]);
6ee73861
BS		 6269
6270 return true;
6271}
6272
6273static
7f245b20 6274void merge_like_dcb_entries(struct drm_device *dev, struct dcb_table *dcb)
6ee73861
BS		 6275{
6276 /*
6277 * DCB v2.0 lists each output combination separately.
6278 * Here we merge compatible entries to have fewer outputs, with
6279 * more options
6280 */
6281
6282 int i, newentries = 0;
6283
6284 for (i = 0; i < dcb->entries; i++) {
6285 struct dcb_entry *ient = &dcb->entry[i];
6286 int j;
6287
6288 for (j = i + 1; j < dcb->entries; j++) {
6289 struct dcb_entry *jent = &dcb->entry[j];
6290
6291 if (jent->type == 100) /* already merged entry */
6292 continue;
6293
6294 /* merge heads field when all other fields the same */
6295 if (jent->i2c_index == ient->i2c_index &&
6296 jent->type == ient->type &&
6297 jent->location == ient->location &&
6298 jent->or == ient->or) {
6299 NV_TRACE(dev, "Merging DCB entries %d and %d\n",
6300 i, j);
6301 ient->heads |= jent->heads;
6302 jent->type = 100; /* dummy value */
6303 }
6304 }
6305 }
6306
6307 /* Compact entries merged into others out of dcb */
6308 for (i = 0; i < dcb->entries; i++) {
6309 if (dcb->entry[i].type == 100)
6310 continue;
6311
6312 if (newentries != i) {
6313 dcb->entry[newentries] = dcb->entry[i];
6314 dcb->entry[newentries].index = newentries;
6315 }
6316 newentries++;
6317 }
6318
6319 dcb->entries = newentries;
6320}
6321
df4cf1b7
BS		 6322static bool
6323apply_dcb_encoder_quirks(struct drm_device *dev, int idx, u32 *conn, u32 *conf)
6324{
670820c0
FJ		 6325 struct drm_nouveau_private *dev_priv = dev->dev_private;
6326 struct dcb_table *dcb = &dev_priv->vbios.dcb;
6327
df4cf1b7
BS		 6328 /* Dell Precision M6300
6329 * DCB entry 2: 02025312 00000010
6330 * DCB entry 3: 02026312 00000020
6331 *
6332 * Identical, except apparently a different connector on a
6333 * different SOR link. Not a clue how we're supposed to know
6334 * which one is in use if it even shares an i2c line...
6335 *
6336 * Ignore the connector on the second SOR link to prevent
6337 * nasty problems until this is sorted (assuming it's not a
6338 * VBIOS bug).
6339 */
acae116c 6340 if (nv_match_device(dev, 0x040d, 0x1028, 0x019b)) {
df4cf1b7
BS		 6341 if (*conn == 0x02026312 && *conf == 0x00000020)
6342 return false;
6343 }
6344
670820c0
FJ		 6345 /* GeForce3 Ti 200
6346 *
6347 * DCB reports an LVDS output that should be TMDS:
6348 * DCB entry 1: f2005014 ffffffff
6349 */
6350 if (nv_match_device(dev, 0x0201, 0x1462, 0x8851)) {
6351 if (*conn == 0xf2005014 && *conf == 0xffffffff) {
6352 fabricate_dcb_output(dcb, OUTPUT_TMDS, 1, 1, 1);
6353 return false;
6354 }
6355 }
6356
c0929b49
BS		 6357 /* XFX GT-240X-YA
6358 *
6359 * So many things wrong here, replace the entire encoder table..
6360 */
6361 if (nv_match_device(dev, 0x0ca3, 0x1682, 0x3003)) {
6362 if (idx == 0) {
6363 *conn = 0x02001300; /* VGA, connector 1 */
6364 *conf = 0x00000028;
6365 } else
6366 if (idx == 1) {
6367 *conn = 0x01010312; /* DVI, connector 0 */
6368 *conf = 0x00020030;
6369 } else
6370 if (idx == 2) {
6371 *conn = 0x01010310; /* VGA, connector 0 */
6372 *conf = 0x00000028;
6373 } else
6374 if (idx == 3) {
6375 *conn = 0x02022362; /* HDMI, connector 2 */
6376 *conf = 0x00020010;
6377 } else {
6378 *conn = 0x0000000e; /* EOL */
6379 *conf = 0x00000000;
6380 }
6381 }
6382
e540afc3
BS		 6383 /* Some other twisted XFX board (rhbz#694914)
6384 *
6385 * The DVI/VGA encoder combo that's supposed to represent the
6386 * DVI-I connector actually point at two different ones, and
6387 * the HDMI connector ends up paired with the VGA instead.
6388 *
6389 * Connector table is missing anything for VGA at all, pointing it
6390 * an invalid conntab entry 2 so we figure it out ourself.
6391 */
6392 if (nv_match_device(dev, 0x0615, 0x1682, 0x2605)) {
6393 if (idx == 0) {
6394 *conn = 0x02002300; /* VGA, connector 2 */
6395 *conf = 0x00000028;
6396 } else
6397 if (idx == 1) {
6398 *conn = 0x01010312; /* DVI, connector 0 */
6399 *conf = 0x00020030;
6400 } else
6401 if (idx == 2) {
6402 *conn = 0x04020310; /* VGA, connector 0 */
6403 *conf = 0x00000028;
6404 } else
6405 if (idx == 3) {
6406 *conn = 0x02021322; /* HDMI, connector 1 */
6407 *conf = 0x00020010;
6408 } else {
6409 *conn = 0x0000000e; /* EOL */
6410 *conf = 0x00000000;
6411 }
6412 }
6413
df4cf1b7
BS		 6414 return true;
6415}
6416
2e5702af
FJ		 6417static void
6418fabricate_dcb_encoder_table(struct drm_device *dev, struct nvbios *bios)
6419{
6420 struct dcb_table *dcb = &bios->dcb;
6421 int all_heads = (nv_two_heads(dev) ? 3 : 1);
6422
6423#ifdef __powerpc__
6424 /* Apple iMac G4 NV17 */
6425 if (of_machine_is_compatible("PowerMac4,5")) {
6426 fabricate_dcb_output(dcb, OUTPUT_TMDS, 0, all_heads, 1);
6427 fabricate_dcb_output(dcb, OUTPUT_ANALOG, 1, all_heads, 2);
6428 return;
6429 }
6430#endif
6431
6432 /* Make up some sane defaults */
0f8067c7
BS		 6433 fabricate_dcb_output(dcb, OUTPUT_ANALOG,
6434 bios->legacy.i2c_indices.crt, 1, 1);
2e5702af
FJ		 6435
6436 if (nv04_tv_identify(dev, bios->legacy.i2c_indices.tv) >= 0)
0f8067c7
BS		 6437 fabricate_dcb_output(dcb, OUTPUT_TV,
6438 bios->legacy.i2c_indices.tv,
2e5702af
FJ		 6439 all_heads, 0);
6440
6441 else if (bios->tmds.output0_script_ptr ||
6442 bios->tmds.output1_script_ptr)
0f8067c7
BS		 6443 fabricate_dcb_output(dcb, OUTPUT_TMDS,
6444 bios->legacy.i2c_indices.panel,
2e5702af
FJ		 6445 all_heads, 1);
6446}
6447
ed42f824 6448static int
2e5702af 6449parse_dcb_table(struct drm_device *dev, struct nvbios *bios)
6ee73861 6450{
ed42f824 6451 struct drm_nouveau_private *dev_priv = dev->dev_private;
7f245b20 6452 struct dcb_table *dcb = &bios->dcb;
ed42f824 6453 uint16_t dcbptr = 0, i2ctabptr = 0;
6ee73861
BS		 6454 uint8_t *dcbtable;
6455 uint8_t headerlen = 0x4, entries = DCB_MAX_NUM_ENTRIES;
6456 bool configblock = true;
6457 int recordlength = 8, confofs = 4;
6458 int i;
6459
6ee73861 6460 /* get the offset from 0x36 */
ed42f824
BS		 6461 if (dev_priv->card_type > NV_04) {
6462 dcbptr = ROM16(bios->data[0x36]);
6463 if (dcbptr == 0x0000)
6464 NV_WARN(dev, "No output data (DCB) found in BIOS\n");
6465 }
6ee73861 6466
ed42f824 6467 /* this situation likely means a really old card, pre DCB */
6ee73861 6468 if (dcbptr == 0x0) {
2e5702af 6469 fabricate_dcb_encoder_table(dev, bios);
6ee73861
BS		 6470 return 0;
6471 }
6472
6473 dcbtable = &bios->data[dcbptr];
6474
6475 /* get DCB version */
7f245b20 6476 dcb->version = dcbtable[0];
6ee73861 6477 NV_TRACE(dev, "Found Display Configuration Block version %d.%d\n",
7f245b20 6478 dcb->version >> 4, dcb->version & 0xf);
6ee73861 6479
7f245b20 6480 if (dcb->version >= 0x20) { /* NV17+ */
6ee73861
BS		 6481 uint32_t sig;
6482
7f245b20 6483 if (dcb->version >= 0x30) { /* NV40+ */
6ee73861
BS		 6484 headerlen = dcbtable[1];
6485 entries = dcbtable[2];
6486 recordlength = dcbtable[3];
6487 i2ctabptr = ROM16(dcbtable[4]);
6488 sig = ROM32(dcbtable[6]);
7f245b20
BS		 6489 dcb->gpio_table_ptr = ROM16(dcbtable[10]);
6490 dcb->connector_table_ptr = ROM16(dcbtable[20]);
6ee73861
BS		 6491 } else {
6492 i2ctabptr = ROM16(dcbtable[2]);
6493 sig = ROM32(dcbtable[4]);
6494 headerlen = 8;
6495 }
6496
6497 if (sig != 0x4edcbdcb) {
6498 NV_ERROR(dev, "Bad Display Configuration Block "
6499 "signature (%08X)\n", sig);
6500 return -EINVAL;
6501 }
7f245b20 6502 } else if (dcb->version >= 0x15) { /* some NV11 and NV20 */
6ee73861
BS		 6503 char sig[8] = { 0 };
6504
6505 strncpy(sig, (char *)&dcbtable[-7], 7);
6506 i2ctabptr = ROM16(dcbtable[2]);
6507 recordlength = 10;
6508 confofs = 6;
6509
6510 if (strcmp(sig, "DEV_REC")) {
6511 NV_ERROR(dev, "Bad Display Configuration Block "
6512 "signature (%s)\n", sig);
6513 return -EINVAL;
6514 }
6515 } else {
6516 /*
6517 * v1.4 (some NV15/16, NV11+) seems the same as v1.5, but always
6518 * has the same single (crt) entry, even when tv-out present, so
6519 * the conclusion is this version cannot really be used.
6520 * v1.2 tables (some NV6/10, and NV15+) normally have the same
6521 * 5 entries, which are not specific to the card and so no use.
6522 * v1.2 does have an I2C table that read_dcb_i2c_table can
6523 * handle, but cards exist (nv11 in #14821) with a bad i2c table
6524 * pointer, so use the indices parsed in parse_bmp_structure.
6525 * v1.1 (NV5+, maybe some NV4) is entirely unhelpful
6526 */
6527 NV_TRACEWARN(dev, "No useful information in BIOS output table; "
6528 "adding all possible outputs\n");
2e5702af 6529 fabricate_dcb_encoder_table(dev, bios);
6ee73861
BS		 6530 return 0;
6531 }
6532
6533 if (!i2ctabptr)
6534 NV_WARN(dev, "No pointer to DCB I2C port table\n");
6535 else {
7f245b20
BS		 6536 dcb->i2c_table = &bios->data[i2ctabptr];
6537 if (dcb->version >= 0x30)
6538 dcb->i2c_default_indices = dcb->i2c_table[4];
4a9f822f
FJ		 6539
6540 /*
6541 * Parse the "management" I2C bus, used for hardware
6542 * monitoring and some external TMDS transmitters.
6543 */
6544 if (dcb->version >= 0x22) {
6545 int idx = (dcb->version >= 0x40 ?
6546 dcb->i2c_default_indices & 0xf :
6547 2);
6548
6549 read_dcb_i2c_entry(dev, dcb->version, dcb->i2c_table,
6550 idx, &dcb->i2c[idx]);
6551 }
6ee73861
BS		 6552 }
6553
6ee73861
BS		 6554 if (entries > DCB_MAX_NUM_ENTRIES)
6555 entries = DCB_MAX_NUM_ENTRIES;
6556
6557 for (i = 0; i < entries; i++) {
6558 uint32_t connection, config = 0;
6559
6560 connection = ROM32(dcbtable[headerlen + recordlength * i]);
6561 if (configblock)
6562 config = ROM32(dcbtable[headerlen + confofs + recordlength * i]);
6563
6564 /* seen on an NV11 with DCB v1.5 */
6565 if (connection == 0x00000000)
6566 break;
6567
6568 /* seen on an NV17 with DCB v2.0 */
6569 if (connection == 0xffffffff)
6570 break;
6571
6572 if ((connection & 0x0000000f) == 0x0000000f)
6573 continue;
6574
df4cf1b7
BS		 6575 if (!apply_dcb_encoder_quirks(dev, i, &connection, &config))
6576 continue;
6577
6ee73861
BS		 6578 NV_TRACEWARN(dev, "Raw DCB entry %d: %08x %08x\n",
6579 dcb->entries, connection, config);
6580
7f245b20 6581 if (!parse_dcb_entry(dev, dcb, connection, config))
6ee73861
BS		 6582 break;
6583 }
6584
6585 /*
6586 * apart for v2.1+ not being known for requiring merging, this
6587 * guarantees dcbent->index is the index of the entry in the rom image
6588 */
7f245b20 6589 if (dcb->version < 0x21)
6ee73861
BS		 6590 merge_like_dcb_entries(dev, dcb);
6591
54abb5dd
BS		 6592 if (!dcb->entries)
6593 return -ENXIO;
6594
6595 parse_dcb_gpio_table(bios);
6596 parse_dcb_connector_table(bios);
6597 return 0;
6ee73861
BS		 6598}
6599
6600static void
6601fixup_legacy_connector(struct nvbios *bios)
6602{
7f245b20 6603 struct dcb_table *dcb = &bios->dcb;
dc5bc4ed 6604 int i, i2c, i2c_conn[DCB_MAX_NUM_I2C_ENTRIES] = { };
6ee73861
BS		 6605
6606 /*
6607 * DCB 3.0 also has the table in most cases, but there are some cards
6608 * where the table is filled with stub entries, and the DCB entriy
6609 * indices are all 0. We don't need the connector indices on pre-G80
6610 * chips (yet?) so limit the use to DCB 4.0 and above.
6611 */
7f245b20 6612 if (dcb->version >= 0x40)
6ee73861
BS		 6613 return;
6614
dc5bc4ed
BS		 6615 dcb->connector.entries = 0;
6616
6ee73861
BS		 6617 /*
6618 * No known connector info before v3.0, so make it up. the rule here
6619 * is: anything on the same i2c bus is considered to be on the same
6620 * connector. any output without an associated i2c bus is assigned
6621 * its own unique connector index.
6622 */
6623 for (i = 0; i < dcb->entries; i++) {
6ee73861
BS		 6624 /*
6625 * Ignore the I2C index for on-chip TV-out, as there
6626 * are cards with bogus values (nv31m in bug 23212),
6627 * and it's otherwise useless.
6628 */
6629 if (dcb->entry[i].type == OUTPUT_TV &&
dc5bc4ed 6630 dcb->entry[i].location == DCB_LOC_ON_CHIP)
6ee73861 6631 dcb->entry[i].i2c_index = 0xf;
dc5bc4ed
BS		 6632 i2c = dcb->entry[i].i2c_index;
6633
6634 if (i2c_conn[i2c]) {
6635 dcb->entry[i].connector = i2c_conn[i2c] - 1;
6ee73861
BS		 6636 continue;
6637 }
6638
dc5bc4ed
BS		 6639 dcb->entry[i].connector = dcb->connector.entries++;
6640 if (i2c != 0xf)
6641 i2c_conn[i2c] = dcb->connector.entries;
6ee73861
BS		 6642 }
6643
dc5bc4ed
BS		 6644 /* Fake the connector table as well as just connector indices */
6645 for (i = 0; i < dcb->connector.entries; i++) {
6646 dcb->connector.entry[i].index = i;
6647 dcb->connector.entry[i].type = divine_connector_type(bios, i);
6648 dcb->connector.entry[i].gpio_tag = 0xff;
6ee73861
BS		 6649 }
6650}
6651
6ee73861
BS		 6652static int load_nv17_hwsq_ucode_entry(struct drm_device *dev, struct nvbios *bios, uint16_t hwsq_offset, int entry)
6653{
6654 /*
6655 * The header following the "HWSQ" signature has the number of entries,
6656 * and the entry size
6657 *
6658 * An entry consists of a dword to write to the sequencer control reg
6659 * (0x00001304), followed by the ucode bytes, written sequentially,
6660 * starting at reg 0x00001400
6661 */
6662
6663 uint8_t bytes_to_write;
6664 uint16_t hwsq_entry_offset;
6665 int i;
6666
6667 if (bios->data[hwsq_offset] <= entry) {
6668 NV_ERROR(dev, "Too few entries in HW sequencer table for "
6669 "requested entry\n");
6670 return -ENOENT;
6671 }
6672
6673 bytes_to_write = bios->data[hwsq_offset + 1];
6674
6675 if (bytes_to_write != 36) {
6676 NV_ERROR(dev, "Unknown HW sequencer entry size\n");
6677 return -EINVAL;
6678 }
6679
6680 NV_TRACE(dev, "Loading NV17 power sequencing microcode\n");
6681
6682 hwsq_entry_offset = hwsq_offset + 2 + entry * bytes_to_write;
6683
6684 /* set sequencer control */
6685 bios_wr32(bios, 0x00001304, ROM32(bios->data[hwsq_entry_offset]));
6686 bytes_to_write -= 4;
6687
6688 /* write ucode */
6689 for (i = 0; i < bytes_to_write; i += 4)
6690 bios_wr32(bios, 0x00001400 + i, ROM32(bios->data[hwsq_entry_offset + i + 4]));
6691
6692 /* twiddle NV_PBUS_DEBUG_4 */
6693 bios_wr32(bios, NV_PBUS_DEBUG_4, bios_rd32(bios, NV_PBUS_DEBUG_4) | 0x18);
6694
6695 return 0;
6696}
6697
6698static int load_nv17_hw_sequencer_ucode(struct drm_device *dev,
6699 struct nvbios *bios)
6700{
6701 /*
6702 * BMP based cards, from NV17, need a microcode loading to correctly
6703 * control the GPIO etc for LVDS panels
6704 *
6705 * BIT based cards seem to do this directly in the init scripts
6706 *
6707 * The microcode entries are found by the "HWSQ" signature.
6708 */
6709
6710 const uint8_t hwsq_signature[] = { 'H', 'W', 'S', 'Q' };
6711 const int sz = sizeof(hwsq_signature);
6712 int hwsq_offset;
6713
6714 hwsq_offset = findstr(bios->data, bios->length, hwsq_signature, sz);
6715 if (!hwsq_offset)
6716 return 0;
6717
6718 /* always use entry 0? */
6719 return load_nv17_hwsq_ucode_entry(dev, bios, hwsq_offset + sz, 0);
6720}
6721
6722uint8_t *nouveau_bios_embedded_edid(struct drm_device *dev)
6723{
6724 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6725 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6726 const uint8_t edid_sig[] = {
6727 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 };
6728 uint16_t offset = 0;
6729 uint16_t newoffset;
6730 int searchlen = NV_PROM_SIZE;
6731
6732 if (bios->fp.edid)
6733 return bios->fp.edid;
6734
6735 while (searchlen) {
6736 newoffset = findstr(&bios->data[offset], searchlen,
6737 edid_sig, 8);
6738 if (!newoffset)
6739 return NULL;
6740 offset += newoffset;
6741 if (!nv_cksum(&bios->data[offset], EDID1_LEN))
6742 break;
6743
6744 searchlen -= offset;
6745 offset++;
6746 }
6747
6748 NV_TRACE(dev, "Found EDID in BIOS\n");
6749
6750 return bios->fp.edid = &bios->data[offset];
6751}
6752
6753void
6754nouveau_bios_run_init_table(struct drm_device *dev, uint16_t table,
02e4f587 6755 struct dcb_entry *dcbent, int crtc)
6ee73861
BS		 6756{
6757 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6758 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6759 struct init_exec iexec = { true, false };
6760
c7ca4d1b 6761 spin_lock_bh(&bios->lock);
6ee73861 6762 bios->display.output = dcbent;
02e4f587 6763 bios->display.crtc = crtc;
6ee73861
BS		 6764 parse_init_table(bios, table, &iexec);
6765 bios->display.output = NULL;
c7ca4d1b 6766 spin_unlock_bh(&bios->lock);
6ee73861
BS		 6767}
6768
59ef9742
BS		 6769void
6770nouveau_bios_init_exec(struct drm_device *dev, uint16_t table)
6771{
6772 struct drm_nouveau_private *dev_priv = dev->dev_private;
6773 struct nvbios *bios = &dev_priv->vbios;
6774 struct init_exec iexec = { true, false };
6775
6776 parse_init_table(bios, table, &iexec);
6777}
6778
6ee73861
BS		 6779static bool NVInitVBIOS(struct drm_device *dev)
6780{
6781 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6782 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6783
6784 memset(bios, 0, sizeof(struct nvbios));
c7ca4d1b 6785 spin_lock_init(&bios->lock);
6ee73861
BS		 6786 bios->dev = dev;
6787
6788 if (!NVShadowVBIOS(dev, bios->data))
6789 return false;
6790
6791 bios->length = NV_PROM_SIZE;
6792 return true;
6793}
6794
6795static int nouveau_parse_vbios_struct(struct drm_device *dev)
6796{
6797 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6798 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6799 const uint8_t bit_signature[] = { 0xff, 0xb8, 'B', 'I', 'T' };
6800 const uint8_t bmp_signature[] = { 0xff, 0x7f, 'N', 'V', 0x0 };
6801 int offset;
6802
6803 offset = findstr(bios->data, bios->length,
6804 bit_signature, sizeof(bit_signature));
6805 if (offset) {
6806 NV_TRACE(dev, "BIT BIOS found\n");
4709bff0
BS		 6807 bios->type = NVBIOS_BIT;
6808 bios->offset = offset;
6ee73861
BS		 6809 return parse_bit_structure(bios, offset + 6);
6810 }
6811
6812 offset = findstr(bios->data, bios->length,
6813 bmp_signature, sizeof(bmp_signature));
6814 if (offset) {
6815 NV_TRACE(dev, "BMP BIOS found\n");
4709bff0
BS		 6816 bios->type = NVBIOS_BMP;
6817 bios->offset = offset;
6ee73861
BS		 6818 return parse_bmp_structure(dev, bios, offset);
6819 }
6820
6821 NV_ERROR(dev, "No known BIOS signature found\n");
6822 return -ENODEV;
6823}
6824
6825int
6826nouveau_run_vbios_init(struct drm_device *dev)
6827{
6828 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6829 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6830 int i, ret = 0;
6831
946fd35f
FJ		 6832 /* Reset the BIOS head to 0. */
6833 bios->state.crtchead = 0;
6ee73861
BS		 6834
6835 if (bios->major_version < 5) /* BMP only */
6836 load_nv17_hw_sequencer_ucode(dev, bios);
6837
6838 if (bios->execute) {
6839 bios->fp.last_script_invoc = 0;
6840 bios->fp.lvds_init_run = false;
6841 }
6842
6843 parse_init_tables(bios);
6844
6845 /*
6846 * Runs some additional script seen on G8x VBIOSen. The VBIOS'
6847 * parser will run this right after the init tables, the binary
6848 * driver appears to run it at some point later.
6849 */
6850 if (bios->some_script_ptr) {
6851 struct init_exec iexec = {true, false};
6852
6853 NV_INFO(dev, "Parsing VBIOS init table at offset 0x%04X\n",
6854 bios->some_script_ptr);
6855 parse_init_table(bios, bios->some_script_ptr, &iexec);
6856 }
6857
6858 if (dev_priv->card_type >= NV_50) {
7f245b20 6859 for (i = 0; i < bios->dcb.entries; i++) {
02e4f587
BS		 6860 nouveau_bios_run_display_table(dev, 0, 0,
6861 &bios->dcb.entry[i], -1);
6ee73861
BS		 6862 }
6863 }
6864
6ee73861
BS		 6865 return ret;
6866}
6867
6868static void
6869nouveau_bios_i2c_devices_takedown(struct drm_device *dev)
6870{
6871 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6872 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6873 struct dcb_i2c_entry *entry;
6874 int i;
6875
7f245b20 6876 entry = &bios->dcb.i2c[0];
6ee73861
BS		 6877 for (i = 0; i < DCB_MAX_NUM_I2C_ENTRIES; i++, entry++)
6878 nouveau_i2c_fini(dev, entry);
6879}
6880
d13102c6
BS		 6881static bool
6882nouveau_bios_posted(struct drm_device *dev)
6883{
6884 struct drm_nouveau_private *dev_priv = dev->dev_private;
d13102c6
BS		 6885 unsigned htotal;
6886
c1b60ece 6887 if (dev_priv->card_type >= NV_50) {
d13102c6
BS		 6888 if (NVReadVgaCrtc(dev, 0, 0x00) == 0 &&
6889 NVReadVgaCrtc(dev, 0, 0x1a) == 0)
6890 return false;
6891 return true;
6892 }
6893
d13102c6
BS		 6894 htotal = NVReadVgaCrtc(dev, 0, 0x06);
6895 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
6896 htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
6897 htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
6898 htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
03cd06ca 6899
d13102c6
BS		 6900 return (htotal != 0);
6901}
6902
6ee73861
BS		 6903int
6904nouveau_bios_init(struct drm_device *dev)
6905{
6906 struct drm_nouveau_private *dev_priv = dev->dev_private;
04a39c57 6907 struct nvbios *bios = &dev_priv->vbios;
6ee73861
BS		 6908 int ret;
6909
6ee73861
BS		 6910 if (!NVInitVBIOS(dev))
6911 return -ENODEV;
6912
6913 ret = nouveau_parse_vbios_struct(dev);
6914 if (ret)
6915 return ret;
6916
2e5702af 6917 ret = parse_dcb_table(dev, bios);
6ee73861
BS		 6918 if (ret)
6919 return ret;
6920
6ee73861
BS		 6921 fixup_legacy_connector(bios);
6922
6923 if (!bios->major_version) /* we don't run version 0 bios */
6924 return 0;
6925
6ee73861
BS		 6926 /* init script execution disabled */
6927 bios->execute = false;
6928
6929 /* ... unless card isn't POSTed already */
d13102c6 6930 if (!nouveau_bios_posted(dev)) {
67eda20e
FJ		 6931 NV_INFO(dev, "Adaptor not initialised, "
6932 "running VBIOS init tables.\n");
6ee73861
BS		 6933 bios->execute = true;
6934 }
0cba1b76
MK		 6935 if (nouveau_force_post)
6936 bios->execute = true;
6ee73861 6937
6ee73861 6938 ret = nouveau_run_vbios_init(dev);
04a39c57 6939 if (ret)
6ee73861 6940 return ret;
6ee73861
BS		 6941
6942 /* feature_byte on BMP is poor, but init always sets CR4B */
6ee73861
BS		 6943 if (bios->major_version < 5)
6944 bios->is_mobile = NVReadVgaCrtc(dev, 0, NV_CIO_CRE_4B) & 0x40;
6945
6946 /* all BIT systems need p_f_m_t for digital_min_front_porch */
6947 if (bios->is_mobile || bios->major_version >= 5)
6948 ret = parse_fp_mode_table(dev, bios);
6ee73861
BS		 6949
6950 /* allow subsequent scripts to execute */
6951 bios->execute = true;
6952
6953 return 0;
6954}
6955
6956void
6957nouveau_bios_takedown(struct drm_device *dev)
6958{
6959 nouveau_bios_i2c_devices_takedown(dev);
6960}