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drm/i915: fixup infoframe support for sdvo
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
79e53945
JB		 32#include "drmP.h"
33#include "drm.h"
34#include "drm_crtc.h"
2b8d33f7 35#include "drm_edid.h"
ea5b213a 36#include "intel_drv.h"
79e53945
JB		 37#include "i915_drm.h"
38#include "i915_drv.h"
39#include "intel_sdvo_regs.h"
40
14571b4c
ZW		 41#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
42#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
43#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 44#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 45
46#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 47 SDVO_TV_MASK)
14571b4c
ZW		 48
49#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 50#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 51#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 52#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 53#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 54
79e53945 55
2e88e40b 56static const char *tv_format_names[] = {
ce6feabd
ZY		 57 "NTSC_M" , "NTSC_J" , "NTSC_443",
58 "PAL_B" , "PAL_D" , "PAL_G" ,
59 "PAL_H" , "PAL_I" , "PAL_M" ,
60 "PAL_N" , "PAL_NC" , "PAL_60" ,
61 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
62 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
63 "SECAM_60"
64};
65
66#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
67
ea5b213a
CW		 68struct intel_sdvo {
69 struct intel_encoder base;
70
f899fc64 71 struct i2c_adapter *i2c;
f9c10a9b 72 u8 slave_addr;
e2f0ba97 73
e957d772
CW		 74 struct i2c_adapter ddc;
75
e2f0ba97 76 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 77 uint32_t sdvo_reg;
79e53945 78
e2f0ba97
JB		 79 /* Active outputs controlled by this SDVO output */
80 uint16_t controlled_output;
79e53945 81
e2f0ba97
JB		 82 /*
83 * Capabilities of the SDVO device returned by
84 * i830_sdvo_get_capabilities()
85 */
79e53945 86 struct intel_sdvo_caps caps;
e2f0ba97
JB		 87
88 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 89 int pixel_clock_min, pixel_clock_max;
90
fb7a46f3 91 /*
92 * For multiple function SDVO device,
93 * this is for current attached outputs.
94 */
95 uint16_t attached_output;
96
cc68c81a
SF		 97 /*
98 * Hotplug activation bits for this device
99 */
100 uint8_t hotplug_active[2];
101
e953fd7b
CW		 102 /**
103 * This is used to select the color range of RBG outputs in HDMI mode.
104 * It is only valid when using TMDS encoding and 8 bit per color mode.
105 */
106 uint32_t color_range;
107
e2f0ba97
JB		 108 /**
109 * This is set if we're going to treat the device as TV-out.
110 *
111 * While we have these nice friendly flags for output types that ought
112 * to decide this for us, the S-Video output on our HDMI+S-Video card
113 * shows up as RGB1 (VGA).
114 */
115 bool is_tv;
116
eef4eacb
DV		 117 /* On different gens SDVOB is at different places. */
118 bool is_sdvob;
119
ce6feabd 120 /* This is for current tv format name */
40039750 121 int tv_format_index;
ce6feabd 122
e2f0ba97
JB		 123 /**
124 * This is set if we treat the device as HDMI, instead of DVI.
125 */
126 bool is_hdmi;
da79de97
CW		 127 bool has_hdmi_monitor;
128 bool has_hdmi_audio;
12682a97 129
7086c87f 130 /**
6c9547ff
CW		 131 * This is set if we detect output of sdvo device as LVDS and
132 * have a valid fixed mode to use with the panel.
7086c87f
ML		 133 */
134 bool is_lvds;
e2f0ba97 135
12682a97 136 /**
137 * This is sdvo fixed pannel mode pointer
138 */
139 struct drm_display_mode *sdvo_lvds_fixed_mode;
140
c751ce4f 141 /* DDC bus used by this SDVO encoder */
e2f0ba97
JB		 142 uint8_t ddc_bus;
143
6c9547ff
CW		 144 /* Input timings for adjusted_mode */
145 struct intel_sdvo_dtd input_dtd;
14571b4c
ZW		 146};
147
148struct intel_sdvo_connector {
615fb93f
CW		 149 struct intel_connector base;
150
14571b4c
ZW		 151 /* Mark the type of connector */
152 uint16_t output_flag;
153
c3e5f67b 154 enum hdmi_force_audio force_audio;
7f36e7ed 155
14571b4c 156 /* This contains all current supported TV format */
40039750 157 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 158 int format_supported_num;
c5521706 159 struct drm_property *tv_format;
14571b4c 160
b9219c5e 161 /* add the property for the SDVO-TV */
c5521706
CW		 162 struct drm_property *left;
163 struct drm_property *right;
164 struct drm_property *top;
165 struct drm_property *bottom;
166 struct drm_property *hpos;
167 struct drm_property *vpos;
168 struct drm_property *contrast;
169 struct drm_property *saturation;
170 struct drm_property *hue;
171 struct drm_property *sharpness;
172 struct drm_property *flicker_filter;
173 struct drm_property *flicker_filter_adaptive;
174 struct drm_property *flicker_filter_2d;
175 struct drm_property *tv_chroma_filter;
176 struct drm_property *tv_luma_filter;
e044218a 177 struct drm_property *dot_crawl;
b9219c5e
ZY		 178
179 /* add the property for the SDVO-TV/LVDS */
c5521706 180 struct drm_property *brightness;
b9219c5e
ZY		 181
182 /* Add variable to record current setting for the above property */
183 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 184
b9219c5e
ZY		 185 /* this is to get the range of margin.*/
186 u32 max_hscan, max_vscan;
187 u32 max_hpos, cur_hpos;
188 u32 max_vpos, cur_vpos;
189 u32 cur_brightness, max_brightness;
190 u32 cur_contrast, max_contrast;
191 u32 cur_saturation, max_saturation;
192 u32 cur_hue, max_hue;
c5521706
CW		 193 u32 cur_sharpness, max_sharpness;
194 u32 cur_flicker_filter, max_flicker_filter;
195 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
196 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
197 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
198 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 199 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 200};
201
890f3359 202static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 203{
4ef69c7a 204 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 205}
206
df0e9248
CW		 207static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
208{
209 return container_of(intel_attached_encoder(connector),
210 struct intel_sdvo, base);
211}
212
615fb93f
CW		 213static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
214{
215 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
216}
217
fb7a46f3 218static bool
ea5b213a 219intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 220static bool
221intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
222 struct intel_sdvo_connector *intel_sdvo_connector,
223 int type);
224static bool
225intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
226 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 227
79e53945
JB		 228/**
229 * Writes the SDVOB or SDVOC with the given value, but always writes both
230 * SDVOB and SDVOC to work around apparent hardware issues (according to
231 * comments in the BIOS).
232 */
ea5b213a 233static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 234{
4ef69c7a 235 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 236 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 237 u32 bval = val, cval = val;
238 int i;
239
ea5b213a
CW		 240 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
241 I915_WRITE(intel_sdvo->sdvo_reg, val);
242 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 243 return;
244 }
245
ea5b213a 246 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 247 cval = I915_READ(SDVOC);
248 } else {
249 bval = I915_READ(SDVOB);
250 }
251 /*
252 * Write the registers twice for luck. Sometimes,
253 * writing them only once doesn't appear to 'stick'.
254 * The BIOS does this too. Yay, magic
255 */
256 for (i = 0; i < 2; i++)
257 {
258 I915_WRITE(SDVOB, bval);
259 I915_READ(SDVOB);
260 I915_WRITE(SDVOC, cval);
261 I915_READ(SDVOC);
262 }
263}
264
32aad86f 265static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 266{
79e53945
JB		 267 struct i2c_msg msgs[] = {
268 {
e957d772 269 .addr = intel_sdvo->slave_addr,
79e53945
JB		 270 .flags = 0,
271 .len = 1,
e957d772 272 .buf = &addr,
79e53945
JB		 273 },
274 {
e957d772 275 .addr = intel_sdvo->slave_addr,
79e53945
JB		 276 .flags = I2C_M_RD,
277 .len = 1,
e957d772 278 .buf = ch,
79e53945
JB		 279 }
280 };
32aad86f 281 int ret;
79e53945 282
f899fc64 283 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 284 return true;
79e53945 285
8a4c47f3 286 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 287 return false;
288}
289
79e53945
JB		 290#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
291/** Mapping of command numbers to names, for debug output */
005568be 292static const struct _sdvo_cmd_name {
e2f0ba97 293 u8 cmd;
2e88e40b 294 const char *name;
79e53945 295} sdvo_cmd_names[] = {
0206e353
AJ		 296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
335 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
336 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
339
340 /* Add the op code for SDVO enhancements */
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
381 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
382 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
385
386 /* HDMI op code */
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
403 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
404 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
405 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
406 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 407};
408
eef4eacb 409#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 410
ea5b213a 411static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 412 const void *args, int args_len)
79e53945 413{
79e53945
JB		 414 int i;
415
8a4c47f3 416 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 417 SDVO_NAME(intel_sdvo), cmd);
79e53945 418 for (i = 0; i < args_len; i++)
342dc382 419 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 420 for (; i < 8; i++)
342dc382 421 DRM_LOG_KMS(" ");
04ad327f 422 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 423 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 424 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 425 break;
426 }
427 }
04ad327f 428 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 429 DRM_LOG_KMS("(%02X)", cmd);
430 DRM_LOG_KMS("\n");
79e53945 431}
79e53945 432
e957d772
CW		 433static const char *cmd_status_names[] = {
434 "Power on",
435 "Success",
436 "Not supported",
437 "Invalid arg",
438 "Pending",
439 "Target not specified",
440 "Scaling not supported"
441};
442
32aad86f
CW		 443static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
444 const void *args, int args_len)
79e53945 445{
3bf3f452
BW		 446 u8 *buf, status;
447 struct i2c_msg *msgs;
448 int i, ret = true;
449
450 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
451 if (!buf)
452 return false;
453
454 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
455 if (!msgs)
456 return false;
79e53945 457
ea5b213a 458 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 459
460 for (i = 0; i < args_len; i++) {
e957d772
CW		 461 msgs[i].addr = intel_sdvo->slave_addr;
462 msgs[i].flags = 0;
463 msgs[i].len = 2;
464 msgs[i].buf = buf + 2 *i;
465 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
466 buf[2*i + 1] = ((u8*)args)[i];
467 }
468 msgs[i].addr = intel_sdvo->slave_addr;
469 msgs[i].flags = 0;
470 msgs[i].len = 2;
471 msgs[i].buf = buf + 2*i;
472 buf[2*i + 0] = SDVO_I2C_OPCODE;
473 buf[2*i + 1] = cmd;
474
475 /* the following two are to read the response */
476 status = SDVO_I2C_CMD_STATUS;
477 msgs[i+1].addr = intel_sdvo->slave_addr;
478 msgs[i+1].flags = 0;
479 msgs[i+1].len = 1;
480 msgs[i+1].buf = &status;
481
482 msgs[i+2].addr = intel_sdvo->slave_addr;
483 msgs[i+2].flags = I2C_M_RD;
484 msgs[i+2].len = 1;
485 msgs[i+2].buf = &status;
486
487 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
488 if (ret < 0) {
489 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 490 ret = false;
491 goto out;
e957d772
CW		 492 }
493 if (ret != i+3) {
494 /* failure in I2C transfer */
495 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 496 ret = false;
e957d772
CW		 497 }
498
3bf3f452
BW		 499out:
500 kfree(msgs);
501 kfree(buf);
502 return ret;
79e53945
JB		 503}
504
b5c616a7
CW		 505static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
506 void *response, int response_len)
79e53945 507{
b5c616a7
CW		 508 u8 retry = 5;
509 u8 status;
33b52961 510 int i;
79e53945 511
d121a5d2
CW		 512 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
513
b5c616a7
CW		 514 /*
515 * The documentation states that all commands will be
516 * processed within 15µs, and that we need only poll
517 * the status byte a maximum of 3 times in order for the
518 * command to be complete.
519 *
520 * Check 5 times in case the hardware failed to read the docs.
521 */
d121a5d2
CW		 522 if (!intel_sdvo_read_byte(intel_sdvo,
523 SDVO_I2C_CMD_STATUS,
524 &status))
525 goto log_fail;
526
527 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
528 udelay(15);
b5c616a7
CW		 529 if (!intel_sdvo_read_byte(intel_sdvo,
530 SDVO_I2C_CMD_STATUS,
531 &status))
d121a5d2
CW		 532 goto log_fail;
533 }
b5c616a7 534
79e53945 535 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 536 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 537 else
342dc382 538 DRM_LOG_KMS("(??? %d)", status);
79e53945 539
b5c616a7
CW		 540 if (status != SDVO_CMD_STATUS_SUCCESS)
541 goto log_fail;
79e53945 542
b5c616a7
CW		 543 /* Read the command response */
544 for (i = 0; i < response_len; i++) {
545 if (!intel_sdvo_read_byte(intel_sdvo,
546 SDVO_I2C_RETURN_0 + i,
547 &((u8 *)response)[i]))
548 goto log_fail;
e957d772 549 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 550 }
b5c616a7 551 DRM_LOG_KMS("\n");
b5c616a7 552 return true;
79e53945 553
b5c616a7 554log_fail:
d121a5d2 555 DRM_LOG_KMS("... failed\n");
b5c616a7 556 return false;
79e53945
JB		 557}
558
b358d0a6 559static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 560{
561 if (mode->clock >= 100000)
562 return 1;
563 else if (mode->clock >= 50000)
564 return 2;
565 else
566 return 4;
567}
568
e957d772
CW		 569static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
570 u8 ddc_bus)
79e53945 571{
d121a5d2 572 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 573 return intel_sdvo_write_cmd(intel_sdvo,
574 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
575 &ddc_bus, 1);
79e53945
JB		 576}
577
32aad86f 578static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 579{
d121a5d2
CW		 580 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
581 return false;
582
583 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 584}
79e53945 585
32aad86f
CW		 586static bool
587intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
588{
589 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
590 return false;
79e53945 591
32aad86f
CW		 592 return intel_sdvo_read_response(intel_sdvo, value, len);
593}
79e53945 594
32aad86f
CW		 595static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
596{
597 struct intel_sdvo_set_target_input_args targets = {0};
598 return intel_sdvo_set_value(intel_sdvo,
599 SDVO_CMD_SET_TARGET_INPUT,
600 &targets, sizeof(targets));
79e53945
JB		 601}
602
603/**
604 * Return whether each input is trained.
605 *
606 * This function is making an assumption about the layout of the response,
607 * which should be checked against the docs.
608 */
ea5b213a 609static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 610{
611 struct intel_sdvo_get_trained_inputs_response response;
79e53945 612
1a3665c8 613 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 614 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
615 &response, sizeof(response)))
79e53945
JB		 616 return false;
617
618 *input_1 = response.input0_trained;
619 *input_2 = response.input1_trained;
620 return true;
621}
622
ea5b213a 623static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 624 u16 outputs)
625{
32aad86f
CW		 626 return intel_sdvo_set_value(intel_sdvo,
627 SDVO_CMD_SET_ACTIVE_OUTPUTS,
628 &outputs, sizeof(outputs));
79e53945
JB		 629}
630
ea5b213a 631static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 632 int mode)
633{
32aad86f 634 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 635
636 switch (mode) {
637 case DRM_MODE_DPMS_ON:
638 state = SDVO_ENCODER_STATE_ON;
639 break;
640 case DRM_MODE_DPMS_STANDBY:
641 state = SDVO_ENCODER_STATE_STANDBY;
642 break;
643 case DRM_MODE_DPMS_SUSPEND:
644 state = SDVO_ENCODER_STATE_SUSPEND;
645 break;
646 case DRM_MODE_DPMS_OFF:
647 state = SDVO_ENCODER_STATE_OFF;
648 break;
649 }
650
32aad86f
CW		 651 return intel_sdvo_set_value(intel_sdvo,
652 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 653}
654
ea5b213a 655static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 656 int *clock_min,
657 int *clock_max)
658{
659 struct intel_sdvo_pixel_clock_range clocks;
79e53945 660
1a3665c8 661 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 662 if (!intel_sdvo_get_value(intel_sdvo,
663 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
664 &clocks, sizeof(clocks)))
79e53945
JB		 665 return false;
666
667 /* Convert the values from units of 10 kHz to kHz. */
668 *clock_min = clocks.min * 10;
669 *clock_max = clocks.max * 10;
79e53945
JB		 670 return true;
671}
672
ea5b213a 673static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 674 u16 outputs)
675{
32aad86f
CW		 676 return intel_sdvo_set_value(intel_sdvo,
677 SDVO_CMD_SET_TARGET_OUTPUT,
678 &outputs, sizeof(outputs));
79e53945
JB		 679}
680
ea5b213a 681static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 682 struct intel_sdvo_dtd *dtd)
683{
32aad86f
CW		 684 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
685 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 686}
687
ea5b213a 688static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 689 struct intel_sdvo_dtd *dtd)
690{
ea5b213a 691 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 692 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
693}
694
ea5b213a 695static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 696 struct intel_sdvo_dtd *dtd)
697{
ea5b213a 698 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 699 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
700}
701
e2f0ba97 702static bool
ea5b213a 703intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 704 uint16_t clock,
705 uint16_t width,
706 uint16_t height)
707{
708 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 709
e642c6f1 710 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 711 args.clock = clock;
712 args.width = width;
713 args.height = height;
e642c6f1 714 args.interlace = 0;
12682a97 715
ea5b213a
CW		 716 if (intel_sdvo->is_lvds &&
717 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
718 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 719 args.scaled = 1;
720
32aad86f
CW		 721 return intel_sdvo_set_value(intel_sdvo,
722 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
723 &args, sizeof(args));
e2f0ba97
JB		 724}
725
ea5b213a 726static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 727 struct intel_sdvo_dtd *dtd)
728{
1a3665c8
CW		 729 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
730 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 731 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
732 &dtd->part1, sizeof(dtd->part1)) &&
733 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
734 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 735}
79e53945 736
ea5b213a 737static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 738{
32aad86f 739 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 740}
741
e2f0ba97 742static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 743 const struct drm_display_mode *mode)
79e53945 744{
e2f0ba97
JB		 745 uint16_t width, height;
746 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
747 uint16_t h_sync_offset, v_sync_offset;
6651819b 748 int mode_clock;
79e53945 749
c6ebd4c0
DV		 750 width = mode->hdisplay;
751 height = mode->vdisplay;
79e53945
JB		 752
753 /* do some mode translations */
c6ebd4c0
DV		 754 h_blank_len = mode->htotal - mode->hdisplay;
755 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 756
c6ebd4c0
DV		 757 v_blank_len = mode->vtotal - mode->vdisplay;
758 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 759
c6ebd4c0
DV		 760 h_sync_offset = mode->hsync_start - mode->hdisplay;
761 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 762
6651819b
DV		 763 mode_clock = mode->clock;
764 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
765 mode_clock /= 10;
766 dtd->part1.clock = mode_clock;
767
e2f0ba97
JB		 768 dtd->part1.h_active = width & 0xff;
769 dtd->part1.h_blank = h_blank_len & 0xff;
770 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 771 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 772 dtd->part1.v_active = height & 0xff;
773 dtd->part1.v_blank = v_blank_len & 0xff;
774 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 775 ((v_blank_len >> 8) & 0xf);
776
171a9e96 777 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 778 dtd->part2.h_sync_width = h_sync_len & 0xff;
779 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 780 (v_sync_len & 0xf);
e2f0ba97 781 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 782 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
783 ((v_sync_len & 0x30) >> 4);
784
e2f0ba97 785 dtd->part2.dtd_flags = 0x18;
79e53945 786 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
e2f0ba97 787 dtd->part2.dtd_flags |= 0x2;
79e53945 788 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
e2f0ba97
JB		 789 dtd->part2.dtd_flags |= 0x4;
790
791 dtd->part2.sdvo_flags = 0;
792 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
793 dtd->part2.reserved = 0;
794}
795
796static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 797 const struct intel_sdvo_dtd *dtd)
e2f0ba97 798{
e2f0ba97
JB		 799 mode->hdisplay = dtd->part1.h_active;
800 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
801 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 802 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 803 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
804 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
805 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
806 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
807
808 mode->vdisplay = dtd->part1.v_active;
809 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
810 mode->vsync_start = mode->vdisplay;
811 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 812 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 813 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
814 mode->vsync_end = mode->vsync_start +
815 (dtd->part2.v_sync_off_width & 0xf);
816 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
817 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
818 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
819
820 mode->clock = dtd->part1.clock * 10;
821
171a9e96 822 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
e2f0ba97
JB		 823 if (dtd->part2.dtd_flags & 0x2)
824 mode->flags |= DRM_MODE_FLAG_PHSYNC;
825 if (dtd->part2.dtd_flags & 0x4)
826 mode->flags |= DRM_MODE_FLAG_PVSYNC;
827}
828
e27d8538 829static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 830{
e27d8538 831 struct intel_sdvo_encode encode;
e2f0ba97 832
1a3665c8 833 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 834 return intel_sdvo_get_value(intel_sdvo,
835 SDVO_CMD_GET_SUPP_ENCODE,
836 &encode, sizeof(encode));
e2f0ba97
JB		 837}
838
ea5b213a 839static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 840 uint8_t mode)
e2f0ba97 841{
32aad86f 842 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 843}
844
ea5b213a 845static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 846 uint8_t mode)
847{
32aad86f 848 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 849}
850
851#if 0
ea5b213a 852static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 853{
854 int i, j;
855 uint8_t set_buf_index[2];
856 uint8_t av_split;
857 uint8_t buf_size;
858 uint8_t buf[48];
859 uint8_t *pos;
860
32aad86f 861 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 862
863 for (i = 0; i <= av_split; i++) {
864 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 865 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 866 set_buf_index, 2);
c751ce4f
EA		 867 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
868 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 869
870 pos = buf;
871 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 872 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 873 NULL, 0);
c751ce4f 874 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 875 pos += 8;
876 }
877 }
878}
879#endif
880
3c17fe4b 881static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 882{
883 struct dip_infoframe avi_if = {
884 .type = DIP_TYPE_AVI,
3c17fe4b 885 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 886 .len = DIP_LEN_AVI,
887 };
3c17fe4b
DH		 888 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
889 uint8_t set_buf_index[2] = { 1, 0 };
81014b9d
DV		 890 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
891 uint64_t *data = (uint64_t *)sdvo_data;
3c17fe4b
DH		 892 unsigned i;
893
894 intel_dip_infoframe_csum(&avi_if);
895
81014b9d
DV		 896 /* sdvo spec says that the ecc is handled by the hw, and it looks like
897 * we must not send the ecc field, either. */
898 memcpy(sdvo_data, &avi_if, 3);
899 sdvo_data[3] = avi_if.checksum;
900 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
901
d121a5d2
CW		 902 if (!intel_sdvo_set_value(intel_sdvo,
903 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 904 set_buf_index, 2))
905 return false;
906
81014b9d 907 for (i = 0; i < sizeof(sdvo_data); i += 8) {
d121a5d2
CW		 908 if (!intel_sdvo_set_value(intel_sdvo,
909 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 910 data, 8))
911 return false;
912 data++;
913 }
e2f0ba97 914
d121a5d2
CW		 915 return intel_sdvo_set_value(intel_sdvo,
916 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 917 &tx_rate, 1);
e2f0ba97
JB		 918}
919
32aad86f 920static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 921{
ce6feabd 922 struct intel_sdvo_tv_format format;
40039750 923 uint32_t format_map;
ce6feabd 924
40039750 925 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 926 memset(&format, 0, sizeof(format));
32aad86f 927 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 928
32aad86f
CW		 929 BUILD_BUG_ON(sizeof(format) != 6);
930 return intel_sdvo_set_value(intel_sdvo,
931 SDVO_CMD_SET_TV_FORMAT,
932 &format, sizeof(format));
7026d4ac
ZW		 933}
934
32aad86f
CW		 935static bool
936intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
937 struct drm_display_mode *mode)
e2f0ba97 938{
32aad86f 939 struct intel_sdvo_dtd output_dtd;
79e53945 940
32aad86f
CW		 941 if (!intel_sdvo_set_target_output(intel_sdvo,
942 intel_sdvo->attached_output))
943 return false;
e2f0ba97 944
32aad86f
CW		 945 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
946 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
947 return false;
e2f0ba97 948
32aad86f
CW		 949 return true;
950}
951
952static bool
953intel_sdvo_set_input_timings_for_mode(struct intel_sdvo *intel_sdvo,
954 struct drm_display_mode *mode,
955 struct drm_display_mode *adjusted_mode)
956{
32aad86f
CW		 957 /* Reset the input timing to the screen. Assume always input 0. */
958 if (!intel_sdvo_set_target_input(intel_sdvo))
959 return false;
e2f0ba97 960
32aad86f
CW		 961 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
962 mode->clock / 10,
963 mode->hdisplay,
964 mode->vdisplay))
965 return false;
e2f0ba97 966
32aad86f 967 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
6c9547ff 968 &intel_sdvo->input_dtd))
32aad86f 969 return false;
e2f0ba97 970
6c9547ff 971 intel_sdvo_get_mode_from_dtd(adjusted_mode, &intel_sdvo->input_dtd);
79e53945 972
32aad86f
CW		 973 return true;
974}
12682a97 975
32aad86f
CW		 976static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
977 struct drm_display_mode *mode,
978 struct drm_display_mode *adjusted_mode)
979{
890f3359 980 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 981 int multiplier;
12682a97 982
32aad86f
CW		 983 /* We need to construct preferred input timings based on our
984 * output timings. To do that, we have to set the output
985 * timings, even though this isn't really the right place in
986 * the sequence to do it. Oh well.
987 */
988 if (intel_sdvo->is_tv) {
989 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
990 return false;
12682a97 991
c74696b9
PR		 992 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
993 mode,
994 adjusted_mode);
ea5b213a 995 } else if (intel_sdvo->is_lvds) {
32aad86f 996 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 997 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 998 return false;
12682a97 999
c74696b9
PR		 1000 (void) intel_sdvo_set_input_timings_for_mode(intel_sdvo,
1001 mode,
1002 adjusted_mode);
e2f0ba97 1003 }
32aad86f
CW		 1004
1005 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1006 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1007 */
6c9547ff
CW		 1008 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1009 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1010
e2f0ba97
JB		 1011 return true;
1012}
1013
1014static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1015 struct drm_display_mode *mode,
1016 struct drm_display_mode *adjusted_mode)
1017{
1018 struct drm_device *dev = encoder->dev;
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1020 struct drm_crtc *crtc = encoder->crtc;
1021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1022 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1023 u32 sdvox;
e2f0ba97 1024 struct intel_sdvo_in_out_map in_out;
6651819b 1025 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1026 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1027 int rate;
e2f0ba97
JB		 1028
1029 if (!mode)
1030 return;
1031
1032 /* First, set the input mapping for the first input to our controlled
1033 * output. This is only correct if we're a single-input device, in
1034 * which case the first input is the output from the appropriate SDVO
1035 * channel on the motherboard. In a two-input device, the first input
1036 * will be SDVOB and the second SDVOC.
1037 */
ea5b213a 1038 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1039 in_out.in1 = 0;
1040
c74696b9
PR		 1041 intel_sdvo_set_value(intel_sdvo,
1042 SDVO_CMD_SET_IN_OUT_MAP,
1043 &in_out, sizeof(in_out));
e2f0ba97 1044
6c9547ff
CW		 1045 /* Set the output timings to the screen */
1046 if (!intel_sdvo_set_target_output(intel_sdvo,
1047 intel_sdvo->attached_output))
1048 return;
e2f0ba97 1049
6651819b
DV		 1050 /* lvds has a special fixed output timing. */
1051 if (intel_sdvo->is_lvds)
1052 intel_sdvo_get_dtd_from_mode(&output_dtd,
1053 intel_sdvo->sdvo_lvds_fixed_mode);
1054 else
1055 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
1056 (void) intel_sdvo_set_output_timing(intel_sdvo, &output_dtd);
79e53945
JB		 1057
1058 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1059 if (!intel_sdvo_set_target_input(intel_sdvo))
1060 return;
79e53945 1061
97aaf910
CW		 1062 if (intel_sdvo->has_hdmi_monitor) {
1063 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1064 intel_sdvo_set_colorimetry(intel_sdvo,
1065 SDVO_COLORIMETRY_RGB256);
1066 intel_sdvo_set_avi_infoframe(intel_sdvo);
1067 } else
1068 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1069
6c9547ff
CW		 1070 if (intel_sdvo->is_tv &&
1071 !intel_sdvo_set_tv_format(intel_sdvo))
1072 return;
e2f0ba97 1073
6651819b
DV		 1074 /* We have tried to get input timing in mode_fixup, and filled into
1075 * adjusted_mode.
1076 */
1077 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c74696b9 1078 (void) intel_sdvo_set_input_timing(intel_sdvo, &input_dtd);
79e53945 1079
6c9547ff
CW		 1080 switch (pixel_multiplier) {
1081 default:
32aad86f
CW		 1082 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1083 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1084 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1085 }
32aad86f
CW		 1086 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1087 return;
79e53945
JB		 1088
1089 /* Set the SDVO control regs. */
a6c45cf0 1090 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1091 /* The real mode polarity is set by the SDVO commands, using
1092 * struct intel_sdvo_dtd. */
1093 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1094 if (intel_sdvo->is_hdmi)
1095 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1096 if (INTEL_INFO(dev)->gen < 5)
1097 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1098 } else {
6c9547ff 1099 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1100 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1101 case SDVOB:
1102 sdvox &= SDVOB_PRESERVE_MASK;
1103 break;
1104 case SDVOC:
1105 sdvox &= SDVOC_PRESERVE_MASK;
1106 break;
1107 }
1108 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1109 }
3573c410
PZ		 1110
1111 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1112 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1113 else
1114 sdvox |= TRANSCODER(intel_crtc->pipe);
1115
da79de97 1116 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1117 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1118
a6c45cf0 1119 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1120 /* done in crtc_mode_set as the dpll_md reg must be written early */
1121 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1122 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1123 } else {
6c9547ff 1124 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1125 }
1126
6714afb1
CW		 1127 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1128 INTEL_INFO(dev)->gen < 5)
12682a97 1129 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1130 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1131}
1132
1133static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1134{
1135 struct drm_device *dev = encoder->dev;
1136 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1137 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1138 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1139 u32 temp;
1140
1141 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1142 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1143 if (0)
ea5b213a 1144 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1145
1146 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1147 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1148 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1149 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1150 }
1151 }
1152 } else {
1153 bool input1, input2;
1154 int i;
1155 u8 status;
1156
ea5b213a 1157 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1158 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1159 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1160 for (i = 0; i < 2; i++)
9d0498a2 1161 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1162
32aad86f 1163 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1164 /* Warn if the device reported failure to sync.
1165 * A lot of SDVO devices fail to notify of sync, but it's
1166 * a given it the status is a success, we succeeded.
1167 */
1168 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1169 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1170 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1171 }
1172
1173 if (0)
ea5b213a
CW		 1174 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1175 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1176 }
1177 return;
1178}
1179
79e53945
JB		 1180static int intel_sdvo_mode_valid(struct drm_connector *connector,
1181 struct drm_display_mode *mode)
1182{
df0e9248 1183 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1184
1185 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1186 return MODE_NO_DBLESCAN;
1187
ea5b213a 1188 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1189 return MODE_CLOCK_LOW;
1190
ea5b213a 1191 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1192 return MODE_CLOCK_HIGH;
1193
8545423a 1194 if (intel_sdvo->is_lvds) {
ea5b213a 1195 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1196 return MODE_PANEL;
1197
ea5b213a 1198 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1199 return MODE_PANEL;
1200 }
1201
79e53945
JB		 1202 return MODE_OK;
1203}
1204
ea5b213a 1205static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1206{
1a3665c8 1207 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1208 if (!intel_sdvo_get_value(intel_sdvo,
1209 SDVO_CMD_GET_DEVICE_CAPS,
1210 caps, sizeof(*caps)))
1211 return false;
1212
1213 DRM_DEBUG_KMS("SDVO capabilities:\n"
1214 " vendor_id: %d\n"
1215 " device_id: %d\n"
1216 " device_rev_id: %d\n"
1217 " sdvo_version_major: %d\n"
1218 " sdvo_version_minor: %d\n"
1219 " sdvo_inputs_mask: %d\n"
1220 " smooth_scaling: %d\n"
1221 " sharp_scaling: %d\n"
1222 " up_scaling: %d\n"
1223 " down_scaling: %d\n"
1224 " stall_support: %d\n"
1225 " output_flags: %d\n",
1226 caps->vendor_id,
1227 caps->device_id,
1228 caps->device_rev_id,
1229 caps->sdvo_version_major,
1230 caps->sdvo_version_minor,
1231 caps->sdvo_inputs_mask,
1232 caps->smooth_scaling,
1233 caps->sharp_scaling,
1234 caps->up_scaling,
1235 caps->down_scaling,
1236 caps->stall_support,
1237 caps->output_flags);
1238
1239 return true;
79e53945
JB		 1240}
1241
cc68c81a 1242static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945
JB		 1243{
1244 u8 response[2];
79e53945 1245
32aad86f
CW		 1246 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1247 &response, 2) && response[0];
79e53945
JB		 1248}
1249
cc68c81a 1250static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1251{
cc68c81a 1252 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1253
cc68c81a 1254 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1255}
1256
fb7a46f3 1257static bool
ea5b213a 1258intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1259{
bc65212c 1260 /* Is there more than one type of output? */
2294488d 1261 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1262}
1263
f899fc64 1264static struct edid *
e957d772 1265intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1266{
e957d772
CW		 1267 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1268 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1269}
1270
ff482d83
CW		 1271/* Mac mini hack -- use the same DDC as the analog connector */
1272static struct edid *
1273intel_sdvo_get_analog_edid(struct drm_connector *connector)
1274{
f899fc64 1275 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1276
0c1dab89 1277 return drm_get_edid(connector,
3bd7d909
DK		 1278 intel_gmbus_get_adapter(dev_priv,
1279 dev_priv->crt_ddc_pin));
ff482d83
CW		 1280}
1281
c43b5634 1282static enum drm_connector_status
8bf38485 1283intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1284{
df0e9248 1285 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1286 enum drm_connector_status status;
1287 struct edid *edid;
9dff6af8 1288
e957d772 1289 edid = intel_sdvo_get_edid(connector);
57cdaf90 1290
ea5b213a 1291 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1292 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1293
7c3f0a27
ZY		 1294 /*
1295 * Don't use the 1 as the argument of DDC bus switch to get
1296 * the EDID. It is used for SDVO SPD ROM.
1297 */
9d1a903d 1298 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1299 intel_sdvo->ddc_bus = ddc;
1300 edid = intel_sdvo_get_edid(connector);
1301 if (edid)
7c3f0a27 1302 break;
7c3f0a27 1303 }
e957d772
CW		 1304 /*
1305 * If we found the EDID on the other bus,
1306 * assume that is the correct DDC bus.
1307 */
1308 if (edid == NULL)
1309 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1310 }
9d1a903d
CW		 1311
1312 /*
1313 * When there is no edid and no monitor is connected with VGA
1314 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1315 */
ff482d83
CW		 1316 if (edid == NULL)
1317 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1318
2f551c84 1319 status = connector_status_unknown;
9dff6af8 1320 if (edid != NULL) {
149c36a3 1321 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1322 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1323 status = connector_status_connected;
da79de97
CW		 1324 if (intel_sdvo->is_hdmi) {
1325 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1326 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1327 }
13946743
CW		 1328 } else
1329 status = connector_status_disconnected;
149c36a3 1330 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1331 kfree(edid);
1332 }
7f36e7ed
CW		 1333
1334 if (status == connector_status_connected) {
1335 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1336 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1337 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1338 }
1339
2b8d33f7 1340 return status;
9dff6af8
ML		 1341}
1342
52220085
CW		 1343static bool
1344intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1345 struct edid *edid)
1346{
1347 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1348 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1349
1350 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1351 connector_is_digital, monitor_is_digital);
1352 return connector_is_digital == monitor_is_digital;
1353}
1354
7b334fcb 1355static enum drm_connector_status
930a9e28 1356intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1357{
fb7a46f3 1358 uint16_t response;
df0e9248 1359 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1360 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1361 enum drm_connector_status ret;
79e53945 1362
32aad86f 1363 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1364 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1365 return connector_status_unknown;
ba84cd1f
CW		 1366
1367 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1368 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
d09c23de 1369 mdelay(30);
ba84cd1f 1370
32aad86f
CW		 1371 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1372 return connector_status_unknown;
79e53945 1373
e957d772
CW		 1374 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1375 response & 0xff, response >> 8,
1376 intel_sdvo_connector->output_flag);
e2f0ba97 1377
fb7a46f3 1378 if (response == 0)
79e53945 1379 return connector_status_disconnected;
fb7a46f3 1380
ea5b213a 1381 intel_sdvo->attached_output = response;
14571b4c 1382
97aaf910
CW		 1383 intel_sdvo->has_hdmi_monitor = false;
1384 intel_sdvo->has_hdmi_audio = false;
1385
615fb93f 1386 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1387 ret = connector_status_disconnected;
13946743 1388 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1389 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1390 else {
1391 struct edid *edid;
1392
1393 /* if we have an edid check it matches the connection */
1394 edid = intel_sdvo_get_edid(connector);
1395 if (edid == NULL)
1396 edid = intel_sdvo_get_analog_edid(connector);
1397 if (edid != NULL) {
52220085
CW		 1398 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1399 edid))
13946743 1400 ret = connector_status_connected;
52220085
CW		 1401 else
1402 ret = connector_status_disconnected;
1403
13946743
CW		 1404 connector->display_info.raw_edid = NULL;
1405 kfree(edid);
1406 } else
1407 ret = connector_status_connected;
1408 }
14571b4c
ZW		 1409
1410 /* May update encoder flag for like clock for SDVO TV, etc.*/
1411 if (ret == connector_status_connected) {
ea5b213a
CW		 1412 intel_sdvo->is_tv = false;
1413 intel_sdvo->is_lvds = false;
1414 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1415
1416 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1417 intel_sdvo->is_tv = true;
1418 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1419 }
1420 if (response & SDVO_LVDS_MASK)
8545423a 1421 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1422 }
14571b4c
ZW		 1423
1424 return ret;
79e53945
JB		 1425}
1426
e2f0ba97 1427static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1428{
ff482d83 1429 struct edid *edid;
79e53945
JB		 1430
1431 /* set the bus switch and get the modes */
e957d772 1432 edid = intel_sdvo_get_edid(connector);
79e53945 1433
57cdaf90
KP		 1434 /*
1435 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1436 * link between analog and digital outputs. So, if the regular SDVO
1437 * DDC fails, check to see if the analog output is disconnected, in
1438 * which case we'll look there for the digital DDC data.
e2f0ba97 1439 */
f899fc64
CW		 1440 if (edid == NULL)
1441 edid = intel_sdvo_get_analog_edid(connector);
1442
ff482d83 1443 if (edid != NULL) {
52220085
CW		 1444 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1445 edid)) {
0c1dab89
CW		 1446 drm_mode_connector_update_edid_property(connector, edid);
1447 drm_add_edid_modes(connector, edid);
1448 }
13946743 1449
ff482d83
CW		 1450 connector->display_info.raw_edid = NULL;
1451 kfree(edid);
e2f0ba97 1452 }
e2f0ba97
JB		 1453}
1454
1455/*
1456 * Set of SDVO TV modes.
1457 * Note! This is in reply order (see loop in get_tv_modes).
1458 * XXX: all 60Hz refresh?
1459 */
b1f559ec 1460static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1461 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1462 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1463 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1464 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1465 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1467 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1468 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1469 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1470 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1471 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1473 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1474 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1475 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1476 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1477 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1478 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1479 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1480 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1482 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1483 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1485 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1486 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1487 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1488 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1489 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1490 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1491 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1492 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1493 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1494 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1495 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1497 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1498 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1499 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1500 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1501 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1502 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1503 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1504 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1505 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1506 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1507 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1508 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1509 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1510 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1512 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1513 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1514 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1515 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1516 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1517 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1518};
1519
1520static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1521{
df0e9248 1522 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1523 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1524 uint32_t reply = 0, format_map = 0;
1525 int i;
e2f0ba97
JB		 1526
1527 /* Read the list of supported input resolutions for the selected TV
1528 * format.
1529 */
40039750 1530 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1531 memcpy(&tv_res, &format_map,
32aad86f 1532 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1533
32aad86f
CW		 1534 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1535 return;
ce6feabd 1536
32aad86f 1537 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1538 if (!intel_sdvo_write_cmd(intel_sdvo,
1539 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1540 &tv_res, sizeof(tv_res)))
1541 return;
1542 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1543 return;
1544
1545 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1546 if (reply & (1 << i)) {
1547 struct drm_display_mode *nmode;
1548 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1549 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1550 if (nmode)
1551 drm_mode_probed_add(connector, nmode);
1552 }
e2f0ba97
JB		 1553}
1554
7086c87f
ML		 1555static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1556{
df0e9248 1557 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1558 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1559 struct drm_display_mode *newmode;
7086c87f
ML		 1560
1561 /*
1562 * Attempt to get the mode list from DDC.
1563 * Assume that the preferred modes are
1564 * arranged in priority order.
1565 */
f899fc64 1566 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1567 if (list_empty(&connector->probed_modes) == false)
12682a97 1568 goto end;
7086c87f
ML		 1569
1570 /* Fetch modes from VBT */
1571 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1572 newmode = drm_mode_duplicate(connector->dev,
1573 dev_priv->sdvo_lvds_vbt_mode);
1574 if (newmode != NULL) {
1575 /* Guarantee the mode is preferred */
1576 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1577 DRM_MODE_TYPE_DRIVER);
1578 drm_mode_probed_add(connector, newmode);
1579 }
1580 }
12682a97 1581
1582end:
1583 list_for_each_entry(newmode, &connector->probed_modes, head) {
1584 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1585 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1586 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1587
8545423a 1588 intel_sdvo->is_lvds = true;
12682a97 1589 break;
1590 }
1591 }
1592
7086c87f
ML		 1593}
1594
e2f0ba97
JB		 1595static int intel_sdvo_get_modes(struct drm_connector *connector)
1596{
615fb93f 1597 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1598
615fb93f 1599 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1600 intel_sdvo_get_tv_modes(connector);
615fb93f 1601 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1602 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1603 else
1604 intel_sdvo_get_ddc_modes(connector);
1605
32aad86f 1606 return !list_empty(&connector->probed_modes);
79e53945
JB		 1607}
1608
fcc8d672
CW		 1609static void
1610intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1611{
615fb93f 1612 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1613 struct drm_device *dev = connector->dev;
1614
c5521706
CW		 1615 if (intel_sdvo_connector->left)
1616 drm_property_destroy(dev, intel_sdvo_connector->left);
1617 if (intel_sdvo_connector->right)
1618 drm_property_destroy(dev, intel_sdvo_connector->right);
1619 if (intel_sdvo_connector->top)
1620 drm_property_destroy(dev, intel_sdvo_connector->top);
1621 if (intel_sdvo_connector->bottom)
1622 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1623 if (intel_sdvo_connector->hpos)
1624 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1625 if (intel_sdvo_connector->vpos)
1626 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1627 if (intel_sdvo_connector->saturation)
1628 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1629 if (intel_sdvo_connector->contrast)
1630 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1631 if (intel_sdvo_connector->hue)
1632 drm_property_destroy(dev, intel_sdvo_connector->hue);
1633 if (intel_sdvo_connector->sharpness)
1634 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1635 if (intel_sdvo_connector->flicker_filter)
1636 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1637 if (intel_sdvo_connector->flicker_filter_2d)
1638 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1639 if (intel_sdvo_connector->flicker_filter_adaptive)
1640 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1641 if (intel_sdvo_connector->tv_luma_filter)
1642 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1643 if (intel_sdvo_connector->tv_chroma_filter)
1644 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1645 if (intel_sdvo_connector->dot_crawl)
1646 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1647 if (intel_sdvo_connector->brightness)
1648 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1649}
1650
79e53945
JB		 1651static void intel_sdvo_destroy(struct drm_connector *connector)
1652{
615fb93f 1653 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1654
c5521706 1655 if (intel_sdvo_connector->tv_format)
ce6feabd 1656 drm_property_destroy(connector->dev,
c5521706 1657 intel_sdvo_connector->tv_format);
b9219c5e 1658
d2a82a6f 1659 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1660 drm_sysfs_connector_remove(connector);
1661 drm_connector_cleanup(connector);
d2a82a6f 1662 kfree(connector);
79e53945
JB		 1663}
1664
1aad7ac0
CW		 1665static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1666{
1667 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1668 struct edid *edid;
1669 bool has_audio = false;
1670
1671 if (!intel_sdvo->is_hdmi)
1672 return false;
1673
1674 edid = intel_sdvo_get_edid(connector);
1675 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1676 has_audio = drm_detect_monitor_audio(edid);
1677
1678 return has_audio;
1679}
1680
ce6feabd
ZY		 1681static int
1682intel_sdvo_set_property(struct drm_connector *connector,
1683 struct drm_property *property,
1684 uint64_t val)
1685{
df0e9248 1686 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1687 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1688 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1689 uint16_t temp_value;
32aad86f
CW		 1690 uint8_t cmd;
1691 int ret;
ce6feabd
ZY		 1692
1693 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1694 if (ret)
1695 return ret;
ce6feabd 1696
3f43c48d 1697 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1698 int i = val;
1699 bool has_audio;
1700
1701 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1702 return 0;
1703
1aad7ac0 1704 intel_sdvo_connector->force_audio = i;
7f36e7ed 1705
c3e5f67b 1706 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1707 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1708 else
c3e5f67b 1709 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1710
1aad7ac0 1711 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1712 return 0;
7f36e7ed 1713
1aad7ac0 1714 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1715 goto done;
1716 }
1717
e953fd7b
CW		 1718 if (property == dev_priv->broadcast_rgb_property) {
1719 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1720 return 0;
1721
e953fd7b 1722 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1723 goto done;
1724 }
1725
c5521706
CW		 1726#define CHECK_PROPERTY(name, NAME) \
1727 if (intel_sdvo_connector->name == property) { \
1728 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1729 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1730 cmd = SDVO_CMD_SET_##NAME; \
1731 intel_sdvo_connector->cur_##name = temp_value; \
1732 goto set_value; \
1733 }
1734
1735 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1736 if (val >= TV_FORMAT_NUM)
1737 return -EINVAL;
1738
40039750 1739 if (intel_sdvo->tv_format_index ==
615fb93f 1740 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1741 return 0;
ce6feabd 1742
40039750 1743 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1744 goto done;
32aad86f 1745 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1746 temp_value = val;
c5521706 1747 if (intel_sdvo_connector->left == property) {
b9219c5e 1748 drm_connector_property_set_value(connector,
c5521706 1749 intel_sdvo_connector->right, val);
615fb93f 1750 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1751 return 0;
b9219c5e 1752
615fb93f
CW		 1753 intel_sdvo_connector->left_margin = temp_value;
1754 intel_sdvo_connector->right_margin = temp_value;
1755 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1756 intel_sdvo_connector->left_margin;
b9219c5e 1757 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1758 goto set_value;
1759 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1760 drm_connector_property_set_value(connector,
c5521706 1761 intel_sdvo_connector->left, val);
615fb93f 1762 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1763 return 0;
b9219c5e 1764
615fb93f
CW		 1765 intel_sdvo_connector->left_margin = temp_value;
1766 intel_sdvo_connector->right_margin = temp_value;
1767 temp_value = intel_sdvo_connector->max_hscan -
1768 intel_sdvo_connector->left_margin;
b9219c5e 1769 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1770 goto set_value;
1771 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1772 drm_connector_property_set_value(connector,
c5521706 1773 intel_sdvo_connector->bottom, val);
615fb93f 1774 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1775 return 0;
b9219c5e 1776
615fb93f
CW		 1777 intel_sdvo_connector->top_margin = temp_value;
1778 intel_sdvo_connector->bottom_margin = temp_value;
1779 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1780 intel_sdvo_connector->top_margin;
b9219c5e 1781 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1782 goto set_value;
1783 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1784 drm_connector_property_set_value(connector,
c5521706 1785 intel_sdvo_connector->top, val);
615fb93f 1786 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1787 return 0;
1788
615fb93f
CW		 1789 intel_sdvo_connector->top_margin = temp_value;
1790 intel_sdvo_connector->bottom_margin = temp_value;
1791 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1792 intel_sdvo_connector->top_margin;
b9219c5e 1793 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1794 goto set_value;
1795 }
1796 CHECK_PROPERTY(hpos, HPOS)
1797 CHECK_PROPERTY(vpos, VPOS)
1798 CHECK_PROPERTY(saturation, SATURATION)
1799 CHECK_PROPERTY(contrast, CONTRAST)
1800 CHECK_PROPERTY(hue, HUE)
1801 CHECK_PROPERTY(brightness, BRIGHTNESS)
1802 CHECK_PROPERTY(sharpness, SHARPNESS)
1803 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1804 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1805 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1806 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1807 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1808 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1809 }
b9219c5e 1810
c5521706 1811 return -EINVAL; /* unknown property */
b9219c5e 1812
c5521706
CW		 1813set_value:
1814 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1815 return -EIO;
b9219c5e 1816
b9219c5e 1817
c5521706 1818done:
df0e9248
CW		 1819 if (intel_sdvo->base.base.crtc) {
1820 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1821 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1822 crtc->y, crtc->fb);
1823 }
1824
32aad86f 1825 return 0;
c5521706 1826#undef CHECK_PROPERTY
ce6feabd
ZY		 1827}
1828
79e53945
JB		 1829static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1830 .dpms = intel_sdvo_dpms,
1831 .mode_fixup = intel_sdvo_mode_fixup,
1832 .prepare = intel_encoder_prepare,
1833 .mode_set = intel_sdvo_mode_set,
1834 .commit = intel_encoder_commit,
1835};
1836
1837static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1838 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1839 .detect = intel_sdvo_detect,
1840 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1841 .set_property = intel_sdvo_set_property,
79e53945
JB		 1842 .destroy = intel_sdvo_destroy,
1843};
1844
1845static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1846 .get_modes = intel_sdvo_get_modes,
1847 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1848 .best_encoder = intel_best_encoder,
79e53945
JB		 1849};
1850
b358d0a6 1851static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1852{
890f3359 1853 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1854
ea5b213a 1855 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1856 drm_mode_destroy(encoder->dev,
ea5b213a 1857 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1858
e957d772 1859 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1860 intel_encoder_destroy(encoder);
79e53945
JB		 1861}
1862
1863static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1864 .destroy = intel_sdvo_enc_destroy,
1865};
1866
b66d8424
CW		 1867static void
1868intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1869{
1870 uint16_t mask = 0;
1871 unsigned int num_bits;
1872
1873 /* Make a mask of outputs less than or equal to our own priority in the
1874 * list.
1875 */
1876 switch (sdvo->controlled_output) {
1877 case SDVO_OUTPUT_LVDS1:
1878 mask |= SDVO_OUTPUT_LVDS1;
1879 case SDVO_OUTPUT_LVDS0:
1880 mask |= SDVO_OUTPUT_LVDS0;
1881 case SDVO_OUTPUT_TMDS1:
1882 mask |= SDVO_OUTPUT_TMDS1;
1883 case SDVO_OUTPUT_TMDS0:
1884 mask |= SDVO_OUTPUT_TMDS0;
1885 case SDVO_OUTPUT_RGB1:
1886 mask |= SDVO_OUTPUT_RGB1;
1887 case SDVO_OUTPUT_RGB0:
1888 mask |= SDVO_OUTPUT_RGB0;
1889 break;
1890 }
1891
1892 /* Count bits to find what number we are in the priority list. */
1893 mask &= sdvo->caps.output_flags;
1894 num_bits = hweight16(mask);
1895 /* If more than 3 outputs, default to DDC bus 3 for now. */
1896 if (num_bits > 3)
1897 num_bits = 3;
1898
1899 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1900 sdvo->ddc_bus = 1 << num_bits;
1901}
79e53945 1902
e2f0ba97
JB		 1903/**
1904 * Choose the appropriate DDC bus for control bus switch command for this
1905 * SDVO output based on the controlled output.
1906 *
1907 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1908 * outputs, then LVDS outputs.
1909 */
1910static void
b1083333 1911intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1912 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1913{
b1083333 1914 struct sdvo_device_mapping *mapping;
e2f0ba97 1915
eef4eacb 1916 if (sdvo->is_sdvob)
b1083333
AJ		 1917 mapping = &(dev_priv->sdvo_mappings[0]);
1918 else
1919 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1920
b66d8424
CW		 1921 if (mapping->initialized)
1922 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1923 else
1924 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1925}
1926
e957d772
CW		 1927static void
1928intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1929 struct intel_sdvo *sdvo, u32 reg)
1930{
1931 struct sdvo_device_mapping *mapping;
46eb3036 1932 u8 pin;
e957d772 1933
eef4eacb 1934 if (sdvo->is_sdvob)
e957d772
CW		 1935 mapping = &dev_priv->sdvo_mappings[0];
1936 else
1937 mapping = &dev_priv->sdvo_mappings[1];
1938
1939 pin = GMBUS_PORT_DPB;
46eb3036 1940 if (mapping->initialized)
e957d772 1941 pin = mapping->i2c_pin;
e957d772 1942
3bd7d909
DK		 1943 if (intel_gmbus_is_port_valid(pin)) {
1944 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
d5090b96 1945 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1946 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1947 } else {
3bd7d909 1948 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
46eb3036 1949 }
e957d772
CW		 1950}
1951
e2f0ba97 1952static bool
e27d8538 1953intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1954{
97aaf910 1955 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1956}
1957
714605e4 1958static u8
eef4eacb 1959intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 1960{
1961 struct drm_i915_private *dev_priv = dev->dev_private;
1962 struct sdvo_device_mapping *my_mapping, *other_mapping;
1963
eef4eacb 1964 if (sdvo->is_sdvob) {
714605e4 1965 my_mapping = &dev_priv->sdvo_mappings[0];
1966 other_mapping = &dev_priv->sdvo_mappings[1];
1967 } else {
1968 my_mapping = &dev_priv->sdvo_mappings[1];
1969 other_mapping = &dev_priv->sdvo_mappings[0];
1970 }
1971
1972 /* If the BIOS described our SDVO device, take advantage of it. */
1973 if (my_mapping->slave_addr)
1974 return my_mapping->slave_addr;
1975
1976 /* If the BIOS only described a different SDVO device, use the
1977 * address that it isn't using.
1978 */
1979 if (other_mapping->slave_addr) {
1980 if (other_mapping->slave_addr == 0x70)
1981 return 0x72;
1982 else
1983 return 0x70;
1984 }
1985
1986 /* No SDVO device info is found for another DVO port,
1987 * so use mapping assumption we had before BIOS parsing.
1988 */
eef4eacb 1989 if (sdvo->is_sdvob)
714605e4 1990 return 0x70;
1991 else
1992 return 0x72;
1993}
1994
14571b4c 1995static void
df0e9248
CW		 1996intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
1997 struct intel_sdvo *encoder)
14571b4c 1998{
df0e9248
CW		 1999 drm_connector_init(encoder->base.base.dev,
2000 &connector->base.base,
2001 &intel_sdvo_connector_funcs,
2002 connector->base.base.connector_type);
6070a4a9 2003
df0e9248
CW		 2004 drm_connector_helper_add(&connector->base.base,
2005 &intel_sdvo_connector_helper_funcs);
14571b4c 2006
8f4839e2 2007 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2008 connector->base.base.doublescan_allowed = 0;
2009 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2010
df0e9248
CW		 2011 intel_connector_attach_encoder(&connector->base, &encoder->base);
2012 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2013}
6070a4a9 2014
7f36e7ed
CW		 2015static void
2016intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2017{
2018 struct drm_device *dev = connector->base.base.dev;
2019
3f43c48d 2020 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2021 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2022 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2023}
2024
fb7a46f3 2025static bool
ea5b213a 2026intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2027{
4ef69c7a 2028 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2029 struct drm_connector *connector;
cc68c81a 2030 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2031 struct intel_connector *intel_connector;
615fb93f 2032 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2033
615fb93f
CW		 2034 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2035 if (!intel_sdvo_connector)
14571b4c
ZW		 2036 return false;
2037
14571b4c 2038 if (device == 0) {
ea5b213a 2039 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2040 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2041 } else if (device == 1) {
ea5b213a 2042 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2043 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2044 }
2045
615fb93f 2046 intel_connector = &intel_sdvo_connector->base;
14571b4c 2047 connector = &intel_connector->base;
cc68c81a
SF		 2048 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2049 connector->polled = DRM_CONNECTOR_POLL_HPD;
2050 intel_sdvo->hotplug_active[0] |= 1 << device;
2051 /* Some SDVO devices have one-shot hotplug interrupts.
2052 * Ensure that they get re-enabled when an interrupt happens.
2053 */
2054 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2055 intel_sdvo_enable_hotplug(intel_encoder);
2056 }
2057 else
2058 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2059 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2060 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2061
e27d8538 2062 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2063 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2064 intel_sdvo->is_hdmi = true;
14571b4c 2065 }
ea5b213a
CW		 2066 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2067 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2068
df0e9248 2069 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2070 if (intel_sdvo->is_hdmi)
2071 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2072
2073 return true;
2074}
2075
2076static bool
ea5b213a 2077intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2078{
4ef69c7a
CW		 2079 struct drm_encoder *encoder = &intel_sdvo->base.base;
2080 struct drm_connector *connector;
2081 struct intel_connector *intel_connector;
2082 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2083
615fb93f
CW		 2084 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2085 if (!intel_sdvo_connector)
2086 return false;
14571b4c 2087
615fb93f 2088 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2089 connector = &intel_connector->base;
2090 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2091 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2092
4ef69c7a
CW		 2093 intel_sdvo->controlled_output |= type;
2094 intel_sdvo_connector->output_flag = type;
14571b4c 2095
4ef69c7a
CW		 2096 intel_sdvo->is_tv = true;
2097 intel_sdvo->base.needs_tv_clock = true;
2098 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2099
df0e9248 2100 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2101
4ef69c7a 2102 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2103 goto err;
14571b4c 2104
4ef69c7a 2105 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2106 goto err;
14571b4c 2107
4ef69c7a 2108 return true;
32aad86f
CW		 2109
2110err:
123d5c01 2111 intel_sdvo_destroy(connector);
32aad86f 2112 return false;
14571b4c
ZW		 2113}
2114
2115static bool
ea5b213a 2116intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2117{
4ef69c7a
CW		 2118 struct drm_encoder *encoder = &intel_sdvo->base.base;
2119 struct drm_connector *connector;
2120 struct intel_connector *intel_connector;
2121 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2122
615fb93f
CW		 2123 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2124 if (!intel_sdvo_connector)
2125 return false;
14571b4c 2126
615fb93f 2127 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2128 connector = &intel_connector->base;
eb1f8e4f 2129 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2130 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2131 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2132
2133 if (device == 0) {
2134 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2135 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2136 } else if (device == 1) {
2137 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2138 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2139 }
2140
2141 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2142 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2143
df0e9248
CW		 2144 intel_sdvo_connector_init(intel_sdvo_connector,
2145 intel_sdvo);
4ef69c7a 2146 return true;
14571b4c
ZW		 2147}
2148
2149static bool
ea5b213a 2150intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2151{
4ef69c7a
CW		 2152 struct drm_encoder *encoder = &intel_sdvo->base.base;
2153 struct drm_connector *connector;
2154 struct intel_connector *intel_connector;
2155 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2156
615fb93f
CW		 2157 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2158 if (!intel_sdvo_connector)
2159 return false;
14571b4c 2160
615fb93f
CW		 2161 intel_connector = &intel_sdvo_connector->base;
2162 connector = &intel_connector->base;
4ef69c7a
CW		 2163 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2164 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2165
2166 if (device == 0) {
2167 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2168 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2169 } else if (device == 1) {
2170 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2171 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2172 }
2173
2174 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2175 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2176
df0e9248 2177 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2178 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2179 goto err;
2180
2181 return true;
2182
2183err:
123d5c01 2184 intel_sdvo_destroy(connector);
32aad86f 2185 return false;
14571b4c
ZW		 2186}
2187
2188static bool
ea5b213a 2189intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2190{
ea5b213a
CW		 2191 intel_sdvo->is_tv = false;
2192 intel_sdvo->base.needs_tv_clock = false;
2193 intel_sdvo->is_lvds = false;
fb7a46f3 2194
14571b4c 2195 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2196
14571b4c 2197 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2198 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2199 return false;
2200
2201 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2202 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2203 return false;
2204
2205 /* TV has no XXX1 function block */
a1f4b7ff 2206 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2207 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2208 return false;
2209
2210 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2211 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2212 return false;
fb7a46f3 2213
a0b1c7a5
CW		 2214 if (flags & SDVO_OUTPUT_YPRPB0)
2215 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2216 return false;
2217
14571b4c 2218 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2219 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2220 return false;
2221
2222 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2223 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2224 return false;
2225
2226 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2227 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2228 return false;
2229
2230 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2231 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2232 return false;
fb7a46f3 2233
14571b4c 2234 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2235 unsigned char bytes[2];
2236
ea5b213a
CW		 2237 intel_sdvo->controlled_output = 0;
2238 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2239 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2240 SDVO_NAME(intel_sdvo),
51c8b407 2241 bytes[0], bytes[1]);
14571b4c 2242 return false;
fb7a46f3 2243 }
27f8227b 2244 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2245
14571b4c 2246 return true;
fb7a46f3 2247}
2248
32aad86f
CW		 2249static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2250 struct intel_sdvo_connector *intel_sdvo_connector,
2251 int type)
ce6feabd 2252{
4ef69c7a 2253 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2254 struct intel_sdvo_tv_format format;
2255 uint32_t format_map, i;
ce6feabd 2256
32aad86f
CW		 2257 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2258 return false;
ce6feabd 2259
1a3665c8 2260 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2261 if (!intel_sdvo_get_value(intel_sdvo,
2262 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2263 &format, sizeof(format)))
2264 return false;
ce6feabd 2265
32aad86f 2266 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2267
2268 if (format_map == 0)
32aad86f 2269 return false;
ce6feabd 2270
615fb93f 2271 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2272 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2273 if (format_map & (1 << i))
2274 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2275
2276
c5521706 2277 intel_sdvo_connector->tv_format =
32aad86f
CW		 2278 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2279 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2280 if (!intel_sdvo_connector->tv_format)
fcc8d672 2281 return false;
ce6feabd 2282
615fb93f 2283 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2284 drm_property_add_enum(
c5521706 2285 intel_sdvo_connector->tv_format, i,
40039750 2286 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2287
40039750 2288 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2289 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2290 intel_sdvo_connector->tv_format, 0);
32aad86f 2291 return true;
ce6feabd
ZY		 2292
2293}
2294
c5521706
CW		 2295#define ENHANCEMENT(name, NAME) do { \
2296 if (enhancements.name) { \
2297 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2298 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2299 return false; \
2300 intel_sdvo_connector->max_##name = data_value[0]; \
2301 intel_sdvo_connector->cur_##name = response; \
2302 intel_sdvo_connector->name = \
d9bc3c02 2303 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2304 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2305 drm_connector_attach_property(connector, \
2306 intel_sdvo_connector->name, \
2307 intel_sdvo_connector->cur_##name); \
2308 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2309 data_value[0], data_value[1], response); \
2310 } \
0206e353 2311} while (0)
c5521706
CW		 2312
2313static bool
2314intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2315 struct intel_sdvo_connector *intel_sdvo_connector,
2316 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2317{
4ef69c7a 2318 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2319 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2320 uint16_t response, data_value[2];
2321
c5521706
CW		 2322 /* when horizontal overscan is supported, Add the left/right property */
2323 if (enhancements.overscan_h) {
2324 if (!intel_sdvo_get_value(intel_sdvo,
2325 SDVO_CMD_GET_MAX_OVERSCAN_H,
2326 &data_value, 4))
2327 return false;
32aad86f 2328
c5521706
CW		 2329 if (!intel_sdvo_get_value(intel_sdvo,
2330 SDVO_CMD_GET_OVERSCAN_H,
2331 &response, 2))
2332 return false;
fcc8d672 2333
c5521706
CW		 2334 intel_sdvo_connector->max_hscan = data_value[0];
2335 intel_sdvo_connector->left_margin = data_value[0] - response;
2336 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2337 intel_sdvo_connector->left =
d9bc3c02 2338 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2339 if (!intel_sdvo_connector->left)
2340 return false;
fcc8d672 2341
c5521706
CW		 2342 drm_connector_attach_property(connector,
2343 intel_sdvo_connector->left,
2344 intel_sdvo_connector->left_margin);
fcc8d672 2345
c5521706 2346 intel_sdvo_connector->right =
d9bc3c02 2347 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2348 if (!intel_sdvo_connector->right)
2349 return false;
32aad86f 2350
c5521706
CW		 2351 drm_connector_attach_property(connector,
2352 intel_sdvo_connector->right,
2353 intel_sdvo_connector->right_margin);
2354 DRM_DEBUG_KMS("h_overscan: max %d, "
2355 "default %d, current %d\n",
2356 data_value[0], data_value[1], response);
2357 }
32aad86f 2358
c5521706
CW		 2359 if (enhancements.overscan_v) {
2360 if (!intel_sdvo_get_value(intel_sdvo,
2361 SDVO_CMD_GET_MAX_OVERSCAN_V,
2362 &data_value, 4))
2363 return false;
fcc8d672 2364
c5521706
CW		 2365 if (!intel_sdvo_get_value(intel_sdvo,
2366 SDVO_CMD_GET_OVERSCAN_V,
2367 &response, 2))
2368 return false;
32aad86f 2369
c5521706
CW		 2370 intel_sdvo_connector->max_vscan = data_value[0];
2371 intel_sdvo_connector->top_margin = data_value[0] - response;
2372 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2373 intel_sdvo_connector->top =
d9bc3c02
SH		 2374 drm_property_create_range(dev, 0,
2375 "top_margin", 0, data_value[0]);
c5521706
CW		 2376 if (!intel_sdvo_connector->top)
2377 return false;
32aad86f 2378
c5521706
CW		 2379 drm_connector_attach_property(connector,
2380 intel_sdvo_connector->top,
2381 intel_sdvo_connector->top_margin);
fcc8d672 2382
c5521706 2383 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2384 drm_property_create_range(dev, 0,
2385 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2386 if (!intel_sdvo_connector->bottom)
2387 return false;
32aad86f 2388
c5521706
CW		 2389 drm_connector_attach_property(connector,
2390 intel_sdvo_connector->bottom,
2391 intel_sdvo_connector->bottom_margin);
2392 DRM_DEBUG_KMS("v_overscan: max %d, "
2393 "default %d, current %d\n",
2394 data_value[0], data_value[1], response);
2395 }
32aad86f 2396
c5521706
CW		 2397 ENHANCEMENT(hpos, HPOS);
2398 ENHANCEMENT(vpos, VPOS);
2399 ENHANCEMENT(saturation, SATURATION);
2400 ENHANCEMENT(contrast, CONTRAST);
2401 ENHANCEMENT(hue, HUE);
2402 ENHANCEMENT(sharpness, SHARPNESS);
2403 ENHANCEMENT(brightness, BRIGHTNESS);
2404 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2405 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2406 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2407 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2408 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2409
e044218a
CW		 2410 if (enhancements.dot_crawl) {
2411 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2412 return false;
2413
2414 intel_sdvo_connector->max_dot_crawl = 1;
2415 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2416 intel_sdvo_connector->dot_crawl =
d9bc3c02 2417 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2418 if (!intel_sdvo_connector->dot_crawl)
2419 return false;
2420
e044218a
CW		 2421 drm_connector_attach_property(connector,
2422 intel_sdvo_connector->dot_crawl,
2423 intel_sdvo_connector->cur_dot_crawl);
2424 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2425 }
2426
c5521706
CW		 2427 return true;
2428}
32aad86f 2429
c5521706
CW		 2430static bool
2431intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2432 struct intel_sdvo_connector *intel_sdvo_connector,
2433 struct intel_sdvo_enhancements_reply enhancements)
2434{
4ef69c7a 2435 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2436 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2437 uint16_t response, data_value[2];
32aad86f 2438
c5521706 2439 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2440
c5521706
CW		 2441 return true;
2442}
2443#undef ENHANCEMENT
32aad86f 2444
c5521706
CW		 2445static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2446 struct intel_sdvo_connector *intel_sdvo_connector)
2447{
2448 union {
2449 struct intel_sdvo_enhancements_reply reply;
2450 uint16_t response;
2451 } enhancements;
32aad86f 2452
1a3665c8
CW		 2453 BUILD_BUG_ON(sizeof(enhancements) != 2);
2454
cf9a2f3a
CW		 2455 enhancements.response = 0;
2456 intel_sdvo_get_value(intel_sdvo,
2457 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2458 &enhancements, sizeof(enhancements));
c5521706
CW		 2459 if (enhancements.response == 0) {
2460 DRM_DEBUG_KMS("No enhancement is supported\n");
2461 return true;
b9219c5e 2462 }
32aad86f 2463
c5521706
CW		 2464 if (IS_TV(intel_sdvo_connector))
2465 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2466 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2467 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2468 else
2469 return true;
e957d772
CW		 2470}
2471
2472static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2473 struct i2c_msg *msgs,
2474 int num)
2475{
2476 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2477
e957d772
CW		 2478 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2479 return -EIO;
2480
2481 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2482}
2483
2484static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2485{
2486 struct intel_sdvo *sdvo = adapter->algo_data;
2487 return sdvo->i2c->algo->functionality(sdvo->i2c);
2488}
2489
2490static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2491 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2492 .functionality = intel_sdvo_ddc_proxy_func
2493};
2494
2495static bool
2496intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2497 struct drm_device *dev)
2498{
2499 sdvo->ddc.owner = THIS_MODULE;
2500 sdvo->ddc.class = I2C_CLASS_DDC;
2501 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2502 sdvo->ddc.dev.parent = &dev->pdev->dev;
2503 sdvo->ddc.algo_data = sdvo;
2504 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2505
2506 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2507}
2508
eef4eacb 2509bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2510{
b01f2c3a 2511 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2512 struct intel_encoder *intel_encoder;
ea5b213a 2513 struct intel_sdvo *intel_sdvo;
79e53945 2514 int i;
79e53945 2515
ea5b213a
CW		 2516 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2517 if (!intel_sdvo)
7d57382e 2518 return false;
79e53945 2519
56184e3d 2520 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2521 intel_sdvo->is_sdvob = is_sdvob;
2522 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2523 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2524 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2525 kfree(intel_sdvo);
2526 return false;
2527 }
2528
56184e3d 2529 /* encoder type will be decided later */
ea5b213a 2530 intel_encoder = &intel_sdvo->base;
21d40d37 2531 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2532 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2533
79e53945
JB		 2534 /* Read the regs to test if we can talk to the device */
2535 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2536 u8 byte;
2537
2538 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2539 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2540 SDVO_NAME(intel_sdvo));
f899fc64 2541 goto err;
79e53945
JB		 2542 }
2543 }
2544
eef4eacb 2545 if (intel_sdvo->is_sdvob)
b01f2c3a 2546 dev_priv->hotplug_supported_mask |= SDVOB_HOTPLUG_INT_STATUS;
f899fc64 2547 else
b01f2c3a 2548 dev_priv->hotplug_supported_mask |= SDVOC_HOTPLUG_INT_STATUS;
619ac3b7 2549
4ef69c7a 2550 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2551
af901ca1 2552 /* In default case sdvo lvds is false */
32aad86f 2553 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2554 goto err;
79e53945 2555
cc68c81a
SF		 2556 /* Set up hotplug command - note paranoia about contents of reply.
2557 * We assume that the hardware is in a sane state, and only touch
2558 * the bits we think we understand.
2559 */
2560 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_ACTIVE_HOT_PLUG,
2561 &intel_sdvo->hotplug_active, 2);
2562 intel_sdvo->hotplug_active[0] &= ~0x3;
2563
ea5b213a
CW		 2564 if (intel_sdvo_output_setup(intel_sdvo,
2565 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2566 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2567 SDVO_NAME(intel_sdvo));
f899fc64 2568 goto err;
79e53945
JB		 2569 }
2570
ea5b213a 2571 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2572
79e53945 2573 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2574 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2575 goto err;
79e53945 2576
32aad86f
CW		 2577 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2578 &intel_sdvo->pixel_clock_min,
2579 &intel_sdvo->pixel_clock_max))
f899fc64 2580 goto err;
79e53945 2581
8a4c47f3 2582 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2583 "clock range %dMHz - %dMHz, "
2584 "input 1: %c, input 2: %c, "
2585 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2586 SDVO_NAME(intel_sdvo),
2587 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2588 intel_sdvo->caps.device_rev_id,
2589 intel_sdvo->pixel_clock_min / 1000,
2590 intel_sdvo->pixel_clock_max / 1000,
2591 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2592 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2593 /* check currently supported outputs */
ea5b213a 2594 intel_sdvo->caps.output_flags &
79e53945 2595 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2596 intel_sdvo->caps.output_flags &
79e53945 2597 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2598 return true;
79e53945 2599
f899fc64 2600err:
373a3cf7 2601 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2602 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2603 kfree(intel_sdvo);
79e53945 2604
7d57382e 2605 return false;
79e53945 2606}
kernel source for telekom puls (alcatel/mediatek)