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UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_sdvo.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2007 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
24 *
25 * Authors:
26 * Eric Anholt <eric@anholt.net>
27 */
28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
79e53945 30#include <linux/delay.h>
2d1a8a48 31#include <linux/export.h>
760285e7
DH		 32#include <drm/drmP.h>
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
ea5b213a 35#include "intel_drv.h"
760285e7 36#include <drm/i915_drm.h>
79e53945
JB		 37#include "i915_drv.h"
38#include "intel_sdvo_regs.h"
39
14571b4c
ZW		 40#define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
41#define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
42#define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
a0b1c7a5 43#define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
14571b4c
ZW		 44
45#define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
0206e353 46 SDVO_TV_MASK)
14571b4c
ZW		 47
48#define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
13946743 49#define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
14571b4c 50#define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
32aad86f 51#define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
52220085 52#define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
14571b4c 53
79e53945 54
2e88e40b 55static const char *tv_format_names[] = {
ce6feabd
ZY		 56 "NTSC_M" , "NTSC_J" , "NTSC_443",
57 "PAL_B" , "PAL_D" , "PAL_G" ,
58 "PAL_H" , "PAL_I" , "PAL_M" ,
59 "PAL_N" , "PAL_NC" , "PAL_60" ,
60 "SECAM_B" , "SECAM_D" , "SECAM_G" ,
61 "SECAM_K" , "SECAM_K1", "SECAM_L" ,
62 "SECAM_60"
63};
64
65#define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
66
ea5b213a
CW		 67struct intel_sdvo {
68 struct intel_encoder base;
69
f899fc64 70 struct i2c_adapter *i2c;
f9c10a9b 71 u8 slave_addr;
e2f0ba97 72
e957d772
CW		 73 struct i2c_adapter ddc;
74
e2f0ba97 75 /* Register for the SDVO device: SDVOB or SDVOC */
eef4eacb 76 uint32_t sdvo_reg;
79e53945 77
e2f0ba97
JB		 78 /* Active outputs controlled by this SDVO output */
79 uint16_t controlled_output;
79e53945 80
e2f0ba97
JB		 81 /*
82 * Capabilities of the SDVO device returned by
83 * i830_sdvo_get_capabilities()
84 */
79e53945 85 struct intel_sdvo_caps caps;
e2f0ba97
JB		 86
87 /* Pixel clock limitations reported by the SDVO device, in kHz */
79e53945
JB		 88 int pixel_clock_min, pixel_clock_max;
89
fb7a46f3 90 /*
91 * For multiple function SDVO device,
92 * this is for current attached outputs.
93 */
94 uint16_t attached_output;
95
cc68c81a
SF		 96 /*
97 * Hotplug activation bits for this device
98 */
99 uint8_t hotplug_active[2];
100
e953fd7b
CW		 101 /**
102 * This is used to select the color range of RBG outputs in HDMI mode.
103 * It is only valid when using TMDS encoding and 8 bit per color mode.
104 */
105 uint32_t color_range;
106
e2f0ba97
JB		 107 /**
108 * This is set if we're going to treat the device as TV-out.
109 *
110 * While we have these nice friendly flags for output types that ought
111 * to decide this for us, the S-Video output on our HDMI+S-Video card
112 * shows up as RGB1 (VGA).
113 */
114 bool is_tv;
115
eef4eacb
DV		 116 /* On different gens SDVOB is at different places. */
117 bool is_sdvob;
118
ce6feabd 119 /* This is for current tv format name */
40039750 120 int tv_format_index;
ce6feabd 121
e2f0ba97
JB		 122 /**
123 * This is set if we treat the device as HDMI, instead of DVI.
124 */
125 bool is_hdmi;
da79de97
CW		 126 bool has_hdmi_monitor;
127 bool has_hdmi_audio;
12682a97 128
7086c87f 129 /**
6c9547ff
CW		 130 * This is set if we detect output of sdvo device as LVDS and
131 * have a valid fixed mode to use with the panel.
7086c87f
ML		 132 */
133 bool is_lvds;
e2f0ba97 134
12682a97 135 /**
136 * This is sdvo fixed pannel mode pointer
137 */
138 struct drm_display_mode *sdvo_lvds_fixed_mode;
139
c751ce4f 140 /* DDC bus used by this SDVO encoder */
e2f0ba97 141 uint8_t ddc_bus;
14571b4c
ZW		 142};
143
144struct intel_sdvo_connector {
615fb93f
CW		 145 struct intel_connector base;
146
14571b4c
ZW		 147 /* Mark the type of connector */
148 uint16_t output_flag;
149
c3e5f67b 150 enum hdmi_force_audio force_audio;
7f36e7ed 151
14571b4c 152 /* This contains all current supported TV format */
40039750 153 u8 tv_format_supported[TV_FORMAT_NUM];
14571b4c 154 int format_supported_num;
c5521706 155 struct drm_property *tv_format;
14571b4c 156
b9219c5e 157 /* add the property for the SDVO-TV */
c5521706
CW		 158 struct drm_property *left;
159 struct drm_property *right;
160 struct drm_property *top;
161 struct drm_property *bottom;
162 struct drm_property *hpos;
163 struct drm_property *vpos;
164 struct drm_property *contrast;
165 struct drm_property *saturation;
166 struct drm_property *hue;
167 struct drm_property *sharpness;
168 struct drm_property *flicker_filter;
169 struct drm_property *flicker_filter_adaptive;
170 struct drm_property *flicker_filter_2d;
171 struct drm_property *tv_chroma_filter;
172 struct drm_property *tv_luma_filter;
e044218a 173 struct drm_property *dot_crawl;
b9219c5e
ZY		 174
175 /* add the property for the SDVO-TV/LVDS */
c5521706 176 struct drm_property *brightness;
b9219c5e
ZY		 177
178 /* Add variable to record current setting for the above property */
179 u32 left_margin, right_margin, top_margin, bottom_margin;
c5521706 180
b9219c5e
ZY		 181 /* this is to get the range of margin.*/
182 u32 max_hscan, max_vscan;
183 u32 max_hpos, cur_hpos;
184 u32 max_vpos, cur_vpos;
185 u32 cur_brightness, max_brightness;
186 u32 cur_contrast, max_contrast;
187 u32 cur_saturation, max_saturation;
188 u32 cur_hue, max_hue;
c5521706
CW		 189 u32 cur_sharpness, max_sharpness;
190 u32 cur_flicker_filter, max_flicker_filter;
191 u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
192 u32 cur_flicker_filter_2d, max_flicker_filter_2d;
193 u32 cur_tv_chroma_filter, max_tv_chroma_filter;
194 u32 cur_tv_luma_filter, max_tv_luma_filter;
e044218a 195 u32 cur_dot_crawl, max_dot_crawl;
79e53945
JB		 196};
197
890f3359 198static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
ea5b213a 199{
4ef69c7a 200 return container_of(encoder, struct intel_sdvo, base.base);
ea5b213a
CW		 201}
202
df0e9248
CW		 203static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
204{
205 return container_of(intel_attached_encoder(connector),
206 struct intel_sdvo, base);
207}
208
615fb93f
CW		 209static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
210{
211 return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
212}
213
fb7a46f3 214static bool
ea5b213a 215intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
32aad86f
CW		 216static bool
217intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
218 struct intel_sdvo_connector *intel_sdvo_connector,
219 int type);
220static bool
221intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
222 struct intel_sdvo_connector *intel_sdvo_connector);
fb7a46f3 223
79e53945
JB		 224/**
225 * Writes the SDVOB or SDVOC with the given value, but always writes both
226 * SDVOB and SDVOC to work around apparent hardware issues (according to
227 * comments in the BIOS).
228 */
ea5b213a 229static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
79e53945 230{
4ef69c7a 231 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 232 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 233 u32 bval = val, cval = val;
234 int i;
235
ea5b213a
CW		 236 if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
237 I915_WRITE(intel_sdvo->sdvo_reg, val);
238 I915_READ(intel_sdvo->sdvo_reg);
461ed3ca
ZY		 239 return;
240 }
241
ea5b213a 242 if (intel_sdvo->sdvo_reg == SDVOB) {
79e53945
JB		 243 cval = I915_READ(SDVOC);
244 } else {
245 bval = I915_READ(SDVOB);
246 }
247 /*
248 * Write the registers twice for luck. Sometimes,
249 * writing them only once doesn't appear to 'stick'.
250 * The BIOS does this too. Yay, magic
251 */
252 for (i = 0; i < 2; i++)
253 {
254 I915_WRITE(SDVOB, bval);
255 I915_READ(SDVOB);
256 I915_WRITE(SDVOC, cval);
257 I915_READ(SDVOC);
258 }
259}
260
32aad86f 261static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
79e53945 262{
79e53945
JB		 263 struct i2c_msg msgs[] = {
264 {
e957d772 265 .addr = intel_sdvo->slave_addr,
79e53945
JB		 266 .flags = 0,
267 .len = 1,
e957d772 268 .buf = &addr,
79e53945
JB		 269 },
270 {
e957d772 271 .addr = intel_sdvo->slave_addr,
79e53945
JB		 272 .flags = I2C_M_RD,
273 .len = 1,
e957d772 274 .buf = ch,
79e53945
JB		 275 }
276 };
32aad86f 277 int ret;
79e53945 278
f899fc64 279 if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
79e53945 280 return true;
79e53945 281
8a4c47f3 282 DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
79e53945
JB		 283 return false;
284}
285
79e53945
JB		 286#define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
287/** Mapping of command numbers to names, for debug output */
005568be 288static const struct _sdvo_cmd_name {
e2f0ba97 289 u8 cmd;
2e88e40b 290 const char *name;
79e53945 291} sdvo_cmd_names[] = {
0206e353
AJ		 292 SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
293 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
294 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
295 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
296 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
297 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
298 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
299 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
300 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
301 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
302 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
303 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
304 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
305 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
306 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
307 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
308 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
309 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
310 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
311 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
312 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
313 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
314 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
315 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
316 SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
317 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
318 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
319 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
320 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
321 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
322 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
323 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
324 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
325 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
326 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
327 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
328 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
329 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
330 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
331 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
332 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
333 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
334 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
335
336 /* Add the op code for SDVO enhancements */
337 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
338 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
339 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
340 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
341 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
342 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
343 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
344 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
345 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
346 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
347 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
348 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
349 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
350 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
351 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
352 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
353 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
354 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
355 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
356 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
357 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
358 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
359 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
360 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
361 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
362 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
363 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
364 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
365 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
366 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
367 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
368 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
369 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
370 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
371 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
372 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
373 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
374 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
375 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
376 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
377 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
378 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
379 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
380 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
381
382 /* HDMI op code */
383 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
384 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
385 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
386 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
387 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
388 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
389 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
390 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
391 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
392 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
393 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
394 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
395 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
396 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
397 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
398 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
399 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
400 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
401 SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
402 SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
79e53945
JB		 403};
404
eef4eacb 405#define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
79e53945 406
ea5b213a 407static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
32aad86f 408 const void *args, int args_len)
79e53945 409{
79e53945
JB		 410 int i;
411
8a4c47f3 412 DRM_DEBUG_KMS("%s: W: %02X ",
ea5b213a 413 SDVO_NAME(intel_sdvo), cmd);
79e53945 414 for (i = 0; i < args_len; i++)
342dc382 415 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
79e53945 416 for (; i < 8; i++)
342dc382 417 DRM_LOG_KMS(" ");
04ad327f 418 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
79e53945 419 if (cmd == sdvo_cmd_names[i].cmd) {
342dc382 420 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
79e53945
JB		 421 break;
422 }
423 }
04ad327f 424 if (i == ARRAY_SIZE(sdvo_cmd_names))
342dc382 425 DRM_LOG_KMS("(%02X)", cmd);
426 DRM_LOG_KMS("\n");
79e53945 427}
79e53945 428
e957d772
CW		 429static const char *cmd_status_names[] = {
430 "Power on",
431 "Success",
432 "Not supported",
433 "Invalid arg",
434 "Pending",
435 "Target not specified",
436 "Scaling not supported"
437};
438
32aad86f
CW		 439static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
440 const void *args, int args_len)
79e53945 441{
3bf3f452
BW		 442 u8 *buf, status;
443 struct i2c_msg *msgs;
444 int i, ret = true;
445
0274df3e 446 /* Would be simpler to allocate both in one go ? */
3bf3f452
BW		 447 buf = (u8 *)kzalloc(args_len * 2 + 2, GFP_KERNEL);
448 if (!buf)
449 return false;
450
451 msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
0274df3e
AC		 452 if (!msgs) {
453 kfree(buf);
3bf3f452 454 return false;
0274df3e 455 }
79e53945 456
ea5b213a 457 intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
79e53945
JB		 458
459 for (i = 0; i < args_len; i++) {
e957d772
CW		 460 msgs[i].addr = intel_sdvo->slave_addr;
461 msgs[i].flags = 0;
462 msgs[i].len = 2;
463 msgs[i].buf = buf + 2 *i;
464 buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
465 buf[2*i + 1] = ((u8*)args)[i];
466 }
467 msgs[i].addr = intel_sdvo->slave_addr;
468 msgs[i].flags = 0;
469 msgs[i].len = 2;
470 msgs[i].buf = buf + 2*i;
471 buf[2*i + 0] = SDVO_I2C_OPCODE;
472 buf[2*i + 1] = cmd;
473
474 /* the following two are to read the response */
475 status = SDVO_I2C_CMD_STATUS;
476 msgs[i+1].addr = intel_sdvo->slave_addr;
477 msgs[i+1].flags = 0;
478 msgs[i+1].len = 1;
479 msgs[i+1].buf = &status;
480
481 msgs[i+2].addr = intel_sdvo->slave_addr;
482 msgs[i+2].flags = I2C_M_RD;
483 msgs[i+2].len = 1;
484 msgs[i+2].buf = &status;
485
486 ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
487 if (ret < 0) {
488 DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
3bf3f452
BW		 489 ret = false;
490 goto out;
e957d772
CW		 491 }
492 if (ret != i+3) {
493 /* failure in I2C transfer */
494 DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
3bf3f452 495 ret = false;
e957d772
CW		 496 }
497
3bf3f452
BW		 498out:
499 kfree(msgs);
500 kfree(buf);
501 return ret;
79e53945
JB		 502}
503
b5c616a7
CW		 504static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
505 void *response, int response_len)
79e53945 506{
b5c616a7
CW		 507 u8 retry = 5;
508 u8 status;
33b52961 509 int i;
79e53945 510
d121a5d2
CW		 511 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
512
b5c616a7
CW		 513 /*
514 * The documentation states that all commands will be
515 * processed within 15µs, and that we need only poll
516 * the status byte a maximum of 3 times in order for the
517 * command to be complete.
518 *
519 * Check 5 times in case the hardware failed to read the docs.
520 */
d121a5d2
CW		 521 if (!intel_sdvo_read_byte(intel_sdvo,
522 SDVO_I2C_CMD_STATUS,
523 &status))
524 goto log_fail;
525
526 while (status == SDVO_CMD_STATUS_PENDING && retry--) {
527 udelay(15);
b5c616a7
CW		 528 if (!intel_sdvo_read_byte(intel_sdvo,
529 SDVO_I2C_CMD_STATUS,
530 &status))
d121a5d2
CW		 531 goto log_fail;
532 }
b5c616a7 533
79e53945 534 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
342dc382 535 DRM_LOG_KMS("(%s)", cmd_status_names[status]);
79e53945 536 else
342dc382 537 DRM_LOG_KMS("(??? %d)", status);
79e53945 538
b5c616a7
CW		 539 if (status != SDVO_CMD_STATUS_SUCCESS)
540 goto log_fail;
79e53945 541
b5c616a7
CW		 542 /* Read the command response */
543 for (i = 0; i < response_len; i++) {
544 if (!intel_sdvo_read_byte(intel_sdvo,
545 SDVO_I2C_RETURN_0 + i,
546 &((u8 *)response)[i]))
547 goto log_fail;
e957d772 548 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
b5c616a7 549 }
b5c616a7 550 DRM_LOG_KMS("\n");
b5c616a7 551 return true;
79e53945 552
b5c616a7 553log_fail:
d121a5d2 554 DRM_LOG_KMS("... failed\n");
b5c616a7 555 return false;
79e53945
JB		 556}
557
b358d0a6 558static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
79e53945
JB		 559{
560 if (mode->clock >= 100000)
561 return 1;
562 else if (mode->clock >= 50000)
563 return 2;
564 else
565 return 4;
566}
567
e957d772
CW		 568static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
569 u8 ddc_bus)
79e53945 570{
d121a5d2 571 /* This must be the immediately preceding write before the i2c xfer */
e957d772
CW		 572 return intel_sdvo_write_cmd(intel_sdvo,
573 SDVO_CMD_SET_CONTROL_BUS_SWITCH,
574 &ddc_bus, 1);
79e53945
JB		 575}
576
32aad86f 577static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
79e53945 578{
d121a5d2
CW		 579 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
580 return false;
581
582 return intel_sdvo_read_response(intel_sdvo, NULL, 0);
32aad86f 583}
79e53945 584
32aad86f
CW		 585static bool
586intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
587{
588 if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
589 return false;
79e53945 590
32aad86f
CW		 591 return intel_sdvo_read_response(intel_sdvo, value, len);
592}
79e53945 593
32aad86f
CW		 594static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
595{
596 struct intel_sdvo_set_target_input_args targets = {0};
597 return intel_sdvo_set_value(intel_sdvo,
598 SDVO_CMD_SET_TARGET_INPUT,
599 &targets, sizeof(targets));
79e53945
JB		 600}
601
602/**
603 * Return whether each input is trained.
604 *
605 * This function is making an assumption about the layout of the response,
606 * which should be checked against the docs.
607 */
ea5b213a 608static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
79e53945
JB		 609{
610 struct intel_sdvo_get_trained_inputs_response response;
79e53945 611
1a3665c8 612 BUILD_BUG_ON(sizeof(response) != 1);
32aad86f
CW		 613 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
614 &response, sizeof(response)))
79e53945
JB		 615 return false;
616
617 *input_1 = response.input0_trained;
618 *input_2 = response.input1_trained;
619 return true;
620}
621
ea5b213a 622static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
79e53945
JB		 623 u16 outputs)
624{
32aad86f
CW		 625 return intel_sdvo_set_value(intel_sdvo,
626 SDVO_CMD_SET_ACTIVE_OUTPUTS,
627 &outputs, sizeof(outputs));
79e53945
JB		 628}
629
ea5b213a 630static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
79e53945
JB		 631 int mode)
632{
32aad86f 633 u8 state = SDVO_ENCODER_STATE_ON;
79e53945
JB		 634
635 switch (mode) {
636 case DRM_MODE_DPMS_ON:
637 state = SDVO_ENCODER_STATE_ON;
638 break;
639 case DRM_MODE_DPMS_STANDBY:
640 state = SDVO_ENCODER_STATE_STANDBY;
641 break;
642 case DRM_MODE_DPMS_SUSPEND:
643 state = SDVO_ENCODER_STATE_SUSPEND;
644 break;
645 case DRM_MODE_DPMS_OFF:
646 state = SDVO_ENCODER_STATE_OFF;
647 break;
648 }
649
32aad86f
CW		 650 return intel_sdvo_set_value(intel_sdvo,
651 SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
79e53945
JB		 652}
653
ea5b213a 654static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
79e53945
JB		 655 int *clock_min,
656 int *clock_max)
657{
658 struct intel_sdvo_pixel_clock_range clocks;
79e53945 659
1a3665c8 660 BUILD_BUG_ON(sizeof(clocks) != 4);
32aad86f
CW		 661 if (!intel_sdvo_get_value(intel_sdvo,
662 SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
663 &clocks, sizeof(clocks)))
79e53945
JB		 664 return false;
665
666 /* Convert the values from units of 10 kHz to kHz. */
667 *clock_min = clocks.min * 10;
668 *clock_max = clocks.max * 10;
79e53945
JB		 669 return true;
670}
671
ea5b213a 672static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
79e53945
JB		 673 u16 outputs)
674{
32aad86f
CW		 675 return intel_sdvo_set_value(intel_sdvo,
676 SDVO_CMD_SET_TARGET_OUTPUT,
677 &outputs, sizeof(outputs));
79e53945
JB		 678}
679
ea5b213a 680static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
79e53945
JB		 681 struct intel_sdvo_dtd *dtd)
682{
32aad86f
CW		 683 return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
684 intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
79e53945
JB		 685}
686
ea5b213a 687static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 688 struct intel_sdvo_dtd *dtd)
689{
ea5b213a 690 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 691 SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
692}
693
ea5b213a 694static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
79e53945
JB		 695 struct intel_sdvo_dtd *dtd)
696{
ea5b213a 697 return intel_sdvo_set_timing(intel_sdvo,
79e53945
JB		 698 SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
699}
700
e2f0ba97 701static bool
ea5b213a 702intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 703 uint16_t clock,
704 uint16_t width,
705 uint16_t height)
706{
707 struct intel_sdvo_preferred_input_timing_args args;
e2f0ba97 708
e642c6f1 709 memset(&args, 0, sizeof(args));
e2f0ba97
JB		 710 args.clock = clock;
711 args.width = width;
712 args.height = height;
e642c6f1 713 args.interlace = 0;
12682a97 714
ea5b213a
CW		 715 if (intel_sdvo->is_lvds &&
716 (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
717 intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
12682a97 718 args.scaled = 1;
719
32aad86f
CW		 720 return intel_sdvo_set_value(intel_sdvo,
721 SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
722 &args, sizeof(args));
e2f0ba97
JB		 723}
724
ea5b213a 725static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 726 struct intel_sdvo_dtd *dtd)
727{
1a3665c8
CW		 728 BUILD_BUG_ON(sizeof(dtd->part1) != 8);
729 BUILD_BUG_ON(sizeof(dtd->part2) != 8);
32aad86f
CW		 730 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
731 &dtd->part1, sizeof(dtd->part1)) &&
732 intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
733 &dtd->part2, sizeof(dtd->part2));
e2f0ba97 734}
79e53945 735
ea5b213a 736static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
79e53945 737{
32aad86f 738 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
79e53945
JB		 739}
740
e2f0ba97 741static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
32aad86f 742 const struct drm_display_mode *mode)
79e53945 743{
e2f0ba97
JB		 744 uint16_t width, height;
745 uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
746 uint16_t h_sync_offset, v_sync_offset;
6651819b 747 int mode_clock;
79e53945 748
c6ebd4c0
DV		 749 width = mode->hdisplay;
750 height = mode->vdisplay;
79e53945
JB		 751
752 /* do some mode translations */
c6ebd4c0
DV		 753 h_blank_len = mode->htotal - mode->hdisplay;
754 h_sync_len = mode->hsync_end - mode->hsync_start;
79e53945 755
c6ebd4c0
DV		 756 v_blank_len = mode->vtotal - mode->vdisplay;
757 v_sync_len = mode->vsync_end - mode->vsync_start;
79e53945 758
c6ebd4c0
DV		 759 h_sync_offset = mode->hsync_start - mode->hdisplay;
760 v_sync_offset = mode->vsync_start - mode->vdisplay;
79e53945 761
6651819b
DV		 762 mode_clock = mode->clock;
763 mode_clock /= intel_mode_get_pixel_multiplier(mode) ?: 1;
764 mode_clock /= 10;
765 dtd->part1.clock = mode_clock;
766
e2f0ba97
JB		 767 dtd->part1.h_active = width & 0xff;
768 dtd->part1.h_blank = h_blank_len & 0xff;
769 dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
79e53945 770 ((h_blank_len >> 8) & 0xf);
e2f0ba97
JB		 771 dtd->part1.v_active = height & 0xff;
772 dtd->part1.v_blank = v_blank_len & 0xff;
773 dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
79e53945
JB		 774 ((v_blank_len >> 8) & 0xf);
775
171a9e96 776 dtd->part2.h_sync_off = h_sync_offset & 0xff;
e2f0ba97
JB		 777 dtd->part2.h_sync_width = h_sync_len & 0xff;
778 dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
79e53945 779 (v_sync_len & 0xf);
e2f0ba97 780 dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
79e53945
JB		 781 ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
782 ((v_sync_len & 0x30) >> 4);
783
e2f0ba97 784 dtd->part2.dtd_flags = 0x18;
59d92bfa
DV		 785 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
786 dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
79e53945 787 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
59d92bfa 788 dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
79e53945 789 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
59d92bfa 790 dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
e2f0ba97
JB		 791
792 dtd->part2.sdvo_flags = 0;
793 dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
794 dtd->part2.reserved = 0;
795}
796
797static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
32aad86f 798 const struct intel_sdvo_dtd *dtd)
e2f0ba97 799{
e2f0ba97
JB		 800 mode->hdisplay = dtd->part1.h_active;
801 mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
802 mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
171a9e96 803 mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
e2f0ba97
JB		 804 mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
805 mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
806 mode->htotal = mode->hdisplay + dtd->part1.h_blank;
807 mode->htotal += (dtd->part1.h_high & 0xf) << 8;
808
809 mode->vdisplay = dtd->part1.v_active;
810 mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
811 mode->vsync_start = mode->vdisplay;
812 mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
171a9e96 813 mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
e2f0ba97
JB		 814 mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
815 mode->vsync_end = mode->vsync_start +
816 (dtd->part2.v_sync_off_width & 0xf);
817 mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
818 mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
819 mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
820
821 mode->clock = dtd->part1.clock * 10;
822
171a9e96 823 mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
59d92bfa
DV		 824 if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
825 mode->flags |= DRM_MODE_FLAG_INTERLACE;
826 if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
e2f0ba97 827 mode->flags |= DRM_MODE_FLAG_PHSYNC;
59d92bfa 828 if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
e2f0ba97
JB		 829 mode->flags |= DRM_MODE_FLAG_PVSYNC;
830}
831
e27d8538 832static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
e2f0ba97 833{
e27d8538 834 struct intel_sdvo_encode encode;
e2f0ba97 835
1a3665c8 836 BUILD_BUG_ON(sizeof(encode) != 2);
e27d8538
CW		 837 return intel_sdvo_get_value(intel_sdvo,
838 SDVO_CMD_GET_SUPP_ENCODE,
839 &encode, sizeof(encode));
e2f0ba97
JB		 840}
841
ea5b213a 842static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
c751ce4f 843 uint8_t mode)
e2f0ba97 844{
32aad86f 845 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
e2f0ba97
JB		 846}
847
ea5b213a 848static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
e2f0ba97
JB		 849 uint8_t mode)
850{
32aad86f 851 return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
e2f0ba97
JB		 852}
853
854#if 0
ea5b213a 855static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 856{
857 int i, j;
858 uint8_t set_buf_index[2];
859 uint8_t av_split;
860 uint8_t buf_size;
861 uint8_t buf[48];
862 uint8_t *pos;
863
32aad86f 864 intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
e2f0ba97
JB		 865
866 for (i = 0; i <= av_split; i++) {
867 set_buf_index[0] = i; set_buf_index[1] = 0;
c751ce4f 868 intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
e2f0ba97 869 set_buf_index, 2);
c751ce4f
EA		 870 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
871 intel_sdvo_read_response(encoder, &buf_size, 1);
e2f0ba97
JB		 872
873 pos = buf;
874 for (j = 0; j <= buf_size; j += 8) {
c751ce4f 875 intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
e2f0ba97 876 NULL, 0);
c751ce4f 877 intel_sdvo_read_response(encoder, pos, 8);
e2f0ba97
JB		 878 pos += 8;
879 }
880 }
881}
882#endif
883
3c17fe4b 884static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo)
e2f0ba97
JB		 885{
886 struct dip_infoframe avi_if = {
887 .type = DIP_TYPE_AVI,
3c17fe4b 888 .ver = DIP_VERSION_AVI,
e2f0ba97
JB		 889 .len = DIP_LEN_AVI,
890 };
3c17fe4b
DH		 891 uint8_t tx_rate = SDVO_HBUF_TX_VSYNC;
892 uint8_t set_buf_index[2] = { 1, 0 };
81014b9d
DV		 893 uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
894 uint64_t *data = (uint64_t *)sdvo_data;
3c17fe4b
DH		 895 unsigned i;
896
897 intel_dip_infoframe_csum(&avi_if);
898
81014b9d
DV		 899 /* sdvo spec says that the ecc is handled by the hw, and it looks like
900 * we must not send the ecc field, either. */
901 memcpy(sdvo_data, &avi_if, 3);
902 sdvo_data[3] = avi_if.checksum;
903 memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
904
d121a5d2
CW		 905 if (!intel_sdvo_set_value(intel_sdvo,
906 SDVO_CMD_SET_HBUF_INDEX,
3c17fe4b
DH		 907 set_buf_index, 2))
908 return false;
909
81014b9d 910 for (i = 0; i < sizeof(sdvo_data); i += 8) {
d121a5d2
CW		 911 if (!intel_sdvo_set_value(intel_sdvo,
912 SDVO_CMD_SET_HBUF_DATA,
3c17fe4b
DH		 913 data, 8))
914 return false;
915 data++;
916 }
e2f0ba97 917
d121a5d2
CW		 918 return intel_sdvo_set_value(intel_sdvo,
919 SDVO_CMD_SET_HBUF_TXRATE,
3c17fe4b 920 &tx_rate, 1);
e2f0ba97
JB		 921}
922
32aad86f 923static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
7026d4ac 924{
ce6feabd 925 struct intel_sdvo_tv_format format;
40039750 926 uint32_t format_map;
ce6feabd 927
40039750 928 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 929 memset(&format, 0, sizeof(format));
32aad86f 930 memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
ce6feabd 931
32aad86f
CW		 932 BUILD_BUG_ON(sizeof(format) != 6);
933 return intel_sdvo_set_value(intel_sdvo,
934 SDVO_CMD_SET_TV_FORMAT,
935 &format, sizeof(format));
7026d4ac
ZW		 936}
937
32aad86f
CW		 938static bool
939intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 940 const struct drm_display_mode *mode)
e2f0ba97 941{
32aad86f 942 struct intel_sdvo_dtd output_dtd;
79e53945 943
32aad86f
CW		 944 if (!intel_sdvo_set_target_output(intel_sdvo,
945 intel_sdvo->attached_output))
946 return false;
e2f0ba97 947
32aad86f
CW		 948 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
949 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
950 return false;
e2f0ba97 951
32aad86f
CW		 952 return true;
953}
954
c9a29698
DV		 955/* Asks the sdvo controller for the preferred input mode given the output mode.
956 * Unfortunately we have to set up the full output mode to do that. */
32aad86f 957static bool
c9a29698 958intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
e811f5ae 959 const struct drm_display_mode *mode,
c9a29698 960 struct drm_display_mode *adjusted_mode)
32aad86f 961{
c9a29698
DV		 962 struct intel_sdvo_dtd input_dtd;
963
32aad86f
CW		 964 /* Reset the input timing to the screen. Assume always input 0. */
965 if (!intel_sdvo_set_target_input(intel_sdvo))
966 return false;
e2f0ba97 967
32aad86f
CW		 968 if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
969 mode->clock / 10,
970 mode->hdisplay,
971 mode->vdisplay))
972 return false;
e2f0ba97 973
32aad86f 974 if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
c9a29698 975 &input_dtd))
32aad86f 976 return false;
e2f0ba97 977
c9a29698 978 intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
79e53945 979
32aad86f
CW		 980 return true;
981}
12682a97 982
32aad86f 983static bool intel_sdvo_mode_fixup(struct drm_encoder *encoder,
e811f5ae 984 const struct drm_display_mode *mode,
32aad86f
CW		 985 struct drm_display_mode *adjusted_mode)
986{
890f3359 987 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 988 int multiplier;
12682a97 989
32aad86f
CW		 990 /* We need to construct preferred input timings based on our
991 * output timings. To do that, we have to set the output
992 * timings, even though this isn't really the right place in
993 * the sequence to do it. Oh well.
994 */
995 if (intel_sdvo->is_tv) {
996 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
997 return false;
12682a97 998
c9a29698
DV		 999 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1000 mode,
1001 adjusted_mode);
ea5b213a 1002 } else if (intel_sdvo->is_lvds) {
32aad86f 1003 if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
6c9547ff 1004 intel_sdvo->sdvo_lvds_fixed_mode))
e2f0ba97 1005 return false;
12682a97 1006
c9a29698
DV		 1007 (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
1008 mode,
1009 adjusted_mode);
e2f0ba97 1010 }
32aad86f
CW		 1011
1012 /* Make the CRTC code factor in the SDVO pixel multiplier. The
6c9547ff 1013 * SDVO device will factor out the multiplier during mode_set.
32aad86f 1014 */
6c9547ff
CW		 1015 multiplier = intel_sdvo_get_pixel_multiplier(adjusted_mode);
1016 intel_mode_set_pixel_multiplier(adjusted_mode, multiplier);
32aad86f 1017
e2f0ba97
JB		 1018 return true;
1019}
1020
1021static void intel_sdvo_mode_set(struct drm_encoder *encoder,
1022 struct drm_display_mode *mode,
1023 struct drm_display_mode *adjusted_mode)
1024{
1025 struct drm_device *dev = encoder->dev;
1026 struct drm_i915_private *dev_priv = dev->dev_private;
1027 struct drm_crtc *crtc = encoder->crtc;
1028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890f3359 1029 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
6c9547ff 1030 u32 sdvox;
e2f0ba97 1031 struct intel_sdvo_in_out_map in_out;
6651819b 1032 struct intel_sdvo_dtd input_dtd, output_dtd;
6c9547ff
CW		 1033 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
1034 int rate;
e2f0ba97
JB		 1035
1036 if (!mode)
1037 return;
1038
1039 /* First, set the input mapping for the first input to our controlled
1040 * output. This is only correct if we're a single-input device, in
1041 * which case the first input is the output from the appropriate SDVO
1042 * channel on the motherboard. In a two-input device, the first input
1043 * will be SDVOB and the second SDVOC.
1044 */
ea5b213a 1045 in_out.in0 = intel_sdvo->attached_output;
e2f0ba97
JB		 1046 in_out.in1 = 0;
1047
c74696b9
PR		 1048 intel_sdvo_set_value(intel_sdvo,
1049 SDVO_CMD_SET_IN_OUT_MAP,
1050 &in_out, sizeof(in_out));
e2f0ba97 1051
6c9547ff
CW		 1052 /* Set the output timings to the screen */
1053 if (!intel_sdvo_set_target_output(intel_sdvo,
1054 intel_sdvo->attached_output))
1055 return;
e2f0ba97 1056
6651819b
DV		 1057 /* lvds has a special fixed output timing. */
1058 if (intel_sdvo->is_lvds)
1059 intel_sdvo_get_dtd_from_mode(&output_dtd,
1060 intel_sdvo->sdvo_lvds_fixed_mode);
1061 else
1062 intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
c8d4bb54
DV		 1063 if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
1064 DRM_INFO("Setting output timings on %s failed\n",
1065 SDVO_NAME(intel_sdvo));
79e53945
JB		 1066
1067 /* Set the input timing to the screen. Assume always input 0. */
32aad86f
CW		 1068 if (!intel_sdvo_set_target_input(intel_sdvo))
1069 return;
79e53945 1070
97aaf910
CW		 1071 if (intel_sdvo->has_hdmi_monitor) {
1072 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
1073 intel_sdvo_set_colorimetry(intel_sdvo,
1074 SDVO_COLORIMETRY_RGB256);
1075 intel_sdvo_set_avi_infoframe(intel_sdvo);
1076 } else
1077 intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
7026d4ac 1078
6c9547ff
CW		 1079 if (intel_sdvo->is_tv &&
1080 !intel_sdvo_set_tv_format(intel_sdvo))
1081 return;
e2f0ba97 1082
6651819b
DV		 1083 /* We have tried to get input timing in mode_fixup, and filled into
1084 * adjusted_mode.
1085 */
1086 intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
c8d4bb54
DV		 1087 if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
1088 DRM_INFO("Setting input timings on %s failed\n",
1089 SDVO_NAME(intel_sdvo));
79e53945 1090
6c9547ff
CW		 1091 switch (pixel_multiplier) {
1092 default:
32aad86f
CW		 1093 case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
1094 case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
1095 case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
79e53945 1096 }
32aad86f
CW		 1097 if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
1098 return;
79e53945
JB		 1099
1100 /* Set the SDVO control regs. */
a6c45cf0 1101 if (INTEL_INFO(dev)->gen >= 4) {
ba68e086
PZ		 1102 /* The real mode polarity is set by the SDVO commands, using
1103 * struct intel_sdvo_dtd. */
1104 sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
e953fd7b
CW		 1105 if (intel_sdvo->is_hdmi)
1106 sdvox |= intel_sdvo->color_range;
6714afb1
CW		 1107 if (INTEL_INFO(dev)->gen < 5)
1108 sdvox |= SDVO_BORDER_ENABLE;
e2f0ba97 1109 } else {
6c9547ff 1110 sdvox = I915_READ(intel_sdvo->sdvo_reg);
ea5b213a 1111 switch (intel_sdvo->sdvo_reg) {
e2f0ba97
JB		 1112 case SDVOB:
1113 sdvox &= SDVOB_PRESERVE_MASK;
1114 break;
1115 case SDVOC:
1116 sdvox &= SDVOC_PRESERVE_MASK;
1117 break;
1118 }
1119 sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
1120 }
3573c410
PZ		 1121
1122 if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
1123 sdvox |= TRANSCODER_CPT(intel_crtc->pipe);
1124 else
1125 sdvox |= TRANSCODER(intel_crtc->pipe);
1126
da79de97 1127 if (intel_sdvo->has_hdmi_audio)
6c9547ff 1128 sdvox |= SDVO_AUDIO_ENABLE;
79e53945 1129
a6c45cf0 1130 if (INTEL_INFO(dev)->gen >= 4) {
e2f0ba97
JB		 1131 /* done in crtc_mode_set as the dpll_md reg must be written early */
1132 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
1133 /* done in crtc_mode_set as it lives inside the dpll register */
79e53945 1134 } else {
6c9547ff 1135 sdvox |= (pixel_multiplier - 1) << SDVO_PORT_MULTIPLY_SHIFT;
79e53945
JB		 1136 }
1137
6714afb1
CW		 1138 if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
1139 INTEL_INFO(dev)->gen < 5)
12682a97 1140 sdvox |= SDVO_STALL_SELECT;
ea5b213a 1141 intel_sdvo_write_sdvox(intel_sdvo, sdvox);
79e53945
JB		 1142}
1143
1144static void intel_sdvo_dpms(struct drm_encoder *encoder, int mode)
1145{
1146 struct drm_device *dev = encoder->dev;
1147 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 1148 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
9d0498a2 1149 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
79e53945
JB		 1150 u32 temp;
1151
1152 if (mode != DRM_MODE_DPMS_ON) {
ea5b213a 1153 intel_sdvo_set_active_outputs(intel_sdvo, 0);
79e53945 1154 if (0)
ea5b213a 1155 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
79e53945
JB		 1156
1157 if (mode == DRM_MODE_DPMS_OFF) {
ea5b213a 1158 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1159 if ((temp & SDVO_ENABLE) != 0) {
ea5b213a 1160 intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
79e53945
JB		 1161 }
1162 }
1163 } else {
1164 bool input1, input2;
1165 int i;
1166 u8 status;
1167
ea5b213a 1168 temp = I915_READ(intel_sdvo->sdvo_reg);
79e53945 1169 if ((temp & SDVO_ENABLE) == 0)
ea5b213a 1170 intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
79e53945 1171 for (i = 0; i < 2; i++)
9d0498a2 1172 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 1173
32aad86f 1174 status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
79e53945
JB		 1175 /* Warn if the device reported failure to sync.
1176 * A lot of SDVO devices fail to notify of sync, but it's
1177 * a given it the status is a success, we succeeded.
1178 */
1179 if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
8a4c47f3 1180 DRM_DEBUG_KMS("First %s output reported failure to "
ea5b213a 1181 "sync\n", SDVO_NAME(intel_sdvo));
79e53945
JB		 1182 }
1183
1184 if (0)
ea5b213a
CW		 1185 intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
1186 intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
79e53945
JB		 1187 }
1188 return;
1189}
1190
79e53945
JB		 1191static int intel_sdvo_mode_valid(struct drm_connector *connector,
1192 struct drm_display_mode *mode)
1193{
df0e9248 1194 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
79e53945
JB		 1195
1196 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1197 return MODE_NO_DBLESCAN;
1198
ea5b213a 1199 if (intel_sdvo->pixel_clock_min > mode->clock)
79e53945
JB		 1200 return MODE_CLOCK_LOW;
1201
ea5b213a 1202 if (intel_sdvo->pixel_clock_max < mode->clock)
79e53945
JB		 1203 return MODE_CLOCK_HIGH;
1204
8545423a 1205 if (intel_sdvo->is_lvds) {
ea5b213a 1206 if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
12682a97 1207 return MODE_PANEL;
1208
ea5b213a 1209 if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
12682a97 1210 return MODE_PANEL;
1211 }
1212
79e53945
JB		 1213 return MODE_OK;
1214}
1215
ea5b213a 1216static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
79e53945 1217{
1a3665c8 1218 BUILD_BUG_ON(sizeof(*caps) != 8);
e957d772
CW		 1219 if (!intel_sdvo_get_value(intel_sdvo,
1220 SDVO_CMD_GET_DEVICE_CAPS,
1221 caps, sizeof(*caps)))
1222 return false;
1223
1224 DRM_DEBUG_KMS("SDVO capabilities:\n"
1225 " vendor_id: %d\n"
1226 " device_id: %d\n"
1227 " device_rev_id: %d\n"
1228 " sdvo_version_major: %d\n"
1229 " sdvo_version_minor: %d\n"
1230 " sdvo_inputs_mask: %d\n"
1231 " smooth_scaling: %d\n"
1232 " sharp_scaling: %d\n"
1233 " up_scaling: %d\n"
1234 " down_scaling: %d\n"
1235 " stall_support: %d\n"
1236 " output_flags: %d\n",
1237 caps->vendor_id,
1238 caps->device_id,
1239 caps->device_rev_id,
1240 caps->sdvo_version_major,
1241 caps->sdvo_version_minor,
1242 caps->sdvo_inputs_mask,
1243 caps->smooth_scaling,
1244 caps->sharp_scaling,
1245 caps->up_scaling,
1246 caps->down_scaling,
1247 caps->stall_support,
1248 caps->output_flags);
1249
1250 return true;
79e53945
JB		 1251}
1252
cc68c81a 1253static int intel_sdvo_supports_hotplug(struct intel_sdvo *intel_sdvo)
79e53945 1254{
768b107e 1255 struct drm_device *dev = intel_sdvo->base.base.dev;
79e53945 1256 u8 response[2];
79e53945 1257
768b107e
DV		 1258 /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
1259 * on the line. */
1260 if (IS_I945G(dev) || IS_I945GM(dev))
1261 return false;
1262
32aad86f
CW		 1263 return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
1264 &response, 2) && response[0];
79e53945
JB		 1265}
1266
cc68c81a 1267static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
79e53945 1268{
cc68c81a 1269 struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
79e53945 1270
cc68c81a 1271 intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG, &intel_sdvo->hotplug_active, 2);
79e53945
JB		 1272}
1273
fb7a46f3 1274static bool
ea5b213a 1275intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
fb7a46f3 1276{
bc65212c 1277 /* Is there more than one type of output? */
2294488d 1278 return hweight16(intel_sdvo->caps.output_flags) > 1;
fb7a46f3 1279}
1280
f899fc64 1281static struct edid *
e957d772 1282intel_sdvo_get_edid(struct drm_connector *connector)
f899fc64 1283{
e957d772
CW		 1284 struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
1285 return drm_get_edid(connector, &sdvo->ddc);
f899fc64
CW		 1286}
1287
ff482d83
CW		 1288/* Mac mini hack -- use the same DDC as the analog connector */
1289static struct edid *
1290intel_sdvo_get_analog_edid(struct drm_connector *connector)
1291{
f899fc64 1292 struct drm_i915_private *dev_priv = connector->dev->dev_private;
ff482d83 1293
0c1dab89 1294 return drm_get_edid(connector,
3bd7d909
DK		 1295 intel_gmbus_get_adapter(dev_priv,
1296 dev_priv->crt_ddc_pin));
ff482d83
CW		 1297}
1298
c43b5634 1299static enum drm_connector_status
8bf38485 1300intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
9dff6af8 1301{
df0e9248 1302 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
9d1a903d
CW		 1303 enum drm_connector_status status;
1304 struct edid *edid;
9dff6af8 1305
e957d772 1306 edid = intel_sdvo_get_edid(connector);
57cdaf90 1307
ea5b213a 1308 if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
e957d772 1309 u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
9d1a903d 1310
7c3f0a27
ZY		 1311 /*
1312 * Don't use the 1 as the argument of DDC bus switch to get
1313 * the EDID. It is used for SDVO SPD ROM.
1314 */
9d1a903d 1315 for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
e957d772
CW		 1316 intel_sdvo->ddc_bus = ddc;
1317 edid = intel_sdvo_get_edid(connector);
1318 if (edid)
7c3f0a27 1319 break;
7c3f0a27 1320 }
e957d772
CW		 1321 /*
1322 * If we found the EDID on the other bus,
1323 * assume that is the correct DDC bus.
1324 */
1325 if (edid == NULL)
1326 intel_sdvo->ddc_bus = saved_ddc;
7c3f0a27 1327 }
9d1a903d
CW		 1328
1329 /*
1330 * When there is no edid and no monitor is connected with VGA
1331 * port, try to use the CRT ddc to read the EDID for DVI-connector.
57cdaf90 1332 */
ff482d83
CW		 1333 if (edid == NULL)
1334 edid = intel_sdvo_get_analog_edid(connector);
149c36a3 1335
2f551c84 1336 status = connector_status_unknown;
9dff6af8 1337 if (edid != NULL) {
149c36a3 1338 /* DDC bus is shared, match EDID to connector type */
9d1a903d
CW		 1339 if (edid->input & DRM_EDID_INPUT_DIGITAL) {
1340 status = connector_status_connected;
da79de97
CW		 1341 if (intel_sdvo->is_hdmi) {
1342 intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
1343 intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
1344 }
13946743
CW		 1345 } else
1346 status = connector_status_disconnected;
149c36a3 1347 connector->display_info.raw_edid = NULL;
9d1a903d
CW		 1348 kfree(edid);
1349 }
7f36e7ed
CW		 1350
1351 if (status == connector_status_connected) {
1352 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
c3e5f67b
DV		 1353 if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
1354 intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
7f36e7ed
CW		 1355 }
1356
2b8d33f7 1357 return status;
9dff6af8
ML		 1358}
1359
52220085
CW		 1360static bool
1361intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
1362 struct edid *edid)
1363{
1364 bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
1365 bool connector_is_digital = !!IS_DIGITAL(sdvo);
1366
1367 DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
1368 connector_is_digital, monitor_is_digital);
1369 return connector_is_digital == monitor_is_digital;
1370}
1371
7b334fcb 1372static enum drm_connector_status
930a9e28 1373intel_sdvo_detect(struct drm_connector *connector, bool force)
79e53945 1374{
fb7a46f3 1375 uint16_t response;
df0e9248 1376 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1377 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
14571b4c 1378 enum drm_connector_status ret;
79e53945 1379
32aad86f 1380 if (!intel_sdvo_write_cmd(intel_sdvo,
e957d772 1381 SDVO_CMD_GET_ATTACHED_DISPLAYS, NULL, 0))
32aad86f 1382 return connector_status_unknown;
ba84cd1f
CW		 1383
1384 /* add 30ms delay when the output type might be TV */
a0b1c7a5 1385 if (intel_sdvo->caps.output_flags & SDVO_TV_MASK)
6c982376 1386 msleep(30);
ba84cd1f 1387
32aad86f
CW		 1388 if (!intel_sdvo_read_response(intel_sdvo, &response, 2))
1389 return connector_status_unknown;
79e53945 1390
e957d772
CW		 1391 DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
1392 response & 0xff, response >> 8,
1393 intel_sdvo_connector->output_flag);
e2f0ba97 1394
fb7a46f3 1395 if (response == 0)
79e53945 1396 return connector_status_disconnected;
fb7a46f3 1397
ea5b213a 1398 intel_sdvo->attached_output = response;
14571b4c 1399
97aaf910
CW		 1400 intel_sdvo->has_hdmi_monitor = false;
1401 intel_sdvo->has_hdmi_audio = false;
1402
615fb93f 1403 if ((intel_sdvo_connector->output_flag & response) == 0)
14571b4c 1404 ret = connector_status_disconnected;
13946743 1405 else if (IS_TMDS(intel_sdvo_connector))
8bf38485 1406 ret = intel_sdvo_tmds_sink_detect(connector);
13946743
CW		 1407 else {
1408 struct edid *edid;
1409
1410 /* if we have an edid check it matches the connection */
1411 edid = intel_sdvo_get_edid(connector);
1412 if (edid == NULL)
1413 edid = intel_sdvo_get_analog_edid(connector);
1414 if (edid != NULL) {
52220085
CW		 1415 if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
1416 edid))
13946743 1417 ret = connector_status_connected;
52220085
CW		 1418 else
1419 ret = connector_status_disconnected;
1420
13946743
CW		 1421 connector->display_info.raw_edid = NULL;
1422 kfree(edid);
1423 } else
1424 ret = connector_status_connected;
1425 }
14571b4c
ZW		 1426
1427 /* May update encoder flag for like clock for SDVO TV, etc.*/
1428 if (ret == connector_status_connected) {
ea5b213a
CW		 1429 intel_sdvo->is_tv = false;
1430 intel_sdvo->is_lvds = false;
1431 intel_sdvo->base.needs_tv_clock = false;
14571b4c
ZW		 1432
1433 if (response & SDVO_TV_MASK) {
ea5b213a
CW		 1434 intel_sdvo->is_tv = true;
1435 intel_sdvo->base.needs_tv_clock = true;
14571b4c
ZW		 1436 }
1437 if (response & SDVO_LVDS_MASK)
8545423a 1438 intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
fb7a46f3 1439 }
14571b4c
ZW		 1440
1441 return ret;
79e53945
JB		 1442}
1443
e2f0ba97 1444static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
79e53945 1445{
ff482d83 1446 struct edid *edid;
79e53945
JB		 1447
1448 /* set the bus switch and get the modes */
e957d772 1449 edid = intel_sdvo_get_edid(connector);
79e53945 1450
57cdaf90
KP		 1451 /*
1452 * Mac mini hack. On this device, the DVI-I connector shares one DDC
1453 * link between analog and digital outputs. So, if the regular SDVO
1454 * DDC fails, check to see if the analog output is disconnected, in
1455 * which case we'll look there for the digital DDC data.
e2f0ba97 1456 */
f899fc64
CW		 1457 if (edid == NULL)
1458 edid = intel_sdvo_get_analog_edid(connector);
1459
ff482d83 1460 if (edid != NULL) {
52220085
CW		 1461 if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
1462 edid)) {
0c1dab89
CW		 1463 drm_mode_connector_update_edid_property(connector, edid);
1464 drm_add_edid_modes(connector, edid);
1465 }
13946743 1466
ff482d83
CW		 1467 connector->display_info.raw_edid = NULL;
1468 kfree(edid);
e2f0ba97 1469 }
e2f0ba97
JB		 1470}
1471
1472/*
1473 * Set of SDVO TV modes.
1474 * Note! This is in reply order (see loop in get_tv_modes).
1475 * XXX: all 60Hz refresh?
1476 */
b1f559ec 1477static const struct drm_display_mode sdvo_tv_modes[] = {
7026d4ac
ZW		 1478 { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
1479 416, 0, 200, 201, 232, 233, 0,
e2f0ba97 1480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1481 { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
1482 416, 0, 240, 241, 272, 273, 0,
e2f0ba97 1483 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1484 { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
1485 496, 0, 300, 301, 332, 333, 0,
e2f0ba97 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1487 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
1488 736, 0, 350, 351, 382, 383, 0,
e2f0ba97 1489 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1490 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
1491 736, 0, 400, 401, 432, 433, 0,
e2f0ba97 1492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1493 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
1494 736, 0, 480, 481, 512, 513, 0,
e2f0ba97 1495 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1496 { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
1497 800, 0, 480, 481, 512, 513, 0,
e2f0ba97 1498 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1499 { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
1500 800, 0, 576, 577, 608, 609, 0,
e2f0ba97 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1502 { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
1503 816, 0, 350, 351, 382, 383, 0,
e2f0ba97 1504 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1505 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
1506 816, 0, 400, 401, 432, 433, 0,
e2f0ba97 1507 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1508 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
1509 816, 0, 480, 481, 512, 513, 0,
e2f0ba97 1510 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1511 { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
1512 816, 0, 540, 541, 572, 573, 0,
e2f0ba97 1513 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1514 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
1515 816, 0, 576, 577, 608, 609, 0,
e2f0ba97 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1517 { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
1518 864, 0, 576, 577, 608, 609, 0,
e2f0ba97 1519 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1520 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
1521 896, 0, 600, 601, 632, 633, 0,
e2f0ba97 1522 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1523 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
1524 928, 0, 624, 625, 656, 657, 0,
e2f0ba97 1525 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1526 { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
1527 1016, 0, 766, 767, 798, 799, 0,
e2f0ba97 1528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1529 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
1530 1120, 0, 768, 769, 800, 801, 0,
e2f0ba97 1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
7026d4ac
ZW		 1532 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
1533 1376, 0, 1024, 1025, 1056, 1057, 0,
e2f0ba97
JB		 1534 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
1535};
1536
1537static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
1538{
df0e9248 1539 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7026d4ac 1540 struct intel_sdvo_sdtv_resolution_request tv_res;
ce6feabd
ZY		 1541 uint32_t reply = 0, format_map = 0;
1542 int i;
e2f0ba97
JB		 1543
1544 /* Read the list of supported input resolutions for the selected TV
1545 * format.
1546 */
40039750 1547 format_map = 1 << intel_sdvo->tv_format_index;
ce6feabd 1548 memcpy(&tv_res, &format_map,
32aad86f 1549 min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
ce6feabd 1550
32aad86f
CW		 1551 if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
1552 return;
ce6feabd 1553
32aad86f 1554 BUILD_BUG_ON(sizeof(tv_res) != 3);
e957d772
CW		 1555 if (!intel_sdvo_write_cmd(intel_sdvo,
1556 SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
32aad86f
CW		 1557 &tv_res, sizeof(tv_res)))
1558 return;
1559 if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
e2f0ba97
JB		 1560 return;
1561
1562 for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
7026d4ac
ZW		 1563 if (reply & (1 << i)) {
1564 struct drm_display_mode *nmode;
1565 nmode = drm_mode_duplicate(connector->dev,
32aad86f 1566 &sdvo_tv_modes[i]);
7026d4ac
ZW		 1567 if (nmode)
1568 drm_mode_probed_add(connector, nmode);
1569 }
e2f0ba97
JB		 1570}
1571
7086c87f
ML		 1572static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
1573{
df0e9248 1574 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
7086c87f 1575 struct drm_i915_private *dev_priv = connector->dev->dev_private;
12682a97 1576 struct drm_display_mode *newmode;
7086c87f
ML		 1577
1578 /*
1579 * Attempt to get the mode list from DDC.
1580 * Assume that the preferred modes are
1581 * arranged in priority order.
1582 */
f899fc64 1583 intel_ddc_get_modes(connector, intel_sdvo->i2c);
7086c87f 1584 if (list_empty(&connector->probed_modes) == false)
12682a97 1585 goto end;
7086c87f
ML		 1586
1587 /* Fetch modes from VBT */
1588 if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
7086c87f
ML		 1589 newmode = drm_mode_duplicate(connector->dev,
1590 dev_priv->sdvo_lvds_vbt_mode);
1591 if (newmode != NULL) {
1592 /* Guarantee the mode is preferred */
1593 newmode->type = (DRM_MODE_TYPE_PREFERRED |
1594 DRM_MODE_TYPE_DRIVER);
1595 drm_mode_probed_add(connector, newmode);
1596 }
1597 }
12682a97 1598
1599end:
1600 list_for_each_entry(newmode, &connector->probed_modes, head) {
1601 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
ea5b213a 1602 intel_sdvo->sdvo_lvds_fixed_mode =
12682a97 1603 drm_mode_duplicate(connector->dev, newmode);
6c9547ff 1604
8545423a 1605 intel_sdvo->is_lvds = true;
12682a97 1606 break;
1607 }
1608 }
1609
7086c87f
ML		 1610}
1611
e2f0ba97
JB		 1612static int intel_sdvo_get_modes(struct drm_connector *connector)
1613{
615fb93f 1614 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e2f0ba97 1615
615fb93f 1616 if (IS_TV(intel_sdvo_connector))
e2f0ba97 1617 intel_sdvo_get_tv_modes(connector);
615fb93f 1618 else if (IS_LVDS(intel_sdvo_connector))
7086c87f 1619 intel_sdvo_get_lvds_modes(connector);
e2f0ba97
JB		 1620 else
1621 intel_sdvo_get_ddc_modes(connector);
1622
32aad86f 1623 return !list_empty(&connector->probed_modes);
79e53945
JB		 1624}
1625
fcc8d672
CW		 1626static void
1627intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
b9219c5e 1628{
615fb93f 1629 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
b9219c5e
ZY		 1630 struct drm_device *dev = connector->dev;
1631
c5521706
CW		 1632 if (intel_sdvo_connector->left)
1633 drm_property_destroy(dev, intel_sdvo_connector->left);
1634 if (intel_sdvo_connector->right)
1635 drm_property_destroy(dev, intel_sdvo_connector->right);
1636 if (intel_sdvo_connector->top)
1637 drm_property_destroy(dev, intel_sdvo_connector->top);
1638 if (intel_sdvo_connector->bottom)
1639 drm_property_destroy(dev, intel_sdvo_connector->bottom);
1640 if (intel_sdvo_connector->hpos)
1641 drm_property_destroy(dev, intel_sdvo_connector->hpos);
1642 if (intel_sdvo_connector->vpos)
1643 drm_property_destroy(dev, intel_sdvo_connector->vpos);
1644 if (intel_sdvo_connector->saturation)
1645 drm_property_destroy(dev, intel_sdvo_connector->saturation);
1646 if (intel_sdvo_connector->contrast)
1647 drm_property_destroy(dev, intel_sdvo_connector->contrast);
1648 if (intel_sdvo_connector->hue)
1649 drm_property_destroy(dev, intel_sdvo_connector->hue);
1650 if (intel_sdvo_connector->sharpness)
1651 drm_property_destroy(dev, intel_sdvo_connector->sharpness);
1652 if (intel_sdvo_connector->flicker_filter)
1653 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
1654 if (intel_sdvo_connector->flicker_filter_2d)
1655 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
1656 if (intel_sdvo_connector->flicker_filter_adaptive)
1657 drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
1658 if (intel_sdvo_connector->tv_luma_filter)
1659 drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
1660 if (intel_sdvo_connector->tv_chroma_filter)
1661 drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
e044218a
CW		 1662 if (intel_sdvo_connector->dot_crawl)
1663 drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
c5521706
CW		 1664 if (intel_sdvo_connector->brightness)
1665 drm_property_destroy(dev, intel_sdvo_connector->brightness);
b9219c5e
ZY		 1666}
1667
79e53945
JB		 1668static void intel_sdvo_destroy(struct drm_connector *connector)
1669{
615fb93f 1670 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
79e53945 1671
c5521706 1672 if (intel_sdvo_connector->tv_format)
ce6feabd 1673 drm_property_destroy(connector->dev,
c5521706 1674 intel_sdvo_connector->tv_format);
b9219c5e 1675
d2a82a6f 1676 intel_sdvo_destroy_enhance_property(connector);
79e53945
JB		 1677 drm_sysfs_connector_remove(connector);
1678 drm_connector_cleanup(connector);
d2a82a6f 1679 kfree(connector);
79e53945
JB		 1680}
1681
1aad7ac0
CW		 1682static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
1683{
1684 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1685 struct edid *edid;
1686 bool has_audio = false;
1687
1688 if (!intel_sdvo->is_hdmi)
1689 return false;
1690
1691 edid = intel_sdvo_get_edid(connector);
1692 if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
1693 has_audio = drm_detect_monitor_audio(edid);
38ab8a20 1694 kfree(edid);
1aad7ac0
CW		 1695
1696 return has_audio;
1697}
1698
ce6feabd
ZY		 1699static int
1700intel_sdvo_set_property(struct drm_connector *connector,
1701 struct drm_property *property,
1702 uint64_t val)
1703{
df0e9248 1704 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
615fb93f 1705 struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
e953fd7b 1706 struct drm_i915_private *dev_priv = connector->dev->dev_private;
b9219c5e 1707 uint16_t temp_value;
32aad86f
CW		 1708 uint8_t cmd;
1709 int ret;
ce6feabd
ZY		 1710
1711 ret = drm_connector_property_set_value(connector, property, val);
32aad86f
CW		 1712 if (ret)
1713 return ret;
ce6feabd 1714
3f43c48d 1715 if (property == dev_priv->force_audio_property) {
1aad7ac0
CW		 1716 int i = val;
1717 bool has_audio;
1718
1719 if (i == intel_sdvo_connector->force_audio)
7f36e7ed
CW		 1720 return 0;
1721
1aad7ac0 1722 intel_sdvo_connector->force_audio = i;
7f36e7ed 1723
c3e5f67b 1724 if (i == HDMI_AUDIO_AUTO)
1aad7ac0
CW		 1725 has_audio = intel_sdvo_detect_hdmi_audio(connector);
1726 else
c3e5f67b 1727 has_audio = (i == HDMI_AUDIO_ON);
7f36e7ed 1728
1aad7ac0 1729 if (has_audio == intel_sdvo->has_hdmi_audio)
7f36e7ed 1730 return 0;
7f36e7ed 1731
1aad7ac0 1732 intel_sdvo->has_hdmi_audio = has_audio;
7f36e7ed
CW		 1733 goto done;
1734 }
1735
e953fd7b
CW		 1736 if (property == dev_priv->broadcast_rgb_property) {
1737 if (val == !!intel_sdvo->color_range)
7f36e7ed
CW		 1738 return 0;
1739
e953fd7b 1740 intel_sdvo->color_range = val ? SDVO_COLOR_RANGE_16_235 : 0;
7f36e7ed
CW		 1741 goto done;
1742 }
1743
c5521706
CW		 1744#define CHECK_PROPERTY(name, NAME) \
1745 if (intel_sdvo_connector->name == property) { \
1746 if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
1747 if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
1748 cmd = SDVO_CMD_SET_##NAME; \
1749 intel_sdvo_connector->cur_##name = temp_value; \
1750 goto set_value; \
1751 }
1752
1753 if (property == intel_sdvo_connector->tv_format) {
32aad86f
CW		 1754 if (val >= TV_FORMAT_NUM)
1755 return -EINVAL;
1756
40039750 1757 if (intel_sdvo->tv_format_index ==
615fb93f 1758 intel_sdvo_connector->tv_format_supported[val])
32aad86f 1759 return 0;
ce6feabd 1760
40039750 1761 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
c5521706 1762 goto done;
32aad86f 1763 } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
b9219c5e 1764 temp_value = val;
c5521706 1765 if (intel_sdvo_connector->left == property) {
b9219c5e 1766 drm_connector_property_set_value(connector,
c5521706 1767 intel_sdvo_connector->right, val);
615fb93f 1768 if (intel_sdvo_connector->left_margin == temp_value)
32aad86f 1769 return 0;
b9219c5e 1770
615fb93f
CW		 1771 intel_sdvo_connector->left_margin = temp_value;
1772 intel_sdvo_connector->right_margin = temp_value;
1773 temp_value = intel_sdvo_connector->max_hscan -
c5521706 1774 intel_sdvo_connector->left_margin;
b9219c5e 1775 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1776 goto set_value;
1777 } else if (intel_sdvo_connector->right == property) {
b9219c5e 1778 drm_connector_property_set_value(connector,
c5521706 1779 intel_sdvo_connector->left, val);
615fb93f 1780 if (intel_sdvo_connector->right_margin == temp_value)
32aad86f 1781 return 0;
b9219c5e 1782
615fb93f
CW		 1783 intel_sdvo_connector->left_margin = temp_value;
1784 intel_sdvo_connector->right_margin = temp_value;
1785 temp_value = intel_sdvo_connector->max_hscan -
1786 intel_sdvo_connector->left_margin;
b9219c5e 1787 cmd = SDVO_CMD_SET_OVERSCAN_H;
c5521706
CW		 1788 goto set_value;
1789 } else if (intel_sdvo_connector->top == property) {
b9219c5e 1790 drm_connector_property_set_value(connector,
c5521706 1791 intel_sdvo_connector->bottom, val);
615fb93f 1792 if (intel_sdvo_connector->top_margin == temp_value)
32aad86f 1793 return 0;
b9219c5e 1794
615fb93f
CW		 1795 intel_sdvo_connector->top_margin = temp_value;
1796 intel_sdvo_connector->bottom_margin = temp_value;
1797 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1798 intel_sdvo_connector->top_margin;
b9219c5e 1799 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1800 goto set_value;
1801 } else if (intel_sdvo_connector->bottom == property) {
b9219c5e 1802 drm_connector_property_set_value(connector,
c5521706 1803 intel_sdvo_connector->top, val);
615fb93f 1804 if (intel_sdvo_connector->bottom_margin == temp_value)
32aad86f
CW		 1805 return 0;
1806
615fb93f
CW		 1807 intel_sdvo_connector->top_margin = temp_value;
1808 intel_sdvo_connector->bottom_margin = temp_value;
1809 temp_value = intel_sdvo_connector->max_vscan -
c5521706 1810 intel_sdvo_connector->top_margin;
b9219c5e 1811 cmd = SDVO_CMD_SET_OVERSCAN_V;
c5521706
CW		 1812 goto set_value;
1813 }
1814 CHECK_PROPERTY(hpos, HPOS)
1815 CHECK_PROPERTY(vpos, VPOS)
1816 CHECK_PROPERTY(saturation, SATURATION)
1817 CHECK_PROPERTY(contrast, CONTRAST)
1818 CHECK_PROPERTY(hue, HUE)
1819 CHECK_PROPERTY(brightness, BRIGHTNESS)
1820 CHECK_PROPERTY(sharpness, SHARPNESS)
1821 CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
1822 CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
1823 CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
1824 CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
1825 CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
e044218a 1826 CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
c5521706 1827 }
b9219c5e 1828
c5521706 1829 return -EINVAL; /* unknown property */
b9219c5e 1830
c5521706
CW		 1831set_value:
1832 if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
1833 return -EIO;
b9219c5e 1834
b9219c5e 1835
c5521706 1836done:
df0e9248
CW		 1837 if (intel_sdvo->base.base.crtc) {
1838 struct drm_crtc *crtc = intel_sdvo->base.base.crtc;
ce6feabd 1839 drm_crtc_helper_set_mode(crtc, &crtc->mode, crtc->x,
c5521706
CW		 1840 crtc->y, crtc->fb);
1841 }
1842
32aad86f 1843 return 0;
c5521706 1844#undef CHECK_PROPERTY
ce6feabd
ZY		 1845}
1846
79e53945
JB		 1847static const struct drm_encoder_helper_funcs intel_sdvo_helper_funcs = {
1848 .dpms = intel_sdvo_dpms,
1849 .mode_fixup = intel_sdvo_mode_fixup,
1850 .prepare = intel_encoder_prepare,
1851 .mode_set = intel_sdvo_mode_set,
1852 .commit = intel_encoder_commit,
1853};
1854
1855static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
c9fb15f6 1856 .dpms = drm_helper_connector_dpms,
79e53945
JB		 1857 .detect = intel_sdvo_detect,
1858 .fill_modes = drm_helper_probe_single_connector_modes,
ce6feabd 1859 .set_property = intel_sdvo_set_property,
79e53945
JB		 1860 .destroy = intel_sdvo_destroy,
1861};
1862
1863static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
1864 .get_modes = intel_sdvo_get_modes,
1865 .mode_valid = intel_sdvo_mode_valid,
df0e9248 1866 .best_encoder = intel_best_encoder,
79e53945
JB		 1867};
1868
b358d0a6 1869static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
79e53945 1870{
890f3359 1871 struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
d2a82a6f 1872
ea5b213a 1873 if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
d2a82a6f 1874 drm_mode_destroy(encoder->dev,
ea5b213a 1875 intel_sdvo->sdvo_lvds_fixed_mode);
d2a82a6f 1876
e957d772 1877 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 1878 intel_encoder_destroy(encoder);
79e53945
JB		 1879}
1880
1881static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
1882 .destroy = intel_sdvo_enc_destroy,
1883};
1884
b66d8424
CW		 1885static void
1886intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
1887{
1888 uint16_t mask = 0;
1889 unsigned int num_bits;
1890
1891 /* Make a mask of outputs less than or equal to our own priority in the
1892 * list.
1893 */
1894 switch (sdvo->controlled_output) {
1895 case SDVO_OUTPUT_LVDS1:
1896 mask |= SDVO_OUTPUT_LVDS1;
1897 case SDVO_OUTPUT_LVDS0:
1898 mask |= SDVO_OUTPUT_LVDS0;
1899 case SDVO_OUTPUT_TMDS1:
1900 mask |= SDVO_OUTPUT_TMDS1;
1901 case SDVO_OUTPUT_TMDS0:
1902 mask |= SDVO_OUTPUT_TMDS0;
1903 case SDVO_OUTPUT_RGB1:
1904 mask |= SDVO_OUTPUT_RGB1;
1905 case SDVO_OUTPUT_RGB0:
1906 mask |= SDVO_OUTPUT_RGB0;
1907 break;
1908 }
1909
1910 /* Count bits to find what number we are in the priority list. */
1911 mask &= sdvo->caps.output_flags;
1912 num_bits = hweight16(mask);
1913 /* If more than 3 outputs, default to DDC bus 3 for now. */
1914 if (num_bits > 3)
1915 num_bits = 3;
1916
1917 /* Corresponds to SDVO_CONTROL_BUS_DDCx */
1918 sdvo->ddc_bus = 1 << num_bits;
1919}
79e53945 1920
e2f0ba97
JB		 1921/**
1922 * Choose the appropriate DDC bus for control bus switch command for this
1923 * SDVO output based on the controlled output.
1924 *
1925 * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
1926 * outputs, then LVDS outputs.
1927 */
1928static void
b1083333 1929intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
ea5b213a 1930 struct intel_sdvo *sdvo, u32 reg)
e2f0ba97 1931{
b1083333 1932 struct sdvo_device_mapping *mapping;
e2f0ba97 1933
eef4eacb 1934 if (sdvo->is_sdvob)
b1083333
AJ		 1935 mapping = &(dev_priv->sdvo_mappings[0]);
1936 else
1937 mapping = &(dev_priv->sdvo_mappings[1]);
e2f0ba97 1938
b66d8424
CW		 1939 if (mapping->initialized)
1940 sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
1941 else
1942 intel_sdvo_guess_ddc_bus(sdvo);
e2f0ba97
JB		 1943}
1944
e957d772
CW		 1945static void
1946intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
1947 struct intel_sdvo *sdvo, u32 reg)
1948{
1949 struct sdvo_device_mapping *mapping;
46eb3036 1950 u8 pin;
e957d772 1951
eef4eacb 1952 if (sdvo->is_sdvob)
e957d772
CW		 1953 mapping = &dev_priv->sdvo_mappings[0];
1954 else
1955 mapping = &dev_priv->sdvo_mappings[1];
1956
1957 pin = GMBUS_PORT_DPB;
46eb3036 1958 if (mapping->initialized)
e957d772 1959 pin = mapping->i2c_pin;
e957d772 1960
3bd7d909
DK		 1961 if (intel_gmbus_is_port_valid(pin)) {
1962 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
d5090b96 1963 intel_gmbus_set_speed(sdvo->i2c, GMBUS_RATE_1MHZ);
63abf3ed 1964 intel_gmbus_force_bit(sdvo->i2c, true);
46eb3036 1965 } else {
3bd7d909 1966 sdvo->i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
46eb3036 1967 }
e957d772
CW		 1968}
1969
e2f0ba97 1970static bool
e27d8538 1971intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
e2f0ba97 1972{
97aaf910 1973 return intel_sdvo_check_supp_encode(intel_sdvo);
e2f0ba97
JB		 1974}
1975
714605e4 1976static u8
eef4eacb 1977intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
714605e4 1978{
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 struct sdvo_device_mapping *my_mapping, *other_mapping;
1981
eef4eacb 1982 if (sdvo->is_sdvob) {
714605e4 1983 my_mapping = &dev_priv->sdvo_mappings[0];
1984 other_mapping = &dev_priv->sdvo_mappings[1];
1985 } else {
1986 my_mapping = &dev_priv->sdvo_mappings[1];
1987 other_mapping = &dev_priv->sdvo_mappings[0];
1988 }
1989
1990 /* If the BIOS described our SDVO device, take advantage of it. */
1991 if (my_mapping->slave_addr)
1992 return my_mapping->slave_addr;
1993
1994 /* If the BIOS only described a different SDVO device, use the
1995 * address that it isn't using.
1996 */
1997 if (other_mapping->slave_addr) {
1998 if (other_mapping->slave_addr == 0x70)
1999 return 0x72;
2000 else
2001 return 0x70;
2002 }
2003
2004 /* No SDVO device info is found for another DVO port,
2005 * so use mapping assumption we had before BIOS parsing.
2006 */
eef4eacb 2007 if (sdvo->is_sdvob)
714605e4 2008 return 0x70;
2009 else
2010 return 0x72;
2011}
2012
14571b4c 2013static void
df0e9248
CW		 2014intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
2015 struct intel_sdvo *encoder)
14571b4c 2016{
df0e9248
CW		 2017 drm_connector_init(encoder->base.base.dev,
2018 &connector->base.base,
2019 &intel_sdvo_connector_funcs,
2020 connector->base.base.connector_type);
6070a4a9 2021
df0e9248
CW		 2022 drm_connector_helper_add(&connector->base.base,
2023 &intel_sdvo_connector_helper_funcs);
14571b4c 2024
8f4839e2 2025 connector->base.base.interlace_allowed = 1;
df0e9248
CW		 2026 connector->base.base.doublescan_allowed = 0;
2027 connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
14571b4c 2028
df0e9248
CW		 2029 intel_connector_attach_encoder(&connector->base, &encoder->base);
2030 drm_sysfs_connector_add(&connector->base.base);
14571b4c 2031}
6070a4a9 2032
7f36e7ed
CW		 2033static void
2034intel_sdvo_add_hdmi_properties(struct intel_sdvo_connector *connector)
2035{
2036 struct drm_device *dev = connector->base.base.dev;
2037
3f43c48d 2038 intel_attach_force_audio_property(&connector->base.base);
e953fd7b
CW		 2039 if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev))
2040 intel_attach_broadcast_rgb_property(&connector->base.base);
7f36e7ed
CW		 2041}
2042
fb7a46f3 2043static bool
ea5b213a 2044intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
fb7a46f3 2045{
4ef69c7a 2046 struct drm_encoder *encoder = &intel_sdvo->base.base;
14571b4c 2047 struct drm_connector *connector;
cc68c81a 2048 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
14571b4c 2049 struct intel_connector *intel_connector;
615fb93f 2050 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2051
615fb93f
CW		 2052 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2053 if (!intel_sdvo_connector)
14571b4c
ZW		 2054 return false;
2055
14571b4c 2056 if (device == 0) {
ea5b213a 2057 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
615fb93f 2058 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
14571b4c 2059 } else if (device == 1) {
ea5b213a 2060 intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
615fb93f 2061 intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
14571b4c
ZW		 2062 }
2063
615fb93f 2064 intel_connector = &intel_sdvo_connector->base;
14571b4c 2065 connector = &intel_connector->base;
cc68c81a
SF		 2066 if (intel_sdvo_supports_hotplug(intel_sdvo) & (1 << device)) {
2067 connector->polled = DRM_CONNECTOR_POLL_HPD;
2068 intel_sdvo->hotplug_active[0] |= 1 << device;
2069 /* Some SDVO devices have one-shot hotplug interrupts.
2070 * Ensure that they get re-enabled when an interrupt happens.
2071 */
2072 intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
2073 intel_sdvo_enable_hotplug(intel_encoder);
2074 }
2075 else
2076 connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
14571b4c
ZW		 2077 encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
2078 connector->connector_type = DRM_MODE_CONNECTOR_DVID;
2079
e27d8538 2080 if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
14571b4c 2081 connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
e27d8538 2082 intel_sdvo->is_hdmi = true;
14571b4c 2083 }
ea5b213a
CW		 2084 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
2085 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2086
df0e9248 2087 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
f797d221
CW		 2088 if (intel_sdvo->is_hdmi)
2089 intel_sdvo_add_hdmi_properties(intel_sdvo_connector);
14571b4c
ZW		 2090
2091 return true;
2092}
2093
2094static bool
ea5b213a 2095intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
14571b4c 2096{
4ef69c7a
CW		 2097 struct drm_encoder *encoder = &intel_sdvo->base.base;
2098 struct drm_connector *connector;
2099 struct intel_connector *intel_connector;
2100 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2101
615fb93f
CW		 2102 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2103 if (!intel_sdvo_connector)
2104 return false;
14571b4c 2105
615fb93f 2106 intel_connector = &intel_sdvo_connector->base;
4ef69c7a
CW		 2107 connector = &intel_connector->base;
2108 encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
2109 connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
14571b4c 2110
4ef69c7a
CW		 2111 intel_sdvo->controlled_output |= type;
2112 intel_sdvo_connector->output_flag = type;
14571b4c 2113
4ef69c7a
CW		 2114 intel_sdvo->is_tv = true;
2115 intel_sdvo->base.needs_tv_clock = true;
2116 intel_sdvo->base.clone_mask = 1 << INTEL_SDVO_TV_CLONE_BIT;
14571b4c 2117
df0e9248 2118 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
14571b4c 2119
4ef69c7a 2120 if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
32aad86f 2121 goto err;
14571b4c 2122
4ef69c7a 2123 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f 2124 goto err;
14571b4c 2125
4ef69c7a 2126 return true;
32aad86f
CW		 2127
2128err:
123d5c01 2129 intel_sdvo_destroy(connector);
32aad86f 2130 return false;
14571b4c
ZW		 2131}
2132
2133static bool
ea5b213a 2134intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2135{
4ef69c7a
CW		 2136 struct drm_encoder *encoder = &intel_sdvo->base.base;
2137 struct drm_connector *connector;
2138 struct intel_connector *intel_connector;
2139 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2140
615fb93f
CW		 2141 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2142 if (!intel_sdvo_connector)
2143 return false;
14571b4c 2144
615fb93f 2145 intel_connector = &intel_sdvo_connector->base;
4ef69c7a 2146 connector = &intel_connector->base;
eb1f8e4f 2147 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
4ef69c7a
CW		 2148 encoder->encoder_type = DRM_MODE_ENCODER_DAC;
2149 connector->connector_type = DRM_MODE_CONNECTOR_VGA;
2150
2151 if (device == 0) {
2152 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
2153 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
2154 } else if (device == 1) {
2155 intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
2156 intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
2157 }
2158
2159 intel_sdvo->base.clone_mask = ((1 << INTEL_SDVO_NON_TV_CLONE_BIT) |
ea5b213a 2160 (1 << INTEL_ANALOG_CLONE_BIT));
14571b4c 2161
df0e9248
CW		 2162 intel_sdvo_connector_init(intel_sdvo_connector,
2163 intel_sdvo);
4ef69c7a 2164 return true;
14571b4c
ZW		 2165}
2166
2167static bool
ea5b213a 2168intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
14571b4c 2169{
4ef69c7a
CW		 2170 struct drm_encoder *encoder = &intel_sdvo->base.base;
2171 struct drm_connector *connector;
2172 struct intel_connector *intel_connector;
2173 struct intel_sdvo_connector *intel_sdvo_connector;
14571b4c 2174
615fb93f
CW		 2175 intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
2176 if (!intel_sdvo_connector)
2177 return false;
14571b4c 2178
615fb93f
CW		 2179 intel_connector = &intel_sdvo_connector->base;
2180 connector = &intel_connector->base;
4ef69c7a
CW		 2181 encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
2182 connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
2183
2184 if (device == 0) {
2185 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
2186 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
2187 } else if (device == 1) {
2188 intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
2189 intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
2190 }
2191
2192 intel_sdvo->base.clone_mask = ((1 << INTEL_ANALOG_CLONE_BIT) |
ea5b213a 2193 (1 << INTEL_SDVO_LVDS_CLONE_BIT));
14571b4c 2194
df0e9248 2195 intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
4ef69c7a 2196 if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
32aad86f
CW		 2197 goto err;
2198
2199 return true;
2200
2201err:
123d5c01 2202 intel_sdvo_destroy(connector);
32aad86f 2203 return false;
14571b4c
ZW		 2204}
2205
2206static bool
ea5b213a 2207intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
14571b4c 2208{
ea5b213a
CW		 2209 intel_sdvo->is_tv = false;
2210 intel_sdvo->base.needs_tv_clock = false;
2211 intel_sdvo->is_lvds = false;
fb7a46f3 2212
14571b4c 2213 /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
fb7a46f3 2214
14571b4c 2215 if (flags & SDVO_OUTPUT_TMDS0)
ea5b213a 2216 if (!intel_sdvo_dvi_init(intel_sdvo, 0))
14571b4c
ZW		 2217 return false;
2218
2219 if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
ea5b213a 2220 if (!intel_sdvo_dvi_init(intel_sdvo, 1))
14571b4c
ZW		 2221 return false;
2222
2223 /* TV has no XXX1 function block */
a1f4b7ff 2224 if (flags & SDVO_OUTPUT_SVID0)
ea5b213a 2225 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
14571b4c
ZW		 2226 return false;
2227
2228 if (flags & SDVO_OUTPUT_CVBS0)
ea5b213a 2229 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
14571b4c 2230 return false;
fb7a46f3 2231
a0b1c7a5
CW		 2232 if (flags & SDVO_OUTPUT_YPRPB0)
2233 if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
2234 return false;
2235
14571b4c 2236 if (flags & SDVO_OUTPUT_RGB0)
ea5b213a 2237 if (!intel_sdvo_analog_init(intel_sdvo, 0))
14571b4c
ZW		 2238 return false;
2239
2240 if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
ea5b213a 2241 if (!intel_sdvo_analog_init(intel_sdvo, 1))
14571b4c
ZW		 2242 return false;
2243
2244 if (flags & SDVO_OUTPUT_LVDS0)
ea5b213a 2245 if (!intel_sdvo_lvds_init(intel_sdvo, 0))
14571b4c
ZW		 2246 return false;
2247
2248 if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
ea5b213a 2249 if (!intel_sdvo_lvds_init(intel_sdvo, 1))
14571b4c 2250 return false;
fb7a46f3 2251
14571b4c 2252 if ((flags & SDVO_OUTPUT_MASK) == 0) {
fb7a46f3 2253 unsigned char bytes[2];
2254
ea5b213a
CW		 2255 intel_sdvo->controlled_output = 0;
2256 memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
51c8b407 2257 DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
ea5b213a 2258 SDVO_NAME(intel_sdvo),
51c8b407 2259 bytes[0], bytes[1]);
14571b4c 2260 return false;
fb7a46f3 2261 }
27f8227b 2262 intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
fb7a46f3 2263
14571b4c 2264 return true;
fb7a46f3 2265}
2266
32aad86f
CW		 2267static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
2268 struct intel_sdvo_connector *intel_sdvo_connector,
2269 int type)
ce6feabd 2270{
4ef69c7a 2271 struct drm_device *dev = intel_sdvo->base.base.dev;
ce6feabd
ZY		 2272 struct intel_sdvo_tv_format format;
2273 uint32_t format_map, i;
ce6feabd 2274
32aad86f
CW		 2275 if (!intel_sdvo_set_target_output(intel_sdvo, type))
2276 return false;
ce6feabd 2277
1a3665c8 2278 BUILD_BUG_ON(sizeof(format) != 6);
32aad86f
CW		 2279 if (!intel_sdvo_get_value(intel_sdvo,
2280 SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
2281 &format, sizeof(format)))
2282 return false;
ce6feabd 2283
32aad86f 2284 memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
ce6feabd
ZY		 2285
2286 if (format_map == 0)
32aad86f 2287 return false;
ce6feabd 2288
615fb93f 2289 intel_sdvo_connector->format_supported_num = 0;
ce6feabd 2290 for (i = 0 ; i < TV_FORMAT_NUM; i++)
40039750
CW		 2291 if (format_map & (1 << i))
2292 intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
ce6feabd
ZY		 2293
2294
c5521706 2295 intel_sdvo_connector->tv_format =
32aad86f
CW		 2296 drm_property_create(dev, DRM_MODE_PROP_ENUM,
2297 "mode", intel_sdvo_connector->format_supported_num);
c5521706 2298 if (!intel_sdvo_connector->tv_format)
fcc8d672 2299 return false;
ce6feabd 2300
615fb93f 2301 for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
ce6feabd 2302 drm_property_add_enum(
c5521706 2303 intel_sdvo_connector->tv_format, i,
40039750 2304 i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
ce6feabd 2305
40039750 2306 intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
32aad86f 2307 drm_connector_attach_property(&intel_sdvo_connector->base.base,
c5521706 2308 intel_sdvo_connector->tv_format, 0);
32aad86f 2309 return true;
ce6feabd
ZY		 2310
2311}
2312
c5521706
CW		 2313#define ENHANCEMENT(name, NAME) do { \
2314 if (enhancements.name) { \
2315 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
2316 !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
2317 return false; \
2318 intel_sdvo_connector->max_##name = data_value[0]; \
2319 intel_sdvo_connector->cur_##name = response; \
2320 intel_sdvo_connector->name = \
d9bc3c02 2321 drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
c5521706 2322 if (!intel_sdvo_connector->name) return false; \
c5521706
CW		 2323 drm_connector_attach_property(connector, \
2324 intel_sdvo_connector->name, \
2325 intel_sdvo_connector->cur_##name); \
2326 DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
2327 data_value[0], data_value[1], response); \
2328 } \
0206e353 2329} while (0)
c5521706
CW		 2330
2331static bool
2332intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
2333 struct intel_sdvo_connector *intel_sdvo_connector,
2334 struct intel_sdvo_enhancements_reply enhancements)
b9219c5e 2335{
4ef69c7a 2336 struct drm_device *dev = intel_sdvo->base.base.dev;
32aad86f 2337 struct drm_connector *connector = &intel_sdvo_connector->base.base;
b9219c5e
ZY		 2338 uint16_t response, data_value[2];
2339
c5521706
CW		 2340 /* when horizontal overscan is supported, Add the left/right property */
2341 if (enhancements.overscan_h) {
2342 if (!intel_sdvo_get_value(intel_sdvo,
2343 SDVO_CMD_GET_MAX_OVERSCAN_H,
2344 &data_value, 4))
2345 return false;
32aad86f 2346
c5521706
CW		 2347 if (!intel_sdvo_get_value(intel_sdvo,
2348 SDVO_CMD_GET_OVERSCAN_H,
2349 &response, 2))
2350 return false;
fcc8d672 2351
c5521706
CW		 2352 intel_sdvo_connector->max_hscan = data_value[0];
2353 intel_sdvo_connector->left_margin = data_value[0] - response;
2354 intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
2355 intel_sdvo_connector->left =
d9bc3c02 2356 drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
c5521706
CW		 2357 if (!intel_sdvo_connector->left)
2358 return false;
fcc8d672 2359
c5521706
CW		 2360 drm_connector_attach_property(connector,
2361 intel_sdvo_connector->left,
2362 intel_sdvo_connector->left_margin);
fcc8d672 2363
c5521706 2364 intel_sdvo_connector->right =
d9bc3c02 2365 drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
c5521706
CW		 2366 if (!intel_sdvo_connector->right)
2367 return false;
32aad86f 2368
c5521706
CW		 2369 drm_connector_attach_property(connector,
2370 intel_sdvo_connector->right,
2371 intel_sdvo_connector->right_margin);
2372 DRM_DEBUG_KMS("h_overscan: max %d, "
2373 "default %d, current %d\n",
2374 data_value[0], data_value[1], response);
2375 }
32aad86f 2376
c5521706
CW		 2377 if (enhancements.overscan_v) {
2378 if (!intel_sdvo_get_value(intel_sdvo,
2379 SDVO_CMD_GET_MAX_OVERSCAN_V,
2380 &data_value, 4))
2381 return false;
fcc8d672 2382
c5521706
CW		 2383 if (!intel_sdvo_get_value(intel_sdvo,
2384 SDVO_CMD_GET_OVERSCAN_V,
2385 &response, 2))
2386 return false;
32aad86f 2387
c5521706
CW		 2388 intel_sdvo_connector->max_vscan = data_value[0];
2389 intel_sdvo_connector->top_margin = data_value[0] - response;
2390 intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
2391 intel_sdvo_connector->top =
d9bc3c02
SH		 2392 drm_property_create_range(dev, 0,
2393 "top_margin", 0, data_value[0]);
c5521706
CW		 2394 if (!intel_sdvo_connector->top)
2395 return false;
32aad86f 2396
c5521706
CW		 2397 drm_connector_attach_property(connector,
2398 intel_sdvo_connector->top,
2399 intel_sdvo_connector->top_margin);
fcc8d672 2400
c5521706 2401 intel_sdvo_connector->bottom =
d9bc3c02
SH		 2402 drm_property_create_range(dev, 0,
2403 "bottom_margin", 0, data_value[0]);
c5521706
CW		 2404 if (!intel_sdvo_connector->bottom)
2405 return false;
32aad86f 2406
c5521706
CW		 2407 drm_connector_attach_property(connector,
2408 intel_sdvo_connector->bottom,
2409 intel_sdvo_connector->bottom_margin);
2410 DRM_DEBUG_KMS("v_overscan: max %d, "
2411 "default %d, current %d\n",
2412 data_value[0], data_value[1], response);
2413 }
32aad86f 2414
c5521706
CW		 2415 ENHANCEMENT(hpos, HPOS);
2416 ENHANCEMENT(vpos, VPOS);
2417 ENHANCEMENT(saturation, SATURATION);
2418 ENHANCEMENT(contrast, CONTRAST);
2419 ENHANCEMENT(hue, HUE);
2420 ENHANCEMENT(sharpness, SHARPNESS);
2421 ENHANCEMENT(brightness, BRIGHTNESS);
2422 ENHANCEMENT(flicker_filter, FLICKER_FILTER);
2423 ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
2424 ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
2425 ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
2426 ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
fcc8d672 2427
e044218a
CW		 2428 if (enhancements.dot_crawl) {
2429 if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
2430 return false;
2431
2432 intel_sdvo_connector->max_dot_crawl = 1;
2433 intel_sdvo_connector->cur_dot_crawl = response & 0x1;
2434 intel_sdvo_connector->dot_crawl =
d9bc3c02 2435 drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
e044218a
CW		 2436 if (!intel_sdvo_connector->dot_crawl)
2437 return false;
2438
e044218a
CW		 2439 drm_connector_attach_property(connector,
2440 intel_sdvo_connector->dot_crawl,
2441 intel_sdvo_connector->cur_dot_crawl);
2442 DRM_DEBUG_KMS("dot crawl: current %d\n", response);
2443 }
2444
c5521706
CW		 2445 return true;
2446}
32aad86f 2447
c5521706
CW		 2448static bool
2449intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
2450 struct intel_sdvo_connector *intel_sdvo_connector,
2451 struct intel_sdvo_enhancements_reply enhancements)
2452{
4ef69c7a 2453 struct drm_device *dev = intel_sdvo->base.base.dev;
c5521706
CW		 2454 struct drm_connector *connector = &intel_sdvo_connector->base.base;
2455 uint16_t response, data_value[2];
32aad86f 2456
c5521706 2457 ENHANCEMENT(brightness, BRIGHTNESS);
fcc8d672 2458
c5521706
CW		 2459 return true;
2460}
2461#undef ENHANCEMENT
32aad86f 2462
c5521706
CW		 2463static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
2464 struct intel_sdvo_connector *intel_sdvo_connector)
2465{
2466 union {
2467 struct intel_sdvo_enhancements_reply reply;
2468 uint16_t response;
2469 } enhancements;
32aad86f 2470
1a3665c8
CW		 2471 BUILD_BUG_ON(sizeof(enhancements) != 2);
2472
cf9a2f3a
CW		 2473 enhancements.response = 0;
2474 intel_sdvo_get_value(intel_sdvo,
2475 SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
2476 &enhancements, sizeof(enhancements));
c5521706
CW		 2477 if (enhancements.response == 0) {
2478 DRM_DEBUG_KMS("No enhancement is supported\n");
2479 return true;
b9219c5e 2480 }
32aad86f 2481
c5521706
CW		 2482 if (IS_TV(intel_sdvo_connector))
2483 return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
0206e353 2484 else if (IS_LVDS(intel_sdvo_connector))
c5521706
CW		 2485 return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
2486 else
2487 return true;
e957d772
CW		 2488}
2489
2490static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
2491 struct i2c_msg *msgs,
2492 int num)
2493{
2494 struct intel_sdvo *sdvo = adapter->algo_data;
fcc8d672 2495
e957d772
CW		 2496 if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
2497 return -EIO;
2498
2499 return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
2500}
2501
2502static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
2503{
2504 struct intel_sdvo *sdvo = adapter->algo_data;
2505 return sdvo->i2c->algo->functionality(sdvo->i2c);
2506}
2507
2508static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
2509 .master_xfer = intel_sdvo_ddc_proxy_xfer,
2510 .functionality = intel_sdvo_ddc_proxy_func
2511};
2512
2513static bool
2514intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
2515 struct drm_device *dev)
2516{
2517 sdvo->ddc.owner = THIS_MODULE;
2518 sdvo->ddc.class = I2C_CLASS_DDC;
2519 snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
2520 sdvo->ddc.dev.parent = &dev->pdev->dev;
2521 sdvo->ddc.algo_data = sdvo;
2522 sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
2523
2524 return i2c_add_adapter(&sdvo->ddc) == 0;
b9219c5e
ZY		 2525}
2526
eef4eacb 2527bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
79e53945 2528{
b01f2c3a 2529 struct drm_i915_private *dev_priv = dev->dev_private;
21d40d37 2530 struct intel_encoder *intel_encoder;
ea5b213a 2531 struct intel_sdvo *intel_sdvo;
084b612e 2532 u32 hotplug_mask;
79e53945 2533 int i;
79e53945 2534
ea5b213a
CW		 2535 intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
2536 if (!intel_sdvo)
7d57382e 2537 return false;
79e53945 2538
56184e3d 2539 intel_sdvo->sdvo_reg = sdvo_reg;
eef4eacb
DV		 2540 intel_sdvo->is_sdvob = is_sdvob;
2541 intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
56184e3d 2542 intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
e957d772
CW		 2543 if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
2544 kfree(intel_sdvo);
2545 return false;
2546 }
2547
56184e3d 2548 /* encoder type will be decided later */
ea5b213a 2549 intel_encoder = &intel_sdvo->base;
21d40d37 2550 intel_encoder->type = INTEL_OUTPUT_SDVO;
373a3cf7 2551 drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
79e53945 2552
79e53945
JB		 2553 /* Read the regs to test if we can talk to the device */
2554 for (i = 0; i < 0x40; i++) {
f899fc64
CW		 2555 u8 byte;
2556
2557 if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
eef4eacb
DV		 2558 DRM_DEBUG_KMS("No SDVO device found on %s\n",
2559 SDVO_NAME(intel_sdvo));
f899fc64 2560 goto err;
79e53945
JB		 2561 }
2562 }
2563
084b612e
CW		 2564 hotplug_mask = 0;
2565 if (IS_G4X(dev)) {
2566 hotplug_mask = intel_sdvo->is_sdvob ?
2567 SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
2568 } else if (IS_GEN4(dev)) {
2569 hotplug_mask = intel_sdvo->is_sdvob ?
2570 SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
2571 } else {
2572 hotplug_mask = intel_sdvo->is_sdvob ?
2573 SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
2574 }
619ac3b7 2575
4ef69c7a 2576 drm_encoder_helper_add(&intel_encoder->base, &intel_sdvo_helper_funcs);
14571b4c 2577
af901ca1 2578 /* In default case sdvo lvds is false */
32aad86f 2579 if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
f899fc64 2580 goto err;
79e53945 2581
ea5b213a
CW		 2582 if (intel_sdvo_output_setup(intel_sdvo,
2583 intel_sdvo->caps.output_flags) != true) {
eef4eacb
DV		 2584 DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
2585 SDVO_NAME(intel_sdvo));
f899fc64 2586 goto err;
79e53945
JB		 2587 }
2588
fcbc50da
JN		 2589 /* Only enable the hotplug irq if we need it, to work around noisy
2590 * hotplug lines.
2591 */
2592 if (intel_sdvo->hotplug_active[0])
2593 dev_priv->hotplug_supported_mask |= hotplug_mask;
2594
ea5b213a 2595 intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
e2f0ba97 2596
79e53945 2597 /* Set the input timing to the screen. Assume always input 0. */
32aad86f 2598 if (!intel_sdvo_set_target_input(intel_sdvo))
f899fc64 2599 goto err;
79e53945 2600
32aad86f
CW		 2601 if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
2602 &intel_sdvo->pixel_clock_min,
2603 &intel_sdvo->pixel_clock_max))
f899fc64 2604 goto err;
79e53945 2605
8a4c47f3 2606 DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
342dc382 2607 "clock range %dMHz - %dMHz, "
2608 "input 1: %c, input 2: %c, "
2609 "output 1: %c, output 2: %c\n",
ea5b213a
CW		 2610 SDVO_NAME(intel_sdvo),
2611 intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
2612 intel_sdvo->caps.device_rev_id,
2613 intel_sdvo->pixel_clock_min / 1000,
2614 intel_sdvo->pixel_clock_max / 1000,
2615 (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
2616 (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
342dc382 2617 /* check currently supported outputs */
ea5b213a 2618 intel_sdvo->caps.output_flags &
79e53945 2619 (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
ea5b213a 2620 intel_sdvo->caps.output_flags &
79e53945 2621 (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
7d57382e 2622 return true;
79e53945 2623
f899fc64 2624err:
373a3cf7 2625 drm_encoder_cleanup(&intel_encoder->base);
e957d772 2626 i2c_del_adapter(&intel_sdvo->ddc);
ea5b213a 2627 kfree(intel_sdvo);
79e53945 2628
7d57382e 2629 return false;
79e53945 2630}
kernel source for telekom puls (alcatel/mediatek)