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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
85208be0 | 33 | |
057d3860 | 34 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
b67a4376 | 35 | |
f6750b3c ED |
36 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
37 | * framebuffer contents in-memory, aiming at reducing the required bandwidth | |
38 | * during in-memory transfers and, therefore, reduce the power packet. | |
85208be0 | 39 | * |
f6750b3c ED |
40 | * The benefits of FBC are mostly visible with solid backgrounds and |
41 | * variation-less patterns. | |
85208be0 | 42 | * |
f6750b3c ED |
43 | * FBC-related functionality can be enabled by the means of the |
44 | * i915.i915_enable_fbc parameter | |
85208be0 ED |
45 | */ |
46 | ||
3490ea5d CW |
47 | static bool intel_crtc_active(struct drm_crtc *crtc) |
48 | { | |
49 | /* Be paranoid as we can arrive here with only partial | |
50 | * state retrieved from the hardware during setup. | |
51 | */ | |
52 | return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock; | |
53 | } | |
54 | ||
1fa61106 | 55 | static void i8xx_disable_fbc(struct drm_device *dev) |
85208be0 ED |
56 | { |
57 | struct drm_i915_private *dev_priv = dev->dev_private; | |
58 | u32 fbc_ctl; | |
59 | ||
60 | /* Disable compression */ | |
61 | fbc_ctl = I915_READ(FBC_CONTROL); | |
62 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
63 | return; | |
64 | ||
65 | fbc_ctl &= ~FBC_CTL_EN; | |
66 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
67 | ||
68 | /* Wait for compressing bit to clear */ | |
69 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
70 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
71 | return; | |
72 | } | |
73 | ||
74 | DRM_DEBUG_KMS("disabled FBC\n"); | |
75 | } | |
76 | ||
1fa61106 | 77 | static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
85208be0 ED |
78 | { |
79 | struct drm_device *dev = crtc->dev; | |
80 | struct drm_i915_private *dev_priv = dev->dev_private; | |
81 | struct drm_framebuffer *fb = crtc->fb; | |
82 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
83 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
84 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
85 | int cfb_pitch; | |
86 | int plane, i; | |
87 | u32 fbc_ctl, fbc_ctl2; | |
88 | ||
89 | cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE; | |
90 | if (fb->pitches[0] < cfb_pitch) | |
91 | cfb_pitch = fb->pitches[0]; | |
92 | ||
93 | /* FBC_CTL wants 64B units */ | |
94 | cfb_pitch = (cfb_pitch / 64) - 1; | |
95 | plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB; | |
96 | ||
97 | /* Clear old tags */ | |
98 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
99 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
100 | ||
101 | /* Set it up... */ | |
102 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
103 | fbc_ctl2 |= plane; | |
104 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); | |
105 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
106 | ||
107 | /* enable it... */ | |
108 | fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC; | |
109 | if (IS_I945GM(dev)) | |
110 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
111 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
112 | fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT; | |
113 | fbc_ctl |= obj->fence_reg; | |
114 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
115 | ||
84f44ce7 VS |
116 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ", |
117 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); | |
85208be0 ED |
118 | } |
119 | ||
1fa61106 | 120 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
121 | { |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | ||
124 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
125 | } | |
126 | ||
1fa61106 | 127 | static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
85208be0 ED |
128 | { |
129 | struct drm_device *dev = crtc->dev; | |
130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
131 | struct drm_framebuffer *fb = crtc->fb; | |
132 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
133 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
134 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
135 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; | |
136 | unsigned long stall_watermark = 200; | |
137 | u32 dpfc_ctl; | |
138 | ||
139 | dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X; | |
140 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; | |
141 | I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY); | |
142 | ||
143 | I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | | |
144 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
145 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
146 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); | |
147 | ||
148 | /* enable it... */ | |
149 | I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN); | |
150 | ||
84f44ce7 | 151 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
152 | } |
153 | ||
1fa61106 | 154 | static void g4x_disable_fbc(struct drm_device *dev) |
85208be0 ED |
155 | { |
156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
157 | u32 dpfc_ctl; | |
158 | ||
159 | /* Disable compression */ | |
160 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
161 | if (dpfc_ctl & DPFC_CTL_EN) { | |
162 | dpfc_ctl &= ~DPFC_CTL_EN; | |
163 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
164 | ||
165 | DRM_DEBUG_KMS("disabled FBC\n"); | |
166 | } | |
167 | } | |
168 | ||
1fa61106 | 169 | static bool g4x_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
170 | { |
171 | struct drm_i915_private *dev_priv = dev->dev_private; | |
172 | ||
173 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
174 | } | |
175 | ||
176 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | |
177 | { | |
178 | struct drm_i915_private *dev_priv = dev->dev_private; | |
179 | u32 blt_ecoskpd; | |
180 | ||
181 | /* Make sure blitter notifies FBC of writes */ | |
182 | gen6_gt_force_wake_get(dev_priv); | |
183 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); | |
184 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
185 | GEN6_BLITTER_LOCK_SHIFT; | |
186 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
187 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
188 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
189 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
190 | GEN6_BLITTER_LOCK_SHIFT); | |
191 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
192 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
193 | gen6_gt_force_wake_put(dev_priv); | |
194 | } | |
195 | ||
1fa61106 | 196 | static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) |
85208be0 ED |
197 | { |
198 | struct drm_device *dev = crtc->dev; | |
199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
200 | struct drm_framebuffer *fb = crtc->fb; | |
201 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
202 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
203 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
204 | int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB; | |
205 | unsigned long stall_watermark = 200; | |
206 | u32 dpfc_ctl; | |
207 | ||
208 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
209 | dpfc_ctl &= DPFC_RESERVED; | |
210 | dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); | |
211 | /* Set persistent mode for front-buffer rendering, ala X. */ | |
212 | dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; | |
213 | dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); | |
214 | I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); | |
215 | ||
216 | I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | | |
217 | (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) | | |
218 | (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT)); | |
219 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); | |
220 | I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); | |
221 | /* enable it... */ | |
222 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
223 | ||
224 | if (IS_GEN6(dev)) { | |
225 | I915_WRITE(SNB_DPFC_CTL_SA, | |
226 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
227 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
228 | sandybridge_blit_fbc_update(dev); | |
229 | } | |
230 | ||
84f44ce7 | 231 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
232 | } |
233 | ||
1fa61106 | 234 | static void ironlake_disable_fbc(struct drm_device *dev) |
85208be0 ED |
235 | { |
236 | struct drm_i915_private *dev_priv = dev->dev_private; | |
237 | u32 dpfc_ctl; | |
238 | ||
239 | /* Disable compression */ | |
240 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
241 | if (dpfc_ctl & DPFC_CTL_EN) { | |
242 | dpfc_ctl &= ~DPFC_CTL_EN; | |
243 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
244 | ||
245 | DRM_DEBUG_KMS("disabled FBC\n"); | |
246 | } | |
247 | } | |
248 | ||
1fa61106 | 249 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
250 | { |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
252 | ||
253 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
254 | } | |
255 | ||
256 | bool intel_fbc_enabled(struct drm_device *dev) | |
257 | { | |
258 | struct drm_i915_private *dev_priv = dev->dev_private; | |
259 | ||
260 | if (!dev_priv->display.fbc_enabled) | |
261 | return false; | |
262 | ||
263 | return dev_priv->display.fbc_enabled(dev); | |
264 | } | |
265 | ||
266 | static void intel_fbc_work_fn(struct work_struct *__work) | |
267 | { | |
268 | struct intel_fbc_work *work = | |
269 | container_of(to_delayed_work(__work), | |
270 | struct intel_fbc_work, work); | |
271 | struct drm_device *dev = work->crtc->dev; | |
272 | struct drm_i915_private *dev_priv = dev->dev_private; | |
273 | ||
274 | mutex_lock(&dev->struct_mutex); | |
275 | if (work == dev_priv->fbc_work) { | |
276 | /* Double check that we haven't switched fb without cancelling | |
277 | * the prior work. | |
278 | */ | |
279 | if (work->crtc->fb == work->fb) { | |
280 | dev_priv->display.enable_fbc(work->crtc, | |
281 | work->interval); | |
282 | ||
283 | dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane; | |
284 | dev_priv->cfb_fb = work->crtc->fb->base.id; | |
285 | dev_priv->cfb_y = work->crtc->y; | |
286 | } | |
287 | ||
288 | dev_priv->fbc_work = NULL; | |
289 | } | |
290 | mutex_unlock(&dev->struct_mutex); | |
291 | ||
292 | kfree(work); | |
293 | } | |
294 | ||
295 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
296 | { | |
297 | if (dev_priv->fbc_work == NULL) | |
298 | return; | |
299 | ||
300 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
301 | ||
302 | /* Synchronisation is provided by struct_mutex and checking of | |
303 | * dev_priv->fbc_work, so we can perform the cancellation | |
304 | * entirely asynchronously. | |
305 | */ | |
306 | if (cancel_delayed_work(&dev_priv->fbc_work->work)) | |
307 | /* tasklet was killed before being run, clean up */ | |
308 | kfree(dev_priv->fbc_work); | |
309 | ||
310 | /* Mark the work as no longer wanted so that if it does | |
311 | * wake-up (because the work was already running and waiting | |
312 | * for our mutex), it will discover that is no longer | |
313 | * necessary to run. | |
314 | */ | |
315 | dev_priv->fbc_work = NULL; | |
316 | } | |
317 | ||
318 | void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval) | |
319 | { | |
320 | struct intel_fbc_work *work; | |
321 | struct drm_device *dev = crtc->dev; | |
322 | struct drm_i915_private *dev_priv = dev->dev_private; | |
323 | ||
324 | if (!dev_priv->display.enable_fbc) | |
325 | return; | |
326 | ||
327 | intel_cancel_fbc_work(dev_priv); | |
328 | ||
329 | work = kzalloc(sizeof *work, GFP_KERNEL); | |
330 | if (work == NULL) { | |
331 | dev_priv->display.enable_fbc(crtc, interval); | |
332 | return; | |
333 | } | |
334 | ||
335 | work->crtc = crtc; | |
336 | work->fb = crtc->fb; | |
337 | work->interval = interval; | |
338 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); | |
339 | ||
340 | dev_priv->fbc_work = work; | |
341 | ||
342 | DRM_DEBUG_KMS("scheduling delayed FBC enable\n"); | |
343 | ||
344 | /* Delay the actual enabling to let pageflipping cease and the | |
345 | * display to settle before starting the compression. Note that | |
346 | * this delay also serves a second purpose: it allows for a | |
347 | * vblank to pass after disabling the FBC before we attempt | |
348 | * to modify the control registers. | |
349 | * | |
350 | * A more complicated solution would involve tracking vblanks | |
351 | * following the termination of the page-flipping sequence | |
352 | * and indeed performing the enable as a co-routine and not | |
353 | * waiting synchronously upon the vblank. | |
354 | */ | |
355 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
356 | } | |
357 | ||
358 | void intel_disable_fbc(struct drm_device *dev) | |
359 | { | |
360 | struct drm_i915_private *dev_priv = dev->dev_private; | |
361 | ||
362 | intel_cancel_fbc_work(dev_priv); | |
363 | ||
364 | if (!dev_priv->display.disable_fbc) | |
365 | return; | |
366 | ||
367 | dev_priv->display.disable_fbc(dev); | |
368 | dev_priv->cfb_plane = -1; | |
369 | } | |
370 | ||
371 | /** | |
372 | * intel_update_fbc - enable/disable FBC as needed | |
373 | * @dev: the drm_device | |
374 | * | |
375 | * Set up the framebuffer compression hardware at mode set time. We | |
376 | * enable it if possible: | |
377 | * - plane A only (on pre-965) | |
378 | * - no pixel mulitply/line duplication | |
379 | * - no alpha buffer discard | |
380 | * - no dual wide | |
381 | * - framebuffer <= 2048 in width, 1536 in height | |
382 | * | |
383 | * We can't assume that any compression will take place (worst case), | |
384 | * so the compressed buffer has to be the same size as the uncompressed | |
385 | * one. It also must reside (along with the line length buffer) in | |
386 | * stolen memory. | |
387 | * | |
388 | * We need to enable/disable FBC on a global basis. | |
389 | */ | |
390 | void intel_update_fbc(struct drm_device *dev) | |
391 | { | |
392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
393 | struct drm_crtc *crtc = NULL, *tmp_crtc; | |
394 | struct intel_crtc *intel_crtc; | |
395 | struct drm_framebuffer *fb; | |
396 | struct intel_framebuffer *intel_fb; | |
397 | struct drm_i915_gem_object *obj; | |
398 | int enable_fbc; | |
399 | ||
85208be0 ED |
400 | if (!i915_powersave) |
401 | return; | |
402 | ||
403 | if (!I915_HAS_FBC(dev)) | |
404 | return; | |
405 | ||
406 | /* | |
407 | * If FBC is already on, we just have to verify that we can | |
408 | * keep it that way... | |
409 | * Need to disable if: | |
410 | * - more than one pipe is active | |
411 | * - changing FBC params (stride, fence, mode) | |
412 | * - new fb is too large to fit in compressed buffer | |
413 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
414 | */ | |
415 | list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) { | |
3490ea5d CW |
416 | if (intel_crtc_active(tmp_crtc) && |
417 | !to_intel_crtc(tmp_crtc)->primary_disabled) { | |
85208be0 ED |
418 | if (crtc) { |
419 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
420 | dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES; | |
421 | goto out_disable; | |
422 | } | |
423 | crtc = tmp_crtc; | |
424 | } | |
425 | } | |
426 | ||
427 | if (!crtc || crtc->fb == NULL) { | |
428 | DRM_DEBUG_KMS("no output, disabling\n"); | |
429 | dev_priv->no_fbc_reason = FBC_NO_OUTPUT; | |
430 | goto out_disable; | |
431 | } | |
432 | ||
433 | intel_crtc = to_intel_crtc(crtc); | |
434 | fb = crtc->fb; | |
435 | intel_fb = to_intel_framebuffer(fb); | |
436 | obj = intel_fb->obj; | |
437 | ||
438 | enable_fbc = i915_enable_fbc; | |
439 | if (enable_fbc < 0) { | |
440 | DRM_DEBUG_KMS("fbc set to per-chip default\n"); | |
441 | enable_fbc = 1; | |
442 | if (INTEL_INFO(dev)->gen <= 6) | |
443 | enable_fbc = 0; | |
444 | } | |
445 | if (!enable_fbc) { | |
446 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
447 | dev_priv->no_fbc_reason = FBC_MODULE_PARAM; | |
448 | goto out_disable; | |
449 | } | |
85208be0 ED |
450 | if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) || |
451 | (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) { | |
452 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
453 | "disabling\n"); | |
454 | dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE; | |
455 | goto out_disable; | |
456 | } | |
457 | if ((crtc->mode.hdisplay > 2048) || | |
458 | (crtc->mode.vdisplay > 1536)) { | |
459 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
460 | dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE; | |
461 | goto out_disable; | |
462 | } | |
463 | if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) { | |
464 | DRM_DEBUG_KMS("plane not 0, disabling compression\n"); | |
465 | dev_priv->no_fbc_reason = FBC_BAD_PLANE; | |
466 | goto out_disable; | |
467 | } | |
468 | ||
469 | /* The use of a CPU fence is mandatory in order to detect writes | |
470 | * by the CPU to the scanout and trigger updates to the FBC. | |
471 | */ | |
472 | if (obj->tiling_mode != I915_TILING_X || | |
473 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
474 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
475 | dev_priv->no_fbc_reason = FBC_NOT_TILED; | |
476 | goto out_disable; | |
477 | } | |
478 | ||
479 | /* If the kernel debugger is active, always disable compression */ | |
480 | if (in_dbg_master()) | |
481 | goto out_disable; | |
482 | ||
11be49eb | 483 | if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) { |
11be49eb CW |
484 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); |
485 | dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL; | |
486 | goto out_disable; | |
487 | } | |
488 | ||
85208be0 ED |
489 | /* If the scanout has not changed, don't modify the FBC settings. |
490 | * Note that we make the fundamental assumption that the fb->obj | |
491 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
492 | * without first being decoupled from the scanout and FBC disabled. | |
493 | */ | |
494 | if (dev_priv->cfb_plane == intel_crtc->plane && | |
495 | dev_priv->cfb_fb == fb->base.id && | |
496 | dev_priv->cfb_y == crtc->y) | |
497 | return; | |
498 | ||
499 | if (intel_fbc_enabled(dev)) { | |
500 | /* We update FBC along two paths, after changing fb/crtc | |
501 | * configuration (modeswitching) and after page-flipping | |
502 | * finishes. For the latter, we know that not only did | |
503 | * we disable the FBC at the start of the page-flip | |
504 | * sequence, but also more than one vblank has passed. | |
505 | * | |
506 | * For the former case of modeswitching, it is possible | |
507 | * to switch between two FBC valid configurations | |
508 | * instantaneously so we do need to disable the FBC | |
509 | * before we can modify its control registers. We also | |
510 | * have to wait for the next vblank for that to take | |
511 | * effect. However, since we delay enabling FBC we can | |
512 | * assume that a vblank has passed since disabling and | |
513 | * that we can safely alter the registers in the deferred | |
514 | * callback. | |
515 | * | |
516 | * In the scenario that we go from a valid to invalid | |
517 | * and then back to valid FBC configuration we have | |
518 | * no strict enforcement that a vblank occurred since | |
519 | * disabling the FBC. However, along all current pipe | |
520 | * disabling paths we do need to wait for a vblank at | |
521 | * some point. And we wait before enabling FBC anyway. | |
522 | */ | |
523 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
524 | intel_disable_fbc(dev); | |
525 | } | |
526 | ||
527 | intel_enable_fbc(crtc, 500); | |
528 | return; | |
529 | ||
530 | out_disable: | |
531 | /* Multiple disables should be harmless */ | |
532 | if (intel_fbc_enabled(dev)) { | |
533 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
534 | intel_disable_fbc(dev); | |
535 | } | |
11be49eb | 536 | i915_gem_stolen_cleanup_compression(dev); |
85208be0 ED |
537 | } |
538 | ||
c921aba8 DV |
539 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
540 | { | |
541 | drm_i915_private_t *dev_priv = dev->dev_private; | |
542 | u32 tmp; | |
543 | ||
544 | tmp = I915_READ(CLKCFG); | |
545 | ||
546 | switch (tmp & CLKCFG_FSB_MASK) { | |
547 | case CLKCFG_FSB_533: | |
548 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
549 | break; | |
550 | case CLKCFG_FSB_800: | |
551 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
552 | break; | |
553 | case CLKCFG_FSB_667: | |
554 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
555 | break; | |
556 | case CLKCFG_FSB_400: | |
557 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
558 | break; | |
559 | } | |
560 | ||
561 | switch (tmp & CLKCFG_MEM_MASK) { | |
562 | case CLKCFG_MEM_533: | |
563 | dev_priv->mem_freq = 533; | |
564 | break; | |
565 | case CLKCFG_MEM_667: | |
566 | dev_priv->mem_freq = 667; | |
567 | break; | |
568 | case CLKCFG_MEM_800: | |
569 | dev_priv->mem_freq = 800; | |
570 | break; | |
571 | } | |
572 | ||
573 | /* detect pineview DDR3 setting */ | |
574 | tmp = I915_READ(CSHRDDR3CTL); | |
575 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
576 | } | |
577 | ||
578 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
579 | { | |
580 | drm_i915_private_t *dev_priv = dev->dev_private; | |
581 | u16 ddrpll, csipll; | |
582 | ||
583 | ddrpll = I915_READ16(DDRMPLL1); | |
584 | csipll = I915_READ16(CSIPLL0); | |
585 | ||
586 | switch (ddrpll & 0xff) { | |
587 | case 0xc: | |
588 | dev_priv->mem_freq = 800; | |
589 | break; | |
590 | case 0x10: | |
591 | dev_priv->mem_freq = 1066; | |
592 | break; | |
593 | case 0x14: | |
594 | dev_priv->mem_freq = 1333; | |
595 | break; | |
596 | case 0x18: | |
597 | dev_priv->mem_freq = 1600; | |
598 | break; | |
599 | default: | |
600 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
601 | ddrpll & 0xff); | |
602 | dev_priv->mem_freq = 0; | |
603 | break; | |
604 | } | |
605 | ||
20e4d407 | 606 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
607 | |
608 | switch (csipll & 0x3ff) { | |
609 | case 0x00c: | |
610 | dev_priv->fsb_freq = 3200; | |
611 | break; | |
612 | case 0x00e: | |
613 | dev_priv->fsb_freq = 3733; | |
614 | break; | |
615 | case 0x010: | |
616 | dev_priv->fsb_freq = 4266; | |
617 | break; | |
618 | case 0x012: | |
619 | dev_priv->fsb_freq = 4800; | |
620 | break; | |
621 | case 0x014: | |
622 | dev_priv->fsb_freq = 5333; | |
623 | break; | |
624 | case 0x016: | |
625 | dev_priv->fsb_freq = 5866; | |
626 | break; | |
627 | case 0x018: | |
628 | dev_priv->fsb_freq = 6400; | |
629 | break; | |
630 | default: | |
631 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
632 | csipll & 0x3ff); | |
633 | dev_priv->fsb_freq = 0; | |
634 | break; | |
635 | } | |
636 | ||
637 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 638 | dev_priv->ips.c_m = 0; |
c921aba8 | 639 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 640 | dev_priv->ips.c_m = 1; |
c921aba8 | 641 | } else { |
20e4d407 | 642 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
643 | } |
644 | } | |
645 | ||
b445e3b0 ED |
646 | static const struct cxsr_latency cxsr_latency_table[] = { |
647 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
648 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
649 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
650 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
651 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
652 | ||
653 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
654 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
655 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
656 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
657 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
658 | ||
659 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
660 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
661 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
662 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
663 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
664 | ||
665 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
666 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
667 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
668 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
669 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
670 | ||
671 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
672 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
673 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
674 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
675 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
676 | ||
677 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
678 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
679 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
680 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
681 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
682 | }; | |
683 | ||
63c62275 | 684 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
685 | int is_ddr3, |
686 | int fsb, | |
687 | int mem) | |
688 | { | |
689 | const struct cxsr_latency *latency; | |
690 | int i; | |
691 | ||
692 | if (fsb == 0 || mem == 0) | |
693 | return NULL; | |
694 | ||
695 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
696 | latency = &cxsr_latency_table[i]; | |
697 | if (is_desktop == latency->is_desktop && | |
698 | is_ddr3 == latency->is_ddr3 && | |
699 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
700 | return latency; | |
701 | } | |
702 | ||
703 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
704 | ||
705 | return NULL; | |
706 | } | |
707 | ||
1fa61106 | 708 | static void pineview_disable_cxsr(struct drm_device *dev) |
b445e3b0 ED |
709 | { |
710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
711 | ||
712 | /* deactivate cxsr */ | |
713 | I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN); | |
714 | } | |
715 | ||
716 | /* | |
717 | * Latency for FIFO fetches is dependent on several factors: | |
718 | * - memory configuration (speed, channels) | |
719 | * - chipset | |
720 | * - current MCH state | |
721 | * It can be fairly high in some situations, so here we assume a fairly | |
722 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
723 | * set this value too high, the FIFO will fetch frequently to stay full) | |
724 | * and power consumption (set it too low to save power and we might see | |
725 | * FIFO underruns and display "flicker"). | |
726 | * | |
727 | * A value of 5us seems to be a good balance; safe for very low end | |
728 | * platforms but not overly aggressive on lower latency configs. | |
729 | */ | |
730 | static const int latency_ns = 5000; | |
731 | ||
1fa61106 | 732 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
733 | { |
734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
735 | uint32_t dsparb = I915_READ(DSPARB); | |
736 | int size; | |
737 | ||
738 | size = dsparb & 0x7f; | |
739 | if (plane) | |
740 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
741 | ||
742 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
743 | plane ? "B" : "A", size); | |
744 | ||
745 | return size; | |
746 | } | |
747 | ||
1fa61106 | 748 | static int i85x_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
749 | { |
750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
751 | uint32_t dsparb = I915_READ(DSPARB); | |
752 | int size; | |
753 | ||
754 | size = dsparb & 0x1ff; | |
755 | if (plane) | |
756 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
757 | size >>= 1; /* Convert to cachelines */ | |
758 | ||
759 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
760 | plane ? "B" : "A", size); | |
761 | ||
762 | return size; | |
763 | } | |
764 | ||
1fa61106 | 765 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
766 | { |
767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
768 | uint32_t dsparb = I915_READ(DSPARB); | |
769 | int size; | |
770 | ||
771 | size = dsparb & 0x7f; | |
772 | size >>= 2; /* Convert to cachelines */ | |
773 | ||
774 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
775 | plane ? "B" : "A", | |
776 | size); | |
777 | ||
778 | return size; | |
779 | } | |
780 | ||
1fa61106 | 781 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
782 | { |
783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
784 | uint32_t dsparb = I915_READ(DSPARB); | |
785 | int size; | |
786 | ||
787 | size = dsparb & 0x7f; | |
788 | size >>= 1; /* Convert to cachelines */ | |
789 | ||
790 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
791 | plane ? "B" : "A", size); | |
792 | ||
793 | return size; | |
794 | } | |
795 | ||
796 | /* Pineview has different values for various configs */ | |
797 | static const struct intel_watermark_params pineview_display_wm = { | |
798 | PINEVIEW_DISPLAY_FIFO, | |
799 | PINEVIEW_MAX_WM, | |
800 | PINEVIEW_DFT_WM, | |
801 | PINEVIEW_GUARD_WM, | |
802 | PINEVIEW_FIFO_LINE_SIZE | |
803 | }; | |
804 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
805 | PINEVIEW_DISPLAY_FIFO, | |
806 | PINEVIEW_MAX_WM, | |
807 | PINEVIEW_DFT_HPLLOFF_WM, | |
808 | PINEVIEW_GUARD_WM, | |
809 | PINEVIEW_FIFO_LINE_SIZE | |
810 | }; | |
811 | static const struct intel_watermark_params pineview_cursor_wm = { | |
812 | PINEVIEW_CURSOR_FIFO, | |
813 | PINEVIEW_CURSOR_MAX_WM, | |
814 | PINEVIEW_CURSOR_DFT_WM, | |
815 | PINEVIEW_CURSOR_GUARD_WM, | |
816 | PINEVIEW_FIFO_LINE_SIZE, | |
817 | }; | |
818 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
819 | PINEVIEW_CURSOR_FIFO, | |
820 | PINEVIEW_CURSOR_MAX_WM, | |
821 | PINEVIEW_CURSOR_DFT_WM, | |
822 | PINEVIEW_CURSOR_GUARD_WM, | |
823 | PINEVIEW_FIFO_LINE_SIZE | |
824 | }; | |
825 | static const struct intel_watermark_params g4x_wm_info = { | |
826 | G4X_FIFO_SIZE, | |
827 | G4X_MAX_WM, | |
828 | G4X_MAX_WM, | |
829 | 2, | |
830 | G4X_FIFO_LINE_SIZE, | |
831 | }; | |
832 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
833 | I965_CURSOR_FIFO, | |
834 | I965_CURSOR_MAX_WM, | |
835 | I965_CURSOR_DFT_WM, | |
836 | 2, | |
837 | G4X_FIFO_LINE_SIZE, | |
838 | }; | |
839 | static const struct intel_watermark_params valleyview_wm_info = { | |
840 | VALLEYVIEW_FIFO_SIZE, | |
841 | VALLEYVIEW_MAX_WM, | |
842 | VALLEYVIEW_MAX_WM, | |
843 | 2, | |
844 | G4X_FIFO_LINE_SIZE, | |
845 | }; | |
846 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
847 | I965_CURSOR_FIFO, | |
848 | VALLEYVIEW_CURSOR_MAX_WM, | |
849 | I965_CURSOR_DFT_WM, | |
850 | 2, | |
851 | G4X_FIFO_LINE_SIZE, | |
852 | }; | |
853 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
854 | I965_CURSOR_FIFO, | |
855 | I965_CURSOR_MAX_WM, | |
856 | I965_CURSOR_DFT_WM, | |
857 | 2, | |
858 | I915_FIFO_LINE_SIZE, | |
859 | }; | |
860 | static const struct intel_watermark_params i945_wm_info = { | |
861 | I945_FIFO_SIZE, | |
862 | I915_MAX_WM, | |
863 | 1, | |
864 | 2, | |
865 | I915_FIFO_LINE_SIZE | |
866 | }; | |
867 | static const struct intel_watermark_params i915_wm_info = { | |
868 | I915_FIFO_SIZE, | |
869 | I915_MAX_WM, | |
870 | 1, | |
871 | 2, | |
872 | I915_FIFO_LINE_SIZE | |
873 | }; | |
874 | static const struct intel_watermark_params i855_wm_info = { | |
875 | I855GM_FIFO_SIZE, | |
876 | I915_MAX_WM, | |
877 | 1, | |
878 | 2, | |
879 | I830_FIFO_LINE_SIZE | |
880 | }; | |
881 | static const struct intel_watermark_params i830_wm_info = { | |
882 | I830_FIFO_SIZE, | |
883 | I915_MAX_WM, | |
884 | 1, | |
885 | 2, | |
886 | I830_FIFO_LINE_SIZE | |
887 | }; | |
888 | ||
889 | static const struct intel_watermark_params ironlake_display_wm_info = { | |
890 | ILK_DISPLAY_FIFO, | |
891 | ILK_DISPLAY_MAXWM, | |
892 | ILK_DISPLAY_DFTWM, | |
893 | 2, | |
894 | ILK_FIFO_LINE_SIZE | |
895 | }; | |
896 | static const struct intel_watermark_params ironlake_cursor_wm_info = { | |
897 | ILK_CURSOR_FIFO, | |
898 | ILK_CURSOR_MAXWM, | |
899 | ILK_CURSOR_DFTWM, | |
900 | 2, | |
901 | ILK_FIFO_LINE_SIZE | |
902 | }; | |
903 | static const struct intel_watermark_params ironlake_display_srwm_info = { | |
904 | ILK_DISPLAY_SR_FIFO, | |
905 | ILK_DISPLAY_MAX_SRWM, | |
906 | ILK_DISPLAY_DFT_SRWM, | |
907 | 2, | |
908 | ILK_FIFO_LINE_SIZE | |
909 | }; | |
910 | static const struct intel_watermark_params ironlake_cursor_srwm_info = { | |
911 | ILK_CURSOR_SR_FIFO, | |
912 | ILK_CURSOR_MAX_SRWM, | |
913 | ILK_CURSOR_DFT_SRWM, | |
914 | 2, | |
915 | ILK_FIFO_LINE_SIZE | |
916 | }; | |
917 | ||
918 | static const struct intel_watermark_params sandybridge_display_wm_info = { | |
919 | SNB_DISPLAY_FIFO, | |
920 | SNB_DISPLAY_MAXWM, | |
921 | SNB_DISPLAY_DFTWM, | |
922 | 2, | |
923 | SNB_FIFO_LINE_SIZE | |
924 | }; | |
925 | static const struct intel_watermark_params sandybridge_cursor_wm_info = { | |
926 | SNB_CURSOR_FIFO, | |
927 | SNB_CURSOR_MAXWM, | |
928 | SNB_CURSOR_DFTWM, | |
929 | 2, | |
930 | SNB_FIFO_LINE_SIZE | |
931 | }; | |
932 | static const struct intel_watermark_params sandybridge_display_srwm_info = { | |
933 | SNB_DISPLAY_SR_FIFO, | |
934 | SNB_DISPLAY_MAX_SRWM, | |
935 | SNB_DISPLAY_DFT_SRWM, | |
936 | 2, | |
937 | SNB_FIFO_LINE_SIZE | |
938 | }; | |
939 | static const struct intel_watermark_params sandybridge_cursor_srwm_info = { | |
940 | SNB_CURSOR_SR_FIFO, | |
941 | SNB_CURSOR_MAX_SRWM, | |
942 | SNB_CURSOR_DFT_SRWM, | |
943 | 2, | |
944 | SNB_FIFO_LINE_SIZE | |
945 | }; | |
946 | ||
947 | ||
948 | /** | |
949 | * intel_calculate_wm - calculate watermark level | |
950 | * @clock_in_khz: pixel clock | |
951 | * @wm: chip FIFO params | |
952 | * @pixel_size: display pixel size | |
953 | * @latency_ns: memory latency for the platform | |
954 | * | |
955 | * Calculate the watermark level (the level at which the display plane will | |
956 | * start fetching from memory again). Each chip has a different display | |
957 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
958 | * in the correct intel_watermark_params structure. | |
959 | * | |
960 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
961 | * on the pixel size. When it reaches the watermark level, it'll start | |
962 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
963 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
964 | * will occur, and a display engine hang could result. | |
965 | */ | |
966 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
967 | const struct intel_watermark_params *wm, | |
968 | int fifo_size, | |
969 | int pixel_size, | |
970 | unsigned long latency_ns) | |
971 | { | |
972 | long entries_required, wm_size; | |
973 | ||
974 | /* | |
975 | * Note: we need to make sure we don't overflow for various clock & | |
976 | * latency values. | |
977 | * clocks go from a few thousand to several hundred thousand. | |
978 | * latency is usually a few thousand | |
979 | */ | |
980 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
981 | 1000; | |
982 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
983 | ||
984 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
985 | ||
986 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
987 | ||
988 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
989 | ||
990 | /* Don't promote wm_size to unsigned... */ | |
991 | if (wm_size > (long)wm->max_wm) | |
992 | wm_size = wm->max_wm; | |
993 | if (wm_size <= 0) | |
994 | wm_size = wm->default_wm; | |
995 | return wm_size; | |
996 | } | |
997 | ||
998 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
999 | { | |
1000 | struct drm_crtc *crtc, *enabled = NULL; | |
1001 | ||
1002 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { | |
3490ea5d | 1003 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
1004 | if (enabled) |
1005 | return NULL; | |
1006 | enabled = crtc; | |
1007 | } | |
1008 | } | |
1009 | ||
1010 | return enabled; | |
1011 | } | |
1012 | ||
1fa61106 | 1013 | static void pineview_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1014 | { |
1015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1016 | struct drm_crtc *crtc; | |
1017 | const struct cxsr_latency *latency; | |
1018 | u32 reg; | |
1019 | unsigned long wm; | |
1020 | ||
1021 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
1022 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
1023 | if (!latency) { | |
1024 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
1025 | pineview_disable_cxsr(dev); | |
1026 | return; | |
1027 | } | |
1028 | ||
1029 | crtc = single_enabled_crtc(dev); | |
1030 | if (crtc) { | |
1031 | int clock = crtc->mode.clock; | |
1032 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
1033 | ||
1034 | /* Display SR */ | |
1035 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
1036 | pineview_display_wm.fifo_size, | |
1037 | pixel_size, latency->display_sr); | |
1038 | reg = I915_READ(DSPFW1); | |
1039 | reg &= ~DSPFW_SR_MASK; | |
1040 | reg |= wm << DSPFW_SR_SHIFT; | |
1041 | I915_WRITE(DSPFW1, reg); | |
1042 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
1043 | ||
1044 | /* cursor SR */ | |
1045 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
1046 | pineview_display_wm.fifo_size, | |
1047 | pixel_size, latency->cursor_sr); | |
1048 | reg = I915_READ(DSPFW3); | |
1049 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
1050 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
1051 | I915_WRITE(DSPFW3, reg); | |
1052 | ||
1053 | /* Display HPLL off SR */ | |
1054 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
1055 | pineview_display_hplloff_wm.fifo_size, | |
1056 | pixel_size, latency->display_hpll_disable); | |
1057 | reg = I915_READ(DSPFW3); | |
1058 | reg &= ~DSPFW_HPLL_SR_MASK; | |
1059 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
1060 | I915_WRITE(DSPFW3, reg); | |
1061 | ||
1062 | /* cursor HPLL off SR */ | |
1063 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
1064 | pineview_display_hplloff_wm.fifo_size, | |
1065 | pixel_size, latency->cursor_hpll_disable); | |
1066 | reg = I915_READ(DSPFW3); | |
1067 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
1068 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
1069 | I915_WRITE(DSPFW3, reg); | |
1070 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
1071 | ||
1072 | /* activate cxsr */ | |
1073 | I915_WRITE(DSPFW3, | |
1074 | I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN); | |
1075 | DRM_DEBUG_KMS("Self-refresh is enabled\n"); | |
1076 | } else { | |
1077 | pineview_disable_cxsr(dev); | |
1078 | DRM_DEBUG_KMS("Self-refresh is disabled\n"); | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | static bool g4x_compute_wm0(struct drm_device *dev, | |
1083 | int plane, | |
1084 | const struct intel_watermark_params *display, | |
1085 | int display_latency_ns, | |
1086 | const struct intel_watermark_params *cursor, | |
1087 | int cursor_latency_ns, | |
1088 | int *plane_wm, | |
1089 | int *cursor_wm) | |
1090 | { | |
1091 | struct drm_crtc *crtc; | |
1092 | int htotal, hdisplay, clock, pixel_size; | |
1093 | int line_time_us, line_count; | |
1094 | int entries, tlb_miss; | |
1095 | ||
1096 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1097 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
1098 | *cursor_wm = cursor->guard_size; |
1099 | *plane_wm = display->guard_size; | |
1100 | return false; | |
1101 | } | |
1102 | ||
1103 | htotal = crtc->mode.htotal; | |
1104 | hdisplay = crtc->mode.hdisplay; | |
1105 | clock = crtc->mode.clock; | |
1106 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
1107 | ||
1108 | /* Use the small buffer method to calculate plane watermark */ | |
1109 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
1110 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
1111 | if (tlb_miss > 0) | |
1112 | entries += tlb_miss; | |
1113 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
1114 | *plane_wm = entries + display->guard_size; | |
1115 | if (*plane_wm > (int)display->max_wm) | |
1116 | *plane_wm = display->max_wm; | |
1117 | ||
1118 | /* Use the large buffer method to calculate cursor watermark */ | |
1119 | line_time_us = ((htotal * 1000) / clock); | |
1120 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; | |
1121 | entries = line_count * 64 * pixel_size; | |
1122 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; | |
1123 | if (tlb_miss > 0) | |
1124 | entries += tlb_miss; | |
1125 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1126 | *cursor_wm = entries + cursor->guard_size; | |
1127 | if (*cursor_wm > (int)cursor->max_wm) | |
1128 | *cursor_wm = (int)cursor->max_wm; | |
1129 | ||
1130 | return true; | |
1131 | } | |
1132 | ||
1133 | /* | |
1134 | * Check the wm result. | |
1135 | * | |
1136 | * If any calculated watermark values is larger than the maximum value that | |
1137 | * can be programmed into the associated watermark register, that watermark | |
1138 | * must be disabled. | |
1139 | */ | |
1140 | static bool g4x_check_srwm(struct drm_device *dev, | |
1141 | int display_wm, int cursor_wm, | |
1142 | const struct intel_watermark_params *display, | |
1143 | const struct intel_watermark_params *cursor) | |
1144 | { | |
1145 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
1146 | display_wm, cursor_wm); | |
1147 | ||
1148 | if (display_wm > display->max_wm) { | |
1149 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
1150 | display_wm, display->max_wm); | |
1151 | return false; | |
1152 | } | |
1153 | ||
1154 | if (cursor_wm > cursor->max_wm) { | |
1155 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
1156 | cursor_wm, cursor->max_wm); | |
1157 | return false; | |
1158 | } | |
1159 | ||
1160 | if (!(display_wm || cursor_wm)) { | |
1161 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
1162 | return false; | |
1163 | } | |
1164 | ||
1165 | return true; | |
1166 | } | |
1167 | ||
1168 | static bool g4x_compute_srwm(struct drm_device *dev, | |
1169 | int plane, | |
1170 | int latency_ns, | |
1171 | const struct intel_watermark_params *display, | |
1172 | const struct intel_watermark_params *cursor, | |
1173 | int *display_wm, int *cursor_wm) | |
1174 | { | |
1175 | struct drm_crtc *crtc; | |
1176 | int hdisplay, htotal, pixel_size, clock; | |
1177 | unsigned long line_time_us; | |
1178 | int line_count, line_size; | |
1179 | int small, large; | |
1180 | int entries; | |
1181 | ||
1182 | if (!latency_ns) { | |
1183 | *display_wm = *cursor_wm = 0; | |
1184 | return false; | |
1185 | } | |
1186 | ||
1187 | crtc = intel_get_crtc_for_plane(dev, plane); | |
1188 | hdisplay = crtc->mode.hdisplay; | |
1189 | htotal = crtc->mode.htotal; | |
1190 | clock = crtc->mode.clock; | |
1191 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
1192 | ||
1193 | line_time_us = (htotal * 1000) / clock; | |
1194 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
1195 | line_size = hdisplay * pixel_size; | |
1196 | ||
1197 | /* Use the minimum of the small and large buffer method for primary */ | |
1198 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1199 | large = line_count * line_size; | |
1200 | ||
1201 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1202 | *display_wm = entries + display->guard_size; | |
1203 | ||
1204 | /* calculate the self-refresh watermark for display cursor */ | |
1205 | entries = line_count * pixel_size * 64; | |
1206 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1207 | *cursor_wm = entries + cursor->guard_size; | |
1208 | ||
1209 | return g4x_check_srwm(dev, | |
1210 | *display_wm, *cursor_wm, | |
1211 | display, cursor); | |
1212 | } | |
1213 | ||
1214 | static bool vlv_compute_drain_latency(struct drm_device *dev, | |
1215 | int plane, | |
1216 | int *plane_prec_mult, | |
1217 | int *plane_dl, | |
1218 | int *cursor_prec_mult, | |
1219 | int *cursor_dl) | |
1220 | { | |
1221 | struct drm_crtc *crtc; | |
1222 | int clock, pixel_size; | |
1223 | int entries; | |
1224 | ||
1225 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1226 | if (!intel_crtc_active(crtc)) |
b445e3b0 ED |
1227 | return false; |
1228 | ||
1229 | clock = crtc->mode.clock; /* VESA DOT Clock */ | |
1230 | pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */ | |
1231 | ||
1232 | entries = (clock / 1000) * pixel_size; | |
1233 | *plane_prec_mult = (entries > 256) ? | |
1234 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1235 | *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) * | |
1236 | pixel_size); | |
1237 | ||
1238 | entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */ | |
1239 | *cursor_prec_mult = (entries > 256) ? | |
1240 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16; | |
1241 | *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4); | |
1242 | ||
1243 | return true; | |
1244 | } | |
1245 | ||
1246 | /* | |
1247 | * Update drain latency registers of memory arbiter | |
1248 | * | |
1249 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
1250 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
1251 | * latency value. | |
1252 | */ | |
1253 | ||
1254 | static void vlv_update_drain_latency(struct drm_device *dev) | |
1255 | { | |
1256 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1257 | int planea_prec, planea_dl, planeb_prec, planeb_dl; | |
1258 | int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl; | |
1259 | int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is | |
1260 | either 16 or 32 */ | |
1261 | ||
1262 | /* For plane A, Cursor A */ | |
1263 | if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl, | |
1264 | &cursor_prec_mult, &cursora_dl)) { | |
1265 | cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1266 | DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16; | |
1267 | planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1268 | DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16; | |
1269 | ||
1270 | I915_WRITE(VLV_DDL1, cursora_prec | | |
1271 | (cursora_dl << DDL_CURSORA_SHIFT) | | |
1272 | planea_prec | planea_dl); | |
1273 | } | |
1274 | ||
1275 | /* For plane B, Cursor B */ | |
1276 | if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl, | |
1277 | &cursor_prec_mult, &cursorb_dl)) { | |
1278 | cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1279 | DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16; | |
1280 | planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ? | |
1281 | DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16; | |
1282 | ||
1283 | I915_WRITE(VLV_DDL2, cursorb_prec | | |
1284 | (cursorb_dl << DDL_CURSORB_SHIFT) | | |
1285 | planeb_prec | planeb_dl); | |
1286 | } | |
1287 | } | |
1288 | ||
1289 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
1290 | ||
1fa61106 | 1291 | static void valleyview_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1292 | { |
1293 | static const int sr_latency_ns = 12000; | |
1294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1295 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1296 | int plane_sr, cursor_sr; | |
af6c4575 | 1297 | int ignore_plane_sr, ignore_cursor_sr; |
b445e3b0 ED |
1298 | unsigned int enabled = 0; |
1299 | ||
1300 | vlv_update_drain_latency(dev); | |
1301 | ||
1302 | if (g4x_compute_wm0(dev, 0, | |
1303 | &valleyview_wm_info, latency_ns, | |
1304 | &valleyview_cursor_wm_info, latency_ns, | |
1305 | &planea_wm, &cursora_wm)) | |
1306 | enabled |= 1; | |
1307 | ||
1308 | if (g4x_compute_wm0(dev, 1, | |
1309 | &valleyview_wm_info, latency_ns, | |
1310 | &valleyview_cursor_wm_info, latency_ns, | |
1311 | &planeb_wm, &cursorb_wm)) | |
1312 | enabled |= 2; | |
1313 | ||
b445e3b0 ED |
1314 | if (single_plane_enabled(enabled) && |
1315 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1316 | sr_latency_ns, | |
1317 | &valleyview_wm_info, | |
1318 | &valleyview_cursor_wm_info, | |
af6c4575 CW |
1319 | &plane_sr, &ignore_cursor_sr) && |
1320 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1321 | 2*sr_latency_ns, | |
1322 | &valleyview_wm_info, | |
1323 | &valleyview_cursor_wm_info, | |
52bd02d8 | 1324 | &ignore_plane_sr, &cursor_sr)) { |
b445e3b0 | 1325 | I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN); |
52bd02d8 | 1326 | } else { |
b445e3b0 ED |
1327 | I915_WRITE(FW_BLC_SELF_VLV, |
1328 | I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN); | |
52bd02d8 CW |
1329 | plane_sr = cursor_sr = 0; |
1330 | } | |
b445e3b0 ED |
1331 | |
1332 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1333 | planea_wm, cursora_wm, | |
1334 | planeb_wm, cursorb_wm, | |
1335 | plane_sr, cursor_sr); | |
1336 | ||
1337 | I915_WRITE(DSPFW1, | |
1338 | (plane_sr << DSPFW_SR_SHIFT) | | |
1339 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1340 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1341 | planea_wm); | |
1342 | I915_WRITE(DSPFW2, | |
8c919b28 | 1343 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1344 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1345 | I915_WRITE(DSPFW3, | |
8c919b28 CW |
1346 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
1347 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
b445e3b0 ED |
1348 | } |
1349 | ||
1fa61106 | 1350 | static void g4x_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1351 | { |
1352 | static const int sr_latency_ns = 12000; | |
1353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1354 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1355 | int plane_sr, cursor_sr; | |
1356 | unsigned int enabled = 0; | |
1357 | ||
1358 | if (g4x_compute_wm0(dev, 0, | |
1359 | &g4x_wm_info, latency_ns, | |
1360 | &g4x_cursor_wm_info, latency_ns, | |
1361 | &planea_wm, &cursora_wm)) | |
1362 | enabled |= 1; | |
1363 | ||
1364 | if (g4x_compute_wm0(dev, 1, | |
1365 | &g4x_wm_info, latency_ns, | |
1366 | &g4x_cursor_wm_info, latency_ns, | |
1367 | &planeb_wm, &cursorb_wm)) | |
1368 | enabled |= 2; | |
1369 | ||
b445e3b0 ED |
1370 | if (single_plane_enabled(enabled) && |
1371 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1372 | sr_latency_ns, | |
1373 | &g4x_wm_info, | |
1374 | &g4x_cursor_wm_info, | |
52bd02d8 | 1375 | &plane_sr, &cursor_sr)) { |
b445e3b0 | 1376 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); |
52bd02d8 | 1377 | } else { |
b445e3b0 ED |
1378 | I915_WRITE(FW_BLC_SELF, |
1379 | I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN); | |
52bd02d8 CW |
1380 | plane_sr = cursor_sr = 0; |
1381 | } | |
b445e3b0 ED |
1382 | |
1383 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
1384 | planea_wm, cursora_wm, | |
1385 | planeb_wm, cursorb_wm, | |
1386 | plane_sr, cursor_sr); | |
1387 | ||
1388 | I915_WRITE(DSPFW1, | |
1389 | (plane_sr << DSPFW_SR_SHIFT) | | |
1390 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1391 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1392 | planea_wm); | |
1393 | I915_WRITE(DSPFW2, | |
8c919b28 | 1394 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1395 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1396 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1397 | I915_WRITE(DSPFW3, | |
8c919b28 | 1398 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
b445e3b0 ED |
1399 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
1400 | } | |
1401 | ||
1fa61106 | 1402 | static void i965_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1403 | { |
1404 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1405 | struct drm_crtc *crtc; | |
1406 | int srwm = 1; | |
1407 | int cursor_sr = 16; | |
1408 | ||
1409 | /* Calc sr entries for one plane configs */ | |
1410 | crtc = single_enabled_crtc(dev); | |
1411 | if (crtc) { | |
1412 | /* self-refresh has much higher latency */ | |
1413 | static const int sr_latency_ns = 12000; | |
1414 | int clock = crtc->mode.clock; | |
1415 | int htotal = crtc->mode.htotal; | |
1416 | int hdisplay = crtc->mode.hdisplay; | |
1417 | int pixel_size = crtc->fb->bits_per_pixel / 8; | |
1418 | unsigned long line_time_us; | |
1419 | int entries; | |
1420 | ||
1421 | line_time_us = ((htotal * 1000) / clock); | |
1422 | ||
1423 | /* Use ns/us then divide to preserve precision */ | |
1424 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1425 | pixel_size * hdisplay; | |
1426 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1427 | srwm = I965_FIFO_SIZE - entries; | |
1428 | if (srwm < 0) | |
1429 | srwm = 1; | |
1430 | srwm &= 0x1ff; | |
1431 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1432 | entries, srwm); | |
1433 | ||
1434 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1435 | pixel_size * 64; | |
1436 | entries = DIV_ROUND_UP(entries, | |
1437 | i965_cursor_wm_info.cacheline_size); | |
1438 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1439 | (entries + i965_cursor_wm_info.guard_size); | |
1440 | ||
1441 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1442 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1443 | ||
1444 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1445 | "cursor %d\n", srwm, cursor_sr); | |
1446 | ||
1447 | if (IS_CRESTLINE(dev)) | |
1448 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN); | |
1449 | } else { | |
1450 | /* Turn off self refresh if both pipes are enabled */ | |
1451 | if (IS_CRESTLINE(dev)) | |
1452 | I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF) | |
1453 | & ~FW_BLC_SELF_EN); | |
1454 | } | |
1455 | ||
1456 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1457 | srwm); | |
1458 | ||
1459 | /* 965 has limitations... */ | |
1460 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
1461 | (8 << 16) | (8 << 8) | (8 << 0)); | |
1462 | I915_WRITE(DSPFW2, (8 << 8) | (8 << 0)); | |
1463 | /* update cursor SR watermark */ | |
1464 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1465 | } | |
1466 | ||
1fa61106 | 1467 | static void i9xx_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1468 | { |
1469 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1470 | const struct intel_watermark_params *wm_info; | |
1471 | uint32_t fwater_lo; | |
1472 | uint32_t fwater_hi; | |
1473 | int cwm, srwm = 1; | |
1474 | int fifo_size; | |
1475 | int planea_wm, planeb_wm; | |
1476 | struct drm_crtc *crtc, *enabled = NULL; | |
1477 | ||
1478 | if (IS_I945GM(dev)) | |
1479 | wm_info = &i945_wm_info; | |
1480 | else if (!IS_GEN2(dev)) | |
1481 | wm_info = &i915_wm_info; | |
1482 | else | |
1483 | wm_info = &i855_wm_info; | |
1484 | ||
1485 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1486 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1487 | if (intel_crtc_active(crtc)) { |
b9e0bda3 CW |
1488 | int cpp = crtc->fb->bits_per_pixel / 8; |
1489 | if (IS_GEN2(dev)) | |
1490 | cpp = 4; | |
1491 | ||
b445e3b0 | 1492 | planea_wm = intel_calculate_wm(crtc->mode.clock, |
b9e0bda3 | 1493 | wm_info, fifo_size, cpp, |
b445e3b0 ED |
1494 | latency_ns); |
1495 | enabled = crtc; | |
1496 | } else | |
1497 | planea_wm = fifo_size - wm_info->guard_size; | |
1498 | ||
1499 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1500 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1501 | if (intel_crtc_active(crtc)) { |
b9e0bda3 CW |
1502 | int cpp = crtc->fb->bits_per_pixel / 8; |
1503 | if (IS_GEN2(dev)) | |
1504 | cpp = 4; | |
1505 | ||
b445e3b0 | 1506 | planeb_wm = intel_calculate_wm(crtc->mode.clock, |
b9e0bda3 | 1507 | wm_info, fifo_size, cpp, |
b445e3b0 ED |
1508 | latency_ns); |
1509 | if (enabled == NULL) | |
1510 | enabled = crtc; | |
1511 | else | |
1512 | enabled = NULL; | |
1513 | } else | |
1514 | planeb_wm = fifo_size - wm_info->guard_size; | |
1515 | ||
1516 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1517 | ||
1518 | /* | |
1519 | * Overlay gets an aggressive default since video jitter is bad. | |
1520 | */ | |
1521 | cwm = 2; | |
1522 | ||
1523 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
1524 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1525 | I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0); | |
1526 | else if (IS_I915GM(dev)) | |
1527 | I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN); | |
1528 | ||
1529 | /* Calc sr entries for one plane configs */ | |
1530 | if (HAS_FW_BLC(dev) && enabled) { | |
1531 | /* self-refresh has much higher latency */ | |
1532 | static const int sr_latency_ns = 6000; | |
1533 | int clock = enabled->mode.clock; | |
1534 | int htotal = enabled->mode.htotal; | |
1535 | int hdisplay = enabled->mode.hdisplay; | |
1536 | int pixel_size = enabled->fb->bits_per_pixel / 8; | |
1537 | unsigned long line_time_us; | |
1538 | int entries; | |
1539 | ||
1540 | line_time_us = (htotal * 1000) / clock; | |
1541 | ||
1542 | /* Use ns/us then divide to preserve precision */ | |
1543 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1544 | pixel_size * hdisplay; | |
1545 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1546 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1547 | srwm = wm_info->fifo_size - entries; | |
1548 | if (srwm < 0) | |
1549 | srwm = 1; | |
1550 | ||
1551 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1552 | I915_WRITE(FW_BLC_SELF, | |
1553 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1554 | else if (IS_I915GM(dev)) | |
1555 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1556 | } | |
1557 | ||
1558 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1559 | planea_wm, planeb_wm, cwm, srwm); | |
1560 | ||
1561 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1562 | fwater_hi = (cwm & 0x1f); | |
1563 | ||
1564 | /* Set request length to 8 cachelines per fetch */ | |
1565 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1566 | fwater_hi = fwater_hi | (1 << 8); | |
1567 | ||
1568 | I915_WRITE(FW_BLC, fwater_lo); | |
1569 | I915_WRITE(FW_BLC2, fwater_hi); | |
1570 | ||
1571 | if (HAS_FW_BLC(dev)) { | |
1572 | if (enabled) { | |
1573 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1574 | I915_WRITE(FW_BLC_SELF, | |
1575 | FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN); | |
1576 | else if (IS_I915GM(dev)) | |
1577 | I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN); | |
1578 | DRM_DEBUG_KMS("memory self refresh enabled\n"); | |
1579 | } else | |
1580 | DRM_DEBUG_KMS("memory self refresh disabled\n"); | |
1581 | } | |
1582 | } | |
1583 | ||
1fa61106 | 1584 | static void i830_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1585 | { |
1586 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1587 | struct drm_crtc *crtc; | |
1588 | uint32_t fwater_lo; | |
1589 | int planea_wm; | |
1590 | ||
1591 | crtc = single_enabled_crtc(dev); | |
1592 | if (crtc == NULL) | |
1593 | return; | |
1594 | ||
1595 | planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info, | |
1596 | dev_priv->display.get_fifo_size(dev, 0), | |
b9e0bda3 | 1597 | 4, latency_ns); |
b445e3b0 ED |
1598 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1599 | fwater_lo |= (3<<8) | planea_wm; | |
1600 | ||
1601 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1602 | ||
1603 | I915_WRITE(FW_BLC, fwater_lo); | |
1604 | } | |
1605 | ||
1606 | #define ILK_LP0_PLANE_LATENCY 700 | |
1607 | #define ILK_LP0_CURSOR_LATENCY 1300 | |
1608 | ||
1609 | /* | |
1610 | * Check the wm result. | |
1611 | * | |
1612 | * If any calculated watermark values is larger than the maximum value that | |
1613 | * can be programmed into the associated watermark register, that watermark | |
1614 | * must be disabled. | |
1615 | */ | |
1616 | static bool ironlake_check_srwm(struct drm_device *dev, int level, | |
1617 | int fbc_wm, int display_wm, int cursor_wm, | |
1618 | const struct intel_watermark_params *display, | |
1619 | const struct intel_watermark_params *cursor) | |
1620 | { | |
1621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1622 | ||
1623 | DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d," | |
1624 | " cursor %d\n", level, display_wm, fbc_wm, cursor_wm); | |
1625 | ||
1626 | if (fbc_wm > SNB_FBC_MAX_SRWM) { | |
1627 | DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n", | |
1628 | fbc_wm, SNB_FBC_MAX_SRWM, level); | |
1629 | ||
1630 | /* fbc has it's own way to disable FBC WM */ | |
1631 | I915_WRITE(DISP_ARB_CTL, | |
1632 | I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS); | |
1633 | return false; | |
1634 | } | |
1635 | ||
1636 | if (display_wm > display->max_wm) { | |
1637 | DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n", | |
1638 | display_wm, SNB_DISPLAY_MAX_SRWM, level); | |
1639 | return false; | |
1640 | } | |
1641 | ||
1642 | if (cursor_wm > cursor->max_wm) { | |
1643 | DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n", | |
1644 | cursor_wm, SNB_CURSOR_MAX_SRWM, level); | |
1645 | return false; | |
1646 | } | |
1647 | ||
1648 | if (!(fbc_wm || display_wm || cursor_wm)) { | |
1649 | DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level); | |
1650 | return false; | |
1651 | } | |
1652 | ||
1653 | return true; | |
1654 | } | |
1655 | ||
1656 | /* | |
1657 | * Compute watermark values of WM[1-3], | |
1658 | */ | |
1659 | static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane, | |
1660 | int latency_ns, | |
1661 | const struct intel_watermark_params *display, | |
1662 | const struct intel_watermark_params *cursor, | |
1663 | int *fbc_wm, int *display_wm, int *cursor_wm) | |
1664 | { | |
1665 | struct drm_crtc *crtc; | |
1666 | unsigned long line_time_us; | |
1667 | int hdisplay, htotal, pixel_size, clock; | |
1668 | int line_count, line_size; | |
1669 | int small, large; | |
1670 | int entries; | |
1671 | ||
1672 | if (!latency_ns) { | |
1673 | *fbc_wm = *display_wm = *cursor_wm = 0; | |
1674 | return false; | |
1675 | } | |
1676 | ||
1677 | crtc = intel_get_crtc_for_plane(dev, plane); | |
1678 | hdisplay = crtc->mode.hdisplay; | |
1679 | htotal = crtc->mode.htotal; | |
1680 | clock = crtc->mode.clock; | |
1681 | pixel_size = crtc->fb->bits_per_pixel / 8; | |
1682 | ||
1683 | line_time_us = (htotal * 1000) / clock; | |
1684 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
1685 | line_size = hdisplay * pixel_size; | |
1686 | ||
1687 | /* Use the minimum of the small and large buffer method for primary */ | |
1688 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1689 | large = line_count * line_size; | |
1690 | ||
1691 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1692 | *display_wm = entries + display->guard_size; | |
1693 | ||
1694 | /* | |
1695 | * Spec says: | |
1696 | * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2 | |
1697 | */ | |
1698 | *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2; | |
1699 | ||
1700 | /* calculate the self-refresh watermark for display cursor */ | |
1701 | entries = line_count * pixel_size * 64; | |
1702 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1703 | *cursor_wm = entries + cursor->guard_size; | |
1704 | ||
1705 | return ironlake_check_srwm(dev, level, | |
1706 | *fbc_wm, *display_wm, *cursor_wm, | |
1707 | display, cursor); | |
1708 | } | |
1709 | ||
1fa61106 | 1710 | static void ironlake_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1711 | { |
1712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1713 | int fbc_wm, plane_wm, cursor_wm; | |
1714 | unsigned int enabled; | |
1715 | ||
1716 | enabled = 0; | |
1717 | if (g4x_compute_wm0(dev, 0, | |
1718 | &ironlake_display_wm_info, | |
1719 | ILK_LP0_PLANE_LATENCY, | |
1720 | &ironlake_cursor_wm_info, | |
1721 | ILK_LP0_CURSOR_LATENCY, | |
1722 | &plane_wm, &cursor_wm)) { | |
1723 | I915_WRITE(WM0_PIPEA_ILK, | |
1724 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
1725 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
1726 | " plane %d, " "cursor: %d\n", | |
1727 | plane_wm, cursor_wm); | |
1728 | enabled |= 1; | |
1729 | } | |
1730 | ||
1731 | if (g4x_compute_wm0(dev, 1, | |
1732 | &ironlake_display_wm_info, | |
1733 | ILK_LP0_PLANE_LATENCY, | |
1734 | &ironlake_cursor_wm_info, | |
1735 | ILK_LP0_CURSOR_LATENCY, | |
1736 | &plane_wm, &cursor_wm)) { | |
1737 | I915_WRITE(WM0_PIPEB_ILK, | |
1738 | (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm); | |
1739 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
1740 | " plane %d, cursor: %d\n", | |
1741 | plane_wm, cursor_wm); | |
1742 | enabled |= 2; | |
1743 | } | |
1744 | ||
1745 | /* | |
1746 | * Calculate and update the self-refresh watermark only when one | |
1747 | * display plane is used. | |
1748 | */ | |
1749 | I915_WRITE(WM3_LP_ILK, 0); | |
1750 | I915_WRITE(WM2_LP_ILK, 0); | |
1751 | I915_WRITE(WM1_LP_ILK, 0); | |
1752 | ||
1753 | if (!single_plane_enabled(enabled)) | |
1754 | return; | |
1755 | enabled = ffs(enabled) - 1; | |
1756 | ||
1757 | /* WM1 */ | |
1758 | if (!ironlake_compute_srwm(dev, 1, enabled, | |
1759 | ILK_READ_WM1_LATENCY() * 500, | |
1760 | &ironlake_display_srwm_info, | |
1761 | &ironlake_cursor_srwm_info, | |
1762 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1763 | return; | |
1764 | ||
1765 | I915_WRITE(WM1_LP_ILK, | |
1766 | WM1_LP_SR_EN | | |
1767 | (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1768 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1769 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1770 | cursor_wm); | |
1771 | ||
1772 | /* WM2 */ | |
1773 | if (!ironlake_compute_srwm(dev, 2, enabled, | |
1774 | ILK_READ_WM2_LATENCY() * 500, | |
1775 | &ironlake_display_srwm_info, | |
1776 | &ironlake_cursor_srwm_info, | |
1777 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1778 | return; | |
1779 | ||
1780 | I915_WRITE(WM2_LP_ILK, | |
1781 | WM2_LP_EN | | |
1782 | (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1783 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1784 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1785 | cursor_wm); | |
1786 | ||
1787 | /* | |
1788 | * WM3 is unsupported on ILK, probably because we don't have latency | |
1789 | * data for that power state | |
1790 | */ | |
1791 | } | |
1792 | ||
1fa61106 | 1793 | static void sandybridge_update_wm(struct drm_device *dev) |
b445e3b0 ED |
1794 | { |
1795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1796 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
1797 | u32 val; | |
1798 | int fbc_wm, plane_wm, cursor_wm; | |
1799 | unsigned int enabled; | |
1800 | ||
1801 | enabled = 0; | |
1802 | if (g4x_compute_wm0(dev, 0, | |
1803 | &sandybridge_display_wm_info, latency, | |
1804 | &sandybridge_cursor_wm_info, latency, | |
1805 | &plane_wm, &cursor_wm)) { | |
1806 | val = I915_READ(WM0_PIPEA_ILK); | |
1807 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1808 | I915_WRITE(WM0_PIPEA_ILK, val | | |
1809 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1810 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
1811 | " plane %d, " "cursor: %d\n", | |
1812 | plane_wm, cursor_wm); | |
1813 | enabled |= 1; | |
1814 | } | |
1815 | ||
1816 | if (g4x_compute_wm0(dev, 1, | |
1817 | &sandybridge_display_wm_info, latency, | |
1818 | &sandybridge_cursor_wm_info, latency, | |
1819 | &plane_wm, &cursor_wm)) { | |
1820 | val = I915_READ(WM0_PIPEB_ILK); | |
1821 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1822 | I915_WRITE(WM0_PIPEB_ILK, val | | |
1823 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1824 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
1825 | " plane %d, cursor: %d\n", | |
1826 | plane_wm, cursor_wm); | |
1827 | enabled |= 2; | |
1828 | } | |
1829 | ||
c43d0188 CW |
1830 | /* |
1831 | * Calculate and update the self-refresh watermark only when one | |
1832 | * display plane is used. | |
1833 | * | |
1834 | * SNB support 3 levels of watermark. | |
1835 | * | |
1836 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
1837 | * and disabled in the descending order | |
1838 | * | |
1839 | */ | |
1840 | I915_WRITE(WM3_LP_ILK, 0); | |
1841 | I915_WRITE(WM2_LP_ILK, 0); | |
1842 | I915_WRITE(WM1_LP_ILK, 0); | |
1843 | ||
1844 | if (!single_plane_enabled(enabled) || | |
1845 | dev_priv->sprite_scaling_enabled) | |
1846 | return; | |
1847 | enabled = ffs(enabled) - 1; | |
1848 | ||
1849 | /* WM1 */ | |
1850 | if (!ironlake_compute_srwm(dev, 1, enabled, | |
1851 | SNB_READ_WM1_LATENCY() * 500, | |
1852 | &sandybridge_display_srwm_info, | |
1853 | &sandybridge_cursor_srwm_info, | |
1854 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1855 | return; | |
1856 | ||
1857 | I915_WRITE(WM1_LP_ILK, | |
1858 | WM1_LP_SR_EN | | |
1859 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1860 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1861 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1862 | cursor_wm); | |
1863 | ||
1864 | /* WM2 */ | |
1865 | if (!ironlake_compute_srwm(dev, 2, enabled, | |
1866 | SNB_READ_WM2_LATENCY() * 500, | |
1867 | &sandybridge_display_srwm_info, | |
1868 | &sandybridge_cursor_srwm_info, | |
1869 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1870 | return; | |
1871 | ||
1872 | I915_WRITE(WM2_LP_ILK, | |
1873 | WM2_LP_EN | | |
1874 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1875 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1876 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1877 | cursor_wm); | |
1878 | ||
1879 | /* WM3 */ | |
1880 | if (!ironlake_compute_srwm(dev, 3, enabled, | |
1881 | SNB_READ_WM3_LATENCY() * 500, | |
1882 | &sandybridge_display_srwm_info, | |
1883 | &sandybridge_cursor_srwm_info, | |
1884 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1885 | return; | |
1886 | ||
1887 | I915_WRITE(WM3_LP_ILK, | |
1888 | WM3_LP_EN | | |
1889 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1890 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1891 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1892 | cursor_wm); | |
1893 | } | |
1894 | ||
1895 | static void ivybridge_update_wm(struct drm_device *dev) | |
1896 | { | |
1897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1898 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
1899 | u32 val; | |
1900 | int fbc_wm, plane_wm, cursor_wm; | |
1901 | int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm; | |
1902 | unsigned int enabled; | |
1903 | ||
1904 | enabled = 0; | |
1905 | if (g4x_compute_wm0(dev, 0, | |
1906 | &sandybridge_display_wm_info, latency, | |
1907 | &sandybridge_cursor_wm_info, latency, | |
1908 | &plane_wm, &cursor_wm)) { | |
1909 | val = I915_READ(WM0_PIPEA_ILK); | |
1910 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1911 | I915_WRITE(WM0_PIPEA_ILK, val | | |
1912 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1913 | DRM_DEBUG_KMS("FIFO watermarks For pipe A -" | |
1914 | " plane %d, " "cursor: %d\n", | |
1915 | plane_wm, cursor_wm); | |
1916 | enabled |= 1; | |
1917 | } | |
1918 | ||
1919 | if (g4x_compute_wm0(dev, 1, | |
1920 | &sandybridge_display_wm_info, latency, | |
1921 | &sandybridge_cursor_wm_info, latency, | |
1922 | &plane_wm, &cursor_wm)) { | |
1923 | val = I915_READ(WM0_PIPEB_ILK); | |
1924 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1925 | I915_WRITE(WM0_PIPEB_ILK, val | | |
1926 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1927 | DRM_DEBUG_KMS("FIFO watermarks For pipe B -" | |
1928 | " plane %d, cursor: %d\n", | |
1929 | plane_wm, cursor_wm); | |
1930 | enabled |= 2; | |
1931 | } | |
1932 | ||
1933 | if (g4x_compute_wm0(dev, 2, | |
b445e3b0 ED |
1934 | &sandybridge_display_wm_info, latency, |
1935 | &sandybridge_cursor_wm_info, latency, | |
1936 | &plane_wm, &cursor_wm)) { | |
1937 | val = I915_READ(WM0_PIPEC_IVB); | |
1938 | val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK); | |
1939 | I915_WRITE(WM0_PIPEC_IVB, val | | |
1940 | ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm)); | |
1941 | DRM_DEBUG_KMS("FIFO watermarks For pipe C -" | |
1942 | " plane %d, cursor: %d\n", | |
1943 | plane_wm, cursor_wm); | |
1944 | enabled |= 3; | |
1945 | } | |
1946 | ||
1947 | /* | |
1948 | * Calculate and update the self-refresh watermark only when one | |
1949 | * display plane is used. | |
1950 | * | |
1951 | * SNB support 3 levels of watermark. | |
1952 | * | |
1953 | * WM1/WM2/WM2 watermarks have to be enabled in the ascending order, | |
1954 | * and disabled in the descending order | |
1955 | * | |
1956 | */ | |
1957 | I915_WRITE(WM3_LP_ILK, 0); | |
1958 | I915_WRITE(WM2_LP_ILK, 0); | |
1959 | I915_WRITE(WM1_LP_ILK, 0); | |
1960 | ||
1961 | if (!single_plane_enabled(enabled) || | |
1962 | dev_priv->sprite_scaling_enabled) | |
1963 | return; | |
1964 | enabled = ffs(enabled) - 1; | |
1965 | ||
1966 | /* WM1 */ | |
1967 | if (!ironlake_compute_srwm(dev, 1, enabled, | |
1968 | SNB_READ_WM1_LATENCY() * 500, | |
1969 | &sandybridge_display_srwm_info, | |
1970 | &sandybridge_cursor_srwm_info, | |
1971 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1972 | return; | |
1973 | ||
1974 | I915_WRITE(WM1_LP_ILK, | |
1975 | WM1_LP_SR_EN | | |
1976 | (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1977 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1978 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1979 | cursor_wm); | |
1980 | ||
1981 | /* WM2 */ | |
1982 | if (!ironlake_compute_srwm(dev, 2, enabled, | |
1983 | SNB_READ_WM2_LATENCY() * 500, | |
1984 | &sandybridge_display_srwm_info, | |
1985 | &sandybridge_cursor_srwm_info, | |
1986 | &fbc_wm, &plane_wm, &cursor_wm)) | |
1987 | return; | |
1988 | ||
1989 | I915_WRITE(WM2_LP_ILK, | |
1990 | WM2_LP_EN | | |
1991 | (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
1992 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
1993 | (plane_wm << WM1_LP_SR_SHIFT) | | |
1994 | cursor_wm); | |
1995 | ||
c43d0188 | 1996 | /* WM3, note we have to correct the cursor latency */ |
b445e3b0 ED |
1997 | if (!ironlake_compute_srwm(dev, 3, enabled, |
1998 | SNB_READ_WM3_LATENCY() * 500, | |
1999 | &sandybridge_display_srwm_info, | |
2000 | &sandybridge_cursor_srwm_info, | |
c43d0188 CW |
2001 | &fbc_wm, &plane_wm, &ignore_cursor_wm) || |
2002 | !ironlake_compute_srwm(dev, 3, enabled, | |
2003 | 2 * SNB_READ_WM3_LATENCY() * 500, | |
2004 | &sandybridge_display_srwm_info, | |
2005 | &sandybridge_cursor_srwm_info, | |
2006 | &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm)) | |
b445e3b0 ED |
2007 | return; |
2008 | ||
2009 | I915_WRITE(WM3_LP_ILK, | |
2010 | WM3_LP_EN | | |
2011 | (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) | | |
2012 | (fbc_wm << WM1_LP_FBC_SHIFT) | | |
2013 | (plane_wm << WM1_LP_SR_SHIFT) | | |
2014 | cursor_wm); | |
2015 | } | |
2016 | ||
1f8eeabf ED |
2017 | static void |
2018 | haswell_update_linetime_wm(struct drm_device *dev, int pipe, | |
2019 | struct drm_display_mode *mode) | |
2020 | { | |
2021 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2022 | u32 temp; | |
2023 | ||
2024 | temp = I915_READ(PIPE_WM_LINETIME(pipe)); | |
2025 | temp &= ~PIPE_WM_LINETIME_MASK; | |
2026 | ||
2027 | /* The WM are computed with base on how long it takes to fill a single | |
2028 | * row at the given clock rate, multiplied by 8. | |
2029 | * */ | |
2030 | temp |= PIPE_WM_LINETIME_TIME( | |
2031 | ((mode->crtc_hdisplay * 1000) / mode->clock) * 8); | |
2032 | ||
2033 | /* IPS watermarks are only used by pipe A, and are ignored by | |
2034 | * pipes B and C. They are calculated similarly to the common | |
2035 | * linetime values, except that we are using CD clock frequency | |
2036 | * in MHz instead of pixel rate for the division. | |
2037 | * | |
2038 | * This is a placeholder for the IPS watermark calculation code. | |
2039 | */ | |
2040 | ||
2041 | I915_WRITE(PIPE_WM_LINETIME(pipe), temp); | |
2042 | } | |
2043 | ||
b445e3b0 ED |
2044 | static bool |
2045 | sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, | |
2046 | uint32_t sprite_width, int pixel_size, | |
2047 | const struct intel_watermark_params *display, | |
2048 | int display_latency_ns, int *sprite_wm) | |
2049 | { | |
2050 | struct drm_crtc *crtc; | |
2051 | int clock; | |
2052 | int entries, tlb_miss; | |
2053 | ||
2054 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 2055 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
2056 | *sprite_wm = display->guard_size; |
2057 | return false; | |
2058 | } | |
2059 | ||
2060 | clock = crtc->mode.clock; | |
2061 | ||
2062 | /* Use the small buffer method to calculate the sprite watermark */ | |
2063 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
2064 | tlb_miss = display->fifo_size*display->cacheline_size - | |
2065 | sprite_width * 8; | |
2066 | if (tlb_miss > 0) | |
2067 | entries += tlb_miss; | |
2068 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
2069 | *sprite_wm = entries + display->guard_size; | |
2070 | if (*sprite_wm > (int)display->max_wm) | |
2071 | *sprite_wm = display->max_wm; | |
2072 | ||
2073 | return true; | |
2074 | } | |
2075 | ||
2076 | static bool | |
2077 | sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane, | |
2078 | uint32_t sprite_width, int pixel_size, | |
2079 | const struct intel_watermark_params *display, | |
2080 | int latency_ns, int *sprite_wm) | |
2081 | { | |
2082 | struct drm_crtc *crtc; | |
2083 | unsigned long line_time_us; | |
2084 | int clock; | |
2085 | int line_count, line_size; | |
2086 | int small, large; | |
2087 | int entries; | |
2088 | ||
2089 | if (!latency_ns) { | |
2090 | *sprite_wm = 0; | |
2091 | return false; | |
2092 | } | |
2093 | ||
2094 | crtc = intel_get_crtc_for_plane(dev, plane); | |
2095 | clock = crtc->mode.clock; | |
2096 | if (!clock) { | |
2097 | *sprite_wm = 0; | |
2098 | return false; | |
2099 | } | |
2100 | ||
2101 | line_time_us = (sprite_width * 1000) / clock; | |
2102 | if (!line_time_us) { | |
2103 | *sprite_wm = 0; | |
2104 | return false; | |
2105 | } | |
2106 | ||
2107 | line_count = (latency_ns / line_time_us + 1000) / 1000; | |
2108 | line_size = sprite_width * pixel_size; | |
2109 | ||
2110 | /* Use the minimum of the small and large buffer method for primary */ | |
2111 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
2112 | large = line_count * line_size; | |
2113 | ||
2114 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
2115 | *sprite_wm = entries + display->guard_size; | |
2116 | ||
2117 | return *sprite_wm > 0x3ff ? false : true; | |
2118 | } | |
2119 | ||
1fa61106 | 2120 | static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe, |
b445e3b0 ED |
2121 | uint32_t sprite_width, int pixel_size) |
2122 | { | |
2123 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2124 | int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */ | |
2125 | u32 val; | |
2126 | int sprite_wm, reg; | |
2127 | int ret; | |
2128 | ||
2129 | switch (pipe) { | |
2130 | case 0: | |
2131 | reg = WM0_PIPEA_ILK; | |
2132 | break; | |
2133 | case 1: | |
2134 | reg = WM0_PIPEB_ILK; | |
2135 | break; | |
2136 | case 2: | |
2137 | reg = WM0_PIPEC_IVB; | |
2138 | break; | |
2139 | default: | |
2140 | return; /* bad pipe */ | |
2141 | } | |
2142 | ||
2143 | ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size, | |
2144 | &sandybridge_display_wm_info, | |
2145 | latency, &sprite_wm); | |
2146 | if (!ret) { | |
84f44ce7 VS |
2147 | DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n", |
2148 | pipe_name(pipe)); | |
b445e3b0 ED |
2149 | return; |
2150 | } | |
2151 | ||
2152 | val = I915_READ(reg); | |
2153 | val &= ~WM0_PIPE_SPRITE_MASK; | |
2154 | I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT)); | |
84f44ce7 | 2155 | DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm); |
b445e3b0 ED |
2156 | |
2157 | ||
2158 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
2159 | pixel_size, | |
2160 | &sandybridge_display_srwm_info, | |
2161 | SNB_READ_WM1_LATENCY() * 500, | |
2162 | &sprite_wm); | |
2163 | if (!ret) { | |
84f44ce7 VS |
2164 | DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n", |
2165 | pipe_name(pipe)); | |
b445e3b0 ED |
2166 | return; |
2167 | } | |
2168 | I915_WRITE(WM1S_LP_ILK, sprite_wm); | |
2169 | ||
2170 | /* Only IVB has two more LP watermarks for sprite */ | |
2171 | if (!IS_IVYBRIDGE(dev)) | |
2172 | return; | |
2173 | ||
2174 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
2175 | pixel_size, | |
2176 | &sandybridge_display_srwm_info, | |
2177 | SNB_READ_WM2_LATENCY() * 500, | |
2178 | &sprite_wm); | |
2179 | if (!ret) { | |
84f44ce7 VS |
2180 | DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n", |
2181 | pipe_name(pipe)); | |
b445e3b0 ED |
2182 | return; |
2183 | } | |
2184 | I915_WRITE(WM2S_LP_IVB, sprite_wm); | |
2185 | ||
2186 | ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width, | |
2187 | pixel_size, | |
2188 | &sandybridge_display_srwm_info, | |
2189 | SNB_READ_WM3_LATENCY() * 500, | |
2190 | &sprite_wm); | |
2191 | if (!ret) { | |
84f44ce7 VS |
2192 | DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n", |
2193 | pipe_name(pipe)); | |
b445e3b0 ED |
2194 | return; |
2195 | } | |
2196 | I915_WRITE(WM3S_LP_IVB, sprite_wm); | |
2197 | } | |
2198 | ||
2199 | /** | |
2200 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
2201 | * | |
2202 | * Calculate watermark values for the various WM regs based on current mode | |
2203 | * and plane configuration. | |
2204 | * | |
2205 | * There are several cases to deal with here: | |
2206 | * - normal (i.e. non-self-refresh) | |
2207 | * - self-refresh (SR) mode | |
2208 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
2209 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
2210 | * lines), so need to account for TLB latency | |
2211 | * | |
2212 | * The normal calculation is: | |
2213 | * watermark = dotclock * bytes per pixel * latency | |
2214 | * where latency is platform & configuration dependent (we assume pessimal | |
2215 | * values here). | |
2216 | * | |
2217 | * The SR calculation is: | |
2218 | * watermark = (trunc(latency/line time)+1) * surface width * | |
2219 | * bytes per pixel | |
2220 | * where | |
2221 | * line time = htotal / dotclock | |
2222 | * surface width = hdisplay for normal plane and 64 for cursor | |
2223 | * and latency is assumed to be high, as above. | |
2224 | * | |
2225 | * The final value programmed to the register should always be rounded up, | |
2226 | * and include an extra 2 entries to account for clock crossings. | |
2227 | * | |
2228 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
2229 | * to set the non-SR watermarks to 8. | |
2230 | */ | |
2231 | void intel_update_watermarks(struct drm_device *dev) | |
2232 | { | |
2233 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2234 | ||
2235 | if (dev_priv->display.update_wm) | |
2236 | dev_priv->display.update_wm(dev); | |
2237 | } | |
2238 | ||
1f8eeabf ED |
2239 | void intel_update_linetime_watermarks(struct drm_device *dev, |
2240 | int pipe, struct drm_display_mode *mode) | |
2241 | { | |
2242 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2243 | ||
2244 | if (dev_priv->display.update_linetime_wm) | |
2245 | dev_priv->display.update_linetime_wm(dev, pipe, mode); | |
2246 | } | |
2247 | ||
b445e3b0 ED |
2248 | void intel_update_sprite_watermarks(struct drm_device *dev, int pipe, |
2249 | uint32_t sprite_width, int pixel_size) | |
2250 | { | |
2251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2252 | ||
2253 | if (dev_priv->display.update_sprite_wm) | |
2254 | dev_priv->display.update_sprite_wm(dev, pipe, sprite_width, | |
2255 | pixel_size); | |
2256 | } | |
2257 | ||
2b4e57bd ED |
2258 | static struct drm_i915_gem_object * |
2259 | intel_alloc_context_page(struct drm_device *dev) | |
2260 | { | |
2261 | struct drm_i915_gem_object *ctx; | |
2262 | int ret; | |
2263 | ||
2264 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
2265 | ||
2266 | ctx = i915_gem_alloc_object(dev, 4096); | |
2267 | if (!ctx) { | |
2268 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | |
2269 | return NULL; | |
2270 | } | |
2271 | ||
86a1ee26 | 2272 | ret = i915_gem_object_pin(ctx, 4096, true, false); |
2b4e57bd ED |
2273 | if (ret) { |
2274 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
2275 | goto err_unref; | |
2276 | } | |
2277 | ||
2278 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); | |
2279 | if (ret) { | |
2280 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
2281 | goto err_unpin; | |
2282 | } | |
2283 | ||
2284 | return ctx; | |
2285 | ||
2286 | err_unpin: | |
2287 | i915_gem_object_unpin(ctx); | |
2288 | err_unref: | |
2289 | drm_gem_object_unreference(&ctx->base); | |
2b4e57bd ED |
2290 | return NULL; |
2291 | } | |
2292 | ||
9270388e DV |
2293 | /** |
2294 | * Lock protecting IPS related data structures | |
9270388e DV |
2295 | */ |
2296 | DEFINE_SPINLOCK(mchdev_lock); | |
2297 | ||
2298 | /* Global for IPS driver to get at the current i915 device. Protected by | |
2299 | * mchdev_lock. */ | |
2300 | static struct drm_i915_private *i915_mch_dev; | |
2301 | ||
2b4e57bd ED |
2302 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
2303 | { | |
2304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2305 | u16 rgvswctl; | |
2306 | ||
9270388e DV |
2307 | assert_spin_locked(&mchdev_lock); |
2308 | ||
2b4e57bd ED |
2309 | rgvswctl = I915_READ16(MEMSWCTL); |
2310 | if (rgvswctl & MEMCTL_CMD_STS) { | |
2311 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
2312 | return false; /* still busy with another command */ | |
2313 | } | |
2314 | ||
2315 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
2316 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
2317 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
2318 | POSTING_READ16(MEMSWCTL); | |
2319 | ||
2320 | rgvswctl |= MEMCTL_CMD_STS; | |
2321 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
2322 | ||
2323 | return true; | |
2324 | } | |
2325 | ||
8090c6b9 | 2326 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
2327 | { |
2328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2329 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
2330 | u8 fmax, fmin, fstart, vstart; | |
2331 | ||
9270388e DV |
2332 | spin_lock_irq(&mchdev_lock); |
2333 | ||
2b4e57bd ED |
2334 | /* Enable temp reporting */ |
2335 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
2336 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
2337 | ||
2338 | /* 100ms RC evaluation intervals */ | |
2339 | I915_WRITE(RCUPEI, 100000); | |
2340 | I915_WRITE(RCDNEI, 100000); | |
2341 | ||
2342 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
2343 | I915_WRITE(RCBMAXAVG, 90000); | |
2344 | I915_WRITE(RCBMINAVG, 80000); | |
2345 | ||
2346 | I915_WRITE(MEMIHYST, 1); | |
2347 | ||
2348 | /* Set up min, max, and cur for interrupt handling */ | |
2349 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
2350 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
2351 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
2352 | MEMMODE_FSTART_SHIFT; | |
2353 | ||
2354 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
2355 | PXVFREQ_PX_SHIFT; | |
2356 | ||
20e4d407 DV |
2357 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
2358 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 2359 | |
20e4d407 DV |
2360 | dev_priv->ips.max_delay = fstart; |
2361 | dev_priv->ips.min_delay = fmin; | |
2362 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
2363 | |
2364 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
2365 | fmax, fmin, fstart); | |
2366 | ||
2367 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
2368 | ||
2369 | /* | |
2370 | * Interrupts will be enabled in ironlake_irq_postinstall | |
2371 | */ | |
2372 | ||
2373 | I915_WRITE(VIDSTART, vstart); | |
2374 | POSTING_READ(VIDSTART); | |
2375 | ||
2376 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
2377 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
2378 | ||
9270388e | 2379 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 2380 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 2381 | mdelay(1); |
2b4e57bd ED |
2382 | |
2383 | ironlake_set_drps(dev, fstart); | |
2384 | ||
20e4d407 | 2385 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 2386 | I915_READ(0x112e0); |
20e4d407 DV |
2387 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
2388 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
2389 | getrawmonotonic(&dev_priv->ips.last_time2); | |
9270388e DV |
2390 | |
2391 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
2392 | } |
2393 | ||
8090c6b9 | 2394 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
2395 | { |
2396 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
2397 | u16 rgvswctl; |
2398 | ||
2399 | spin_lock_irq(&mchdev_lock); | |
2400 | ||
2401 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
2402 | |
2403 | /* Ack interrupts, disable EFC interrupt */ | |
2404 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
2405 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
2406 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
2407 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
2408 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
2409 | ||
2410 | /* Go back to the starting frequency */ | |
20e4d407 | 2411 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 2412 | mdelay(1); |
2b4e57bd ED |
2413 | rgvswctl |= MEMCTL_CMD_STS; |
2414 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 2415 | mdelay(1); |
2b4e57bd | 2416 | |
9270388e | 2417 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
2418 | } |
2419 | ||
acbe9475 DV |
2420 | /* There's a funny hw issue where the hw returns all 0 when reading from |
2421 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
2422 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
2423 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
2424 | */ | |
65bccb5c | 2425 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) |
2b4e57bd | 2426 | { |
7b9e0ae6 | 2427 | u32 limits; |
2b4e57bd | 2428 | |
7b9e0ae6 | 2429 | limits = 0; |
c6a828d3 DV |
2430 | |
2431 | if (*val >= dev_priv->rps.max_delay) | |
2432 | *val = dev_priv->rps.max_delay; | |
2433 | limits |= dev_priv->rps.max_delay << 24; | |
20b46e59 DV |
2434 | |
2435 | /* Only set the down limit when we've reached the lowest level to avoid | |
2436 | * getting more interrupts, otherwise leave this clear. This prevents a | |
2437 | * race in the hw when coming out of rc6: There's a tiny window where | |
2438 | * the hw runs at the minimal clock before selecting the desired | |
2439 | * frequency, if the down threshold expires in that window we will not | |
2440 | * receive a down interrupt. */ | |
c6a828d3 DV |
2441 | if (*val <= dev_priv->rps.min_delay) { |
2442 | *val = dev_priv->rps.min_delay; | |
2443 | limits |= dev_priv->rps.min_delay << 16; | |
20b46e59 DV |
2444 | } |
2445 | ||
2446 | return limits; | |
2447 | } | |
2448 | ||
2449 | void gen6_set_rps(struct drm_device *dev, u8 val) | |
2450 | { | |
2451 | struct drm_i915_private *dev_priv = dev->dev_private; | |
65bccb5c | 2452 | u32 limits = gen6_rps_limits(dev_priv, &val); |
7b9e0ae6 | 2453 | |
4fc688ce | 2454 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79249636 BW |
2455 | WARN_ON(val > dev_priv->rps.max_delay); |
2456 | WARN_ON(val < dev_priv->rps.min_delay); | |
004777cb | 2457 | |
c6a828d3 | 2458 | if (val == dev_priv->rps.cur_delay) |
7b9e0ae6 CW |
2459 | return; |
2460 | ||
92bd1bf0 RV |
2461 | if (IS_HASWELL(dev)) |
2462 | I915_WRITE(GEN6_RPNSWREQ, | |
2463 | HSW_FREQUENCY(val)); | |
2464 | else | |
2465 | I915_WRITE(GEN6_RPNSWREQ, | |
2466 | GEN6_FREQUENCY(val) | | |
2467 | GEN6_OFFSET(0) | | |
2468 | GEN6_AGGRESSIVE_TURBO); | |
7b9e0ae6 CW |
2469 | |
2470 | /* Make sure we continue to get interrupts | |
2471 | * until we hit the minimum or maximum frequencies. | |
2472 | */ | |
2473 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); | |
2474 | ||
d5570a72 BW |
2475 | POSTING_READ(GEN6_RPNSWREQ); |
2476 | ||
c6a828d3 | 2477 | dev_priv->rps.cur_delay = val; |
be2cde9a DV |
2478 | |
2479 | trace_intel_gpu_freq_change(val * 50); | |
2b4e57bd ED |
2480 | } |
2481 | ||
0a073b84 JB |
2482 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
2483 | { | |
2484 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2485 | unsigned long timeout = jiffies + msecs_to_jiffies(10); | |
2486 | u32 limits = gen6_rps_limits(dev_priv, &val); | |
2487 | u32 pval; | |
2488 | ||
2489 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
2490 | WARN_ON(val > dev_priv->rps.max_delay); | |
2491 | WARN_ON(val < dev_priv->rps.min_delay); | |
2492 | ||
2493 | DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n", | |
2494 | vlv_gpu_freq(dev_priv->mem_freq, | |
2495 | dev_priv->rps.cur_delay), | |
2496 | vlv_gpu_freq(dev_priv->mem_freq, val)); | |
2497 | ||
2498 | if (val == dev_priv->rps.cur_delay) | |
2499 | return; | |
2500 | ||
2501 | valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); | |
2502 | ||
2503 | do { | |
2504 | valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval); | |
2505 | if (time_after(jiffies, timeout)) { | |
2506 | DRM_DEBUG_DRIVER("timed out waiting for Punit\n"); | |
2507 | break; | |
2508 | } | |
2509 | udelay(10); | |
2510 | } while (pval & 1); | |
2511 | ||
2512 | valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval); | |
2513 | if ((pval >> 8) != val) | |
2514 | DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n", | |
2515 | val, pval >> 8); | |
2516 | ||
2517 | /* Make sure we continue to get interrupts | |
2518 | * until we hit the minimum or maximum frequencies. | |
2519 | */ | |
2520 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); | |
2521 | ||
2522 | dev_priv->rps.cur_delay = pval >> 8; | |
2523 | ||
2524 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); | |
2525 | } | |
2526 | ||
2527 | ||
8090c6b9 | 2528 | static void gen6_disable_rps(struct drm_device *dev) |
2b4e57bd ED |
2529 | { |
2530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2531 | ||
88509484 | 2532 | I915_WRITE(GEN6_RC_CONTROL, 0); |
2b4e57bd ED |
2533 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2534 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
2535 | I915_WRITE(GEN6_PMIER, 0); | |
2536 | /* Complete PM interrupt masking here doesn't race with the rps work | |
2537 | * item again unmasking PM interrupts because that is using a different | |
2538 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
2539 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
2540 | ||
c6a828d3 DV |
2541 | spin_lock_irq(&dev_priv->rps.lock); |
2542 | dev_priv->rps.pm_iir = 0; | |
2543 | spin_unlock_irq(&dev_priv->rps.lock); | |
2b4e57bd ED |
2544 | |
2545 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); | |
2546 | } | |
2547 | ||
d20d4f0c JB |
2548 | static void valleyview_disable_rps(struct drm_device *dev) |
2549 | { | |
2550 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2551 | ||
2552 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
2553 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
2554 | I915_WRITE(GEN6_PMIER, 0); | |
2555 | /* Complete PM interrupt masking here doesn't race with the rps work | |
2556 | * item again unmasking PM interrupts because that is using a different | |
2557 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
2558 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
2559 | ||
2560 | spin_lock_irq(&dev_priv->rps.lock); | |
2561 | dev_priv->rps.pm_iir = 0; | |
2562 | spin_unlock_irq(&dev_priv->rps.lock); | |
2563 | ||
2564 | I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); | |
2565 | } | |
2566 | ||
2b4e57bd ED |
2567 | int intel_enable_rc6(const struct drm_device *dev) |
2568 | { | |
456470eb | 2569 | /* Respect the kernel parameter if it is set */ |
2b4e57bd ED |
2570 | if (i915_enable_rc6 >= 0) |
2571 | return i915_enable_rc6; | |
2572 | ||
6567d748 CW |
2573 | /* Disable RC6 on Ironlake */ |
2574 | if (INTEL_INFO(dev)->gen == 5) | |
2575 | return 0; | |
2b4e57bd | 2576 | |
456470eb DV |
2577 | if (IS_HASWELL(dev)) { |
2578 | DRM_DEBUG_DRIVER("Haswell: only RC6 available\n"); | |
4a637c2c | 2579 | return INTEL_RC6_ENABLE; |
456470eb | 2580 | } |
2b4e57bd | 2581 | |
456470eb | 2582 | /* snb/ivb have more than one rc6 state. */ |
2b4e57bd ED |
2583 | if (INTEL_INFO(dev)->gen == 6) { |
2584 | DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n"); | |
2585 | return INTEL_RC6_ENABLE; | |
2586 | } | |
456470eb | 2587 | |
2b4e57bd ED |
2588 | DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n"); |
2589 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); | |
2590 | } | |
2591 | ||
79f5b2c7 | 2592 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 2593 | { |
79f5b2c7 | 2594 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2595 | struct intel_ring_buffer *ring; |
7b9e0ae6 CW |
2596 | u32 rp_state_cap; |
2597 | u32 gt_perf_status; | |
31643d54 | 2598 | u32 rc6vids, pcu_mbox, rc6_mask = 0; |
2b4e57bd | 2599 | u32 gtfifodbg; |
2b4e57bd | 2600 | int rc6_mode; |
42c0526c | 2601 | int i, ret; |
2b4e57bd | 2602 | |
4fc688ce | 2603 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 2604 | |
2b4e57bd ED |
2605 | /* Here begins a magic sequence of register writes to enable |
2606 | * auto-downclocking. | |
2607 | * | |
2608 | * Perhaps there might be some value in exposing these to | |
2609 | * userspace... | |
2610 | */ | |
2611 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
2612 | |
2613 | /* Clear the DBG now so we don't confuse earlier errors */ | |
2614 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
2615 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
2616 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
2617 | } | |
2618 | ||
2619 | gen6_gt_force_wake_get(dev_priv); | |
2620 | ||
7b9e0ae6 CW |
2621 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
2622 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); | |
2623 | ||
31c77388 BW |
2624 | /* In units of 50MHz */ |
2625 | dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff; | |
c6a828d3 DV |
2626 | dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16; |
2627 | dev_priv->rps.cur_delay = 0; | |
7b9e0ae6 | 2628 | |
2b4e57bd ED |
2629 | /* disable the counters and set deterministic thresholds */ |
2630 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
2631 | ||
2632 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
2633 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
2634 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
2635 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
2636 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
2637 | ||
b4519513 CW |
2638 | for_each_ring(ring, dev_priv, i) |
2639 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
2640 | |
2641 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
2642 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
2643 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 2644 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
2645 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
2646 | ||
5a7dc92a | 2647 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
2648 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
2649 | if (rc6_mode & INTEL_RC6_ENABLE) | |
2650 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
2651 | ||
5a7dc92a ED |
2652 | /* We don't use those on Haswell */ |
2653 | if (!IS_HASWELL(dev)) { | |
2654 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
2655 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 2656 | |
5a7dc92a ED |
2657 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
2658 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
2659 | } | |
2b4e57bd ED |
2660 | |
2661 | DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", | |
5a7dc92a ED |
2662 | (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
2663 | (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
2664 | (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
2b4e57bd ED |
2665 | |
2666 | I915_WRITE(GEN6_RC_CONTROL, | |
2667 | rc6_mask | | |
2668 | GEN6_RC_CTL_EI_MODE(1) | | |
2669 | GEN6_RC_CTL_HW_ENABLE); | |
2670 | ||
92bd1bf0 RV |
2671 | if (IS_HASWELL(dev)) { |
2672 | I915_WRITE(GEN6_RPNSWREQ, | |
2673 | HSW_FREQUENCY(10)); | |
2674 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
2675 | HSW_FREQUENCY(12)); | |
2676 | } else { | |
2677 | I915_WRITE(GEN6_RPNSWREQ, | |
2678 | GEN6_FREQUENCY(10) | | |
2679 | GEN6_OFFSET(0) | | |
2680 | GEN6_AGGRESSIVE_TURBO); | |
2681 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
2682 | GEN6_FREQUENCY(12)); | |
2683 | } | |
2b4e57bd ED |
2684 | |
2685 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); | |
2686 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
c6a828d3 DV |
2687 | dev_priv->rps.max_delay << 24 | |
2688 | dev_priv->rps.min_delay << 16); | |
5a7dc92a | 2689 | |
1ee9ae32 DV |
2690 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
2691 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
2692 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
2693 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5a7dc92a | 2694 | |
2b4e57bd ED |
2695 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2696 | I915_WRITE(GEN6_RP_CONTROL, | |
2697 | GEN6_RP_MEDIA_TURBO | | |
89ba829e | 2698 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
2b4e57bd ED |
2699 | GEN6_RP_MEDIA_IS_GFX | |
2700 | GEN6_RP_ENABLE | | |
2701 | GEN6_RP_UP_BUSY_AVG | | |
5a7dc92a | 2702 | (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT)); |
2b4e57bd | 2703 | |
42c0526c | 2704 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
fec46b5e | 2705 | if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) { |
42c0526c BW |
2706 | pcu_mbox = 0; |
2707 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
a2b3fc01 | 2708 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
10e08497 | 2709 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
a2b3fc01 BW |
2710 | (dev_priv->rps.max_delay & 0xff) * 50, |
2711 | (pcu_mbox & 0xff) * 50); | |
31c77388 | 2712 | dev_priv->rps.hw_max = pcu_mbox & 0xff; |
42c0526c BW |
2713 | } |
2714 | } else { | |
2715 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); | |
2b4e57bd ED |
2716 | } |
2717 | ||
7b9e0ae6 | 2718 | gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8); |
2b4e57bd ED |
2719 | |
2720 | /* requires MSI enabled */ | |
ff928261 | 2721 | I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); |
c6a828d3 DV |
2722 | spin_lock_irq(&dev_priv->rps.lock); |
2723 | WARN_ON(dev_priv->rps.pm_iir != 0); | |
2b4e57bd | 2724 | I915_WRITE(GEN6_PMIMR, 0); |
c6a828d3 | 2725 | spin_unlock_irq(&dev_priv->rps.lock); |
2b4e57bd ED |
2726 | /* enable all PM interrupts */ |
2727 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
2728 | ||
31643d54 BW |
2729 | rc6vids = 0; |
2730 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
2731 | if (IS_GEN6(dev) && ret) { | |
2732 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
2733 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
2734 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
2735 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
2736 | rc6vids &= 0xffff00; | |
2737 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
2738 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
2739 | if (ret) | |
2740 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
2741 | } | |
2742 | ||
2b4e57bd | 2743 | gen6_gt_force_wake_put(dev_priv); |
2b4e57bd ED |
2744 | } |
2745 | ||
79f5b2c7 | 2746 | static void gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 2747 | { |
79f5b2c7 | 2748 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 2749 | int min_freq = 15; |
3ebecd07 CW |
2750 | unsigned int gpu_freq; |
2751 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd ED |
2752 | int scaling_factor = 180; |
2753 | ||
4fc688ce | 2754 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 2755 | |
2b4e57bd ED |
2756 | max_ia_freq = cpufreq_quick_get_max(0); |
2757 | /* | |
2758 | * Default to measured freq if none found, PCU will ensure we don't go | |
2759 | * over | |
2760 | */ | |
2761 | if (!max_ia_freq) | |
2762 | max_ia_freq = tsc_khz; | |
2763 | ||
2764 | /* Convert from kHz to MHz */ | |
2765 | max_ia_freq /= 1000; | |
2766 | ||
3ebecd07 CW |
2767 | min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK); |
2768 | /* convert DDR frequency from units of 133.3MHz to bandwidth */ | |
2769 | min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3; | |
2770 | ||
2b4e57bd ED |
2771 | /* |
2772 | * For each potential GPU frequency, load a ring frequency we'd like | |
2773 | * to use for memory access. We do this by specifying the IA frequency | |
2774 | * the PCU should use as a reference to determine the ring frequency. | |
2775 | */ | |
c6a828d3 | 2776 | for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay; |
2b4e57bd | 2777 | gpu_freq--) { |
c6a828d3 | 2778 | int diff = dev_priv->rps.max_delay - gpu_freq; |
3ebecd07 CW |
2779 | unsigned int ia_freq = 0, ring_freq = 0; |
2780 | ||
2781 | if (IS_HASWELL(dev)) { | |
2782 | ring_freq = (gpu_freq * 5 + 3) / 4; | |
2783 | ring_freq = max(min_ring_freq, ring_freq); | |
2784 | /* leave ia_freq as the default, chosen by cpufreq */ | |
2785 | } else { | |
2786 | /* On older processors, there is no separate ring | |
2787 | * clock domain, so in order to boost the bandwidth | |
2788 | * of the ring, we need to upclock the CPU (ia_freq). | |
2789 | * | |
2790 | * For GPU frequencies less than 750MHz, | |
2791 | * just use the lowest ring freq. | |
2792 | */ | |
2793 | if (gpu_freq < min_freq) | |
2794 | ia_freq = 800; | |
2795 | else | |
2796 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
2797 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
2798 | } | |
2b4e57bd | 2799 | |
42c0526c BW |
2800 | sandybridge_pcode_write(dev_priv, |
2801 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
2802 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
2803 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
2804 | gpu_freq); | |
2b4e57bd | 2805 | } |
2b4e57bd ED |
2806 | } |
2807 | ||
0a073b84 JB |
2808 | int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
2809 | { | |
2810 | u32 val, rp0; | |
2811 | ||
2812 | valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val); | |
2813 | ||
2814 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
2815 | /* Clamp to max */ | |
2816 | rp0 = min_t(u32, rp0, 0xea); | |
2817 | ||
2818 | return rp0; | |
2819 | } | |
2820 | ||
2821 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
2822 | { | |
2823 | u32 val, rpe; | |
2824 | ||
2825 | valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val); | |
2826 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; | |
2827 | valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val); | |
2828 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; | |
2829 | ||
2830 | return rpe; | |
2831 | } | |
2832 | ||
2833 | int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) | |
2834 | { | |
2835 | u32 val; | |
2836 | ||
2837 | valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val); | |
2838 | ||
2839 | return val & 0xff; | |
2840 | } | |
2841 | ||
52ceb908 JB |
2842 | static void vlv_rps_timer_work(struct work_struct *work) |
2843 | { | |
2844 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
2845 | rps.vlv_work.work); | |
2846 | ||
2847 | /* | |
2848 | * Timer fired, we must be idle. Drop to min voltage state. | |
2849 | * Note: we use RPe here since it should match the | |
2850 | * Vmin we were shooting for. That should give us better | |
2851 | * perf when we come back out of RC6 than if we used the | |
2852 | * min freq available. | |
2853 | */ | |
2854 | mutex_lock(&dev_priv->rps.hw_lock); | |
2855 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); | |
2856 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2857 | } | |
2858 | ||
0a073b84 JB |
2859 | static void valleyview_enable_rps(struct drm_device *dev) |
2860 | { | |
2861 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2862 | struct intel_ring_buffer *ring; | |
2863 | u32 gtfifodbg, val, rpe; | |
2864 | int i; | |
2865 | ||
2866 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
2867 | ||
2868 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
2869 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
2870 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
2871 | } | |
2872 | ||
2873 | gen6_gt_force_wake_get(dev_priv); | |
2874 | ||
2875 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
2876 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
2877 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
2878 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
2879 | ||
2880 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
2881 | ||
2882 | I915_WRITE(GEN6_RP_CONTROL, | |
2883 | GEN6_RP_MEDIA_TURBO | | |
2884 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
2885 | GEN6_RP_MEDIA_IS_GFX | | |
2886 | GEN6_RP_ENABLE | | |
2887 | GEN6_RP_UP_BUSY_AVG | | |
2888 | GEN6_RP_DOWN_IDLE_CONT); | |
2889 | ||
2890 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
2891 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
2892 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
2893 | ||
2894 | for_each_ring(ring, dev_priv, i) | |
2895 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2896 | ||
2897 | I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350); | |
2898 | ||
2899 | /* allows RC6 residency counter to work */ | |
2900 | I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3)); | |
2901 | I915_WRITE(GEN6_RC_CONTROL, | |
2902 | GEN7_RC_CTL_TO_MODE); | |
2903 | ||
2904 | valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val); | |
2445966e JB |
2905 | switch ((val >> 6) & 3) { |
2906 | case 0: | |
2907 | case 1: | |
2908 | dev_priv->mem_freq = 800; | |
2909 | break; | |
2910 | case 2: | |
2911 | dev_priv->mem_freq = 1066; | |
2912 | break; | |
2913 | case 3: | |
2914 | dev_priv->mem_freq = 1333; | |
2915 | break; | |
2916 | } | |
0a073b84 JB |
2917 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); |
2918 | ||
2919 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
2920 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
2921 | ||
2922 | DRM_DEBUG_DRIVER("current GPU freq: %d\n", | |
2923 | vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff)); | |
2924 | dev_priv->rps.cur_delay = (val >> 8) & 0xff; | |
2925 | ||
2926 | dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); | |
2927 | dev_priv->rps.hw_max = dev_priv->rps.max_delay; | |
2928 | DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq, | |
2929 | dev_priv->rps.max_delay)); | |
2930 | ||
2931 | rpe = valleyview_rps_rpe_freq(dev_priv); | |
2932 | DRM_DEBUG_DRIVER("RPe GPU freq: %d\n", | |
2933 | vlv_gpu_freq(dev_priv->mem_freq, rpe)); | |
52ceb908 | 2934 | dev_priv->rps.rpe_delay = rpe; |
0a073b84 JB |
2935 | |
2936 | val = valleyview_rps_min_freq(dev_priv); | |
2937 | DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq, | |
2938 | val)); | |
2939 | dev_priv->rps.min_delay = val; | |
2940 | ||
2941 | DRM_DEBUG_DRIVER("setting GPU freq to %d\n", | |
2942 | vlv_gpu_freq(dev_priv->mem_freq, rpe)); | |
2943 | ||
52ceb908 JB |
2944 | INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work); |
2945 | ||
0a073b84 JB |
2946 | valleyview_set_rps(dev_priv->dev, rpe); |
2947 | ||
2948 | /* requires MSI enabled */ | |
2949 | I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS); | |
2950 | spin_lock_irq(&dev_priv->rps.lock); | |
2951 | WARN_ON(dev_priv->rps.pm_iir != 0); | |
2952 | I915_WRITE(GEN6_PMIMR, 0); | |
2953 | spin_unlock_irq(&dev_priv->rps.lock); | |
2954 | /* enable all PM interrupts */ | |
2955 | I915_WRITE(GEN6_PMINTRMSK, 0); | |
2956 | ||
2957 | gen6_gt_force_wake_put(dev_priv); | |
2958 | } | |
2959 | ||
930ebb46 | 2960 | void ironlake_teardown_rc6(struct drm_device *dev) |
2b4e57bd ED |
2961 | { |
2962 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2963 | ||
3e373948 DV |
2964 | if (dev_priv->ips.renderctx) { |
2965 | i915_gem_object_unpin(dev_priv->ips.renderctx); | |
2966 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); | |
2967 | dev_priv->ips.renderctx = NULL; | |
2b4e57bd ED |
2968 | } |
2969 | ||
3e373948 DV |
2970 | if (dev_priv->ips.pwrctx) { |
2971 | i915_gem_object_unpin(dev_priv->ips.pwrctx); | |
2972 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); | |
2973 | dev_priv->ips.pwrctx = NULL; | |
2b4e57bd ED |
2974 | } |
2975 | } | |
2976 | ||
930ebb46 | 2977 | static void ironlake_disable_rc6(struct drm_device *dev) |
2b4e57bd ED |
2978 | { |
2979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2980 | ||
2981 | if (I915_READ(PWRCTXA)) { | |
2982 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
2983 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
2984 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
2985 | 50); | |
2986 | ||
2987 | I915_WRITE(PWRCTXA, 0); | |
2988 | POSTING_READ(PWRCTXA); | |
2989 | ||
2990 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
2991 | POSTING_READ(RSTDBYCTL); | |
2992 | } | |
2b4e57bd ED |
2993 | } |
2994 | ||
2995 | static int ironlake_setup_rc6(struct drm_device *dev) | |
2996 | { | |
2997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2998 | ||
3e373948 DV |
2999 | if (dev_priv->ips.renderctx == NULL) |
3000 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); | |
3001 | if (!dev_priv->ips.renderctx) | |
2b4e57bd ED |
3002 | return -ENOMEM; |
3003 | ||
3e373948 DV |
3004 | if (dev_priv->ips.pwrctx == NULL) |
3005 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); | |
3006 | if (!dev_priv->ips.pwrctx) { | |
2b4e57bd ED |
3007 | ironlake_teardown_rc6(dev); |
3008 | return -ENOMEM; | |
3009 | } | |
3010 | ||
3011 | return 0; | |
3012 | } | |
3013 | ||
930ebb46 | 3014 | static void ironlake_enable_rc6(struct drm_device *dev) |
2b4e57bd ED |
3015 | { |
3016 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6d90c952 | 3017 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
3e960501 | 3018 | bool was_interruptible; |
2b4e57bd ED |
3019 | int ret; |
3020 | ||
3021 | /* rc6 disabled by default due to repeated reports of hanging during | |
3022 | * boot and resume. | |
3023 | */ | |
3024 | if (!intel_enable_rc6(dev)) | |
3025 | return; | |
3026 | ||
79f5b2c7 DV |
3027 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
3028 | ||
2b4e57bd | 3029 | ret = ironlake_setup_rc6(dev); |
79f5b2c7 | 3030 | if (ret) |
2b4e57bd | 3031 | return; |
2b4e57bd | 3032 | |
3e960501 CW |
3033 | was_interruptible = dev_priv->mm.interruptible; |
3034 | dev_priv->mm.interruptible = false; | |
3035 | ||
2b4e57bd ED |
3036 | /* |
3037 | * GPU can automatically power down the render unit if given a page | |
3038 | * to save state. | |
3039 | */ | |
6d90c952 | 3040 | ret = intel_ring_begin(ring, 6); |
2b4e57bd ED |
3041 | if (ret) { |
3042 | ironlake_teardown_rc6(dev); | |
3e960501 | 3043 | dev_priv->mm.interruptible = was_interruptible; |
2b4e57bd ED |
3044 | return; |
3045 | } | |
3046 | ||
6d90c952 DV |
3047 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
3048 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
3e373948 | 3049 | intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | |
6d90c952 DV |
3050 | MI_MM_SPACE_GTT | |
3051 | MI_SAVE_EXT_STATE_EN | | |
3052 | MI_RESTORE_EXT_STATE_EN | | |
3053 | MI_RESTORE_INHIBIT); | |
3054 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); | |
3055 | intel_ring_emit(ring, MI_NOOP); | |
3056 | intel_ring_emit(ring, MI_FLUSH); | |
3057 | intel_ring_advance(ring); | |
2b4e57bd ED |
3058 | |
3059 | /* | |
3060 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
3061 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
3062 | * safe to assume that renderctx is valid | |
3063 | */ | |
3e960501 CW |
3064 | ret = intel_ring_idle(ring); |
3065 | dev_priv->mm.interruptible = was_interruptible; | |
2b4e57bd | 3066 | if (ret) { |
def27a58 | 3067 | DRM_ERROR("failed to enable ironlake power savings\n"); |
2b4e57bd | 3068 | ironlake_teardown_rc6(dev); |
2b4e57bd ED |
3069 | return; |
3070 | } | |
3071 | ||
3e373948 | 3072 | I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); |
2b4e57bd | 3073 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
2b4e57bd ED |
3074 | } |
3075 | ||
dde18883 ED |
3076 | static unsigned long intel_pxfreq(u32 vidfreq) |
3077 | { | |
3078 | unsigned long freq; | |
3079 | int div = (vidfreq & 0x3f0000) >> 16; | |
3080 | int post = (vidfreq & 0x3000) >> 12; | |
3081 | int pre = (vidfreq & 0x7); | |
3082 | ||
3083 | if (!pre) | |
3084 | return 0; | |
3085 | ||
3086 | freq = ((div * 133333) / ((1<<post) * pre)); | |
3087 | ||
3088 | return freq; | |
3089 | } | |
3090 | ||
eb48eb00 DV |
3091 | static const struct cparams { |
3092 | u16 i; | |
3093 | u16 t; | |
3094 | u16 m; | |
3095 | u16 c; | |
3096 | } cparams[] = { | |
3097 | { 1, 1333, 301, 28664 }, | |
3098 | { 1, 1066, 294, 24460 }, | |
3099 | { 1, 800, 294, 25192 }, | |
3100 | { 0, 1333, 276, 27605 }, | |
3101 | { 0, 1066, 276, 27605 }, | |
3102 | { 0, 800, 231, 23784 }, | |
3103 | }; | |
3104 | ||
f531dcb2 | 3105 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
3106 | { |
3107 | u64 total_count, diff, ret; | |
3108 | u32 count1, count2, count3, m = 0, c = 0; | |
3109 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
3110 | int i; | |
3111 | ||
02d71956 DV |
3112 | assert_spin_locked(&mchdev_lock); |
3113 | ||
20e4d407 | 3114 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
3115 | |
3116 | /* Prevent division-by-zero if we are asking too fast. | |
3117 | * Also, we don't get interesting results if we are polling | |
3118 | * faster than once in 10ms, so just return the saved value | |
3119 | * in such cases. | |
3120 | */ | |
3121 | if (diff1 <= 10) | |
20e4d407 | 3122 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
3123 | |
3124 | count1 = I915_READ(DMIEC); | |
3125 | count2 = I915_READ(DDREC); | |
3126 | count3 = I915_READ(CSIEC); | |
3127 | ||
3128 | total_count = count1 + count2 + count3; | |
3129 | ||
3130 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
3131 | if (total_count < dev_priv->ips.last_count1) { |
3132 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
3133 | diff += total_count; |
3134 | } else { | |
20e4d407 | 3135 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
3136 | } |
3137 | ||
3138 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
3139 | if (cparams[i].i == dev_priv->ips.c_m && |
3140 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
3141 | m = cparams[i].m; |
3142 | c = cparams[i].c; | |
3143 | break; | |
3144 | } | |
3145 | } | |
3146 | ||
3147 | diff = div_u64(diff, diff1); | |
3148 | ret = ((m * diff) + c); | |
3149 | ret = div_u64(ret, 10); | |
3150 | ||
20e4d407 DV |
3151 | dev_priv->ips.last_count1 = total_count; |
3152 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 3153 | |
20e4d407 | 3154 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
3155 | |
3156 | return ret; | |
3157 | } | |
3158 | ||
f531dcb2 CW |
3159 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
3160 | { | |
3161 | unsigned long val; | |
3162 | ||
3163 | if (dev_priv->info->gen != 5) | |
3164 | return 0; | |
3165 | ||
3166 | spin_lock_irq(&mchdev_lock); | |
3167 | ||
3168 | val = __i915_chipset_val(dev_priv); | |
3169 | ||
3170 | spin_unlock_irq(&mchdev_lock); | |
3171 | ||
3172 | return val; | |
3173 | } | |
3174 | ||
eb48eb00 DV |
3175 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
3176 | { | |
3177 | unsigned long m, x, b; | |
3178 | u32 tsfs; | |
3179 | ||
3180 | tsfs = I915_READ(TSFS); | |
3181 | ||
3182 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
3183 | x = I915_READ8(TR1); | |
3184 | ||
3185 | b = tsfs & TSFS_INTR_MASK; | |
3186 | ||
3187 | return ((m * x) / 127) - b; | |
3188 | } | |
3189 | ||
3190 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
3191 | { | |
3192 | static const struct v_table { | |
3193 | u16 vd; /* in .1 mil */ | |
3194 | u16 vm; /* in .1 mil */ | |
3195 | } v_table[] = { | |
3196 | { 0, 0, }, | |
3197 | { 375, 0, }, | |
3198 | { 500, 0, }, | |
3199 | { 625, 0, }, | |
3200 | { 750, 0, }, | |
3201 | { 875, 0, }, | |
3202 | { 1000, 0, }, | |
3203 | { 1125, 0, }, | |
3204 | { 4125, 3000, }, | |
3205 | { 4125, 3000, }, | |
3206 | { 4125, 3000, }, | |
3207 | { 4125, 3000, }, | |
3208 | { 4125, 3000, }, | |
3209 | { 4125, 3000, }, | |
3210 | { 4125, 3000, }, | |
3211 | { 4125, 3000, }, | |
3212 | { 4125, 3000, }, | |
3213 | { 4125, 3000, }, | |
3214 | { 4125, 3000, }, | |
3215 | { 4125, 3000, }, | |
3216 | { 4125, 3000, }, | |
3217 | { 4125, 3000, }, | |
3218 | { 4125, 3000, }, | |
3219 | { 4125, 3000, }, | |
3220 | { 4125, 3000, }, | |
3221 | { 4125, 3000, }, | |
3222 | { 4125, 3000, }, | |
3223 | { 4125, 3000, }, | |
3224 | { 4125, 3000, }, | |
3225 | { 4125, 3000, }, | |
3226 | { 4125, 3000, }, | |
3227 | { 4125, 3000, }, | |
3228 | { 4250, 3125, }, | |
3229 | { 4375, 3250, }, | |
3230 | { 4500, 3375, }, | |
3231 | { 4625, 3500, }, | |
3232 | { 4750, 3625, }, | |
3233 | { 4875, 3750, }, | |
3234 | { 5000, 3875, }, | |
3235 | { 5125, 4000, }, | |
3236 | { 5250, 4125, }, | |
3237 | { 5375, 4250, }, | |
3238 | { 5500, 4375, }, | |
3239 | { 5625, 4500, }, | |
3240 | { 5750, 4625, }, | |
3241 | { 5875, 4750, }, | |
3242 | { 6000, 4875, }, | |
3243 | { 6125, 5000, }, | |
3244 | { 6250, 5125, }, | |
3245 | { 6375, 5250, }, | |
3246 | { 6500, 5375, }, | |
3247 | { 6625, 5500, }, | |
3248 | { 6750, 5625, }, | |
3249 | { 6875, 5750, }, | |
3250 | { 7000, 5875, }, | |
3251 | { 7125, 6000, }, | |
3252 | { 7250, 6125, }, | |
3253 | { 7375, 6250, }, | |
3254 | { 7500, 6375, }, | |
3255 | { 7625, 6500, }, | |
3256 | { 7750, 6625, }, | |
3257 | { 7875, 6750, }, | |
3258 | { 8000, 6875, }, | |
3259 | { 8125, 7000, }, | |
3260 | { 8250, 7125, }, | |
3261 | { 8375, 7250, }, | |
3262 | { 8500, 7375, }, | |
3263 | { 8625, 7500, }, | |
3264 | { 8750, 7625, }, | |
3265 | { 8875, 7750, }, | |
3266 | { 9000, 7875, }, | |
3267 | { 9125, 8000, }, | |
3268 | { 9250, 8125, }, | |
3269 | { 9375, 8250, }, | |
3270 | { 9500, 8375, }, | |
3271 | { 9625, 8500, }, | |
3272 | { 9750, 8625, }, | |
3273 | { 9875, 8750, }, | |
3274 | { 10000, 8875, }, | |
3275 | { 10125, 9000, }, | |
3276 | { 10250, 9125, }, | |
3277 | { 10375, 9250, }, | |
3278 | { 10500, 9375, }, | |
3279 | { 10625, 9500, }, | |
3280 | { 10750, 9625, }, | |
3281 | { 10875, 9750, }, | |
3282 | { 11000, 9875, }, | |
3283 | { 11125, 10000, }, | |
3284 | { 11250, 10125, }, | |
3285 | { 11375, 10250, }, | |
3286 | { 11500, 10375, }, | |
3287 | { 11625, 10500, }, | |
3288 | { 11750, 10625, }, | |
3289 | { 11875, 10750, }, | |
3290 | { 12000, 10875, }, | |
3291 | { 12125, 11000, }, | |
3292 | { 12250, 11125, }, | |
3293 | { 12375, 11250, }, | |
3294 | { 12500, 11375, }, | |
3295 | { 12625, 11500, }, | |
3296 | { 12750, 11625, }, | |
3297 | { 12875, 11750, }, | |
3298 | { 13000, 11875, }, | |
3299 | { 13125, 12000, }, | |
3300 | { 13250, 12125, }, | |
3301 | { 13375, 12250, }, | |
3302 | { 13500, 12375, }, | |
3303 | { 13625, 12500, }, | |
3304 | { 13750, 12625, }, | |
3305 | { 13875, 12750, }, | |
3306 | { 14000, 12875, }, | |
3307 | { 14125, 13000, }, | |
3308 | { 14250, 13125, }, | |
3309 | { 14375, 13250, }, | |
3310 | { 14500, 13375, }, | |
3311 | { 14625, 13500, }, | |
3312 | { 14750, 13625, }, | |
3313 | { 14875, 13750, }, | |
3314 | { 15000, 13875, }, | |
3315 | { 15125, 14000, }, | |
3316 | { 15250, 14125, }, | |
3317 | { 15375, 14250, }, | |
3318 | { 15500, 14375, }, | |
3319 | { 15625, 14500, }, | |
3320 | { 15750, 14625, }, | |
3321 | { 15875, 14750, }, | |
3322 | { 16000, 14875, }, | |
3323 | { 16125, 15000, }, | |
3324 | }; | |
3325 | if (dev_priv->info->is_mobile) | |
3326 | return v_table[pxvid].vm; | |
3327 | else | |
3328 | return v_table[pxvid].vd; | |
3329 | } | |
3330 | ||
02d71956 | 3331 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
3332 | { |
3333 | struct timespec now, diff1; | |
3334 | u64 diff; | |
3335 | unsigned long diffms; | |
3336 | u32 count; | |
3337 | ||
02d71956 | 3338 | assert_spin_locked(&mchdev_lock); |
eb48eb00 DV |
3339 | |
3340 | getrawmonotonic(&now); | |
20e4d407 | 3341 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
eb48eb00 DV |
3342 | |
3343 | /* Don't divide by 0 */ | |
3344 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; | |
3345 | if (!diffms) | |
3346 | return; | |
3347 | ||
3348 | count = I915_READ(GFXEC); | |
3349 | ||
20e4d407 DV |
3350 | if (count < dev_priv->ips.last_count2) { |
3351 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
3352 | diff += count; |
3353 | } else { | |
20e4d407 | 3354 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
3355 | } |
3356 | ||
20e4d407 DV |
3357 | dev_priv->ips.last_count2 = count; |
3358 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
3359 | |
3360 | /* More magic constants... */ | |
3361 | diff = diff * 1181; | |
3362 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 3363 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
3364 | } |
3365 | ||
02d71956 DV |
3366 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
3367 | { | |
3368 | if (dev_priv->info->gen != 5) | |
3369 | return; | |
3370 | ||
9270388e | 3371 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
3372 | |
3373 | __i915_update_gfx_val(dev_priv); | |
3374 | ||
9270388e | 3375 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
3376 | } |
3377 | ||
f531dcb2 | 3378 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
3379 | { |
3380 | unsigned long t, corr, state1, corr2, state2; | |
3381 | u32 pxvid, ext_v; | |
3382 | ||
02d71956 DV |
3383 | assert_spin_locked(&mchdev_lock); |
3384 | ||
c6a828d3 | 3385 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4)); |
eb48eb00 DV |
3386 | pxvid = (pxvid >> 24) & 0x7f; |
3387 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
3388 | ||
3389 | state1 = ext_v; | |
3390 | ||
3391 | t = i915_mch_val(dev_priv); | |
3392 | ||
3393 | /* Revel in the empirically derived constants */ | |
3394 | ||
3395 | /* Correction factor in 1/100000 units */ | |
3396 | if (t > 80) | |
3397 | corr = ((t * 2349) + 135940); | |
3398 | else if (t >= 50) | |
3399 | corr = ((t * 964) + 29317); | |
3400 | else /* < 50 */ | |
3401 | corr = ((t * 301) + 1004); | |
3402 | ||
3403 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
3404 | corr /= 100000; | |
20e4d407 | 3405 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
3406 | |
3407 | state2 = (corr2 * state1) / 10000; | |
3408 | state2 /= 100; /* convert to mW */ | |
3409 | ||
02d71956 | 3410 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 3411 | |
20e4d407 | 3412 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
3413 | } |
3414 | ||
f531dcb2 CW |
3415 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
3416 | { | |
3417 | unsigned long val; | |
3418 | ||
3419 | if (dev_priv->info->gen != 5) | |
3420 | return 0; | |
3421 | ||
3422 | spin_lock_irq(&mchdev_lock); | |
3423 | ||
3424 | val = __i915_gfx_val(dev_priv); | |
3425 | ||
3426 | spin_unlock_irq(&mchdev_lock); | |
3427 | ||
3428 | return val; | |
3429 | } | |
3430 | ||
eb48eb00 DV |
3431 | /** |
3432 | * i915_read_mch_val - return value for IPS use | |
3433 | * | |
3434 | * Calculate and return a value for the IPS driver to use when deciding whether | |
3435 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
3436 | */ | |
3437 | unsigned long i915_read_mch_val(void) | |
3438 | { | |
3439 | struct drm_i915_private *dev_priv; | |
3440 | unsigned long chipset_val, graphics_val, ret = 0; | |
3441 | ||
9270388e | 3442 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
3443 | if (!i915_mch_dev) |
3444 | goto out_unlock; | |
3445 | dev_priv = i915_mch_dev; | |
3446 | ||
f531dcb2 CW |
3447 | chipset_val = __i915_chipset_val(dev_priv); |
3448 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
3449 | |
3450 | ret = chipset_val + graphics_val; | |
3451 | ||
3452 | out_unlock: | |
9270388e | 3453 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
3454 | |
3455 | return ret; | |
3456 | } | |
3457 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
3458 | ||
3459 | /** | |
3460 | * i915_gpu_raise - raise GPU frequency limit | |
3461 | * | |
3462 | * Raise the limit; IPS indicates we have thermal headroom. | |
3463 | */ | |
3464 | bool i915_gpu_raise(void) | |
3465 | { | |
3466 | struct drm_i915_private *dev_priv; | |
3467 | bool ret = true; | |
3468 | ||
9270388e | 3469 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
3470 | if (!i915_mch_dev) { |
3471 | ret = false; | |
3472 | goto out_unlock; | |
3473 | } | |
3474 | dev_priv = i915_mch_dev; | |
3475 | ||
20e4d407 DV |
3476 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
3477 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
3478 | |
3479 | out_unlock: | |
9270388e | 3480 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
3481 | |
3482 | return ret; | |
3483 | } | |
3484 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
3485 | ||
3486 | /** | |
3487 | * i915_gpu_lower - lower GPU frequency limit | |
3488 | * | |
3489 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
3490 | * frequency maximum. | |
3491 | */ | |
3492 | bool i915_gpu_lower(void) | |
3493 | { | |
3494 | struct drm_i915_private *dev_priv; | |
3495 | bool ret = true; | |
3496 | ||
9270388e | 3497 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
3498 | if (!i915_mch_dev) { |
3499 | ret = false; | |
3500 | goto out_unlock; | |
3501 | } | |
3502 | dev_priv = i915_mch_dev; | |
3503 | ||
20e4d407 DV |
3504 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
3505 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
3506 | |
3507 | out_unlock: | |
9270388e | 3508 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
3509 | |
3510 | return ret; | |
3511 | } | |
3512 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
3513 | ||
3514 | /** | |
3515 | * i915_gpu_busy - indicate GPU business to IPS | |
3516 | * | |
3517 | * Tell the IPS driver whether or not the GPU is busy. | |
3518 | */ | |
3519 | bool i915_gpu_busy(void) | |
3520 | { | |
3521 | struct drm_i915_private *dev_priv; | |
f047e395 | 3522 | struct intel_ring_buffer *ring; |
eb48eb00 | 3523 | bool ret = false; |
f047e395 | 3524 | int i; |
eb48eb00 | 3525 | |
9270388e | 3526 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
3527 | if (!i915_mch_dev) |
3528 | goto out_unlock; | |
3529 | dev_priv = i915_mch_dev; | |
3530 | ||
f047e395 CW |
3531 | for_each_ring(ring, dev_priv, i) |
3532 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
3533 | |
3534 | out_unlock: | |
9270388e | 3535 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
3536 | |
3537 | return ret; | |
3538 | } | |
3539 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
3540 | ||
3541 | /** | |
3542 | * i915_gpu_turbo_disable - disable graphics turbo | |
3543 | * | |
3544 | * Disable graphics turbo by resetting the max frequency and setting the | |
3545 | * current frequency to the default. | |
3546 | */ | |
3547 | bool i915_gpu_turbo_disable(void) | |
3548 | { | |
3549 | struct drm_i915_private *dev_priv; | |
3550 | bool ret = true; | |
3551 | ||
9270388e | 3552 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
3553 | if (!i915_mch_dev) { |
3554 | ret = false; | |
3555 | goto out_unlock; | |
3556 | } | |
3557 | dev_priv = i915_mch_dev; | |
3558 | ||
20e4d407 | 3559 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 3560 | |
20e4d407 | 3561 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
3562 | ret = false; |
3563 | ||
3564 | out_unlock: | |
9270388e | 3565 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
3566 | |
3567 | return ret; | |
3568 | } | |
3569 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
3570 | ||
3571 | /** | |
3572 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
3573 | * IPS got loaded first. | |
3574 | * | |
3575 | * This awkward dance is so that neither module has to depend on the | |
3576 | * other in order for IPS to do the appropriate communication of | |
3577 | * GPU turbo limits to i915. | |
3578 | */ | |
3579 | static void | |
3580 | ips_ping_for_i915_load(void) | |
3581 | { | |
3582 | void (*link)(void); | |
3583 | ||
3584 | link = symbol_get(ips_link_to_i915_driver); | |
3585 | if (link) { | |
3586 | link(); | |
3587 | symbol_put(ips_link_to_i915_driver); | |
3588 | } | |
3589 | } | |
3590 | ||
3591 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
3592 | { | |
02d71956 DV |
3593 | /* We only register the i915 ips part with intel-ips once everything is |
3594 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 3595 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 3596 | i915_mch_dev = dev_priv; |
9270388e | 3597 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
3598 | |
3599 | ips_ping_for_i915_load(); | |
3600 | } | |
3601 | ||
3602 | void intel_gpu_ips_teardown(void) | |
3603 | { | |
9270388e | 3604 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 3605 | i915_mch_dev = NULL; |
9270388e | 3606 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 3607 | } |
8090c6b9 | 3608 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
3609 | { |
3610 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3611 | u32 lcfuse; | |
3612 | u8 pxw[16]; | |
3613 | int i; | |
3614 | ||
3615 | /* Disable to program */ | |
3616 | I915_WRITE(ECR, 0); | |
3617 | POSTING_READ(ECR); | |
3618 | ||
3619 | /* Program energy weights for various events */ | |
3620 | I915_WRITE(SDEW, 0x15040d00); | |
3621 | I915_WRITE(CSIEW0, 0x007f0000); | |
3622 | I915_WRITE(CSIEW1, 0x1e220004); | |
3623 | I915_WRITE(CSIEW2, 0x04000004); | |
3624 | ||
3625 | for (i = 0; i < 5; i++) | |
3626 | I915_WRITE(PEW + (i * 4), 0); | |
3627 | for (i = 0; i < 3; i++) | |
3628 | I915_WRITE(DEW + (i * 4), 0); | |
3629 | ||
3630 | /* Program P-state weights to account for frequency power adjustment */ | |
3631 | for (i = 0; i < 16; i++) { | |
3632 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
3633 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
3634 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
3635 | PXVFREQ_PX_SHIFT; | |
3636 | unsigned long val; | |
3637 | ||
3638 | val = vid * vid; | |
3639 | val *= (freq / 1000); | |
3640 | val *= 255; | |
3641 | val /= (127*127*900); | |
3642 | if (val > 0xff) | |
3643 | DRM_ERROR("bad pxval: %ld\n", val); | |
3644 | pxw[i] = val; | |
3645 | } | |
3646 | /* Render standby states get 0 weight */ | |
3647 | pxw[14] = 0; | |
3648 | pxw[15] = 0; | |
3649 | ||
3650 | for (i = 0; i < 4; i++) { | |
3651 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
3652 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
3653 | I915_WRITE(PXW + (i * 4), val); | |
3654 | } | |
3655 | ||
3656 | /* Adjust magic regs to magic values (more experimental results) */ | |
3657 | I915_WRITE(OGW0, 0); | |
3658 | I915_WRITE(OGW1, 0); | |
3659 | I915_WRITE(EG0, 0x00007f00); | |
3660 | I915_WRITE(EG1, 0x0000000e); | |
3661 | I915_WRITE(EG2, 0x000e0000); | |
3662 | I915_WRITE(EG3, 0x68000300); | |
3663 | I915_WRITE(EG4, 0x42000000); | |
3664 | I915_WRITE(EG5, 0x00140031); | |
3665 | I915_WRITE(EG6, 0); | |
3666 | I915_WRITE(EG7, 0); | |
3667 | ||
3668 | for (i = 0; i < 8; i++) | |
3669 | I915_WRITE(PXWL + (i * 4), 0); | |
3670 | ||
3671 | /* Enable PMON + select events */ | |
3672 | I915_WRITE(ECR, 0x80000019); | |
3673 | ||
3674 | lcfuse = I915_READ(LCFUSE02); | |
3675 | ||
20e4d407 | 3676 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
3677 | } |
3678 | ||
8090c6b9 DV |
3679 | void intel_disable_gt_powersave(struct drm_device *dev) |
3680 | { | |
1a01ab3b JB |
3681 | struct drm_i915_private *dev_priv = dev->dev_private; |
3682 | ||
fd0c0642 DV |
3683 | /* Interrupts should be disabled already to avoid re-arming. */ |
3684 | WARN_ON(dev->irq_enabled); | |
3685 | ||
930ebb46 | 3686 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 3687 | ironlake_disable_drps(dev); |
930ebb46 | 3688 | ironlake_disable_rc6(dev); |
0a073b84 | 3689 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b | 3690 | cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work); |
250848ca | 3691 | cancel_work_sync(&dev_priv->rps.work); |
52ceb908 JB |
3692 | if (IS_VALLEYVIEW(dev)) |
3693 | cancel_delayed_work_sync(&dev_priv->rps.vlv_work); | |
4fc688ce | 3694 | mutex_lock(&dev_priv->rps.hw_lock); |
d20d4f0c JB |
3695 | if (IS_VALLEYVIEW(dev)) |
3696 | valleyview_disable_rps(dev); | |
3697 | else | |
3698 | gen6_disable_rps(dev); | |
4fc688ce | 3699 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 3700 | } |
8090c6b9 DV |
3701 | } |
3702 | ||
1a01ab3b JB |
3703 | static void intel_gen6_powersave_work(struct work_struct *work) |
3704 | { | |
3705 | struct drm_i915_private *dev_priv = | |
3706 | container_of(work, struct drm_i915_private, | |
3707 | rps.delayed_resume_work.work); | |
3708 | struct drm_device *dev = dev_priv->dev; | |
3709 | ||
4fc688ce | 3710 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 JB |
3711 | |
3712 | if (IS_VALLEYVIEW(dev)) { | |
3713 | valleyview_enable_rps(dev); | |
3714 | } else { | |
3715 | gen6_enable_rps(dev); | |
3716 | gen6_update_ring_freq(dev); | |
3717 | } | |
4fc688ce | 3718 | mutex_unlock(&dev_priv->rps.hw_lock); |
1a01ab3b JB |
3719 | } |
3720 | ||
8090c6b9 DV |
3721 | void intel_enable_gt_powersave(struct drm_device *dev) |
3722 | { | |
1a01ab3b JB |
3723 | struct drm_i915_private *dev_priv = dev->dev_private; |
3724 | ||
8090c6b9 DV |
3725 | if (IS_IRONLAKE_M(dev)) { |
3726 | ironlake_enable_drps(dev); | |
3727 | ironlake_enable_rc6(dev); | |
3728 | intel_init_emon(dev); | |
0a073b84 | 3729 | } else if (IS_GEN6(dev) || IS_GEN7(dev)) { |
1a01ab3b JB |
3730 | /* |
3731 | * PCU communication is slow and this doesn't need to be | |
3732 | * done at any specific time, so do this out of our fast path | |
3733 | * to make resume and init faster. | |
3734 | */ | |
3735 | schedule_delayed_work(&dev_priv->rps.delayed_resume_work, | |
3736 | round_jiffies_up_relative(HZ)); | |
8090c6b9 DV |
3737 | } |
3738 | } | |
3739 | ||
3107bd48 DV |
3740 | static void ibx_init_clock_gating(struct drm_device *dev) |
3741 | { | |
3742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3743 | ||
3744 | /* | |
3745 | * On Ibex Peak and Cougar Point, we need to disable clock | |
3746 | * gating for the panel power sequencer or it will fail to | |
3747 | * start up when no ports are active. | |
3748 | */ | |
3749 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
3750 | } | |
3751 | ||
1fa61106 | 3752 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
3753 | { |
3754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 3755 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 ED |
3756 | |
3757 | /* Required for FBC */ | |
4d47e4f5 DL |
3758 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
3759 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
3760 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
3761 | |
3762 | I915_WRITE(PCH_3DCGDIS0, | |
3763 | MARIUNIT_CLOCK_GATE_DISABLE | | |
3764 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
3765 | I915_WRITE(PCH_3DCGDIS1, | |
3766 | VFMUNIT_CLOCK_GATE_DISABLE); | |
3767 | ||
6f1d69b0 ED |
3768 | /* |
3769 | * According to the spec the following bits should be set in | |
3770 | * order to enable memory self-refresh | |
3771 | * The bit 22/21 of 0x42004 | |
3772 | * The bit 5 of 0x42020 | |
3773 | * The bit 15 of 0x45000 | |
3774 | */ | |
3775 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
3776 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
3777 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 3778 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
3779 | I915_WRITE(DISP_ARB_CTL, |
3780 | (I915_READ(DISP_ARB_CTL) | | |
3781 | DISP_FBC_WM_DIS)); | |
3782 | I915_WRITE(WM3_LP_ILK, 0); | |
3783 | I915_WRITE(WM2_LP_ILK, 0); | |
3784 | I915_WRITE(WM1_LP_ILK, 0); | |
3785 | ||
3786 | /* | |
3787 | * Based on the document from hardware guys the following bits | |
3788 | * should be set unconditionally in order to enable FBC. | |
3789 | * The bit 22 of 0x42000 | |
3790 | * The bit 22 of 0x42004 | |
3791 | * The bit 7,8,9 of 0x42020. | |
3792 | */ | |
3793 | if (IS_IRONLAKE_M(dev)) { | |
3794 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
3795 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
3796 | ILK_FBCQ_DIS); | |
3797 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
3798 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
3799 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
3800 | } |
3801 | ||
4d47e4f5 DL |
3802 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
3803 | ||
6f1d69b0 ED |
3804 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
3805 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
3806 | ILK_ELPIN_409_SELECT); | |
3807 | I915_WRITE(_3D_CHICKEN2, | |
3808 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
3809 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 3810 | |
ecdb4eb7 | 3811 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
3812 | I915_WRITE(CACHE_MODE_0, |
3813 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 DV |
3814 | |
3815 | ibx_init_clock_gating(dev); | |
3816 | } | |
3817 | ||
3818 | static void cpt_init_clock_gating(struct drm_device *dev) | |
3819 | { | |
3820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3821 | int pipe; | |
3f704fa2 | 3822 | uint32_t val; |
3107bd48 DV |
3823 | |
3824 | /* | |
3825 | * On Ibex Peak and Cougar Point, we need to disable clock | |
3826 | * gating for the panel power sequencer or it will fail to | |
3827 | * start up when no ports are active. | |
3828 | */ | |
3829 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
3830 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | | |
3831 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
3832 | /* The below fixes the weird display corruption, a few pixels shifted |
3833 | * downward, on (only) LVDS of some HP laptops with IVY. | |
3834 | */ | |
3f704fa2 | 3835 | for_each_pipe(pipe) { |
dc4bd2d1 PZ |
3836 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
3837 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
3838 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
3f704fa2 PZ |
3839 | if (dev_priv->fdi_rx_polarity_inverted) |
3840 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
dc4bd2d1 PZ |
3841 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
3842 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
3843 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
3844 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
3845 | } | |
3107bd48 DV |
3846 | /* WADP0ClockGatingDisable */ |
3847 | for_each_pipe(pipe) { | |
3848 | I915_WRITE(TRANS_CHICKEN1(pipe), | |
3849 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
3850 | } | |
6f1d69b0 ED |
3851 | } |
3852 | ||
1d7aaa0c DV |
3853 | static void gen6_check_mch_setup(struct drm_device *dev) |
3854 | { | |
3855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3856 | uint32_t tmp; | |
3857 | ||
3858 | tmp = I915_READ(MCH_SSKPD); | |
3859 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) { | |
3860 | DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp); | |
3861 | DRM_INFO("This can cause pipe underruns and display issues.\n"); | |
3862 | DRM_INFO("Please upgrade your BIOS to fix this.\n"); | |
3863 | } | |
3864 | } | |
3865 | ||
1fa61106 | 3866 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
3867 | { |
3868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3869 | int pipe; | |
231e54f6 | 3870 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 3871 | |
231e54f6 | 3872 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
3873 | |
3874 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
3875 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
3876 | ILK_ELPIN_409_SELECT); | |
3877 | ||
ecdb4eb7 | 3878 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
3879 | I915_WRITE(_3D_CHICKEN, |
3880 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
3881 | ||
ecdb4eb7 | 3882 | /* WaSetupGtModeTdRowDispatch:snb */ |
6547fbdb DV |
3883 | if (IS_SNB_GT1(dev)) |
3884 | I915_WRITE(GEN6_GT_MODE, | |
3885 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); | |
3886 | ||
6f1d69b0 ED |
3887 | I915_WRITE(WM3_LP_ILK, 0); |
3888 | I915_WRITE(WM2_LP_ILK, 0); | |
3889 | I915_WRITE(WM1_LP_ILK, 0); | |
3890 | ||
6f1d69b0 | 3891 | I915_WRITE(CACHE_MODE_0, |
50743298 | 3892 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
3893 | |
3894 | I915_WRITE(GEN6_UCGCTL1, | |
3895 | I915_READ(GEN6_UCGCTL1) | | |
3896 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
3897 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
3898 | ||
3899 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
3900 | * gating disable must be set. Failure to set it results in | |
3901 | * flickering pixels due to Z write ordering failures after | |
3902 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
3903 | * Sanctuary and Tropics, and apparently anything else with | |
3904 | * alpha test or pixel discard. | |
3905 | * | |
3906 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
3907 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 3908 | * |
ecdb4eb7 DL |
3909 | * Also apply WaDisableVDSUnitClockGating:snb and |
3910 | * WaDisableRCPBUnitClockGating:snb. | |
6f1d69b0 ED |
3911 | */ |
3912 | I915_WRITE(GEN6_UCGCTL2, | |
0f846f81 | 3913 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | |
6f1d69b0 ED |
3914 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
3915 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
3916 | ||
3917 | /* Bspec says we need to always set all mask bits. */ | |
26b6e44a KG |
3918 | I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) | |
3919 | _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL); | |
6f1d69b0 ED |
3920 | |
3921 | /* | |
3922 | * According to the spec the following bits should be | |
3923 | * set in order to enable memory self-refresh and fbc: | |
3924 | * The bit21 and bit22 of 0x42000 | |
3925 | * The bit21 and bit22 of 0x42004 | |
3926 | * The bit5 and bit7 of 0x42020 | |
3927 | * The bit14 of 0x70180 | |
3928 | * The bit14 of 0x71180 | |
3929 | */ | |
3930 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
3931 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
3932 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
3933 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
3934 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
3935 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
3936 | I915_WRITE(ILK_DSPCLK_GATE_D, |
3937 | I915_READ(ILK_DSPCLK_GATE_D) | | |
3938 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
3939 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 3940 | |
ecdb4eb7 | 3941 | /* WaMbcDriverBootEnable:snb */ |
b4ae3f22 JB |
3942 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
3943 | GEN6_MBCTL_ENABLE_BOOT_FETCH); | |
3944 | ||
6f1d69b0 ED |
3945 | for_each_pipe(pipe) { |
3946 | I915_WRITE(DSPCNTR(pipe), | |
3947 | I915_READ(DSPCNTR(pipe)) | | |
3948 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
3949 | intel_flush_display_plane(dev_priv, pipe); | |
3950 | } | |
f8f2ac9a BW |
3951 | |
3952 | /* The default value should be 0x200 according to docs, but the two | |
3953 | * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */ | |
3954 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff)); | |
3955 | I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI)); | |
3107bd48 DV |
3956 | |
3957 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
3958 | |
3959 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
3960 | } |
3961 | ||
3962 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
3963 | { | |
3964 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
3965 | ||
3966 | reg &= ~GEN7_FF_SCHED_MASK; | |
3967 | reg |= GEN7_FF_TS_SCHED_HW; | |
3968 | reg |= GEN7_FF_VS_SCHED_HW; | |
3969 | reg |= GEN7_FF_DS_SCHED_HW; | |
3970 | ||
41c0b3a8 BW |
3971 | if (IS_HASWELL(dev_priv->dev)) |
3972 | reg &= ~GEN7_FF_VS_REF_CNT_FFME; | |
3973 | ||
6f1d69b0 ED |
3974 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
3975 | } | |
3976 | ||
17a303ec PZ |
3977 | static void lpt_init_clock_gating(struct drm_device *dev) |
3978 | { | |
3979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3980 | ||
3981 | /* | |
3982 | * TODO: this bit should only be enabled when really needed, then | |
3983 | * disabled when not needed anymore in order to save power. | |
3984 | */ | |
3985 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
3986 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
3987 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
3988 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
3989 | } | |
3990 | ||
cad2a2d7 ED |
3991 | static void haswell_init_clock_gating(struct drm_device *dev) |
3992 | { | |
3993 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3994 | int pipe; | |
cad2a2d7 ED |
3995 | |
3996 | I915_WRITE(WM3_LP_ILK, 0); | |
3997 | I915_WRITE(WM2_LP_ILK, 0); | |
3998 | I915_WRITE(WM1_LP_ILK, 0); | |
3999 | ||
4000 | /* According to the spec, bit 13 (RCZUNIT) must be set on IVB. | |
ecdb4eb7 | 4001 | * This implements the WaDisableRCZUnitClockGating:hsw workaround. |
cad2a2d7 ED |
4002 | */ |
4003 | I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE); | |
4004 | ||
ecdb4eb7 | 4005 | /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */ |
cad2a2d7 ED |
4006 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
4007 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
4008 | ||
ecdb4eb7 | 4009 | /* WaApplyL3ControlAndL3ChickenMode:hsw */ |
cad2a2d7 ED |
4010 | I915_WRITE(GEN7_L3CNTLREG1, |
4011 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
4012 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
4013 | GEN7_WA_L3_CHICKEN_MODE); | |
4014 | ||
ecdb4eb7 | 4015 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
4016 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
4017 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
4018 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
4019 | ||
4020 | for_each_pipe(pipe) { | |
4021 | I915_WRITE(DSPCNTR(pipe), | |
4022 | I915_READ(DSPCNTR(pipe)) | | |
4023 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
4024 | intel_flush_display_plane(dev_priv, pipe); | |
4025 | } | |
4026 | ||
ecdb4eb7 | 4027 | /* WaVSRefCountFullforceMissDisable:hsw */ |
cad2a2d7 ED |
4028 | gen7_setup_fixed_func_scheduler(dev_priv); |
4029 | ||
ecdb4eb7 | 4030 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
4031 | I915_WRITE(CACHE_MODE_1, |
4032 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 4033 | |
ecdb4eb7 | 4034 | /* WaMbcDriverBootEnable:hsw */ |
b3bf0766 PZ |
4035 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
4036 | GEN6_MBCTL_ENABLE_BOOT_FETCH); | |
4037 | ||
ecdb4eb7 | 4038 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
4039 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
4040 | ||
1544d9d5 ED |
4041 | /* XXX: This is a workaround for early silicon revisions and should be |
4042 | * removed later. | |
4043 | */ | |
4044 | I915_WRITE(WM_DBG, | |
4045 | I915_READ(WM_DBG) | | |
4046 | WM_DBG_DISALLOW_MULTIPLE_LP | | |
4047 | WM_DBG_DISALLOW_SPRITE | | |
4048 | WM_DBG_DISALLOW_MAXFIFO); | |
4049 | ||
17a303ec | 4050 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
4051 | } |
4052 | ||
1fa61106 | 4053 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4054 | { |
4055 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4056 | int pipe; | |
20848223 | 4057 | uint32_t snpcr; |
6f1d69b0 | 4058 | |
6f1d69b0 ED |
4059 | I915_WRITE(WM3_LP_ILK, 0); |
4060 | I915_WRITE(WM2_LP_ILK, 0); | |
4061 | I915_WRITE(WM1_LP_ILK, 0); | |
4062 | ||
231e54f6 | 4063 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 4064 | |
ecdb4eb7 | 4065 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
4066 | I915_WRITE(_3D_CHICKEN3, |
4067 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
4068 | ||
ecdb4eb7 | 4069 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
4070 | I915_WRITE(IVB_CHICKEN3, |
4071 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
4072 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
4073 | ||
ecdb4eb7 | 4074 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
4075 | if (IS_IVB_GT1(dev)) |
4076 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
4077 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
4078 | else | |
4079 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2, | |
4080 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
4081 | ||
ecdb4eb7 | 4082 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
4083 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
4084 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
4085 | ||
ecdb4eb7 | 4086 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
4087 | I915_WRITE(GEN7_L3CNTLREG1, |
4088 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
4089 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
4090 | GEN7_WA_L3_CHICKEN_MODE); |
4091 | if (IS_IVB_GT1(dev)) | |
4092 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
4093 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
4094 | else | |
4095 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, | |
4096 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
4097 | ||
6f1d69b0 | 4098 | |
ecdb4eb7 | 4099 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
4100 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
4101 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
4102 | ||
0f846f81 JB |
4103 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
4104 | * gating disable must be set. Failure to set it results in | |
4105 | * flickering pixels due to Z write ordering failures after | |
4106 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
4107 | * Sanctuary and Tropics, and apparently anything else with | |
4108 | * alpha test or pixel discard. | |
4109 | * | |
4110 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
4111 | * but we didn't debug actual testcases to find it out. | |
4112 | * | |
4113 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. | |
ecdb4eb7 | 4114 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
4115 | */ |
4116 | I915_WRITE(GEN6_UCGCTL2, | |
4117 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | | |
4118 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
4119 | ||
ecdb4eb7 | 4120 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
4121 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
4122 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
4123 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
4124 | ||
4125 | for_each_pipe(pipe) { | |
4126 | I915_WRITE(DSPCNTR(pipe), | |
4127 | I915_READ(DSPCNTR(pipe)) | | |
4128 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
4129 | intel_flush_display_plane(dev_priv, pipe); | |
4130 | } | |
4131 | ||
ecdb4eb7 | 4132 | /* WaMbcDriverBootEnable:ivb */ |
b4ae3f22 JB |
4133 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
4134 | GEN6_MBCTL_ENABLE_BOOT_FETCH); | |
4135 | ||
ecdb4eb7 | 4136 | /* WaVSRefCountFullforceMissDisable:ivb */ |
6f1d69b0 | 4137 | gen7_setup_fixed_func_scheduler(dev_priv); |
97e1930f | 4138 | |
ecdb4eb7 | 4139 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
4140 | I915_WRITE(CACHE_MODE_1, |
4141 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 BW |
4142 | |
4143 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); | |
4144 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
4145 | snpcr |= GEN6_MBC_SNPCR_MED; | |
4146 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 4147 | |
ab5c608b BW |
4148 | if (!HAS_PCH_NOP(dev)) |
4149 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
4150 | |
4151 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
4152 | } |
4153 | ||
1fa61106 | 4154 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4155 | { |
4156 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4157 | int pipe; | |
6f1d69b0 ED |
4158 | |
4159 | I915_WRITE(WM3_LP_ILK, 0); | |
4160 | I915_WRITE(WM2_LP_ILK, 0); | |
4161 | I915_WRITE(WM1_LP_ILK, 0); | |
4162 | ||
231e54f6 | 4163 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 4164 | |
ecdb4eb7 | 4165 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
4166 | I915_WRITE(_3D_CHICKEN3, |
4167 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
4168 | ||
ecdb4eb7 | 4169 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
4170 | I915_WRITE(IVB_CHICKEN3, |
4171 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
4172 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
4173 | ||
ecdb4eb7 | 4174 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 4175 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
4176 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
4177 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 4178 | |
ecdb4eb7 | 4179 | /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */ |
6f1d69b0 ED |
4180 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
4181 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
4182 | ||
ecdb4eb7 | 4183 | /* WaApplyL3ControlAndL3ChickenMode:vlv */ |
d0cf5ead | 4184 | I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS); |
6f1d69b0 ED |
4185 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE); |
4186 | ||
ecdb4eb7 | 4187 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
4188 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
4189 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
4190 | ||
ecdb4eb7 | 4191 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
4192 | I915_WRITE(GEN7_ROW_CHICKEN2, |
4193 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
4194 | ||
ecdb4eb7 | 4195 | /* WaForceL3Serialization:vlv */ |
5c9664d7 JB |
4196 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
4197 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
4198 | ||
ecdb4eb7 | 4199 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
4200 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
4201 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
4202 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
4203 | ||
ecdb4eb7 | 4204 | /* WaMbcDriverBootEnable:vlv */ |
b4ae3f22 JB |
4205 | I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | |
4206 | GEN6_MBCTL_ENABLE_BOOT_FETCH); | |
4207 | ||
0f846f81 JB |
4208 | |
4209 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
4210 | * gating disable must be set. Failure to set it results in | |
4211 | * flickering pixels due to Z write ordering failures after | |
4212 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
4213 | * Sanctuary and Tropics, and apparently anything else with | |
4214 | * alpha test or pixel discard. | |
4215 | * | |
4216 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
4217 | * but we didn't debug actual testcases to find it out. | |
4218 | * | |
4219 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. | |
ecdb4eb7 | 4220 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 | 4221 | * |
ecdb4eb7 DL |
4222 | * Also apply WaDisableVDSUnitClockGating:vlv and |
4223 | * WaDisableRCPBUnitClockGating:vlv. | |
0f846f81 JB |
4224 | */ |
4225 | I915_WRITE(GEN6_UCGCTL2, | |
4226 | GEN7_VDSUNIT_CLOCK_GATE_DISABLE | | |
6edaa7fc | 4227 | GEN7_TDLUNIT_CLOCK_GATE_DISABLE | |
0f846f81 JB |
4228 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE | |
4229 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
4230 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
4231 | ||
e3f33d46 JB |
4232 | I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
4233 | ||
6f1d69b0 ED |
4234 | for_each_pipe(pipe) { |
4235 | I915_WRITE(DSPCNTR(pipe), | |
4236 | I915_READ(DSPCNTR(pipe)) | | |
4237 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
4238 | intel_flush_display_plane(dev_priv, pipe); | |
4239 | } | |
4240 | ||
6b26c86d DV |
4241 | I915_WRITE(CACHE_MODE_1, |
4242 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 4243 | |
2d809570 | 4244 | /* |
ecdb4eb7 | 4245 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
4246 | * Disable clock gating on th GCFG unit to prevent a delay |
4247 | * in the reporting of vblank events. | |
4248 | */ | |
4e8c84a5 JB |
4249 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff); |
4250 | ||
4251 | /* Conservative clock gating settings for now */ | |
4252 | I915_WRITE(0x9400, 0xffffffff); | |
4253 | I915_WRITE(0x9404, 0xffffffff); | |
4254 | I915_WRITE(0x9408, 0xffffffff); | |
4255 | I915_WRITE(0x940c, 0xffffffff); | |
4256 | I915_WRITE(0x9410, 0xffffffff); | |
4257 | I915_WRITE(0x9414, 0xffffffff); | |
4258 | I915_WRITE(0x9418, 0xffffffff); | |
6f1d69b0 ED |
4259 | } |
4260 | ||
1fa61106 | 4261 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4262 | { |
4263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4264 | uint32_t dspclk_gate; | |
4265 | ||
4266 | I915_WRITE(RENCLK_GATE_D1, 0); | |
4267 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
4268 | GS_UNIT_CLOCK_GATE_DISABLE | | |
4269 | CL_UNIT_CLOCK_GATE_DISABLE); | |
4270 | I915_WRITE(RAMCLK_GATE_D, 0); | |
4271 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
4272 | OVRUNIT_CLOCK_GATE_DISABLE | | |
4273 | OVCUNIT_CLOCK_GATE_DISABLE; | |
4274 | if (IS_GM45(dev)) | |
4275 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
4276 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
4277 | |
4278 | /* WaDisableRenderCachePipelinedFlush */ | |
4279 | I915_WRITE(CACHE_MODE_0, | |
4280 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
6f1d69b0 ED |
4281 | } |
4282 | ||
1fa61106 | 4283 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4284 | { |
4285 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4286 | ||
4287 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
4288 | I915_WRITE(RENCLK_GATE_D2, 0); | |
4289 | I915_WRITE(DSPCLK_GATE_D, 0); | |
4290 | I915_WRITE(RAMCLK_GATE_D, 0); | |
4291 | I915_WRITE16(DEUC, 0); | |
4292 | } | |
4293 | ||
1fa61106 | 4294 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4295 | { |
4296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4297 | ||
4298 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
4299 | I965_RCC_CLOCK_GATE_DISABLE | | |
4300 | I965_RCPB_CLOCK_GATE_DISABLE | | |
4301 | I965_ISC_CLOCK_GATE_DISABLE | | |
4302 | I965_FBC_CLOCK_GATE_DISABLE); | |
4303 | I915_WRITE(RENCLK_GATE_D2, 0); | |
4304 | } | |
4305 | ||
1fa61106 | 4306 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4307 | { |
4308 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4309 | u32 dstate = I915_READ(D_STATE); | |
4310 | ||
4311 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
4312 | DSTATE_DOT_CLOCK_GATING; | |
4313 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
4314 | |
4315 | if (IS_PINEVIEW(dev)) | |
4316 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
4317 | |
4318 | /* IIR "flip pending" means done if this bit is set */ | |
4319 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
6f1d69b0 ED |
4320 | } |
4321 | ||
1fa61106 | 4322 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4323 | { |
4324 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4325 | ||
4326 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
4327 | } | |
4328 | ||
1fa61106 | 4329 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
4330 | { |
4331 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4332 | ||
4333 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
4334 | } | |
4335 | ||
6f1d69b0 ED |
4336 | void intel_init_clock_gating(struct drm_device *dev) |
4337 | { | |
4338 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4339 | ||
4340 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
4341 | } |
4342 | ||
15d199ea PZ |
4343 | /** |
4344 | * We should only use the power well if we explicitly asked the hardware to | |
4345 | * enable it, so check if it's enabled and also check if we've requested it to | |
4346 | * be enabled. | |
4347 | */ | |
b97186f0 PZ |
4348 | bool intel_display_power_enabled(struct drm_device *dev, |
4349 | enum intel_display_power_domain domain) | |
15d199ea PZ |
4350 | { |
4351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4352 | ||
b97186f0 PZ |
4353 | if (!HAS_POWER_WELL(dev)) |
4354 | return true; | |
4355 | ||
4356 | switch (domain) { | |
4357 | case POWER_DOMAIN_PIPE_A: | |
4358 | case POWER_DOMAIN_TRANSCODER_EDP: | |
4359 | return true; | |
4360 | case POWER_DOMAIN_PIPE_B: | |
4361 | case POWER_DOMAIN_PIPE_C: | |
4362 | case POWER_DOMAIN_PIPE_A_PANEL_FITTER: | |
4363 | case POWER_DOMAIN_PIPE_B_PANEL_FITTER: | |
4364 | case POWER_DOMAIN_PIPE_C_PANEL_FITTER: | |
4365 | case POWER_DOMAIN_TRANSCODER_A: | |
4366 | case POWER_DOMAIN_TRANSCODER_B: | |
4367 | case POWER_DOMAIN_TRANSCODER_C: | |
15d199ea PZ |
4368 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
4369 | (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE); | |
b97186f0 PZ |
4370 | default: |
4371 | BUG(); | |
4372 | } | |
15d199ea PZ |
4373 | } |
4374 | ||
cb10799c | 4375 | void intel_set_power_well(struct drm_device *dev, bool enable) |
d0d3e513 ED |
4376 | { |
4377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa42e23c PZ |
4378 | bool is_enabled, enable_requested; |
4379 | uint32_t tmp; | |
d0d3e513 | 4380 | |
86d52df6 | 4381 | if (!HAS_POWER_WELL(dev)) |
d0d3e513 ED |
4382 | return; |
4383 | ||
2124b72e PZ |
4384 | if (!i915_disable_power_well && !enable) |
4385 | return; | |
4386 | ||
fa42e23c PZ |
4387 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
4388 | is_enabled = tmp & HSW_PWR_WELL_STATE; | |
4389 | enable_requested = tmp & HSW_PWR_WELL_ENABLE; | |
d0d3e513 | 4390 | |
fa42e23c PZ |
4391 | if (enable) { |
4392 | if (!enable_requested) | |
4393 | I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE); | |
d0d3e513 | 4394 | |
fa42e23c PZ |
4395 | if (!is_enabled) { |
4396 | DRM_DEBUG_KMS("Enabling power well\n"); | |
4397 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & | |
4398 | HSW_PWR_WELL_STATE), 20)) | |
4399 | DRM_ERROR("Timeout enabling power well\n"); | |
4400 | } | |
4401 | } else { | |
4402 | if (enable_requested) { | |
4403 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); | |
4404 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); | |
d0d3e513 ED |
4405 | } |
4406 | } | |
fa42e23c | 4407 | } |
d0d3e513 | 4408 | |
fa42e23c PZ |
4409 | /* |
4410 | * Starting with Haswell, we have a "Power Down Well" that can be turned off | |
4411 | * when not needed anymore. We have 4 registers that can request the power well | |
4412 | * to be enabled, and it will only be disabled if none of the registers is | |
4413 | * requesting it to be enabled. | |
d0d3e513 | 4414 | */ |
fa42e23c | 4415 | void intel_init_power_well(struct drm_device *dev) |
d0d3e513 ED |
4416 | { |
4417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d0d3e513 | 4418 | |
86d52df6 | 4419 | if (!HAS_POWER_WELL(dev)) |
d0d3e513 ED |
4420 | return; |
4421 | ||
fa42e23c PZ |
4422 | /* For now, we need the power well to be always enabled. */ |
4423 | intel_set_power_well(dev, true); | |
d0d3e513 | 4424 | |
fa42e23c PZ |
4425 | /* We're taking over the BIOS, so clear any requests made by it since |
4426 | * the driver is in charge now. */ | |
4427 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE) | |
4428 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); | |
d0d3e513 ED |
4429 | } |
4430 | ||
1fa61106 ED |
4431 | /* Set up chip specific power management-related functions */ |
4432 | void intel_init_pm(struct drm_device *dev) | |
4433 | { | |
4434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4435 | ||
4436 | if (I915_HAS_FBC(dev)) { | |
4437 | if (HAS_PCH_SPLIT(dev)) { | |
4438 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
4439 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
4440 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
4441 | } else if (IS_GM45(dev)) { | |
4442 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
4443 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
4444 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
4445 | } else if (IS_CRESTLINE(dev)) { | |
4446 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; | |
4447 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
4448 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
4449 | } | |
4450 | /* 855GM needs testing */ | |
4451 | } | |
4452 | ||
c921aba8 DV |
4453 | /* For cxsr */ |
4454 | if (IS_PINEVIEW(dev)) | |
4455 | i915_pineview_get_mem_freq(dev); | |
4456 | else if (IS_GEN5(dev)) | |
4457 | i915_ironlake_get_mem_freq(dev); | |
4458 | ||
1fa61106 ED |
4459 | /* For FIFO watermark updates */ |
4460 | if (HAS_PCH_SPLIT(dev)) { | |
1fa61106 ED |
4461 | if (IS_GEN5(dev)) { |
4462 | if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK) | |
4463 | dev_priv->display.update_wm = ironlake_update_wm; | |
4464 | else { | |
4465 | DRM_DEBUG_KMS("Failed to get proper latency. " | |
4466 | "Disable CxSR\n"); | |
4467 | dev_priv->display.update_wm = NULL; | |
4468 | } | |
4469 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; | |
4470 | } else if (IS_GEN6(dev)) { | |
4471 | if (SNB_READ_WM0_LATENCY()) { | |
4472 | dev_priv->display.update_wm = sandybridge_update_wm; | |
4473 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; | |
4474 | } else { | |
4475 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
4476 | "Disable CxSR\n"); | |
4477 | dev_priv->display.update_wm = NULL; | |
4478 | } | |
4479 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; | |
4480 | } else if (IS_IVYBRIDGE(dev)) { | |
1fa61106 | 4481 | if (SNB_READ_WM0_LATENCY()) { |
c43d0188 | 4482 | dev_priv->display.update_wm = ivybridge_update_wm; |
1fa61106 ED |
4483 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; |
4484 | } else { | |
4485 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
4486 | "Disable CxSR\n"); | |
4487 | dev_priv->display.update_wm = NULL; | |
4488 | } | |
4489 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; | |
6b8a5eeb ED |
4490 | } else if (IS_HASWELL(dev)) { |
4491 | if (SNB_READ_WM0_LATENCY()) { | |
4492 | dev_priv->display.update_wm = sandybridge_update_wm; | |
4493 | dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm; | |
1f8eeabf | 4494 | dev_priv->display.update_linetime_wm = haswell_update_linetime_wm; |
6b8a5eeb ED |
4495 | } else { |
4496 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
4497 | "Disable CxSR\n"); | |
4498 | dev_priv->display.update_wm = NULL; | |
4499 | } | |
cad2a2d7 | 4500 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
1fa61106 ED |
4501 | } else |
4502 | dev_priv->display.update_wm = NULL; | |
4503 | } else if (IS_VALLEYVIEW(dev)) { | |
4504 | dev_priv->display.update_wm = valleyview_update_wm; | |
4505 | dev_priv->display.init_clock_gating = | |
4506 | valleyview_init_clock_gating; | |
1fa61106 ED |
4507 | } else if (IS_PINEVIEW(dev)) { |
4508 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
4509 | dev_priv->is_ddr3, | |
4510 | dev_priv->fsb_freq, | |
4511 | dev_priv->mem_freq)) { | |
4512 | DRM_INFO("failed to find known CxSR latency " | |
4513 | "(found ddr%s fsb freq %d, mem freq %d), " | |
4514 | "disabling CxSR\n", | |
4515 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
4516 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
4517 | /* Disable CxSR and never update its watermark again */ | |
4518 | pineview_disable_cxsr(dev); | |
4519 | dev_priv->display.update_wm = NULL; | |
4520 | } else | |
4521 | dev_priv->display.update_wm = pineview_update_wm; | |
4522 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
4523 | } else if (IS_G4X(dev)) { | |
4524 | dev_priv->display.update_wm = g4x_update_wm; | |
4525 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
4526 | } else if (IS_GEN4(dev)) { | |
4527 | dev_priv->display.update_wm = i965_update_wm; | |
4528 | if (IS_CRESTLINE(dev)) | |
4529 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
4530 | else if (IS_BROADWATER(dev)) | |
4531 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
4532 | } else if (IS_GEN3(dev)) { | |
4533 | dev_priv->display.update_wm = i9xx_update_wm; | |
4534 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
4535 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
4536 | } else if (IS_I865G(dev)) { | |
4537 | dev_priv->display.update_wm = i830_update_wm; | |
4538 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
4539 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
4540 | } else if (IS_I85X(dev)) { | |
4541 | dev_priv->display.update_wm = i9xx_update_wm; | |
4542 | dev_priv->display.get_fifo_size = i85x_get_fifo_size; | |
4543 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
4544 | } else { | |
4545 | dev_priv->display.update_wm = i830_update_wm; | |
4546 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
4547 | if (IS_845G(dev)) | |
4548 | dev_priv->display.get_fifo_size = i845_get_fifo_size; | |
4549 | else | |
4550 | dev_priv->display.get_fifo_size = i830_get_fifo_size; | |
4551 | } | |
4552 | } | |
4553 | ||
6590190d ED |
4554 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
4555 | { | |
4556 | u32 gt_thread_status_mask; | |
4557 | ||
4558 | if (IS_HASWELL(dev_priv->dev)) | |
4559 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; | |
4560 | else | |
4561 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; | |
4562 | ||
4563 | /* w/a for a sporadic read returning 0 by waiting for the GT | |
4564 | * thread to wake up. | |
4565 | */ | |
4566 | if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) | |
4567 | DRM_ERROR("GT thread status wait timed out\n"); | |
4568 | } | |
4569 | ||
16995a9f CW |
4570 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
4571 | { | |
4572 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
4573 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ | |
4574 | } | |
4575 | ||
6590190d ED |
4576 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
4577 | { | |
ebd37ce1 | 4578 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0, |
057d3860 | 4579 | FORCEWAKE_ACK_TIMEOUT_MS)) |
8a038fd6 | 4580 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
6590190d | 4581 | |
30771e16 | 4582 | I915_WRITE_NOTRACE(FORCEWAKE, 1); |
8dee3eea | 4583 | POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */ |
6590190d | 4584 | |
ebd37ce1 | 4585 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1), |
057d3860 | 4586 | FORCEWAKE_ACK_TIMEOUT_MS)) |
8a038fd6 | 4587 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
6590190d ED |
4588 | |
4589 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
4590 | } | |
4591 | ||
16995a9f CW |
4592 | static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
4593 | { | |
4594 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); | |
b5144075 JN |
4595 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4596 | POSTING_READ(ECOBUS); | |
16995a9f CW |
4597 | } |
4598 | ||
6590190d ED |
4599 | static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
4600 | { | |
4601 | u32 forcewake_ack; | |
4602 | ||
4603 | if (IS_HASWELL(dev_priv->dev)) | |
4604 | forcewake_ack = FORCEWAKE_ACK_HSW; | |
4605 | else | |
4606 | forcewake_ack = FORCEWAKE_MT_ACK; | |
4607 | ||
83983c8b | 4608 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
057d3860 | 4609 | FORCEWAKE_ACK_TIMEOUT_MS)) |
8a038fd6 | 4610 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
6590190d | 4611 | |
c5836c27 | 4612 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
b5144075 JN |
4613 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4614 | POSTING_READ(ECOBUS); | |
6590190d | 4615 | |
83983c8b | 4616 | if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL), |
057d3860 | 4617 | FORCEWAKE_ACK_TIMEOUT_MS)) |
8a038fd6 | 4618 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
6590190d ED |
4619 | |
4620 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
4621 | } | |
4622 | ||
4623 | /* | |
4624 | * Generally this is called implicitly by the register read function. However, | |
4625 | * if some sequence requires the GT to not power down then this function should | |
4626 | * be called at the beginning of the sequence followed by a call to | |
4627 | * gen6_gt_force_wake_put() at the end of the sequence. | |
4628 | */ | |
4629 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
4630 | { | |
4631 | unsigned long irqflags; | |
4632 | ||
4633 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); | |
4634 | if (dev_priv->forcewake_count++ == 0) | |
4635 | dev_priv->gt.force_wake_get(dev_priv); | |
4636 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); | |
4637 | } | |
4638 | ||
4639 | void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) | |
4640 | { | |
4641 | u32 gtfifodbg; | |
4642 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); | |
4643 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, | |
4644 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
4645 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); | |
4646 | } | |
4647 | ||
4648 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
4649 | { | |
4650 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
b5144075 JN |
4651 | /* something from same cacheline, but !FORCEWAKE */ |
4652 | POSTING_READ(ECOBUS); | |
6590190d ED |
4653 | gen6_gt_check_fifodbg(dev_priv); |
4654 | } | |
4655 | ||
4656 | static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) | |
4657 | { | |
c5836c27 | 4658 | I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
b5144075 JN |
4659 | /* something from same cacheline, but !FORCEWAKE_MT */ |
4660 | POSTING_READ(ECOBUS); | |
6590190d ED |
4661 | gen6_gt_check_fifodbg(dev_priv); |
4662 | } | |
4663 | ||
4664 | /* | |
4665 | * see gen6_gt_force_wake_get() | |
4666 | */ | |
4667 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
4668 | { | |
4669 | unsigned long irqflags; | |
4670 | ||
4671 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); | |
4672 | if (--dev_priv->forcewake_count == 0) | |
4673 | dev_priv->gt.force_wake_put(dev_priv); | |
4674 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); | |
4675 | } | |
4676 | ||
4677 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) | |
4678 | { | |
4679 | int ret = 0; | |
4680 | ||
4681 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { | |
4682 | int loop = 500; | |
4683 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
4684 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
4685 | udelay(10); | |
4686 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
4687 | } | |
4688 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) | |
4689 | ++ret; | |
4690 | dev_priv->gt_fifo_count = fifo; | |
4691 | } | |
4692 | dev_priv->gt_fifo_count--; | |
4693 | ||
4694 | return ret; | |
4695 | } | |
4696 | ||
16995a9f CW |
4697 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
4698 | { | |
4699 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff)); | |
b5144075 JN |
4700 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
4701 | POSTING_READ(FORCEWAKE_ACK_VLV); | |
16995a9f CW |
4702 | } |
4703 | ||
6590190d ED |
4704 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv) |
4705 | { | |
83983c8b | 4706 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, |
057d3860 | 4707 | FORCEWAKE_ACK_TIMEOUT_MS)) |
8a038fd6 | 4708 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
6590190d | 4709 | |
c5836c27 | 4710 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
ed5de399 JB |
4711 | I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, |
4712 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); | |
6590190d | 4713 | |
83983c8b | 4714 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), |
057d3860 | 4715 | FORCEWAKE_ACK_TIMEOUT_MS)) |
ed5de399 JB |
4716 | DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); |
4717 | ||
4718 | if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) & | |
4719 | FORCEWAKE_KERNEL), | |
4720 | FORCEWAKE_ACK_TIMEOUT_MS)) | |
4721 | DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); | |
6590190d ED |
4722 | |
4723 | __gen6_gt_wait_for_thread_c0(dev_priv); | |
4724 | } | |
4725 | ||
4726 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv) | |
4727 | { | |
c5836c27 | 4728 | I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
ed5de399 JB |
4729 | I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV, |
4730 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); | |
4731 | /* The below doubles as a POSTING_READ */ | |
5ab140a4 | 4732 | gen6_gt_check_fifodbg(dev_priv); |
6590190d ED |
4733 | } |
4734 | ||
16995a9f CW |
4735 | void intel_gt_reset(struct drm_device *dev) |
4736 | { | |
4737 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4738 | ||
4739 | if (IS_VALLEYVIEW(dev)) { | |
4740 | vlv_force_wake_reset(dev_priv); | |
4741 | } else if (INTEL_INFO(dev)->gen >= 6) { | |
4742 | __gen6_gt_force_wake_reset(dev_priv); | |
4743 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
4744 | __gen6_gt_force_wake_mt_reset(dev_priv); | |
4745 | } | |
4746 | } | |
4747 | ||
6590190d ED |
4748 | void intel_gt_init(struct drm_device *dev) |
4749 | { | |
4750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4751 | ||
4752 | spin_lock_init(&dev_priv->gt_lock); | |
4753 | ||
16995a9f CW |
4754 | intel_gt_reset(dev); |
4755 | ||
6590190d ED |
4756 | if (IS_VALLEYVIEW(dev)) { |
4757 | dev_priv->gt.force_wake_get = vlv_force_wake_get; | |
4758 | dev_priv->gt.force_wake_put = vlv_force_wake_put; | |
36ec8f87 DV |
4759 | } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) { |
4760 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get; | |
4761 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put; | |
4762 | } else if (IS_GEN6(dev)) { | |
6590190d ED |
4763 | dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get; |
4764 | dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put; | |
6590190d | 4765 | } |
1a01ab3b JB |
4766 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
4767 | intel_gen6_powersave_work); | |
6590190d ED |
4768 | } |
4769 | ||
42c0526c BW |
4770 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
4771 | { | |
4fc688ce | 4772 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
4773 | |
4774 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
4775 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
4776 | return -EAGAIN; | |
4777 | } | |
4778 | ||
4779 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
4780 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
4781 | ||
4782 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
4783 | 500)) { | |
4784 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
4785 | return -ETIMEDOUT; | |
4786 | } | |
4787 | ||
4788 | *val = I915_READ(GEN6_PCODE_DATA); | |
4789 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
4790 | ||
4791 | return 0; | |
4792 | } | |
4793 | ||
4794 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) | |
4795 | { | |
4fc688ce | 4796 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
4797 | |
4798 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
4799 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
4800 | return -EAGAIN; | |
4801 | } | |
4802 | ||
4803 | I915_WRITE(GEN6_PCODE_DATA, val); | |
4804 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
4805 | ||
4806 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
4807 | 500)) { | |
4808 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
4809 | return -ETIMEDOUT; | |
4810 | } | |
4811 | ||
4812 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
4813 | ||
4814 | return 0; | |
4815 | } | |
a0e4e199 | 4816 | |
0a073b84 | 4817 | static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode, |
a0e4e199 JB |
4818 | u8 addr, u32 *val) |
4819 | { | |
0a073b84 | 4820 | u32 cmd, devfn, be, bar; |
a0e4e199 JB |
4821 | |
4822 | bar = 0; | |
4823 | be = 0xf; | |
a0e4e199 JB |
4824 | devfn = PCI_DEVFN(2, 0); |
4825 | ||
4826 | cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) | | |
4827 | (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) | | |
4828 | (bar << IOSF_BAR_SHIFT); | |
4829 | ||
4830 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4831 | ||
4832 | if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) { | |
4833 | DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n", | |
4834 | opcode == PUNIT_OPCODE_REG_READ ? | |
4835 | "read" : "write"); | |
4836 | return -EAGAIN; | |
4837 | } | |
4838 | ||
4839 | I915_WRITE(VLV_IOSF_ADDR, addr); | |
4840 | if (opcode == PUNIT_OPCODE_REG_WRITE) | |
4841 | I915_WRITE(VLV_IOSF_DATA, *val); | |
4842 | I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd); | |
4843 | ||
4844 | if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, | |
0a073b84 | 4845 | 5)) { |
a0e4e199 JB |
4846 | DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n", |
4847 | opcode == PUNIT_OPCODE_REG_READ ? "read" : "write", | |
4848 | addr); | |
4849 | return -ETIMEDOUT; | |
4850 | } | |
4851 | ||
4852 | if (opcode == PUNIT_OPCODE_REG_READ) | |
4853 | *val = I915_READ(VLV_IOSF_DATA); | |
4854 | I915_WRITE(VLV_IOSF_DATA, 0); | |
4855 | ||
4856 | return 0; | |
4857 | } | |
4858 | ||
4859 | int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) | |
4860 | { | |
0a073b84 JB |
4861 | return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ, |
4862 | addr, val); | |
a0e4e199 JB |
4863 | } |
4864 | ||
4865 | int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) | |
4866 | { | |
0a073b84 JB |
4867 | return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE, |
4868 | addr, &val); | |
4869 | } | |
4870 | ||
4871 | int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val) | |
4872 | { | |
4873 | return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ, | |
4874 | addr, val); | |
a0e4e199 | 4875 | } |
855ba3be JB |
4876 | |
4877 | int vlv_gpu_freq(int ddr_freq, int val) | |
4878 | { | |
4879 | int mult, base; | |
4880 | ||
4881 | switch (ddr_freq) { | |
4882 | case 800: | |
4883 | mult = 20; | |
4884 | base = 120; | |
4885 | break; | |
4886 | case 1066: | |
4887 | mult = 22; | |
4888 | base = 133; | |
4889 | break; | |
4890 | case 1333: | |
4891 | mult = 21; | |
4892 | base = 125; | |
4893 | break; | |
4894 | default: | |
4895 | return -1; | |
4896 | } | |
4897 | ||
4898 | return ((val - 0xbd) * mult) + base; | |
4899 | } | |
4900 | ||
4901 | int vlv_freq_opcode(int ddr_freq, int val) | |
4902 | { | |
4903 | int mult, base; | |
4904 | ||
4905 | switch (ddr_freq) { | |
4906 | case 800: | |
4907 | mult = 20; | |
4908 | base = 120; | |
4909 | break; | |
4910 | case 1066: | |
4911 | mult = 22; | |
4912 | base = 133; | |
4913 | break; | |
4914 | case 1333: | |
4915 | mult = 21; | |
4916 | base = 125; | |
4917 | break; | |
4918 | default: | |
4919 | return -1; | |
4920 | } | |
4921 | ||
4922 | val /= mult; | |
4923 | val -= base / mult; | |
4924 | val += 0xbd; | |
4925 | ||
4926 | if (val > 0xea) | |
4927 | val = 0xea; | |
4928 | ||
4929 | return val; | |
4930 | } | |
4931 |