projects / GitHub / MotorolaMobilityLLC / kernel-slsi.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: fix intel_ddi_get_cdclk_freq for ULT machines
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
1fa61106 47static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 48{
49 struct drm_i915_private *dev_priv = dev->dev_private;
50 u32 fbc_ctl;
51
52 /* Disable compression */
53 fbc_ctl = I915_READ(FBC_CONTROL);
54 if ((fbc_ctl & FBC_CTL_EN) == 0)
55 return;
56
57 fbc_ctl &= ~FBC_CTL_EN;
58 I915_WRITE(FBC_CONTROL, fbc_ctl);
59
60 /* Wait for compressing bit to clear */
61 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
62 DRM_DEBUG_KMS("FBC idle timed out\n");
63 return;
64 }
65
66 DRM_DEBUG_KMS("disabled FBC\n");
67}
68
1fa61106 69static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 70{
71 struct drm_device *dev = crtc->dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
73 struct drm_framebuffer *fb = crtc->fb;
74 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
75 struct drm_i915_gem_object *obj = intel_fb->obj;
76 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
77 int cfb_pitch;
78 int plane, i;
79 u32 fbc_ctl, fbc_ctl2;
80
81 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
82 if (fb->pitches[0] < cfb_pitch)
83 cfb_pitch = fb->pitches[0];
84
85 /* FBC_CTL wants 64B units */
86 cfb_pitch = (cfb_pitch / 64) - 1;
87 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
88
89 /* Clear old tags */
90 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
91 I915_WRITE(FBC_TAG + (i * 4), 0);
92
93 /* Set it up... */
94 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
95 fbc_ctl2 |= plane;
96 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
97 I915_WRITE(FBC_FENCE_OFF, crtc->y);
98
99 /* enable it... */
100 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
101 if (IS_I945GM(dev))
102 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
103 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
104 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
105 fbc_ctl |= obj->fence_reg;
106 I915_WRITE(FBC_CONTROL, fbc_ctl);
107
108 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
109 cfb_pitch, crtc->y, intel_crtc->plane);
110}
111
1fa61106 112static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 113{
114 struct drm_i915_private *dev_priv = dev->dev_private;
115
116 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
117}
118
1fa61106 119static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 120{
121 struct drm_device *dev = crtc->dev;
122 struct drm_i915_private *dev_priv = dev->dev_private;
123 struct drm_framebuffer *fb = crtc->fb;
124 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
125 struct drm_i915_gem_object *obj = intel_fb->obj;
126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
127 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
128 unsigned long stall_watermark = 200;
129 u32 dpfc_ctl;
130
131 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
132 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
133 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
134
135 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
136 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
137 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
138 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
139
140 /* enable it... */
141 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
142
143 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
144}
145
1fa61106 146static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 147{
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 u32 dpfc_ctl;
150
151 /* Disable compression */
152 dpfc_ctl = I915_READ(DPFC_CONTROL);
153 if (dpfc_ctl & DPFC_CTL_EN) {
154 dpfc_ctl &= ~DPFC_CTL_EN;
155 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
156
157 DRM_DEBUG_KMS("disabled FBC\n");
158 }
159}
160
1fa61106 161static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 162{
163 struct drm_i915_private *dev_priv = dev->dev_private;
164
165 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
166}
167
168static void sandybridge_blit_fbc_update(struct drm_device *dev)
169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171 u32 blt_ecoskpd;
172
173 /* Make sure blitter notifies FBC of writes */
174 gen6_gt_force_wake_get(dev_priv);
175 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
176 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
177 GEN6_BLITTER_LOCK_SHIFT;
178 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
179 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
180 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
181 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
182 GEN6_BLITTER_LOCK_SHIFT);
183 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
184 POSTING_READ(GEN6_BLITTER_ECOSKPD);
185 gen6_gt_force_wake_put(dev_priv);
186}
187
1fa61106 188static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 189{
190 struct drm_device *dev = crtc->dev;
191 struct drm_i915_private *dev_priv = dev->dev_private;
192 struct drm_framebuffer *fb = crtc->fb;
193 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
194 struct drm_i915_gem_object *obj = intel_fb->obj;
195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
196 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
197 unsigned long stall_watermark = 200;
198 u32 dpfc_ctl;
199
200 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
201 dpfc_ctl &= DPFC_RESERVED;
202 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
203 /* Set persistent mode for front-buffer rendering, ala X. */
204 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
205 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
206 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
207
208 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
209 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
210 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
211 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
212 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
213 /* enable it... */
214 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
215
216 if (IS_GEN6(dev)) {
217 I915_WRITE(SNB_DPFC_CTL_SA,
218 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
219 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
220 sandybridge_blit_fbc_update(dev);
221 }
222
223 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
224}
225
1fa61106 226static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 227{
228 struct drm_i915_private *dev_priv = dev->dev_private;
229 u32 dpfc_ctl;
230
231 /* Disable compression */
232 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
233 if (dpfc_ctl & DPFC_CTL_EN) {
234 dpfc_ctl &= ~DPFC_CTL_EN;
235 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
236
237 DRM_DEBUG_KMS("disabled FBC\n");
238 }
239}
240
1fa61106 241static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 242{
243 struct drm_i915_private *dev_priv = dev->dev_private;
244
245 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
246}
247
248bool intel_fbc_enabled(struct drm_device *dev)
249{
250 struct drm_i915_private *dev_priv = dev->dev_private;
251
252 if (!dev_priv->display.fbc_enabled)
253 return false;
254
255 return dev_priv->display.fbc_enabled(dev);
256}
257
258static void intel_fbc_work_fn(struct work_struct *__work)
259{
260 struct intel_fbc_work *work =
261 container_of(to_delayed_work(__work),
262 struct intel_fbc_work, work);
263 struct drm_device *dev = work->crtc->dev;
264 struct drm_i915_private *dev_priv = dev->dev_private;
265
266 mutex_lock(&dev->struct_mutex);
267 if (work == dev_priv->fbc_work) {
268 /* Double check that we haven't switched fb without cancelling
269 * the prior work.
270 */
271 if (work->crtc->fb == work->fb) {
272 dev_priv->display.enable_fbc(work->crtc,
273 work->interval);
274
275 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
276 dev_priv->cfb_fb = work->crtc->fb->base.id;
277 dev_priv->cfb_y = work->crtc->y;
278 }
279
280 dev_priv->fbc_work = NULL;
281 }
282 mutex_unlock(&dev->struct_mutex);
283
284 kfree(work);
285}
286
287static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
288{
289 if (dev_priv->fbc_work == NULL)
290 return;
291
292 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
293
294 /* Synchronisation is provided by struct_mutex and checking of
295 * dev_priv->fbc_work, so we can perform the cancellation
296 * entirely asynchronously.
297 */
298 if (cancel_delayed_work(&dev_priv->fbc_work->work))
299 /* tasklet was killed before being run, clean up */
300 kfree(dev_priv->fbc_work);
301
302 /* Mark the work as no longer wanted so that if it does
303 * wake-up (because the work was already running and waiting
304 * for our mutex), it will discover that is no longer
305 * necessary to run.
306 */
307 dev_priv->fbc_work = NULL;
308}
309
310void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
311{
312 struct intel_fbc_work *work;
313 struct drm_device *dev = crtc->dev;
314 struct drm_i915_private *dev_priv = dev->dev_private;
315
316 if (!dev_priv->display.enable_fbc)
317 return;
318
319 intel_cancel_fbc_work(dev_priv);
320
321 work = kzalloc(sizeof *work, GFP_KERNEL);
322 if (work == NULL) {
323 dev_priv->display.enable_fbc(crtc, interval);
324 return;
325 }
326
327 work->crtc = crtc;
328 work->fb = crtc->fb;
329 work->interval = interval;
330 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
331
332 dev_priv->fbc_work = work;
333
334 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
335
336 /* Delay the actual enabling to let pageflipping cease and the
337 * display to settle before starting the compression. Note that
338 * this delay also serves a second purpose: it allows for a
339 * vblank to pass after disabling the FBC before we attempt
340 * to modify the control registers.
341 *
342 * A more complicated solution would involve tracking vblanks
343 * following the termination of the page-flipping sequence
344 * and indeed performing the enable as a co-routine and not
345 * waiting synchronously upon the vblank.
346 */
347 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
348}
349
350void intel_disable_fbc(struct drm_device *dev)
351{
352 struct drm_i915_private *dev_priv = dev->dev_private;
353
354 intel_cancel_fbc_work(dev_priv);
355
356 if (!dev_priv->display.disable_fbc)
357 return;
358
359 dev_priv->display.disable_fbc(dev);
360 dev_priv->cfb_plane = -1;
361}
362
363/**
364 * intel_update_fbc - enable/disable FBC as needed
365 * @dev: the drm_device
366 *
367 * Set up the framebuffer compression hardware at mode set time. We
368 * enable it if possible:
369 * - plane A only (on pre-965)
370 * - no pixel mulitply/line duplication
371 * - no alpha buffer discard
372 * - no dual wide
373 * - framebuffer <= 2048 in width, 1536 in height
374 *
375 * We can't assume that any compression will take place (worst case),
376 * so the compressed buffer has to be the same size as the uncompressed
377 * one. It also must reside (along with the line length buffer) in
378 * stolen memory.
379 *
380 * We need to enable/disable FBC on a global basis.
381 */
382void intel_update_fbc(struct drm_device *dev)
383{
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 struct drm_crtc *crtc = NULL, *tmp_crtc;
386 struct intel_crtc *intel_crtc;
387 struct drm_framebuffer *fb;
388 struct intel_framebuffer *intel_fb;
389 struct drm_i915_gem_object *obj;
390 int enable_fbc;
391
85208be0
ED		 392 if (!i915_powersave)
393 return;
394
395 if (!I915_HAS_FBC(dev))
396 return;
397
398 /*
399 * If FBC is already on, we just have to verify that we can
400 * keep it that way...
401 * Need to disable if:
402 * - more than one pipe is active
403 * - changing FBC params (stride, fence, mode)
404 * - new fb is too large to fit in compressed buffer
405 * - going to an unsupported config (interlace, pixel multiply, etc.)
406 */
407 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
93314b5b
CW		 408 if (tmp_crtc->enabled &&
409 !to_intel_crtc(tmp_crtc)->primary_disabled &&
410 tmp_crtc->fb) {
85208be0
ED		 411 if (crtc) {
412 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
413 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
414 goto out_disable;
415 }
416 crtc = tmp_crtc;
417 }
418 }
419
420 if (!crtc || crtc->fb == NULL) {
421 DRM_DEBUG_KMS("no output, disabling\n");
422 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
423 goto out_disable;
424 }
425
426 intel_crtc = to_intel_crtc(crtc);
427 fb = crtc->fb;
428 intel_fb = to_intel_framebuffer(fb);
429 obj = intel_fb->obj;
430
431 enable_fbc = i915_enable_fbc;
432 if (enable_fbc < 0) {
433 DRM_DEBUG_KMS("fbc set to per-chip default\n");
434 enable_fbc = 1;
435 if (INTEL_INFO(dev)->gen <= 6)
436 enable_fbc = 0;
437 }
438 if (!enable_fbc) {
439 DRM_DEBUG_KMS("fbc disabled per module param\n");
440 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
441 goto out_disable;
442 }
443 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
444 DRM_DEBUG_KMS("framebuffer too large, disabling "
445 "compression\n");
446 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
447 goto out_disable;
448 }
449 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
450 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
451 DRM_DEBUG_KMS("mode incompatible with compression, "
452 "disabling\n");
453 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
454 goto out_disable;
455 }
456 if ((crtc->mode.hdisplay > 2048) ||
457 (crtc->mode.vdisplay > 1536)) {
458 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
459 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
460 goto out_disable;
461 }
462 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
463 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
464 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
465 goto out_disable;
466 }
467
468 /* The use of a CPU fence is mandatory in order to detect writes
469 * by the CPU to the scanout and trigger updates to the FBC.
470 */
471 if (obj->tiling_mode != I915_TILING_X ||
472 obj->fence_reg == I915_FENCE_REG_NONE) {
473 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
474 dev_priv->no_fbc_reason = FBC_NOT_TILED;
475 goto out_disable;
476 }
477
478 /* If the kernel debugger is active, always disable compression */
479 if (in_dbg_master())
480 goto out_disable;
481
482 /* If the scanout has not changed, don't modify the FBC settings.
483 * Note that we make the fundamental assumption that the fb->obj
484 * cannot be unpinned (and have its GTT offset and fence revoked)
485 * without first being decoupled from the scanout and FBC disabled.
486 */
487 if (dev_priv->cfb_plane == intel_crtc->plane &&
488 dev_priv->cfb_fb == fb->base.id &&
489 dev_priv->cfb_y == crtc->y)
490 return;
491
492 if (intel_fbc_enabled(dev)) {
493 /* We update FBC along two paths, after changing fb/crtc
494 * configuration (modeswitching) and after page-flipping
495 * finishes. For the latter, we know that not only did
496 * we disable the FBC at the start of the page-flip
497 * sequence, but also more than one vblank has passed.
498 *
499 * For the former case of modeswitching, it is possible
500 * to switch between two FBC valid configurations
501 * instantaneously so we do need to disable the FBC
502 * before we can modify its control registers. We also
503 * have to wait for the next vblank for that to take
504 * effect. However, since we delay enabling FBC we can
505 * assume that a vblank has passed since disabling and
506 * that we can safely alter the registers in the deferred
507 * callback.
508 *
509 * In the scenario that we go from a valid to invalid
510 * and then back to valid FBC configuration we have
511 * no strict enforcement that a vblank occurred since
512 * disabling the FBC. However, along all current pipe
513 * disabling paths we do need to wait for a vblank at
514 * some point. And we wait before enabling FBC anyway.
515 */
516 DRM_DEBUG_KMS("disabling active FBC for update\n");
517 intel_disable_fbc(dev);
518 }
519
520 intel_enable_fbc(crtc, 500);
521 return;
522
523out_disable:
524 /* Multiple disables should be harmless */
525 if (intel_fbc_enabled(dev)) {
526 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
527 intel_disable_fbc(dev);
528 }
529}
530
c921aba8
DV		 531static void i915_pineview_get_mem_freq(struct drm_device *dev)
532{
533 drm_i915_private_t *dev_priv = dev->dev_private;
534 u32 tmp;
535
536 tmp = I915_READ(CLKCFG);
537
538 switch (tmp & CLKCFG_FSB_MASK) {
539 case CLKCFG_FSB_533:
540 dev_priv->fsb_freq = 533; /* 133*4 */
541 break;
542 case CLKCFG_FSB_800:
543 dev_priv->fsb_freq = 800; /* 200*4 */
544 break;
545 case CLKCFG_FSB_667:
546 dev_priv->fsb_freq = 667; /* 167*4 */
547 break;
548 case CLKCFG_FSB_400:
549 dev_priv->fsb_freq = 400; /* 100*4 */
550 break;
551 }
552
553 switch (tmp & CLKCFG_MEM_MASK) {
554 case CLKCFG_MEM_533:
555 dev_priv->mem_freq = 533;
556 break;
557 case CLKCFG_MEM_667:
558 dev_priv->mem_freq = 667;
559 break;
560 case CLKCFG_MEM_800:
561 dev_priv->mem_freq = 800;
562 break;
563 }
564
565 /* detect pineview DDR3 setting */
566 tmp = I915_READ(CSHRDDR3CTL);
567 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
568}
569
570static void i915_ironlake_get_mem_freq(struct drm_device *dev)
571{
572 drm_i915_private_t *dev_priv = dev->dev_private;
573 u16 ddrpll, csipll;
574
575 ddrpll = I915_READ16(DDRMPLL1);
576 csipll = I915_READ16(CSIPLL0);
577
578 switch (ddrpll & 0xff) {
579 case 0xc:
580 dev_priv->mem_freq = 800;
581 break;
582 case 0x10:
583 dev_priv->mem_freq = 1066;
584 break;
585 case 0x14:
586 dev_priv->mem_freq = 1333;
587 break;
588 case 0x18:
589 dev_priv->mem_freq = 1600;
590 break;
591 default:
592 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
593 ddrpll & 0xff);
594 dev_priv->mem_freq = 0;
595 break;
596 }
597
20e4d407 598 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 599
600 switch (csipll & 0x3ff) {
601 case 0x00c:
602 dev_priv->fsb_freq = 3200;
603 break;
604 case 0x00e:
605 dev_priv->fsb_freq = 3733;
606 break;
607 case 0x010:
608 dev_priv->fsb_freq = 4266;
609 break;
610 case 0x012:
611 dev_priv->fsb_freq = 4800;
612 break;
613 case 0x014:
614 dev_priv->fsb_freq = 5333;
615 break;
616 case 0x016:
617 dev_priv->fsb_freq = 5866;
618 break;
619 case 0x018:
620 dev_priv->fsb_freq = 6400;
621 break;
622 default:
623 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
624 csipll & 0x3ff);
625 dev_priv->fsb_freq = 0;
626 break;
627 }
628
629 if (dev_priv->fsb_freq == 3200) {
20e4d407 630 dev_priv->ips.c_m = 0;
c921aba8 631 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 632 dev_priv->ips.c_m = 1;
c921aba8 633 } else {
20e4d407 634 dev_priv->ips.c_m = 2;
c921aba8
DV		 635 }
636}
637
b445e3b0
ED		 638static const struct cxsr_latency cxsr_latency_table[] = {
639 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
640 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
641 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
642 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
643 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
644
645 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
646 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
647 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
648 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
649 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
650
651 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
652 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
653 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
654 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
655 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
656
657 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
658 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
659 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
660 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
661 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
662
663 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
664 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
665 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
666 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
667 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
668
669 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
670 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
671 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
672 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
673 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
674};
675
63c62275 676static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 677 int is_ddr3,
678 int fsb,
679 int mem)
680{
681 const struct cxsr_latency *latency;
682 int i;
683
684 if (fsb == 0 || mem == 0)
685 return NULL;
686
687 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
688 latency = &cxsr_latency_table[i];
689 if (is_desktop == latency->is_desktop &&
690 is_ddr3 == latency->is_ddr3 &&
691 fsb == latency->fsb_freq && mem == latency->mem_freq)
692 return latency;
693 }
694
695 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
696
697 return NULL;
698}
699
1fa61106 700static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 701{
702 struct drm_i915_private *dev_priv = dev->dev_private;
703
704 /* deactivate cxsr */
705 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
706}
707
708/*
709 * Latency for FIFO fetches is dependent on several factors:
710 * - memory configuration (speed, channels)
711 * - chipset
712 * - current MCH state
713 * It can be fairly high in some situations, so here we assume a fairly
714 * pessimal value. It's a tradeoff between extra memory fetches (if we
715 * set this value too high, the FIFO will fetch frequently to stay full)
716 * and power consumption (set it too low to save power and we might see
717 * FIFO underruns and display "flicker").
718 *
719 * A value of 5us seems to be a good balance; safe for very low end
720 * platforms but not overly aggressive on lower latency configs.
721 */
722static const int latency_ns = 5000;
723
1fa61106 724static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 725{
726 struct drm_i915_private *dev_priv = dev->dev_private;
727 uint32_t dsparb = I915_READ(DSPARB);
728 int size;
729
730 size = dsparb & 0x7f;
731 if (plane)
732 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
733
734 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
735 plane ? "B" : "A", size);
736
737 return size;
738}
739
1fa61106 740static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 741{
742 struct drm_i915_private *dev_priv = dev->dev_private;
743 uint32_t dsparb = I915_READ(DSPARB);
744 int size;
745
746 size = dsparb & 0x1ff;
747 if (plane)
748 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
749 size >>= 1; /* Convert to cachelines */
750
751 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
752 plane ? "B" : "A", size);
753
754 return size;
755}
756
1fa61106 757static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 758{
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 uint32_t dsparb = I915_READ(DSPARB);
761 int size;
762
763 size = dsparb & 0x7f;
764 size >>= 2; /* Convert to cachelines */
765
766 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
767 plane ? "B" : "A",
768 size);
769
770 return size;
771}
772
1fa61106 773static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 774{
775 struct drm_i915_private *dev_priv = dev->dev_private;
776 uint32_t dsparb = I915_READ(DSPARB);
777 int size;
778
779 size = dsparb & 0x7f;
780 size >>= 1; /* Convert to cachelines */
781
782 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
783 plane ? "B" : "A", size);
784
785 return size;
786}
787
788/* Pineview has different values for various configs */
789static const struct intel_watermark_params pineview_display_wm = {
790 PINEVIEW_DISPLAY_FIFO,
791 PINEVIEW_MAX_WM,
792 PINEVIEW_DFT_WM,
793 PINEVIEW_GUARD_WM,
794 PINEVIEW_FIFO_LINE_SIZE
795};
796static const struct intel_watermark_params pineview_display_hplloff_wm = {
797 PINEVIEW_DISPLAY_FIFO,
798 PINEVIEW_MAX_WM,
799 PINEVIEW_DFT_HPLLOFF_WM,
800 PINEVIEW_GUARD_WM,
801 PINEVIEW_FIFO_LINE_SIZE
802};
803static const struct intel_watermark_params pineview_cursor_wm = {
804 PINEVIEW_CURSOR_FIFO,
805 PINEVIEW_CURSOR_MAX_WM,
806 PINEVIEW_CURSOR_DFT_WM,
807 PINEVIEW_CURSOR_GUARD_WM,
808 PINEVIEW_FIFO_LINE_SIZE,
809};
810static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
811 PINEVIEW_CURSOR_FIFO,
812 PINEVIEW_CURSOR_MAX_WM,
813 PINEVIEW_CURSOR_DFT_WM,
814 PINEVIEW_CURSOR_GUARD_WM,
815 PINEVIEW_FIFO_LINE_SIZE
816};
817static const struct intel_watermark_params g4x_wm_info = {
818 G4X_FIFO_SIZE,
819 G4X_MAX_WM,
820 G4X_MAX_WM,
821 2,
822 G4X_FIFO_LINE_SIZE,
823};
824static const struct intel_watermark_params g4x_cursor_wm_info = {
825 I965_CURSOR_FIFO,
826 I965_CURSOR_MAX_WM,
827 I965_CURSOR_DFT_WM,
828 2,
829 G4X_FIFO_LINE_SIZE,
830};
831static const struct intel_watermark_params valleyview_wm_info = {
832 VALLEYVIEW_FIFO_SIZE,
833 VALLEYVIEW_MAX_WM,
834 VALLEYVIEW_MAX_WM,
835 2,
836 G4X_FIFO_LINE_SIZE,
837};
838static const struct intel_watermark_params valleyview_cursor_wm_info = {
839 I965_CURSOR_FIFO,
840 VALLEYVIEW_CURSOR_MAX_WM,
841 I965_CURSOR_DFT_WM,
842 2,
843 G4X_FIFO_LINE_SIZE,
844};
845static const struct intel_watermark_params i965_cursor_wm_info = {
846 I965_CURSOR_FIFO,
847 I965_CURSOR_MAX_WM,
848 I965_CURSOR_DFT_WM,
849 2,
850 I915_FIFO_LINE_SIZE,
851};
852static const struct intel_watermark_params i945_wm_info = {
853 I945_FIFO_SIZE,
854 I915_MAX_WM,
855 1,
856 2,
857 I915_FIFO_LINE_SIZE
858};
859static const struct intel_watermark_params i915_wm_info = {
860 I915_FIFO_SIZE,
861 I915_MAX_WM,
862 1,
863 2,
864 I915_FIFO_LINE_SIZE
865};
866static const struct intel_watermark_params i855_wm_info = {
867 I855GM_FIFO_SIZE,
868 I915_MAX_WM,
869 1,
870 2,
871 I830_FIFO_LINE_SIZE
872};
873static const struct intel_watermark_params i830_wm_info = {
874 I830_FIFO_SIZE,
875 I915_MAX_WM,
876 1,
877 2,
878 I830_FIFO_LINE_SIZE
879};
880
881static const struct intel_watermark_params ironlake_display_wm_info = {
882 ILK_DISPLAY_FIFO,
883 ILK_DISPLAY_MAXWM,
884 ILK_DISPLAY_DFTWM,
885 2,
886 ILK_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params ironlake_cursor_wm_info = {
889 ILK_CURSOR_FIFO,
890 ILK_CURSOR_MAXWM,
891 ILK_CURSOR_DFTWM,
892 2,
893 ILK_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params ironlake_display_srwm_info = {
896 ILK_DISPLAY_SR_FIFO,
897 ILK_DISPLAY_MAX_SRWM,
898 ILK_DISPLAY_DFT_SRWM,
899 2,
900 ILK_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params ironlake_cursor_srwm_info = {
903 ILK_CURSOR_SR_FIFO,
904 ILK_CURSOR_MAX_SRWM,
905 ILK_CURSOR_DFT_SRWM,
906 2,
907 ILK_FIFO_LINE_SIZE
908};
909
910static const struct intel_watermark_params sandybridge_display_wm_info = {
911 SNB_DISPLAY_FIFO,
912 SNB_DISPLAY_MAXWM,
913 SNB_DISPLAY_DFTWM,
914 2,
915 SNB_FIFO_LINE_SIZE
916};
917static const struct intel_watermark_params sandybridge_cursor_wm_info = {
918 SNB_CURSOR_FIFO,
919 SNB_CURSOR_MAXWM,
920 SNB_CURSOR_DFTWM,
921 2,
922 SNB_FIFO_LINE_SIZE
923};
924static const struct intel_watermark_params sandybridge_display_srwm_info = {
925 SNB_DISPLAY_SR_FIFO,
926 SNB_DISPLAY_MAX_SRWM,
927 SNB_DISPLAY_DFT_SRWM,
928 2,
929 SNB_FIFO_LINE_SIZE
930};
931static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
932 SNB_CURSOR_SR_FIFO,
933 SNB_CURSOR_MAX_SRWM,
934 SNB_CURSOR_DFT_SRWM,
935 2,
936 SNB_FIFO_LINE_SIZE
937};
938
939
940/**
941 * intel_calculate_wm - calculate watermark level
942 * @clock_in_khz: pixel clock
943 * @wm: chip FIFO params
944 * @pixel_size: display pixel size
945 * @latency_ns: memory latency for the platform
946 *
947 * Calculate the watermark level (the level at which the display plane will
948 * start fetching from memory again). Each chip has a different display
949 * FIFO size and allocation, so the caller needs to figure that out and pass
950 * in the correct intel_watermark_params structure.
951 *
952 * As the pixel clock runs, the FIFO will be drained at a rate that depends
953 * on the pixel size. When it reaches the watermark level, it'll start
954 * fetching FIFO line sized based chunks from memory until the FIFO fills
955 * past the watermark point. If the FIFO drains completely, a FIFO underrun
956 * will occur, and a display engine hang could result.
957 */
958static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
959 const struct intel_watermark_params *wm,
960 int fifo_size,
961 int pixel_size,
962 unsigned long latency_ns)
963{
964 long entries_required, wm_size;
965
966 /*
967 * Note: we need to make sure we don't overflow for various clock &
968 * latency values.
969 * clocks go from a few thousand to several hundred thousand.
970 * latency is usually a few thousand
971 */
972 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
973 1000;
974 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
975
976 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
977
978 wm_size = fifo_size - (entries_required + wm->guard_size);
979
980 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
981
982 /* Don't promote wm_size to unsigned... */
983 if (wm_size > (long)wm->max_wm)
984 wm_size = wm->max_wm;
985 if (wm_size <= 0)
986 wm_size = wm->default_wm;
987 return wm_size;
988}
989
990static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
991{
992 struct drm_crtc *crtc, *enabled = NULL;
993
994 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
995 if (crtc->enabled && crtc->fb) {
996 if (enabled)
997 return NULL;
998 enabled = crtc;
999 }
1000 }
1001
1002 return enabled;
1003}
1004
1fa61106 1005static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1006{
1007 struct drm_i915_private *dev_priv = dev->dev_private;
1008 struct drm_crtc *crtc;
1009 const struct cxsr_latency *latency;
1010 u32 reg;
1011 unsigned long wm;
1012
1013 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1014 dev_priv->fsb_freq, dev_priv->mem_freq);
1015 if (!latency) {
1016 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1017 pineview_disable_cxsr(dev);
1018 return;
1019 }
1020
1021 crtc = single_enabled_crtc(dev);
1022 if (crtc) {
1023 int clock = crtc->mode.clock;
1024 int pixel_size = crtc->fb->bits_per_pixel / 8;
1025
1026 /* Display SR */
1027 wm = intel_calculate_wm(clock, &pineview_display_wm,
1028 pineview_display_wm.fifo_size,
1029 pixel_size, latency->display_sr);
1030 reg = I915_READ(DSPFW1);
1031 reg &= ~DSPFW_SR_MASK;
1032 reg |= wm << DSPFW_SR_SHIFT;
1033 I915_WRITE(DSPFW1, reg);
1034 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1035
1036 /* cursor SR */
1037 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1038 pineview_display_wm.fifo_size,
1039 pixel_size, latency->cursor_sr);
1040 reg = I915_READ(DSPFW3);
1041 reg &= ~DSPFW_CURSOR_SR_MASK;
1042 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1043 I915_WRITE(DSPFW3, reg);
1044
1045 /* Display HPLL off SR */
1046 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1047 pineview_display_hplloff_wm.fifo_size,
1048 pixel_size, latency->display_hpll_disable);
1049 reg = I915_READ(DSPFW3);
1050 reg &= ~DSPFW_HPLL_SR_MASK;
1051 reg |= wm & DSPFW_HPLL_SR_MASK;
1052 I915_WRITE(DSPFW3, reg);
1053
1054 /* cursor HPLL off SR */
1055 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1056 pineview_display_hplloff_wm.fifo_size,
1057 pixel_size, latency->cursor_hpll_disable);
1058 reg = I915_READ(DSPFW3);
1059 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1060 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1061 I915_WRITE(DSPFW3, reg);
1062 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1063
1064 /* activate cxsr */
1065 I915_WRITE(DSPFW3,
1066 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1067 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1068 } else {
1069 pineview_disable_cxsr(dev);
1070 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1071 }
1072}
1073
1074static bool g4x_compute_wm0(struct drm_device *dev,
1075 int plane,
1076 const struct intel_watermark_params *display,
1077 int display_latency_ns,
1078 const struct intel_watermark_params *cursor,
1079 int cursor_latency_ns,
1080 int *plane_wm,
1081 int *cursor_wm)
1082{
1083 struct drm_crtc *crtc;
1084 int htotal, hdisplay, clock, pixel_size;
1085 int line_time_us, line_count;
1086 int entries, tlb_miss;
1087
1088 crtc = intel_get_crtc_for_plane(dev, plane);
1089 if (crtc->fb == NULL || !crtc->enabled) {
1090 *cursor_wm = cursor->guard_size;
1091 *plane_wm = display->guard_size;
1092 return false;
1093 }
1094
1095 htotal = crtc->mode.htotal;
1096 hdisplay = crtc->mode.hdisplay;
1097 clock = crtc->mode.clock;
1098 pixel_size = crtc->fb->bits_per_pixel / 8;
1099
1100 /* Use the small buffer method to calculate plane watermark */
1101 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1102 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1103 if (tlb_miss > 0)
1104 entries += tlb_miss;
1105 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1106 *plane_wm = entries + display->guard_size;
1107 if (*plane_wm > (int)display->max_wm)
1108 *plane_wm = display->max_wm;
1109
1110 /* Use the large buffer method to calculate cursor watermark */
1111 line_time_us = ((htotal * 1000) / clock);
1112 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1113 entries = line_count * 64 * pixel_size;
1114 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1115 if (tlb_miss > 0)
1116 entries += tlb_miss;
1117 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1118 *cursor_wm = entries + cursor->guard_size;
1119 if (*cursor_wm > (int)cursor->max_wm)
1120 *cursor_wm = (int)cursor->max_wm;
1121
1122 return true;
1123}
1124
1125/*
1126 * Check the wm result.
1127 *
1128 * If any calculated watermark values is larger than the maximum value that
1129 * can be programmed into the associated watermark register, that watermark
1130 * must be disabled.
1131 */
1132static bool g4x_check_srwm(struct drm_device *dev,
1133 int display_wm, int cursor_wm,
1134 const struct intel_watermark_params *display,
1135 const struct intel_watermark_params *cursor)
1136{
1137 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1138 display_wm, cursor_wm);
1139
1140 if (display_wm > display->max_wm) {
1141 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1142 display_wm, display->max_wm);
1143 return false;
1144 }
1145
1146 if (cursor_wm > cursor->max_wm) {
1147 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1148 cursor_wm, cursor->max_wm);
1149 return false;
1150 }
1151
1152 if (!(display_wm || cursor_wm)) {
1153 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1154 return false;
1155 }
1156
1157 return true;
1158}
1159
1160static bool g4x_compute_srwm(struct drm_device *dev,
1161 int plane,
1162 int latency_ns,
1163 const struct intel_watermark_params *display,
1164 const struct intel_watermark_params *cursor,
1165 int *display_wm, int *cursor_wm)
1166{
1167 struct drm_crtc *crtc;
1168 int hdisplay, htotal, pixel_size, clock;
1169 unsigned long line_time_us;
1170 int line_count, line_size;
1171 int small, large;
1172 int entries;
1173
1174 if (!latency_ns) {
1175 *display_wm = *cursor_wm = 0;
1176 return false;
1177 }
1178
1179 crtc = intel_get_crtc_for_plane(dev, plane);
1180 hdisplay = crtc->mode.hdisplay;
1181 htotal = crtc->mode.htotal;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 line_time_us = (htotal * 1000) / clock;
1186 line_count = (latency_ns / line_time_us + 1000) / 1000;
1187 line_size = hdisplay * pixel_size;
1188
1189 /* Use the minimum of the small and large buffer method for primary */
1190 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1191 large = line_count * line_size;
1192
1193 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1194 *display_wm = entries + display->guard_size;
1195
1196 /* calculate the self-refresh watermark for display cursor */
1197 entries = line_count * pixel_size * 64;
1198 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1199 *cursor_wm = entries + cursor->guard_size;
1200
1201 return g4x_check_srwm(dev,
1202 *display_wm, *cursor_wm,
1203 display, cursor);
1204}
1205
1206static bool vlv_compute_drain_latency(struct drm_device *dev,
1207 int plane,
1208 int *plane_prec_mult,
1209 int *plane_dl,
1210 int *cursor_prec_mult,
1211 int *cursor_dl)
1212{
1213 struct drm_crtc *crtc;
1214 int clock, pixel_size;
1215 int entries;
1216
1217 crtc = intel_get_crtc_for_plane(dev, plane);
1218 if (crtc->fb == NULL || !crtc->enabled)
1219 return false;
1220
1221 clock = crtc->mode.clock; /* VESA DOT Clock */
1222 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1223
1224 entries = (clock / 1000) * pixel_size;
1225 *plane_prec_mult = (entries > 256) ?
1226 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1227 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1228 pixel_size);
1229
1230 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1231 *cursor_prec_mult = (entries > 256) ?
1232 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1233 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1234
1235 return true;
1236}
1237
1238/*
1239 * Update drain latency registers of memory arbiter
1240 *
1241 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1242 * to be programmed. Each plane has a drain latency multiplier and a drain
1243 * latency value.
1244 */
1245
1246static void vlv_update_drain_latency(struct drm_device *dev)
1247{
1248 struct drm_i915_private *dev_priv = dev->dev_private;
1249 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1250 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1251 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1252 either 16 or 32 */
1253
1254 /* For plane A, Cursor A */
1255 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1256 &cursor_prec_mult, &cursora_dl)) {
1257 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1258 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1259 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1260 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1261
1262 I915_WRITE(VLV_DDL1, cursora_prec |
1263 (cursora_dl << DDL_CURSORA_SHIFT) |
1264 planea_prec | planea_dl);
1265 }
1266
1267 /* For plane B, Cursor B */
1268 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1269 &cursor_prec_mult, &cursorb_dl)) {
1270 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1271 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1272 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1273 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1274
1275 I915_WRITE(VLV_DDL2, cursorb_prec |
1276 (cursorb_dl << DDL_CURSORB_SHIFT) |
1277 planeb_prec | planeb_dl);
1278 }
1279}
1280
1281#define single_plane_enabled(mask) is_power_of_2(mask)
1282
1fa61106 1283static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1284{
1285 static const int sr_latency_ns = 12000;
1286 struct drm_i915_private *dev_priv = dev->dev_private;
1287 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1288 int plane_sr, cursor_sr;
1289 unsigned int enabled = 0;
1290
1291 vlv_update_drain_latency(dev);
1292
1293 if (g4x_compute_wm0(dev, 0,
1294 &valleyview_wm_info, latency_ns,
1295 &valleyview_cursor_wm_info, latency_ns,
1296 &planea_wm, &cursora_wm))
1297 enabled |= 1;
1298
1299 if (g4x_compute_wm0(dev, 1,
1300 &valleyview_wm_info, latency_ns,
1301 &valleyview_cursor_wm_info, latency_ns,
1302 &planeb_wm, &cursorb_wm))
1303 enabled |= 2;
1304
1305 plane_sr = cursor_sr = 0;
1306 if (single_plane_enabled(enabled) &&
1307 g4x_compute_srwm(dev, ffs(enabled) - 1,
1308 sr_latency_ns,
1309 &valleyview_wm_info,
1310 &valleyview_cursor_wm_info,
1311 &plane_sr, &cursor_sr))
1312 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1313 else
1314 I915_WRITE(FW_BLC_SELF_VLV,
1315 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1316
1317 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1318 planea_wm, cursora_wm,
1319 planeb_wm, cursorb_wm,
1320 plane_sr, cursor_sr);
1321
1322 I915_WRITE(DSPFW1,
1323 (plane_sr << DSPFW_SR_SHIFT) |
1324 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1325 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1326 planea_wm);
1327 I915_WRITE(DSPFW2,
1328 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1329 (cursora_wm << DSPFW_CURSORA_SHIFT));
1330 I915_WRITE(DSPFW3,
1331 (I915_READ(DSPFW3) | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)));
1332}
1333
1fa61106 1334static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1335{
1336 static const int sr_latency_ns = 12000;
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1339 int plane_sr, cursor_sr;
1340 unsigned int enabled = 0;
1341
1342 if (g4x_compute_wm0(dev, 0,
1343 &g4x_wm_info, latency_ns,
1344 &g4x_cursor_wm_info, latency_ns,
1345 &planea_wm, &cursora_wm))
1346 enabled |= 1;
1347
1348 if (g4x_compute_wm0(dev, 1,
1349 &g4x_wm_info, latency_ns,
1350 &g4x_cursor_wm_info, latency_ns,
1351 &planeb_wm, &cursorb_wm))
1352 enabled |= 2;
1353
1354 plane_sr = cursor_sr = 0;
1355 if (single_plane_enabled(enabled) &&
1356 g4x_compute_srwm(dev, ffs(enabled) - 1,
1357 sr_latency_ns,
1358 &g4x_wm_info,
1359 &g4x_cursor_wm_info,
1360 &plane_sr, &cursor_sr))
1361 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1362 else
1363 I915_WRITE(FW_BLC_SELF,
1364 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1365
1366 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1367 planea_wm, cursora_wm,
1368 planeb_wm, cursorb_wm,
1369 plane_sr, cursor_sr);
1370
1371 I915_WRITE(DSPFW1,
1372 (plane_sr << DSPFW_SR_SHIFT) |
1373 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1374 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1375 planea_wm);
1376 I915_WRITE(DSPFW2,
1377 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
1378 (cursora_wm << DSPFW_CURSORA_SHIFT));
1379 /* HPLL off in SR has some issues on G4x... disable it */
1380 I915_WRITE(DSPFW3,
1381 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
1382 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1383}
1384
1fa61106 1385static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1386{
1387 struct drm_i915_private *dev_priv = dev->dev_private;
1388 struct drm_crtc *crtc;
1389 int srwm = 1;
1390 int cursor_sr = 16;
1391
1392 /* Calc sr entries for one plane configs */
1393 crtc = single_enabled_crtc(dev);
1394 if (crtc) {
1395 /* self-refresh has much higher latency */
1396 static const int sr_latency_ns = 12000;
1397 int clock = crtc->mode.clock;
1398 int htotal = crtc->mode.htotal;
1399 int hdisplay = crtc->mode.hdisplay;
1400 int pixel_size = crtc->fb->bits_per_pixel / 8;
1401 unsigned long line_time_us;
1402 int entries;
1403
1404 line_time_us = ((htotal * 1000) / clock);
1405
1406 /* Use ns/us then divide to preserve precision */
1407 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1408 pixel_size * hdisplay;
1409 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1410 srwm = I965_FIFO_SIZE - entries;
1411 if (srwm < 0)
1412 srwm = 1;
1413 srwm &= 0x1ff;
1414 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1415 entries, srwm);
1416
1417 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1418 pixel_size * 64;
1419 entries = DIV_ROUND_UP(entries,
1420 i965_cursor_wm_info.cacheline_size);
1421 cursor_sr = i965_cursor_wm_info.fifo_size -
1422 (entries + i965_cursor_wm_info.guard_size);
1423
1424 if (cursor_sr > i965_cursor_wm_info.max_wm)
1425 cursor_sr = i965_cursor_wm_info.max_wm;
1426
1427 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1428 "cursor %d\n", srwm, cursor_sr);
1429
1430 if (IS_CRESTLINE(dev))
1431 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1432 } else {
1433 /* Turn off self refresh if both pipes are enabled */
1434 if (IS_CRESTLINE(dev))
1435 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1436 & ~FW_BLC_SELF_EN);
1437 }
1438
1439 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1440 srwm);
1441
1442 /* 965 has limitations... */
1443 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1444 (8 << 16) | (8 << 8) | (8 << 0));
1445 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1446 /* update cursor SR watermark */
1447 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1448}
1449
1fa61106 1450static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1451{
1452 struct drm_i915_private *dev_priv = dev->dev_private;
1453 const struct intel_watermark_params *wm_info;
1454 uint32_t fwater_lo;
1455 uint32_t fwater_hi;
1456 int cwm, srwm = 1;
1457 int fifo_size;
1458 int planea_wm, planeb_wm;
1459 struct drm_crtc *crtc, *enabled = NULL;
1460
1461 if (IS_I945GM(dev))
1462 wm_info = &i945_wm_info;
1463 else if (!IS_GEN2(dev))
1464 wm_info = &i915_wm_info;
1465 else
1466 wm_info = &i855_wm_info;
1467
1468 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1469 crtc = intel_get_crtc_for_plane(dev, 0);
1470 if (crtc->enabled && crtc->fb) {
b9e0bda3
CW		 1471 int cpp = crtc->fb->bits_per_pixel / 8;
1472 if (IS_GEN2(dev))
1473 cpp = 4;
1474
b445e3b0 1475 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1476 wm_info, fifo_size, cpp,
b445e3b0
ED		 1477 latency_ns);
1478 enabled = crtc;
1479 } else
1480 planea_wm = fifo_size - wm_info->guard_size;
1481
1482 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1483 crtc = intel_get_crtc_for_plane(dev, 1);
1484 if (crtc->enabled && crtc->fb) {
b9e0bda3
CW		 1485 int cpp = crtc->fb->bits_per_pixel / 8;
1486 if (IS_GEN2(dev))
1487 cpp = 4;
1488
b445e3b0 1489 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1490 wm_info, fifo_size, cpp,
b445e3b0
ED		 1491 latency_ns);
1492 if (enabled == NULL)
1493 enabled = crtc;
1494 else
1495 enabled = NULL;
1496 } else
1497 planeb_wm = fifo_size - wm_info->guard_size;
1498
1499 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1500
1501 /*
1502 * Overlay gets an aggressive default since video jitter is bad.
1503 */
1504 cwm = 2;
1505
1506 /* Play safe and disable self-refresh before adjusting watermarks. */
1507 if (IS_I945G(dev) || IS_I945GM(dev))
1508 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1509 else if (IS_I915GM(dev))
1510 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1511
1512 /* Calc sr entries for one plane configs */
1513 if (HAS_FW_BLC(dev) && enabled) {
1514 /* self-refresh has much higher latency */
1515 static const int sr_latency_ns = 6000;
1516 int clock = enabled->mode.clock;
1517 int htotal = enabled->mode.htotal;
1518 int hdisplay = enabled->mode.hdisplay;
1519 int pixel_size = enabled->fb->bits_per_pixel / 8;
1520 unsigned long line_time_us;
1521 int entries;
1522
1523 line_time_us = (htotal * 1000) / clock;
1524
1525 /* Use ns/us then divide to preserve precision */
1526 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1527 pixel_size * hdisplay;
1528 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1529 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1530 srwm = wm_info->fifo_size - entries;
1531 if (srwm < 0)
1532 srwm = 1;
1533
1534 if (IS_I945G(dev) || IS_I945GM(dev))
1535 I915_WRITE(FW_BLC_SELF,
1536 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1537 else if (IS_I915GM(dev))
1538 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1539 }
1540
1541 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1542 planea_wm, planeb_wm, cwm, srwm);
1543
1544 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1545 fwater_hi = (cwm & 0x1f);
1546
1547 /* Set request length to 8 cachelines per fetch */
1548 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1549 fwater_hi = fwater_hi | (1 << 8);
1550
1551 I915_WRITE(FW_BLC, fwater_lo);
1552 I915_WRITE(FW_BLC2, fwater_hi);
1553
1554 if (HAS_FW_BLC(dev)) {
1555 if (enabled) {
1556 if (IS_I945G(dev) || IS_I945GM(dev))
1557 I915_WRITE(FW_BLC_SELF,
1558 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1559 else if (IS_I915GM(dev))
1560 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1561 DRM_DEBUG_KMS("memory self refresh enabled\n");
1562 } else
1563 DRM_DEBUG_KMS("memory self refresh disabled\n");
1564 }
1565}
1566
1fa61106 1567static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1568{
1569 struct drm_i915_private *dev_priv = dev->dev_private;
1570 struct drm_crtc *crtc;
1571 uint32_t fwater_lo;
1572 int planea_wm;
1573
1574 crtc = single_enabled_crtc(dev);
1575 if (crtc == NULL)
1576 return;
1577
1578 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1579 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1580 4, latency_ns);
b445e3b0
ED		 1581 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1582 fwater_lo |= (3<<8) | planea_wm;
1583
1584 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1585
1586 I915_WRITE(FW_BLC, fwater_lo);
1587}
1588
1589#define ILK_LP0_PLANE_LATENCY 700
1590#define ILK_LP0_CURSOR_LATENCY 1300
1591
1592/*
1593 * Check the wm result.
1594 *
1595 * If any calculated watermark values is larger than the maximum value that
1596 * can be programmed into the associated watermark register, that watermark
1597 * must be disabled.
1598 */
1599static bool ironlake_check_srwm(struct drm_device *dev, int level,
1600 int fbc_wm, int display_wm, int cursor_wm,
1601 const struct intel_watermark_params *display,
1602 const struct intel_watermark_params *cursor)
1603{
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605
1606 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1607 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1608
1609 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1610 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1611 fbc_wm, SNB_FBC_MAX_SRWM, level);
1612
1613 /* fbc has it's own way to disable FBC WM */
1614 I915_WRITE(DISP_ARB_CTL,
1615 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1616 return false;
1617 }
1618
1619 if (display_wm > display->max_wm) {
1620 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1621 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1622 return false;
1623 }
1624
1625 if (cursor_wm > cursor->max_wm) {
1626 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1627 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1628 return false;
1629 }
1630
1631 if (!(fbc_wm || display_wm || cursor_wm)) {
1632 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1633 return false;
1634 }
1635
1636 return true;
1637}
1638
1639/*
1640 * Compute watermark values of WM[1-3],
1641 */
1642static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1643 int latency_ns,
1644 const struct intel_watermark_params *display,
1645 const struct intel_watermark_params *cursor,
1646 int *fbc_wm, int *display_wm, int *cursor_wm)
1647{
1648 struct drm_crtc *crtc;
1649 unsigned long line_time_us;
1650 int hdisplay, htotal, pixel_size, clock;
1651 int line_count, line_size;
1652 int small, large;
1653 int entries;
1654
1655 if (!latency_ns) {
1656 *fbc_wm = *display_wm = *cursor_wm = 0;
1657 return false;
1658 }
1659
1660 crtc = intel_get_crtc_for_plane(dev, plane);
1661 hdisplay = crtc->mode.hdisplay;
1662 htotal = crtc->mode.htotal;
1663 clock = crtc->mode.clock;
1664 pixel_size = crtc->fb->bits_per_pixel / 8;
1665
1666 line_time_us = (htotal * 1000) / clock;
1667 line_count = (latency_ns / line_time_us + 1000) / 1000;
1668 line_size = hdisplay * pixel_size;
1669
1670 /* Use the minimum of the small and large buffer method for primary */
1671 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1672 large = line_count * line_size;
1673
1674 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1675 *display_wm = entries + display->guard_size;
1676
1677 /*
1678 * Spec says:
1679 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1680 */
1681 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1682
1683 /* calculate the self-refresh watermark for display cursor */
1684 entries = line_count * pixel_size * 64;
1685 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1686 *cursor_wm = entries + cursor->guard_size;
1687
1688 return ironlake_check_srwm(dev, level,
1689 *fbc_wm, *display_wm, *cursor_wm,
1690 display, cursor);
1691}
1692
1fa61106 1693static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1694{
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 int fbc_wm, plane_wm, cursor_wm;
1697 unsigned int enabled;
1698
1699 enabled = 0;
1700 if (g4x_compute_wm0(dev, 0,
1701 &ironlake_display_wm_info,
1702 ILK_LP0_PLANE_LATENCY,
1703 &ironlake_cursor_wm_info,
1704 ILK_LP0_CURSOR_LATENCY,
1705 &plane_wm, &cursor_wm)) {
1706 I915_WRITE(WM0_PIPEA_ILK,
1707 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1708 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1709 " plane %d, " "cursor: %d\n",
1710 plane_wm, cursor_wm);
1711 enabled |= 1;
1712 }
1713
1714 if (g4x_compute_wm0(dev, 1,
1715 &ironlake_display_wm_info,
1716 ILK_LP0_PLANE_LATENCY,
1717 &ironlake_cursor_wm_info,
1718 ILK_LP0_CURSOR_LATENCY,
1719 &plane_wm, &cursor_wm)) {
1720 I915_WRITE(WM0_PIPEB_ILK,
1721 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1722 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1723 " plane %d, cursor: %d\n",
1724 plane_wm, cursor_wm);
1725 enabled |= 2;
1726 }
1727
1728 /*
1729 * Calculate and update the self-refresh watermark only when one
1730 * display plane is used.
1731 */
1732 I915_WRITE(WM3_LP_ILK, 0);
1733 I915_WRITE(WM2_LP_ILK, 0);
1734 I915_WRITE(WM1_LP_ILK, 0);
1735
1736 if (!single_plane_enabled(enabled))
1737 return;
1738 enabled = ffs(enabled) - 1;
1739
1740 /* WM1 */
1741 if (!ironlake_compute_srwm(dev, 1, enabled,
1742 ILK_READ_WM1_LATENCY() * 500,
1743 &ironlake_display_srwm_info,
1744 &ironlake_cursor_srwm_info,
1745 &fbc_wm, &plane_wm, &cursor_wm))
1746 return;
1747
1748 I915_WRITE(WM1_LP_ILK,
1749 WM1_LP_SR_EN |
1750 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1751 (fbc_wm << WM1_LP_FBC_SHIFT) |
1752 (plane_wm << WM1_LP_SR_SHIFT) |
1753 cursor_wm);
1754
1755 /* WM2 */
1756 if (!ironlake_compute_srwm(dev, 2, enabled,
1757 ILK_READ_WM2_LATENCY() * 500,
1758 &ironlake_display_srwm_info,
1759 &ironlake_cursor_srwm_info,
1760 &fbc_wm, &plane_wm, &cursor_wm))
1761 return;
1762
1763 I915_WRITE(WM2_LP_ILK,
1764 WM2_LP_EN |
1765 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1766 (fbc_wm << WM1_LP_FBC_SHIFT) |
1767 (plane_wm << WM1_LP_SR_SHIFT) |
1768 cursor_wm);
1769
1770 /*
1771 * WM3 is unsupported on ILK, probably because we don't have latency
1772 * data for that power state
1773 */
1774}
1775
1fa61106 1776static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1777{
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1780 u32 val;
1781 int fbc_wm, plane_wm, cursor_wm;
1782 unsigned int enabled;
1783
1784 enabled = 0;
1785 if (g4x_compute_wm0(dev, 0,
1786 &sandybridge_display_wm_info, latency,
1787 &sandybridge_cursor_wm_info, latency,
1788 &plane_wm, &cursor_wm)) {
1789 val = I915_READ(WM0_PIPEA_ILK);
1790 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1791 I915_WRITE(WM0_PIPEA_ILK, val |
1792 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1793 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1794 " plane %d, " "cursor: %d\n",
1795 plane_wm, cursor_wm);
1796 enabled |= 1;
1797 }
1798
1799 if (g4x_compute_wm0(dev, 1,
1800 &sandybridge_display_wm_info, latency,
1801 &sandybridge_cursor_wm_info, latency,
1802 &plane_wm, &cursor_wm)) {
1803 val = I915_READ(WM0_PIPEB_ILK);
1804 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1805 I915_WRITE(WM0_PIPEB_ILK, val |
1806 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1807 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1808 " plane %d, cursor: %d\n",
1809 plane_wm, cursor_wm);
1810 enabled |= 2;
1811 }
1812
461bc9b5 1813 if ((dev_priv->num_pipe == 3) &&
b445e3b0
ED		 1814 g4x_compute_wm0(dev, 2,
1815 &sandybridge_display_wm_info, latency,
1816 &sandybridge_cursor_wm_info, latency,
1817 &plane_wm, &cursor_wm)) {
1818 val = I915_READ(WM0_PIPEC_IVB);
1819 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1820 I915_WRITE(WM0_PIPEC_IVB, val |
1821 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1822 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1823 " plane %d, cursor: %d\n",
1824 plane_wm, cursor_wm);
1825 enabled |= 3;
1826 }
1827
1828 /*
1829 * Calculate and update the self-refresh watermark only when one
1830 * display plane is used.
1831 *
1832 * SNB support 3 levels of watermark.
1833 *
1834 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1835 * and disabled in the descending order
1836 *
1837 */
1838 I915_WRITE(WM3_LP_ILK, 0);
1839 I915_WRITE(WM2_LP_ILK, 0);
1840 I915_WRITE(WM1_LP_ILK, 0);
1841
1842 if (!single_plane_enabled(enabled) ||
1843 dev_priv->sprite_scaling_enabled)
1844 return;
1845 enabled = ffs(enabled) - 1;
1846
1847 /* WM1 */
1848 if (!ironlake_compute_srwm(dev, 1, enabled,
1849 SNB_READ_WM1_LATENCY() * 500,
1850 &sandybridge_display_srwm_info,
1851 &sandybridge_cursor_srwm_info,
1852 &fbc_wm, &plane_wm, &cursor_wm))
1853 return;
1854
1855 I915_WRITE(WM1_LP_ILK,
1856 WM1_LP_SR_EN |
1857 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1858 (fbc_wm << WM1_LP_FBC_SHIFT) |
1859 (plane_wm << WM1_LP_SR_SHIFT) |
1860 cursor_wm);
1861
1862 /* WM2 */
1863 if (!ironlake_compute_srwm(dev, 2, enabled,
1864 SNB_READ_WM2_LATENCY() * 500,
1865 &sandybridge_display_srwm_info,
1866 &sandybridge_cursor_srwm_info,
1867 &fbc_wm, &plane_wm, &cursor_wm))
1868 return;
1869
1870 I915_WRITE(WM2_LP_ILK,
1871 WM2_LP_EN |
1872 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1873 (fbc_wm << WM1_LP_FBC_SHIFT) |
1874 (plane_wm << WM1_LP_SR_SHIFT) |
1875 cursor_wm);
1876
1877 /* WM3 */
1878 if (!ironlake_compute_srwm(dev, 3, enabled,
1879 SNB_READ_WM3_LATENCY() * 500,
1880 &sandybridge_display_srwm_info,
1881 &sandybridge_cursor_srwm_info,
1882 &fbc_wm, &plane_wm, &cursor_wm))
1883 return;
1884
1885 I915_WRITE(WM3_LP_ILK,
1886 WM3_LP_EN |
1887 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1888 (fbc_wm << WM1_LP_FBC_SHIFT) |
1889 (plane_wm << WM1_LP_SR_SHIFT) |
1890 cursor_wm);
1891}
1892
1f8eeabf
ED		 1893static void
1894haswell_update_linetime_wm(struct drm_device *dev, int pipe,
1895 struct drm_display_mode *mode)
1896{
1897 struct drm_i915_private *dev_priv = dev->dev_private;
1898 u32 temp;
1899
1900 temp = I915_READ(PIPE_WM_LINETIME(pipe));
1901 temp &= ~PIPE_WM_LINETIME_MASK;
1902
1903 /* The WM are computed with base on how long it takes to fill a single
1904 * row at the given clock rate, multiplied by 8.
1905 * */
1906 temp |= PIPE_WM_LINETIME_TIME(
1907 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
1908
1909 /* IPS watermarks are only used by pipe A, and are ignored by
1910 * pipes B and C. They are calculated similarly to the common
1911 * linetime values, except that we are using CD clock frequency
1912 * in MHz instead of pixel rate for the division.
1913 *
1914 * This is a placeholder for the IPS watermark calculation code.
1915 */
1916
1917 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
1918}
1919
b445e3b0
ED		 1920static bool
1921sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
1922 uint32_t sprite_width, int pixel_size,
1923 const struct intel_watermark_params *display,
1924 int display_latency_ns, int *sprite_wm)
1925{
1926 struct drm_crtc *crtc;
1927 int clock;
1928 int entries, tlb_miss;
1929
1930 crtc = intel_get_crtc_for_plane(dev, plane);
1931 if (crtc->fb == NULL || !crtc->enabled) {
1932 *sprite_wm = display->guard_size;
1933 return false;
1934 }
1935
1936 clock = crtc->mode.clock;
1937
1938 /* Use the small buffer method to calculate the sprite watermark */
1939 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1940 tlb_miss = display->fifo_size*display->cacheline_size -
1941 sprite_width * 8;
1942 if (tlb_miss > 0)
1943 entries += tlb_miss;
1944 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1945 *sprite_wm = entries + display->guard_size;
1946 if (*sprite_wm > (int)display->max_wm)
1947 *sprite_wm = display->max_wm;
1948
1949 return true;
1950}
1951
1952static bool
1953sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
1954 uint32_t sprite_width, int pixel_size,
1955 const struct intel_watermark_params *display,
1956 int latency_ns, int *sprite_wm)
1957{
1958 struct drm_crtc *crtc;
1959 unsigned long line_time_us;
1960 int clock;
1961 int line_count, line_size;
1962 int small, large;
1963 int entries;
1964
1965 if (!latency_ns) {
1966 *sprite_wm = 0;
1967 return false;
1968 }
1969
1970 crtc = intel_get_crtc_for_plane(dev, plane);
1971 clock = crtc->mode.clock;
1972 if (!clock) {
1973 *sprite_wm = 0;
1974 return false;
1975 }
1976
1977 line_time_us = (sprite_width * 1000) / clock;
1978 if (!line_time_us) {
1979 *sprite_wm = 0;
1980 return false;
1981 }
1982
1983 line_count = (latency_ns / line_time_us + 1000) / 1000;
1984 line_size = sprite_width * pixel_size;
1985
1986 /* Use the minimum of the small and large buffer method for primary */
1987 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1988 large = line_count * line_size;
1989
1990 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1991 *sprite_wm = entries + display->guard_size;
1992
1993 return *sprite_wm > 0x3ff ? false : true;
1994}
1995
1fa61106 1996static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 1997 uint32_t sprite_width, int pixel_size)
1998{
1999 struct drm_i915_private *dev_priv = dev->dev_private;
2000 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2001 u32 val;
2002 int sprite_wm, reg;
2003 int ret;
2004
2005 switch (pipe) {
2006 case 0:
2007 reg = WM0_PIPEA_ILK;
2008 break;
2009 case 1:
2010 reg = WM0_PIPEB_ILK;
2011 break;
2012 case 2:
2013 reg = WM0_PIPEC_IVB;
2014 break;
2015 default:
2016 return; /* bad pipe */
2017 }
2018
2019 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2020 &sandybridge_display_wm_info,
2021 latency, &sprite_wm);
2022 if (!ret) {
2023 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2024 pipe);
2025 return;
2026 }
2027
2028 val = I915_READ(reg);
2029 val &= ~WM0_PIPE_SPRITE_MASK;
2030 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2031 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2032
2033
2034 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2035 pixel_size,
2036 &sandybridge_display_srwm_info,
2037 SNB_READ_WM1_LATENCY() * 500,
2038 &sprite_wm);
2039 if (!ret) {
2040 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2041 pipe);
2042 return;
2043 }
2044 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2045
2046 /* Only IVB has two more LP watermarks for sprite */
2047 if (!IS_IVYBRIDGE(dev))
2048 return;
2049
2050 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2051 pixel_size,
2052 &sandybridge_display_srwm_info,
2053 SNB_READ_WM2_LATENCY() * 500,
2054 &sprite_wm);
2055 if (!ret) {
2056 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2057 pipe);
2058 return;
2059 }
2060 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2061
2062 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2063 pixel_size,
2064 &sandybridge_display_srwm_info,
2065 SNB_READ_WM3_LATENCY() * 500,
2066 &sprite_wm);
2067 if (!ret) {
2068 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2069 pipe);
2070 return;
2071 }
2072 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2073}
2074
2075/**
2076 * intel_update_watermarks - update FIFO watermark values based on current modes
2077 *
2078 * Calculate watermark values for the various WM regs based on current mode
2079 * and plane configuration.
2080 *
2081 * There are several cases to deal with here:
2082 * - normal (i.e. non-self-refresh)
2083 * - self-refresh (SR) mode
2084 * - lines are large relative to FIFO size (buffer can hold up to 2)
2085 * - lines are small relative to FIFO size (buffer can hold more than 2
2086 * lines), so need to account for TLB latency
2087 *
2088 * The normal calculation is:
2089 * watermark = dotclock * bytes per pixel * latency
2090 * where latency is platform & configuration dependent (we assume pessimal
2091 * values here).
2092 *
2093 * The SR calculation is:
2094 * watermark = (trunc(latency/line time)+1) * surface width *
2095 * bytes per pixel
2096 * where
2097 * line time = htotal / dotclock
2098 * surface width = hdisplay for normal plane and 64 for cursor
2099 * and latency is assumed to be high, as above.
2100 *
2101 * The final value programmed to the register should always be rounded up,
2102 * and include an extra 2 entries to account for clock crossings.
2103 *
2104 * We don't use the sprite, so we can ignore that. And on Crestline we have
2105 * to set the non-SR watermarks to 8.
2106 */
2107void intel_update_watermarks(struct drm_device *dev)
2108{
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110
2111 if (dev_priv->display.update_wm)
2112 dev_priv->display.update_wm(dev);
2113}
2114
1f8eeabf
ED		 2115void intel_update_linetime_watermarks(struct drm_device *dev,
2116 int pipe, struct drm_display_mode *mode)
2117{
2118 struct drm_i915_private *dev_priv = dev->dev_private;
2119
2120 if (dev_priv->display.update_linetime_wm)
2121 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2122}
2123
b445e3b0
ED		 2124void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2125 uint32_t sprite_width, int pixel_size)
2126{
2127 struct drm_i915_private *dev_priv = dev->dev_private;
2128
2129 if (dev_priv->display.update_sprite_wm)
2130 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2131 pixel_size);
2132}
2133
2b4e57bd
ED		 2134static struct drm_i915_gem_object *
2135intel_alloc_context_page(struct drm_device *dev)
2136{
2137 struct drm_i915_gem_object *ctx;
2138 int ret;
2139
2140 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2141
2142 ctx = i915_gem_alloc_object(dev, 4096);
2143 if (!ctx) {
2144 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2145 return NULL;
2146 }
2147
86a1ee26 2148 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2149 if (ret) {
2150 DRM_ERROR("failed to pin power context: %d\n", ret);
2151 goto err_unref;
2152 }
2153
2154 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2155 if (ret) {
2156 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2157 goto err_unpin;
2158 }
2159
2160 return ctx;
2161
2162err_unpin:
2163 i915_gem_object_unpin(ctx);
2164err_unref:
2165 drm_gem_object_unreference(&ctx->base);
2166 mutex_unlock(&dev->struct_mutex);
2167 return NULL;
2168}
2169
9270388e
DV		 2170/**
2171 * Lock protecting IPS related data structures
9270388e
DV		 2172 */
2173DEFINE_SPINLOCK(mchdev_lock);
2174
2175/* Global for IPS driver to get at the current i915 device. Protected by
2176 * mchdev_lock. */
2177static struct drm_i915_private *i915_mch_dev;
2178
2b4e57bd
ED		 2179bool ironlake_set_drps(struct drm_device *dev, u8 val)
2180{
2181 struct drm_i915_private *dev_priv = dev->dev_private;
2182 u16 rgvswctl;
2183
9270388e
DV		 2184 assert_spin_locked(&mchdev_lock);
2185
2b4e57bd
ED		 2186 rgvswctl = I915_READ16(MEMSWCTL);
2187 if (rgvswctl & MEMCTL_CMD_STS) {
2188 DRM_DEBUG("gpu busy, RCS change rejected\n");
2189 return false; /* still busy with another command */
2190 }
2191
2192 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2193 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2194 I915_WRITE16(MEMSWCTL, rgvswctl);
2195 POSTING_READ16(MEMSWCTL);
2196
2197 rgvswctl |= MEMCTL_CMD_STS;
2198 I915_WRITE16(MEMSWCTL, rgvswctl);
2199
2200 return true;
2201}
2202
8090c6b9 2203static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2204{
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 u32 rgvmodectl = I915_READ(MEMMODECTL);
2207 u8 fmax, fmin, fstart, vstart;
2208
9270388e
DV		 2209 spin_lock_irq(&mchdev_lock);
2210
2b4e57bd
ED		 2211 /* Enable temp reporting */
2212 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2213 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2214
2215 /* 100ms RC evaluation intervals */
2216 I915_WRITE(RCUPEI, 100000);
2217 I915_WRITE(RCDNEI, 100000);
2218
2219 /* Set max/min thresholds to 90ms and 80ms respectively */
2220 I915_WRITE(RCBMAXAVG, 90000);
2221 I915_WRITE(RCBMINAVG, 80000);
2222
2223 I915_WRITE(MEMIHYST, 1);
2224
2225 /* Set up min, max, and cur for interrupt handling */
2226 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2227 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2228 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2229 MEMMODE_FSTART_SHIFT;
2230
2231 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2232 PXVFREQ_PX_SHIFT;
2233
20e4d407
DV		 2234 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2235 dev_priv->ips.fstart = fstart;
2b4e57bd 2236
20e4d407
DV		 2237 dev_priv->ips.max_delay = fstart;
2238 dev_priv->ips.min_delay = fmin;
2239 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2240
2241 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2242 fmax, fmin, fstart);
2243
2244 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2245
2246 /*
2247 * Interrupts will be enabled in ironlake_irq_postinstall
2248 */
2249
2250 I915_WRITE(VIDSTART, vstart);
2251 POSTING_READ(VIDSTART);
2252
2253 rgvmodectl |= MEMMODE_SWMODE_EN;
2254 I915_WRITE(MEMMODECTL, rgvmodectl);
2255
9270388e 2256 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2257 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2258 mdelay(1);
2b4e57bd
ED		 2259
2260 ironlake_set_drps(dev, fstart);
2261
20e4d407 2262 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2263 I915_READ(0x112e0);
20e4d407
DV		 2264 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2265 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2266 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2267
2268 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2269}
2270
8090c6b9 2271static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2272{
2273 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2274 u16 rgvswctl;
2275
2276 spin_lock_irq(&mchdev_lock);
2277
2278 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2279
2280 /* Ack interrupts, disable EFC interrupt */
2281 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2282 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2283 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2284 I915_WRITE(DEIIR, DE_PCU_EVENT);
2285 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2286
2287 /* Go back to the starting frequency */
20e4d407 2288 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2289 mdelay(1);
2b4e57bd
ED		 2290 rgvswctl |= MEMCTL_CMD_STS;
2291 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2292 mdelay(1);
2b4e57bd 2293
9270388e 2294 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2295}
2296
acbe9475
DV		 2297/* There's a funny hw issue where the hw returns all 0 when reading from
2298 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2299 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2300 * all limits and the gpu stuck at whatever frequency it is at atm).
2301 */
65bccb5c 2302static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2303{
7b9e0ae6 2304 u32 limits;
2b4e57bd 2305
7b9e0ae6 2306 limits = 0;
c6a828d3
DV		 2307
2308 if (*val >= dev_priv->rps.max_delay)
2309 *val = dev_priv->rps.max_delay;
2310 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2311
2312 /* Only set the down limit when we've reached the lowest level to avoid
2313 * getting more interrupts, otherwise leave this clear. This prevents a
2314 * race in the hw when coming out of rc6: There's a tiny window where
2315 * the hw runs at the minimal clock before selecting the desired
2316 * frequency, if the down threshold expires in that window we will not
2317 * receive a down interrupt. */
c6a828d3
DV		 2318 if (*val <= dev_priv->rps.min_delay) {
2319 *val = dev_priv->rps.min_delay;
2320 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2321 }
2322
2323 return limits;
2324}
2325
2326void gen6_set_rps(struct drm_device *dev, u8 val)
2327{
2328 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2329 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2330
4fc688ce 2331 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 2332 WARN_ON(val > dev_priv->rps.max_delay);
2333 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2334
c6a828d3 2335 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2336 return;
2337
2338 I915_WRITE(GEN6_RPNSWREQ,
2339 GEN6_FREQUENCY(val) |
2340 GEN6_OFFSET(0) |
2341 GEN6_AGGRESSIVE_TURBO);
2342
2343 /* Make sure we continue to get interrupts
2344 * until we hit the minimum or maximum frequencies.
2345 */
2346 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2347
d5570a72
BW		 2348 POSTING_READ(GEN6_RPNSWREQ);
2349
c6a828d3 2350 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2351
2352 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2353}
2354
8090c6b9 2355static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2356{
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358
88509484 2359 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2360 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2361 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2362 I915_WRITE(GEN6_PMIER, 0);
2363 /* Complete PM interrupt masking here doesn't race with the rps work
2364 * item again unmasking PM interrupts because that is using a different
2365 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2366 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2367
c6a828d3
DV		 2368 spin_lock_irq(&dev_priv->rps.lock);
2369 dev_priv->rps.pm_iir = 0;
2370 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2371
2372 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2373}
2374
2375int intel_enable_rc6(const struct drm_device *dev)
2376{
456470eb 2377 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2378 if (i915_enable_rc6 >= 0)
2379 return i915_enable_rc6;
2380
456470eb 2381 if (INTEL_INFO(dev)->gen == 5) {
cd7988ee
DV		 2382#ifdef CONFIG_INTEL_IOMMU
2383 /* Disable rc6 on ilk if VT-d is on. */
2384 if (intel_iommu_gfx_mapped)
2385 return false;
2386#endif
456470eb
DV		 2387 DRM_DEBUG_DRIVER("Ironlake: only RC6 available\n");
2388 return INTEL_RC6_ENABLE;
2389 }
2b4e57bd 2390
456470eb
DV		 2391 if (IS_HASWELL(dev)) {
2392 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2393 return INTEL_RC6_ENABLE;
456470eb 2394 }
2b4e57bd 2395
456470eb 2396 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2397 if (INTEL_INFO(dev)->gen == 6) {
2398 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2399 return INTEL_RC6_ENABLE;
2400 }
456470eb 2401
2b4e57bd
ED		 2402 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2403 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2404}
2405
79f5b2c7 2406static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2407{
79f5b2c7 2408 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2409 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2410 u32 rp_state_cap;
2411 u32 gt_perf_status;
31643d54 2412 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 2413 u32 gtfifodbg;
2b4e57bd 2414 int rc6_mode;
42c0526c 2415 int i, ret;
2b4e57bd 2416
4fc688ce 2417 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2418
2b4e57bd
ED		 2419 /* Here begins a magic sequence of register writes to enable
2420 * auto-downclocking.
2421 *
2422 * Perhaps there might be some value in exposing these to
2423 * userspace...
2424 */
2425 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2426
2427 /* Clear the DBG now so we don't confuse earlier errors */
2428 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2429 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2430 I915_WRITE(GTFIFODBG, gtfifodbg);
2431 }
2432
2433 gen6_gt_force_wake_get(dev_priv);
2434
7b9e0ae6
CW		 2435 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2436 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2437
2438 /* In units of 100MHz */
c6a828d3
DV		 2439 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2440 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2441 dev_priv->rps.cur_delay = 0;
7b9e0ae6 2442
2b4e57bd
ED		 2443 /* disable the counters and set deterministic thresholds */
2444 I915_WRITE(GEN6_RC_CONTROL, 0);
2445
2446 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2447 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2448 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2449 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2450 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2451
b4519513
CW		 2452 for_each_ring(ring, dev_priv, i)
2453 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2454
2455 I915_WRITE(GEN6_RC_SLEEP, 0);
2456 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2457 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2458 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2459 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2460
5a7dc92a 2461 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2462 rc6_mode = intel_enable_rc6(dev_priv->dev);
2463 if (rc6_mode & INTEL_RC6_ENABLE)
2464 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2465
5a7dc92a
ED		 2466 /* We don't use those on Haswell */
2467 if (!IS_HASWELL(dev)) {
2468 if (rc6_mode & INTEL_RC6p_ENABLE)
2469 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2470
5a7dc92a
ED		 2471 if (rc6_mode & INTEL_RC6pp_ENABLE)
2472 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2473 }
2b4e57bd
ED		 2474
2475 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2476 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2477 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2478 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2479
2480 I915_WRITE(GEN6_RC_CONTROL,
2481 rc6_mask |
2482 GEN6_RC_CTL_EI_MODE(1) |
2483 GEN6_RC_CTL_HW_ENABLE);
2484
2485 I915_WRITE(GEN6_RPNSWREQ,
2486 GEN6_FREQUENCY(10) |
2487 GEN6_OFFSET(0) |
2488 GEN6_AGGRESSIVE_TURBO);
2489 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2490 GEN6_FREQUENCY(12));
2491
2492 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2493 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 2494 dev_priv->rps.max_delay << 24 |
2495 dev_priv->rps.min_delay << 16);
5a7dc92a 2496
1ee9ae32
DV		 2497 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2498 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2499 I915_WRITE(GEN6_RP_UP_EI, 66000);
2500 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 2501
2b4e57bd
ED		 2502 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2503 I915_WRITE(GEN6_RP_CONTROL,
2504 GEN6_RP_MEDIA_TURBO |
89ba829e 2505 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2506 GEN6_RP_MEDIA_IS_GFX |
2507 GEN6_RP_ENABLE |
2508 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2509 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 2510
42c0526c
BW		 2511 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2512 if (!ret) {
2513 pcu_mbox = 0;
2514 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2515 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2516 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2517 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2518 }
2519 } else {
2520 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 2521 }
2522
7b9e0ae6 2523 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2524
2525 /* requires MSI enabled */
ff928261 2526 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 2527 spin_lock_irq(&dev_priv->rps.lock);
2528 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 2529 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 2530 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2531 /* enable all PM interrupts */
2532 I915_WRITE(GEN6_PMINTRMSK, 0);
2533
31643d54
BW		 2534 rc6vids = 0;
2535 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2536 if (IS_GEN6(dev) && ret) {
2537 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2538 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2539 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2540 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2541 rc6vids &= 0xffff00;
2542 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2543 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2544 if (ret)
2545 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2546 }
2547
2b4e57bd 2548 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2549}
2550
79f5b2c7 2551static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2552{
79f5b2c7 2553 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 2554 int min_freq = 15;
e3fef09d
JD		 2555 int gpu_freq;
2556 unsigned int ia_freq, max_ia_freq;
2b4e57bd
ED		 2557 int scaling_factor = 180;
2558
4fc688ce 2559 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2560
2b4e57bd
ED		 2561 max_ia_freq = cpufreq_quick_get_max(0);
2562 /*
2563 * Default to measured freq if none found, PCU will ensure we don't go
2564 * over
2565 */
2566 if (!max_ia_freq)
2567 max_ia_freq = tsc_khz;
2568
2569 /* Convert from kHz to MHz */
2570 max_ia_freq /= 1000;
2571
2b4e57bd
ED		 2572 /*
2573 * For each potential GPU frequency, load a ring frequency we'd like
2574 * to use for memory access. We do this by specifying the IA frequency
2575 * the PCU should use as a reference to determine the ring frequency.
2576 */
c6a828d3 2577 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 2578 gpu_freq--) {
c6a828d3 2579 int diff = dev_priv->rps.max_delay - gpu_freq;
2b4e57bd
ED		 2580
2581 /*
2582 * For GPU frequencies less than 750MHz, just use the lowest
2583 * ring freq.
2584 */
2585 if (gpu_freq < min_freq)
2586 ia_freq = 800;
2587 else
2588 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2589 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
42c0526c 2590 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2b4e57bd 2591
42c0526c
BW		 2592 sandybridge_pcode_write(dev_priv,
2593 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2594 ia_freq | gpu_freq);
2b4e57bd 2595 }
2b4e57bd
ED		 2596}
2597
930ebb46 2598void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 2599{
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601
3e373948
DV		 2602 if (dev_priv->ips.renderctx) {
2603 i915_gem_object_unpin(dev_priv->ips.renderctx);
2604 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2605 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 2606 }
2607
3e373948
DV		 2608 if (dev_priv->ips.pwrctx) {
2609 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2610 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2611 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 2612 }
2613}
2614
930ebb46 2615static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2616{
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618
2619 if (I915_READ(PWRCTXA)) {
2620 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2621 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2622 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2623 50);
2624
2625 I915_WRITE(PWRCTXA, 0);
2626 POSTING_READ(PWRCTXA);
2627
2628 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2629 POSTING_READ(RSTDBYCTL);
2630 }
2b4e57bd
ED		 2631}
2632
2633static int ironlake_setup_rc6(struct drm_device *dev)
2634{
2635 struct drm_i915_private *dev_priv = dev->dev_private;
2636
3e373948
DV		 2637 if (dev_priv->ips.renderctx == NULL)
2638 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2639 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 2640 return -ENOMEM;
2641
3e373948
DV		 2642 if (dev_priv->ips.pwrctx == NULL)
2643 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2644 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 2645 ironlake_teardown_rc6(dev);
2646 return -ENOMEM;
2647 }
2648
2649 return 0;
2650}
2651
930ebb46 2652static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2653{
2654 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 2655 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2b4e57bd
ED		 2656 int ret;
2657
2658 /* rc6 disabled by default due to repeated reports of hanging during
2659 * boot and resume.
2660 */
2661 if (!intel_enable_rc6(dev))
2662 return;
2663
79f5b2c7
DV		 2664 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2665
2b4e57bd 2666 ret = ironlake_setup_rc6(dev);
79f5b2c7 2667 if (ret)
2b4e57bd 2668 return;
2b4e57bd
ED		 2669
2670 /*
2671 * GPU can automatically power down the render unit if given a page
2672 * to save state.
2673 */
6d90c952 2674 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 2675 if (ret) {
2676 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2677 return;
2678 }
2679
6d90c952
DV		 2680 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2681 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 2682 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 2683 MI_MM_SPACE_GTT |
2684 MI_SAVE_EXT_STATE_EN |
2685 MI_RESTORE_EXT_STATE_EN |
2686 MI_RESTORE_INHIBIT);
2687 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2688 intel_ring_emit(ring, MI_NOOP);
2689 intel_ring_emit(ring, MI_FLUSH);
2690 intel_ring_advance(ring);
2b4e57bd
ED		 2691
2692 /*
2693 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2694 * does an implicit flush, combined with MI_FLUSH above, it should be
2695 * safe to assume that renderctx is valid
2696 */
6d90c952 2697 ret = intel_wait_ring_idle(ring);
2b4e57bd
ED		 2698 if (ret) {
2699 DRM_ERROR("failed to enable ironlake power power savings\n");
2700 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2701 return;
2702 }
2703
3e373948 2704 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 2705 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 2706}
2707
dde18883
ED		 2708static unsigned long intel_pxfreq(u32 vidfreq)
2709{
2710 unsigned long freq;
2711 int div = (vidfreq & 0x3f0000) >> 16;
2712 int post = (vidfreq & 0x3000) >> 12;
2713 int pre = (vidfreq & 0x7);
2714
2715 if (!pre)
2716 return 0;
2717
2718 freq = ((div * 133333) / ((1<<post) * pre));
2719
2720 return freq;
2721}
2722
eb48eb00
DV		 2723static const struct cparams {
2724 u16 i;
2725 u16 t;
2726 u16 m;
2727 u16 c;
2728} cparams[] = {
2729 { 1, 1333, 301, 28664 },
2730 { 1, 1066, 294, 24460 },
2731 { 1, 800, 294, 25192 },
2732 { 0, 1333, 276, 27605 },
2733 { 0, 1066, 276, 27605 },
2734 { 0, 800, 231, 23784 },
2735};
2736
f531dcb2 2737static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2738{
2739 u64 total_count, diff, ret;
2740 u32 count1, count2, count3, m = 0, c = 0;
2741 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2742 int i;
2743
02d71956
DV		 2744 assert_spin_locked(&mchdev_lock);
2745
20e4d407 2746 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 2747
2748 /* Prevent division-by-zero if we are asking too fast.
2749 * Also, we don't get interesting results if we are polling
2750 * faster than once in 10ms, so just return the saved value
2751 * in such cases.
2752 */
2753 if (diff1 <= 10)
20e4d407 2754 return dev_priv->ips.chipset_power;
eb48eb00
DV		 2755
2756 count1 = I915_READ(DMIEC);
2757 count2 = I915_READ(DDREC);
2758 count3 = I915_READ(CSIEC);
2759
2760 total_count = count1 + count2 + count3;
2761
2762 /* FIXME: handle per-counter overflow */
20e4d407
DV		 2763 if (total_count < dev_priv->ips.last_count1) {
2764 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 2765 diff += total_count;
2766 } else {
20e4d407 2767 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 2768 }
2769
2770 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 2771 if (cparams[i].i == dev_priv->ips.c_m &&
2772 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 2773 m = cparams[i].m;
2774 c = cparams[i].c;
2775 break;
2776 }
2777 }
2778
2779 diff = div_u64(diff, diff1);
2780 ret = ((m * diff) + c);
2781 ret = div_u64(ret, 10);
2782
20e4d407
DV		 2783 dev_priv->ips.last_count1 = total_count;
2784 dev_priv->ips.last_time1 = now;
eb48eb00 2785
20e4d407 2786 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 2787
2788 return ret;
2789}
2790
f531dcb2
CW		 2791unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2792{
2793 unsigned long val;
2794
2795 if (dev_priv->info->gen != 5)
2796 return 0;
2797
2798 spin_lock_irq(&mchdev_lock);
2799
2800 val = __i915_chipset_val(dev_priv);
2801
2802 spin_unlock_irq(&mchdev_lock);
2803
2804 return val;
2805}
2806
eb48eb00
DV		 2807unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2808{
2809 unsigned long m, x, b;
2810 u32 tsfs;
2811
2812 tsfs = I915_READ(TSFS);
2813
2814 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2815 x = I915_READ8(TR1);
2816
2817 b = tsfs & TSFS_INTR_MASK;
2818
2819 return ((m * x) / 127) - b;
2820}
2821
2822static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2823{
2824 static const struct v_table {
2825 u16 vd; /* in .1 mil */
2826 u16 vm; /* in .1 mil */
2827 } v_table[] = {
2828 { 0, 0, },
2829 { 375, 0, },
2830 { 500, 0, },
2831 { 625, 0, },
2832 { 750, 0, },
2833 { 875, 0, },
2834 { 1000, 0, },
2835 { 1125, 0, },
2836 { 4125, 3000, },
2837 { 4125, 3000, },
2838 { 4125, 3000, },
2839 { 4125, 3000, },
2840 { 4125, 3000, },
2841 { 4125, 3000, },
2842 { 4125, 3000, },
2843 { 4125, 3000, },
2844 { 4125, 3000, },
2845 { 4125, 3000, },
2846 { 4125, 3000, },
2847 { 4125, 3000, },
2848 { 4125, 3000, },
2849 { 4125, 3000, },
2850 { 4125, 3000, },
2851 { 4125, 3000, },
2852 { 4125, 3000, },
2853 { 4125, 3000, },
2854 { 4125, 3000, },
2855 { 4125, 3000, },
2856 { 4125, 3000, },
2857 { 4125, 3000, },
2858 { 4125, 3000, },
2859 { 4125, 3000, },
2860 { 4250, 3125, },
2861 { 4375, 3250, },
2862 { 4500, 3375, },
2863 { 4625, 3500, },
2864 { 4750, 3625, },
2865 { 4875, 3750, },
2866 { 5000, 3875, },
2867 { 5125, 4000, },
2868 { 5250, 4125, },
2869 { 5375, 4250, },
2870 { 5500, 4375, },
2871 { 5625, 4500, },
2872 { 5750, 4625, },
2873 { 5875, 4750, },
2874 { 6000, 4875, },
2875 { 6125, 5000, },
2876 { 6250, 5125, },
2877 { 6375, 5250, },
2878 { 6500, 5375, },
2879 { 6625, 5500, },
2880 { 6750, 5625, },
2881 { 6875, 5750, },
2882 { 7000, 5875, },
2883 { 7125, 6000, },
2884 { 7250, 6125, },
2885 { 7375, 6250, },
2886 { 7500, 6375, },
2887 { 7625, 6500, },
2888 { 7750, 6625, },
2889 { 7875, 6750, },
2890 { 8000, 6875, },
2891 { 8125, 7000, },
2892 { 8250, 7125, },
2893 { 8375, 7250, },
2894 { 8500, 7375, },
2895 { 8625, 7500, },
2896 { 8750, 7625, },
2897 { 8875, 7750, },
2898 { 9000, 7875, },
2899 { 9125, 8000, },
2900 { 9250, 8125, },
2901 { 9375, 8250, },
2902 { 9500, 8375, },
2903 { 9625, 8500, },
2904 { 9750, 8625, },
2905 { 9875, 8750, },
2906 { 10000, 8875, },
2907 { 10125, 9000, },
2908 { 10250, 9125, },
2909 { 10375, 9250, },
2910 { 10500, 9375, },
2911 { 10625, 9500, },
2912 { 10750, 9625, },
2913 { 10875, 9750, },
2914 { 11000, 9875, },
2915 { 11125, 10000, },
2916 { 11250, 10125, },
2917 { 11375, 10250, },
2918 { 11500, 10375, },
2919 { 11625, 10500, },
2920 { 11750, 10625, },
2921 { 11875, 10750, },
2922 { 12000, 10875, },
2923 { 12125, 11000, },
2924 { 12250, 11125, },
2925 { 12375, 11250, },
2926 { 12500, 11375, },
2927 { 12625, 11500, },
2928 { 12750, 11625, },
2929 { 12875, 11750, },
2930 { 13000, 11875, },
2931 { 13125, 12000, },
2932 { 13250, 12125, },
2933 { 13375, 12250, },
2934 { 13500, 12375, },
2935 { 13625, 12500, },
2936 { 13750, 12625, },
2937 { 13875, 12750, },
2938 { 14000, 12875, },
2939 { 14125, 13000, },
2940 { 14250, 13125, },
2941 { 14375, 13250, },
2942 { 14500, 13375, },
2943 { 14625, 13500, },
2944 { 14750, 13625, },
2945 { 14875, 13750, },
2946 { 15000, 13875, },
2947 { 15125, 14000, },
2948 { 15250, 14125, },
2949 { 15375, 14250, },
2950 { 15500, 14375, },
2951 { 15625, 14500, },
2952 { 15750, 14625, },
2953 { 15875, 14750, },
2954 { 16000, 14875, },
2955 { 16125, 15000, },
2956 };
2957 if (dev_priv->info->is_mobile)
2958 return v_table[pxvid].vm;
2959 else
2960 return v_table[pxvid].vd;
2961}
2962
02d71956 2963static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2964{
2965 struct timespec now, diff1;
2966 u64 diff;
2967 unsigned long diffms;
2968 u32 count;
2969
02d71956 2970 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 2971
2972 getrawmonotonic(&now);
20e4d407 2973 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 2974
2975 /* Don't divide by 0 */
2976 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
2977 if (!diffms)
2978 return;
2979
2980 count = I915_READ(GFXEC);
2981
20e4d407
DV		 2982 if (count < dev_priv->ips.last_count2) {
2983 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 2984 diff += count;
2985 } else {
20e4d407 2986 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 2987 }
2988
20e4d407
DV		 2989 dev_priv->ips.last_count2 = count;
2990 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 2991
2992 /* More magic constants... */
2993 diff = diff * 1181;
2994 diff = div_u64(diff, diffms * 10);
20e4d407 2995 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 2996}
2997
02d71956
DV		 2998void i915_update_gfx_val(struct drm_i915_private *dev_priv)
2999{
3000 if (dev_priv->info->gen != 5)
3001 return;
3002
9270388e 3003 spin_lock_irq(&mchdev_lock);
02d71956
DV		 3004
3005 __i915_update_gfx_val(dev_priv);
3006
9270388e 3007 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3008}
3009
f531dcb2 3010static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3011{
3012 unsigned long t, corr, state1, corr2, state2;
3013 u32 pxvid, ext_v;
3014
02d71956
DV		 3015 assert_spin_locked(&mchdev_lock);
3016
c6a828d3 3017 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3018 pxvid = (pxvid >> 24) & 0x7f;
3019 ext_v = pvid_to_extvid(dev_priv, pxvid);
3020
3021 state1 = ext_v;
3022
3023 t = i915_mch_val(dev_priv);
3024
3025 /* Revel in the empirically derived constants */
3026
3027 /* Correction factor in 1/100000 units */
3028 if (t > 80)
3029 corr = ((t * 2349) + 135940);
3030 else if (t >= 50)
3031 corr = ((t * 964) + 29317);
3032 else /* < 50 */
3033 corr = ((t * 301) + 1004);
3034
3035 corr = corr * ((150142 * state1) / 10000 - 78642);
3036 corr /= 100000;
20e4d407 3037 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3038
3039 state2 = (corr2 * state1) / 10000;
3040 state2 /= 100; /* convert to mW */
3041
02d71956 3042 __i915_update_gfx_val(dev_priv);
eb48eb00 3043
20e4d407 3044 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3045}
3046
f531dcb2
CW		 3047unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3048{
3049 unsigned long val;
3050
3051 if (dev_priv->info->gen != 5)
3052 return 0;
3053
3054 spin_lock_irq(&mchdev_lock);
3055
3056 val = __i915_gfx_val(dev_priv);
3057
3058 spin_unlock_irq(&mchdev_lock);
3059
3060 return val;
3061}
3062
eb48eb00
DV		 3063/**
3064 * i915_read_mch_val - return value for IPS use
3065 *
3066 * Calculate and return a value for the IPS driver to use when deciding whether
3067 * we have thermal and power headroom to increase CPU or GPU power budget.
3068 */
3069unsigned long i915_read_mch_val(void)
3070{
3071 struct drm_i915_private *dev_priv;
3072 unsigned long chipset_val, graphics_val, ret = 0;
3073
9270388e 3074 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3075 if (!i915_mch_dev)
3076 goto out_unlock;
3077 dev_priv = i915_mch_dev;
3078
f531dcb2
CW		 3079 chipset_val = __i915_chipset_val(dev_priv);
3080 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3081
3082 ret = chipset_val + graphics_val;
3083
3084out_unlock:
9270388e 3085 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3086
3087 return ret;
3088}
3089EXPORT_SYMBOL_GPL(i915_read_mch_val);
3090
3091/**
3092 * i915_gpu_raise - raise GPU frequency limit
3093 *
3094 * Raise the limit; IPS indicates we have thermal headroom.
3095 */
3096bool i915_gpu_raise(void)
3097{
3098 struct drm_i915_private *dev_priv;
3099 bool ret = true;
3100
9270388e 3101 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3102 if (!i915_mch_dev) {
3103 ret = false;
3104 goto out_unlock;
3105 }
3106 dev_priv = i915_mch_dev;
3107
20e4d407
DV		 3108 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3109 dev_priv->ips.max_delay--;
eb48eb00
DV		 3110
3111out_unlock:
9270388e 3112 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3113
3114 return ret;
3115}
3116EXPORT_SYMBOL_GPL(i915_gpu_raise);
3117
3118/**
3119 * i915_gpu_lower - lower GPU frequency limit
3120 *
3121 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3122 * frequency maximum.
3123 */
3124bool i915_gpu_lower(void)
3125{
3126 struct drm_i915_private *dev_priv;
3127 bool ret = true;
3128
9270388e 3129 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3130 if (!i915_mch_dev) {
3131 ret = false;
3132 goto out_unlock;
3133 }
3134 dev_priv = i915_mch_dev;
3135
20e4d407
DV		 3136 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3137 dev_priv->ips.max_delay++;
eb48eb00
DV		 3138
3139out_unlock:
9270388e 3140 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3141
3142 return ret;
3143}
3144EXPORT_SYMBOL_GPL(i915_gpu_lower);
3145
3146/**
3147 * i915_gpu_busy - indicate GPU business to IPS
3148 *
3149 * Tell the IPS driver whether or not the GPU is busy.
3150 */
3151bool i915_gpu_busy(void)
3152{
3153 struct drm_i915_private *dev_priv;
f047e395 3154 struct intel_ring_buffer *ring;
eb48eb00 3155 bool ret = false;
f047e395 3156 int i;
eb48eb00 3157
9270388e 3158 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3159 if (!i915_mch_dev)
3160 goto out_unlock;
3161 dev_priv = i915_mch_dev;
3162
f047e395
CW		 3163 for_each_ring(ring, dev_priv, i)
3164 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3165
3166out_unlock:
9270388e 3167 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3168
3169 return ret;
3170}
3171EXPORT_SYMBOL_GPL(i915_gpu_busy);
3172
3173/**
3174 * i915_gpu_turbo_disable - disable graphics turbo
3175 *
3176 * Disable graphics turbo by resetting the max frequency and setting the
3177 * current frequency to the default.
3178 */
3179bool i915_gpu_turbo_disable(void)
3180{
3181 struct drm_i915_private *dev_priv;
3182 bool ret = true;
3183
9270388e 3184 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3185 if (!i915_mch_dev) {
3186 ret = false;
3187 goto out_unlock;
3188 }
3189 dev_priv = i915_mch_dev;
3190
20e4d407 3191 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 3192
20e4d407 3193 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 3194 ret = false;
3195
3196out_unlock:
9270388e 3197 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3198
3199 return ret;
3200}
3201EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3202
3203/**
3204 * Tells the intel_ips driver that the i915 driver is now loaded, if
3205 * IPS got loaded first.
3206 *
3207 * This awkward dance is so that neither module has to depend on the
3208 * other in order for IPS to do the appropriate communication of
3209 * GPU turbo limits to i915.
3210 */
3211static void
3212ips_ping_for_i915_load(void)
3213{
3214 void (*link)(void);
3215
3216 link = symbol_get(ips_link_to_i915_driver);
3217 if (link) {
3218 link();
3219 symbol_put(ips_link_to_i915_driver);
3220 }
3221}
3222
3223void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3224{
02d71956
DV		 3225 /* We only register the i915 ips part with intel-ips once everything is
3226 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 3227 spin_lock_irq(&mchdev_lock);
eb48eb00 3228 i915_mch_dev = dev_priv;
9270388e 3229 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3230
3231 ips_ping_for_i915_load();
3232}
3233
3234void intel_gpu_ips_teardown(void)
3235{
9270388e 3236 spin_lock_irq(&mchdev_lock);
eb48eb00 3237 i915_mch_dev = NULL;
9270388e 3238 spin_unlock_irq(&mchdev_lock);
eb48eb00 3239}
8090c6b9 3240static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3241{
3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 u32 lcfuse;
3244 u8 pxw[16];
3245 int i;
3246
3247 /* Disable to program */
3248 I915_WRITE(ECR, 0);
3249 POSTING_READ(ECR);
3250
3251 /* Program energy weights for various events */
3252 I915_WRITE(SDEW, 0x15040d00);
3253 I915_WRITE(CSIEW0, 0x007f0000);
3254 I915_WRITE(CSIEW1, 0x1e220004);
3255 I915_WRITE(CSIEW2, 0x04000004);
3256
3257 for (i = 0; i < 5; i++)
3258 I915_WRITE(PEW + (i * 4), 0);
3259 for (i = 0; i < 3; i++)
3260 I915_WRITE(DEW + (i * 4), 0);
3261
3262 /* Program P-state weights to account for frequency power adjustment */
3263 for (i = 0; i < 16; i++) {
3264 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3265 unsigned long freq = intel_pxfreq(pxvidfreq);
3266 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3267 PXVFREQ_PX_SHIFT;
3268 unsigned long val;
3269
3270 val = vid * vid;
3271 val *= (freq / 1000);
3272 val *= 255;
3273 val /= (127*127*900);
3274 if (val > 0xff)
3275 DRM_ERROR("bad pxval: %ld\n", val);
3276 pxw[i] = val;
3277 }
3278 /* Render standby states get 0 weight */
3279 pxw[14] = 0;
3280 pxw[15] = 0;
3281
3282 for (i = 0; i < 4; i++) {
3283 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3284 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3285 I915_WRITE(PXW + (i * 4), val);
3286 }
3287
3288 /* Adjust magic regs to magic values (more experimental results) */
3289 I915_WRITE(OGW0, 0);
3290 I915_WRITE(OGW1, 0);
3291 I915_WRITE(EG0, 0x00007f00);
3292 I915_WRITE(EG1, 0x0000000e);
3293 I915_WRITE(EG2, 0x000e0000);
3294 I915_WRITE(EG3, 0x68000300);
3295 I915_WRITE(EG4, 0x42000000);
3296 I915_WRITE(EG5, 0x00140031);
3297 I915_WRITE(EG6, 0);
3298 I915_WRITE(EG7, 0);
3299
3300 for (i = 0; i < 8; i++)
3301 I915_WRITE(PXWL + (i * 4), 0);
3302
3303 /* Enable PMON + select events */
3304 I915_WRITE(ECR, 0x80000019);
3305
3306 lcfuse = I915_READ(LCFUSE02);
3307
20e4d407 3308 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 3309}
3310
8090c6b9
DV		 3311void intel_disable_gt_powersave(struct drm_device *dev)
3312{
1a01ab3b
JB		 3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314
930ebb46 3315 if (IS_IRONLAKE_M(dev)) {
8090c6b9 3316 ironlake_disable_drps(dev);
930ebb46
DV		 3317 ironlake_disable_rc6(dev);
3318 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
1a01ab3b 3319 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4fc688ce 3320 mutex_lock(&dev_priv->rps.hw_lock);
8090c6b9 3321 gen6_disable_rps(dev);
4fc688ce 3322 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 3323 }
8090c6b9
DV		 3324}
3325
1a01ab3b
JB		 3326static void intel_gen6_powersave_work(struct work_struct *work)
3327{
3328 struct drm_i915_private *dev_priv =
3329 container_of(work, struct drm_i915_private,
3330 rps.delayed_resume_work.work);
3331 struct drm_device *dev = dev_priv->dev;
3332
4fc688ce 3333 mutex_lock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3334 gen6_enable_rps(dev);
3335 gen6_update_ring_freq(dev);
4fc688ce 3336 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3337}
3338
8090c6b9
DV		 3339void intel_enable_gt_powersave(struct drm_device *dev)
3340{
1a01ab3b
JB		 3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342
8090c6b9
DV		 3343 if (IS_IRONLAKE_M(dev)) {
3344 ironlake_enable_drps(dev);
3345 ironlake_enable_rc6(dev);
3346 intel_init_emon(dev);
7cf50fc8 3347 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1a01ab3b
JB		 3348 /*
3349 * PCU communication is slow and this doesn't need to be
3350 * done at any specific time, so do this out of our fast path
3351 * to make resume and init faster.
3352 */
3353 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3354 round_jiffies_up_relative(HZ));
8090c6b9
DV		 3355 }
3356}
3357
3107bd48
DV		 3358static void ibx_init_clock_gating(struct drm_device *dev)
3359{
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361
3362 /*
3363 * On Ibex Peak and Cougar Point, we need to disable clock
3364 * gating for the panel power sequencer or it will fail to
3365 * start up when no ports are active.
3366 */
3367 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3368}
3369
1fa61106 3370static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3371{
3372 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 3373 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 3374
3375 /* Required for FBC */
4d47e4f5
DL		 3376 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3377 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3378 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3379
3380 I915_WRITE(PCH_3DCGDIS0,
3381 MARIUNIT_CLOCK_GATE_DISABLE |
3382 SVSMUNIT_CLOCK_GATE_DISABLE);
3383 I915_WRITE(PCH_3DCGDIS1,
3384 VFMUNIT_CLOCK_GATE_DISABLE);
3385
6f1d69b0
ED		 3386 /*
3387 * According to the spec the following bits should be set in
3388 * order to enable memory self-refresh
3389 * The bit 22/21 of 0x42004
3390 * The bit 5 of 0x42020
3391 * The bit 15 of 0x45000
3392 */
3393 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3394 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3395 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 3396 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3397 I915_WRITE(DISP_ARB_CTL,
3398 (I915_READ(DISP_ARB_CTL) |
3399 DISP_FBC_WM_DIS));
3400 I915_WRITE(WM3_LP_ILK, 0);
3401 I915_WRITE(WM2_LP_ILK, 0);
3402 I915_WRITE(WM1_LP_ILK, 0);
3403
3404 /*
3405 * Based on the document from hardware guys the following bits
3406 * should be set unconditionally in order to enable FBC.
3407 * The bit 22 of 0x42000
3408 * The bit 22 of 0x42004
3409 * The bit 7,8,9 of 0x42020.
3410 */
3411 if (IS_IRONLAKE_M(dev)) {
3412 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3413 I915_READ(ILK_DISPLAY_CHICKEN1) |
3414 ILK_FBCQ_DIS);
3415 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3416 I915_READ(ILK_DISPLAY_CHICKEN2) |
3417 ILK_DPARB_GATE);
6f1d69b0
ED		 3418 }
3419
4d47e4f5
DL		 3420 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3421
6f1d69b0
ED		 3422 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3423 I915_READ(ILK_DISPLAY_CHICKEN2) |
3424 ILK_ELPIN_409_SELECT);
3425 I915_WRITE(_3D_CHICKEN2,
3426 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3427 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374
DV		 3428
3429 /* WaDisableRenderCachePipelinedFlush */
3430 I915_WRITE(CACHE_MODE_0,
3431 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 3432
3433 ibx_init_clock_gating(dev);
3434}
3435
3436static void cpt_init_clock_gating(struct drm_device *dev)
3437{
3438 struct drm_i915_private *dev_priv = dev->dev_private;
3439 int pipe;
3440
3441 /*
3442 * On Ibex Peak and Cougar Point, we need to disable clock
3443 * gating for the panel power sequencer or it will fail to
3444 * start up when no ports are active.
3445 */
3446 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3447 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3448 DPLS_EDP_PPS_FIX_DIS);
3449 /* WADP0ClockGatingDisable */
3450 for_each_pipe(pipe) {
3451 I915_WRITE(TRANS_CHICKEN1(pipe),
3452 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3453 }
6f1d69b0
ED		 3454}
3455
1fa61106 3456static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3457{
3458 struct drm_i915_private *dev_priv = dev->dev_private;
3459 int pipe;
231e54f6 3460 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 3461
231e54f6 3462 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 3463
3464 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3465 I915_READ(ILK_DISPLAY_CHICKEN2) |
3466 ILK_ELPIN_409_SELECT);
3467
3468 I915_WRITE(WM3_LP_ILK, 0);
3469 I915_WRITE(WM2_LP_ILK, 0);
3470 I915_WRITE(WM1_LP_ILK, 0);
3471
6f1d69b0 3472 I915_WRITE(CACHE_MODE_0,
50743298 3473 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3474
3475 I915_WRITE(GEN6_UCGCTL1,
3476 I915_READ(GEN6_UCGCTL1) |
3477 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3478 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3479
3480 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3481 * gating disable must be set. Failure to set it results in
3482 * flickering pixels due to Z write ordering failures after
3483 * some amount of runtime in the Mesa "fire" demo, and Unigine
3484 * Sanctuary and Tropics, and apparently anything else with
3485 * alpha test or pixel discard.
3486 *
3487 * According to the spec, bit 11 (RCCUNIT) must also be set,
3488 * but we didn't debug actual testcases to find it out.
0f846f81
JB		 3489 *
3490 * Also apply WaDisableVDSUnitClockGating and
3491 * WaDisableRCPBUnitClockGating.
6f1d69b0
ED		 3492 */
3493 I915_WRITE(GEN6_UCGCTL2,
0f846f81 3494 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 3495 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3496 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3497
3498 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 3499 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3500 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 3501
3502 /*
3503 * According to the spec the following bits should be
3504 * set in order to enable memory self-refresh and fbc:
3505 * The bit21 and bit22 of 0x42000
3506 * The bit21 and bit22 of 0x42004
3507 * The bit5 and bit7 of 0x42020
3508 * The bit14 of 0x70180
3509 * The bit14 of 0x71180
3510 */
3511 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3512 I915_READ(ILK_DISPLAY_CHICKEN1) |
3513 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3514 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3515 I915_READ(ILK_DISPLAY_CHICKEN2) |
3516 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 3517 I915_WRITE(ILK_DSPCLK_GATE_D,
3518 I915_READ(ILK_DSPCLK_GATE_D) |
3519 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3520 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 3521
b4ae3f22
JB		 3522 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3523 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3524
6f1d69b0
ED		 3525 for_each_pipe(pipe) {
3526 I915_WRITE(DSPCNTR(pipe),
3527 I915_READ(DSPCNTR(pipe)) |
3528 DISPPLANE_TRICKLE_FEED_DISABLE);
3529 intel_flush_display_plane(dev_priv, pipe);
3530 }
f8f2ac9a
BW		 3531
3532 /* The default value should be 0x200 according to docs, but the two
3533 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3534 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3535 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 3536
3537 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3538}
3539
3540static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3541{
3542 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3543
3544 reg &= ~GEN7_FF_SCHED_MASK;
3545 reg |= GEN7_FF_TS_SCHED_HW;
3546 reg |= GEN7_FF_VS_SCHED_HW;
3547 reg |= GEN7_FF_DS_SCHED_HW;
3548
3549 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3550}
3551
17a303ec
PZ		 3552static void lpt_init_clock_gating(struct drm_device *dev)
3553{
3554 struct drm_i915_private *dev_priv = dev->dev_private;
3555
3556 /*
3557 * TODO: this bit should only be enabled when really needed, then
3558 * disabled when not needed anymore in order to save power.
3559 */
3560 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3561 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3562 I915_READ(SOUTH_DSPCLK_GATE_D) |
3563 PCH_LP_PARTITION_LEVEL_DISABLE);
3564}
3565
cad2a2d7
ED		 3566static void haswell_init_clock_gating(struct drm_device *dev)
3567{
3568 struct drm_i915_private *dev_priv = dev->dev_private;
3569 int pipe;
cad2a2d7
ED		 3570
3571 I915_WRITE(WM3_LP_ILK, 0);
3572 I915_WRITE(WM2_LP_ILK, 0);
3573 I915_WRITE(WM1_LP_ILK, 0);
3574
3575 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3576 * This implements the WaDisableRCZUnitClockGating workaround.
3577 */
3578 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3579
cad2a2d7
ED		 3580 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3581 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3582 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3583
3584 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3585 I915_WRITE(GEN7_L3CNTLREG1,
3586 GEN7_WA_FOR_GEN7_L3_CONTROL);
3587 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3588 GEN7_WA_L3_CHICKEN_MODE);
3589
3590 /* This is required by WaCatErrorRejectionIssue */
3591 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3592 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3593 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3594
3595 for_each_pipe(pipe) {
3596 I915_WRITE(DSPCNTR(pipe),
3597 I915_READ(DSPCNTR(pipe)) |
3598 DISPPLANE_TRICKLE_FEED_DISABLE);
3599 intel_flush_display_plane(dev_priv, pipe);
3600 }
3601
3602 gen7_setup_fixed_func_scheduler(dev_priv);
3603
3604 /* WaDisable4x2SubspanOptimization */
3605 I915_WRITE(CACHE_MODE_1,
3606 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5
ED		 3607
3608 /* XXX: This is a workaround for early silicon revisions and should be
3609 * removed later.
3610 */
3611 I915_WRITE(WM_DBG,
3612 I915_READ(WM_DBG) |
3613 WM_DBG_DISALLOW_MULTIPLE_LP |
3614 WM_DBG_DISALLOW_SPRITE |
3615 WM_DBG_DISALLOW_MAXFIFO);
3616
17a303ec 3617 lpt_init_clock_gating(dev);
cad2a2d7
ED		 3618}
3619
1fa61106 3620static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3621{
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 int pipe;
20848223 3624 uint32_t snpcr;
6f1d69b0 3625
6f1d69b0
ED		 3626 I915_WRITE(WM3_LP_ILK, 0);
3627 I915_WRITE(WM2_LP_ILK, 0);
3628 I915_WRITE(WM1_LP_ILK, 0);
3629
231e54f6 3630 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3631
87f8020e
JB		 3632 /* WaDisableEarlyCull */
3633 I915_WRITE(_3D_CHICKEN3,
3634 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3635
62cb944f 3636 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3637 I915_WRITE(IVB_CHICKEN3,
3638 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3639 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3640
12f3382b
JB		 3641 /* WaDisablePSDDualDispatchEnable */
3642 if (IS_IVB_GT1(dev))
3643 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3644 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3645 else
3646 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3647 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3648
6f1d69b0
ED		 3649 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3650 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3651 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3652
3653 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3654 I915_WRITE(GEN7_L3CNTLREG1,
3655 GEN7_WA_FOR_GEN7_L3_CONTROL);
3656 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 3657 GEN7_WA_L3_CHICKEN_MODE);
3658 if (IS_IVB_GT1(dev))
3659 I915_WRITE(GEN7_ROW_CHICKEN2,
3660 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3661 else
3662 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3663 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3664
6f1d69b0 3665
61939d97
JB		 3666 /* WaForceL3Serialization */
3667 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3668 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3669
0f846f81
JB		 3670 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3671 * gating disable must be set. Failure to set it results in
3672 * flickering pixels due to Z write ordering failures after
3673 * some amount of runtime in the Mesa "fire" demo, and Unigine
3674 * Sanctuary and Tropics, and apparently anything else with
3675 * alpha test or pixel discard.
3676 *
3677 * According to the spec, bit 11 (RCCUNIT) must also be set,
3678 * but we didn't debug actual testcases to find it out.
3679 *
3680 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3681 * This implements the WaDisableRCZUnitClockGating workaround.
3682 */
3683 I915_WRITE(GEN6_UCGCTL2,
3684 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3685 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3686
6f1d69b0
ED		 3687 /* This is required by WaCatErrorRejectionIssue */
3688 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3689 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3690 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3691
3692 for_each_pipe(pipe) {
3693 I915_WRITE(DSPCNTR(pipe),
3694 I915_READ(DSPCNTR(pipe)) |
3695 DISPPLANE_TRICKLE_FEED_DISABLE);
3696 intel_flush_display_plane(dev_priv, pipe);
3697 }
3698
b4ae3f22
JB		 3699 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3700 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3701
6f1d69b0 3702 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f
DV		 3703
3704 /* WaDisable4x2SubspanOptimization */
3705 I915_WRITE(CACHE_MODE_1,
3706 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 3707
3708 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3709 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3710 snpcr |= GEN6_MBC_SNPCR_MED;
3711 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48
DV		 3712
3713 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3714}
3715
1fa61106 3716static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3717{
3718 struct drm_i915_private *dev_priv = dev->dev_private;
3719 int pipe;
6f1d69b0
ED		 3720
3721 I915_WRITE(WM3_LP_ILK, 0);
3722 I915_WRITE(WM2_LP_ILK, 0);
3723 I915_WRITE(WM1_LP_ILK, 0);
3724
231e54f6 3725 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3726
87f8020e
JB		 3727 /* WaDisableEarlyCull */
3728 I915_WRITE(_3D_CHICKEN3,
3729 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3730
62cb944f 3731 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3732 I915_WRITE(IVB_CHICKEN3,
3733 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3734 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3735
12f3382b
JB		 3736 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3737 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3738
6f1d69b0
ED		 3739 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3740 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3741 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3742
3743 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
d0cf5ead 3744 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 3745 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3746
61939d97
JB		 3747 /* WaForceL3Serialization */
3748 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3749 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3750
8ab43976
JB		 3751 /* WaDisableDopClockGating */
3752 I915_WRITE(GEN7_ROW_CHICKEN2,
3753 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3754
5c9664d7
JB		 3755 /* WaForceL3Serialization */
3756 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3757 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3758
6f1d69b0
ED		 3759 /* This is required by WaCatErrorRejectionIssue */
3760 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3761 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3762 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3763
b4ae3f22
JB		 3764 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3765 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3766
0f846f81
JB		 3767
3768 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3769 * gating disable must be set. Failure to set it results in
3770 * flickering pixels due to Z write ordering failures after
3771 * some amount of runtime in the Mesa "fire" demo, and Unigine
3772 * Sanctuary and Tropics, and apparently anything else with
3773 * alpha test or pixel discard.
3774 *
3775 * According to the spec, bit 11 (RCCUNIT) must also be set,
3776 * but we didn't debug actual testcases to find it out.
3777 *
3778 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3779 * This implements the WaDisableRCZUnitClockGating workaround.
3780 *
3781 * Also apply WaDisableVDSUnitClockGating and
3782 * WaDisableRCPBUnitClockGating.
3783 */
3784 I915_WRITE(GEN6_UCGCTL2,
3785 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 3786 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 3787 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3788 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3789 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3790
e3f33d46
JB		 3791 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3792
6f1d69b0
ED		 3793 for_each_pipe(pipe) {
3794 I915_WRITE(DSPCNTR(pipe),
3795 I915_READ(DSPCNTR(pipe)) |
3796 DISPPLANE_TRICKLE_FEED_DISABLE);
3797 intel_flush_display_plane(dev_priv, pipe);
3798 }
3799
6b26c86d
DV		 3800 I915_WRITE(CACHE_MODE_1,
3801 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f
JB		 3802
3803 /*
3804 * On ValleyView, the GUnit needs to signal the GT
3805 * when flip and other events complete. So enable
3806 * all the GUnit->GT interrupts here
3807 */
3808 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3809 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3810 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3811 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3812 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3813 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3814 PLANEA_FLIPDONE_INT_EN);
2d809570
JB		 3815
3816 /*
3817 * WaDisableVLVClockGating_VBIIssue
3818 * Disable clock gating on th GCFG unit to prevent a delay
3819 * in the reporting of vblank events.
3820 */
3821 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 3822}
3823
1fa61106 3824static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3825{
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 uint32_t dspclk_gate;
3828
3829 I915_WRITE(RENCLK_GATE_D1, 0);
3830 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3831 GS_UNIT_CLOCK_GATE_DISABLE |
3832 CL_UNIT_CLOCK_GATE_DISABLE);
3833 I915_WRITE(RAMCLK_GATE_D, 0);
3834 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3835 OVRUNIT_CLOCK_GATE_DISABLE |
3836 OVCUNIT_CLOCK_GATE_DISABLE;
3837 if (IS_GM45(dev))
3838 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3839 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 3840
3841 /* WaDisableRenderCachePipelinedFlush */
3842 I915_WRITE(CACHE_MODE_0,
3843 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 3844}
3845
1fa61106 3846static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3847{
3848 struct drm_i915_private *dev_priv = dev->dev_private;
3849
3850 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3851 I915_WRITE(RENCLK_GATE_D2, 0);
3852 I915_WRITE(DSPCLK_GATE_D, 0);
3853 I915_WRITE(RAMCLK_GATE_D, 0);
3854 I915_WRITE16(DEUC, 0);
3855}
3856
1fa61106 3857static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3858{
3859 struct drm_i915_private *dev_priv = dev->dev_private;
3860
3861 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
3862 I965_RCC_CLOCK_GATE_DISABLE |
3863 I965_RCPB_CLOCK_GATE_DISABLE |
3864 I965_ISC_CLOCK_GATE_DISABLE |
3865 I965_FBC_CLOCK_GATE_DISABLE);
3866 I915_WRITE(RENCLK_GATE_D2, 0);
3867}
3868
1fa61106 3869static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3870{
3871 struct drm_i915_private *dev_priv = dev->dev_private;
3872 u32 dstate = I915_READ(D_STATE);
3873
3874 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
3875 DSTATE_DOT_CLOCK_GATING;
3876 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 3877
3878 if (IS_PINEVIEW(dev))
3879 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 3880
3881 /* IIR "flip pending" means done if this bit is set */
3882 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 3883}
3884
1fa61106 3885static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3886{
3887 struct drm_i915_private *dev_priv = dev->dev_private;
3888
3889 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
3890}
3891
1fa61106 3892static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3893{
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895
3896 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
3897}
3898
6f1d69b0
ED		 3899void intel_init_clock_gating(struct drm_device *dev)
3900{
3901 struct drm_i915_private *dev_priv = dev->dev_private;
3902
3903 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 3904}
3905
d0d3e513
ED		 3906/* Starting with Haswell, we have different power wells for
3907 * different parts of the GPU. This attempts to enable them all.
3908 */
3909void intel_init_power_wells(struct drm_device *dev)
3910{
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3912 unsigned long power_wells[] = {
3913 HSW_PWR_WELL_CTL1,
3914 HSW_PWR_WELL_CTL2,
3915 HSW_PWR_WELL_CTL4
3916 };
3917 int i;
3918
3919 if (!IS_HASWELL(dev))
3920 return;
3921
3922 mutex_lock(&dev->struct_mutex);
3923
3924 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
3925 int well = I915_READ(power_wells[i]);
3926
3927 if ((well & HSW_PWR_WELL_STATE) == 0) {
3928 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
263b30d4 3929 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
d0d3e513
ED		 3930 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
3931 }
3932 }
3933
3934 mutex_unlock(&dev->struct_mutex);
3935}
3936
1fa61106
ED		 3937/* Set up chip specific power management-related functions */
3938void intel_init_pm(struct drm_device *dev)
3939{
3940 struct drm_i915_private *dev_priv = dev->dev_private;
3941
3942 if (I915_HAS_FBC(dev)) {
3943 if (HAS_PCH_SPLIT(dev)) {
3944 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
3945 dev_priv->display.enable_fbc = ironlake_enable_fbc;
3946 dev_priv->display.disable_fbc = ironlake_disable_fbc;
3947 } else if (IS_GM45(dev)) {
3948 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
3949 dev_priv->display.enable_fbc = g4x_enable_fbc;
3950 dev_priv->display.disable_fbc = g4x_disable_fbc;
3951 } else if (IS_CRESTLINE(dev)) {
3952 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
3953 dev_priv->display.enable_fbc = i8xx_enable_fbc;
3954 dev_priv->display.disable_fbc = i8xx_disable_fbc;
3955 }
3956 /* 855GM needs testing */
3957 }
3958
c921aba8
DV		 3959 /* For cxsr */
3960 if (IS_PINEVIEW(dev))
3961 i915_pineview_get_mem_freq(dev);
3962 else if (IS_GEN5(dev))
3963 i915_ironlake_get_mem_freq(dev);
3964
1fa61106
ED		 3965 /* For FIFO watermark updates */
3966 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 3967 if (IS_GEN5(dev)) {
3968 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
3969 dev_priv->display.update_wm = ironlake_update_wm;
3970 else {
3971 DRM_DEBUG_KMS("Failed to get proper latency. "
3972 "Disable CxSR\n");
3973 dev_priv->display.update_wm = NULL;
3974 }
3975 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
3976 } else if (IS_GEN6(dev)) {
3977 if (SNB_READ_WM0_LATENCY()) {
3978 dev_priv->display.update_wm = sandybridge_update_wm;
3979 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3980 } else {
3981 DRM_DEBUG_KMS("Failed to read display plane latency. "
3982 "Disable CxSR\n");
3983 dev_priv->display.update_wm = NULL;
3984 }
3985 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
3986 } else if (IS_IVYBRIDGE(dev)) {
3987 /* FIXME: detect B0+ stepping and use auto training */
3988 if (SNB_READ_WM0_LATENCY()) {
3989 dev_priv->display.update_wm = sandybridge_update_wm;
3990 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
3991 } else {
3992 DRM_DEBUG_KMS("Failed to read display plane latency. "
3993 "Disable CxSR\n");
3994 dev_priv->display.update_wm = NULL;
3995 }
3996 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb
ED		 3997 } else if (IS_HASWELL(dev)) {
3998 if (SNB_READ_WM0_LATENCY()) {
3999 dev_priv->display.update_wm = sandybridge_update_wm;
4000 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 4001 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 4002 } else {
4003 DRM_DEBUG_KMS("Failed to read display plane latency. "
4004 "Disable CxSR\n");
4005 dev_priv->display.update_wm = NULL;
4006 }
cad2a2d7 4007 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 4008 } else
4009 dev_priv->display.update_wm = NULL;
4010 } else if (IS_VALLEYVIEW(dev)) {
4011 dev_priv->display.update_wm = valleyview_update_wm;
4012 dev_priv->display.init_clock_gating =
4013 valleyview_init_clock_gating;
1fa61106
ED		 4014 } else if (IS_PINEVIEW(dev)) {
4015 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4016 dev_priv->is_ddr3,
4017 dev_priv->fsb_freq,
4018 dev_priv->mem_freq)) {
4019 DRM_INFO("failed to find known CxSR latency "
4020 "(found ddr%s fsb freq %d, mem freq %d), "
4021 "disabling CxSR\n",
4022 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4023 dev_priv->fsb_freq, dev_priv->mem_freq);
4024 /* Disable CxSR and never update its watermark again */
4025 pineview_disable_cxsr(dev);
4026 dev_priv->display.update_wm = NULL;
4027 } else
4028 dev_priv->display.update_wm = pineview_update_wm;
4029 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4030 } else if (IS_G4X(dev)) {
4031 dev_priv->display.update_wm = g4x_update_wm;
4032 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4033 } else if (IS_GEN4(dev)) {
4034 dev_priv->display.update_wm = i965_update_wm;
4035 if (IS_CRESTLINE(dev))
4036 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4037 else if (IS_BROADWATER(dev))
4038 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4039 } else if (IS_GEN3(dev)) {
4040 dev_priv->display.update_wm = i9xx_update_wm;
4041 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4042 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4043 } else if (IS_I865G(dev)) {
4044 dev_priv->display.update_wm = i830_update_wm;
4045 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4046 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4047 } else if (IS_I85X(dev)) {
4048 dev_priv->display.update_wm = i9xx_update_wm;
4049 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4050 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4051 } else {
4052 dev_priv->display.update_wm = i830_update_wm;
4053 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4054 if (IS_845G(dev))
4055 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4056 else
4057 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4058 }
4059}
4060
6590190d
ED		 4061static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4062{
4063 u32 gt_thread_status_mask;
4064
4065 if (IS_HASWELL(dev_priv->dev))
4066 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4067 else
4068 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4069
4070 /* w/a for a sporadic read returning 0 by waiting for the GT
4071 * thread to wake up.
4072 */
4073 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4074 DRM_ERROR("GT thread status wait timed out\n");
4075}
4076
16995a9f
CW		 4077static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4078{
4079 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4080 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4081}
4082
6590190d
ED		 4083static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4084{
4085 u32 forcewake_ack;
4086
4087 if (IS_HASWELL(dev_priv->dev))
4088 forcewake_ack = FORCEWAKE_ACK_HSW;
4089 else
4090 forcewake_ack = FORCEWAKE_ACK;
4091
057d3860
BW		 4092 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4093 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4094 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4095
c5836c27 4096 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
8dee3eea 4097 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4098
057d3860
BW		 4099 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4100 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4101 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4102
4103 __gen6_gt_wait_for_thread_c0(dev_priv);
4104}
4105
16995a9f
CW		 4106static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4107{
4108 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4109 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4110}
4111
6590190d
ED		 4112static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4113{
4114 u32 forcewake_ack;
4115
4116 if (IS_HASWELL(dev_priv->dev))
4117 forcewake_ack = FORCEWAKE_ACK_HSW;
4118 else
4119 forcewake_ack = FORCEWAKE_MT_ACK;
4120
057d3860
BW		 4121 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4122 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4123 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4124
c5836c27 4125 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
8dee3eea 4126 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4127
057d3860
BW		 4128 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4129 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4130 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4131
4132 __gen6_gt_wait_for_thread_c0(dev_priv);
4133}
4134
4135/*
4136 * Generally this is called implicitly by the register read function. However,
4137 * if some sequence requires the GT to not power down then this function should
4138 * be called at the beginning of the sequence followed by a call to
4139 * gen6_gt_force_wake_put() at the end of the sequence.
4140 */
4141void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4142{
4143 unsigned long irqflags;
4144
4145 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4146 if (dev_priv->forcewake_count++ == 0)
4147 dev_priv->gt.force_wake_get(dev_priv);
4148 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4149}
4150
4151void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4152{
4153 u32 gtfifodbg;
4154 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4155 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4156 "MMIO read or write has been dropped %x\n", gtfifodbg))
4157 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4158}
4159
4160static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4161{
4162 I915_WRITE_NOTRACE(FORCEWAKE, 0);
8dee3eea 4163 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4164 gen6_gt_check_fifodbg(dev_priv);
4165}
4166
4167static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4168{
c5836c27 4169 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
8dee3eea 4170 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4171 gen6_gt_check_fifodbg(dev_priv);
4172}
4173
4174/*
4175 * see gen6_gt_force_wake_get()
4176 */
4177void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4178{
4179 unsigned long irqflags;
4180
4181 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4182 if (--dev_priv->forcewake_count == 0)
4183 dev_priv->gt.force_wake_put(dev_priv);
4184 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4185}
4186
4187int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4188{
4189 int ret = 0;
4190
4191 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4192 int loop = 500;
4193 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4194 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4195 udelay(10);
4196 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4197 }
4198 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4199 ++ret;
4200 dev_priv->gt_fifo_count = fifo;
4201 }
4202 dev_priv->gt_fifo_count--;
4203
4204 return ret;
4205}
4206
16995a9f
CW		 4207static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4208{
4209 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4210}
4211
6590190d
ED		 4212static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4213{
057d3860
BW		 4214 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4215 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4216 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4217
c5836c27 4218 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 4219
057d3860
BW		 4220 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4221 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4222 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4223
4224 __gen6_gt_wait_for_thread_c0(dev_priv);
4225}
4226
4227static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4228{
c5836c27 4229 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5ab140a4
DV		 4230 /* The below doubles as a POSTING_READ */
4231 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 4232}
4233
16995a9f
CW		 4234void intel_gt_reset(struct drm_device *dev)
4235{
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237
4238 if (IS_VALLEYVIEW(dev)) {
4239 vlv_force_wake_reset(dev_priv);
4240 } else if (INTEL_INFO(dev)->gen >= 6) {
4241 __gen6_gt_force_wake_reset(dev_priv);
4242 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4243 __gen6_gt_force_wake_mt_reset(dev_priv);
4244 }
4245}
4246
6590190d
ED		 4247void intel_gt_init(struct drm_device *dev)
4248{
4249 struct drm_i915_private *dev_priv = dev->dev_private;
4250
4251 spin_lock_init(&dev_priv->gt_lock);
4252
16995a9f
CW		 4253 intel_gt_reset(dev);
4254
6590190d
ED		 4255 if (IS_VALLEYVIEW(dev)) {
4256 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4257 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 4258 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4259 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4260 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4261 } else if (IS_GEN6(dev)) {
6590190d
ED		 4262 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4263 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 4264 }
1a01ab3b
JB		 4265 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4266 intel_gen6_powersave_work);
6590190d
ED		 4267}
4268
42c0526c
BW		 4269int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4270{
4fc688ce 4271 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4272
4273 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4274 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4275 return -EAGAIN;
4276 }
4277
4278 I915_WRITE(GEN6_PCODE_DATA, *val);
4279 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4280
4281 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4282 500)) {
4283 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4284 return -ETIMEDOUT;
4285 }
4286
4287 *val = I915_READ(GEN6_PCODE_DATA);
4288 I915_WRITE(GEN6_PCODE_DATA, 0);
4289
4290 return 0;
4291}
4292
4293int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4294{
4fc688ce 4295 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4296
4297 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4298 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4299 return -EAGAIN;
4300 }
4301
4302 I915_WRITE(GEN6_PCODE_DATA, val);
4303 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4304
4305 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4306 500)) {
4307 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4308 return -ETIMEDOUT;
4309 }
4310
4311 I915_WRITE(GEN6_PCODE_DATA, 0);
4312
4313 return 0;
4314}
Motorola kernel-slsi