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drm/i915: Invalidate the relocation presumed_offsets along the slow path
[GitHub/MotorolaMobilityLLC/kernel-slsi.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
3490ea5d
CW		 47static bool intel_crtc_active(struct drm_crtc *crtc)
48{
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53}
54
1fa61106 55static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 56{
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75}
76
1fa61106 77static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 78{
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
117 cfb_pitch, crtc->y, intel_crtc->plane);
118}
119
1fa61106 120static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125}
126
1fa61106 127static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 128{
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
151 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
152}
153
1fa61106 154static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 155{
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167}
168
1fa61106 169static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 170{
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174}
175
176static void sandybridge_blit_fbc_update(struct drm_device *dev)
177{
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194}
195
1fa61106 196static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 197{
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
231 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
232}
233
1fa61106 234static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 235{
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
245 DRM_DEBUG_KMS("disabled FBC\n");
246 }
247}
248
1fa61106 249static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 250{
251 struct drm_i915_private *dev_priv = dev->dev_private;
252
253 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
254}
255
256bool intel_fbc_enabled(struct drm_device *dev)
257{
258 struct drm_i915_private *dev_priv = dev->dev_private;
259
260 if (!dev_priv->display.fbc_enabled)
261 return false;
262
263 return dev_priv->display.fbc_enabled(dev);
264}
265
266static void intel_fbc_work_fn(struct work_struct *__work)
267{
268 struct intel_fbc_work *work =
269 container_of(to_delayed_work(__work),
270 struct intel_fbc_work, work);
271 struct drm_device *dev = work->crtc->dev;
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 mutex_lock(&dev->struct_mutex);
275 if (work == dev_priv->fbc_work) {
276 /* Double check that we haven't switched fb without cancelling
277 * the prior work.
278 */
279 if (work->crtc->fb == work->fb) {
280 dev_priv->display.enable_fbc(work->crtc,
281 work->interval);
282
283 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
284 dev_priv->cfb_fb = work->crtc->fb->base.id;
285 dev_priv->cfb_y = work->crtc->y;
286 }
287
288 dev_priv->fbc_work = NULL;
289 }
290 mutex_unlock(&dev->struct_mutex);
291
292 kfree(work);
293}
294
295static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
296{
297 if (dev_priv->fbc_work == NULL)
298 return;
299
300 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
301
302 /* Synchronisation is provided by struct_mutex and checking of
303 * dev_priv->fbc_work, so we can perform the cancellation
304 * entirely asynchronously.
305 */
306 if (cancel_delayed_work(&dev_priv->fbc_work->work))
307 /* tasklet was killed before being run, clean up */
308 kfree(dev_priv->fbc_work);
309
310 /* Mark the work as no longer wanted so that if it does
311 * wake-up (because the work was already running and waiting
312 * for our mutex), it will discover that is no longer
313 * necessary to run.
314 */
315 dev_priv->fbc_work = NULL;
316}
317
318void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
319{
320 struct intel_fbc_work *work;
321 struct drm_device *dev = crtc->dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 if (!dev_priv->display.enable_fbc)
325 return;
326
327 intel_cancel_fbc_work(dev_priv);
328
329 work = kzalloc(sizeof *work, GFP_KERNEL);
330 if (work == NULL) {
331 dev_priv->display.enable_fbc(crtc, interval);
332 return;
333 }
334
335 work->crtc = crtc;
336 work->fb = crtc->fb;
337 work->interval = interval;
338 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
339
340 dev_priv->fbc_work = work;
341
342 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
343
344 /* Delay the actual enabling to let pageflipping cease and the
345 * display to settle before starting the compression. Note that
346 * this delay also serves a second purpose: it allows for a
347 * vblank to pass after disabling the FBC before we attempt
348 * to modify the control registers.
349 *
350 * A more complicated solution would involve tracking vblanks
351 * following the termination of the page-flipping sequence
352 * and indeed performing the enable as a co-routine and not
353 * waiting synchronously upon the vblank.
354 */
355 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
356}
357
358void intel_disable_fbc(struct drm_device *dev)
359{
360 struct drm_i915_private *dev_priv = dev->dev_private;
361
362 intel_cancel_fbc_work(dev_priv);
363
364 if (!dev_priv->display.disable_fbc)
365 return;
366
367 dev_priv->display.disable_fbc(dev);
368 dev_priv->cfb_plane = -1;
369}
370
371/**
372 * intel_update_fbc - enable/disable FBC as needed
373 * @dev: the drm_device
374 *
375 * Set up the framebuffer compression hardware at mode set time. We
376 * enable it if possible:
377 * - plane A only (on pre-965)
378 * - no pixel mulitply/line duplication
379 * - no alpha buffer discard
380 * - no dual wide
381 * - framebuffer <= 2048 in width, 1536 in height
382 *
383 * We can't assume that any compression will take place (worst case),
384 * so the compressed buffer has to be the same size as the uncompressed
385 * one. It also must reside (along with the line length buffer) in
386 * stolen memory.
387 *
388 * We need to enable/disable FBC on a global basis.
389 */
390void intel_update_fbc(struct drm_device *dev)
391{
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 struct drm_crtc *crtc = NULL, *tmp_crtc;
394 struct intel_crtc *intel_crtc;
395 struct drm_framebuffer *fb;
396 struct intel_framebuffer *intel_fb;
397 struct drm_i915_gem_object *obj;
398 int enable_fbc;
399
85208be0
ED		 400 if (!i915_powersave)
401 return;
402
403 if (!I915_HAS_FBC(dev))
404 return;
405
406 /*
407 * If FBC is already on, we just have to verify that we can
408 * keep it that way...
409 * Need to disable if:
410 * - more than one pipe is active
411 * - changing FBC params (stride, fence, mode)
412 * - new fb is too large to fit in compressed buffer
413 * - going to an unsupported config (interlace, pixel multiply, etc.)
414 */
415 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 416 if (intel_crtc_active(tmp_crtc) &&
417 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 418 if (crtc) {
419 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
420 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
421 goto out_disable;
422 }
423 crtc = tmp_crtc;
424 }
425 }
426
427 if (!crtc || crtc->fb == NULL) {
428 DRM_DEBUG_KMS("no output, disabling\n");
429 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
430 goto out_disable;
431 }
432
433 intel_crtc = to_intel_crtc(crtc);
434 fb = crtc->fb;
435 intel_fb = to_intel_framebuffer(fb);
436 obj = intel_fb->obj;
437
438 enable_fbc = i915_enable_fbc;
439 if (enable_fbc < 0) {
440 DRM_DEBUG_KMS("fbc set to per-chip default\n");
441 enable_fbc = 1;
442 if (INTEL_INFO(dev)->gen <= 6)
443 enable_fbc = 0;
444 }
445 if (!enable_fbc) {
446 DRM_DEBUG_KMS("fbc disabled per module param\n");
447 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
448 goto out_disable;
449 }
450 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
451 DRM_DEBUG_KMS("framebuffer too large, disabling "
452 "compression\n");
453 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
454 goto out_disable;
455 }
456 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
457 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
458 DRM_DEBUG_KMS("mode incompatible with compression, "
459 "disabling\n");
460 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
461 goto out_disable;
462 }
463 if ((crtc->mode.hdisplay > 2048) ||
464 (crtc->mode.vdisplay > 1536)) {
465 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
466 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
467 goto out_disable;
468 }
469 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
470 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
471 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
472 goto out_disable;
473 }
474
475 /* The use of a CPU fence is mandatory in order to detect writes
476 * by the CPU to the scanout and trigger updates to the FBC.
477 */
478 if (obj->tiling_mode != I915_TILING_X ||
479 obj->fence_reg == I915_FENCE_REG_NONE) {
480 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
481 dev_priv->no_fbc_reason = FBC_NOT_TILED;
482 goto out_disable;
483 }
484
485 /* If the kernel debugger is active, always disable compression */
486 if (in_dbg_master())
487 goto out_disable;
488
489 /* If the scanout has not changed, don't modify the FBC settings.
490 * Note that we make the fundamental assumption that the fb->obj
491 * cannot be unpinned (and have its GTT offset and fence revoked)
492 * without first being decoupled from the scanout and FBC disabled.
493 */
494 if (dev_priv->cfb_plane == intel_crtc->plane &&
495 dev_priv->cfb_fb == fb->base.id &&
496 dev_priv->cfb_y == crtc->y)
497 return;
498
499 if (intel_fbc_enabled(dev)) {
500 /* We update FBC along two paths, after changing fb/crtc
501 * configuration (modeswitching) and after page-flipping
502 * finishes. For the latter, we know that not only did
503 * we disable the FBC at the start of the page-flip
504 * sequence, but also more than one vblank has passed.
505 *
506 * For the former case of modeswitching, it is possible
507 * to switch between two FBC valid configurations
508 * instantaneously so we do need to disable the FBC
509 * before we can modify its control registers. We also
510 * have to wait for the next vblank for that to take
511 * effect. However, since we delay enabling FBC we can
512 * assume that a vblank has passed since disabling and
513 * that we can safely alter the registers in the deferred
514 * callback.
515 *
516 * In the scenario that we go from a valid to invalid
517 * and then back to valid FBC configuration we have
518 * no strict enforcement that a vblank occurred since
519 * disabling the FBC. However, along all current pipe
520 * disabling paths we do need to wait for a vblank at
521 * some point. And we wait before enabling FBC anyway.
522 */
523 DRM_DEBUG_KMS("disabling active FBC for update\n");
524 intel_disable_fbc(dev);
525 }
526
527 intel_enable_fbc(crtc, 500);
528 return;
529
530out_disable:
531 /* Multiple disables should be harmless */
532 if (intel_fbc_enabled(dev)) {
533 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
534 intel_disable_fbc(dev);
535 }
536}
537
c921aba8
DV		 538static void i915_pineview_get_mem_freq(struct drm_device *dev)
539{
540 drm_i915_private_t *dev_priv = dev->dev_private;
541 u32 tmp;
542
543 tmp = I915_READ(CLKCFG);
544
545 switch (tmp & CLKCFG_FSB_MASK) {
546 case CLKCFG_FSB_533:
547 dev_priv->fsb_freq = 533; /* 133*4 */
548 break;
549 case CLKCFG_FSB_800:
550 dev_priv->fsb_freq = 800; /* 200*4 */
551 break;
552 case CLKCFG_FSB_667:
553 dev_priv->fsb_freq = 667; /* 167*4 */
554 break;
555 case CLKCFG_FSB_400:
556 dev_priv->fsb_freq = 400; /* 100*4 */
557 break;
558 }
559
560 switch (tmp & CLKCFG_MEM_MASK) {
561 case CLKCFG_MEM_533:
562 dev_priv->mem_freq = 533;
563 break;
564 case CLKCFG_MEM_667:
565 dev_priv->mem_freq = 667;
566 break;
567 case CLKCFG_MEM_800:
568 dev_priv->mem_freq = 800;
569 break;
570 }
571
572 /* detect pineview DDR3 setting */
573 tmp = I915_READ(CSHRDDR3CTL);
574 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
575}
576
577static void i915_ironlake_get_mem_freq(struct drm_device *dev)
578{
579 drm_i915_private_t *dev_priv = dev->dev_private;
580 u16 ddrpll, csipll;
581
582 ddrpll = I915_READ16(DDRMPLL1);
583 csipll = I915_READ16(CSIPLL0);
584
585 switch (ddrpll & 0xff) {
586 case 0xc:
587 dev_priv->mem_freq = 800;
588 break;
589 case 0x10:
590 dev_priv->mem_freq = 1066;
591 break;
592 case 0x14:
593 dev_priv->mem_freq = 1333;
594 break;
595 case 0x18:
596 dev_priv->mem_freq = 1600;
597 break;
598 default:
599 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
600 ddrpll & 0xff);
601 dev_priv->mem_freq = 0;
602 break;
603 }
604
20e4d407 605 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 606
607 switch (csipll & 0x3ff) {
608 case 0x00c:
609 dev_priv->fsb_freq = 3200;
610 break;
611 case 0x00e:
612 dev_priv->fsb_freq = 3733;
613 break;
614 case 0x010:
615 dev_priv->fsb_freq = 4266;
616 break;
617 case 0x012:
618 dev_priv->fsb_freq = 4800;
619 break;
620 case 0x014:
621 dev_priv->fsb_freq = 5333;
622 break;
623 case 0x016:
624 dev_priv->fsb_freq = 5866;
625 break;
626 case 0x018:
627 dev_priv->fsb_freq = 6400;
628 break;
629 default:
630 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
631 csipll & 0x3ff);
632 dev_priv->fsb_freq = 0;
633 break;
634 }
635
636 if (dev_priv->fsb_freq == 3200) {
20e4d407 637 dev_priv->ips.c_m = 0;
c921aba8 638 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 639 dev_priv->ips.c_m = 1;
c921aba8 640 } else {
20e4d407 641 dev_priv->ips.c_m = 2;
c921aba8
DV		 642 }
643}
644
b445e3b0
ED		 645static const struct cxsr_latency cxsr_latency_table[] = {
646 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
647 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
648 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
649 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
650 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
651
652 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
653 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
654 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
655 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
656 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
657
658 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
659 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
660 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
661 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
662 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
663
664 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
665 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
666 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
667 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
668 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
669
670 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
671 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
672 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
673 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
674 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
675
676 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
677 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
678 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
679 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
680 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
681};
682
63c62275 683static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 684 int is_ddr3,
685 int fsb,
686 int mem)
687{
688 const struct cxsr_latency *latency;
689 int i;
690
691 if (fsb == 0 || mem == 0)
692 return NULL;
693
694 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
695 latency = &cxsr_latency_table[i];
696 if (is_desktop == latency->is_desktop &&
697 is_ddr3 == latency->is_ddr3 &&
698 fsb == latency->fsb_freq && mem == latency->mem_freq)
699 return latency;
700 }
701
702 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
703
704 return NULL;
705}
706
1fa61106 707static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 708{
709 struct drm_i915_private *dev_priv = dev->dev_private;
710
711 /* deactivate cxsr */
712 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
713}
714
715/*
716 * Latency for FIFO fetches is dependent on several factors:
717 * - memory configuration (speed, channels)
718 * - chipset
719 * - current MCH state
720 * It can be fairly high in some situations, so here we assume a fairly
721 * pessimal value. It's a tradeoff between extra memory fetches (if we
722 * set this value too high, the FIFO will fetch frequently to stay full)
723 * and power consumption (set it too low to save power and we might see
724 * FIFO underruns and display "flicker").
725 *
726 * A value of 5us seems to be a good balance; safe for very low end
727 * platforms but not overly aggressive on lower latency configs.
728 */
729static const int latency_ns = 5000;
730
1fa61106 731static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 732{
733 struct drm_i915_private *dev_priv = dev->dev_private;
734 uint32_t dsparb = I915_READ(DSPARB);
735 int size;
736
737 size = dsparb & 0x7f;
738 if (plane)
739 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
740
741 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
742 plane ? "B" : "A", size);
743
744 return size;
745}
746
1fa61106 747static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
750 uint32_t dsparb = I915_READ(DSPARB);
751 int size;
752
753 size = dsparb & 0x1ff;
754 if (plane)
755 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
756 size >>= 1; /* Convert to cachelines */
757
758 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
759 plane ? "B" : "A", size);
760
761 return size;
762}
763
1fa61106 764static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 765{
766 struct drm_i915_private *dev_priv = dev->dev_private;
767 uint32_t dsparb = I915_READ(DSPARB);
768 int size;
769
770 size = dsparb & 0x7f;
771 size >>= 2; /* Convert to cachelines */
772
773 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
774 plane ? "B" : "A",
775 size);
776
777 return size;
778}
779
1fa61106 780static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 781{
782 struct drm_i915_private *dev_priv = dev->dev_private;
783 uint32_t dsparb = I915_READ(DSPARB);
784 int size;
785
786 size = dsparb & 0x7f;
787 size >>= 1; /* Convert to cachelines */
788
789 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
790 plane ? "B" : "A", size);
791
792 return size;
793}
794
795/* Pineview has different values for various configs */
796static const struct intel_watermark_params pineview_display_wm = {
797 PINEVIEW_DISPLAY_FIFO,
798 PINEVIEW_MAX_WM,
799 PINEVIEW_DFT_WM,
800 PINEVIEW_GUARD_WM,
801 PINEVIEW_FIFO_LINE_SIZE
802};
803static const struct intel_watermark_params pineview_display_hplloff_wm = {
804 PINEVIEW_DISPLAY_FIFO,
805 PINEVIEW_MAX_WM,
806 PINEVIEW_DFT_HPLLOFF_WM,
807 PINEVIEW_GUARD_WM,
808 PINEVIEW_FIFO_LINE_SIZE
809};
810static const struct intel_watermark_params pineview_cursor_wm = {
811 PINEVIEW_CURSOR_FIFO,
812 PINEVIEW_CURSOR_MAX_WM,
813 PINEVIEW_CURSOR_DFT_WM,
814 PINEVIEW_CURSOR_GUARD_WM,
815 PINEVIEW_FIFO_LINE_SIZE,
816};
817static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
818 PINEVIEW_CURSOR_FIFO,
819 PINEVIEW_CURSOR_MAX_WM,
820 PINEVIEW_CURSOR_DFT_WM,
821 PINEVIEW_CURSOR_GUARD_WM,
822 PINEVIEW_FIFO_LINE_SIZE
823};
824static const struct intel_watermark_params g4x_wm_info = {
825 G4X_FIFO_SIZE,
826 G4X_MAX_WM,
827 G4X_MAX_WM,
828 2,
829 G4X_FIFO_LINE_SIZE,
830};
831static const struct intel_watermark_params g4x_cursor_wm_info = {
832 I965_CURSOR_FIFO,
833 I965_CURSOR_MAX_WM,
834 I965_CURSOR_DFT_WM,
835 2,
836 G4X_FIFO_LINE_SIZE,
837};
838static const struct intel_watermark_params valleyview_wm_info = {
839 VALLEYVIEW_FIFO_SIZE,
840 VALLEYVIEW_MAX_WM,
841 VALLEYVIEW_MAX_WM,
842 2,
843 G4X_FIFO_LINE_SIZE,
844};
845static const struct intel_watermark_params valleyview_cursor_wm_info = {
846 I965_CURSOR_FIFO,
847 VALLEYVIEW_CURSOR_MAX_WM,
848 I965_CURSOR_DFT_WM,
849 2,
850 G4X_FIFO_LINE_SIZE,
851};
852static const struct intel_watermark_params i965_cursor_wm_info = {
853 I965_CURSOR_FIFO,
854 I965_CURSOR_MAX_WM,
855 I965_CURSOR_DFT_WM,
856 2,
857 I915_FIFO_LINE_SIZE,
858};
859static const struct intel_watermark_params i945_wm_info = {
860 I945_FIFO_SIZE,
861 I915_MAX_WM,
862 1,
863 2,
864 I915_FIFO_LINE_SIZE
865};
866static const struct intel_watermark_params i915_wm_info = {
867 I915_FIFO_SIZE,
868 I915_MAX_WM,
869 1,
870 2,
871 I915_FIFO_LINE_SIZE
872};
873static const struct intel_watermark_params i855_wm_info = {
874 I855GM_FIFO_SIZE,
875 I915_MAX_WM,
876 1,
877 2,
878 I830_FIFO_LINE_SIZE
879};
880static const struct intel_watermark_params i830_wm_info = {
881 I830_FIFO_SIZE,
882 I915_MAX_WM,
883 1,
884 2,
885 I830_FIFO_LINE_SIZE
886};
887
888static const struct intel_watermark_params ironlake_display_wm_info = {
889 ILK_DISPLAY_FIFO,
890 ILK_DISPLAY_MAXWM,
891 ILK_DISPLAY_DFTWM,
892 2,
893 ILK_FIFO_LINE_SIZE
894};
895static const struct intel_watermark_params ironlake_cursor_wm_info = {
896 ILK_CURSOR_FIFO,
897 ILK_CURSOR_MAXWM,
898 ILK_CURSOR_DFTWM,
899 2,
900 ILK_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params ironlake_display_srwm_info = {
903 ILK_DISPLAY_SR_FIFO,
904 ILK_DISPLAY_MAX_SRWM,
905 ILK_DISPLAY_DFT_SRWM,
906 2,
907 ILK_FIFO_LINE_SIZE
908};
909static const struct intel_watermark_params ironlake_cursor_srwm_info = {
910 ILK_CURSOR_SR_FIFO,
911 ILK_CURSOR_MAX_SRWM,
912 ILK_CURSOR_DFT_SRWM,
913 2,
914 ILK_FIFO_LINE_SIZE
915};
916
917static const struct intel_watermark_params sandybridge_display_wm_info = {
918 SNB_DISPLAY_FIFO,
919 SNB_DISPLAY_MAXWM,
920 SNB_DISPLAY_DFTWM,
921 2,
922 SNB_FIFO_LINE_SIZE
923};
924static const struct intel_watermark_params sandybridge_cursor_wm_info = {
925 SNB_CURSOR_FIFO,
926 SNB_CURSOR_MAXWM,
927 SNB_CURSOR_DFTWM,
928 2,
929 SNB_FIFO_LINE_SIZE
930};
931static const struct intel_watermark_params sandybridge_display_srwm_info = {
932 SNB_DISPLAY_SR_FIFO,
933 SNB_DISPLAY_MAX_SRWM,
934 SNB_DISPLAY_DFT_SRWM,
935 2,
936 SNB_FIFO_LINE_SIZE
937};
938static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
939 SNB_CURSOR_SR_FIFO,
940 SNB_CURSOR_MAX_SRWM,
941 SNB_CURSOR_DFT_SRWM,
942 2,
943 SNB_FIFO_LINE_SIZE
944};
945
946
947/**
948 * intel_calculate_wm - calculate watermark level
949 * @clock_in_khz: pixel clock
950 * @wm: chip FIFO params
951 * @pixel_size: display pixel size
952 * @latency_ns: memory latency for the platform
953 *
954 * Calculate the watermark level (the level at which the display plane will
955 * start fetching from memory again). Each chip has a different display
956 * FIFO size and allocation, so the caller needs to figure that out and pass
957 * in the correct intel_watermark_params structure.
958 *
959 * As the pixel clock runs, the FIFO will be drained at a rate that depends
960 * on the pixel size. When it reaches the watermark level, it'll start
961 * fetching FIFO line sized based chunks from memory until the FIFO fills
962 * past the watermark point. If the FIFO drains completely, a FIFO underrun
963 * will occur, and a display engine hang could result.
964 */
965static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
966 const struct intel_watermark_params *wm,
967 int fifo_size,
968 int pixel_size,
969 unsigned long latency_ns)
970{
971 long entries_required, wm_size;
972
973 /*
974 * Note: we need to make sure we don't overflow for various clock &
975 * latency values.
976 * clocks go from a few thousand to several hundred thousand.
977 * latency is usually a few thousand
978 */
979 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
980 1000;
981 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
982
983 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
984
985 wm_size = fifo_size - (entries_required + wm->guard_size);
986
987 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
988
989 /* Don't promote wm_size to unsigned... */
990 if (wm_size > (long)wm->max_wm)
991 wm_size = wm->max_wm;
992 if (wm_size <= 0)
993 wm_size = wm->default_wm;
994 return wm_size;
995}
996
997static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
998{
999 struct drm_crtc *crtc, *enabled = NULL;
1000
1001 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1002 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1003 if (enabled)
1004 return NULL;
1005 enabled = crtc;
1006 }
1007 }
1008
1009 return enabled;
1010}
1011
1fa61106 1012static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1013{
1014 struct drm_i915_private *dev_priv = dev->dev_private;
1015 struct drm_crtc *crtc;
1016 const struct cxsr_latency *latency;
1017 u32 reg;
1018 unsigned long wm;
1019
1020 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1021 dev_priv->fsb_freq, dev_priv->mem_freq);
1022 if (!latency) {
1023 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1024 pineview_disable_cxsr(dev);
1025 return;
1026 }
1027
1028 crtc = single_enabled_crtc(dev);
1029 if (crtc) {
1030 int clock = crtc->mode.clock;
1031 int pixel_size = crtc->fb->bits_per_pixel / 8;
1032
1033 /* Display SR */
1034 wm = intel_calculate_wm(clock, &pineview_display_wm,
1035 pineview_display_wm.fifo_size,
1036 pixel_size, latency->display_sr);
1037 reg = I915_READ(DSPFW1);
1038 reg &= ~DSPFW_SR_MASK;
1039 reg |= wm << DSPFW_SR_SHIFT;
1040 I915_WRITE(DSPFW1, reg);
1041 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1042
1043 /* cursor SR */
1044 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1045 pineview_display_wm.fifo_size,
1046 pixel_size, latency->cursor_sr);
1047 reg = I915_READ(DSPFW3);
1048 reg &= ~DSPFW_CURSOR_SR_MASK;
1049 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1050 I915_WRITE(DSPFW3, reg);
1051
1052 /* Display HPLL off SR */
1053 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1054 pineview_display_hplloff_wm.fifo_size,
1055 pixel_size, latency->display_hpll_disable);
1056 reg = I915_READ(DSPFW3);
1057 reg &= ~DSPFW_HPLL_SR_MASK;
1058 reg |= wm & DSPFW_HPLL_SR_MASK;
1059 I915_WRITE(DSPFW3, reg);
1060
1061 /* cursor HPLL off SR */
1062 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1063 pineview_display_hplloff_wm.fifo_size,
1064 pixel_size, latency->cursor_hpll_disable);
1065 reg = I915_READ(DSPFW3);
1066 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1067 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1068 I915_WRITE(DSPFW3, reg);
1069 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1070
1071 /* activate cxsr */
1072 I915_WRITE(DSPFW3,
1073 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1074 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1075 } else {
1076 pineview_disable_cxsr(dev);
1077 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1078 }
1079}
1080
1081static bool g4x_compute_wm0(struct drm_device *dev,
1082 int plane,
1083 const struct intel_watermark_params *display,
1084 int display_latency_ns,
1085 const struct intel_watermark_params *cursor,
1086 int cursor_latency_ns,
1087 int *plane_wm,
1088 int *cursor_wm)
1089{
1090 struct drm_crtc *crtc;
1091 int htotal, hdisplay, clock, pixel_size;
1092 int line_time_us, line_count;
1093 int entries, tlb_miss;
1094
1095 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1096 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1097 *cursor_wm = cursor->guard_size;
1098 *plane_wm = display->guard_size;
1099 return false;
1100 }
1101
1102 htotal = crtc->mode.htotal;
1103 hdisplay = crtc->mode.hdisplay;
1104 clock = crtc->mode.clock;
1105 pixel_size = crtc->fb->bits_per_pixel / 8;
1106
1107 /* Use the small buffer method to calculate plane watermark */
1108 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1109 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1110 if (tlb_miss > 0)
1111 entries += tlb_miss;
1112 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1113 *plane_wm = entries + display->guard_size;
1114 if (*plane_wm > (int)display->max_wm)
1115 *plane_wm = display->max_wm;
1116
1117 /* Use the large buffer method to calculate cursor watermark */
1118 line_time_us = ((htotal * 1000) / clock);
1119 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1120 entries = line_count * 64 * pixel_size;
1121 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1122 if (tlb_miss > 0)
1123 entries += tlb_miss;
1124 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1125 *cursor_wm = entries + cursor->guard_size;
1126 if (*cursor_wm > (int)cursor->max_wm)
1127 *cursor_wm = (int)cursor->max_wm;
1128
1129 return true;
1130}
1131
1132/*
1133 * Check the wm result.
1134 *
1135 * If any calculated watermark values is larger than the maximum value that
1136 * can be programmed into the associated watermark register, that watermark
1137 * must be disabled.
1138 */
1139static bool g4x_check_srwm(struct drm_device *dev,
1140 int display_wm, int cursor_wm,
1141 const struct intel_watermark_params *display,
1142 const struct intel_watermark_params *cursor)
1143{
1144 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1145 display_wm, cursor_wm);
1146
1147 if (display_wm > display->max_wm) {
1148 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1149 display_wm, display->max_wm);
1150 return false;
1151 }
1152
1153 if (cursor_wm > cursor->max_wm) {
1154 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1155 cursor_wm, cursor->max_wm);
1156 return false;
1157 }
1158
1159 if (!(display_wm || cursor_wm)) {
1160 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1161 return false;
1162 }
1163
1164 return true;
1165}
1166
1167static bool g4x_compute_srwm(struct drm_device *dev,
1168 int plane,
1169 int latency_ns,
1170 const struct intel_watermark_params *display,
1171 const struct intel_watermark_params *cursor,
1172 int *display_wm, int *cursor_wm)
1173{
1174 struct drm_crtc *crtc;
1175 int hdisplay, htotal, pixel_size, clock;
1176 unsigned long line_time_us;
1177 int line_count, line_size;
1178 int small, large;
1179 int entries;
1180
1181 if (!latency_ns) {
1182 *display_wm = *cursor_wm = 0;
1183 return false;
1184 }
1185
1186 crtc = intel_get_crtc_for_plane(dev, plane);
1187 hdisplay = crtc->mode.hdisplay;
1188 htotal = crtc->mode.htotal;
1189 clock = crtc->mode.clock;
1190 pixel_size = crtc->fb->bits_per_pixel / 8;
1191
1192 line_time_us = (htotal * 1000) / clock;
1193 line_count = (latency_ns / line_time_us + 1000) / 1000;
1194 line_size = hdisplay * pixel_size;
1195
1196 /* Use the minimum of the small and large buffer method for primary */
1197 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1198 large = line_count * line_size;
1199
1200 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1201 *display_wm = entries + display->guard_size;
1202
1203 /* calculate the self-refresh watermark for display cursor */
1204 entries = line_count * pixel_size * 64;
1205 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1206 *cursor_wm = entries + cursor->guard_size;
1207
1208 return g4x_check_srwm(dev,
1209 *display_wm, *cursor_wm,
1210 display, cursor);
1211}
1212
1213static bool vlv_compute_drain_latency(struct drm_device *dev,
1214 int plane,
1215 int *plane_prec_mult,
1216 int *plane_dl,
1217 int *cursor_prec_mult,
1218 int *cursor_dl)
1219{
1220 struct drm_crtc *crtc;
1221 int clock, pixel_size;
1222 int entries;
1223
1224 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1225 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1226 return false;
1227
1228 clock = crtc->mode.clock; /* VESA DOT Clock */
1229 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1230
1231 entries = (clock / 1000) * pixel_size;
1232 *plane_prec_mult = (entries > 256) ?
1233 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1234 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1235 pixel_size);
1236
1237 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1238 *cursor_prec_mult = (entries > 256) ?
1239 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1240 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1241
1242 return true;
1243}
1244
1245/*
1246 * Update drain latency registers of memory arbiter
1247 *
1248 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1249 * to be programmed. Each plane has a drain latency multiplier and a drain
1250 * latency value.
1251 */
1252
1253static void vlv_update_drain_latency(struct drm_device *dev)
1254{
1255 struct drm_i915_private *dev_priv = dev->dev_private;
1256 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1257 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1258 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1259 either 16 or 32 */
1260
1261 /* For plane A, Cursor A */
1262 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1263 &cursor_prec_mult, &cursora_dl)) {
1264 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1265 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1266 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1267 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1268
1269 I915_WRITE(VLV_DDL1, cursora_prec |
1270 (cursora_dl << DDL_CURSORA_SHIFT) |
1271 planea_prec | planea_dl);
1272 }
1273
1274 /* For plane B, Cursor B */
1275 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1276 &cursor_prec_mult, &cursorb_dl)) {
1277 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1278 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1279 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1280 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1281
1282 I915_WRITE(VLV_DDL2, cursorb_prec |
1283 (cursorb_dl << DDL_CURSORB_SHIFT) |
1284 planeb_prec | planeb_dl);
1285 }
1286}
1287
1288#define single_plane_enabled(mask) is_power_of_2(mask)
1289
1fa61106 1290static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1291{
1292 static const int sr_latency_ns = 12000;
1293 struct drm_i915_private *dev_priv = dev->dev_private;
1294 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1295 int plane_sr, cursor_sr;
af6c4575 1296 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1297 unsigned int enabled = 0;
1298
1299 vlv_update_drain_latency(dev);
1300
1301 if (g4x_compute_wm0(dev, 0,
1302 &valleyview_wm_info, latency_ns,
1303 &valleyview_cursor_wm_info, latency_ns,
1304 &planea_wm, &cursora_wm))
1305 enabled |= 1;
1306
1307 if (g4x_compute_wm0(dev, 1,
1308 &valleyview_wm_info, latency_ns,
1309 &valleyview_cursor_wm_info, latency_ns,
1310 &planeb_wm, &cursorb_wm))
1311 enabled |= 2;
1312
b445e3b0
ED		 1313 if (single_plane_enabled(enabled) &&
1314 g4x_compute_srwm(dev, ffs(enabled) - 1,
1315 sr_latency_ns,
1316 &valleyview_wm_info,
1317 &valleyview_cursor_wm_info,
af6c4575
CW		 1318 &plane_sr, &ignore_cursor_sr) &&
1319 g4x_compute_srwm(dev, ffs(enabled) - 1,
1320 2*sr_latency_ns,
1321 &valleyview_wm_info,
1322 &valleyview_cursor_wm_info,
52bd02d8 1323 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1324 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1325 } else {
b445e3b0
ED		 1326 I915_WRITE(FW_BLC_SELF_VLV,
1327 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1328 plane_sr = cursor_sr = 0;
1329 }
b445e3b0
ED		 1330
1331 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1332 planea_wm, cursora_wm,
1333 planeb_wm, cursorb_wm,
1334 plane_sr, cursor_sr);
1335
1336 I915_WRITE(DSPFW1,
1337 (plane_sr << DSPFW_SR_SHIFT) |
1338 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1339 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1340 planea_wm);
1341 I915_WRITE(DSPFW2,
8c919b28 1342 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1343 (cursora_wm << DSPFW_CURSORA_SHIFT));
1344 I915_WRITE(DSPFW3,
8c919b28
CW		 1345 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1346 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1347}
1348
1fa61106 1349static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1350{
1351 static const int sr_latency_ns = 12000;
1352 struct drm_i915_private *dev_priv = dev->dev_private;
1353 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1354 int plane_sr, cursor_sr;
1355 unsigned int enabled = 0;
1356
1357 if (g4x_compute_wm0(dev, 0,
1358 &g4x_wm_info, latency_ns,
1359 &g4x_cursor_wm_info, latency_ns,
1360 &planea_wm, &cursora_wm))
1361 enabled |= 1;
1362
1363 if (g4x_compute_wm0(dev, 1,
1364 &g4x_wm_info, latency_ns,
1365 &g4x_cursor_wm_info, latency_ns,
1366 &planeb_wm, &cursorb_wm))
1367 enabled |= 2;
1368
b445e3b0
ED		 1369 if (single_plane_enabled(enabled) &&
1370 g4x_compute_srwm(dev, ffs(enabled) - 1,
1371 sr_latency_ns,
1372 &g4x_wm_info,
1373 &g4x_cursor_wm_info,
52bd02d8 1374 &plane_sr, &cursor_sr)) {
b445e3b0 1375 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1376 } else {
b445e3b0
ED		 1377 I915_WRITE(FW_BLC_SELF,
1378 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1379 plane_sr = cursor_sr = 0;
1380 }
b445e3b0
ED		 1381
1382 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1383 planea_wm, cursora_wm,
1384 planeb_wm, cursorb_wm,
1385 plane_sr, cursor_sr);
1386
1387 I915_WRITE(DSPFW1,
1388 (plane_sr << DSPFW_SR_SHIFT) |
1389 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1390 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1391 planea_wm);
1392 I915_WRITE(DSPFW2,
8c919b28 1393 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1394 (cursora_wm << DSPFW_CURSORA_SHIFT));
1395 /* HPLL off in SR has some issues on G4x... disable it */
1396 I915_WRITE(DSPFW3,
8c919b28 1397 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1398 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1399}
1400
1fa61106 1401static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1402{
1403 struct drm_i915_private *dev_priv = dev->dev_private;
1404 struct drm_crtc *crtc;
1405 int srwm = 1;
1406 int cursor_sr = 16;
1407
1408 /* Calc sr entries for one plane configs */
1409 crtc = single_enabled_crtc(dev);
1410 if (crtc) {
1411 /* self-refresh has much higher latency */
1412 static const int sr_latency_ns = 12000;
1413 int clock = crtc->mode.clock;
1414 int htotal = crtc->mode.htotal;
1415 int hdisplay = crtc->mode.hdisplay;
1416 int pixel_size = crtc->fb->bits_per_pixel / 8;
1417 unsigned long line_time_us;
1418 int entries;
1419
1420 line_time_us = ((htotal * 1000) / clock);
1421
1422 /* Use ns/us then divide to preserve precision */
1423 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1424 pixel_size * hdisplay;
1425 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1426 srwm = I965_FIFO_SIZE - entries;
1427 if (srwm < 0)
1428 srwm = 1;
1429 srwm &= 0x1ff;
1430 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1431 entries, srwm);
1432
1433 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1434 pixel_size * 64;
1435 entries = DIV_ROUND_UP(entries,
1436 i965_cursor_wm_info.cacheline_size);
1437 cursor_sr = i965_cursor_wm_info.fifo_size -
1438 (entries + i965_cursor_wm_info.guard_size);
1439
1440 if (cursor_sr > i965_cursor_wm_info.max_wm)
1441 cursor_sr = i965_cursor_wm_info.max_wm;
1442
1443 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1444 "cursor %d\n", srwm, cursor_sr);
1445
1446 if (IS_CRESTLINE(dev))
1447 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1448 } else {
1449 /* Turn off self refresh if both pipes are enabled */
1450 if (IS_CRESTLINE(dev))
1451 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1452 & ~FW_BLC_SELF_EN);
1453 }
1454
1455 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1456 srwm);
1457
1458 /* 965 has limitations... */
1459 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1460 (8 << 16) | (8 << 8) | (8 << 0));
1461 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1462 /* update cursor SR watermark */
1463 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1464}
1465
1fa61106 1466static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1467{
1468 struct drm_i915_private *dev_priv = dev->dev_private;
1469 const struct intel_watermark_params *wm_info;
1470 uint32_t fwater_lo;
1471 uint32_t fwater_hi;
1472 int cwm, srwm = 1;
1473 int fifo_size;
1474 int planea_wm, planeb_wm;
1475 struct drm_crtc *crtc, *enabled = NULL;
1476
1477 if (IS_I945GM(dev))
1478 wm_info = &i945_wm_info;
1479 else if (!IS_GEN2(dev))
1480 wm_info = &i915_wm_info;
1481 else
1482 wm_info = &i855_wm_info;
1483
1484 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1485 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1486 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1487 int cpp = crtc->fb->bits_per_pixel / 8;
1488 if (IS_GEN2(dev))
1489 cpp = 4;
1490
b445e3b0 1491 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1492 wm_info, fifo_size, cpp,
b445e3b0
ED		 1493 latency_ns);
1494 enabled = crtc;
1495 } else
1496 planea_wm = fifo_size - wm_info->guard_size;
1497
1498 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1499 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1500 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1501 int cpp = crtc->fb->bits_per_pixel / 8;
1502 if (IS_GEN2(dev))
1503 cpp = 4;
1504
b445e3b0 1505 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1506 wm_info, fifo_size, cpp,
b445e3b0
ED		 1507 latency_ns);
1508 if (enabled == NULL)
1509 enabled = crtc;
1510 else
1511 enabled = NULL;
1512 } else
1513 planeb_wm = fifo_size - wm_info->guard_size;
1514
1515 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1516
1517 /*
1518 * Overlay gets an aggressive default since video jitter is bad.
1519 */
1520 cwm = 2;
1521
1522 /* Play safe and disable self-refresh before adjusting watermarks. */
1523 if (IS_I945G(dev) || IS_I945GM(dev))
1524 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1525 else if (IS_I915GM(dev))
1526 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1527
1528 /* Calc sr entries for one plane configs */
1529 if (HAS_FW_BLC(dev) && enabled) {
1530 /* self-refresh has much higher latency */
1531 static const int sr_latency_ns = 6000;
1532 int clock = enabled->mode.clock;
1533 int htotal = enabled->mode.htotal;
1534 int hdisplay = enabled->mode.hdisplay;
1535 int pixel_size = enabled->fb->bits_per_pixel / 8;
1536 unsigned long line_time_us;
1537 int entries;
1538
1539 line_time_us = (htotal * 1000) / clock;
1540
1541 /* Use ns/us then divide to preserve precision */
1542 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1543 pixel_size * hdisplay;
1544 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1545 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1546 srwm = wm_info->fifo_size - entries;
1547 if (srwm < 0)
1548 srwm = 1;
1549
1550 if (IS_I945G(dev) || IS_I945GM(dev))
1551 I915_WRITE(FW_BLC_SELF,
1552 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1553 else if (IS_I915GM(dev))
1554 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1555 }
1556
1557 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1558 planea_wm, planeb_wm, cwm, srwm);
1559
1560 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1561 fwater_hi = (cwm & 0x1f);
1562
1563 /* Set request length to 8 cachelines per fetch */
1564 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1565 fwater_hi = fwater_hi | (1 << 8);
1566
1567 I915_WRITE(FW_BLC, fwater_lo);
1568 I915_WRITE(FW_BLC2, fwater_hi);
1569
1570 if (HAS_FW_BLC(dev)) {
1571 if (enabled) {
1572 if (IS_I945G(dev) || IS_I945GM(dev))
1573 I915_WRITE(FW_BLC_SELF,
1574 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1575 else if (IS_I915GM(dev))
1576 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1577 DRM_DEBUG_KMS("memory self refresh enabled\n");
1578 } else
1579 DRM_DEBUG_KMS("memory self refresh disabled\n");
1580 }
1581}
1582
1fa61106 1583static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1584{
1585 struct drm_i915_private *dev_priv = dev->dev_private;
1586 struct drm_crtc *crtc;
1587 uint32_t fwater_lo;
1588 int planea_wm;
1589
1590 crtc = single_enabled_crtc(dev);
1591 if (crtc == NULL)
1592 return;
1593
1594 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1595 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1596 4, latency_ns);
b445e3b0
ED		 1597 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1598 fwater_lo |= (3<<8) | planea_wm;
1599
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1601
1602 I915_WRITE(FW_BLC, fwater_lo);
1603}
1604
1605#define ILK_LP0_PLANE_LATENCY 700
1606#define ILK_LP0_CURSOR_LATENCY 1300
1607
1608/*
1609 * Check the wm result.
1610 *
1611 * If any calculated watermark values is larger than the maximum value that
1612 * can be programmed into the associated watermark register, that watermark
1613 * must be disabled.
1614 */
1615static bool ironlake_check_srwm(struct drm_device *dev, int level,
1616 int fbc_wm, int display_wm, int cursor_wm,
1617 const struct intel_watermark_params *display,
1618 const struct intel_watermark_params *cursor)
1619{
1620 struct drm_i915_private *dev_priv = dev->dev_private;
1621
1622 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1623 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1624
1625 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1626 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1627 fbc_wm, SNB_FBC_MAX_SRWM, level);
1628
1629 /* fbc has it's own way to disable FBC WM */
1630 I915_WRITE(DISP_ARB_CTL,
1631 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1632 return false;
1633 }
1634
1635 if (display_wm > display->max_wm) {
1636 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1637 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1638 return false;
1639 }
1640
1641 if (cursor_wm > cursor->max_wm) {
1642 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1643 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1644 return false;
1645 }
1646
1647 if (!(fbc_wm || display_wm || cursor_wm)) {
1648 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1649 return false;
1650 }
1651
1652 return true;
1653}
1654
1655/*
1656 * Compute watermark values of WM[1-3],
1657 */
1658static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1659 int latency_ns,
1660 const struct intel_watermark_params *display,
1661 const struct intel_watermark_params *cursor,
1662 int *fbc_wm, int *display_wm, int *cursor_wm)
1663{
1664 struct drm_crtc *crtc;
1665 unsigned long line_time_us;
1666 int hdisplay, htotal, pixel_size, clock;
1667 int line_count, line_size;
1668 int small, large;
1669 int entries;
1670
1671 if (!latency_ns) {
1672 *fbc_wm = *display_wm = *cursor_wm = 0;
1673 return false;
1674 }
1675
1676 crtc = intel_get_crtc_for_plane(dev, plane);
1677 hdisplay = crtc->mode.hdisplay;
1678 htotal = crtc->mode.htotal;
1679 clock = crtc->mode.clock;
1680 pixel_size = crtc->fb->bits_per_pixel / 8;
1681
1682 line_time_us = (htotal * 1000) / clock;
1683 line_count = (latency_ns / line_time_us + 1000) / 1000;
1684 line_size = hdisplay * pixel_size;
1685
1686 /* Use the minimum of the small and large buffer method for primary */
1687 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1688 large = line_count * line_size;
1689
1690 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1691 *display_wm = entries + display->guard_size;
1692
1693 /*
1694 * Spec says:
1695 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1696 */
1697 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1698
1699 /* calculate the self-refresh watermark for display cursor */
1700 entries = line_count * pixel_size * 64;
1701 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1702 *cursor_wm = entries + cursor->guard_size;
1703
1704 return ironlake_check_srwm(dev, level,
1705 *fbc_wm, *display_wm, *cursor_wm,
1706 display, cursor);
1707}
1708
1fa61106 1709static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1710{
1711 struct drm_i915_private *dev_priv = dev->dev_private;
1712 int fbc_wm, plane_wm, cursor_wm;
1713 unsigned int enabled;
1714
1715 enabled = 0;
1716 if (g4x_compute_wm0(dev, 0,
1717 &ironlake_display_wm_info,
1718 ILK_LP0_PLANE_LATENCY,
1719 &ironlake_cursor_wm_info,
1720 ILK_LP0_CURSOR_LATENCY,
1721 &plane_wm, &cursor_wm)) {
1722 I915_WRITE(WM0_PIPEA_ILK,
1723 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1724 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1725 " plane %d, " "cursor: %d\n",
1726 plane_wm, cursor_wm);
1727 enabled |= 1;
1728 }
1729
1730 if (g4x_compute_wm0(dev, 1,
1731 &ironlake_display_wm_info,
1732 ILK_LP0_PLANE_LATENCY,
1733 &ironlake_cursor_wm_info,
1734 ILK_LP0_CURSOR_LATENCY,
1735 &plane_wm, &cursor_wm)) {
1736 I915_WRITE(WM0_PIPEB_ILK,
1737 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1738 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1739 " plane %d, cursor: %d\n",
1740 plane_wm, cursor_wm);
1741 enabled |= 2;
1742 }
1743
1744 /*
1745 * Calculate and update the self-refresh watermark only when one
1746 * display plane is used.
1747 */
1748 I915_WRITE(WM3_LP_ILK, 0);
1749 I915_WRITE(WM2_LP_ILK, 0);
1750 I915_WRITE(WM1_LP_ILK, 0);
1751
1752 if (!single_plane_enabled(enabled))
1753 return;
1754 enabled = ffs(enabled) - 1;
1755
1756 /* WM1 */
1757 if (!ironlake_compute_srwm(dev, 1, enabled,
1758 ILK_READ_WM1_LATENCY() * 500,
1759 &ironlake_display_srwm_info,
1760 &ironlake_cursor_srwm_info,
1761 &fbc_wm, &plane_wm, &cursor_wm))
1762 return;
1763
1764 I915_WRITE(WM1_LP_ILK,
1765 WM1_LP_SR_EN |
1766 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1767 (fbc_wm << WM1_LP_FBC_SHIFT) |
1768 (plane_wm << WM1_LP_SR_SHIFT) |
1769 cursor_wm);
1770
1771 /* WM2 */
1772 if (!ironlake_compute_srwm(dev, 2, enabled,
1773 ILK_READ_WM2_LATENCY() * 500,
1774 &ironlake_display_srwm_info,
1775 &ironlake_cursor_srwm_info,
1776 &fbc_wm, &plane_wm, &cursor_wm))
1777 return;
1778
1779 I915_WRITE(WM2_LP_ILK,
1780 WM2_LP_EN |
1781 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1782 (fbc_wm << WM1_LP_FBC_SHIFT) |
1783 (plane_wm << WM1_LP_SR_SHIFT) |
1784 cursor_wm);
1785
1786 /*
1787 * WM3 is unsupported on ILK, probably because we don't have latency
1788 * data for that power state
1789 */
1790}
1791
1fa61106 1792static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1793{
1794 struct drm_i915_private *dev_priv = dev->dev_private;
1795 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1796 u32 val;
1797 int fbc_wm, plane_wm, cursor_wm;
1798 unsigned int enabled;
1799
1800 enabled = 0;
1801 if (g4x_compute_wm0(dev, 0,
1802 &sandybridge_display_wm_info, latency,
1803 &sandybridge_cursor_wm_info, latency,
1804 &plane_wm, &cursor_wm)) {
1805 val = I915_READ(WM0_PIPEA_ILK);
1806 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1807 I915_WRITE(WM0_PIPEA_ILK, val |
1808 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1809 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1810 " plane %d, " "cursor: %d\n",
1811 plane_wm, cursor_wm);
1812 enabled |= 1;
1813 }
1814
1815 if (g4x_compute_wm0(dev, 1,
1816 &sandybridge_display_wm_info, latency,
1817 &sandybridge_cursor_wm_info, latency,
1818 &plane_wm, &cursor_wm)) {
1819 val = I915_READ(WM0_PIPEB_ILK);
1820 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1821 I915_WRITE(WM0_PIPEB_ILK, val |
1822 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1823 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1824 " plane %d, cursor: %d\n",
1825 plane_wm, cursor_wm);
1826 enabled |= 2;
1827 }
1828
c43d0188
CW		 1829 /*
1830 * Calculate and update the self-refresh watermark only when one
1831 * display plane is used.
1832 *
1833 * SNB support 3 levels of watermark.
1834 *
1835 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1836 * and disabled in the descending order
1837 *
1838 */
1839 I915_WRITE(WM3_LP_ILK, 0);
1840 I915_WRITE(WM2_LP_ILK, 0);
1841 I915_WRITE(WM1_LP_ILK, 0);
1842
1843 if (!single_plane_enabled(enabled) ||
1844 dev_priv->sprite_scaling_enabled)
1845 return;
1846 enabled = ffs(enabled) - 1;
1847
1848 /* WM1 */
1849 if (!ironlake_compute_srwm(dev, 1, enabled,
1850 SNB_READ_WM1_LATENCY() * 500,
1851 &sandybridge_display_srwm_info,
1852 &sandybridge_cursor_srwm_info,
1853 &fbc_wm, &plane_wm, &cursor_wm))
1854 return;
1855
1856 I915_WRITE(WM1_LP_ILK,
1857 WM1_LP_SR_EN |
1858 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1859 (fbc_wm << WM1_LP_FBC_SHIFT) |
1860 (plane_wm << WM1_LP_SR_SHIFT) |
1861 cursor_wm);
1862
1863 /* WM2 */
1864 if (!ironlake_compute_srwm(dev, 2, enabled,
1865 SNB_READ_WM2_LATENCY() * 500,
1866 &sandybridge_display_srwm_info,
1867 &sandybridge_cursor_srwm_info,
1868 &fbc_wm, &plane_wm, &cursor_wm))
1869 return;
1870
1871 I915_WRITE(WM2_LP_ILK,
1872 WM2_LP_EN |
1873 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1874 (fbc_wm << WM1_LP_FBC_SHIFT) |
1875 (plane_wm << WM1_LP_SR_SHIFT) |
1876 cursor_wm);
1877
1878 /* WM3 */
1879 if (!ironlake_compute_srwm(dev, 3, enabled,
1880 SNB_READ_WM3_LATENCY() * 500,
1881 &sandybridge_display_srwm_info,
1882 &sandybridge_cursor_srwm_info,
1883 &fbc_wm, &plane_wm, &cursor_wm))
1884 return;
1885
1886 I915_WRITE(WM3_LP_ILK,
1887 WM3_LP_EN |
1888 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1889 (fbc_wm << WM1_LP_FBC_SHIFT) |
1890 (plane_wm << WM1_LP_SR_SHIFT) |
1891 cursor_wm);
1892}
1893
1894static void ivybridge_update_wm(struct drm_device *dev)
1895{
1896 struct drm_i915_private *dev_priv = dev->dev_private;
1897 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1898 u32 val;
1899 int fbc_wm, plane_wm, cursor_wm;
1900 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1901 unsigned int enabled;
1902
1903 enabled = 0;
1904 if (g4x_compute_wm0(dev, 0,
1905 &sandybridge_display_wm_info, latency,
1906 &sandybridge_cursor_wm_info, latency,
1907 &plane_wm, &cursor_wm)) {
1908 val = I915_READ(WM0_PIPEA_ILK);
1909 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1910 I915_WRITE(WM0_PIPEA_ILK, val |
1911 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1912 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1913 " plane %d, " "cursor: %d\n",
1914 plane_wm, cursor_wm);
1915 enabled |= 1;
1916 }
1917
1918 if (g4x_compute_wm0(dev, 1,
1919 &sandybridge_display_wm_info, latency,
1920 &sandybridge_cursor_wm_info, latency,
1921 &plane_wm, &cursor_wm)) {
1922 val = I915_READ(WM0_PIPEB_ILK);
1923 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1924 I915_WRITE(WM0_PIPEB_ILK, val |
1925 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1926 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1927 " plane %d, cursor: %d\n",
1928 plane_wm, cursor_wm);
1929 enabled |= 2;
1930 }
1931
1932 if (g4x_compute_wm0(dev, 2,
b445e3b0
ED		 1933 &sandybridge_display_wm_info, latency,
1934 &sandybridge_cursor_wm_info, latency,
1935 &plane_wm, &cursor_wm)) {
1936 val = I915_READ(WM0_PIPEC_IVB);
1937 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1938 I915_WRITE(WM0_PIPEC_IVB, val |
1939 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1940 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1941 " plane %d, cursor: %d\n",
1942 plane_wm, cursor_wm);
1943 enabled |= 3;
1944 }
1945
1946 /*
1947 * Calculate and update the self-refresh watermark only when one
1948 * display plane is used.
1949 *
1950 * SNB support 3 levels of watermark.
1951 *
1952 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1953 * and disabled in the descending order
1954 *
1955 */
1956 I915_WRITE(WM3_LP_ILK, 0);
1957 I915_WRITE(WM2_LP_ILK, 0);
1958 I915_WRITE(WM1_LP_ILK, 0);
1959
1960 if (!single_plane_enabled(enabled) ||
1961 dev_priv->sprite_scaling_enabled)
1962 return;
1963 enabled = ffs(enabled) - 1;
1964
1965 /* WM1 */
1966 if (!ironlake_compute_srwm(dev, 1, enabled,
1967 SNB_READ_WM1_LATENCY() * 500,
1968 &sandybridge_display_srwm_info,
1969 &sandybridge_cursor_srwm_info,
1970 &fbc_wm, &plane_wm, &cursor_wm))
1971 return;
1972
1973 I915_WRITE(WM1_LP_ILK,
1974 WM1_LP_SR_EN |
1975 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1976 (fbc_wm << WM1_LP_FBC_SHIFT) |
1977 (plane_wm << WM1_LP_SR_SHIFT) |
1978 cursor_wm);
1979
1980 /* WM2 */
1981 if (!ironlake_compute_srwm(dev, 2, enabled,
1982 SNB_READ_WM2_LATENCY() * 500,
1983 &sandybridge_display_srwm_info,
1984 &sandybridge_cursor_srwm_info,
1985 &fbc_wm, &plane_wm, &cursor_wm))
1986 return;
1987
1988 I915_WRITE(WM2_LP_ILK,
1989 WM2_LP_EN |
1990 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1991 (fbc_wm << WM1_LP_FBC_SHIFT) |
1992 (plane_wm << WM1_LP_SR_SHIFT) |
1993 cursor_wm);
1994
c43d0188 1995 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 1996 if (!ironlake_compute_srwm(dev, 3, enabled,
1997 SNB_READ_WM3_LATENCY() * 500,
1998 &sandybridge_display_srwm_info,
1999 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2000 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2001 !ironlake_compute_srwm(dev, 3, enabled,
2002 2 * SNB_READ_WM3_LATENCY() * 500,
2003 &sandybridge_display_srwm_info,
2004 &sandybridge_cursor_srwm_info,
2005 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2006 return;
2007
2008 I915_WRITE(WM3_LP_ILK,
2009 WM3_LP_EN |
2010 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2011 (fbc_wm << WM1_LP_FBC_SHIFT) |
2012 (plane_wm << WM1_LP_SR_SHIFT) |
2013 cursor_wm);
2014}
2015
1f8eeabf
ED		 2016static void
2017haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2018 struct drm_display_mode *mode)
2019{
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 u32 temp;
2022
2023 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2024 temp &= ~PIPE_WM_LINETIME_MASK;
2025
2026 /* The WM are computed with base on how long it takes to fill a single
2027 * row at the given clock rate, multiplied by 8.
2028 * */
2029 temp |= PIPE_WM_LINETIME_TIME(
2030 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2031
2032 /* IPS watermarks are only used by pipe A, and are ignored by
2033 * pipes B and C. They are calculated similarly to the common
2034 * linetime values, except that we are using CD clock frequency
2035 * in MHz instead of pixel rate for the division.
2036 *
2037 * This is a placeholder for the IPS watermark calculation code.
2038 */
2039
2040 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2041}
2042
b445e3b0
ED		 2043static bool
2044sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2045 uint32_t sprite_width, int pixel_size,
2046 const struct intel_watermark_params *display,
2047 int display_latency_ns, int *sprite_wm)
2048{
2049 struct drm_crtc *crtc;
2050 int clock;
2051 int entries, tlb_miss;
2052
2053 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2054 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2055 *sprite_wm = display->guard_size;
2056 return false;
2057 }
2058
2059 clock = crtc->mode.clock;
2060
2061 /* Use the small buffer method to calculate the sprite watermark */
2062 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2063 tlb_miss = display->fifo_size*display->cacheline_size -
2064 sprite_width * 8;
2065 if (tlb_miss > 0)
2066 entries += tlb_miss;
2067 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2068 *sprite_wm = entries + display->guard_size;
2069 if (*sprite_wm > (int)display->max_wm)
2070 *sprite_wm = display->max_wm;
2071
2072 return true;
2073}
2074
2075static bool
2076sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2077 uint32_t sprite_width, int pixel_size,
2078 const struct intel_watermark_params *display,
2079 int latency_ns, int *sprite_wm)
2080{
2081 struct drm_crtc *crtc;
2082 unsigned long line_time_us;
2083 int clock;
2084 int line_count, line_size;
2085 int small, large;
2086 int entries;
2087
2088 if (!latency_ns) {
2089 *sprite_wm = 0;
2090 return false;
2091 }
2092
2093 crtc = intel_get_crtc_for_plane(dev, plane);
2094 clock = crtc->mode.clock;
2095 if (!clock) {
2096 *sprite_wm = 0;
2097 return false;
2098 }
2099
2100 line_time_us = (sprite_width * 1000) / clock;
2101 if (!line_time_us) {
2102 *sprite_wm = 0;
2103 return false;
2104 }
2105
2106 line_count = (latency_ns / line_time_us + 1000) / 1000;
2107 line_size = sprite_width * pixel_size;
2108
2109 /* Use the minimum of the small and large buffer method for primary */
2110 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2111 large = line_count * line_size;
2112
2113 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2114 *sprite_wm = entries + display->guard_size;
2115
2116 return *sprite_wm > 0x3ff ? false : true;
2117}
2118
1fa61106 2119static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 2120 uint32_t sprite_width, int pixel_size)
2121{
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2124 u32 val;
2125 int sprite_wm, reg;
2126 int ret;
2127
2128 switch (pipe) {
2129 case 0:
2130 reg = WM0_PIPEA_ILK;
2131 break;
2132 case 1:
2133 reg = WM0_PIPEB_ILK;
2134 break;
2135 case 2:
2136 reg = WM0_PIPEC_IVB;
2137 break;
2138 default:
2139 return; /* bad pipe */
2140 }
2141
2142 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2143 &sandybridge_display_wm_info,
2144 latency, &sprite_wm);
2145 if (!ret) {
2146 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2147 pipe);
2148 return;
2149 }
2150
2151 val = I915_READ(reg);
2152 val &= ~WM0_PIPE_SPRITE_MASK;
2153 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2154 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2155
2156
2157 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2158 pixel_size,
2159 &sandybridge_display_srwm_info,
2160 SNB_READ_WM1_LATENCY() * 500,
2161 &sprite_wm);
2162 if (!ret) {
2163 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2164 pipe);
2165 return;
2166 }
2167 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2168
2169 /* Only IVB has two more LP watermarks for sprite */
2170 if (!IS_IVYBRIDGE(dev))
2171 return;
2172
2173 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2174 pixel_size,
2175 &sandybridge_display_srwm_info,
2176 SNB_READ_WM2_LATENCY() * 500,
2177 &sprite_wm);
2178 if (!ret) {
2179 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2180 pipe);
2181 return;
2182 }
2183 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2184
2185 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2186 pixel_size,
2187 &sandybridge_display_srwm_info,
2188 SNB_READ_WM3_LATENCY() * 500,
2189 &sprite_wm);
2190 if (!ret) {
2191 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2192 pipe);
2193 return;
2194 }
2195 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2196}
2197
2198/**
2199 * intel_update_watermarks - update FIFO watermark values based on current modes
2200 *
2201 * Calculate watermark values for the various WM regs based on current mode
2202 * and plane configuration.
2203 *
2204 * There are several cases to deal with here:
2205 * - normal (i.e. non-self-refresh)
2206 * - self-refresh (SR) mode
2207 * - lines are large relative to FIFO size (buffer can hold up to 2)
2208 * - lines are small relative to FIFO size (buffer can hold more than 2
2209 * lines), so need to account for TLB latency
2210 *
2211 * The normal calculation is:
2212 * watermark = dotclock * bytes per pixel * latency
2213 * where latency is platform & configuration dependent (we assume pessimal
2214 * values here).
2215 *
2216 * The SR calculation is:
2217 * watermark = (trunc(latency/line time)+1) * surface width *
2218 * bytes per pixel
2219 * where
2220 * line time = htotal / dotclock
2221 * surface width = hdisplay for normal plane and 64 for cursor
2222 * and latency is assumed to be high, as above.
2223 *
2224 * The final value programmed to the register should always be rounded up,
2225 * and include an extra 2 entries to account for clock crossings.
2226 *
2227 * We don't use the sprite, so we can ignore that. And on Crestline we have
2228 * to set the non-SR watermarks to 8.
2229 */
2230void intel_update_watermarks(struct drm_device *dev)
2231{
2232 struct drm_i915_private *dev_priv = dev->dev_private;
2233
2234 if (dev_priv->display.update_wm)
2235 dev_priv->display.update_wm(dev);
2236}
2237
1f8eeabf
ED		 2238void intel_update_linetime_watermarks(struct drm_device *dev,
2239 int pipe, struct drm_display_mode *mode)
2240{
2241 struct drm_i915_private *dev_priv = dev->dev_private;
2242
2243 if (dev_priv->display.update_linetime_wm)
2244 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2245}
2246
b445e3b0
ED		 2247void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2248 uint32_t sprite_width, int pixel_size)
2249{
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251
2252 if (dev_priv->display.update_sprite_wm)
2253 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2254 pixel_size);
2255}
2256
2b4e57bd
ED		 2257static struct drm_i915_gem_object *
2258intel_alloc_context_page(struct drm_device *dev)
2259{
2260 struct drm_i915_gem_object *ctx;
2261 int ret;
2262
2263 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2264
2265 ctx = i915_gem_alloc_object(dev, 4096);
2266 if (!ctx) {
2267 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2268 return NULL;
2269 }
2270
86a1ee26 2271 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2272 if (ret) {
2273 DRM_ERROR("failed to pin power context: %d\n", ret);
2274 goto err_unref;
2275 }
2276
2277 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2278 if (ret) {
2279 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2280 goto err_unpin;
2281 }
2282
2283 return ctx;
2284
2285err_unpin:
2286 i915_gem_object_unpin(ctx);
2287err_unref:
2288 drm_gem_object_unreference(&ctx->base);
2289 mutex_unlock(&dev->struct_mutex);
2290 return NULL;
2291}
2292
9270388e
DV		 2293/**
2294 * Lock protecting IPS related data structures
9270388e
DV		 2295 */
2296DEFINE_SPINLOCK(mchdev_lock);
2297
2298/* Global for IPS driver to get at the current i915 device. Protected by
2299 * mchdev_lock. */
2300static struct drm_i915_private *i915_mch_dev;
2301
2b4e57bd
ED		 2302bool ironlake_set_drps(struct drm_device *dev, u8 val)
2303{
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 u16 rgvswctl;
2306
9270388e
DV		 2307 assert_spin_locked(&mchdev_lock);
2308
2b4e57bd
ED		 2309 rgvswctl = I915_READ16(MEMSWCTL);
2310 if (rgvswctl & MEMCTL_CMD_STS) {
2311 DRM_DEBUG("gpu busy, RCS change rejected\n");
2312 return false; /* still busy with another command */
2313 }
2314
2315 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2316 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2317 I915_WRITE16(MEMSWCTL, rgvswctl);
2318 POSTING_READ16(MEMSWCTL);
2319
2320 rgvswctl |= MEMCTL_CMD_STS;
2321 I915_WRITE16(MEMSWCTL, rgvswctl);
2322
2323 return true;
2324}
2325
8090c6b9 2326static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2327{
2328 struct drm_i915_private *dev_priv = dev->dev_private;
2329 u32 rgvmodectl = I915_READ(MEMMODECTL);
2330 u8 fmax, fmin, fstart, vstart;
2331
9270388e
DV		 2332 spin_lock_irq(&mchdev_lock);
2333
2b4e57bd
ED		 2334 /* Enable temp reporting */
2335 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2336 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2337
2338 /* 100ms RC evaluation intervals */
2339 I915_WRITE(RCUPEI, 100000);
2340 I915_WRITE(RCDNEI, 100000);
2341
2342 /* Set max/min thresholds to 90ms and 80ms respectively */
2343 I915_WRITE(RCBMAXAVG, 90000);
2344 I915_WRITE(RCBMINAVG, 80000);
2345
2346 I915_WRITE(MEMIHYST, 1);
2347
2348 /* Set up min, max, and cur for interrupt handling */
2349 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2350 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2351 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2352 MEMMODE_FSTART_SHIFT;
2353
2354 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2355 PXVFREQ_PX_SHIFT;
2356
20e4d407
DV		 2357 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2358 dev_priv->ips.fstart = fstart;
2b4e57bd 2359
20e4d407
DV		 2360 dev_priv->ips.max_delay = fstart;
2361 dev_priv->ips.min_delay = fmin;
2362 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2363
2364 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2365 fmax, fmin, fstart);
2366
2367 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2368
2369 /*
2370 * Interrupts will be enabled in ironlake_irq_postinstall
2371 */
2372
2373 I915_WRITE(VIDSTART, vstart);
2374 POSTING_READ(VIDSTART);
2375
2376 rgvmodectl |= MEMMODE_SWMODE_EN;
2377 I915_WRITE(MEMMODECTL, rgvmodectl);
2378
9270388e 2379 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2380 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2381 mdelay(1);
2b4e57bd
ED		 2382
2383 ironlake_set_drps(dev, fstart);
2384
20e4d407 2385 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2386 I915_READ(0x112e0);
20e4d407
DV		 2387 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2388 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2389 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2390
2391 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2392}
2393
8090c6b9 2394static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2395{
2396 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2397 u16 rgvswctl;
2398
2399 spin_lock_irq(&mchdev_lock);
2400
2401 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2402
2403 /* Ack interrupts, disable EFC interrupt */
2404 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2405 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2406 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2407 I915_WRITE(DEIIR, DE_PCU_EVENT);
2408 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2409
2410 /* Go back to the starting frequency */
20e4d407 2411 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2412 mdelay(1);
2b4e57bd
ED		 2413 rgvswctl |= MEMCTL_CMD_STS;
2414 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2415 mdelay(1);
2b4e57bd 2416
9270388e 2417 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2418}
2419
acbe9475
DV		 2420/* There's a funny hw issue where the hw returns all 0 when reading from
2421 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2422 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2423 * all limits and the gpu stuck at whatever frequency it is at atm).
2424 */
65bccb5c 2425static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2426{
7b9e0ae6 2427 u32 limits;
2b4e57bd 2428
7b9e0ae6 2429 limits = 0;
c6a828d3
DV		 2430
2431 if (*val >= dev_priv->rps.max_delay)
2432 *val = dev_priv->rps.max_delay;
2433 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2434
2435 /* Only set the down limit when we've reached the lowest level to avoid
2436 * getting more interrupts, otherwise leave this clear. This prevents a
2437 * race in the hw when coming out of rc6: There's a tiny window where
2438 * the hw runs at the minimal clock before selecting the desired
2439 * frequency, if the down threshold expires in that window we will not
2440 * receive a down interrupt. */
c6a828d3
DV		 2441 if (*val <= dev_priv->rps.min_delay) {
2442 *val = dev_priv->rps.min_delay;
2443 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2444 }
2445
2446 return limits;
2447}
2448
2449void gen6_set_rps(struct drm_device *dev, u8 val)
2450{
2451 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2452 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2453
4fc688ce 2454 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 2455 WARN_ON(val > dev_priv->rps.max_delay);
2456 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2457
c6a828d3 2458 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2459 return;
2460
2461 I915_WRITE(GEN6_RPNSWREQ,
2462 GEN6_FREQUENCY(val) |
2463 GEN6_OFFSET(0) |
2464 GEN6_AGGRESSIVE_TURBO);
2465
2466 /* Make sure we continue to get interrupts
2467 * until we hit the minimum or maximum frequencies.
2468 */
2469 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2470
d5570a72
BW		 2471 POSTING_READ(GEN6_RPNSWREQ);
2472
c6a828d3 2473 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2474
2475 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2476}
2477
8090c6b9 2478static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2479{
2480 struct drm_i915_private *dev_priv = dev->dev_private;
2481
88509484 2482 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2483 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2484 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2485 I915_WRITE(GEN6_PMIER, 0);
2486 /* Complete PM interrupt masking here doesn't race with the rps work
2487 * item again unmasking PM interrupts because that is using a different
2488 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2489 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2490
c6a828d3
DV		 2491 spin_lock_irq(&dev_priv->rps.lock);
2492 dev_priv->rps.pm_iir = 0;
2493 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2494
2495 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2496}
2497
2498int intel_enable_rc6(const struct drm_device *dev)
2499{
456470eb 2500 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2501 if (i915_enable_rc6 >= 0)
2502 return i915_enable_rc6;
2503
6567d748
CW		 2504 /* Disable RC6 on Ironlake */
2505 if (INTEL_INFO(dev)->gen == 5)
2506 return 0;
2b4e57bd 2507
456470eb
DV		 2508 if (IS_HASWELL(dev)) {
2509 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2510 return INTEL_RC6_ENABLE;
456470eb 2511 }
2b4e57bd 2512
456470eb 2513 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2514 if (INTEL_INFO(dev)->gen == 6) {
2515 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2516 return INTEL_RC6_ENABLE;
2517 }
456470eb 2518
2b4e57bd
ED		 2519 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2520 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2521}
2522
79f5b2c7 2523static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2524{
79f5b2c7 2525 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2526 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2527 u32 rp_state_cap;
2528 u32 gt_perf_status;
31643d54 2529 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 2530 u32 gtfifodbg;
2b4e57bd 2531 int rc6_mode;
42c0526c 2532 int i, ret;
2b4e57bd 2533
4fc688ce 2534 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2535
2b4e57bd
ED		 2536 /* Here begins a magic sequence of register writes to enable
2537 * auto-downclocking.
2538 *
2539 * Perhaps there might be some value in exposing these to
2540 * userspace...
2541 */
2542 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2543
2544 /* Clear the DBG now so we don't confuse earlier errors */
2545 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2546 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2547 I915_WRITE(GTFIFODBG, gtfifodbg);
2548 }
2549
2550 gen6_gt_force_wake_get(dev_priv);
2551
7b9e0ae6
CW		 2552 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2553 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2554
2555 /* In units of 100MHz */
c6a828d3
DV		 2556 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2557 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2558 dev_priv->rps.cur_delay = 0;
7b9e0ae6 2559
2b4e57bd
ED		 2560 /* disable the counters and set deterministic thresholds */
2561 I915_WRITE(GEN6_RC_CONTROL, 0);
2562
2563 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2564 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2565 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2566 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2567 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2568
b4519513
CW		 2569 for_each_ring(ring, dev_priv, i)
2570 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2571
2572 I915_WRITE(GEN6_RC_SLEEP, 0);
2573 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2574 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2575 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
2576 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2577
5a7dc92a 2578 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2579 rc6_mode = intel_enable_rc6(dev_priv->dev);
2580 if (rc6_mode & INTEL_RC6_ENABLE)
2581 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2582
5a7dc92a
ED		 2583 /* We don't use those on Haswell */
2584 if (!IS_HASWELL(dev)) {
2585 if (rc6_mode & INTEL_RC6p_ENABLE)
2586 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2587
5a7dc92a
ED		 2588 if (rc6_mode & INTEL_RC6pp_ENABLE)
2589 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2590 }
2b4e57bd
ED		 2591
2592 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2593 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2594 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2595 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2596
2597 I915_WRITE(GEN6_RC_CONTROL,
2598 rc6_mask |
2599 GEN6_RC_CTL_EI_MODE(1) |
2600 GEN6_RC_CTL_HW_ENABLE);
2601
2602 I915_WRITE(GEN6_RPNSWREQ,
2603 GEN6_FREQUENCY(10) |
2604 GEN6_OFFSET(0) |
2605 GEN6_AGGRESSIVE_TURBO);
2606 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2607 GEN6_FREQUENCY(12));
2608
2609 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2610 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 2611 dev_priv->rps.max_delay << 24 |
2612 dev_priv->rps.min_delay << 16);
5a7dc92a 2613
1ee9ae32
DV		 2614 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2615 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2616 I915_WRITE(GEN6_RP_UP_EI, 66000);
2617 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 2618
2b4e57bd
ED		 2619 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2620 I915_WRITE(GEN6_RP_CONTROL,
2621 GEN6_RP_MEDIA_TURBO |
89ba829e 2622 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2623 GEN6_RP_MEDIA_IS_GFX |
2624 GEN6_RP_ENABLE |
2625 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2626 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 2627
42c0526c
BW		 2628 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2629 if (!ret) {
2630 pcu_mbox = 0;
2631 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2632 if (ret && pcu_mbox & (1<<31)) { /* OC supported */
2633 dev_priv->rps.max_delay = pcu_mbox & 0xff;
2634 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
2635 }
2636 } else {
2637 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 2638 }
2639
7b9e0ae6 2640 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2641
2642 /* requires MSI enabled */
ff928261 2643 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 2644 spin_lock_irq(&dev_priv->rps.lock);
2645 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 2646 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 2647 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2648 /* enable all PM interrupts */
2649 I915_WRITE(GEN6_PMINTRMSK, 0);
2650
31643d54
BW		 2651 rc6vids = 0;
2652 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2653 if (IS_GEN6(dev) && ret) {
2654 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2655 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2656 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2657 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2658 rc6vids &= 0xffff00;
2659 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2660 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2661 if (ret)
2662 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2663 }
2664
2b4e57bd 2665 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2666}
2667
79f5b2c7 2668static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2669{
79f5b2c7 2670 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 2671 int min_freq = 15;
e3fef09d
JD		 2672 int gpu_freq;
2673 unsigned int ia_freq, max_ia_freq;
2b4e57bd
ED		 2674 int scaling_factor = 180;
2675
4fc688ce 2676 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2677
2b4e57bd
ED		 2678 max_ia_freq = cpufreq_quick_get_max(0);
2679 /*
2680 * Default to measured freq if none found, PCU will ensure we don't go
2681 * over
2682 */
2683 if (!max_ia_freq)
2684 max_ia_freq = tsc_khz;
2685
2686 /* Convert from kHz to MHz */
2687 max_ia_freq /= 1000;
2688
2b4e57bd
ED		 2689 /*
2690 * For each potential GPU frequency, load a ring frequency we'd like
2691 * to use for memory access. We do this by specifying the IA frequency
2692 * the PCU should use as a reference to determine the ring frequency.
2693 */
c6a828d3 2694 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 2695 gpu_freq--) {
c6a828d3 2696 int diff = dev_priv->rps.max_delay - gpu_freq;
2b4e57bd
ED		 2697
2698 /*
2699 * For GPU frequencies less than 750MHz, just use the lowest
2700 * ring freq.
2701 */
2702 if (gpu_freq < min_freq)
2703 ia_freq = 800;
2704 else
2705 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2706 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
42c0526c 2707 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2b4e57bd 2708
42c0526c
BW		 2709 sandybridge_pcode_write(dev_priv,
2710 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2711 ia_freq | gpu_freq);
2b4e57bd 2712 }
2b4e57bd
ED		 2713}
2714
930ebb46 2715void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 2716{
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718
3e373948
DV		 2719 if (dev_priv->ips.renderctx) {
2720 i915_gem_object_unpin(dev_priv->ips.renderctx);
2721 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2722 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 2723 }
2724
3e373948
DV		 2725 if (dev_priv->ips.pwrctx) {
2726 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2727 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2728 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 2729 }
2730}
2731
930ebb46 2732static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2733{
2734 struct drm_i915_private *dev_priv = dev->dev_private;
2735
2736 if (I915_READ(PWRCTXA)) {
2737 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2738 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2739 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2740 50);
2741
2742 I915_WRITE(PWRCTXA, 0);
2743 POSTING_READ(PWRCTXA);
2744
2745 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2746 POSTING_READ(RSTDBYCTL);
2747 }
2b4e57bd
ED		 2748}
2749
2750static int ironlake_setup_rc6(struct drm_device *dev)
2751{
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753
3e373948
DV		 2754 if (dev_priv->ips.renderctx == NULL)
2755 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2756 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 2757 return -ENOMEM;
2758
3e373948
DV		 2759 if (dev_priv->ips.pwrctx == NULL)
2760 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2761 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 2762 ironlake_teardown_rc6(dev);
2763 return -ENOMEM;
2764 }
2765
2766 return 0;
2767}
2768
930ebb46 2769static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2770{
2771 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 2772 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 2773 bool was_interruptible;
2b4e57bd
ED		 2774 int ret;
2775
2776 /* rc6 disabled by default due to repeated reports of hanging during
2777 * boot and resume.
2778 */
2779 if (!intel_enable_rc6(dev))
2780 return;
2781
79f5b2c7
DV		 2782 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2783
2b4e57bd 2784 ret = ironlake_setup_rc6(dev);
79f5b2c7 2785 if (ret)
2b4e57bd 2786 return;
2b4e57bd 2787
3e960501
CW		 2788 was_interruptible = dev_priv->mm.interruptible;
2789 dev_priv->mm.interruptible = false;
2790
2b4e57bd
ED		 2791 /*
2792 * GPU can automatically power down the render unit if given a page
2793 * to save state.
2794 */
6d90c952 2795 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 2796 if (ret) {
2797 ironlake_teardown_rc6(dev);
3e960501 2798 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 2799 return;
2800 }
2801
6d90c952
DV		 2802 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2803 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 2804 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 2805 MI_MM_SPACE_GTT |
2806 MI_SAVE_EXT_STATE_EN |
2807 MI_RESTORE_EXT_STATE_EN |
2808 MI_RESTORE_INHIBIT);
2809 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2810 intel_ring_emit(ring, MI_NOOP);
2811 intel_ring_emit(ring, MI_FLUSH);
2812 intel_ring_advance(ring);
2b4e57bd
ED		 2813
2814 /*
2815 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2816 * does an implicit flush, combined with MI_FLUSH above, it should be
2817 * safe to assume that renderctx is valid
2818 */
3e960501
CW		 2819 ret = intel_ring_idle(ring);
2820 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 2821 if (ret) {
2822 DRM_ERROR("failed to enable ironlake power power savings\n");
2823 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2824 return;
2825 }
2826
3e373948 2827 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 2828 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 2829}
2830
dde18883
ED		 2831static unsigned long intel_pxfreq(u32 vidfreq)
2832{
2833 unsigned long freq;
2834 int div = (vidfreq & 0x3f0000) >> 16;
2835 int post = (vidfreq & 0x3000) >> 12;
2836 int pre = (vidfreq & 0x7);
2837
2838 if (!pre)
2839 return 0;
2840
2841 freq = ((div * 133333) / ((1<<post) * pre));
2842
2843 return freq;
2844}
2845
eb48eb00
DV		 2846static const struct cparams {
2847 u16 i;
2848 u16 t;
2849 u16 m;
2850 u16 c;
2851} cparams[] = {
2852 { 1, 1333, 301, 28664 },
2853 { 1, 1066, 294, 24460 },
2854 { 1, 800, 294, 25192 },
2855 { 0, 1333, 276, 27605 },
2856 { 0, 1066, 276, 27605 },
2857 { 0, 800, 231, 23784 },
2858};
2859
f531dcb2 2860static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2861{
2862 u64 total_count, diff, ret;
2863 u32 count1, count2, count3, m = 0, c = 0;
2864 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2865 int i;
2866
02d71956
DV		 2867 assert_spin_locked(&mchdev_lock);
2868
20e4d407 2869 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 2870
2871 /* Prevent division-by-zero if we are asking too fast.
2872 * Also, we don't get interesting results if we are polling
2873 * faster than once in 10ms, so just return the saved value
2874 * in such cases.
2875 */
2876 if (diff1 <= 10)
20e4d407 2877 return dev_priv->ips.chipset_power;
eb48eb00
DV		 2878
2879 count1 = I915_READ(DMIEC);
2880 count2 = I915_READ(DDREC);
2881 count3 = I915_READ(CSIEC);
2882
2883 total_count = count1 + count2 + count3;
2884
2885 /* FIXME: handle per-counter overflow */
20e4d407
DV		 2886 if (total_count < dev_priv->ips.last_count1) {
2887 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 2888 diff += total_count;
2889 } else {
20e4d407 2890 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 2891 }
2892
2893 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 2894 if (cparams[i].i == dev_priv->ips.c_m &&
2895 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 2896 m = cparams[i].m;
2897 c = cparams[i].c;
2898 break;
2899 }
2900 }
2901
2902 diff = div_u64(diff, diff1);
2903 ret = ((m * diff) + c);
2904 ret = div_u64(ret, 10);
2905
20e4d407
DV		 2906 dev_priv->ips.last_count1 = total_count;
2907 dev_priv->ips.last_time1 = now;
eb48eb00 2908
20e4d407 2909 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 2910
2911 return ret;
2912}
2913
f531dcb2
CW		 2914unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2915{
2916 unsigned long val;
2917
2918 if (dev_priv->info->gen != 5)
2919 return 0;
2920
2921 spin_lock_irq(&mchdev_lock);
2922
2923 val = __i915_chipset_val(dev_priv);
2924
2925 spin_unlock_irq(&mchdev_lock);
2926
2927 return val;
2928}
2929
eb48eb00
DV		 2930unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2931{
2932 unsigned long m, x, b;
2933 u32 tsfs;
2934
2935 tsfs = I915_READ(TSFS);
2936
2937 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2938 x = I915_READ8(TR1);
2939
2940 b = tsfs & TSFS_INTR_MASK;
2941
2942 return ((m * x) / 127) - b;
2943}
2944
2945static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2946{
2947 static const struct v_table {
2948 u16 vd; /* in .1 mil */
2949 u16 vm; /* in .1 mil */
2950 } v_table[] = {
2951 { 0, 0, },
2952 { 375, 0, },
2953 { 500, 0, },
2954 { 625, 0, },
2955 { 750, 0, },
2956 { 875, 0, },
2957 { 1000, 0, },
2958 { 1125, 0, },
2959 { 4125, 3000, },
2960 { 4125, 3000, },
2961 { 4125, 3000, },
2962 { 4125, 3000, },
2963 { 4125, 3000, },
2964 { 4125, 3000, },
2965 { 4125, 3000, },
2966 { 4125, 3000, },
2967 { 4125, 3000, },
2968 { 4125, 3000, },
2969 { 4125, 3000, },
2970 { 4125, 3000, },
2971 { 4125, 3000, },
2972 { 4125, 3000, },
2973 { 4125, 3000, },
2974 { 4125, 3000, },
2975 { 4125, 3000, },
2976 { 4125, 3000, },
2977 { 4125, 3000, },
2978 { 4125, 3000, },
2979 { 4125, 3000, },
2980 { 4125, 3000, },
2981 { 4125, 3000, },
2982 { 4125, 3000, },
2983 { 4250, 3125, },
2984 { 4375, 3250, },
2985 { 4500, 3375, },
2986 { 4625, 3500, },
2987 { 4750, 3625, },
2988 { 4875, 3750, },
2989 { 5000, 3875, },
2990 { 5125, 4000, },
2991 { 5250, 4125, },
2992 { 5375, 4250, },
2993 { 5500, 4375, },
2994 { 5625, 4500, },
2995 { 5750, 4625, },
2996 { 5875, 4750, },
2997 { 6000, 4875, },
2998 { 6125, 5000, },
2999 { 6250, 5125, },
3000 { 6375, 5250, },
3001 { 6500, 5375, },
3002 { 6625, 5500, },
3003 { 6750, 5625, },
3004 { 6875, 5750, },
3005 { 7000, 5875, },
3006 { 7125, 6000, },
3007 { 7250, 6125, },
3008 { 7375, 6250, },
3009 { 7500, 6375, },
3010 { 7625, 6500, },
3011 { 7750, 6625, },
3012 { 7875, 6750, },
3013 { 8000, 6875, },
3014 { 8125, 7000, },
3015 { 8250, 7125, },
3016 { 8375, 7250, },
3017 { 8500, 7375, },
3018 { 8625, 7500, },
3019 { 8750, 7625, },
3020 { 8875, 7750, },
3021 { 9000, 7875, },
3022 { 9125, 8000, },
3023 { 9250, 8125, },
3024 { 9375, 8250, },
3025 { 9500, 8375, },
3026 { 9625, 8500, },
3027 { 9750, 8625, },
3028 { 9875, 8750, },
3029 { 10000, 8875, },
3030 { 10125, 9000, },
3031 { 10250, 9125, },
3032 { 10375, 9250, },
3033 { 10500, 9375, },
3034 { 10625, 9500, },
3035 { 10750, 9625, },
3036 { 10875, 9750, },
3037 { 11000, 9875, },
3038 { 11125, 10000, },
3039 { 11250, 10125, },
3040 { 11375, 10250, },
3041 { 11500, 10375, },
3042 { 11625, 10500, },
3043 { 11750, 10625, },
3044 { 11875, 10750, },
3045 { 12000, 10875, },
3046 { 12125, 11000, },
3047 { 12250, 11125, },
3048 { 12375, 11250, },
3049 { 12500, 11375, },
3050 { 12625, 11500, },
3051 { 12750, 11625, },
3052 { 12875, 11750, },
3053 { 13000, 11875, },
3054 { 13125, 12000, },
3055 { 13250, 12125, },
3056 { 13375, 12250, },
3057 { 13500, 12375, },
3058 { 13625, 12500, },
3059 { 13750, 12625, },
3060 { 13875, 12750, },
3061 { 14000, 12875, },
3062 { 14125, 13000, },
3063 { 14250, 13125, },
3064 { 14375, 13250, },
3065 { 14500, 13375, },
3066 { 14625, 13500, },
3067 { 14750, 13625, },
3068 { 14875, 13750, },
3069 { 15000, 13875, },
3070 { 15125, 14000, },
3071 { 15250, 14125, },
3072 { 15375, 14250, },
3073 { 15500, 14375, },
3074 { 15625, 14500, },
3075 { 15750, 14625, },
3076 { 15875, 14750, },
3077 { 16000, 14875, },
3078 { 16125, 15000, },
3079 };
3080 if (dev_priv->info->is_mobile)
3081 return v_table[pxvid].vm;
3082 else
3083 return v_table[pxvid].vd;
3084}
3085
02d71956 3086static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3087{
3088 struct timespec now, diff1;
3089 u64 diff;
3090 unsigned long diffms;
3091 u32 count;
3092
02d71956 3093 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3094
3095 getrawmonotonic(&now);
20e4d407 3096 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3097
3098 /* Don't divide by 0 */
3099 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3100 if (!diffms)
3101 return;
3102
3103 count = I915_READ(GFXEC);
3104
20e4d407
DV		 3105 if (count < dev_priv->ips.last_count2) {
3106 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 3107 diff += count;
3108 } else {
20e4d407 3109 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 3110 }
3111
20e4d407
DV		 3112 dev_priv->ips.last_count2 = count;
3113 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 3114
3115 /* More magic constants... */
3116 diff = diff * 1181;
3117 diff = div_u64(diff, diffms * 10);
20e4d407 3118 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 3119}
3120
02d71956
DV		 3121void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3122{
3123 if (dev_priv->info->gen != 5)
3124 return;
3125
9270388e 3126 spin_lock_irq(&mchdev_lock);
02d71956
DV		 3127
3128 __i915_update_gfx_val(dev_priv);
3129
9270388e 3130 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3131}
3132
f531dcb2 3133static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3134{
3135 unsigned long t, corr, state1, corr2, state2;
3136 u32 pxvid, ext_v;
3137
02d71956
DV		 3138 assert_spin_locked(&mchdev_lock);
3139
c6a828d3 3140 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3141 pxvid = (pxvid >> 24) & 0x7f;
3142 ext_v = pvid_to_extvid(dev_priv, pxvid);
3143
3144 state1 = ext_v;
3145
3146 t = i915_mch_val(dev_priv);
3147
3148 /* Revel in the empirically derived constants */
3149
3150 /* Correction factor in 1/100000 units */
3151 if (t > 80)
3152 corr = ((t * 2349) + 135940);
3153 else if (t >= 50)
3154 corr = ((t * 964) + 29317);
3155 else /* < 50 */
3156 corr = ((t * 301) + 1004);
3157
3158 corr = corr * ((150142 * state1) / 10000 - 78642);
3159 corr /= 100000;
20e4d407 3160 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3161
3162 state2 = (corr2 * state1) / 10000;
3163 state2 /= 100; /* convert to mW */
3164
02d71956 3165 __i915_update_gfx_val(dev_priv);
eb48eb00 3166
20e4d407 3167 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3168}
3169
f531dcb2
CW		 3170unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3171{
3172 unsigned long val;
3173
3174 if (dev_priv->info->gen != 5)
3175 return 0;
3176
3177 spin_lock_irq(&mchdev_lock);
3178
3179 val = __i915_gfx_val(dev_priv);
3180
3181 spin_unlock_irq(&mchdev_lock);
3182
3183 return val;
3184}
3185
eb48eb00
DV		 3186/**
3187 * i915_read_mch_val - return value for IPS use
3188 *
3189 * Calculate and return a value for the IPS driver to use when deciding whether
3190 * we have thermal and power headroom to increase CPU or GPU power budget.
3191 */
3192unsigned long i915_read_mch_val(void)
3193{
3194 struct drm_i915_private *dev_priv;
3195 unsigned long chipset_val, graphics_val, ret = 0;
3196
9270388e 3197 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3198 if (!i915_mch_dev)
3199 goto out_unlock;
3200 dev_priv = i915_mch_dev;
3201
f531dcb2
CW		 3202 chipset_val = __i915_chipset_val(dev_priv);
3203 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3204
3205 ret = chipset_val + graphics_val;
3206
3207out_unlock:
9270388e 3208 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3209
3210 return ret;
3211}
3212EXPORT_SYMBOL_GPL(i915_read_mch_val);
3213
3214/**
3215 * i915_gpu_raise - raise GPU frequency limit
3216 *
3217 * Raise the limit; IPS indicates we have thermal headroom.
3218 */
3219bool i915_gpu_raise(void)
3220{
3221 struct drm_i915_private *dev_priv;
3222 bool ret = true;
3223
9270388e 3224 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3225 if (!i915_mch_dev) {
3226 ret = false;
3227 goto out_unlock;
3228 }
3229 dev_priv = i915_mch_dev;
3230
20e4d407
DV		 3231 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3232 dev_priv->ips.max_delay--;
eb48eb00
DV		 3233
3234out_unlock:
9270388e 3235 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3236
3237 return ret;
3238}
3239EXPORT_SYMBOL_GPL(i915_gpu_raise);
3240
3241/**
3242 * i915_gpu_lower - lower GPU frequency limit
3243 *
3244 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3245 * frequency maximum.
3246 */
3247bool i915_gpu_lower(void)
3248{
3249 struct drm_i915_private *dev_priv;
3250 bool ret = true;
3251
9270388e 3252 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3253 if (!i915_mch_dev) {
3254 ret = false;
3255 goto out_unlock;
3256 }
3257 dev_priv = i915_mch_dev;
3258
20e4d407
DV		 3259 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3260 dev_priv->ips.max_delay++;
eb48eb00
DV		 3261
3262out_unlock:
9270388e 3263 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3264
3265 return ret;
3266}
3267EXPORT_SYMBOL_GPL(i915_gpu_lower);
3268
3269/**
3270 * i915_gpu_busy - indicate GPU business to IPS
3271 *
3272 * Tell the IPS driver whether or not the GPU is busy.
3273 */
3274bool i915_gpu_busy(void)
3275{
3276 struct drm_i915_private *dev_priv;
f047e395 3277 struct intel_ring_buffer *ring;
eb48eb00 3278 bool ret = false;
f047e395 3279 int i;
eb48eb00 3280
9270388e 3281 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3282 if (!i915_mch_dev)
3283 goto out_unlock;
3284 dev_priv = i915_mch_dev;
3285
f047e395
CW		 3286 for_each_ring(ring, dev_priv, i)
3287 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3288
3289out_unlock:
9270388e 3290 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3291
3292 return ret;
3293}
3294EXPORT_SYMBOL_GPL(i915_gpu_busy);
3295
3296/**
3297 * i915_gpu_turbo_disable - disable graphics turbo
3298 *
3299 * Disable graphics turbo by resetting the max frequency and setting the
3300 * current frequency to the default.
3301 */
3302bool i915_gpu_turbo_disable(void)
3303{
3304 struct drm_i915_private *dev_priv;
3305 bool ret = true;
3306
9270388e 3307 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3308 if (!i915_mch_dev) {
3309 ret = false;
3310 goto out_unlock;
3311 }
3312 dev_priv = i915_mch_dev;
3313
20e4d407 3314 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 3315
20e4d407 3316 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 3317 ret = false;
3318
3319out_unlock:
9270388e 3320 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3321
3322 return ret;
3323}
3324EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3325
3326/**
3327 * Tells the intel_ips driver that the i915 driver is now loaded, if
3328 * IPS got loaded first.
3329 *
3330 * This awkward dance is so that neither module has to depend on the
3331 * other in order for IPS to do the appropriate communication of
3332 * GPU turbo limits to i915.
3333 */
3334static void
3335ips_ping_for_i915_load(void)
3336{
3337 void (*link)(void);
3338
3339 link = symbol_get(ips_link_to_i915_driver);
3340 if (link) {
3341 link();
3342 symbol_put(ips_link_to_i915_driver);
3343 }
3344}
3345
3346void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3347{
02d71956
DV		 3348 /* We only register the i915 ips part with intel-ips once everything is
3349 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 3350 spin_lock_irq(&mchdev_lock);
eb48eb00 3351 i915_mch_dev = dev_priv;
9270388e 3352 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3353
3354 ips_ping_for_i915_load();
3355}
3356
3357void intel_gpu_ips_teardown(void)
3358{
9270388e 3359 spin_lock_irq(&mchdev_lock);
eb48eb00 3360 i915_mch_dev = NULL;
9270388e 3361 spin_unlock_irq(&mchdev_lock);
eb48eb00 3362}
8090c6b9 3363static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3364{
3365 struct drm_i915_private *dev_priv = dev->dev_private;
3366 u32 lcfuse;
3367 u8 pxw[16];
3368 int i;
3369
3370 /* Disable to program */
3371 I915_WRITE(ECR, 0);
3372 POSTING_READ(ECR);
3373
3374 /* Program energy weights for various events */
3375 I915_WRITE(SDEW, 0x15040d00);
3376 I915_WRITE(CSIEW0, 0x007f0000);
3377 I915_WRITE(CSIEW1, 0x1e220004);
3378 I915_WRITE(CSIEW2, 0x04000004);
3379
3380 for (i = 0; i < 5; i++)
3381 I915_WRITE(PEW + (i * 4), 0);
3382 for (i = 0; i < 3; i++)
3383 I915_WRITE(DEW + (i * 4), 0);
3384
3385 /* Program P-state weights to account for frequency power adjustment */
3386 for (i = 0; i < 16; i++) {
3387 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3388 unsigned long freq = intel_pxfreq(pxvidfreq);
3389 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3390 PXVFREQ_PX_SHIFT;
3391 unsigned long val;
3392
3393 val = vid * vid;
3394 val *= (freq / 1000);
3395 val *= 255;
3396 val /= (127*127*900);
3397 if (val > 0xff)
3398 DRM_ERROR("bad pxval: %ld\n", val);
3399 pxw[i] = val;
3400 }
3401 /* Render standby states get 0 weight */
3402 pxw[14] = 0;
3403 pxw[15] = 0;
3404
3405 for (i = 0; i < 4; i++) {
3406 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3407 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3408 I915_WRITE(PXW + (i * 4), val);
3409 }
3410
3411 /* Adjust magic regs to magic values (more experimental results) */
3412 I915_WRITE(OGW0, 0);
3413 I915_WRITE(OGW1, 0);
3414 I915_WRITE(EG0, 0x00007f00);
3415 I915_WRITE(EG1, 0x0000000e);
3416 I915_WRITE(EG2, 0x000e0000);
3417 I915_WRITE(EG3, 0x68000300);
3418 I915_WRITE(EG4, 0x42000000);
3419 I915_WRITE(EG5, 0x00140031);
3420 I915_WRITE(EG6, 0);
3421 I915_WRITE(EG7, 0);
3422
3423 for (i = 0; i < 8; i++)
3424 I915_WRITE(PXWL + (i * 4), 0);
3425
3426 /* Enable PMON + select events */
3427 I915_WRITE(ECR, 0x80000019);
3428
3429 lcfuse = I915_READ(LCFUSE02);
3430
20e4d407 3431 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 3432}
3433
8090c6b9
DV		 3434void intel_disable_gt_powersave(struct drm_device *dev)
3435{
1a01ab3b
JB		 3436 struct drm_i915_private *dev_priv = dev->dev_private;
3437
930ebb46 3438 if (IS_IRONLAKE_M(dev)) {
8090c6b9 3439 ironlake_disable_drps(dev);
930ebb46
DV		 3440 ironlake_disable_rc6(dev);
3441 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
1a01ab3b 3442 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4fc688ce 3443 mutex_lock(&dev_priv->rps.hw_lock);
8090c6b9 3444 gen6_disable_rps(dev);
4fc688ce 3445 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 3446 }
8090c6b9
DV		 3447}
3448
1a01ab3b
JB		 3449static void intel_gen6_powersave_work(struct work_struct *work)
3450{
3451 struct drm_i915_private *dev_priv =
3452 container_of(work, struct drm_i915_private,
3453 rps.delayed_resume_work.work);
3454 struct drm_device *dev = dev_priv->dev;
3455
4fc688ce 3456 mutex_lock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3457 gen6_enable_rps(dev);
3458 gen6_update_ring_freq(dev);
4fc688ce 3459 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3460}
3461
8090c6b9
DV		 3462void intel_enable_gt_powersave(struct drm_device *dev)
3463{
1a01ab3b
JB		 3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465
8090c6b9
DV		 3466 if (IS_IRONLAKE_M(dev)) {
3467 ironlake_enable_drps(dev);
3468 ironlake_enable_rc6(dev);
3469 intel_init_emon(dev);
7cf50fc8 3470 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1a01ab3b
JB		 3471 /*
3472 * PCU communication is slow and this doesn't need to be
3473 * done at any specific time, so do this out of our fast path
3474 * to make resume and init faster.
3475 */
3476 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3477 round_jiffies_up_relative(HZ));
8090c6b9
DV		 3478 }
3479}
3480
3107bd48
DV		 3481static void ibx_init_clock_gating(struct drm_device *dev)
3482{
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484
3485 /*
3486 * On Ibex Peak and Cougar Point, we need to disable clock
3487 * gating for the panel power sequencer or it will fail to
3488 * start up when no ports are active.
3489 */
3490 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3491}
3492
1fa61106 3493static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3494{
3495 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 3496 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 3497
3498 /* Required for FBC */
4d47e4f5
DL		 3499 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3500 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3501 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3502
3503 I915_WRITE(PCH_3DCGDIS0,
3504 MARIUNIT_CLOCK_GATE_DISABLE |
3505 SVSMUNIT_CLOCK_GATE_DISABLE);
3506 I915_WRITE(PCH_3DCGDIS1,
3507 VFMUNIT_CLOCK_GATE_DISABLE);
3508
6f1d69b0
ED		 3509 /*
3510 * According to the spec the following bits should be set in
3511 * order to enable memory self-refresh
3512 * The bit 22/21 of 0x42004
3513 * The bit 5 of 0x42020
3514 * The bit 15 of 0x45000
3515 */
3516 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3517 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3518 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 3519 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3520 I915_WRITE(DISP_ARB_CTL,
3521 (I915_READ(DISP_ARB_CTL) |
3522 DISP_FBC_WM_DIS));
3523 I915_WRITE(WM3_LP_ILK, 0);
3524 I915_WRITE(WM2_LP_ILK, 0);
3525 I915_WRITE(WM1_LP_ILK, 0);
3526
3527 /*
3528 * Based on the document from hardware guys the following bits
3529 * should be set unconditionally in order to enable FBC.
3530 * The bit 22 of 0x42000
3531 * The bit 22 of 0x42004
3532 * The bit 7,8,9 of 0x42020.
3533 */
3534 if (IS_IRONLAKE_M(dev)) {
3535 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3536 I915_READ(ILK_DISPLAY_CHICKEN1) |
3537 ILK_FBCQ_DIS);
3538 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3539 I915_READ(ILK_DISPLAY_CHICKEN2) |
3540 ILK_DPARB_GATE);
6f1d69b0
ED		 3541 }
3542
4d47e4f5
DL		 3543 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3544
6f1d69b0
ED		 3545 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3546 I915_READ(ILK_DISPLAY_CHICKEN2) |
3547 ILK_ELPIN_409_SELECT);
3548 I915_WRITE(_3D_CHICKEN2,
3549 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3550 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374
DV		 3551
3552 /* WaDisableRenderCachePipelinedFlush */
3553 I915_WRITE(CACHE_MODE_0,
3554 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 3555
3556 ibx_init_clock_gating(dev);
3557}
3558
3559static void cpt_init_clock_gating(struct drm_device *dev)
3560{
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 int pipe;
3563
3564 /*
3565 * On Ibex Peak and Cougar Point, we need to disable clock
3566 * gating for the panel power sequencer or it will fail to
3567 * start up when no ports are active.
3568 */
3569 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3570 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3571 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 3572 /* The below fixes the weird display corruption, a few pixels shifted
3573 * downward, on (only) LVDS of some HP laptops with IVY.
3574 */
3575 for_each_pipe(pipe)
3576 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
3107bd48
DV		 3577 /* WADP0ClockGatingDisable */
3578 for_each_pipe(pipe) {
3579 I915_WRITE(TRANS_CHICKEN1(pipe),
3580 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3581 }
6f1d69b0
ED		 3582}
3583
1fa61106 3584static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3585{
3586 struct drm_i915_private *dev_priv = dev->dev_private;
3587 int pipe;
231e54f6 3588 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 3589
231e54f6 3590 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 3591
3592 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3593 I915_READ(ILK_DISPLAY_CHICKEN2) |
3594 ILK_ELPIN_409_SELECT);
3595
4283908e
DV		 3596 /* WaDisableHiZPlanesWhenMSAAEnabled */
3597 I915_WRITE(_3D_CHICKEN,
3598 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3599
6547fbdb
DV		 3600 /* WaSetupGtModeTdRowDispatch */
3601 if (IS_SNB_GT1(dev))
3602 I915_WRITE(GEN6_GT_MODE,
3603 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3604
6f1d69b0
ED		 3605 I915_WRITE(WM3_LP_ILK, 0);
3606 I915_WRITE(WM2_LP_ILK, 0);
3607 I915_WRITE(WM1_LP_ILK, 0);
3608
6f1d69b0 3609 I915_WRITE(CACHE_MODE_0,
50743298 3610 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3611
3612 I915_WRITE(GEN6_UCGCTL1,
3613 I915_READ(GEN6_UCGCTL1) |
3614 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3615 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3616
3617 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3618 * gating disable must be set. Failure to set it results in
3619 * flickering pixels due to Z write ordering failures after
3620 * some amount of runtime in the Mesa "fire" demo, and Unigine
3621 * Sanctuary and Tropics, and apparently anything else with
3622 * alpha test or pixel discard.
3623 *
3624 * According to the spec, bit 11 (RCCUNIT) must also be set,
3625 * but we didn't debug actual testcases to find it out.
0f846f81
JB		 3626 *
3627 * Also apply WaDisableVDSUnitClockGating and
3628 * WaDisableRCPBUnitClockGating.
6f1d69b0
ED		 3629 */
3630 I915_WRITE(GEN6_UCGCTL2,
0f846f81 3631 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 3632 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3633 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3634
3635 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 3636 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3637 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 3638
3639 /*
3640 * According to the spec the following bits should be
3641 * set in order to enable memory self-refresh and fbc:
3642 * The bit21 and bit22 of 0x42000
3643 * The bit21 and bit22 of 0x42004
3644 * The bit5 and bit7 of 0x42020
3645 * The bit14 of 0x70180
3646 * The bit14 of 0x71180
3647 */
3648 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3649 I915_READ(ILK_DISPLAY_CHICKEN1) |
3650 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3651 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3652 I915_READ(ILK_DISPLAY_CHICKEN2) |
3653 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 3654 I915_WRITE(ILK_DSPCLK_GATE_D,
3655 I915_READ(ILK_DSPCLK_GATE_D) |
3656 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3657 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 3658
b3bf0766 3659 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3660 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3661 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3662
6f1d69b0
ED		 3663 for_each_pipe(pipe) {
3664 I915_WRITE(DSPCNTR(pipe),
3665 I915_READ(DSPCNTR(pipe)) |
3666 DISPPLANE_TRICKLE_FEED_DISABLE);
3667 intel_flush_display_plane(dev_priv, pipe);
3668 }
f8f2ac9a
BW		 3669
3670 /* The default value should be 0x200 according to docs, but the two
3671 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3672 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3673 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 3674
3675 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3676}
3677
3678static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3679{
3680 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3681
3682 reg &= ~GEN7_FF_SCHED_MASK;
3683 reg |= GEN7_FF_TS_SCHED_HW;
3684 reg |= GEN7_FF_VS_SCHED_HW;
3685 reg |= GEN7_FF_DS_SCHED_HW;
3686
3687 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3688}
3689
17a303ec
PZ		 3690static void lpt_init_clock_gating(struct drm_device *dev)
3691{
3692 struct drm_i915_private *dev_priv = dev->dev_private;
3693
3694 /*
3695 * TODO: this bit should only be enabled when really needed, then
3696 * disabled when not needed anymore in order to save power.
3697 */
3698 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3699 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3700 I915_READ(SOUTH_DSPCLK_GATE_D) |
3701 PCH_LP_PARTITION_LEVEL_DISABLE);
3702}
3703
cad2a2d7
ED		 3704static void haswell_init_clock_gating(struct drm_device *dev)
3705{
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707 int pipe;
cad2a2d7
ED		 3708
3709 I915_WRITE(WM3_LP_ILK, 0);
3710 I915_WRITE(WM2_LP_ILK, 0);
3711 I915_WRITE(WM1_LP_ILK, 0);
3712
3713 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3714 * This implements the WaDisableRCZUnitClockGating workaround.
3715 */
3716 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3717
cad2a2d7
ED		 3718 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3719 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3720 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3721
3722 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3723 I915_WRITE(GEN7_L3CNTLREG1,
3724 GEN7_WA_FOR_GEN7_L3_CONTROL);
3725 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3726 GEN7_WA_L3_CHICKEN_MODE);
3727
3728 /* This is required by WaCatErrorRejectionIssue */
3729 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3730 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3731 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3732
3733 for_each_pipe(pipe) {
3734 I915_WRITE(DSPCNTR(pipe),
3735 I915_READ(DSPCNTR(pipe)) |
3736 DISPPLANE_TRICKLE_FEED_DISABLE);
3737 intel_flush_display_plane(dev_priv, pipe);
3738 }
3739
3740 gen7_setup_fixed_func_scheduler(dev_priv);
3741
3742 /* WaDisable4x2SubspanOptimization */
3743 I915_WRITE(CACHE_MODE_1,
3744 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 3745
b3bf0766
PZ		 3746 /* WaMbcDriverBootEnable */
3747 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3748 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3749
1544d9d5
ED		 3750 /* XXX: This is a workaround for early silicon revisions and should be
3751 * removed later.
3752 */
3753 I915_WRITE(WM_DBG,
3754 I915_READ(WM_DBG) |
3755 WM_DBG_DISALLOW_MULTIPLE_LP |
3756 WM_DBG_DISALLOW_SPRITE |
3757 WM_DBG_DISALLOW_MAXFIFO);
3758
17a303ec 3759 lpt_init_clock_gating(dev);
cad2a2d7
ED		 3760}
3761
1fa61106 3762static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3763{
3764 struct drm_i915_private *dev_priv = dev->dev_private;
3765 int pipe;
20848223 3766 uint32_t snpcr;
6f1d69b0 3767
6f1d69b0
ED		 3768 I915_WRITE(WM3_LP_ILK, 0);
3769 I915_WRITE(WM2_LP_ILK, 0);
3770 I915_WRITE(WM1_LP_ILK, 0);
3771
231e54f6 3772 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3773
87f8020e
JB		 3774 /* WaDisableEarlyCull */
3775 I915_WRITE(_3D_CHICKEN3,
3776 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3777
62cb944f 3778 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3779 I915_WRITE(IVB_CHICKEN3,
3780 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3781 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3782
12f3382b
JB		 3783 /* WaDisablePSDDualDispatchEnable */
3784 if (IS_IVB_GT1(dev))
3785 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3786 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3787 else
3788 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3789 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3790
6f1d69b0
ED		 3791 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3792 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3793 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3794
3795 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3796 I915_WRITE(GEN7_L3CNTLREG1,
3797 GEN7_WA_FOR_GEN7_L3_CONTROL);
3798 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 3799 GEN7_WA_L3_CHICKEN_MODE);
3800 if (IS_IVB_GT1(dev))
3801 I915_WRITE(GEN7_ROW_CHICKEN2,
3802 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3803 else
3804 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3805 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3806
6f1d69b0 3807
61939d97
JB		 3808 /* WaForceL3Serialization */
3809 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3810 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3811
0f846f81
JB		 3812 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3813 * gating disable must be set. Failure to set it results in
3814 * flickering pixels due to Z write ordering failures after
3815 * some amount of runtime in the Mesa "fire" demo, and Unigine
3816 * Sanctuary and Tropics, and apparently anything else with
3817 * alpha test or pixel discard.
3818 *
3819 * According to the spec, bit 11 (RCCUNIT) must also be set,
3820 * but we didn't debug actual testcases to find it out.
3821 *
3822 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3823 * This implements the WaDisableRCZUnitClockGating workaround.
3824 */
3825 I915_WRITE(GEN6_UCGCTL2,
3826 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3827 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3828
6f1d69b0
ED		 3829 /* This is required by WaCatErrorRejectionIssue */
3830 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3831 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3832 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3833
3834 for_each_pipe(pipe) {
3835 I915_WRITE(DSPCNTR(pipe),
3836 I915_READ(DSPCNTR(pipe)) |
3837 DISPPLANE_TRICKLE_FEED_DISABLE);
3838 intel_flush_display_plane(dev_priv, pipe);
3839 }
3840
b3bf0766 3841 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3842 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3843 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3844
6f1d69b0 3845 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f
DV		 3846
3847 /* WaDisable4x2SubspanOptimization */
3848 I915_WRITE(CACHE_MODE_1,
3849 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 3850
3851 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3852 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3853 snpcr |= GEN6_MBC_SNPCR_MED;
3854 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48
DV		 3855
3856 cpt_init_clock_gating(dev);
6f1d69b0
ED		 3857}
3858
1fa61106 3859static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3860{
3861 struct drm_i915_private *dev_priv = dev->dev_private;
3862 int pipe;
6f1d69b0
ED		 3863
3864 I915_WRITE(WM3_LP_ILK, 0);
3865 I915_WRITE(WM2_LP_ILK, 0);
3866 I915_WRITE(WM1_LP_ILK, 0);
3867
231e54f6 3868 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3869
87f8020e
JB		 3870 /* WaDisableEarlyCull */
3871 I915_WRITE(_3D_CHICKEN3,
3872 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3873
62cb944f 3874 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3875 I915_WRITE(IVB_CHICKEN3,
3876 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3877 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3878
12f3382b
JB		 3879 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3880 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3881
6f1d69b0
ED		 3882 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3883 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3884 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3885
3886 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
d0cf5ead 3887 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 3888 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3889
61939d97
JB		 3890 /* WaForceL3Serialization */
3891 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3892 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3893
8ab43976
JB		 3894 /* WaDisableDopClockGating */
3895 I915_WRITE(GEN7_ROW_CHICKEN2,
3896 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3897
5c9664d7
JB		 3898 /* WaForceL3Serialization */
3899 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3900 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3901
6f1d69b0
ED		 3902 /* This is required by WaCatErrorRejectionIssue */
3903 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3904 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3905 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3906
b3bf0766 3907 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3908 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3909 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3910
0f846f81
JB		 3911
3912 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3913 * gating disable must be set. Failure to set it results in
3914 * flickering pixels due to Z write ordering failures after
3915 * some amount of runtime in the Mesa "fire" demo, and Unigine
3916 * Sanctuary and Tropics, and apparently anything else with
3917 * alpha test or pixel discard.
3918 *
3919 * According to the spec, bit 11 (RCCUNIT) must also be set,
3920 * but we didn't debug actual testcases to find it out.
3921 *
3922 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3923 * This implements the WaDisableRCZUnitClockGating workaround.
3924 *
3925 * Also apply WaDisableVDSUnitClockGating and
3926 * WaDisableRCPBUnitClockGating.
3927 */
3928 I915_WRITE(GEN6_UCGCTL2,
3929 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 3930 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 3931 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3932 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3933 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3934
e3f33d46
JB		 3935 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3936
6f1d69b0
ED		 3937 for_each_pipe(pipe) {
3938 I915_WRITE(DSPCNTR(pipe),
3939 I915_READ(DSPCNTR(pipe)) |
3940 DISPPLANE_TRICKLE_FEED_DISABLE);
3941 intel_flush_display_plane(dev_priv, pipe);
3942 }
3943
6b26c86d
DV		 3944 I915_WRITE(CACHE_MODE_1,
3945 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f
JB		 3946
3947 /*
3948 * On ValleyView, the GUnit needs to signal the GT
3949 * when flip and other events complete. So enable
3950 * all the GUnit->GT interrupts here
3951 */
3952 I915_WRITE(VLV_DPFLIPSTAT, PIPEB_LINE_COMPARE_INT_EN |
3953 PIPEB_HLINE_INT_EN | PIPEB_VBLANK_INT_EN |
3954 SPRITED_FLIPDONE_INT_EN | SPRITEC_FLIPDONE_INT_EN |
3955 PLANEB_FLIPDONE_INT_EN | PIPEA_LINE_COMPARE_INT_EN |
3956 PIPEA_HLINE_INT_EN | PIPEA_VBLANK_INT_EN |
3957 SPRITEB_FLIPDONE_INT_EN | SPRITEA_FLIPDONE_INT_EN |
3958 PLANEA_FLIPDONE_INT_EN);
2d809570
JB		 3959
3960 /*
3961 * WaDisableVLVClockGating_VBIIssue
3962 * Disable clock gating on th GCFG unit to prevent a delay
3963 * in the reporting of vblank events.
3964 */
3965 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 3966}
3967
1fa61106 3968static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3969{
3970 struct drm_i915_private *dev_priv = dev->dev_private;
3971 uint32_t dspclk_gate;
3972
3973 I915_WRITE(RENCLK_GATE_D1, 0);
3974 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
3975 GS_UNIT_CLOCK_GATE_DISABLE |
3976 CL_UNIT_CLOCK_GATE_DISABLE);
3977 I915_WRITE(RAMCLK_GATE_D, 0);
3978 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
3979 OVRUNIT_CLOCK_GATE_DISABLE |
3980 OVCUNIT_CLOCK_GATE_DISABLE;
3981 if (IS_GM45(dev))
3982 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
3983 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 3984
3985 /* WaDisableRenderCachePipelinedFlush */
3986 I915_WRITE(CACHE_MODE_0,
3987 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 3988}
3989
1fa61106 3990static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3991{
3992 struct drm_i915_private *dev_priv = dev->dev_private;
3993
3994 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
3995 I915_WRITE(RENCLK_GATE_D2, 0);
3996 I915_WRITE(DSPCLK_GATE_D, 0);
3997 I915_WRITE(RAMCLK_GATE_D, 0);
3998 I915_WRITE16(DEUC, 0);
3999}
4000
1fa61106 4001static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4002{
4003 struct drm_i915_private *dev_priv = dev->dev_private;
4004
4005 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4006 I965_RCC_CLOCK_GATE_DISABLE |
4007 I965_RCPB_CLOCK_GATE_DISABLE |
4008 I965_ISC_CLOCK_GATE_DISABLE |
4009 I965_FBC_CLOCK_GATE_DISABLE);
4010 I915_WRITE(RENCLK_GATE_D2, 0);
4011}
4012
1fa61106 4013static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4014{
4015 struct drm_i915_private *dev_priv = dev->dev_private;
4016 u32 dstate = I915_READ(D_STATE);
4017
4018 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4019 DSTATE_DOT_CLOCK_GATING;
4020 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4021
4022 if (IS_PINEVIEW(dev))
4023 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4024
4025 /* IIR "flip pending" means done if this bit is set */
4026 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4027}
4028
1fa61106 4029static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4030{
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032
4033 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4034}
4035
1fa61106 4036static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4037{
4038 struct drm_i915_private *dev_priv = dev->dev_private;
4039
4040 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4041}
4042
6f1d69b0
ED		 4043void intel_init_clock_gating(struct drm_device *dev)
4044{
4045 struct drm_i915_private *dev_priv = dev->dev_private;
4046
4047 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4048}
4049
d0d3e513
ED		 4050/* Starting with Haswell, we have different power wells for
4051 * different parts of the GPU. This attempts to enable them all.
4052 */
4053void intel_init_power_wells(struct drm_device *dev)
4054{
4055 struct drm_i915_private *dev_priv = dev->dev_private;
4056 unsigned long power_wells[] = {
4057 HSW_PWR_WELL_CTL1,
4058 HSW_PWR_WELL_CTL2,
4059 HSW_PWR_WELL_CTL4
4060 };
4061 int i;
4062
4063 if (!IS_HASWELL(dev))
4064 return;
4065
4066 mutex_lock(&dev->struct_mutex);
4067
4068 for (i = 0; i < ARRAY_SIZE(power_wells); i++) {
4069 int well = I915_READ(power_wells[i]);
4070
4071 if ((well & HSW_PWR_WELL_STATE) == 0) {
4072 I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
263b30d4 4073 if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
d0d3e513
ED		 4074 DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
4075 }
4076 }
4077
4078 mutex_unlock(&dev->struct_mutex);
4079}
4080
1fa61106
ED		 4081/* Set up chip specific power management-related functions */
4082void intel_init_pm(struct drm_device *dev)
4083{
4084 struct drm_i915_private *dev_priv = dev->dev_private;
4085
4086 if (I915_HAS_FBC(dev)) {
4087 if (HAS_PCH_SPLIT(dev)) {
4088 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4089 dev_priv->display.enable_fbc = ironlake_enable_fbc;
4090 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4091 } else if (IS_GM45(dev)) {
4092 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4093 dev_priv->display.enable_fbc = g4x_enable_fbc;
4094 dev_priv->display.disable_fbc = g4x_disable_fbc;
4095 } else if (IS_CRESTLINE(dev)) {
4096 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4097 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4098 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4099 }
4100 /* 855GM needs testing */
4101 }
4102
c921aba8
DV		 4103 /* For cxsr */
4104 if (IS_PINEVIEW(dev))
4105 i915_pineview_get_mem_freq(dev);
4106 else if (IS_GEN5(dev))
4107 i915_ironlake_get_mem_freq(dev);
4108
1fa61106
ED		 4109 /* For FIFO watermark updates */
4110 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 4111 if (IS_GEN5(dev)) {
4112 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4113 dev_priv->display.update_wm = ironlake_update_wm;
4114 else {
4115 DRM_DEBUG_KMS("Failed to get proper latency. "
4116 "Disable CxSR\n");
4117 dev_priv->display.update_wm = NULL;
4118 }
4119 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4120 } else if (IS_GEN6(dev)) {
4121 if (SNB_READ_WM0_LATENCY()) {
4122 dev_priv->display.update_wm = sandybridge_update_wm;
4123 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4124 } else {
4125 DRM_DEBUG_KMS("Failed to read display plane latency. "
4126 "Disable CxSR\n");
4127 dev_priv->display.update_wm = NULL;
4128 }
4129 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4130 } else if (IS_IVYBRIDGE(dev)) {
4131 /* FIXME: detect B0+ stepping and use auto training */
4132 if (SNB_READ_WM0_LATENCY()) {
c43d0188 4133 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 4134 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4135 } else {
4136 DRM_DEBUG_KMS("Failed to read display plane latency. "
4137 "Disable CxSR\n");
4138 dev_priv->display.update_wm = NULL;
4139 }
4140 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb
ED		 4141 } else if (IS_HASWELL(dev)) {
4142 if (SNB_READ_WM0_LATENCY()) {
4143 dev_priv->display.update_wm = sandybridge_update_wm;
4144 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 4145 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 4146 } else {
4147 DRM_DEBUG_KMS("Failed to read display plane latency. "
4148 "Disable CxSR\n");
4149 dev_priv->display.update_wm = NULL;
4150 }
cad2a2d7 4151 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 4152 } else
4153 dev_priv->display.update_wm = NULL;
4154 } else if (IS_VALLEYVIEW(dev)) {
4155 dev_priv->display.update_wm = valleyview_update_wm;
4156 dev_priv->display.init_clock_gating =
4157 valleyview_init_clock_gating;
1fa61106
ED		 4158 } else if (IS_PINEVIEW(dev)) {
4159 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4160 dev_priv->is_ddr3,
4161 dev_priv->fsb_freq,
4162 dev_priv->mem_freq)) {
4163 DRM_INFO("failed to find known CxSR latency "
4164 "(found ddr%s fsb freq %d, mem freq %d), "
4165 "disabling CxSR\n",
4166 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4167 dev_priv->fsb_freq, dev_priv->mem_freq);
4168 /* Disable CxSR and never update its watermark again */
4169 pineview_disable_cxsr(dev);
4170 dev_priv->display.update_wm = NULL;
4171 } else
4172 dev_priv->display.update_wm = pineview_update_wm;
4173 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4174 } else if (IS_G4X(dev)) {
4175 dev_priv->display.update_wm = g4x_update_wm;
4176 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4177 } else if (IS_GEN4(dev)) {
4178 dev_priv->display.update_wm = i965_update_wm;
4179 if (IS_CRESTLINE(dev))
4180 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4181 else if (IS_BROADWATER(dev))
4182 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4183 } else if (IS_GEN3(dev)) {
4184 dev_priv->display.update_wm = i9xx_update_wm;
4185 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4186 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4187 } else if (IS_I865G(dev)) {
4188 dev_priv->display.update_wm = i830_update_wm;
4189 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4190 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4191 } else if (IS_I85X(dev)) {
4192 dev_priv->display.update_wm = i9xx_update_wm;
4193 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4194 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4195 } else {
4196 dev_priv->display.update_wm = i830_update_wm;
4197 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4198 if (IS_845G(dev))
4199 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4200 else
4201 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4202 }
4203}
4204
6590190d
ED		 4205static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4206{
4207 u32 gt_thread_status_mask;
4208
4209 if (IS_HASWELL(dev_priv->dev))
4210 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4211 else
4212 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4213
4214 /* w/a for a sporadic read returning 0 by waiting for the GT
4215 * thread to wake up.
4216 */
4217 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4218 DRM_ERROR("GT thread status wait timed out\n");
4219}
4220
16995a9f
CW		 4221static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4222{
4223 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4224 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4225}
4226
6590190d
ED		 4227static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4228{
4229 u32 forcewake_ack;
4230
4231 if (IS_HASWELL(dev_priv->dev))
4232 forcewake_ack = FORCEWAKE_ACK_HSW;
4233 else
4234 forcewake_ack = FORCEWAKE_ACK;
4235
057d3860
BW		 4236 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4237 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4238 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4239
c5836c27 4240 I915_WRITE_NOTRACE(FORCEWAKE, FORCEWAKE_KERNEL);
8dee3eea 4241 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4242
057d3860
BW		 4243 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4244 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4245 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4246
4247 __gen6_gt_wait_for_thread_c0(dev_priv);
4248}
4249
16995a9f
CW		 4250static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4251{
4252 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4253 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4254}
4255
6590190d
ED		 4256static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4257{
4258 u32 forcewake_ack;
4259
4260 if (IS_HASWELL(dev_priv->dev))
4261 forcewake_ack = FORCEWAKE_ACK_HSW;
4262 else
4263 forcewake_ack = FORCEWAKE_MT_ACK;
4264
057d3860
BW		 4265 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1) == 0,
4266 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4267 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4268
c5836c27 4269 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
8dee3eea 4270 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4271
057d3860
BW		 4272 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & 1),
4273 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4274 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4275
4276 __gen6_gt_wait_for_thread_c0(dev_priv);
4277}
4278
4279/*
4280 * Generally this is called implicitly by the register read function. However,
4281 * if some sequence requires the GT to not power down then this function should
4282 * be called at the beginning of the sequence followed by a call to
4283 * gen6_gt_force_wake_put() at the end of the sequence.
4284 */
4285void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4286{
4287 unsigned long irqflags;
4288
4289 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4290 if (dev_priv->forcewake_count++ == 0)
4291 dev_priv->gt.force_wake_get(dev_priv);
4292 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4293}
4294
4295void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4296{
4297 u32 gtfifodbg;
4298 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4299 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4300 "MMIO read or write has been dropped %x\n", gtfifodbg))
4301 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4302}
4303
4304static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4305{
4306 I915_WRITE_NOTRACE(FORCEWAKE, 0);
8dee3eea 4307 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4308 gen6_gt_check_fifodbg(dev_priv);
4309}
4310
4311static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4312{
c5836c27 4313 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
8dee3eea 4314 /* gen6_gt_check_fifodbg doubles as the POSTING_READ */
6590190d
ED		 4315 gen6_gt_check_fifodbg(dev_priv);
4316}
4317
4318/*
4319 * see gen6_gt_force_wake_get()
4320 */
4321void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4322{
4323 unsigned long irqflags;
4324
4325 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4326 if (--dev_priv->forcewake_count == 0)
4327 dev_priv->gt.force_wake_put(dev_priv);
4328 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4329}
4330
4331int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4332{
4333 int ret = 0;
4334
4335 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4336 int loop = 500;
4337 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4338 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4339 udelay(10);
4340 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4341 }
4342 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4343 ++ret;
4344 dev_priv->gt_fifo_count = fifo;
4345 }
4346 dev_priv->gt_fifo_count--;
4347
4348 return ret;
4349}
4350
16995a9f
CW		 4351static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4352{
4353 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4354}
4355
6590190d
ED		 4356static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4357{
057d3860
BW		 4358 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1) == 0,
4359 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4360 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4361
c5836c27 4362 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 4363
057d3860
BW		 4364 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1),
4365 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4366 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4367
4368 __gen6_gt_wait_for_thread_c0(dev_priv);
4369}
4370
4371static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4372{
c5836c27 4373 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
5ab140a4
DV		 4374 /* The below doubles as a POSTING_READ */
4375 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 4376}
4377
16995a9f
CW		 4378void intel_gt_reset(struct drm_device *dev)
4379{
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4381
4382 if (IS_VALLEYVIEW(dev)) {
4383 vlv_force_wake_reset(dev_priv);
4384 } else if (INTEL_INFO(dev)->gen >= 6) {
4385 __gen6_gt_force_wake_reset(dev_priv);
4386 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4387 __gen6_gt_force_wake_mt_reset(dev_priv);
4388 }
4389}
4390
6590190d
ED		 4391void intel_gt_init(struct drm_device *dev)
4392{
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394
4395 spin_lock_init(&dev_priv->gt_lock);
4396
16995a9f
CW		 4397 intel_gt_reset(dev);
4398
6590190d
ED		 4399 if (IS_VALLEYVIEW(dev)) {
4400 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4401 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 4402 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4403 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4404 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4405 } else if (IS_GEN6(dev)) {
6590190d
ED		 4406 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4407 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 4408 }
1a01ab3b
JB		 4409 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4410 intel_gen6_powersave_work);
6590190d
ED		 4411}
4412
42c0526c
BW		 4413int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4414{
4fc688ce 4415 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4416
4417 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4418 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4419 return -EAGAIN;
4420 }
4421
4422 I915_WRITE(GEN6_PCODE_DATA, *val);
4423 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4424
4425 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4426 500)) {
4427 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4428 return -ETIMEDOUT;
4429 }
4430
4431 *val = I915_READ(GEN6_PCODE_DATA);
4432 I915_WRITE(GEN6_PCODE_DATA, 0);
4433
4434 return 0;
4435}
4436
4437int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4438{
4fc688ce 4439 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4440
4441 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4442 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4443 return -EAGAIN;
4444 }
4445
4446 I915_WRITE(GEN6_PCODE_DATA, val);
4447 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4448
4449 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4450 500)) {
4451 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4452 return -ETIMEDOUT;
4453 }
4454
4455 I915_WRITE(GEN6_PCODE_DATA, 0);
4456
4457 return 0;
4458}
Motorola kernel-slsi