drm/i915: Make dev_priv->mm.wedged an atomic_t
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945
JB
32#include <linux/i2c.h>
33#include "drmP.h"
34#include "drm.h"
35#include "drm_crtc.h"
36#include "drm_edid.h"
37#include "intel_drv.h"
38#include "i915_drm.h"
39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6
ZY
42/* Private structure for the integrated LVDS support */
43struct intel_lvds_priv {
44 int fitting_mode;
45 u32 pfit_control;
46 u32 pfit_pgm_ratios;
47};
48
79e53945
JB
49/**
50 * Sets the backlight level.
51 *
52 * \param level backlight level, from 0 to intel_lvds_get_max_backlight().
53 */
54static void intel_lvds_set_backlight(struct drm_device *dev, int level)
55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1 57 u32 blc_pwm_ctl, reg;
79e53945 58
541998a1
ZW
59 if (IS_IGDNG(dev))
60 reg = BLC_PWM_CPU_CTL;
61 else
62 reg = BLC_PWM_CTL;
79e53945 63
541998a1
ZW
64 blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK;
65 I915_WRITE(reg, (blc_pwm_ctl |
79e53945
JB
66 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
67}
68
69/**
70 * Returns the maximum level of the backlight duty cycle field.
71 */
72static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
75 u32 reg;
76
77 if (IS_IGDNG(dev))
78 reg = BLC_PWM_PCH_CTL2;
79 else
80 reg = BLC_PWM_CTL;
79e53945 81
541998a1 82 return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >>
79e53945
JB
83 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
84}
85
86/**
87 * Sets the power state for the panel.
88 */
89static void intel_lvds_set_power(struct drm_device *dev, bool on)
90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
92 u32 pp_status, ctl_reg, status_reg;
93
94 if (IS_IGDNG(dev)) {
95 ctl_reg = PCH_PP_CONTROL;
96 status_reg = PCH_PP_STATUS;
97 } else {
98 ctl_reg = PP_CONTROL;
99 status_reg = PP_STATUS;
100 }
79e53945
JB
101
102 if (on) {
541998a1 103 I915_WRITE(ctl_reg, I915_READ(ctl_reg) |
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JB
104 POWER_TARGET_ON);
105 do {
541998a1 106 pp_status = I915_READ(status_reg);
79e53945
JB
107 } while ((pp_status & PP_ON) == 0);
108
109 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle);
110 } else {
111 intel_lvds_set_backlight(dev, 0);
112
541998a1 113 I915_WRITE(ctl_reg, I915_READ(ctl_reg) &
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JB
114 ~POWER_TARGET_ON);
115 do {
541998a1 116 pp_status = I915_READ(status_reg);
79e53945
JB
117 } while (pp_status & PP_ON);
118 }
119}
120
121static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
122{
123 struct drm_device *dev = encoder->dev;
124
125 if (mode == DRM_MODE_DPMS_ON)
126 intel_lvds_set_power(dev, true);
127 else
128 intel_lvds_set_power(dev, false);
129
130 /* XXX: We never power down the LVDS pairs. */
131}
132
133static void intel_lvds_save(struct drm_connector *connector)
134{
135 struct drm_device *dev = connector->dev;
136 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
137 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
138 u32 pwm_ctl_reg;
139
140 if (IS_IGDNG(dev)) {
141 pp_on_reg = PCH_PP_ON_DELAYS;
142 pp_off_reg = PCH_PP_OFF_DELAYS;
143 pp_ctl_reg = PCH_PP_CONTROL;
144 pp_div_reg = PCH_PP_DIVISOR;
145 pwm_ctl_reg = BLC_PWM_CPU_CTL;
146 } else {
147 pp_on_reg = PP_ON_DELAYS;
148 pp_off_reg = PP_OFF_DELAYS;
149 pp_ctl_reg = PP_CONTROL;
150 pp_div_reg = PP_DIVISOR;
151 pwm_ctl_reg = BLC_PWM_CTL;
152 }
79e53945 153
541998a1
ZW
154 dev_priv->savePP_ON = I915_READ(pp_on_reg);
155 dev_priv->savePP_OFF = I915_READ(pp_off_reg);
156 dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg);
157 dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg);
158 dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg);
79e53945
JB
159 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
160 BACKLIGHT_DUTY_CYCLE_MASK);
161
162 /*
163 * If the light is off at server startup, just make it full brightness
164 */
165 if (dev_priv->backlight_duty_cycle == 0)
166 dev_priv->backlight_duty_cycle =
167 intel_lvds_get_max_backlight(dev);
168}
169
170static void intel_lvds_restore(struct drm_connector *connector)
171{
172 struct drm_device *dev = connector->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
174 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
175 u32 pwm_ctl_reg;
176
177 if (IS_IGDNG(dev)) {
178 pp_on_reg = PCH_PP_ON_DELAYS;
179 pp_off_reg = PCH_PP_OFF_DELAYS;
180 pp_ctl_reg = PCH_PP_CONTROL;
181 pp_div_reg = PCH_PP_DIVISOR;
182 pwm_ctl_reg = BLC_PWM_CPU_CTL;
183 } else {
184 pp_on_reg = PP_ON_DELAYS;
185 pp_off_reg = PP_OFF_DELAYS;
186 pp_ctl_reg = PP_CONTROL;
187 pp_div_reg = PP_DIVISOR;
188 pwm_ctl_reg = BLC_PWM_CTL;
189 }
79e53945 190
541998a1
ZW
191 I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL);
192 I915_WRITE(pp_on_reg, dev_priv->savePP_ON);
193 I915_WRITE(pp_off_reg, dev_priv->savePP_OFF);
194 I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR);
195 I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL);
79e53945
JB
196 if (dev_priv->savePP_CONTROL & POWER_TARGET_ON)
197 intel_lvds_set_power(dev, true);
198 else
199 intel_lvds_set_power(dev, false);
200}
201
202static int intel_lvds_mode_valid(struct drm_connector *connector,
203 struct drm_display_mode *mode)
204{
205 struct drm_device *dev = connector->dev;
206 struct drm_i915_private *dev_priv = dev->dev_private;
207 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
208
209 if (fixed_mode) {
210 if (mode->hdisplay > fixed_mode->hdisplay)
211 return MODE_PANEL;
212 if (mode->vdisplay > fixed_mode->vdisplay)
213 return MODE_PANEL;
214 }
215
216 return MODE_OK;
217}
218
219static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
220 struct drm_display_mode *mode,
221 struct drm_display_mode *adjusted_mode)
222{
3fbe18d6
ZY
223 /*
224 * float point operation is not supported . So the PANEL_RATIO_FACTOR
225 * is defined, which can avoid the float point computation when
226 * calculating the panel ratio.
227 */
228#define PANEL_RATIO_FACTOR 8192
79e53945
JB
229 struct drm_device *dev = encoder->dev;
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
232 struct drm_encoder *tmp_encoder;
3fbe18d6
ZY
233 struct intel_output *intel_output = enc_to_intel_output(encoder);
234 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
235 u32 pfit_control = 0, pfit_pgm_ratios = 0;
236 int left_border = 0, right_border = 0, top_border = 0;
237 int bottom_border = 0;
238 bool border = 0;
239 int panel_ratio, desired_ratio, vert_scale, horiz_scale;
240 int horiz_ratio, vert_ratio;
aa0261f2
ZY
241 u32 hsync_width, vsync_width;
242 u32 hblank_width, vblank_width;
243 u32 hsync_pos, vsync_pos;
79e53945
JB
244
245 /* Should never happen!! */
246 if (!IS_I965G(dev) && intel_crtc->pipe == 0) {
1ae8c0a5 247 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
248 return false;
249 }
250
251 /* Should never happen!! */
252 list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) {
253 if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) {
1ae8c0a5 254 DRM_ERROR("Can't enable LVDS and another "
79e53945
JB
255 "encoder on the same pipe\n");
256 return false;
257 }
258 }
3fbe18d6
ZY
259 /* If we don't have a panel mode, there is nothing we can do */
260 if (dev_priv->panel_fixed_mode == NULL)
261 return true;
79e53945
JB
262 /*
263 * If we have timings from the BIOS for the panel, put them in
264 * to the adjusted mode. The CRTC will be set up for this mode,
265 * with the panel scaling set up to source from the H/VDisplay
266 * of the original mode.
267 */
268 if (dev_priv->panel_fixed_mode != NULL) {
269 adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay;
270 adjusted_mode->hsync_start =
271 dev_priv->panel_fixed_mode->hsync_start;
272 adjusted_mode->hsync_end =
273 dev_priv->panel_fixed_mode->hsync_end;
274 adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal;
275 adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay;
276 adjusted_mode->vsync_start =
277 dev_priv->panel_fixed_mode->vsync_start;
278 adjusted_mode->vsync_end =
279 dev_priv->panel_fixed_mode->vsync_end;
280 adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
281 adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
282 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
283 }
284
3fbe18d6
ZY
285 /* Make sure pre-965s set dither correctly */
286 if (!IS_I965G(dev)) {
287 if (dev_priv->panel_wants_dither || dev_priv->lvds_dither)
288 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
289 }
290
291 /* Native modes don't need fitting */
292 if (adjusted_mode->hdisplay == mode->hdisplay &&
293 adjusted_mode->vdisplay == mode->vdisplay) {
294 pfit_pgm_ratios = 0;
295 border = 0;
296 goto out;
297 }
298
8dd81a38
ZW
299 /* full screen scale for now */
300 if (IS_IGDNG(dev))
301 goto out;
302
3fbe18d6
ZY
303 /* 965+ wants fuzzy fitting */
304 if (IS_I965G(dev))
305 pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
306 PFIT_FILTER_FUZZY;
307
aa0261f2
ZY
308 hsync_width = adjusted_mode->crtc_hsync_end -
309 adjusted_mode->crtc_hsync_start;
310 vsync_width = adjusted_mode->crtc_vsync_end -
311 adjusted_mode->crtc_vsync_start;
312 hblank_width = adjusted_mode->crtc_hblank_end -
313 adjusted_mode->crtc_hblank_start;
314 vblank_width = adjusted_mode->crtc_vblank_end -
315 adjusted_mode->crtc_vblank_start;
3fbe18d6
ZY
316 /*
317 * Deal with panel fitting options. Figure out how to stretch the
318 * image based on its aspect ratio & the current panel fitting mode.
319 */
320 panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR /
321 adjusted_mode->vdisplay;
322 desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR /
323 mode->vdisplay;
324 /*
325 * Enable automatic panel scaling for non-native modes so that they fill
326 * the screen. Should be enabled before the pipe is enabled, according
327 * to register description and PRM.
328 * Change the value here to see the borders for debugging
329 */
8dd81a38
ZW
330 if (!IS_IGDNG(dev)) {
331 I915_WRITE(BCLRPAT_A, 0);
332 I915_WRITE(BCLRPAT_B, 0);
333 }
3fbe18d6
ZY
334
335 switch (lvds_priv->fitting_mode) {
53bd8389 336 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
337 /*
338 * For centered modes, we have to calculate border widths &
339 * heights and modify the values programmed into the CRTC.
340 */
341 left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2;
342 right_border = left_border;
343 if (mode->hdisplay & 1)
344 right_border++;
345 top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2;
346 bottom_border = top_border;
347 if (mode->vdisplay & 1)
348 bottom_border++;
349 /* Set active & border values */
350 adjusted_mode->crtc_hdisplay = mode->hdisplay;
aa0261f2
ZY
351 /* Keep the boder be even */
352 if (right_border & 1)
353 right_border++;
354 /* use the border directly instead of border minuse one */
3fbe18d6 355 adjusted_mode->crtc_hblank_start = mode->hdisplay +
aa0261f2
ZY
356 right_border;
357 /* keep the blank width constant */
358 adjusted_mode->crtc_hblank_end =
359 adjusted_mode->crtc_hblank_start + hblank_width;
360 /* get the hsync pos relative to hblank start */
361 hsync_pos = (hblank_width - hsync_width) / 2;
362 /* keep the hsync pos be even */
363 if (hsync_pos & 1)
364 hsync_pos++;
3fbe18d6 365 adjusted_mode->crtc_hsync_start =
aa0261f2
ZY
366 adjusted_mode->crtc_hblank_start + hsync_pos;
367 /* keep the hsync width constant */
3fbe18d6 368 adjusted_mode->crtc_hsync_end =
aa0261f2 369 adjusted_mode->crtc_hsync_start + hsync_width;
3fbe18d6 370 adjusted_mode->crtc_vdisplay = mode->vdisplay;
aa0261f2 371 /* use the border instead of border minus one */
3fbe18d6 372 adjusted_mode->crtc_vblank_start = mode->vdisplay +
aa0261f2
ZY
373 bottom_border;
374 /* keep the vblank width constant */
375 adjusted_mode->crtc_vblank_end =
376 adjusted_mode->crtc_vblank_start + vblank_width;
377 /* get the vsync start postion relative to vblank start */
378 vsync_pos = (vblank_width - vsync_width) / 2;
3fbe18d6 379 adjusted_mode->crtc_vsync_start =
aa0261f2
ZY
380 adjusted_mode->crtc_vblank_start + vsync_pos;
381 /* keep the vsync width constant */
3fbe18d6 382 adjusted_mode->crtc_vsync_end =
aa0261f2 383 adjusted_mode->crtc_vblank_start + vsync_width;
3fbe18d6
ZY
384 border = 1;
385 break;
386 case DRM_MODE_SCALE_ASPECT:
387 /* Scale but preserve the spect ratio */
388 pfit_control |= PFIT_ENABLE;
389 if (IS_I965G(dev)) {
390 /* 965+ is easy, it does everything in hw */
391 if (panel_ratio > desired_ratio)
392 pfit_control |= PFIT_SCALING_PILLAR;
393 else if (panel_ratio < desired_ratio)
394 pfit_control |= PFIT_SCALING_LETTER;
395 else
396 pfit_control |= PFIT_SCALING_AUTO;
397 } else {
398 /*
399 * For earlier chips we have to calculate the scaling
400 * ratio by hand and program it into the
401 * PFIT_PGM_RATIO register
402 */
403 u32 horiz_bits, vert_bits, bits = 12;
404 horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/
405 adjusted_mode->hdisplay;
406 vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/
407 adjusted_mode->vdisplay;
408 horiz_scale = adjusted_mode->hdisplay *
409 PANEL_RATIO_FACTOR / mode->hdisplay;
410 vert_scale = adjusted_mode->vdisplay *
411 PANEL_RATIO_FACTOR / mode->vdisplay;
412
413 /* retain aspect ratio */
414 if (panel_ratio > desired_ratio) { /* Pillar */
415 u32 scaled_width;
416 scaled_width = mode->hdisplay * vert_scale /
417 PANEL_RATIO_FACTOR;
418 horiz_ratio = vert_ratio;
419 pfit_control |= (VERT_AUTO_SCALE |
420 VERT_INTERP_BILINEAR |
421 HORIZ_INTERP_BILINEAR);
422 /* Pillar will have left/right borders */
423 left_border = (adjusted_mode->hdisplay -
424 scaled_width) / 2;
425 right_border = left_border;
426 if (mode->hdisplay & 1) /* odd resolutions */
427 right_border++;
aa0261f2
ZY
428 /* keep the border be even */
429 if (right_border & 1)
430 right_border++;
3fbe18d6 431 adjusted_mode->crtc_hdisplay = scaled_width;
aa0261f2 432 /* use border instead of border minus one */
3fbe18d6 433 adjusted_mode->crtc_hblank_start =
aa0261f2
ZY
434 scaled_width + right_border;
435 /* keep the hblank width constant */
3fbe18d6 436 adjusted_mode->crtc_hblank_end =
aa0261f2
ZY
437 adjusted_mode->crtc_hblank_start +
438 hblank_width;
439 /*
440 * get the hsync start pos relative to
441 * hblank start
442 */
443 hsync_pos = (hblank_width - hsync_width) / 2;
444 /* keep the hsync_pos be even */
445 if (hsync_pos & 1)
446 hsync_pos++;
3fbe18d6 447 adjusted_mode->crtc_hsync_start =
aa0261f2
ZY
448 adjusted_mode->crtc_hblank_start +
449 hsync_pos;
450 /* keept hsync width constant */
3fbe18d6 451 adjusted_mode->crtc_hsync_end =
aa0261f2
ZY
452 adjusted_mode->crtc_hsync_start +
453 hsync_width;
3fbe18d6
ZY
454 border = 1;
455 } else if (panel_ratio < desired_ratio) { /* letter */
456 u32 scaled_height = mode->vdisplay *
457 horiz_scale / PANEL_RATIO_FACTOR;
458 vert_ratio = horiz_ratio;
459 pfit_control |= (HORIZ_AUTO_SCALE |
460 VERT_INTERP_BILINEAR |
461 HORIZ_INTERP_BILINEAR);
462 /* Letterbox will have top/bottom border */
463 top_border = (adjusted_mode->vdisplay -
464 scaled_height) / 2;
465 bottom_border = top_border;
466 if (mode->vdisplay & 1)
467 bottom_border++;
468 adjusted_mode->crtc_vdisplay = scaled_height;
aa0261f2 469 /* use border instead of border minus one */
3fbe18d6 470 adjusted_mode->crtc_vblank_start =
aa0261f2
ZY
471 scaled_height + bottom_border;
472 /* keep the vblank width constant */
3fbe18d6 473 adjusted_mode->crtc_vblank_end =
aa0261f2
ZY
474 adjusted_mode->crtc_vblank_start +
475 vblank_width;
476 /*
477 * get the vsync start pos relative to
478 * vblank start
479 */
480 vsync_pos = (vblank_width - vsync_width) / 2;
3fbe18d6 481 adjusted_mode->crtc_vsync_start =
aa0261f2
ZY
482 adjusted_mode->crtc_vblank_start +
483 vsync_pos;
484 /* keep the vsync width constant */
3fbe18d6 485 adjusted_mode->crtc_vsync_end =
aa0261f2
ZY
486 adjusted_mode->crtc_vsync_start +
487 vsync_width;
3fbe18d6
ZY
488 border = 1;
489 } else {
490 /* Aspects match, Let hw scale both directions */
491 pfit_control |= (VERT_AUTO_SCALE |
492 HORIZ_AUTO_SCALE |
493 VERT_INTERP_BILINEAR |
494 HORIZ_INTERP_BILINEAR);
495 }
496 horiz_bits = (1 << bits) * horiz_ratio /
497 PANEL_RATIO_FACTOR;
498 vert_bits = (1 << bits) * vert_ratio /
499 PANEL_RATIO_FACTOR;
500 pfit_pgm_ratios =
501 ((vert_bits << PFIT_VERT_SCALE_SHIFT) &
502 PFIT_VERT_SCALE_MASK) |
503 ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) &
504 PFIT_HORIZ_SCALE_MASK);
505 }
506 break;
507
508 case DRM_MODE_SCALE_FULLSCREEN:
509 /*
510 * Full scaling, even if it changes the aspect ratio.
511 * Fortunately this is all done for us in hw.
512 */
513 pfit_control |= PFIT_ENABLE;
514 if (IS_I965G(dev))
515 pfit_control |= PFIT_SCALING_AUTO;
516 else
517 pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
518 VERT_INTERP_BILINEAR |
519 HORIZ_INTERP_BILINEAR);
520 break;
521 default:
522 break;
523 }
524
525out:
526 lvds_priv->pfit_control = pfit_control;
527 lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
79e53945
JB
528 /*
529 * XXX: It would be nice to support lower refresh rates on the
530 * panels to reduce power consumption, and perhaps match the
531 * user's requested refresh rate.
532 */
533
534 return true;
535}
536
537static void intel_lvds_prepare(struct drm_encoder *encoder)
538{
539 struct drm_device *dev = encoder->dev;
540 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1 541 u32 reg;
79e53945 542
541998a1
ZW
543 if (IS_IGDNG(dev))
544 reg = BLC_PWM_CPU_CTL;
545 else
546 reg = BLC_PWM_CTL;
79e53945 547
541998a1 548 dev_priv->saveBLC_PWM_CTL = I915_READ(reg);
79e53945
JB
549 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
550 BACKLIGHT_DUTY_CYCLE_MASK);
551
552 intel_lvds_set_power(dev, false);
553}
554
555static void intel_lvds_commit( struct drm_encoder *encoder)
556{
557 struct drm_device *dev = encoder->dev;
558 struct drm_i915_private *dev_priv = dev->dev_private;
559
560 if (dev_priv->backlight_duty_cycle == 0)
561 dev_priv->backlight_duty_cycle =
562 intel_lvds_get_max_backlight(dev);
563
564 intel_lvds_set_power(dev, true);
565}
566
567static void intel_lvds_mode_set(struct drm_encoder *encoder,
568 struct drm_display_mode *mode,
569 struct drm_display_mode *adjusted_mode)
570{
571 struct drm_device *dev = encoder->dev;
572 struct drm_i915_private *dev_priv = dev->dev_private;
3fbe18d6
ZY
573 struct intel_output *intel_output = enc_to_intel_output(encoder);
574 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
79e53945
JB
575
576 /*
577 * The LVDS pin pair will already have been turned on in the
578 * intel_crtc_mode_set since it has a large impact on the DPLL
579 * settings.
580 */
581
541998a1
ZW
582 if (IS_IGDNG(dev))
583 return;
584
79e53945
JB
585 /*
586 * Enable automatic panel scaling so that non-native modes fill the
587 * screen. Should be enabled before the pipe is enabled, according to
588 * register description and PRM.
589 */
3fbe18d6
ZY
590 I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios);
591 I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control);
79e53945
JB
592}
593
594/**
595 * Detect the LVDS connection.
596 *
b42d4c5c
JB
597 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
598 * connected and closed means disconnected. We also send hotplug events as
599 * needed, using lid status notification from the input layer.
79e53945
JB
600 */
601static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector)
602{
b42d4c5c
JB
603 enum drm_connector_status status = connector_status_connected;
604
605 if (!acpi_lid_open())
606 status = connector_status_disconnected;
607
608 return status;
79e53945
JB
609}
610
611/**
612 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
613 */
614static int intel_lvds_get_modes(struct drm_connector *connector)
615{
616 struct drm_device *dev = connector->dev;
617 struct intel_output *intel_output = to_intel_output(connector);
618 struct drm_i915_private *dev_priv = dev->dev_private;
619 int ret = 0;
620
621 ret = intel_ddc_get_modes(intel_output);
622
623 if (ret)
624 return ret;
625
626 /* Didn't get an EDID, so
627 * Set wide sync ranges so we get all modes
628 * handed to valid_mode for checking
629 */
630 connector->display_info.min_vfreq = 0;
631 connector->display_info.max_vfreq = 200;
632 connector->display_info.min_hfreq = 0;
633 connector->display_info.max_hfreq = 200;
634
635 if (dev_priv->panel_fixed_mode != NULL) {
636 struct drm_display_mode *mode;
637
79e53945
JB
638 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
639 drm_mode_probed_add(connector, mode);
79e53945
JB
640
641 return 1;
642 }
643
644 return 0;
645}
646
c1c7af60
JB
647static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
648 void *unused)
649{
650 struct drm_i915_private *dev_priv =
651 container_of(nb, struct drm_i915_private, lid_notifier);
652 struct drm_device *dev = dev_priv->dev;
653
654 if (acpi_lid_open())
655 drm_helper_resume_force_mode(dev);
656
06324194
JB
657 drm_sysfs_hotplug_event(dev_priv->dev);
658
c1c7af60
JB
659 return NOTIFY_OK;
660}
661
79e53945
JB
662/**
663 * intel_lvds_destroy - unregister and free LVDS structures
664 * @connector: connector to free
665 *
666 * Unregister the DDC bus for this connector then free the driver private
667 * structure.
668 */
669static void intel_lvds_destroy(struct drm_connector *connector)
670{
c1c7af60 671 struct drm_device *dev = connector->dev;
79e53945 672 struct intel_output *intel_output = to_intel_output(connector);
c1c7af60 673 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB
674
675 if (intel_output->ddc_bus)
676 intel_i2c_destroy(intel_output->ddc_bus);
c1c7af60
JB
677 if (dev_priv->lid_notifier.notifier_call)
678 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB
679 drm_sysfs_connector_remove(connector);
680 drm_connector_cleanup(connector);
681 kfree(connector);
682}
683
335041ed
JB
684static int intel_lvds_set_property(struct drm_connector *connector,
685 struct drm_property *property,
686 uint64_t value)
687{
3fbe18d6
ZY
688 struct drm_device *dev = connector->dev;
689 struct intel_output *intel_output =
690 to_intel_output(connector);
691
692 if (property == dev->mode_config.scaling_mode_property &&
693 connector->encoder) {
694 struct drm_crtc *crtc = connector->encoder->crtc;
695 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
53bd8389
JB
696 if (value == DRM_MODE_SCALE_NONE) {
697 DRM_DEBUG_KMS("no scaling not supported\n");
3fbe18d6
ZY
698 return 0;
699 }
700 if (lvds_priv->fitting_mode == value) {
701 /* the LVDS scaling property is not changed */
702 return 0;
703 }
704 lvds_priv->fitting_mode = value;
705 if (crtc && crtc->enabled) {
706 /*
707 * If the CRTC is enabled, the display will be changed
708 * according to the new panel fitting mode.
709 */
710 drm_crtc_helper_set_mode(crtc, &crtc->mode,
711 crtc->x, crtc->y, crtc->fb);
712 }
713 }
714
335041ed
JB
715 return 0;
716}
717
79e53945
JB
718static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
719 .dpms = intel_lvds_dpms,
720 .mode_fixup = intel_lvds_mode_fixup,
721 .prepare = intel_lvds_prepare,
722 .mode_set = intel_lvds_mode_set,
723 .commit = intel_lvds_commit,
724};
725
726static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
727 .get_modes = intel_lvds_get_modes,
728 .mode_valid = intel_lvds_mode_valid,
729 .best_encoder = intel_best_encoder,
730};
731
732static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c9fb15f6 733 .dpms = drm_helper_connector_dpms,
79e53945
JB
734 .save = intel_lvds_save,
735 .restore = intel_lvds_restore,
736 .detect = intel_lvds_detect,
737 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 738 .set_property = intel_lvds_set_property,
79e53945
JB
739 .destroy = intel_lvds_destroy,
740};
741
742
743static void intel_lvds_enc_destroy(struct drm_encoder *encoder)
744{
745 drm_encoder_cleanup(encoder);
746}
747
748static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
749 .destroy = intel_lvds_enc_destroy,
750};
751
425d244c
JW
752static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
753{
8a4c47f3 754 DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
755 return 1;
756}
79e53945 757
425d244c 758/* These systems claim to have LVDS, but really don't */
93c05f22 759static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
760 {
761 .callback = intel_no_lvds_dmi_callback,
762 .ident = "Apple Mac Mini (Core series)",
763 .matches = {
98acd46f 764 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
765 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
766 },
767 },
768 {
769 .callback = intel_no_lvds_dmi_callback,
770 .ident = "Apple Mac Mini (Core 2 series)",
771 .matches = {
98acd46f 772 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
773 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
774 },
775 },
776 {
777 .callback = intel_no_lvds_dmi_callback,
778 .ident = "MSI IM-945GSE-A",
779 .matches = {
780 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
781 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
782 },
783 },
784 {
785 .callback = intel_no_lvds_dmi_callback,
786 .ident = "Dell Studio Hybrid",
787 .matches = {
788 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
789 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
790 },
791 },
70aa96ca
JW
792 {
793 .callback = intel_no_lvds_dmi_callback,
794 .ident = "AOpen Mini PC",
795 .matches = {
796 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
797 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
798 },
799 },
ed8c754b
TV
800 {
801 .callback = intel_no_lvds_dmi_callback,
802 .ident = "AOpen Mini PC MP915",
803 .matches = {
804 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
805 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
806 },
807 },
fa0864b2
MC
808 {
809 .callback = intel_no_lvds_dmi_callback,
810 .ident = "Aopen i945GTt-VFA",
811 .matches = {
812 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
813 },
814 },
425d244c
JW
815
816 { } /* terminating entry */
817};
79e53945 818
e99da35f
ZY
819#ifdef CONFIG_ACPI
820/*
821 * check_lid_device -- check whether @handle is an ACPI LID device.
822 * @handle: ACPI device handle
823 * @level : depth in the ACPI namespace tree
824 * @context: the number of LID device when we find the device
825 * @rv: a return value to fill if desired (Not use)
826 */
827static acpi_status
828check_lid_device(acpi_handle handle, u32 level, void *context,
829 void **return_value)
830{
831 struct acpi_device *acpi_dev;
832 int *lid_present = context;
833
834 acpi_dev = NULL;
835 /* Get the acpi device for device handle */
836 if (acpi_bus_get_device(handle, &acpi_dev) || !acpi_dev) {
837 /* If there is no ACPI device for handle, return */
838 return AE_OK;
839 }
840
841 if (!strncmp(acpi_device_hid(acpi_dev), "PNP0C0D", 7))
842 *lid_present = 1;
843
844 return AE_OK;
845}
846
847/**
848 * check whether there exists the ACPI LID device by enumerating the ACPI
849 * device tree.
850 */
851static int intel_lid_present(void)
852{
853 int lid_present = 0;
854
855 if (acpi_disabled) {
856 /* If ACPI is disabled, there is no ACPI device tree to
857 * check, so assume the LID device would have been present.
858 */
859 return 1;
860 }
861
862 acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
863 ACPI_UINT32_MAX,
864 check_lid_device, &lid_present, NULL);
865
866 return lid_present;
867}
868#else
869static int intel_lid_present(void)
870{
871 /* In the absence of ACPI built in, assume that the LID device would
872 * have been present.
873 */
874 return 1;
875}
876#endif
877
79e53945
JB
878/**
879 * intel_lvds_init - setup LVDS connectors on this device
880 * @dev: drm device
881 *
882 * Create the connector, register the LVDS DDC bus, and try to figure out what
883 * modes we can display on the LVDS panel (if present).
884 */
885void intel_lvds_init(struct drm_device *dev)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 struct intel_output *intel_output;
889 struct drm_connector *connector;
890 struct drm_encoder *encoder;
891 struct drm_display_mode *scan; /* *modes, *bios_mode; */
892 struct drm_crtc *crtc;
3fbe18d6 893 struct intel_lvds_priv *lvds_priv;
79e53945 894 u32 lvds;
541998a1 895 int pipe, gpio = GPIOC;
79e53945 896
425d244c
JW
897 /* Skip init on machines we know falsely report LVDS */
898 if (dmi_check_system(intel_no_lvds))
565dcd46 899 return;
565dcd46 900
e99da35f
ZY
901 /* Assume that any device without an ACPI LID device also doesn't
902 * have an integrated LVDS. We would be better off parsing the BIOS
903 * to get a reliable indicator, but that code isn't written yet.
904 *
905 * In the case of all-in-one desktops using LVDS that we've seen,
906 * they're using SDVO LVDS.
907 */
908 if (!intel_lid_present())
909 return;
910
541998a1
ZW
911 if (IS_IGDNG(dev)) {
912 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
913 return;
32f9d658
ZW
914 if (dev_priv->edp_support) {
915 DRM_DEBUG("disable LVDS for eDP support\n");
916 return;
917 }
541998a1
ZW
918 gpio = PCH_GPIOC;
919 }
920
3fbe18d6
ZY
921 intel_output = kzalloc(sizeof(struct intel_output) +
922 sizeof(struct intel_lvds_priv), GFP_KERNEL);
79e53945
JB
923 if (!intel_output) {
924 return;
925 }
926
927 connector = &intel_output->base;
928 encoder = &intel_output->enc;
929 drm_connector_init(dev, &intel_output->base, &intel_lvds_connector_funcs,
930 DRM_MODE_CONNECTOR_LVDS);
931
932 drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs,
933 DRM_MODE_ENCODER_LVDS);
934
935 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
936 intel_output->type = INTEL_OUTPUT_LVDS;
937
f8aed700
ML
938 intel_output->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
939 intel_output->crtc_mask = (1 << 1);
79e53945
JB
940 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
941 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
942 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
943 connector->interlace_allowed = false;
944 connector->doublescan_allowed = false;
945
3fbe18d6
ZY
946 lvds_priv = (struct intel_lvds_priv *)(intel_output + 1);
947 intel_output->dev_priv = lvds_priv;
948 /* create the scaling mode property */
949 drm_mode_create_scaling_mode_property(dev);
950 /*
951 * the initial panel fitting mode will be FULL_SCREEN.
952 */
79e53945 953
3fbe18d6
ZY
954 drm_connector_attach_property(&intel_output->base,
955 dev->mode_config.scaling_mode_property,
956 DRM_MODE_SCALE_FULLSCREEN);
957 lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN;
79e53945
JB
958 /*
959 * LVDS discovery:
960 * 1) check for EDID on DDC
961 * 2) check for VBT data
962 * 3) check to see if LVDS is already on
963 * if none of the above, no panel
964 * 4) make sure lid is open
965 * if closed, act like it's not there for now
966 */
967
968 /* Set up the DDC bus. */
541998a1 969 intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C");
79e53945
JB
970 if (!intel_output->ddc_bus) {
971 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
972 "failed.\n");
973 goto failed;
974 }
975
976 /*
977 * Attempt to get the fixed panel mode from DDC. Assume that the
978 * preferred mode is the right one.
979 */
980 intel_ddc_get_modes(intel_output);
981
982 list_for_each_entry(scan, &connector->probed_modes, head) {
983 mutex_lock(&dev->mode_config.mutex);
984 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
985 dev_priv->panel_fixed_mode =
986 drm_mode_duplicate(dev, scan);
987 mutex_unlock(&dev->mode_config.mutex);
565dcd46 988 goto out;
79e53945
JB
989 }
990 mutex_unlock(&dev->mode_config.mutex);
991 }
992
993 /* Failed to get EDID, what about VBT? */
88631706 994 if (dev_priv->lfp_lvds_vbt_mode) {
79e53945
JB
995 mutex_lock(&dev->mode_config.mutex);
996 dev_priv->panel_fixed_mode =
88631706 997 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
79e53945 998 mutex_unlock(&dev->mode_config.mutex);
e285f3cd
JB
999 if (dev_priv->panel_fixed_mode) {
1000 dev_priv->panel_fixed_mode->type |=
1001 DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1002 goto out;
1003 }
79e53945
JB
1004 }
1005
1006 /*
1007 * If we didn't get EDID, try checking if the panel is already turned
1008 * on. If so, assume that whatever is currently programmed is the
1009 * correct mode.
1010 */
541998a1
ZW
1011
1012 /* IGDNG: FIXME if still fail, not try pipe mode now */
1013 if (IS_IGDNG(dev))
1014 goto failed;
1015
79e53945
JB
1016 lvds = I915_READ(LVDS);
1017 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1018 crtc = intel_get_crtc_from_pipe(dev, pipe);
1019
1020 if (crtc && (lvds & LVDS_PORT_EN)) {
1021 dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc);
1022 if (dev_priv->panel_fixed_mode) {
1023 dev_priv->panel_fixed_mode->type |=
1024 DRM_MODE_TYPE_PREFERRED;
565dcd46 1025 goto out;
79e53945
JB
1026 }
1027 }
1028
1029 /* If we still don't have a mode after all that, give up. */
1030 if (!dev_priv->panel_fixed_mode)
1031 goto failed;
1032
79e53945 1033out:
541998a1
ZW
1034 if (IS_IGDNG(dev)) {
1035 u32 pwm;
1036 /* make sure PWM is enabled */
1037 pwm = I915_READ(BLC_PWM_CPU_CTL2);
1038 pwm |= (PWM_ENABLE | PWM_PIPE_B);
1039 I915_WRITE(BLC_PWM_CPU_CTL2, pwm);
1040
1041 pwm = I915_READ(BLC_PWM_PCH_CTL1);
1042 pwm |= PWM_PCH_ENABLE;
1043 I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
1044 }
c1c7af60
JB
1045 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1046 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
1047 DRM_DEBUG("lid notifier registration failed\n");
1048 dev_priv->lid_notifier.notifier_call = NULL;
1049 }
79e53945
JB
1050 drm_sysfs_connector_add(connector);
1051 return;
1052
1053failed:
8a4c47f3 1054 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945
JB
1055 if (intel_output->ddc_bus)
1056 intel_i2c_destroy(intel_output->ddc_bus);
1057 drm_connector_cleanup(connector);
3fbe18d6 1058 kfree(intel_output);
79e53945 1059}