[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_i2c.c

/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2008,2010 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Chris Wilson <chris@chris-wilson.co.uk>
 */
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/export.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"

struct gmbus_port {
	const char *name;
	int reg;
};

static const struct gmbus_port gmbus_ports[] = {
	{ "ssc", GPIOB },
	{ "vga", GPIOA },
	{ "panel", GPIOC },
	{ "dpc", GPIOD },
	{ "dpb", GPIOE },
	{ "dpd", GPIOF },
};

/* Intel GPIO access functions */

#define I2C_RISEFALL_TIME 10

static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter *i2c)
{
	return container_of(i2c, struct intel_gmbus, adapter);
}

void
intel_i2c_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
}

static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
{
	u32 val;

	/* When using bit bashing for I2C, this bit needs to be set to 1 */
	if (!IS_PINEVIEW(dev_priv->dev))
		return;

	val = I915_READ(DSPCLK_GATE_D);
	if (enable)
		val |= DPCUNIT_CLOCK_GATE_DISABLE;
	else
		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, val);
}

static u32 get_reserved(struct intel_gmbus *bus)
{
	struct drm_i915_private *dev_priv = bus->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = 0;

	/* On most chips, these bits must be preserved in software. */
	if (!IS_I830(dev) && !IS_845G(dev))
		reserved = I915_READ_NOTRACE(bus->gpio_reg) &
					     (GPIO_DATA_PULLUP_DISABLE |
					      GPIO_CLOCK_PULLUP_DISABLE);

	return reserved;
}

static int get_clock(void *data)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
}

static int get_data(void *data)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
}

static void set_clock(void *data, int state_high)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	u32 clock_bits;

	if (state_high)
		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
	else
		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
			GPIO_CLOCK_VAL_MASK;

	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
	POSTING_READ(bus->gpio_reg);
}

static void set_data(void *data, int state_high)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	u32 data_bits;

	if (state_high)
		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
	else
		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
			GPIO_DATA_VAL_MASK;

	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
	POSTING_READ(bus->gpio_reg);
}

static int
intel_gpio_pre_xfer(struct i2c_adapter *adapter)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = bus->dev_priv;

	intel_i2c_reset(dev_priv->dev);
	intel_i2c_quirk_set(dev_priv, true);
	set_data(bus, 1);
	set_clock(bus, 1);
	udelay(I2C_RISEFALL_TIME);
	return 0;
}

static void
intel_gpio_post_xfer(struct i2c_adapter *adapter)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = bus->dev_priv;

	set_data(bus, 1);
	set_clock(bus, 1);
	intel_i2c_quirk_set(dev_priv, false);
}

static void
intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
{
	struct drm_i915_private *dev_priv = bus->dev_priv;
	struct i2c_algo_bit_data *algo;

	algo = &bus->bit_algo;

	/* -1 to map pin pair to gmbus index */
	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;

	bus->adapter.algo_data = algo;
	algo->setsda = set_data;
	algo->setscl = set_clock;
	algo->getsda = get_data;
	algo->getscl = get_clock;
	algo->pre_xfer = intel_gpio_pre_xfer;
	algo->post_xfer = intel_gpio_post_xfer;
	algo->udelay = I2C_RISEFALL_TIME;
	algo->timeout = usecs_to_jiffies(2200);
	algo->data = bus;
}

static int
gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
		u32 gmbus1_index)
{
	int reg_offset = dev_priv->gpio_mmio_base;
	u16 len = msg->len;
	u8 *buf = msg->buf;

	I915_WRITE(GMBUS1 + reg_offset,
		   gmbus1_index |
		   GMBUS_CYCLE_WAIT |
		   (len << GMBUS_BYTE_COUNT_SHIFT) |
		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
		   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
	while (len) {
		int ret;
		u32 val, loop = 0;
		u32 gmbus2;

		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
			       (GMBUS_SATOER | GMBUS_HW_RDY),
			       50);
		if (ret)
			return -ETIMEDOUT;
		if (gmbus2 & GMBUS_SATOER)
			return -ENXIO;

		val = I915_READ(GMBUS3 + reg_offset);
		do {
			*buf++ = val & 0xff;
			val >>= 8;
		} while (--len && ++loop < 4);
	}

	return 0;
}

static int
gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
{
	int reg_offset = dev_priv->gpio_mmio_base;
	u16 len = msg->len;
	u8 *buf = msg->buf;
	u32 val, loop;

	val = loop = 0;
	while (len && loop < 4) {
		val |= *buf++ << (8 * loop++);
		len -= 1;
	}

	I915_WRITE(GMBUS3 + reg_offset, val);
	I915_WRITE(GMBUS1 + reg_offset,
		   GMBUS_CYCLE_WAIT |
		   (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
		   (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
		   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
	while (len) {
		int ret;
		u32 gmbus2;

		val = loop = 0;
		do {
			val |= *buf++ << (8 * loop);
		} while (--len && ++loop < 4);

		I915_WRITE(GMBUS3 + reg_offset, val);

		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
			       (GMBUS_SATOER | GMBUS_HW_RDY),
			       50);
		if (ret)
			return -ETIMEDOUT;
		if (gmbus2 & GMBUS_SATOER)
			return -ENXIO;
	}
	return 0;
}

/*
 * The gmbus controller can combine a 1 or 2 byte write with a read that
 * immediately follows it by using an "INDEX" cycle.
 */
static bool
gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
{
	return (i + 1 < num &&
		!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
		(msgs[i + 1].flags & I2C_M_RD));
}

static int
gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
{
	int reg_offset = dev_priv->gpio_mmio_base;
	u32 gmbus1_index = 0;
	u32 gmbus5 = 0;
	int ret;

	if (msgs[0].len == 2)
		gmbus5 = GMBUS_2BYTE_INDEX_EN |
			 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
	if (msgs[0].len == 1)
		gmbus1_index = GMBUS_CYCLE_INDEX |
			       (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);

	/* GMBUS5 holds 16-bit index */
	if (gmbus5)
		I915_WRITE(GMBUS5 + reg_offset, gmbus5);

	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);

	/* Clear GMBUS5 after each index transfer */
	if (gmbus5)
		I915_WRITE(GMBUS5 + reg_offset, 0);

	return ret;
}

static int
gmbus_xfer(struct i2c_adapter *adapter,
	   struct i2c_msg *msgs,
	   int num)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = bus->dev_priv;
	int i, reg_offset;
	int ret = 0;

	mutex_lock(&dev_priv->gmbus_mutex);

	if (bus->force_bit) {
		ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
		goto out;
	}

	reg_offset = dev_priv->gpio_mmio_base;

	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);

	for (i = 0; i < num; i++) {
		u32 gmbus2;

		if (gmbus_is_index_read(msgs, i, num)) {
			ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
			i += 1;  /* set i to the index of the read xfer */
		} else if (msgs[i].flags & I2C_M_RD) {
			ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
		} else {
			ret = gmbus_xfer_write(dev_priv, &msgs[i]);
		}

		if (ret == -ETIMEDOUT)
			goto timeout;
		if (ret == -ENXIO)
			goto clear_err;

		ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
			       (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE),
			       50);
		if (ret)
			goto timeout;
		if (gmbus2 & GMBUS_SATOER)
			goto clear_err;
	}

	/* Generate a STOP condition on the bus. Note that gmbus can't generata
	 * a STOP on the very first cycle. To simplify the code we
	 * unconditionally generate the STOP condition with an additional gmbus
	 * cycle. */
	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);

	/* Mark the GMBUS interface as disabled after waiting for idle.
	 * We will re-enable it at the start of the next xfer,
	 * till then let it sleep.
	 */
	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
		     10)) {
		DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
			 adapter->name);
		ret = -ETIMEDOUT;
	}
	I915_WRITE(GMBUS0 + reg_offset, 0);
	ret = ret ?: i;
	goto out;

clear_err:
	/*
	 * Wait for bus to IDLE before clearing NAK.
	 * If we clear the NAK while bus is still active, then it will stay
	 * active and the next transaction may fail.
	 *
	 * If no ACK is received during the address phase of a transaction, the
	 * adapter must report -ENXIO. It is not clear what to return if no ACK
	 * is received at other times. But we have to be careful to not return
	 * spurious -ENXIO because that will prevent i2c and drm edid functions
	 * from retrying. So return -ENXIO only when gmbus properly quiescents -
	 * timing out seems to happen when there _is_ a ddc chip present, but
	 * it's slow responding and only answers on the 2nd retry.
	 */
	ret = -ENXIO;
	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
		     10)) {
		DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
			      adapter->name);
		ret = -ETIMEDOUT;
	}

	/* Toggle the Software Clear Interrupt bit. This has the effect
	 * of resetting the GMBUS controller and so clearing the
	 * BUS_ERROR raised by the slave's NAK.
	 */
	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
	I915_WRITE(GMBUS1 + reg_offset, 0);
	I915_WRITE(GMBUS0 + reg_offset, 0);

	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
			 adapter->name, msgs[i].addr,
			 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);

	goto out;

timeout:
	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
		 bus->adapter.name, bus->reg0 & 0xff);
	I915_WRITE(GMBUS0 + reg_offset, 0);

	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
	bus->force_bit = true;
	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);

out:
	mutex_unlock(&dev_priv->gmbus_mutex);
	return ret;
}

static u32 gmbus_func(struct i2c_adapter *adapter)
{
	return i2c_bit_algo.functionality(adapter) &
		(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
		/* I2C_FUNC_10BIT_ADDR | */
		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
}

static const struct i2c_algorithm gmbus_algorithm = {
	.master_xfer	= gmbus_xfer,
	.functionality	= gmbus_func
};

/**
 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 * @dev: DRM device
 */
int intel_setup_gmbus(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret, i;

	if (HAS_PCH_SPLIT(dev))
		dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
	else
		dev_priv->gpio_mmio_base = 0;

	mutex_init(&dev_priv->gmbus_mutex);

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		u32 port = i + 1; /* +1 to map gmbus index to pin pair */

		bus->adapter.owner = THIS_MODULE;
		bus->adapter.class = I2C_CLASS_DDC;
		snprintf(bus->adapter.name,
			 sizeof(bus->adapter.name),
			 "i915 gmbus %s",
			 gmbus_ports[i].name);

		bus->adapter.dev.parent = &dev->pdev->dev;
		bus->dev_priv = dev_priv;

		bus->adapter.algo = &gmbus_algorithm;

		/* By default use a conservative clock rate */
		bus->reg0 = port | GMBUS_RATE_100KHZ;

		/* gmbus seems to be broken on i830 */
		if (IS_I830(dev))
			bus->force_bit = true;

		intel_gpio_setup(bus, port);

		ret = i2c_add_adapter(&bus->adapter);
		if (ret)
			goto err;
	}

	intel_i2c_reset(dev_priv->dev);

	return 0;

err:
	while (--i) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		i2c_del_adapter(&bus->adapter);
	}
	return ret;
}

struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
					    unsigned port)
{
	WARN_ON(!intel_gmbus_is_port_valid(port));
	/* -1 to map pin pair to gmbus index */
	return (intel_gmbus_is_port_valid(port)) ?
		&dev_priv->gmbus[port - 1].adapter : NULL;
}

void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
}

void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	bus->force_bit = force_bit;
}

void intel_teardown_gmbus(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		i2c_del_adapter(&bus->adapter);
	}
}
Commit	Line	Data
79e53945 JB	1	/*
79e53945 JB	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
f899fc64	3	* Copyright © 2006-2008,2010 Intel Corporation
79e53945 JB	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the next
	14	* paragraph) shall be included in all copies or substantial portions of the
	15	* Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	23	* DEALINGS IN THE SOFTWARE.
	24	*
	25	* Authors:
	26	* Eric Anholt <eric@anholt.net>
f899fc64	27	* Chris Wilson <chris@chris-wilson.co.uk>
79e53945 JB	28	*/
79e53945 JB	29	#include <linux/i2c.h>
79e53945	30	#include <linux/i2c-algo-bit.h>
2d1a8a48	31	#include <linux/export.h>
760285e7	32	#include <drm/drmP.h>
79e53945	33	#include "intel_drv.h"
760285e7	34	#include <drm/i915_drm.h>
79e53945 JB	35	#include "i915_drv.h"
79e53945 JB	36
2ed06c93 DK	37	struct gmbus_port {
	38	const char *name;
	39	int reg;
	40	};
	41
	42	static const struct gmbus_port gmbus_ports[] = {
	43	{ "ssc", GPIOB },
	44	{ "vga", GPIOA },
	45	{ "panel", GPIOC },
	46	{ "dpc", GPIOD },
	47	{ "dpb", GPIOE },
	48	{ "dpd", GPIOF },
	49	};
	50
f899fc64 CW	51	/* Intel GPIO access functions */
f899fc64 CW	52
1849ecb2	53	#define I2C_RISEFALL_TIME 10
f899fc64	54
e957d772 CW	55	static inline struct intel_gmbus *
	56	to_intel_gmbus(struct i2c_adapter *i2c)
	57	{
	58	return container_of(i2c, struct intel_gmbus, adapter);
	59	}
	60
f899fc64 CW	61	void
f899fc64 CW	62	intel_i2c_reset(struct drm_device *dev)
0ba0e9e1 SL	63	{
0ba0e9e1 SL	64	struct drm_i915_private *dev_priv = dev->dev_private;
110447fc	65	I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
f899fc64 CW	66	}
	67
	68	static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
	69	{
b222f267	70	u32 val;
0ba0e9e1 SL	71
0ba0e9e1 SL	72	/* When using bit bashing for I2C, this bit needs to be set to 1 */
f899fc64	73	if (!IS_PINEVIEW(dev_priv->dev))
0ba0e9e1	74	return;
b222f267 CW	75
b222f267 CW	76	val = I915_READ(DSPCLK_GATE_D);
0ba0e9e1	77	if (enable)
b222f267	78	val \|= DPCUNIT_CLOCK_GATE_DISABLE;
0ba0e9e1	79	else
b222f267 CW	80	val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
b222f267 CW	81	I915_WRITE(DSPCLK_GATE_D, val);
0ba0e9e1 SL	82	}
0ba0e9e1 SL	83
36c785f0	84	static u32 get_reserved(struct intel_gmbus *bus)
e957d772	85	{
36c785f0	86	struct drm_i915_private *dev_priv = bus->dev_priv;
e957d772 CW	87	struct drm_device *dev = dev_priv->dev;
	88	u32 reserved = 0;
	89
	90	/* On most chips, these bits must be preserved in software. */
	91	if (!IS_I830(dev) && !IS_845G(dev))
36c785f0	92	reserved = I915_READ_NOTRACE(bus->gpio_reg) &
db5e4172 YL	93	(GPIO_DATA_PULLUP_DISABLE \|
db5e4172 YL	94	GPIO_CLOCK_PULLUP_DISABLE);
e957d772 CW	95
	96	return reserved;
	97	}
	98
79e53945 JB	99	static int get_clock(void *data)
79e53945 JB	100	{
36c785f0 DV	101	struct intel_gmbus *bus = data;
	102	struct drm_i915_private *dev_priv = bus->dev_priv;
	103	u32 reserved = get_reserved(bus);
	104	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| GPIO_CLOCK_DIR_MASK);
	105	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	106	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
79e53945 JB	107	}
	108
	109	static int get_data(void *data)
	110	{
36c785f0 DV	111	struct intel_gmbus *bus = data;
	112	struct drm_i915_private *dev_priv = bus->dev_priv;
	113	u32 reserved = get_reserved(bus);
	114	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| GPIO_DATA_DIR_MASK);
	115	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	116	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
79e53945 JB	117	}
	118
	119	static void set_clock(void *data, int state_high)
	120	{
36c785f0 DV	121	struct intel_gmbus *bus = data;
	122	struct drm_i915_private *dev_priv = bus->dev_priv;
	123	u32 reserved = get_reserved(bus);
e957d772	124	u32 clock_bits;
79e53945 JB	125
	126	if (state_high)
	127	clock_bits = GPIO_CLOCK_DIR_IN \| GPIO_CLOCK_DIR_MASK;
	128	else
	129	clock_bits = GPIO_CLOCK_DIR_OUT \| GPIO_CLOCK_DIR_MASK \|
	130	GPIO_CLOCK_VAL_MASK;
f899fc64	131
36c785f0 DV	132	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| clock_bits);
36c785f0 DV	133	POSTING_READ(bus->gpio_reg);
79e53945 JB	134	}
	135
	136	static void set_data(void *data, int state_high)
	137	{
36c785f0 DV	138	struct intel_gmbus *bus = data;
	139	struct drm_i915_private *dev_priv = bus->dev_priv;
	140	u32 reserved = get_reserved(bus);
e957d772	141	u32 data_bits;
79e53945 JB	142
	143	if (state_high)
	144	data_bits = GPIO_DATA_DIR_IN \| GPIO_DATA_DIR_MASK;
	145	else
	146	data_bits = GPIO_DATA_DIR_OUT \| GPIO_DATA_DIR_MASK \|
	147	GPIO_DATA_VAL_MASK;
	148
36c785f0 DV	149	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| data_bits);
36c785f0 DV	150	POSTING_READ(bus->gpio_reg);
79e53945 JB	151	}
79e53945 JB	152
489fbc10 DK	153	static int
	154	intel_gpio_pre_xfer(struct i2c_adapter *adapter)
	155	{
	156	struct intel_gmbus *bus = container_of(adapter,
	157	struct intel_gmbus,
	158	adapter);
	159	struct drm_i915_private *dev_priv = bus->dev_priv;
	160
	161	intel_i2c_reset(dev_priv->dev);
	162	intel_i2c_quirk_set(dev_priv, true);
	163	set_data(bus, 1);
	164	set_clock(bus, 1);
	165	udelay(I2C_RISEFALL_TIME);
	166	return 0;
	167	}
	168
	169	static void
	170	intel_gpio_post_xfer(struct i2c_adapter *adapter)
	171	{
	172	struct intel_gmbus *bus = container_of(adapter,
	173	struct intel_gmbus,
	174	adapter);
	175	struct drm_i915_private *dev_priv = bus->dev_priv;
	176
	177	set_data(bus, 1);
	178	set_clock(bus, 1);
	179	intel_i2c_quirk_set(dev_priv, false);
	180	}
	181
2ed06c93	182	static void
f6f808c8	183	intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
f0217c42	184	{
36c785f0	185	struct drm_i915_private *dev_priv = bus->dev_priv;
36c785f0	186	struct i2c_algo_bit_data *algo;
f0217c42	187
c167a6fc	188	algo = &bus->bit_algo;
36c785f0	189
2ed06c93 DK	190	/* -1 to map pin pair to gmbus index */
2ed06c93 DK	191	bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
79e53945	192
c167a6fc	193	bus->adapter.algo_data = algo;
36c785f0 DV	194	algo->setsda = set_data;
	195	algo->setscl = set_clock;
	196	algo->getsda = get_data;
	197	algo->getscl = get_clock;
489fbc10 DK	198	algo->pre_xfer = intel_gpio_pre_xfer;
489fbc10 DK	199	algo->post_xfer = intel_gpio_post_xfer;
36c785f0 DV	200	algo->udelay = I2C_RISEFALL_TIME;
	201	algo->timeout = usecs_to_jiffies(2200);
	202	algo->data = bus;
79e53945 JB	203	}
79e53945 JB	204
924a93ed	205	static int
56f9eac0 DK	206	gmbus_xfer_read(struct drm_i915_private dev_priv, struct i2c_msg msg,
56f9eac0 DK	207	u32 gmbus1_index)
924a93ed DK	208	{
	209	int reg_offset = dev_priv->gpio_mmio_base;
	210	u16 len = msg->len;
	211	u8 *buf = msg->buf;
	212
	213	I915_WRITE(GMBUS1 + reg_offset,
56f9eac0	214	gmbus1_index \|
924a93ed	215	GMBUS_CYCLE_WAIT \|
924a93ed DK	216	(len << GMBUS_BYTE_COUNT_SHIFT) \|
	217	(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	218	GMBUS_SLAVE_READ \| GMBUS_SW_RDY);
79985eee	219	while (len) {
90e6b26d	220	int ret;
924a93ed	221	u32 val, loop = 0;
90e6b26d	222	u32 gmbus2;
924a93ed	223
90e6b26d DK	224	ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
	225	(GMBUS_SATOER \| GMBUS_HW_RDY),
	226	50);
	227	if (ret)
924a93ed	228	return -ETIMEDOUT;
90e6b26d	229	if (gmbus2 & GMBUS_SATOER)
924a93ed DK	230	return -ENXIO;
	231
	232	val = I915_READ(GMBUS3 + reg_offset);
	233	do {
	234	*buf++ = val & 0xff;
	235	val >>= 8;
	236	} while (--len && ++loop < 4);
79985eee	237	}
924a93ed DK	238
	239	return 0;
	240	}
	241
	242	static int
72d66afd	243	gmbus_xfer_write(struct drm_i915_private dev_priv, struct i2c_msg msg)
924a93ed DK	244	{
	245	int reg_offset = dev_priv->gpio_mmio_base;
	246	u16 len = msg->len;
	247	u8 *buf = msg->buf;
	248	u32 val, loop;
	249
	250	val = loop = 0;
26883c31 DK	251	while (len && loop < 4) {
	252	val \|= buf++ << (8 loop++);
	253	len -= 1;
	254	}
924a93ed DK	255
	256	I915_WRITE(GMBUS3 + reg_offset, val);
	257	I915_WRITE(GMBUS1 + reg_offset,
	258	GMBUS_CYCLE_WAIT \|
924a93ed DK	259	(msg->len << GMBUS_BYTE_COUNT_SHIFT) \|
	260	(msg->addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	261	GMBUS_SLAVE_WRITE \| GMBUS_SW_RDY);
924a93ed	262	while (len) {
90e6b26d DK	263	int ret;
	264	u32 gmbus2;
	265
924a93ed DK	266	val = loop = 0;
	267	do {
	268	val \|= buf++ << (8 loop);
	269	} while (--len && ++loop < 4);
	270
	271	I915_WRITE(GMBUS3 + reg_offset, val);
7a39a9d4	272
90e6b26d DK	273	ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
	274	(GMBUS_SATOER \| GMBUS_HW_RDY),
	275	50);
	276	if (ret)
7a39a9d4	277	return -ETIMEDOUT;
90e6b26d	278	if (gmbus2 & GMBUS_SATOER)
7a39a9d4	279	return -ENXIO;
924a93ed DK	280	}
	281	return 0;
	282	}
	283
56f9eac0 DK	284	/*
	285	* The gmbus controller can combine a 1 or 2 byte write with a read that
	286	* immediately follows it by using an "INDEX" cycle.
	287	*/
	288	static bool
	289	gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
	290	{
	291	return (i + 1 < num &&
	292	!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
	293	(msgs[i + 1].flags & I2C_M_RD));
	294	}
	295
	296	static int
	297	gmbus_xfer_index_read(struct drm_i915_private dev_priv, struct i2c_msg msgs)
	298	{
	299	int reg_offset = dev_priv->gpio_mmio_base;
	300	u32 gmbus1_index = 0;
	301	u32 gmbus5 = 0;
	302	int ret;
	303
	304	if (msgs[0].len == 2)
	305	gmbus5 = GMBUS_2BYTE_INDEX_EN \|
	306	msgs[0].buf[1] \| (msgs[0].buf[0] << 8);
	307	if (msgs[0].len == 1)
	308	gmbus1_index = GMBUS_CYCLE_INDEX \|
	309	(msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
	310
	311	/* GMBUS5 holds 16-bit index */
	312	if (gmbus5)
	313	I915_WRITE(GMBUS5 + reg_offset, gmbus5);
	314
	315	ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
	316
	317	/* Clear GMBUS5 after each index transfer */
	318	if (gmbus5)
	319	I915_WRITE(GMBUS5 + reg_offset, 0);
	320
	321	return ret;
	322	}
	323
f899fc64 CW	324	static int
	325	gmbus_xfer(struct i2c_adapter *adapter,
	326	struct i2c_msg *msgs,
	327	int num)
	328	{
	329	struct intel_gmbus *bus = container_of(adapter,
	330	struct intel_gmbus,
	331	adapter);
c2b9152f	332	struct drm_i915_private *dev_priv = bus->dev_priv;
72d66afd DK	333	int i, reg_offset;
72d66afd DK	334	int ret = 0;
f899fc64	335
8a8ed1f5 YS	336	mutex_lock(&dev_priv->gmbus_mutex);
	337
	338	if (bus->force_bit) {
489fbc10	339	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
8a8ed1f5 YS	340	goto out;
8a8ed1f5 YS	341	}
f899fc64	342
110447fc	343	reg_offset = dev_priv->gpio_mmio_base;
f899fc64	344
e957d772	345	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
f899fc64 CW	346
f899fc64 CW	347	for (i = 0; i < num; i++) {
90e6b26d DK	348	u32 gmbus2;
90e6b26d DK	349
56f9eac0 DK	350	if (gmbus_is_index_read(msgs, i, num)) {
	351	ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
	352	i += 1; /* set i to the index of the read xfer */
	353	} else if (msgs[i].flags & I2C_M_RD) {
	354	ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
	355	} else {
72d66afd	356	ret = gmbus_xfer_write(dev_priv, &msgs[i]);
56f9eac0	357	}
924a93ed DK	358
	359	if (ret == -ETIMEDOUT)
	360	goto timeout;
	361	if (ret == -ENXIO)
	362	goto clear_err;
	363
90e6b26d DK	364	ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
	365	(GMBUS_SATOER \| GMBUS_HW_WAIT_PHASE),
	366	50);
	367	if (ret)
f899fc64	368	goto timeout;
90e6b26d	369	if (gmbus2 & GMBUS_SATOER)
7f58aabc	370	goto clear_err;
f899fc64 CW	371	}
f899fc64 CW	372
72d66afd DK	373	/* Generate a STOP condition on the bus. Note that gmbus can't generata
	374	* a STOP on the very first cycle. To simplify the code we
	375	* unconditionally generate the STOP condition with an additional gmbus
	376	* cycle. */
	377	I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP \| GMBUS_SW_RDY);
	378
e646d577 DK	379	/* Mark the GMBUS interface as disabled after waiting for idle.
	380	* We will re-enable it at the start of the next xfer,
	381	* till then let it sleep.
	382	*/
72d66afd DK	383	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
72d66afd DK	384	10)) {
56fa6d6f	385	DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
e646d577	386	adapter->name);
72d66afd DK	387	ret = -ETIMEDOUT;
72d66afd DK	388	}
e646d577	389	I915_WRITE(GMBUS0 + reg_offset, 0);
72d66afd	390	ret = ret ?: i;
e646d577	391	goto out;
7f58aabc CW	392
7f58aabc CW	393	clear_err:
e646d577 DK	394	/*
	395	* Wait for bus to IDLE before clearing NAK.
	396	* If we clear the NAK while bus is still active, then it will stay
	397	* active and the next transaction may fail.
65e81866 DV	398	*
	399	* If no ACK is received during the address phase of a transaction, the
	400	* adapter must report -ENXIO. It is not clear what to return if no ACK
	401	* is received at other times. But we have to be careful to not return
	402	* spurious -ENXIO because that will prevent i2c and drm edid functions
	403	* from retrying. So return -ENXIO only when gmbus properly quiescents -
	404	* timing out seems to happen when there _is_ a ddc chip present, but
	405	* it's slow responding and only answers on the 2nd retry.
e646d577	406	*/
65e81866	407	ret = -ENXIO;
e646d577	408	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
65e81866	409	10)) {
56fa6d6f DK	410	DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
56fa6d6f DK	411	adapter->name);
65e81866 DV	412	ret = -ETIMEDOUT;
65e81866 DV	413	}
e646d577	414
7f58aabc CW	415	/* Toggle the Software Clear Interrupt bit. This has the effect
	416	* of resetting the GMBUS controller and so clearing the
	417	* BUS_ERROR raised by the slave's NAK.
	418	*/
	419	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
	420	I915_WRITE(GMBUS1 + reg_offset, 0);
e646d577	421	I915_WRITE(GMBUS0 + reg_offset, 0);
7f58aabc	422
56fa6d6f	423	DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
e646d577 DK	424	adapter->name, msgs[i].addr,
	425	(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
	426
8a8ed1f5	427	goto out;
f899fc64 CW	428
f899fc64 CW	429	timeout:
874e3cc9 DK	430	DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
874e3cc9 DK	431	bus->adapter.name, bus->reg0 & 0xff);
7f58aabc CW	432	I915_WRITE(GMBUS0 + reg_offset, 0);
7f58aabc CW	433
2ed06c93 DK	434	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
	435	bus->force_bit = true;
	436	ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
489fbc10	437
8a8ed1f5 YS	438	out:
	439	mutex_unlock(&dev_priv->gmbus_mutex);
	440	return ret;
f899fc64 CW	441	}
	442
	443	static u32 gmbus_func(struct i2c_adapter *adapter)
	444	{
f6f808c8 DV	445	return i2c_bit_algo.functionality(adapter) &
f6f808c8 DV	446	(I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
f899fc64 CW	447	/* I2C_FUNC_10BIT_ADDR \| */
	448	I2C_FUNC_SMBUS_READ_BLOCK_DATA \|
	449	I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
	450	}
	451
	452	static const struct i2c_algorithm gmbus_algorithm = {
	453	.master_xfer = gmbus_xfer,
	454	.functionality = gmbus_func
	455	};
	456
79e53945	457	/**
f899fc64 CW	458	* intel_gmbus_setup - instantiate all Intel i2c GMBuses
f899fc64 CW	459	* @dev: DRM device
79e53945	460	*/
f899fc64 CW	461	int intel_setup_gmbus(struct drm_device *dev)
f899fc64 CW	462	{
f899fc64 CW	463	struct drm_i915_private *dev_priv = dev->dev_private;
	464	int ret, i;
	465
110447fc DV	466	if (HAS_PCH_SPLIT(dev))
	467	dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
	468	else
	469	dev_priv->gpio_mmio_base = 0;
	470
8a8ed1f5 YS	471	mutex_init(&dev_priv->gmbus_mutex);
8a8ed1f5 YS	472
f899fc64 CW	473	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
f899fc64 CW	474	struct intel_gmbus *bus = &dev_priv->gmbus[i];
2ed06c93	475	u32 port = i + 1; /* +1 to map gmbus index to pin pair */
f899fc64 CW	476
	477	bus->adapter.owner = THIS_MODULE;
	478	bus->adapter.class = I2C_CLASS_DDC;
	479	snprintf(bus->adapter.name,
69669455 JD	480	sizeof(bus->adapter.name),
69669455 JD	481	"i915 gmbus %s",
2ed06c93	482	gmbus_ports[i].name);
f899fc64 CW	483
f899fc64 CW	484	bus->adapter.dev.parent = &dev->pdev->dev;
c2b9152f	485	bus->dev_priv = dev_priv;
f899fc64 CW	486
f899fc64 CW	487	bus->adapter.algo = &gmbus_algorithm;
f899fc64	488
e957d772	489	/* By default use a conservative clock rate */
2ed06c93	490	bus->reg0 = port \| GMBUS_RATE_100KHZ;
cb8ea752	491
83ee9e64 DV	492	/* gmbus seems to be broken on i830 */
	493	if (IS_I830(dev))
	494	bus->force_bit = true;
	495
2ed06c93	496	intel_gpio_setup(bus, port);
cee25168 JN	497
	498	ret = i2c_add_adapter(&bus->adapter);
	499	if (ret)
	500	goto err;
f899fc64 CW	501	}
	502
	503	intel_i2c_reset(dev_priv->dev);
	504
	505	return 0;
	506
	507	err:
	508	while (--i) {
	509	struct intel_gmbus *bus = &dev_priv->gmbus[i];
	510	i2c_del_adapter(&bus->adapter);
	511	}
f899fc64 CW	512	return ret;
	513	}
	514
3bd7d909 DK	515	struct i2c_adapter intel_gmbus_get_adapter(struct drm_i915_private dev_priv,
	516	unsigned port)
	517	{
	518	WARN_ON(!intel_gmbus_is_port_valid(port));
2ed06c93	519	/* -1 to map pin pair to gmbus index */
3bd7d909	520	return (intel_gmbus_is_port_valid(port)) ?
2ed06c93	521	&dev_priv->gmbus[port - 1].adapter : NULL;
3bd7d909 DK	522	}
3bd7d909 DK	523
e957d772 CW	524	void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
	525	{
	526	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	527
d5090b96	528	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) \| speed;
e957d772 CW	529	}
	530
	531	void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
	532	{
	533	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	534
2ed06c93	535	bus->force_bit = force_bit;
e957d772 CW	536	}
e957d772 CW	537
f899fc64	538	void intel_teardown_gmbus(struct drm_device *dev)
79e53945	539	{
f899fc64 CW	540	struct drm_i915_private *dev_priv = dev->dev_private;
f899fc64 CW	541	int i;
f9c10a9b	542
f899fc64 CW	543	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
f899fc64 CW	544	struct intel_gmbus *bus = &dev_priv->gmbus[i];
f899fc64 CW	545	i2c_del_adapter(&bus->adapter);
f899fc64 CW	546	}
79e53945	547	}