Commit | Line | Data |
---|---|---|
4e646495 JN |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Jani Nikula <jani.nikula@intel.com> | |
24 | */ | |
25 | ||
26 | #include <drm/drmP.h> | |
27 | #include <drm/drm_crtc.h> | |
28 | #include <drm/drm_edid.h> | |
29 | #include <drm/i915_drm.h> | |
30 | #include <linux/slab.h> | |
31 | #include "i915_drv.h" | |
32 | #include "intel_drv.h" | |
33 | #include "intel_dsi.h" | |
34 | #include "intel_dsi_cmd.h" | |
35 | ||
36 | /* the sub-encoders aka panel drivers */ | |
37 | static const struct intel_dsi_device intel_dsi_devices[] = { | |
2ab8b458 SK |
38 | { |
39 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, | |
40 | .name = "vbt-generic-dsi-vid-mode-display", | |
41 | .dev_ops = &vbt_generic_dsi_display_ops, | |
42 | }, | |
4e646495 JN |
43 | }; |
44 | ||
e9fe51c6 | 45 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
4ce8c9a7 SK |
46 | { |
47 | mutex_lock(&dev_priv->dpio_lock); | |
48 | ||
e9fe51c6 SK |
49 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
50 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); | |
51 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); | |
52 | udelay(150); | |
53 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); | |
54 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); | |
4ce8c9a7 SK |
55 | |
56 | mutex_unlock(&dev_priv->dpio_lock); | |
4ce8c9a7 SK |
57 | } |
58 | ||
4e646495 JN |
59 | static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector) |
60 | { | |
61 | return container_of(intel_attached_encoder(connector), | |
62 | struct intel_dsi, base); | |
63 | } | |
64 | ||
65 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) | |
66 | { | |
dfba2e2d | 67 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4e646495 JN |
68 | } |
69 | ||
70 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) | |
71 | { | |
dfba2e2d | 72 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4e646495 JN |
73 | } |
74 | ||
75 | static void intel_dsi_hot_plug(struct intel_encoder *encoder) | |
76 | { | |
77 | DRM_DEBUG_KMS("\n"); | |
78 | } | |
79 | ||
80 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, | |
81 | struct intel_crtc_config *config) | |
82 | { | |
83 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, | |
84 | base); | |
85 | struct intel_connector *intel_connector = intel_dsi->attached_connector; | |
86 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
87 | struct drm_display_mode *adjusted_mode = &config->adjusted_mode; | |
88 | struct drm_display_mode *mode = &config->requested_mode; | |
89 | ||
90 | DRM_DEBUG_KMS("\n"); | |
91 | ||
92 | if (fixed_mode) | |
93 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); | |
94 | ||
f573de5a SK |
95 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
96 | adjusted_mode->flags = 0; | |
97 | ||
4e646495 JN |
98 | if (intel_dsi->dev.dev_ops->mode_fixup) |
99 | return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev, | |
100 | mode, adjusted_mode); | |
101 | ||
102 | return true; | |
103 | } | |
104 | ||
5505a244 GS |
105 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
106 | { | |
107 | struct drm_device *dev = encoder->base.dev; | |
108 | struct drm_i915_private *dev_priv = dev->dev_private; | |
109 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
110 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
369602d3 | 111 | enum port port; |
5505a244 GS |
112 | u32 temp; |
113 | ||
a9da9bce GS |
114 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
115 | temp = I915_READ(VLV_CHICKEN_3); | |
116 | temp &= ~PIXEL_OVERLAP_CNT_MASK | | |
117 | intel_dsi->pixel_overlap << | |
118 | PIXEL_OVERLAP_CNT_SHIFT; | |
119 | I915_WRITE(VLV_CHICKEN_3, temp); | |
120 | } | |
121 | ||
369602d3 GS |
122 | for_each_dsi_port(port, intel_dsi->ports) { |
123 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
124 | temp &= ~LANE_CONFIGURATION_MASK; | |
125 | temp &= ~DUAL_LINK_MODE_MASK; | |
126 | ||
127 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { | |
128 | temp |= (intel_dsi->dual_link - 1) | |
129 | << DUAL_LINK_MODE_SHIFT; | |
130 | temp |= intel_crtc->pipe ? | |
131 | LANE_CONFIGURATION_DUAL_LINK_B : | |
132 | LANE_CONFIGURATION_DUAL_LINK_A; | |
133 | } | |
134 | /* assert ip_tg_enable signal */ | |
135 | I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE); | |
136 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
137 | } | |
5505a244 GS |
138 | } |
139 | ||
140 | static void intel_dsi_port_disable(struct intel_encoder *encoder) | |
141 | { | |
142 | struct drm_device *dev = encoder->base.dev; | |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
369602d3 GS |
144 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
145 | enum port port; | |
5505a244 GS |
146 | u32 temp; |
147 | ||
369602d3 GS |
148 | for_each_dsi_port(port, intel_dsi->ports) { |
149 | /* de-assert ip_tg_enable signal */ | |
150 | temp = I915_READ(MIPI_PORT_CTRL(port)); | |
151 | I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE); | |
152 | POSTING_READ(MIPI_PORT_CTRL(port)); | |
153 | } | |
5505a244 GS |
154 | } |
155 | ||
1dbd7cb2 | 156 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4e646495 | 157 | { |
1dbd7cb2 | 158 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
24ee0e64 GS |
159 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
160 | enum port port; | |
1dbd7cb2 SK |
161 | u32 val; |
162 | ||
4e646495 | 163 | DRM_DEBUG_KMS("\n"); |
4e646495 | 164 | |
2095f9fc SK |
165 | mutex_lock(&dev_priv->dpio_lock); |
166 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms | |
167 | * needed everytime after power gate */ | |
168 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); | |
169 | mutex_unlock(&dev_priv->dpio_lock); | |
170 | ||
171 | /* bandgap reset is needed after everytime we do power gate */ | |
172 | band_gap_reset(dev_priv); | |
173 | ||
24ee0e64 | 174 | for_each_dsi_port(port, intel_dsi->ports) { |
aceb365c | 175 | |
24ee0e64 GS |
176 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
177 | usleep_range(2500, 3000); | |
aceb365c | 178 | |
24ee0e64 | 179 | val = I915_READ(MIPI_PORT_CTRL(port)); |
bf344e80 GS |
180 | |
181 | /* Enable MIPI PHY transparent latch | |
182 | * Common bit for both MIPI Port A & MIPI Port C | |
183 | * No similar bit in MIPI Port C reg | |
184 | */ | |
185 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); | |
24ee0e64 | 186 | usleep_range(1000, 1500); |
aceb365c | 187 | |
24ee0e64 GS |
188 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
189 | usleep_range(2500, 3000); | |
190 | ||
191 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); | |
192 | usleep_range(2500, 3000); | |
193 | } | |
1dbd7cb2 | 194 | } |
1dbd7cb2 SK |
195 | |
196 | static void intel_dsi_enable(struct intel_encoder *encoder) | |
197 | { | |
198 | struct drm_device *dev = encoder->base.dev; | |
199 | struct drm_i915_private *dev_priv = dev->dev_private; | |
200 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
201 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
e7d7cad0 | 202 | enum port port = intel_dsi_pipe_to_port(intel_crtc->pipe); |
1dbd7cb2 SK |
203 | |
204 | DRM_DEBUG_KMS("\n"); | |
b9f5e07d | 205 | |
4e646495 | 206 | if (is_cmd_mode(intel_dsi)) |
e7d7cad0 | 207 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); |
1dbd7cb2 | 208 | else { |
4e646495 | 209 | msleep(20); /* XXX */ |
e1047028 | 210 | dpi_send_cmd(intel_dsi, TURN_ON, DPI_LP_MODE_EN); |
4e646495 JN |
211 | msleep(100); |
212 | ||
2634fd7f SK |
213 | if (intel_dsi->dev.dev_ops->enable) |
214 | intel_dsi->dev.dev_ops->enable(&intel_dsi->dev); | |
215 | ||
1381308b SK |
216 | wait_for_dsi_fifo_empty(intel_dsi); |
217 | ||
5505a244 | 218 | intel_dsi_port_enable(encoder); |
4e646495 | 219 | } |
2634fd7f SK |
220 | } |
221 | ||
222 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) | |
223 | { | |
20e5bf66 SK |
224 | struct drm_device *dev = encoder->base.dev; |
225 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2634fd7f | 226 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 SK |
227 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
228 | enum pipe pipe = intel_crtc->pipe; | |
229 | u32 tmp; | |
2634fd7f SK |
230 | |
231 | DRM_DEBUG_KMS("\n"); | |
232 | ||
20e5bf66 SK |
233 | /* Disable DPOunit clock gating, can stall pipe |
234 | * and we need DPLL REFA always enabled */ | |
235 | tmp = I915_READ(DPLL(pipe)); | |
236 | tmp |= DPLL_REFA_CLK_ENABLE_VLV; | |
237 | I915_WRITE(DPLL(pipe), tmp); | |
238 | ||
f573de5a SK |
239 | /* update the hw state for DPLL */ |
240 | intel_crtc->config.dpll_hw_state.dpll = DPLL_INTEGRATED_CLOCK_VLV | | |
7f3de833 | 241 | DPLL_REFA_CLK_ENABLE_VLV; |
f573de5a | 242 | |
20e5bf66 SK |
243 | tmp = I915_READ(DSPCLK_GATE_D); |
244 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; | |
245 | I915_WRITE(DSPCLK_GATE_D, tmp); | |
2634fd7f SK |
246 | |
247 | /* put device in ready state */ | |
248 | intel_dsi_device_ready(encoder); | |
4e646495 | 249 | |
df38e655 SK |
250 | msleep(intel_dsi->panel_on_delay); |
251 | ||
20e5bf66 SK |
252 | if (intel_dsi->dev.dev_ops->panel_reset) |
253 | intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev); | |
254 | ||
2634fd7f SK |
255 | if (intel_dsi->dev.dev_ops->send_otp_cmds) |
256 | intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev); | |
257 | ||
1381308b SK |
258 | wait_for_dsi_fifo_empty(intel_dsi); |
259 | ||
2634fd7f SK |
260 | /* Enable port in pre-enable phase itself because as per hw team |
261 | * recommendation, port should be enabled befor plane & pipe */ | |
262 | intel_dsi_enable(encoder); | |
263 | } | |
264 | ||
265 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) | |
266 | { | |
267 | DRM_DEBUG_KMS("\n"); | |
268 | ||
269 | /* for DSI port enable has to be done before pipe | |
270 | * and plane enable, so port enable is done in | |
271 | * pre_enable phase itself unlike other encoders | |
272 | */ | |
4e646495 JN |
273 | } |
274 | ||
c315faf8 ID |
275 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
276 | { | |
277 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); | |
278 | ||
279 | DRM_DEBUG_KMS("\n"); | |
280 | ||
281 | if (is_vid_mode(intel_dsi)) { | |
282 | /* Send Shutdown command to the panel in LP mode */ | |
283 | dpi_send_cmd(intel_dsi, SHUTDOWN, DPI_LP_MODE_EN); | |
284 | msleep(10); | |
285 | } | |
286 | } | |
287 | ||
4e646495 JN |
288 | static void intel_dsi_disable(struct intel_encoder *encoder) |
289 | { | |
1dbd7cb2 SK |
290 | struct drm_device *dev = encoder->base.dev; |
291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4e646495 | 292 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
384f02a2 | 293 | enum port port; |
4e646495 JN |
294 | u32 temp; |
295 | ||
296 | DRM_DEBUG_KMS("\n"); | |
297 | ||
4e646495 | 298 | if (is_vid_mode(intel_dsi)) { |
1381308b SK |
299 | wait_for_dsi_fifo_empty(intel_dsi); |
300 | ||
5505a244 | 301 | intel_dsi_port_disable(encoder); |
4e646495 JN |
302 | msleep(2); |
303 | } | |
304 | ||
384f02a2 GS |
305 | for_each_dsi_port(port, intel_dsi->ports) { |
306 | /* Panel commands can be sent when clock is in LP11 */ | |
307 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); | |
339023ec | 308 | |
384f02a2 GS |
309 | temp = I915_READ(MIPI_CTRL(port)); |
310 | temp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
311 | I915_WRITE(MIPI_CTRL(port), temp | | |
312 | intel_dsi->escape_clk_div << | |
313 | ESCAPE_CLOCK_DIVIDER_SHIFT); | |
339023ec | 314 | |
384f02a2 | 315 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
339023ec | 316 | |
384f02a2 GS |
317 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
318 | temp &= ~VID_MODE_FORMAT_MASK; | |
319 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); | |
339023ec | 320 | |
384f02a2 GS |
321 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
322 | } | |
1dbd7cb2 SK |
323 | /* if disable packets are sent before sending shutdown packet then in |
324 | * some next enable sequence send turn on packet error is observed */ | |
325 | if (intel_dsi->dev.dev_ops->disable) | |
326 | intel_dsi->dev.dev_ops->disable(&intel_dsi->dev); | |
1381308b SK |
327 | |
328 | wait_for_dsi_fifo_empty(intel_dsi); | |
4e646495 JN |
329 | } |
330 | ||
1dbd7cb2 | 331 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
4e646495 | 332 | { |
1dbd7cb2 | 333 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
384f02a2 GS |
334 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
335 | enum port port; | |
1dbd7cb2 SK |
336 | u32 val; |
337 | ||
4e646495 | 338 | DRM_DEBUG_KMS("\n"); |
384f02a2 | 339 | for_each_dsi_port(port, intel_dsi->ports) { |
be4fc046 | 340 | |
384f02a2 GS |
341 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
342 | ULPS_STATE_ENTER); | |
343 | usleep_range(2000, 2500); | |
344 | ||
345 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
346 | ULPS_STATE_EXIT); | |
347 | usleep_range(2000, 2500); | |
348 | ||
349 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | | |
350 | ULPS_STATE_ENTER); | |
351 | usleep_range(2000, 2500); | |
352 | ||
353 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A | |
354 | * only. MIPI Port C has no similar bit for checking | |
355 | */ | |
356 | if (wait_for(((I915_READ(MIPI_PORT_CTRL(PORT_A)) & AFE_LATCHOUT) | |
357 | == 0x00000), 30)) | |
358 | DRM_ERROR("DSI LP not going Low\n"); | |
359 | ||
360 | val = I915_READ(MIPI_PORT_CTRL(port)); | |
361 | /* Disable MIPI PHY transparent latch | |
362 | * Common bit for both MIPI Port A & MIPI Port C | |
363 | */ | |
364 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val & ~LP_OUTPUT_HOLD); | |
365 | usleep_range(1000, 1500); | |
366 | ||
367 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); | |
368 | usleep_range(2000, 2500); | |
369 | } | |
1dbd7cb2 | 370 | |
be4fc046 | 371 | vlv_disable_dsi_pll(encoder); |
4e646495 | 372 | } |
20e5bf66 | 373 | |
1dbd7cb2 SK |
374 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
375 | { | |
20e5bf66 | 376 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
1dbd7cb2 | 377 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
20e5bf66 | 378 | u32 val; |
1dbd7cb2 SK |
379 | |
380 | DRM_DEBUG_KMS("\n"); | |
381 | ||
c315faf8 ID |
382 | intel_dsi_disable(encoder); |
383 | ||
1dbd7cb2 SK |
384 | intel_dsi_clear_device_ready(encoder); |
385 | ||
20e5bf66 SK |
386 | val = I915_READ(DSPCLK_GATE_D); |
387 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; | |
388 | I915_WRITE(DSPCLK_GATE_D, val); | |
389 | ||
1dbd7cb2 SK |
390 | if (intel_dsi->dev.dev_ops->disable_panel_power) |
391 | intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev); | |
df38e655 SK |
392 | |
393 | msleep(intel_dsi->panel_off_delay); | |
394 | msleep(intel_dsi->panel_pwr_cycle_delay); | |
1dbd7cb2 | 395 | } |
4e646495 JN |
396 | |
397 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, | |
398 | enum pipe *pipe) | |
399 | { | |
400 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
6d129bea | 401 | enum intel_display_power_domain power_domain; |
e7d7cad0 JN |
402 | u32 port_ctl, func; |
403 | enum port port; | |
4e646495 JN |
404 | |
405 | DRM_DEBUG_KMS("\n"); | |
406 | ||
6d129bea | 407 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 408 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
409 | return false; |
410 | ||
4e646495 | 411 | /* XXX: this only works for one DSI output */ |
e7d7cad0 JN |
412 | for_each_dsi_port(port, (1 << PORT_A) | (1 << PORT_C)) { |
413 | port_ctl = I915_READ(MIPI_PORT_CTRL(port)); | |
414 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); | |
4e646495 | 415 | |
e7d7cad0 JN |
416 | if ((port_ctl & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
417 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { | |
418 | *pipe = port == PORT_A ? PIPE_A : PIPE_C; | |
4e646495 JN |
419 | return true; |
420 | } | |
421 | } | |
422 | } | |
423 | ||
424 | return false; | |
425 | } | |
426 | ||
427 | static void intel_dsi_get_config(struct intel_encoder *encoder, | |
428 | struct intel_crtc_config *pipe_config) | |
429 | { | |
f573de5a | 430 | u32 pclk; |
4e646495 JN |
431 | DRM_DEBUG_KMS("\n"); |
432 | ||
f573de5a SK |
433 | /* |
434 | * DPLL_MD is not used in case of DSI, reading will get some default value | |
435 | * set dpll_md = 0 | |
436 | */ | |
437 | pipe_config->dpll_hw_state.dpll_md = 0; | |
438 | ||
439 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); | |
440 | if (!pclk) | |
441 | return; | |
442 | ||
443 | pipe_config->adjusted_mode.crtc_clock = pclk; | |
444 | pipe_config->port_clock = pclk; | |
4e646495 JN |
445 | } |
446 | ||
c19de8eb DL |
447 | static enum drm_mode_status |
448 | intel_dsi_mode_valid(struct drm_connector *connector, | |
449 | struct drm_display_mode *mode) | |
4e646495 JN |
450 | { |
451 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
452 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
453 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
454 | ||
455 | DRM_DEBUG_KMS("\n"); | |
456 | ||
457 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { | |
458 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); | |
459 | return MODE_NO_DBLESCAN; | |
460 | } | |
461 | ||
462 | if (fixed_mode) { | |
463 | if (mode->hdisplay > fixed_mode->hdisplay) | |
464 | return MODE_PANEL; | |
465 | if (mode->vdisplay > fixed_mode->vdisplay) | |
466 | return MODE_PANEL; | |
467 | } | |
468 | ||
469 | return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode); | |
470 | } | |
471 | ||
472 | /* return txclkesc cycles in terms of divider and duration in us */ | |
473 | static u16 txclkesc(u32 divider, unsigned int us) | |
474 | { | |
475 | switch (divider) { | |
476 | case ESCAPE_CLOCK_DIVIDER_1: | |
477 | default: | |
478 | return 20 * us; | |
479 | case ESCAPE_CLOCK_DIVIDER_2: | |
480 | return 10 * us; | |
481 | case ESCAPE_CLOCK_DIVIDER_4: | |
482 | return 5 * us; | |
483 | } | |
484 | } | |
485 | ||
486 | /* return pixels in terms of txbyteclkhs */ | |
7f0c8605 SK |
487 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
488 | u16 burst_mode_ratio) | |
4e646495 | 489 | { |
7f0c8605 | 490 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
7f3de833 | 491 | 8 * 100), lane_count); |
4e646495 JN |
492 | } |
493 | ||
494 | static void set_dsi_timings(struct drm_encoder *encoder, | |
495 | const struct drm_display_mode *mode) | |
496 | { | |
497 | struct drm_device *dev = encoder->dev; | |
498 | struct drm_i915_private *dev_priv = dev->dev_private; | |
499 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
500 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
aa102d28 | 501 | enum port port; |
4e646495 JN |
502 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
503 | unsigned int lane_count = intel_dsi->lane_count; | |
504 | ||
505 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; | |
506 | ||
507 | hactive = mode->hdisplay; | |
508 | hfp = mode->hsync_start - mode->hdisplay; | |
509 | hsync = mode->hsync_end - mode->hsync_start; | |
510 | hbp = mode->htotal - mode->hsync_end; | |
511 | ||
aa102d28 GS |
512 | if (intel_dsi->dual_link) { |
513 | hactive /= 2; | |
514 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
515 | hactive += intel_dsi->pixel_overlap; | |
516 | hfp /= 2; | |
517 | hsync /= 2; | |
518 | hbp /= 2; | |
519 | } | |
520 | ||
4e646495 JN |
521 | vfp = mode->vsync_start - mode->vdisplay; |
522 | vsync = mode->vsync_end - mode->vsync_start; | |
523 | vbp = mode->vtotal - mode->vsync_end; | |
524 | ||
525 | /* horizontal values are in terms of high speed byte clock */ | |
7f0c8605 | 526 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
7f3de833 | 527 | intel_dsi->burst_mode_ratio); |
7f0c8605 SK |
528 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
529 | hsync = txbyteclkhs(hsync, bpp, lane_count, | |
7f3de833 | 530 | intel_dsi->burst_mode_ratio); |
7f0c8605 | 531 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
4e646495 | 532 | |
aa102d28 GS |
533 | for_each_dsi_port(port, intel_dsi->ports) { |
534 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); | |
535 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); | |
536 | ||
537 | /* meaningful for video mode non-burst sync pulse mode only, | |
538 | * can be zero for non-burst sync events and burst modes */ | |
539 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); | |
540 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); | |
541 | ||
542 | /* vertical values are in terms of lines */ | |
543 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); | |
544 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); | |
545 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); | |
546 | } | |
4e646495 JN |
547 | } |
548 | ||
07e4fb9e | 549 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4e646495 JN |
550 | { |
551 | struct drm_encoder *encoder = &intel_encoder->base; | |
552 | struct drm_device *dev = encoder->dev; | |
553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
554 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
555 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); | |
556 | struct drm_display_mode *adjusted_mode = | |
557 | &intel_crtc->config.adjusted_mode; | |
24ee0e64 | 558 | enum port port; |
4e646495 JN |
559 | unsigned int bpp = intel_crtc->config.pipe_bpp; |
560 | u32 val, tmp; | |
24ee0e64 | 561 | u16 mode_hdisplay; |
4e646495 | 562 | |
e7d7cad0 | 563 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4e646495 | 564 | |
24ee0e64 | 565 | mode_hdisplay = adjusted_mode->hdisplay; |
4e646495 | 566 | |
24ee0e64 GS |
567 | if (intel_dsi->dual_link) { |
568 | mode_hdisplay /= 2; | |
569 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) | |
570 | mode_hdisplay += intel_dsi->pixel_overlap; | |
571 | } | |
4e646495 | 572 | |
24ee0e64 GS |
573 | for_each_dsi_port(port, intel_dsi->ports) { |
574 | /* escape clock divider, 20MHz, shared for A and C. | |
575 | * device ready must be off when doing this! txclkesc? */ | |
576 | tmp = I915_READ(MIPI_CTRL(PORT_A)); | |
577 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; | |
578 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1); | |
579 | ||
580 | /* read request priority is per pipe */ | |
581 | tmp = I915_READ(MIPI_CTRL(port)); | |
582 | tmp &= ~READ_REQUEST_PRIORITY_MASK; | |
583 | I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH); | |
584 | ||
585 | /* XXX: why here, why like this? handling in irq handler?! */ | |
586 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); | |
587 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); | |
588 | ||
589 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); | |
590 | ||
591 | I915_WRITE(MIPI_DPI_RESOLUTION(port), | |
592 | adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT | | |
593 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); | |
594 | } | |
4e646495 JN |
595 | |
596 | set_dsi_timings(encoder, adjusted_mode); | |
597 | ||
598 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; | |
599 | if (is_cmd_mode(intel_dsi)) { | |
600 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; | |
601 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ | |
602 | } else { | |
603 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; | |
604 | ||
605 | /* XXX: cross-check bpp vs. pixel format? */ | |
606 | val |= intel_dsi->pixel_format; | |
607 | } | |
4e646495 | 608 | |
24ee0e64 GS |
609 | tmp = 0; |
610 | if (intel_dsi->eotp_pkt == 0) | |
611 | tmp |= EOT_DISABLE; | |
612 | if (intel_dsi->clock_stop) | |
613 | tmp |= CLOCKSTOP; | |
4e646495 | 614 | |
24ee0e64 GS |
615 | for_each_dsi_port(port, intel_dsi->ports) { |
616 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); | |
617 | ||
618 | /* timeouts for recovery. one frame IIUC. if counter expires, | |
619 | * EOT and stop state. */ | |
620 | ||
621 | /* | |
622 | * In burst mode, value greater than one DPI line Time in byte | |
623 | * clock (txbyteclkhs) To timeout this timer 1+ of the above | |
624 | * said value is recommended. | |
625 | * | |
626 | * In non-burst mode, Value greater than one DPI frame time in | |
627 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
628 | * said value is recommended. | |
629 | * | |
630 | * In DBI only mode, value greater than one DBI frame time in | |
631 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above | |
632 | * said value is recommended. | |
633 | */ | |
4e646495 | 634 | |
24ee0e64 GS |
635 | if (is_vid_mode(intel_dsi) && |
636 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { | |
637 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
638 | txbyteclkhs(adjusted_mode->htotal, bpp, | |
639 | intel_dsi->lane_count, | |
640 | intel_dsi->burst_mode_ratio) + 1); | |
641 | } else { | |
642 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), | |
643 | txbyteclkhs(adjusted_mode->vtotal * | |
644 | adjusted_mode->htotal, | |
645 | bpp, intel_dsi->lane_count, | |
646 | intel_dsi->burst_mode_ratio) + 1); | |
647 | } | |
648 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); | |
649 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), | |
650 | intel_dsi->turn_arnd_val); | |
651 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), | |
652 | intel_dsi->rst_timer_val); | |
f1c79f16 | 653 | |
24ee0e64 | 654 | /* dphy stuff */ |
f1c79f16 | 655 | |
24ee0e64 GS |
656 | /* in terms of low power clock */ |
657 | I915_WRITE(MIPI_INIT_COUNT(port), | |
658 | txclkesc(intel_dsi->escape_clk_div, 100)); | |
4e646495 | 659 | |
4e646495 | 660 | |
24ee0e64 GS |
661 | /* recovery disables */ |
662 | I915_WRITE(MIPI_EOT_DISABLE(port), val); | |
cf4dbd2e | 663 | |
24ee0e64 GS |
664 | /* in terms of low power clock */ |
665 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); | |
4e646495 | 666 | |
24ee0e64 GS |
667 | /* in terms of txbyteclkhs. actual high to low switch + |
668 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. | |
669 | * | |
670 | * XXX: write MIPI_STOP_STATE_STALL? | |
671 | */ | |
672 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), | |
673 | intel_dsi->hs_to_lp_count); | |
674 | ||
675 | /* XXX: low power clock equivalence in terms of byte clock. | |
676 | * the number of byte clocks occupied in one low power clock. | |
677 | * based on txbyteclkhs and txclkesc. | |
678 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL | |
679 | * ) / 105.??? | |
680 | */ | |
681 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); | |
682 | ||
683 | /* the bw essential for transmitting 16 long packets containing | |
684 | * 252 bytes meant for dcs write memory command is programmed in | |
685 | * this register in terms of byte clocks. based on dsi transfer | |
686 | * rate and the number of lanes configured the time taken to | |
687 | * transmit 16 long packets in a dsi stream varies. */ | |
688 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); | |
689 | ||
690 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), | |
691 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | | |
692 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); | |
693 | ||
694 | if (is_vid_mode(intel_dsi)) | |
695 | /* Some panels might have resolution which is not a | |
696 | * multiple of 64 like 1366 x 768. Enable RANDOM | |
697 | * resolution support for such panels by default */ | |
698 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), | |
699 | intel_dsi->video_frmt_cfg_bits | | |
700 | intel_dsi->video_mode_format | | |
701 | IP_TG_CONFIG | | |
702 | RANDOM_DPI_DISPLAY_RESOLUTION); | |
703 | } | |
4e646495 JN |
704 | } |
705 | ||
07e4fb9e DV |
706 | static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder) |
707 | { | |
708 | DRM_DEBUG_KMS("\n"); | |
709 | ||
710 | intel_dsi_prepare(encoder); | |
711 | ||
712 | vlv_enable_dsi_pll(encoder); | |
713 | } | |
714 | ||
4e646495 JN |
715 | static enum drm_connector_status |
716 | intel_dsi_detect(struct drm_connector *connector, bool force) | |
717 | { | |
718 | struct intel_dsi *intel_dsi = intel_attached_dsi(connector); | |
671dedd2 ID |
719 | struct intel_encoder *intel_encoder = &intel_dsi->base; |
720 | enum intel_display_power_domain power_domain; | |
721 | enum drm_connector_status connector_status; | |
722 | struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private; | |
723 | ||
4e646495 | 724 | DRM_DEBUG_KMS("\n"); |
671dedd2 ID |
725 | power_domain = intel_display_port_power_domain(intel_encoder); |
726 | ||
727 | intel_display_power_get(dev_priv, power_domain); | |
728 | connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev); | |
729 | intel_display_power_put(dev_priv, power_domain); | |
730 | ||
731 | return connector_status; | |
4e646495 JN |
732 | } |
733 | ||
734 | static int intel_dsi_get_modes(struct drm_connector *connector) | |
735 | { | |
736 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
737 | struct drm_display_mode *mode; | |
738 | ||
739 | DRM_DEBUG_KMS("\n"); | |
740 | ||
741 | if (!intel_connector->panel.fixed_mode) { | |
742 | DRM_DEBUG_KMS("no fixed mode\n"); | |
743 | return 0; | |
744 | } | |
745 | ||
746 | mode = drm_mode_duplicate(connector->dev, | |
747 | intel_connector->panel.fixed_mode); | |
748 | if (!mode) { | |
749 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); | |
750 | return 0; | |
751 | } | |
752 | ||
753 | drm_mode_probed_add(connector, mode); | |
754 | return 1; | |
755 | } | |
756 | ||
757 | static void intel_dsi_destroy(struct drm_connector *connector) | |
758 | { | |
759 | struct intel_connector *intel_connector = to_intel_connector(connector); | |
760 | ||
761 | DRM_DEBUG_KMS("\n"); | |
762 | intel_panel_fini(&intel_connector->panel); | |
4e646495 JN |
763 | drm_connector_cleanup(connector); |
764 | kfree(connector); | |
765 | } | |
766 | ||
767 | static const struct drm_encoder_funcs intel_dsi_funcs = { | |
768 | .destroy = intel_encoder_destroy, | |
769 | }; | |
770 | ||
771 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { | |
772 | .get_modes = intel_dsi_get_modes, | |
773 | .mode_valid = intel_dsi_mode_valid, | |
774 | .best_encoder = intel_best_encoder, | |
775 | }; | |
776 | ||
777 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { | |
778 | .dpms = intel_connector_dpms, | |
779 | .detect = intel_dsi_detect, | |
780 | .destroy = intel_dsi_destroy, | |
781 | .fill_modes = drm_helper_probe_single_connector_modes, | |
782 | }; | |
783 | ||
4328633d | 784 | void intel_dsi_init(struct drm_device *dev) |
4e646495 JN |
785 | { |
786 | struct intel_dsi *intel_dsi; | |
787 | struct intel_encoder *intel_encoder; | |
788 | struct drm_encoder *encoder; | |
789 | struct intel_connector *intel_connector; | |
790 | struct drm_connector *connector; | |
791 | struct drm_display_mode *fixed_mode = NULL; | |
b6fdd0f2 | 792 | struct drm_i915_private *dev_priv = dev->dev_private; |
4e646495 JN |
793 | const struct intel_dsi_device *dsi; |
794 | unsigned int i; | |
795 | ||
796 | DRM_DEBUG_KMS("\n"); | |
797 | ||
3e6bd011 SK |
798 | /* There is no detection method for MIPI so rely on VBT */ |
799 | if (!dev_priv->vbt.has_mipi) | |
4328633d | 800 | return; |
3e6bd011 | 801 | |
868d665b CJ |
802 | if (IS_VALLEYVIEW(dev)) { |
803 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; | |
804 | } else { | |
805 | DRM_ERROR("Unsupported Mipi device to reg base"); | |
806 | return; | |
807 | } | |
3e6bd011 | 808 | |
4e646495 JN |
809 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
810 | if (!intel_dsi) | |
4328633d | 811 | return; |
4e646495 JN |
812 | |
813 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); | |
814 | if (!intel_connector) { | |
815 | kfree(intel_dsi); | |
4328633d | 816 | return; |
4e646495 JN |
817 | } |
818 | ||
819 | intel_encoder = &intel_dsi->base; | |
820 | encoder = &intel_encoder->base; | |
821 | intel_dsi->attached_connector = intel_connector; | |
822 | ||
823 | connector = &intel_connector->base; | |
824 | ||
825 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI); | |
826 | ||
827 | /* XXX: very likely not all of these are needed */ | |
828 | intel_encoder->hot_plug = intel_dsi_hot_plug; | |
829 | intel_encoder->compute_config = intel_dsi_compute_config; | |
830 | intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable; | |
831 | intel_encoder->pre_enable = intel_dsi_pre_enable; | |
2634fd7f | 832 | intel_encoder->enable = intel_dsi_enable_nop; |
c315faf8 | 833 | intel_encoder->disable = intel_dsi_pre_disable; |
4e646495 JN |
834 | intel_encoder->post_disable = intel_dsi_post_disable; |
835 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; | |
836 | intel_encoder->get_config = intel_dsi_get_config; | |
837 | ||
838 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
4932e2c3 | 839 | intel_connector->unregister = intel_connector_unregister; |
4e646495 | 840 | |
e7d7cad0 | 841 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
17af40a8 | 842 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
e7d7cad0 | 843 | intel_encoder->crtc_mask = (1 << PIPE_A); |
17af40a8 JN |
844 | intel_dsi->ports = (1 << PORT_A); |
845 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { | |
e7d7cad0 | 846 | intel_encoder->crtc_mask = (1 << PIPE_B); |
17af40a8 JN |
847 | intel_dsi->ports = (1 << PORT_C); |
848 | } | |
e7d7cad0 | 849 | |
4e646495 JN |
850 | for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) { |
851 | dsi = &intel_dsi_devices[i]; | |
852 | intel_dsi->dev = *dsi; | |
853 | ||
854 | if (dsi->dev_ops->init(&intel_dsi->dev)) | |
855 | break; | |
856 | } | |
857 | ||
858 | if (i == ARRAY_SIZE(intel_dsi_devices)) { | |
859 | DRM_DEBUG_KMS("no device found\n"); | |
860 | goto err; | |
861 | } | |
862 | ||
863 | intel_encoder->type = INTEL_OUTPUT_DSI; | |
bc079e8b | 864 | intel_encoder->cloneable = 0; |
4e646495 JN |
865 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
866 | DRM_MODE_CONNECTOR_DSI); | |
867 | ||
868 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); | |
869 | ||
870 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ | |
871 | connector->interlace_allowed = false; | |
872 | connector->doublescan_allowed = false; | |
873 | ||
874 | intel_connector_attach_encoder(intel_connector, intel_encoder); | |
875 | ||
34ea3d38 | 876 | drm_connector_register(connector); |
4e646495 JN |
877 | |
878 | fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev); | |
879 | if (!fixed_mode) { | |
880 | DRM_DEBUG_KMS("no fixed mode\n"); | |
881 | goto err; | |
882 | } | |
883 | ||
884 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
4b6ed685 | 885 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
4e646495 | 886 | |
4328633d | 887 | return; |
4e646495 JN |
888 | |
889 | err: | |
890 | drm_encoder_cleanup(&intel_encoder->base); | |
891 | kfree(intel_dsi); | |
892 | kfree(intel_connector); | |
4e646495 | 893 | } |