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drm/i915: set bpc for DP transcoder
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
79e53945
JB		 34#include "drmP.h"
35#include "intel_drv.h"
36#include "i915_drm.h"
37#include "i915_drv.h"
e5510fac 38#include "i915_trace.h"
ab2c0672 39#include "drm_dp_helper.h"
79e53945
JB		 40
41#include "drm_crtc_helper.h"
42
32f9d658
ZW		 43#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
44
79e53945 45bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
7662c8bd 46static void intel_update_watermarks(struct drm_device *dev);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60} intel_clock_t;
61
62typedef struct {
63 int min, max;
64} intel_range_t;
65
66typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
79e53945
JB		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
d4906093
ML		 76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *);
78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *best_clock);
86static bool
87intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
88 int target, int refclk, intel_clock_t *best_clock);
79e53945 89
a4fc5ed6
KP		 90static bool
91intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
92 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 93static bool
f2b115e6
AJ		 94intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 96
021357ac
CW		 97static inline u32 /* units of 100MHz */
98intel_fdi_link_freq(struct drm_device *dev)
99{
8b99e68c
CW		 100 if (IS_GEN5(dev)) {
101 struct drm_i915_private *dev_priv = dev->dev_private;
102 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
103 } else
104 return 27;
021357ac
CW		 105}
106
e4b36699 107static const intel_limit_t intel_limits_i8xx_dvo = {
273e27ca
EA		 108 .dot = { .min = 25000, .max = 350000 },
109 .vco = { .min = 930000, .max = 1400000 },
110 .n = { .min = 3, .max = 16 },
111 .m = { .min = 96, .max = 140 },
112 .m1 = { .min = 18, .max = 26 },
113 .m2 = { .min = 6, .max = 16 },
114 .p = { .min = 4, .max = 128 },
115 .p1 = { .min = 2, .max = 33 },
116 .p2 = { .dot_limit = 165000,
117 .p2_slow = 4, .p2_fast = 2 },
d4906093 118 .find_pll = intel_find_best_PLL,
e4b36699
KP		 119};
120
121static const intel_limit_t intel_limits_i8xx_lvds = {
273e27ca
EA		 122 .dot = { .min = 25000, .max = 350000 },
123 .vco = { .min = 930000, .max = 1400000 },
124 .n = { .min = 3, .max = 16 },
125 .m = { .min = 96, .max = 140 },
126 .m1 = { .min = 18, .max = 26 },
127 .m2 = { .min = 6, .max = 16 },
128 .p = { .min = 4, .max = 128 },
129 .p1 = { .min = 1, .max = 6 },
130 .p2 = { .dot_limit = 165000,
131 .p2_slow = 14, .p2_fast = 7 },
d4906093 132 .find_pll = intel_find_best_PLL,
e4b36699 133};
273e27ca 134
e4b36699 135static const intel_limit_t intel_limits_i9xx_sdvo = {
273e27ca
EA		 136 .dot = { .min = 20000, .max = 400000 },
137 .vco = { .min = 1400000, .max = 2800000 },
138 .n = { .min = 1, .max = 6 },
139 .m = { .min = 70, .max = 120 },
140 .m1 = { .min = 10, .max = 22 },
141 .m2 = { .min = 5, .max = 9 },
142 .p = { .min = 5, .max = 80 },
143 .p1 = { .min = 1, .max = 8 },
144 .p2 = { .dot_limit = 200000,
145 .p2_slow = 10, .p2_fast = 5 },
d4906093 146 .find_pll = intel_find_best_PLL,
e4b36699
KP		 147};
148
149static const intel_limit_t intel_limits_i9xx_lvds = {
273e27ca
EA		 150 .dot = { .min = 20000, .max = 400000 },
151 .vco = { .min = 1400000, .max = 2800000 },
152 .n = { .min = 1, .max = 6 },
153 .m = { .min = 70, .max = 120 },
154 .m1 = { .min = 10, .max = 22 },
155 .m2 = { .min = 5, .max = 9 },
156 .p = { .min = 7, .max = 98 },
157 .p1 = { .min = 1, .max = 8 },
158 .p2 = { .dot_limit = 112000,
159 .p2_slow = 14, .p2_fast = 7 },
d4906093 160 .find_pll = intel_find_best_PLL,
e4b36699
KP		 161};
162
273e27ca 163
e4b36699 164static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 165 .dot = { .min = 25000, .max = 270000 },
166 .vco = { .min = 1750000, .max = 3500000},
167 .n = { .min = 1, .max = 4 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 10, .max = 30 },
172 .p1 = { .min = 1, .max = 3},
173 .p2 = { .dot_limit = 270000,
174 .p2_slow = 10,
175 .p2_fast = 10
044c7c41 176 },
d4906093 177 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 178};
179
180static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 181 .dot = { .min = 22000, .max = 400000 },
182 .vco = { .min = 1750000, .max = 3500000},
183 .n = { .min = 1, .max = 4 },
184 .m = { .min = 104, .max = 138 },
185 .m1 = { .min = 16, .max = 23 },
186 .m2 = { .min = 5, .max = 11 },
187 .p = { .min = 5, .max = 80 },
188 .p1 = { .min = 1, .max = 8},
189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 10, .p2_fast = 5 },
d4906093 191 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 192};
193
194static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 195 .dot = { .min = 20000, .max = 115000 },
196 .vco = { .min = 1750000, .max = 3500000 },
197 .n = { .min = 1, .max = 3 },
198 .m = { .min = 104, .max = 138 },
199 .m1 = { .min = 17, .max = 23 },
200 .m2 = { .min = 5, .max = 11 },
201 .p = { .min = 28, .max = 112 },
202 .p1 = { .min = 2, .max = 8 },
203 .p2 = { .dot_limit = 0,
204 .p2_slow = 14, .p2_fast = 14
044c7c41 205 },
d4906093 206 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 210 .dot = { .min = 80000, .max = 224000 },
211 .vco = { .min = 1750000, .max = 3500000 },
212 .n = { .min = 1, .max = 3 },
213 .m = { .min = 104, .max = 138 },
214 .m1 = { .min = 17, .max = 23 },
215 .m2 = { .min = 5, .max = 11 },
216 .p = { .min = 14, .max = 42 },
217 .p1 = { .min = 2, .max = 6 },
218 .p2 = { .dot_limit = 0,
219 .p2_slow = 7, .p2_fast = 7
044c7c41 220 },
d4906093 221 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 222};
223
224static const intel_limit_t intel_limits_g4x_display_port = {
273e27ca
EA		 225 .dot = { .min = 161670, .max = 227000 },
226 .vco = { .min = 1750000, .max = 3500000},
227 .n = { .min = 1, .max = 2 },
228 .m = { .min = 97, .max = 108 },
229 .m1 = { .min = 0x10, .max = 0x12 },
230 .m2 = { .min = 0x05, .max = 0x06 },
231 .p = { .min = 10, .max = 20 },
232 .p1 = { .min = 1, .max = 2},
233 .p2 = { .dot_limit = 0,
234 .p2_slow = 10, .p2_fast = 10 },
a4fc5ed6 235 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 236};
237
f2b115e6 238static const intel_limit_t intel_limits_pineview_sdvo = {
273e27ca
EA		 239 .dot = { .min = 20000, .max = 400000},
240 .vco = { .min = 1700000, .max = 3500000 },
241 /* Pineview's Ncounter is a ring counter */
242 .n = { .min = 3, .max = 6 },
243 .m = { .min = 2, .max = 256 },
244 /* Pineview only has one combined m divider, which we treat as m2. */
245 .m1 = { .min = 0, .max = 0 },
246 .m2 = { .min = 0, .max = 254 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8 },
249 .p2 = { .dot_limit = 200000,
250 .p2_slow = 10, .p2_fast = 5 },
6115707b 251 .find_pll = intel_find_best_PLL,
e4b36699
KP		 252};
253
f2b115e6 254static const intel_limit_t intel_limits_pineview_lvds = {
273e27ca
EA		 255 .dot = { .min = 20000, .max = 400000 },
256 .vco = { .min = 1700000, .max = 3500000 },
257 .n = { .min = 3, .max = 6 },
258 .m = { .min = 2, .max = 256 },
259 .m1 = { .min = 0, .max = 0 },
260 .m2 = { .min = 0, .max = 254 },
261 .p = { .min = 7, .max = 112 },
262 .p1 = { .min = 1, .max = 8 },
263 .p2 = { .dot_limit = 112000,
264 .p2_slow = 14, .p2_fast = 14 },
6115707b 265 .find_pll = intel_find_best_PLL,
e4b36699
KP		 266};
267
273e27ca
EA		 268/* Ironlake / Sandybridge
269 *
270 * We calculate clock using (register_value + 2) for N/M1/M2, so here
271 * the range value for them is (actual_value - 2).
272 */
b91ad0ec 273static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 5 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 10, .p2_fast = 5 },
4547668a 284 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 285};
286
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 118 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298 .find_pll = intel_g4x_find_best_PLL,
299};
300
301static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 3 },
305 .m = { .min = 79, .max = 127 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 14, .max = 56 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 312 .find_pll = intel_g4x_find_best_PLL,
313};
314
273e27ca 315/* LVDS 100mhz refclk limits. */
b91ad0ec 316static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 2 },
320 .m = { .min = 79, .max = 126 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2,.max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 327 .find_pll = intel_g4x_find_best_PLL,
328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 126 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 42 },
338 .p1 = { .min = 2,.max = 6 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 341 .find_pll = intel_g4x_find_best_PLL,
342};
343
344static const intel_limit_t intel_limits_ironlake_display_port = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000},
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 81, .max = 90 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 10, .max = 20 },
352 .p1 = { .min = 1, .max = 2},
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 10, .p2_fast = 10 },
4547668a 355 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 356};
357
1b894b59
CW		 358static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
359 int refclk)
2c07245f 360{
b91ad0ec
ZW		 361 struct drm_device *dev = crtc->dev;
362 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 363 const intel_limit_t *limit;
b91ad0ec
ZW		 364
365 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 366 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
367 LVDS_CLKB_POWER_UP) {
368 /* LVDS dual channel */
1b894b59 369 if (refclk == 100000)
b91ad0ec
ZW		 370 limit = &intel_limits_ironlake_dual_lvds_100m;
371 else
372 limit = &intel_limits_ironlake_dual_lvds;
373 } else {
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_single_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_single_lvds;
378 }
379 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 380 HAS_eDP)
381 limit = &intel_limits_ironlake_display_port;
2c07245f 382 else
b91ad0ec 383 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 384
385 return limit;
386}
387
044c7c41
ML		 388static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
389{
390 struct drm_device *dev = crtc->dev;
391 struct drm_i915_private *dev_priv = dev->dev_private;
392 const intel_limit_t *limit;
393
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
395 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
396 LVDS_CLKB_POWER_UP)
397 /* LVDS with dual channel */
e4b36699 398 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 399 else
400 /* LVDS with dual channel */
e4b36699 401 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 402 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
403 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 404 limit = &intel_limits_g4x_hdmi;
044c7c41 405 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 406 limit = &intel_limits_g4x_sdvo;
a4fc5ed6 407 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 408 limit = &intel_limits_g4x_display_port;
044c7c41 409 } else /* The option is for other outputs */
e4b36699 410 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 411
412 return limit;
413}
414
1b894b59 415static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 416{
417 struct drm_device *dev = crtc->dev;
418 const intel_limit_t *limit;
419
bad720ff 420 if (HAS_PCH_SPLIT(dev))
1b894b59 421 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 422 else if (IS_G4X(dev)) {
044c7c41 423 limit = intel_g4x_limit(crtc);
f2b115e6 424 } else if (IS_PINEVIEW(dev)) {
2177832f 425 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 426 limit = &intel_limits_pineview_lvds;
2177832f 427 else
f2b115e6 428 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 429 } else if (!IS_GEN2(dev)) {
430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
431 limit = &intel_limits_i9xx_lvds;
432 else
433 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 434 } else {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 436 limit = &intel_limits_i8xx_lvds;
79e53945 437 else
e4b36699 438 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 439 }
440 return limit;
441}
442
f2b115e6
AJ		 443/* m1 is reserved as 0 in Pineview, n is a ring counter */
444static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 445{
2177832f
SL		 446 clock->m = clock->m2 + 2;
447 clock->p = clock->p1 * clock->p2;
448 clock->vco = refclk * clock->m / clock->n;
449 clock->dot = clock->vco / clock->p;
450}
451
452static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
453{
f2b115e6
AJ		 454 if (IS_PINEVIEW(dev)) {
455 pineview_clock(refclk, clock);
2177832f
SL		 456 return;
457 }
79e53945
JB		 458 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
459 clock->p = clock->p1 * clock->p2;
460 clock->vco = refclk * clock->m / (clock->n + 2);
461 clock->dot = clock->vco / clock->p;
462}
463
79e53945
JB		 464/**
465 * Returns whether any output on the specified pipe is of the specified type
466 */
4ef69c7a 467bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 468{
4ef69c7a
CW		 469 struct drm_device *dev = crtc->dev;
470 struct drm_mode_config *mode_config = &dev->mode_config;
471 struct intel_encoder *encoder;
472
473 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
474 if (encoder->base.crtc == crtc && encoder->type == type)
475 return true;
476
477 return false;
79e53945
JB		 478}
479
7c04d1d9 480#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 481/**
482 * Returns whether the given set of divisors are valid for a given refclk with
483 * the given connectors.
484 */
485
1b894b59
CW		 486static bool intel_PLL_is_valid(struct drm_device *dev,
487 const intel_limit_t *limit,
488 const intel_clock_t *clock)
79e53945 489{
79e53945
JB		 490 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
491 INTELPllInvalid ("p1 out of range\n");
492 if (clock->p < limit->p.min || limit->p.max < clock->p)
493 INTELPllInvalid ("p out of range\n");
494 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
495 INTELPllInvalid ("m2 out of range\n");
496 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
497 INTELPllInvalid ("m1 out of range\n");
f2b115e6 498 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
79e53945
JB		 499 INTELPllInvalid ("m1 <= m2\n");
500 if (clock->m < limit->m.min || limit->m.max < clock->m)
501 INTELPllInvalid ("m out of range\n");
502 if (clock->n < limit->n.min || limit->n.max < clock->n)
503 INTELPllInvalid ("n out of range\n");
504 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
505 INTELPllInvalid ("vco out of range\n");
506 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
507 * connector, etc., rather than just a single range.
508 */
509 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
510 INTELPllInvalid ("dot out of range\n");
511
512 return true;
513}
514
d4906093
ML		 515static bool
516intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
517 int target, int refclk, intel_clock_t *best_clock)
518
79e53945
JB		 519{
520 struct drm_device *dev = crtc->dev;
521 struct drm_i915_private *dev_priv = dev->dev_private;
522 intel_clock_t clock;
79e53945
JB		 523 int err = target;
524
bc5e5718 525 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 526 (I915_READ(LVDS)) != 0) {
79e53945
JB		 527 /*
528 * For LVDS, if the panel is on, just rely on its current
529 * settings for dual-channel. We haven't figured out how to
530 * reliably set up different single/dual channel state, if we
531 * even can.
532 */
533 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
534 LVDS_CLKB_POWER_UP)
535 clock.p2 = limit->p2.p2_fast;
536 else
537 clock.p2 = limit->p2.p2_slow;
538 } else {
539 if (target < limit->p2.dot_limit)
540 clock.p2 = limit->p2.p2_slow;
541 else
542 clock.p2 = limit->p2.p2_fast;
543 }
544
545 memset (best_clock, 0, sizeof (*best_clock));
546
42158660
ZY		 547 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
548 clock.m1++) {
549 for (clock.m2 = limit->m2.min;
550 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 551 /* m1 is always 0 in Pineview */
552 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 553 break;
554 for (clock.n = limit->n.min;
555 clock.n <= limit->n.max; clock.n++) {
556 for (clock.p1 = limit->p1.min;
557 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 558 int this_err;
559
2177832f 560 intel_clock(dev, refclk, &clock);
1b894b59
CW		 561 if (!intel_PLL_is_valid(dev, limit,
562 &clock))
79e53945
JB		 563 continue;
564
565 this_err = abs(clock.dot - target);
566 if (this_err < err) {
567 *best_clock = clock;
568 err = this_err;
569 }
570 }
571 }
572 }
573 }
574
575 return (err != target);
576}
577
d4906093
ML		 578static bool
579intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
580 int target, int refclk, intel_clock_t *best_clock)
581{
582 struct drm_device *dev = crtc->dev;
583 struct drm_i915_private *dev_priv = dev->dev_private;
584 intel_clock_t clock;
585 int max_n;
586 bool found;
6ba770dc
AJ		 587 /* approximately equals target * 0.00585 */
588 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 589 found = false;
590
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 592 int lvds_reg;
593
c619eed4 594 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 595 lvds_reg = PCH_LVDS;
596 else
597 lvds_reg = LVDS;
598 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 599 LVDS_CLKB_POWER_UP)
600 clock.p2 = limit->p2.p2_fast;
601 else
602 clock.p2 = limit->p2.p2_slow;
603 } else {
604 if (target < limit->p2.dot_limit)
605 clock.p2 = limit->p2.p2_slow;
606 else
607 clock.p2 = limit->p2.p2_fast;
608 }
609
610 memset(best_clock, 0, sizeof(*best_clock));
611 max_n = limit->n.max;
f77f13e2 612 /* based on hardware requirement, prefer smaller n to precision */
d4906093 613 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 614 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 615 for (clock.m1 = limit->m1.max;
616 clock.m1 >= limit->m1.min; clock.m1--) {
617 for (clock.m2 = limit->m2.max;
618 clock.m2 >= limit->m2.min; clock.m2--) {
619 for (clock.p1 = limit->p1.max;
620 clock.p1 >= limit->p1.min; clock.p1--) {
621 int this_err;
622
2177832f 623 intel_clock(dev, refclk, &clock);
1b894b59
CW		 624 if (!intel_PLL_is_valid(dev, limit,
625 &clock))
d4906093 626 continue;
1b894b59
CW		 627
628 this_err = abs(clock.dot - target);
d4906093
ML		 629 if (this_err < err_most) {
630 *best_clock = clock;
631 err_most = this_err;
632 max_n = clock.n;
633 found = true;
634 }
635 }
636 }
637 }
638 }
2c07245f
ZW		 639 return found;
640}
641
5eb08b69 642static bool
f2b115e6
AJ		 643intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
644 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 645{
646 struct drm_device *dev = crtc->dev;
647 intel_clock_t clock;
4547668a 648
5eb08b69
ZW		 649 if (target < 200000) {
650 clock.n = 1;
651 clock.p1 = 2;
652 clock.p2 = 10;
653 clock.m1 = 12;
654 clock.m2 = 9;
655 } else {
656 clock.n = 2;
657 clock.p1 = 1;
658 clock.p2 = 10;
659 clock.m1 = 14;
660 clock.m2 = 8;
661 }
662 intel_clock(dev, refclk, &clock);
663 memcpy(best_clock, &clock, sizeof(intel_clock_t));
664 return true;
665}
666
a4fc5ed6
KP		 667/* DisplayPort has only two frequencies, 162MHz and 270MHz */
668static bool
669intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *best_clock)
671{
5eddb70b
CW		 672 intel_clock_t clock;
673 if (target < 200000) {
674 clock.p1 = 2;
675 clock.p2 = 10;
676 clock.n = 2;
677 clock.m1 = 23;
678 clock.m2 = 8;
679 } else {
680 clock.p1 = 1;
681 clock.p2 = 10;
682 clock.n = 1;
683 clock.m1 = 14;
684 clock.m2 = 2;
685 }
686 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
687 clock.p = (clock.p1 * clock.p2);
688 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
689 clock.vco = 0;
690 memcpy(best_clock, &clock, sizeof(intel_clock_t));
691 return true;
a4fc5ed6
KP		 692}
693
9d0498a2
JB		 694/**
695 * intel_wait_for_vblank - wait for vblank on a given pipe
696 * @dev: drm device
697 * @pipe: pipe to wait for
698 *
699 * Wait for vblank to occur on a given pipe. Needed for various bits of
700 * mode setting code.
701 */
702void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 703{
9d0498a2 704 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 705 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 706
300387c0
CW		 707 /* Clear existing vblank status. Note this will clear any other
708 * sticky status fields as well.
709 *
710 * This races with i915_driver_irq_handler() with the result
711 * that either function could miss a vblank event. Here it is not
712 * fatal, as we will either wait upon the next vblank interrupt or
713 * timeout. Generally speaking intel_wait_for_vblank() is only
714 * called during modeset at which time the GPU should be idle and
715 * should *not* be performing page flips and thus not waiting on
716 * vblanks...
717 * Currently, the result of us stealing a vblank from the irq
718 * handler is that a single frame will be skipped during swapbuffers.
719 */
720 I915_WRITE(pipestat_reg,
721 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
722
9d0498a2 723 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 724 if (wait_for(I915_READ(pipestat_reg) &
725 PIPE_VBLANK_INTERRUPT_STATUS,
726 50))
9d0498a2
JB		 727 DRM_DEBUG_KMS("vblank wait timed out\n");
728}
729
ab7ad7f6
KP		 730/*
731 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 732 * @dev: drm device
733 * @pipe: pipe to wait for
734 *
735 * After disabling a pipe, we can't wait for vblank in the usual way,
736 * spinning on the vblank interrupt status bit, since we won't actually
737 * see an interrupt when the pipe is disabled.
738 *
ab7ad7f6
KP		 739 * On Gen4 and above:
740 * wait for the pipe register state bit to turn off
741 *
742 * Otherwise:
743 * wait for the display line value to settle (it usually
744 * ends up stopping at the start of the next frame).
58e10eb9 745 *
9d0498a2 746 */
58e10eb9 747void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 748{
749 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 750
751 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 752 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 753
754 /* Wait for the Pipe State to go off */
58e10eb9
CW		 755 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
756 100))
ab7ad7f6
KP		 757 DRM_DEBUG_KMS("pipe_off wait timed out\n");
758 } else {
759 u32 last_line;
58e10eb9 760 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 761 unsigned long timeout = jiffies + msecs_to_jiffies(100);
762
763 /* Wait for the display line to settle */
764 do {
58e10eb9 765 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 766 mdelay(5);
58e10eb9 767 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 768 time_after(timeout, jiffies));
769 if (time_after(jiffies, timeout))
770 DRM_DEBUG_KMS("pipe_off wait timed out\n");
771 }
79e53945
JB		 772}
773
b24e7179
JB		 774static const char *state_string(bool enabled)
775{
776 return enabled ? "on" : "off";
777}
778
779/* Only for pre-ILK configs */
780static void assert_pll(struct drm_i915_private *dev_priv,
781 enum pipe pipe, bool state)
782{
783 int reg;
784 u32 val;
785 bool cur_state;
786
787 reg = DPLL(pipe);
788 val = I915_READ(reg);
789 cur_state = !!(val & DPLL_VCO_ENABLE);
790 WARN(cur_state != state,
791 "PLL state assertion failure (expected %s, current %s)\n",
792 state_string(state), state_string(cur_state));
793}
794#define assert_pll_enabled(d, p) assert_pll(d, p, true)
795#define assert_pll_disabled(d, p) assert_pll(d, p, false)
796
040484af
JB		 797/* For ILK+ */
798static void assert_pch_pll(struct drm_i915_private *dev_priv,
799 enum pipe pipe, bool state)
800{
801 int reg;
802 u32 val;
803 bool cur_state;
804
805 reg = PCH_DPLL(pipe);
806 val = I915_READ(reg);
807 cur_state = !!(val & DPLL_VCO_ENABLE);
808 WARN(cur_state != state,
809 "PCH PLL state assertion failure (expected %s, current %s)\n",
810 state_string(state), state_string(cur_state));
811}
812#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
813#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
814
815static void assert_fdi_tx(struct drm_i915_private *dev_priv,
816 enum pipe pipe, bool state)
817{
818 int reg;
819 u32 val;
820 bool cur_state;
821
822 reg = FDI_TX_CTL(pipe);
823 val = I915_READ(reg);
824 cur_state = !!(val & FDI_TX_ENABLE);
825 WARN(cur_state != state,
826 "FDI TX state assertion failure (expected %s, current %s)\n",
827 state_string(state), state_string(cur_state));
828}
829#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
830#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
831
832static void assert_fdi_rx(struct drm_i915_private *dev_priv,
833 enum pipe pipe, bool state)
834{
835 int reg;
836 u32 val;
837 bool cur_state;
838
839 reg = FDI_RX_CTL(pipe);
840 val = I915_READ(reg);
841 cur_state = !!(val & FDI_RX_ENABLE);
842 WARN(cur_state != state,
843 "FDI RX state assertion failure (expected %s, current %s)\n",
844 state_string(state), state_string(cur_state));
845}
846#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
847#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
848
849static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
850 enum pipe pipe)
851{
852 int reg;
853 u32 val;
854
855 /* ILK FDI PLL is always enabled */
856 if (dev_priv->info->gen == 5)
857 return;
858
859 reg = FDI_TX_CTL(pipe);
860 val = I915_READ(reg);
861 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
862}
863
864static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
865 enum pipe pipe)
866{
867 int reg;
868 u32 val;
869
870 reg = FDI_RX_CTL(pipe);
871 val = I915_READ(reg);
872 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
873}
874
ea0760cf
JB		 875static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
876 enum pipe pipe)
877{
878 int pp_reg, lvds_reg;
879 u32 val;
880 enum pipe panel_pipe = PIPE_A;
881 bool locked = locked;
882
883 if (HAS_PCH_SPLIT(dev_priv->dev)) {
884 pp_reg = PCH_PP_CONTROL;
885 lvds_reg = PCH_LVDS;
886 } else {
887 pp_reg = PP_CONTROL;
888 lvds_reg = LVDS;
889 }
890
891 val = I915_READ(pp_reg);
892 if (!(val & PANEL_POWER_ON) ||
893 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
894 locked = false;
895
896 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
897 panel_pipe = PIPE_B;
898
899 WARN(panel_pipe == pipe && locked,
900 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 901 pipe_name(pipe));
ea0760cf
JB		 902}
903
63d7bbe9
JB		 904static void assert_pipe(struct drm_i915_private *dev_priv,
905 enum pipe pipe, bool state)
b24e7179
JB		 906{
907 int reg;
908 u32 val;
63d7bbe9 909 bool cur_state;
b24e7179
JB		 910
911 reg = PIPECONF(pipe);
912 val = I915_READ(reg);
63d7bbe9
JB		 913 cur_state = !!(val & PIPECONF_ENABLE);
914 WARN(cur_state != state,
915 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 916 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 917}
63d7bbe9
JB		 918#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
919#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 920
921static void assert_plane_enabled(struct drm_i915_private *dev_priv,
922 enum plane plane)
923{
924 int reg;
925 u32 val;
926
927 reg = DSPCNTR(plane);
928 val = I915_READ(reg);
929 WARN(!(val & DISPLAY_PLANE_ENABLE),
930 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 931 plane_name(plane));
b24e7179
JB		 932}
933
934static void assert_planes_disabled(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936{
937 int reg, i;
938 u32 val;
939 int cur_pipe;
940
19ec1358
JB		 941 /* Planes are fixed to pipes on ILK+ */
942 if (HAS_PCH_SPLIT(dev_priv->dev))
943 return;
944
b24e7179
JB		 945 /* Need to check both planes against the pipe */
946 for (i = 0; i < 2; i++) {
947 reg = DSPCNTR(i);
948 val = I915_READ(reg);
949 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
950 DISPPLANE_SEL_PIPE_SHIFT;
951 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 952 "plane %c assertion failure, should be off on pipe %c but is still active\n",
953 plane_name(i), pipe_name(pipe));
b24e7179
JB		 954 }
955}
956
92f2584a
JB		 957static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
958{
959 u32 val;
960 bool enabled;
961
962 val = I915_READ(PCH_DREF_CONTROL);
963 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
964 DREF_SUPERSPREAD_SOURCE_MASK));
965 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
966}
967
968static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
969 enum pipe pipe)
970{
971 int reg;
972 u32 val;
973 bool enabled;
974
975 reg = TRANSCONF(pipe);
976 val = I915_READ(reg);
977 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 978 WARN(enabled,
979 "transcoder assertion failed, should be off on pipe %c but is still active\n",
980 pipe_name(pipe));
92f2584a
JB		 981}
982
291906f1
JB		 983static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
984 enum pipe pipe, int reg)
985{
47a05eca
JB		 986 u32 val = I915_READ(reg);
987 WARN(DP_PIPE_ENABLED(val, pipe),
291906f1 988 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 989 reg, pipe_name(pipe));
291906f1
JB		 990}
991
992static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe, int reg)
994{
47a05eca
JB		 995 u32 val = I915_READ(reg);
996 WARN(HDMI_PIPE_ENABLED(val, pipe),
291906f1 997 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 998 reg, pipe_name(pipe));
291906f1
JB		 999}
1000
1001static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
291906f1
JB		 1006
1007 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B);
1008 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C);
1009 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D);
1010
1011 reg = PCH_ADPA;
1012 val = I915_READ(reg);
47a05eca 1013 WARN(ADPA_PIPE_ENABLED(val, pipe),
291906f1 1014 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1015 pipe_name(pipe));
291906f1
JB		 1016
1017 reg = PCH_LVDS;
1018 val = I915_READ(reg);
47a05eca 1019 WARN(LVDS_PIPE_ENABLED(val, pipe),
291906f1 1020 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1021 pipe_name(pipe));
291906f1
JB		 1022
1023 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1024 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1025 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1026}
1027
63d7bbe9
JB		 1028/**
1029 * intel_enable_pll - enable a PLL
1030 * @dev_priv: i915 private structure
1031 * @pipe: pipe PLL to enable
1032 *
1033 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1034 * make sure the PLL reg is writable first though, since the panel write
1035 * protect mechanism may be enabled.
1036 *
1037 * Note! This is for pre-ILK only.
1038 */
1039static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1040{
1041 int reg;
1042 u32 val;
1043
1044 /* No really, not for ILK+ */
1045 BUG_ON(dev_priv->info->gen >= 5);
1046
1047 /* PLL is protected by panel, make sure we can write it */
1048 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1049 assert_panel_unlocked(dev_priv, pipe);
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 val |= DPLL_VCO_ENABLE;
1054
1055 /* We do this three times for luck */
1056 I915_WRITE(reg, val);
1057 POSTING_READ(reg);
1058 udelay(150); /* wait for warmup */
1059 I915_WRITE(reg, val);
1060 POSTING_READ(reg);
1061 udelay(150); /* wait for warmup */
1062 I915_WRITE(reg, val);
1063 POSTING_READ(reg);
1064 udelay(150); /* wait for warmup */
1065}
1066
1067/**
1068 * intel_disable_pll - disable a PLL
1069 * @dev_priv: i915 private structure
1070 * @pipe: pipe PLL to disable
1071 *
1072 * Disable the PLL for @pipe, making sure the pipe is off first.
1073 *
1074 * Note! This is for pre-ILK only.
1075 */
1076static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1077{
1078 int reg;
1079 u32 val;
1080
1081 /* Don't disable pipe A or pipe A PLLs if needed */
1082 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1083 return;
1084
1085 /* Make sure the pipe isn't still relying on us */
1086 assert_pipe_disabled(dev_priv, pipe);
1087
1088 reg = DPLL(pipe);
1089 val = I915_READ(reg);
1090 val &= ~DPLL_VCO_ENABLE;
1091 I915_WRITE(reg, val);
1092 POSTING_READ(reg);
1093}
1094
92f2584a
JB		 1095/**
1096 * intel_enable_pch_pll - enable PCH PLL
1097 * @dev_priv: i915 private structure
1098 * @pipe: pipe PLL to enable
1099 *
1100 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1101 * drives the transcoder clock.
1102 */
1103static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1104 enum pipe pipe)
1105{
1106 int reg;
1107 u32 val;
1108
1109 /* PCH only available on ILK+ */
1110 BUG_ON(dev_priv->info->gen < 5);
1111
1112 /* PCH refclock must be enabled first */
1113 assert_pch_refclk_enabled(dev_priv);
1114
1115 reg = PCH_DPLL(pipe);
1116 val = I915_READ(reg);
1117 val |= DPLL_VCO_ENABLE;
1118 I915_WRITE(reg, val);
1119 POSTING_READ(reg);
1120 udelay(200);
1121}
1122
1123static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1124 enum pipe pipe)
1125{
1126 int reg;
1127 u32 val;
1128
1129 /* PCH only available on ILK+ */
1130 BUG_ON(dev_priv->info->gen < 5);
1131
1132 /* Make sure transcoder isn't still depending on us */
1133 assert_transcoder_disabled(dev_priv, pipe);
1134
1135 reg = PCH_DPLL(pipe);
1136 val = I915_READ(reg);
1137 val &= ~DPLL_VCO_ENABLE;
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(200);
1141}
1142
040484af
JB		 1143static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145{
1146 int reg;
1147 u32 val;
1148
1149 /* PCH only available on ILK+ */
1150 BUG_ON(dev_priv->info->gen < 5);
1151
1152 /* Make sure PCH DPLL is enabled */
1153 assert_pch_pll_enabled(dev_priv, pipe);
1154
1155 /* FDI must be feeding us bits for PCH ports */
1156 assert_fdi_tx_enabled(dev_priv, pipe);
1157 assert_fdi_rx_enabled(dev_priv, pipe);
1158
1159 reg = TRANSCONF(pipe);
1160 val = I915_READ(reg);
e9bcff5c
JB		 1161
1162 if (HAS_PCH_IBX(dev_priv->dev)) {
1163 /*
1164 * make the BPC in transcoder be consistent with
1165 * that in pipeconf reg.
1166 */
1167 val &= ~PIPE_BPC_MASK;
1168 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1169 }
040484af
JB		 1170 I915_WRITE(reg, val | TRANS_ENABLE);
1171 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1172 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1173}
1174
1175static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int reg;
1179 u32 val;
1180
1181 /* FDI relies on the transcoder */
1182 assert_fdi_tx_disabled(dev_priv, pipe);
1183 assert_fdi_rx_disabled(dev_priv, pipe);
1184
291906f1
JB		 1185 /* Ports must be off as well */
1186 assert_pch_ports_disabled(dev_priv, pipe);
1187
040484af
JB		 1188 reg = TRANSCONF(pipe);
1189 val = I915_READ(reg);
1190 val &= ~TRANS_ENABLE;
1191 I915_WRITE(reg, val);
1192 /* wait for PCH transcoder off, transcoder state */
1193 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1194 DRM_ERROR("failed to disable transcoder\n");
1195}
1196
b24e7179 1197/**
309cfea8 1198 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1199 * @dev_priv: i915 private structure
1200 * @pipe: pipe to enable
040484af 1201 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1202 *
1203 * Enable @pipe, making sure that various hardware specific requirements
1204 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1205 *
1206 * @pipe should be %PIPE_A or %PIPE_B.
1207 *
1208 * Will wait until the pipe is actually running (i.e. first vblank) before
1209 * returning.
1210 */
040484af
JB		 1211static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1212 bool pch_port)
b24e7179
JB		 1213{
1214 int reg;
1215 u32 val;
1216
1217 /*
1218 * A pipe without a PLL won't actually be able to drive bits from
1219 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1220 * need the check.
1221 */
1222 if (!HAS_PCH_SPLIT(dev_priv->dev))
1223 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1224 else {
1225 if (pch_port) {
1226 /* if driving the PCH, we need FDI enabled */
1227 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1228 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1229 }
1230 /* FIXME: assert CPU port conditions for SNB+ */
1231 }
b24e7179
JB		 1232
1233 reg = PIPECONF(pipe);
1234 val = I915_READ(reg);
00d70b15
CW		 1235 if (val & PIPECONF_ENABLE)
1236 return;
1237
1238 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1239 intel_wait_for_vblank(dev_priv->dev, pipe);
1240}
1241
1242/**
309cfea8 1243 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1244 * @dev_priv: i915 private structure
1245 * @pipe: pipe to disable
1246 *
1247 * Disable @pipe, making sure that various hardware specific requirements
1248 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1249 *
1250 * @pipe should be %PIPE_A or %PIPE_B.
1251 *
1252 * Will wait until the pipe has shut down before returning.
1253 */
1254static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256{
1257 int reg;
1258 u32 val;
1259
1260 /*
1261 * Make sure planes won't keep trying to pump pixels to us,
1262 * or we might hang the display.
1263 */
1264 assert_planes_disabled(dev_priv, pipe);
1265
1266 /* Don't disable pipe A or pipe A PLLs if needed */
1267 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1268 return;
1269
1270 reg = PIPECONF(pipe);
1271 val = I915_READ(reg);
00d70b15
CW		 1272 if ((val & PIPECONF_ENABLE) == 0)
1273 return;
1274
1275 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1276 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1277}
1278
1279/**
1280 * intel_enable_plane - enable a display plane on a given pipe
1281 * @dev_priv: i915 private structure
1282 * @plane: plane to enable
1283 * @pipe: pipe being fed
1284 *
1285 * Enable @plane on @pipe, making sure that @pipe is running first.
1286 */
1287static void intel_enable_plane(struct drm_i915_private *dev_priv,
1288 enum plane plane, enum pipe pipe)
1289{
1290 int reg;
1291 u32 val;
1292
1293 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1294 assert_pipe_enabled(dev_priv, pipe);
1295
1296 reg = DSPCNTR(plane);
1297 val = I915_READ(reg);
00d70b15
CW		 1298 if (val & DISPLAY_PLANE_ENABLE)
1299 return;
1300
1301 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1302 intel_wait_for_vblank(dev_priv->dev, pipe);
1303}
1304
1305/*
1306 * Plane regs are double buffered, going from enabled->disabled needs a
1307 * trigger in order to latch. The display address reg provides this.
1308 */
1309static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1310 enum plane plane)
1311{
1312 u32 reg = DSPADDR(plane);
1313 I915_WRITE(reg, I915_READ(reg));
1314}
1315
1316/**
1317 * intel_disable_plane - disable a display plane
1318 * @dev_priv: i915 private structure
1319 * @plane: plane to disable
1320 * @pipe: pipe consuming the data
1321 *
1322 * Disable @plane; should be an independent operation.
1323 */
1324static void intel_disable_plane(struct drm_i915_private *dev_priv,
1325 enum plane plane, enum pipe pipe)
1326{
1327 int reg;
1328 u32 val;
1329
1330 reg = DSPCNTR(plane);
1331 val = I915_READ(reg);
00d70b15
CW		 1332 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1333 return;
1334
1335 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1336 intel_flush_display_plane(dev_priv, plane);
1337 intel_wait_for_vblank(dev_priv->dev, pipe);
1338}
1339
47a05eca
JB		 1340static void disable_pch_dp(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, int reg)
1342{
1343 u32 val = I915_READ(reg);
1344 if (DP_PIPE_ENABLED(val, pipe))
1345 I915_WRITE(reg, val & ~DP_PORT_EN);
1346}
1347
1348static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1349 enum pipe pipe, int reg)
1350{
1351 u32 val = I915_READ(reg);
1352 if (HDMI_PIPE_ENABLED(val, pipe))
1353 I915_WRITE(reg, val & ~PORT_ENABLE);
1354}
1355
1356/* Disable any ports connected to this transcoder */
1357static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1358 enum pipe pipe)
1359{
1360 u32 reg, val;
1361
1362 val = I915_READ(PCH_PP_CONTROL);
1363 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1364
1365 disable_pch_dp(dev_priv, pipe, PCH_DP_B);
1366 disable_pch_dp(dev_priv, pipe, PCH_DP_C);
1367 disable_pch_dp(dev_priv, pipe, PCH_DP_D);
1368
1369 reg = PCH_ADPA;
1370 val = I915_READ(reg);
1371 if (ADPA_PIPE_ENABLED(val, pipe))
1372 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1373
1374 reg = PCH_LVDS;
1375 val = I915_READ(reg);
1376 if (LVDS_PIPE_ENABLED(val, pipe)) {
1377 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1378 POSTING_READ(reg);
1379 udelay(100);
1380 }
1381
1382 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1383 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1384 disable_pch_hdmi(dev_priv, pipe, HDMID);
1385}
1386
80824003
JB		 1387static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1388{
1389 struct drm_device *dev = crtc->dev;
1390 struct drm_i915_private *dev_priv = dev->dev_private;
1391 struct drm_framebuffer *fb = crtc->fb;
1392 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1393 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003
JB		 1394 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1395 int plane, i;
1396 u32 fbc_ctl, fbc_ctl2;
1397
bed4a673 1398 if (fb->pitch == dev_priv->cfb_pitch &&
05394f39 1399 obj->fence_reg == dev_priv->cfb_fence &&
bed4a673
CW		 1400 intel_crtc->plane == dev_priv->cfb_plane &&
1401 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1402 return;
1403
1404 i8xx_disable_fbc(dev);
1405
80824003
JB		 1406 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1407
1408 if (fb->pitch < dev_priv->cfb_pitch)
1409 dev_priv->cfb_pitch = fb->pitch;
1410
1411 /* FBC_CTL wants 64B units */
1412 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1413 dev_priv->cfb_fence = obj->fence_reg;
80824003
JB		 1414 dev_priv->cfb_plane = intel_crtc->plane;
1415 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1416
1417 /* Clear old tags */
1418 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1419 I915_WRITE(FBC_TAG + (i * 4), 0);
1420
1421 /* Set it up... */
1422 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
05394f39 1423 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1424 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1425 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1426 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1427
1428 /* enable it... */
1429 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1430 if (IS_I945GM(dev))
49677901 1431 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
80824003
JB		 1432 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1433 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
05394f39 1434 if (obj->tiling_mode != I915_TILING_NONE)
80824003
JB		 1435 fbc_ctl |= dev_priv->cfb_fence;
1436 I915_WRITE(FBC_CONTROL, fbc_ctl);
1437
28c97730 1438 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
5eddb70b 1439 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
80824003
JB		 1440}
1441
1442void i8xx_disable_fbc(struct drm_device *dev)
1443{
1444 struct drm_i915_private *dev_priv = dev->dev_private;
1445 u32 fbc_ctl;
1446
1447 /* Disable compression */
1448 fbc_ctl = I915_READ(FBC_CONTROL);
a5cad620
CW		 1449 if ((fbc_ctl & FBC_CTL_EN) == 0)
1450 return;
1451
80824003
JB		 1452 fbc_ctl &= ~FBC_CTL_EN;
1453 I915_WRITE(FBC_CONTROL, fbc_ctl);
1454
1455 /* Wait for compressing bit to clear */
481b6af3 1456 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
913d8d11
CW		 1457 DRM_DEBUG_KMS("FBC idle timed out\n");
1458 return;
9517a92f 1459 }
80824003 1460
28c97730 1461 DRM_DEBUG_KMS("disabled FBC\n");
80824003
JB		 1462}
1463
ee5382ae 1464static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1465{
80824003
JB		 1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467
1468 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1469}
1470
74dff282
JB		 1471static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1472{
1473 struct drm_device *dev = crtc->dev;
1474 struct drm_i915_private *dev_priv = dev->dev_private;
1475 struct drm_framebuffer *fb = crtc->fb;
1476 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1477 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1479 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1480 unsigned long stall_watermark = 200;
1481 u32 dpfc_ctl;
1482
bed4a673
CW		 1483 dpfc_ctl = I915_READ(DPFC_CONTROL);
1484 if (dpfc_ctl & DPFC_CTL_EN) {
1485 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1486 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673
CW		 1487 dev_priv->cfb_plane == intel_crtc->plane &&
1488 dev_priv->cfb_y == crtc->y)
1489 return;
1490
1491 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1492 intel_wait_for_vblank(dev, intel_crtc->pipe);
1493 }
1494
74dff282 1495 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1496 dev_priv->cfb_fence = obj->fence_reg;
74dff282 1497 dev_priv->cfb_plane = intel_crtc->plane;
bed4a673 1498 dev_priv->cfb_y = crtc->y;
74dff282
JB		 1499
1500 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
05394f39 1501 if (obj->tiling_mode != I915_TILING_NONE) {
74dff282
JB		 1502 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1503 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1504 } else {
1505 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1506 }
1507
74dff282
JB		 1508 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1509 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1510 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1511 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1512
1513 /* enable it... */
1514 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1515
28c97730 1516 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1517}
1518
1519void g4x_disable_fbc(struct drm_device *dev)
1520{
1521 struct drm_i915_private *dev_priv = dev->dev_private;
1522 u32 dpfc_ctl;
1523
1524 /* Disable compression */
1525 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1526 if (dpfc_ctl & DPFC_CTL_EN) {
1527 dpfc_ctl &= ~DPFC_CTL_EN;
1528 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1529
bed4a673
CW		 1530 DRM_DEBUG_KMS("disabled FBC\n");
1531 }
74dff282
JB		 1532}
1533
ee5382ae 1534static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1535{
74dff282
JB		 1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1539}
1540
4efe0708
JB		 1541static void sandybridge_blit_fbc_update(struct drm_device *dev)
1542{
1543 struct drm_i915_private *dev_priv = dev->dev_private;
1544 u32 blt_ecoskpd;
1545
1546 /* Make sure blitter notifies FBC of writes */
fcca7926 1547 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1548 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1549 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1550 GEN6_BLITTER_LOCK_SHIFT;
1551 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1552 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1553 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1554 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1555 GEN6_BLITTER_LOCK_SHIFT);
1556 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1557 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1558 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1559}
1560
b52eb4dc
ZY		 1561static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1562{
1563 struct drm_device *dev = crtc->dev;
1564 struct drm_i915_private *dev_priv = dev->dev_private;
1565 struct drm_framebuffer *fb = crtc->fb;
1566 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1567 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1569 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1570 unsigned long stall_watermark = 200;
1571 u32 dpfc_ctl;
1572
bed4a673
CW		 1573 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1574 if (dpfc_ctl & DPFC_CTL_EN) {
1575 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
05394f39 1576 dev_priv->cfb_fence == obj->fence_reg &&
bed4a673 1577 dev_priv->cfb_plane == intel_crtc->plane &&
05394f39 1578 dev_priv->cfb_offset == obj->gtt_offset &&
bed4a673
CW		 1579 dev_priv->cfb_y == crtc->y)
1580 return;
1581
1582 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
bed4a673
CW		 1583 intel_wait_for_vblank(dev, intel_crtc->pipe);
1584 }
1585
b52eb4dc 1586 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
05394f39 1587 dev_priv->cfb_fence = obj->fence_reg;
b52eb4dc 1588 dev_priv->cfb_plane = intel_crtc->plane;
05394f39 1589 dev_priv->cfb_offset = obj->gtt_offset;
bed4a673 1590 dev_priv->cfb_y = crtc->y;
b52eb4dc 1591
b52eb4dc
ZY		 1592 dpfc_ctl &= DPFC_RESERVED;
1593 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
05394f39 1594 if (obj->tiling_mode != I915_TILING_NONE) {
b52eb4dc
ZY		 1595 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1596 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1597 } else {
1598 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1599 }
1600
b52eb4dc
ZY		 1601 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1602 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1603 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1604 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1605 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1606 /* enable it... */
bed4a673 1607 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1608
9c04f015
YL		 1609 if (IS_GEN6(dev)) {
1610 I915_WRITE(SNB_DPFC_CTL_SA,
1611 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1612 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1613 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1614 }
1615
b52eb4dc
ZY		 1616 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1617}
1618
1619void ironlake_disable_fbc(struct drm_device *dev)
1620{
1621 struct drm_i915_private *dev_priv = dev->dev_private;
1622 u32 dpfc_ctl;
1623
1624 /* Disable compression */
1625 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1626 if (dpfc_ctl & DPFC_CTL_EN) {
1627 dpfc_ctl &= ~DPFC_CTL_EN;
1628 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1629
bed4a673
CW		 1630 DRM_DEBUG_KMS("disabled FBC\n");
1631 }
b52eb4dc
ZY		 1632}
1633
1634static bool ironlake_fbc_enabled(struct drm_device *dev)
1635{
1636 struct drm_i915_private *dev_priv = dev->dev_private;
1637
1638 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1639}
1640
ee5382ae
AJ		 1641bool intel_fbc_enabled(struct drm_device *dev)
1642{
1643 struct drm_i915_private *dev_priv = dev->dev_private;
1644
1645 if (!dev_priv->display.fbc_enabled)
1646 return false;
1647
1648 return dev_priv->display.fbc_enabled(dev);
1649}
1650
1651void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1652{
1653 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1654
1655 if (!dev_priv->display.enable_fbc)
1656 return;
1657
1658 dev_priv->display.enable_fbc(crtc, interval);
1659}
1660
1661void intel_disable_fbc(struct drm_device *dev)
1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664
1665 if (!dev_priv->display.disable_fbc)
1666 return;
1667
1668 dev_priv->display.disable_fbc(dev);
1669}
1670
80824003
JB		 1671/**
1672 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1673 * @dev: the drm_device
80824003
JB		 1674 *
1675 * Set up the framebuffer compression hardware at mode set time. We
1676 * enable it if possible:
1677 * - plane A only (on pre-965)
1678 * - no pixel mulitply/line duplication
1679 * - no alpha buffer discard
1680 * - no dual wide
1681 * - framebuffer <= 2048 in width, 1536 in height
1682 *
1683 * We can't assume that any compression will take place (worst case),
1684 * so the compressed buffer has to be the same size as the uncompressed
1685 * one. It also must reside (along with the line length buffer) in
1686 * stolen memory.
1687 *
1688 * We need to enable/disable FBC on a global basis.
1689 */
bed4a673 1690static void intel_update_fbc(struct drm_device *dev)
80824003 1691{
80824003 1692 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1693 struct drm_crtc *crtc = NULL, *tmp_crtc;
1694 struct intel_crtc *intel_crtc;
1695 struct drm_framebuffer *fb;
80824003 1696 struct intel_framebuffer *intel_fb;
05394f39 1697 struct drm_i915_gem_object *obj;
9c928d16
JB		 1698
1699 DRM_DEBUG_KMS("\n");
80824003
JB		 1700
1701 if (!i915_powersave)
1702 return;
1703
ee5382ae 1704 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1705 return;
1706
80824003
JB		 1707 /*
1708 * If FBC is already on, we just have to verify that we can
1709 * keep it that way...
1710 * Need to disable if:
9c928d16 1711 * - more than one pipe is active
80824003
JB		 1712 * - changing FBC params (stride, fence, mode)
1713 * - new fb is too large to fit in compressed buffer
1714 * - going to an unsupported config (interlace, pixel multiply, etc.)
1715 */
9c928d16 1716 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1717 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1718 if (crtc) {
1719 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1720 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1721 goto out_disable;
1722 }
1723 crtc = tmp_crtc;
1724 }
9c928d16 1725 }
bed4a673
CW		 1726
1727 if (!crtc || crtc->fb == NULL) {
1728 DRM_DEBUG_KMS("no output, disabling\n");
1729 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1730 goto out_disable;
1731 }
bed4a673
CW		 1732
1733 intel_crtc = to_intel_crtc(crtc);
1734 fb = crtc->fb;
1735 intel_fb = to_intel_framebuffer(fb);
05394f39 1736 obj = intel_fb->obj;
bed4a673 1737
c1a9f047
JB		 1738 if (!i915_enable_fbc) {
1739 DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
1740 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1741 goto out_disable;
1742 }
05394f39 1743 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1744 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1745 "compression\n");
b5e50c3f 1746 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1747 goto out_disable;
1748 }
bed4a673
CW		 1749 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1750 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1751 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1752 "disabling\n");
b5e50c3f 1753 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1754 goto out_disable;
1755 }
bed4a673
CW		 1756 if ((crtc->mode.hdisplay > 2048) ||
1757 (crtc->mode.vdisplay > 1536)) {
28c97730 1758 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1759 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1760 goto out_disable;
1761 }
bed4a673 1762 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1763 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1764 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1765 goto out_disable;
1766 }
05394f39 1767 if (obj->tiling_mode != I915_TILING_X) {
28c97730 1768 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
b5e50c3f 1769 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1770 goto out_disable;
1771 }
1772
c924b934
JW		 1773 /* If the kernel debugger is active, always disable compression */
1774 if (in_dbg_master())
1775 goto out_disable;
1776
bed4a673 1777 intel_enable_fbc(crtc, 500);
80824003
JB		 1778 return;
1779
1780out_disable:
80824003 1781 /* Multiple disables should be harmless */
a939406f
CW		 1782 if (intel_fbc_enabled(dev)) {
1783 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1784 intel_disable_fbc(dev);
a939406f 1785 }
80824003
JB		 1786}
1787
127bd2ac 1788int
48b956c5 1789intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1790 struct drm_i915_gem_object *obj,
919926ae 1791 struct intel_ring_buffer *pipelined)
6b95a207 1792{
ce453d81 1793 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1794 u32 alignment;
1795 int ret;
1796
05394f39 1797 switch (obj->tiling_mode) {
6b95a207 1798 case I915_TILING_NONE:
534843da
CW		 1799 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1800 alignment = 128 * 1024;
a6c45cf0 1801 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1802 alignment = 4 * 1024;
1803 else
1804 alignment = 64 * 1024;
6b95a207
KH		 1805 break;
1806 case I915_TILING_X:
1807 /* pin() will align the object as required by fence */
1808 alignment = 0;
1809 break;
1810 case I915_TILING_Y:
1811 /* FIXME: Is this true? */
1812 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1813 return -EINVAL;
1814 default:
1815 BUG();
1816 }
1817
ce453d81 1818 dev_priv->mm.interruptible = false;
2da3b9b9 1819 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1820 if (ret)
ce453d81 1821 goto err_interruptible;
6b95a207
KH		 1822
1823 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1824 * fence, whereas 965+ only requires a fence if using
1825 * framebuffer compression. For simplicity, we always install
1826 * a fence as the cost is not that onerous.
1827 */
05394f39 1828 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 1829 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 1830 if (ret)
1831 goto err_unpin;
6b95a207
KH		 1832 }
1833
ce453d81 1834 dev_priv->mm.interruptible = true;
6b95a207 1835 return 0;
48b956c5
CW		 1836
1837err_unpin:
1838 i915_gem_object_unpin(obj);
ce453d81
CW		 1839err_interruptible:
1840 dev_priv->mm.interruptible = true;
48b956c5 1841 return ret;
6b95a207
KH		 1842}
1843
81255565
JB		 1844/* Assume fb object is pinned & idle & fenced and just update base pointers */
1845static int
1846intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
21c74a8e 1847 int x, int y, enum mode_set_atomic state)
81255565
JB		 1848{
1849 struct drm_device *dev = crtc->dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
1851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1852 struct intel_framebuffer *intel_fb;
05394f39 1853 struct drm_i915_gem_object *obj;
81255565
JB		 1854 int plane = intel_crtc->plane;
1855 unsigned long Start, Offset;
81255565 1856 u32 dspcntr;
5eddb70b 1857 u32 reg;
81255565
JB		 1858
1859 switch (plane) {
1860 case 0:
1861 case 1:
1862 break;
1863 default:
1864 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1865 return -EINVAL;
1866 }
1867
1868 intel_fb = to_intel_framebuffer(fb);
1869 obj = intel_fb->obj;
81255565 1870
5eddb70b
CW		 1871 reg = DSPCNTR(plane);
1872 dspcntr = I915_READ(reg);
81255565
JB		 1873 /* Mask out pixel format bits in case we change it */
1874 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1875 switch (fb->bits_per_pixel) {
1876 case 8:
1877 dspcntr |= DISPPLANE_8BPP;
1878 break;
1879 case 16:
1880 if (fb->depth == 15)
1881 dspcntr |= DISPPLANE_15_16BPP;
1882 else
1883 dspcntr |= DISPPLANE_16BPP;
1884 break;
1885 case 24:
1886 case 32:
1887 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1888 break;
1889 default:
1890 DRM_ERROR("Unknown color depth\n");
1891 return -EINVAL;
1892 }
a6c45cf0 1893 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1894 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1895 dspcntr |= DISPPLANE_TILED;
1896 else
1897 dspcntr &= ~DISPPLANE_TILED;
1898 }
1899
4e6cfefc 1900 if (HAS_PCH_SPLIT(dev))
81255565
JB		 1901 /* must disable */
1902 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1903
5eddb70b 1904 I915_WRITE(reg, dspcntr);
81255565 1905
05394f39 1906 Start = obj->gtt_offset;
81255565
JB		 1907 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1908
4e6cfefc
CW		 1909 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1910 Start, Offset, x, y, fb->pitch);
5eddb70b 1911 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 1912 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 1913 I915_WRITE(DSPSURF(plane), Start);
1914 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1915 I915_WRITE(DSPADDR(plane), Offset);
1916 } else
1917 I915_WRITE(DSPADDR(plane), Start + Offset);
1918 POSTING_READ(reg);
81255565 1919
bed4a673 1920 intel_update_fbc(dev);
3dec0095 1921 intel_increase_pllclock(crtc);
81255565
JB		 1922
1923 return 0;
1924}
1925
5c3b82e2 1926static int
3c4fdcfb
KH		 1927intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1928 struct drm_framebuffer *old_fb)
79e53945
JB		 1929{
1930 struct drm_device *dev = crtc->dev;
79e53945
JB		 1931 struct drm_i915_master_private *master_priv;
1932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 1933 int ret;
79e53945
JB		 1934
1935 /* no fb bound */
1936 if (!crtc->fb) {
28c97730 1937 DRM_DEBUG_KMS("No FB bound\n");
5c3b82e2
CW		 1938 return 0;
1939 }
1940
265db958 1941 switch (intel_crtc->plane) {
5c3b82e2
CW		 1942 case 0:
1943 case 1:
1944 break;
1945 default:
5c3b82e2 1946 return -EINVAL;
79e53945
JB		 1947 }
1948
5c3b82e2 1949 mutex_lock(&dev->struct_mutex);
265db958
CW		 1950 ret = intel_pin_and_fence_fb_obj(dev,
1951 to_intel_framebuffer(crtc->fb)->obj,
919926ae 1952 NULL);
5c3b82e2
CW		 1953 if (ret != 0) {
1954 mutex_unlock(&dev->struct_mutex);
1955 return ret;
1956 }
79e53945 1957
265db958 1958 if (old_fb) {
e6c3a2a6 1959 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1960 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 1961
e6c3a2a6 1962 wait_event(dev_priv->pending_flip_queue,
01eec727 1963 atomic_read(&dev_priv->mm.wedged) ||
05394f39 1964 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 1965
1966 /* Big Hammer, we also need to ensure that any pending
1967 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1968 * current scanout is retired before unpinning the old
1969 * framebuffer.
01eec727
CW		 1970 *
1971 * This should only fail upon a hung GPU, in which case we
1972 * can safely continue.
85345517 1973 */
a8198eea 1974 ret = i915_gem_object_finish_gpu(obj);
01eec727 1975 (void) ret;
265db958
CW		 1976 }
1977
21c74a8e
JW		 1978 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1979 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 1980 if (ret) {
265db958 1981 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 1982 mutex_unlock(&dev->struct_mutex);
4e6cfefc 1983 return ret;
79e53945 1984 }
3c4fdcfb 1985
b7f1de28
CW		 1986 if (old_fb) {
1987 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 1988 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 1989 }
652c393a 1990
5c3b82e2 1991 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 1992
1993 if (!dev->primary->master)
5c3b82e2 1994 return 0;
79e53945
JB		 1995
1996 master_priv = dev->primary->master->driver_priv;
1997 if (!master_priv->sarea_priv)
5c3b82e2 1998 return 0;
79e53945 1999
265db958 2000 if (intel_crtc->pipe) {
79e53945
JB		 2001 master_priv->sarea_priv->pipeB_x = x;
2002 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2003 } else {
2004 master_priv->sarea_priv->pipeA_x = x;
2005 master_priv->sarea_priv->pipeA_y = y;
79e53945 2006 }
5c3b82e2
CW		 2007
2008 return 0;
79e53945
JB		 2009}
2010
5eddb70b 2011static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2012{
2013 struct drm_device *dev = crtc->dev;
2014 struct drm_i915_private *dev_priv = dev->dev_private;
2015 u32 dpa_ctl;
2016
28c97730 2017 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2018 dpa_ctl = I915_READ(DP_A);
2019 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2020
2021 if (clock < 200000) {
2022 u32 temp;
2023 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2024 /* workaround for 160Mhz:
2025 1) program 0x4600c bits 15:0 = 0x8124
2026 2) program 0x46010 bit 0 = 1
2027 3) program 0x46034 bit 24 = 1
2028 4) program 0x64000 bit 14 = 1
2029 */
2030 temp = I915_READ(0x4600c);
2031 temp &= 0xffff0000;
2032 I915_WRITE(0x4600c, temp | 0x8124);
2033
2034 temp = I915_READ(0x46010);
2035 I915_WRITE(0x46010, temp | 1);
2036
2037 temp = I915_READ(0x46034);
2038 I915_WRITE(0x46034, temp | (1 << 24));
2039 } else {
2040 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2041 }
2042 I915_WRITE(DP_A, dpa_ctl);
2043
5eddb70b 2044 POSTING_READ(DP_A);
32f9d658
ZW		 2045 udelay(500);
2046}
2047
5e84e1a4
ZW		 2048static void intel_fdi_normal_train(struct drm_crtc *crtc)
2049{
2050 struct drm_device *dev = crtc->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053 int pipe = intel_crtc->pipe;
2054 u32 reg, temp;
2055
2056 /* enable normal train */
2057 reg = FDI_TX_CTL(pipe);
2058 temp = I915_READ(reg);
61e499bf 2059 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2060 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2061 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2062 } else {
2063 temp &= ~FDI_LINK_TRAIN_NONE;
2064 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2065 }
5e84e1a4
ZW		 2066 I915_WRITE(reg, temp);
2067
2068 reg = FDI_RX_CTL(pipe);
2069 temp = I915_READ(reg);
2070 if (HAS_PCH_CPT(dev)) {
2071 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2072 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2073 } else {
2074 temp &= ~FDI_LINK_TRAIN_NONE;
2075 temp |= FDI_LINK_TRAIN_NONE;
2076 }
2077 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2078
2079 /* wait one idle pattern time */
2080 POSTING_READ(reg);
2081 udelay(1000);
357555c0
JB		 2082
2083 /* IVB wants error correction enabled */
2084 if (IS_IVYBRIDGE(dev))
2085 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2086 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2087}
2088
8db9d77b
ZW		 2089/* The FDI link training functions for ILK/Ibexpeak. */
2090static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2091{
2092 struct drm_device *dev = crtc->dev;
2093 struct drm_i915_private *dev_priv = dev->dev_private;
2094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2095 int pipe = intel_crtc->pipe;
0fc932b8 2096 int plane = intel_crtc->plane;
5eddb70b 2097 u32 reg, temp, tries;
8db9d77b 2098
0fc932b8
JB		 2099 /* FDI needs bits from pipe & plane first */
2100 assert_pipe_enabled(dev_priv, pipe);
2101 assert_plane_enabled(dev_priv, plane);
2102
e1a44743
AJ		 2103 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2104 for train result */
5eddb70b
CW		 2105 reg = FDI_RX_IMR(pipe);
2106 temp = I915_READ(reg);
e1a44743
AJ		 2107 temp &= ~FDI_RX_SYMBOL_LOCK;
2108 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2109 I915_WRITE(reg, temp);
2110 I915_READ(reg);
e1a44743
AJ		 2111 udelay(150);
2112
8db9d77b 2113 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2114 reg = FDI_TX_CTL(pipe);
2115 temp = I915_READ(reg);
77ffb597
AJ		 2116 temp &= ~(7 << 19);
2117 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2118 temp &= ~FDI_LINK_TRAIN_NONE;
2119 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2120 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2121
5eddb70b
CW		 2122 reg = FDI_RX_CTL(pipe);
2123 temp = I915_READ(reg);
8db9d77b
ZW		 2124 temp &= ~FDI_LINK_TRAIN_NONE;
2125 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2126 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2127
2128 POSTING_READ(reg);
8db9d77b
ZW		 2129 udelay(150);
2130
5b2adf89 2131 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2132 if (HAS_PCH_IBX(dev)) {
2133 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2134 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2135 FDI_RX_PHASE_SYNC_POINTER_EN);
2136 }
5b2adf89 2137
5eddb70b 2138 reg = FDI_RX_IIR(pipe);
e1a44743 2139 for (tries = 0; tries < 5; tries++) {
5eddb70b 2140 temp = I915_READ(reg);
8db9d77b
ZW		 2141 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2142
2143 if ((temp & FDI_RX_BIT_LOCK)) {
2144 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2145 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2146 break;
2147 }
8db9d77b 2148 }
e1a44743 2149 if (tries == 5)
5eddb70b 2150 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2151
2152 /* Train 2 */
5eddb70b
CW		 2153 reg = FDI_TX_CTL(pipe);
2154 temp = I915_READ(reg);
8db9d77b
ZW		 2155 temp &= ~FDI_LINK_TRAIN_NONE;
2156 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2157 I915_WRITE(reg, temp);
8db9d77b 2158
5eddb70b
CW		 2159 reg = FDI_RX_CTL(pipe);
2160 temp = I915_READ(reg);
8db9d77b
ZW		 2161 temp &= ~FDI_LINK_TRAIN_NONE;
2162 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2163 I915_WRITE(reg, temp);
8db9d77b 2164
5eddb70b
CW		 2165 POSTING_READ(reg);
2166 udelay(150);
8db9d77b 2167
5eddb70b 2168 reg = FDI_RX_IIR(pipe);
e1a44743 2169 for (tries = 0; tries < 5; tries++) {
5eddb70b 2170 temp = I915_READ(reg);
8db9d77b
ZW		 2171 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2172
2173 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2174 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2175 DRM_DEBUG_KMS("FDI train 2 done.\n");
2176 break;
2177 }
8db9d77b 2178 }
e1a44743 2179 if (tries == 5)
5eddb70b 2180 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2181
2182 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2183
8db9d77b
ZW		 2184}
2185
311bd68e 2186static const int snb_b_fdi_train_param [] = {
8db9d77b
ZW		 2187 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2188 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2189 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2190 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2191};
2192
2193/* The FDI link training functions for SNB/Cougarpoint. */
2194static void gen6_fdi_link_train(struct drm_crtc *crtc)
2195{
2196 struct drm_device *dev = crtc->dev;
2197 struct drm_i915_private *dev_priv = dev->dev_private;
2198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2199 int pipe = intel_crtc->pipe;
5eddb70b 2200 u32 reg, temp, i;
8db9d77b 2201
e1a44743
AJ		 2202 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2203 for train result */
5eddb70b
CW		 2204 reg = FDI_RX_IMR(pipe);
2205 temp = I915_READ(reg);
e1a44743
AJ		 2206 temp &= ~FDI_RX_SYMBOL_LOCK;
2207 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2208 I915_WRITE(reg, temp);
2209
2210 POSTING_READ(reg);
e1a44743
AJ		 2211 udelay(150);
2212
8db9d77b 2213 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2214 reg = FDI_TX_CTL(pipe);
2215 temp = I915_READ(reg);
77ffb597
AJ		 2216 temp &= ~(7 << 19);
2217 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2218 temp &= ~FDI_LINK_TRAIN_NONE;
2219 temp |= FDI_LINK_TRAIN_PATTERN_1;
2220 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2221 /* SNB-B */
2222 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2223 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2224
5eddb70b
CW		 2225 reg = FDI_RX_CTL(pipe);
2226 temp = I915_READ(reg);
8db9d77b
ZW		 2227 if (HAS_PCH_CPT(dev)) {
2228 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2229 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2230 } else {
2231 temp &= ~FDI_LINK_TRAIN_NONE;
2232 temp |= FDI_LINK_TRAIN_PATTERN_1;
2233 }
5eddb70b
CW		 2234 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2235
2236 POSTING_READ(reg);
8db9d77b
ZW		 2237 udelay(150);
2238
8db9d77b 2239 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
8db9d77b
ZW		 2242 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2243 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2244 I915_WRITE(reg, temp);
2245
2246 POSTING_READ(reg);
8db9d77b
ZW		 2247 udelay(500);
2248
5eddb70b
CW		 2249 reg = FDI_RX_IIR(pipe);
2250 temp = I915_READ(reg);
8db9d77b
ZW		 2251 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2252
2253 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2254 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2255 DRM_DEBUG_KMS("FDI train 1 done.\n");
2256 break;
2257 }
2258 }
2259 if (i == 4)
5eddb70b 2260 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2261
2262 /* Train 2 */
5eddb70b
CW		 2263 reg = FDI_TX_CTL(pipe);
2264 temp = I915_READ(reg);
8db9d77b
ZW		 2265 temp &= ~FDI_LINK_TRAIN_NONE;
2266 temp |= FDI_LINK_TRAIN_PATTERN_2;
2267 if (IS_GEN6(dev)) {
2268 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2269 /* SNB-B */
2270 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2271 }
5eddb70b 2272 I915_WRITE(reg, temp);
8db9d77b 2273
5eddb70b
CW		 2274 reg = FDI_RX_CTL(pipe);
2275 temp = I915_READ(reg);
8db9d77b
ZW		 2276 if (HAS_PCH_CPT(dev)) {
2277 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2278 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2279 } else {
2280 temp &= ~FDI_LINK_TRAIN_NONE;
2281 temp |= FDI_LINK_TRAIN_PATTERN_2;
2282 }
5eddb70b
CW		 2283 I915_WRITE(reg, temp);
2284
2285 POSTING_READ(reg);
8db9d77b
ZW		 2286 udelay(150);
2287
2288 for (i = 0; i < 4; i++ ) {
5eddb70b
CW		 2289 reg = FDI_TX_CTL(pipe);
2290 temp = I915_READ(reg);
8db9d77b
ZW		 2291 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2292 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2293 I915_WRITE(reg, temp);
2294
2295 POSTING_READ(reg);
8db9d77b
ZW		 2296 udelay(500);
2297
5eddb70b
CW		 2298 reg = FDI_RX_IIR(pipe);
2299 temp = I915_READ(reg);
8db9d77b
ZW		 2300 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2301
2302 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2303 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2304 DRM_DEBUG_KMS("FDI train 2 done.\n");
2305 break;
2306 }
2307 }
2308 if (i == 4)
5eddb70b 2309 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2310
2311 DRM_DEBUG_KMS("FDI train done.\n");
2312}
2313
357555c0
JB		 2314/* Manual link training for Ivy Bridge A0 parts */
2315static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2316{
2317 struct drm_device *dev = crtc->dev;
2318 struct drm_i915_private *dev_priv = dev->dev_private;
2319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2320 int pipe = intel_crtc->pipe;
2321 u32 reg, temp, i;
2322
2323 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2324 for train result */
2325 reg = FDI_RX_IMR(pipe);
2326 temp = I915_READ(reg);
2327 temp &= ~FDI_RX_SYMBOL_LOCK;
2328 temp &= ~FDI_RX_BIT_LOCK;
2329 I915_WRITE(reg, temp);
2330
2331 POSTING_READ(reg);
2332 udelay(150);
2333
2334 /* enable CPU FDI TX and PCH FDI RX */
2335 reg = FDI_TX_CTL(pipe);
2336 temp = I915_READ(reg);
2337 temp &= ~(7 << 19);
2338 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2339 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2340 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2341 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2342 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2343 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2344
2345 reg = FDI_RX_CTL(pipe);
2346 temp = I915_READ(reg);
2347 temp &= ~FDI_LINK_TRAIN_AUTO;
2348 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2349 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2350 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2351
2352 POSTING_READ(reg);
2353 udelay(150);
2354
2355 for (i = 0; i < 4; i++ ) {
2356 reg = FDI_TX_CTL(pipe);
2357 temp = I915_READ(reg);
2358 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2359 temp |= snb_b_fdi_train_param[i];
2360 I915_WRITE(reg, temp);
2361
2362 POSTING_READ(reg);
2363 udelay(500);
2364
2365 reg = FDI_RX_IIR(pipe);
2366 temp = I915_READ(reg);
2367 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2368
2369 if (temp & FDI_RX_BIT_LOCK ||
2370 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2371 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2372 DRM_DEBUG_KMS("FDI train 1 done.\n");
2373 break;
2374 }
2375 }
2376 if (i == 4)
2377 DRM_ERROR("FDI train 1 fail!\n");
2378
2379 /* Train 2 */
2380 reg = FDI_TX_CTL(pipe);
2381 temp = I915_READ(reg);
2382 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2383 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2384 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2385 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2386 I915_WRITE(reg, temp);
2387
2388 reg = FDI_RX_CTL(pipe);
2389 temp = I915_READ(reg);
2390 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2391 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2392 I915_WRITE(reg, temp);
2393
2394 POSTING_READ(reg);
2395 udelay(150);
2396
2397 for (i = 0; i < 4; i++ ) {
2398 reg = FDI_TX_CTL(pipe);
2399 temp = I915_READ(reg);
2400 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2401 temp |= snb_b_fdi_train_param[i];
2402 I915_WRITE(reg, temp);
2403
2404 POSTING_READ(reg);
2405 udelay(500);
2406
2407 reg = FDI_RX_IIR(pipe);
2408 temp = I915_READ(reg);
2409 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2410
2411 if (temp & FDI_RX_SYMBOL_LOCK) {
2412 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2413 DRM_DEBUG_KMS("FDI train 2 done.\n");
2414 break;
2415 }
2416 }
2417 if (i == 4)
2418 DRM_ERROR("FDI train 2 fail!\n");
2419
2420 DRM_DEBUG_KMS("FDI train done.\n");
2421}
2422
2423static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2424{
2425 struct drm_device *dev = crtc->dev;
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2428 int pipe = intel_crtc->pipe;
5eddb70b 2429 u32 reg, temp;
79e53945 2430
c64e311e 2431 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2432 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2433 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2434
c98e9dcf 2435 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
2438 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2439 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2440 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2441 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2442
2443 POSTING_READ(reg);
c98e9dcf
JB		 2444 udelay(200);
2445
2446 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2447 temp = I915_READ(reg);
2448 I915_WRITE(reg, temp | FDI_PCDCLK);
2449
2450 POSTING_READ(reg);
c98e9dcf
JB		 2451 udelay(200);
2452
2453 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2454 reg = FDI_TX_CTL(pipe);
2455 temp = I915_READ(reg);
c98e9dcf 2456 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2457 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2458
2459 POSTING_READ(reg);
c98e9dcf 2460 udelay(100);
6be4a607 2461 }
0e23b99d
JB		 2462}
2463
0fc932b8
JB		 2464static void ironlake_fdi_disable(struct drm_crtc *crtc)
2465{
2466 struct drm_device *dev = crtc->dev;
2467 struct drm_i915_private *dev_priv = dev->dev_private;
2468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2469 int pipe = intel_crtc->pipe;
2470 u32 reg, temp;
2471
2472 /* disable CPU FDI tx and PCH FDI rx */
2473 reg = FDI_TX_CTL(pipe);
2474 temp = I915_READ(reg);
2475 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2476 POSTING_READ(reg);
2477
2478 reg = FDI_RX_CTL(pipe);
2479 temp = I915_READ(reg);
2480 temp &= ~(0x7 << 16);
2481 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2482 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2483
2484 POSTING_READ(reg);
2485 udelay(100);
2486
2487 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2488 if (HAS_PCH_IBX(dev)) {
2489 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2490 I915_WRITE(FDI_RX_CHICKEN(pipe),
2491 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18
JB		 2492 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2493 }
0fc932b8
JB		 2494
2495 /* still set train pattern 1 */
2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
2498 temp &= ~FDI_LINK_TRAIN_NONE;
2499 temp |= FDI_LINK_TRAIN_PATTERN_1;
2500 I915_WRITE(reg, temp);
2501
2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507 } else {
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 }
2511 /* BPC in FDI rx is consistent with that in PIPECONF */
2512 temp &= ~(0x07 << 16);
2513 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2514 I915_WRITE(reg, temp);
2515
2516 POSTING_READ(reg);
2517 udelay(100);
2518}
2519
6b383a7f
CW		 2520/*
2521 * When we disable a pipe, we need to clear any pending scanline wait events
2522 * to avoid hanging the ring, which we assume we are waiting on.
2523 */
2524static void intel_clear_scanline_wait(struct drm_device *dev)
2525{
2526 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2527 struct intel_ring_buffer *ring;
6b383a7f
CW		 2528 u32 tmp;
2529
2530 if (IS_GEN2(dev))
2531 /* Can't break the hang on i8xx */
2532 return;
2533
1ec14ad3 2534 ring = LP_RING(dev_priv);
8168bd48
CW		 2535 tmp = I915_READ_CTL(ring);
2536 if (tmp & RING_WAIT)
2537 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2538}
2539
e6c3a2a6
CW		 2540static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2541{
05394f39 2542 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2543 struct drm_i915_private *dev_priv;
2544
2545 if (crtc->fb == NULL)
2546 return;
2547
05394f39 2548 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2549 dev_priv = crtc->dev->dev_private;
2550 wait_event(dev_priv->pending_flip_queue,
05394f39 2551 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2552}
2553
040484af
JB		 2554static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2555{
2556 struct drm_device *dev = crtc->dev;
2557 struct drm_mode_config *mode_config = &dev->mode_config;
2558 struct intel_encoder *encoder;
2559
2560 /*
2561 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2562 * must be driven by its own crtc; no sharing is possible.
2563 */
2564 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2565 if (encoder->base.crtc != crtc)
2566 continue;
2567
2568 switch (encoder->type) {
2569 case INTEL_OUTPUT_EDP:
2570 if (!intel_encoder_is_pch_edp(&encoder->base))
2571 return false;
2572 continue;
2573 }
2574 }
2575
2576 return true;
2577}
2578
f67a559d
JB		 2579/*
2580 * Enable PCH resources required for PCH ports:
2581 * - PCH PLLs
2582 * - FDI training & RX/TX
2583 * - update transcoder timings
2584 * - DP transcoding bits
2585 * - transcoder
2586 */
2587static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2588{
2589 struct drm_device *dev = crtc->dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2592 int pipe = intel_crtc->pipe;
5eddb70b 2593 u32 reg, temp;
2c07245f 2594
c98e9dcf 2595 /* For PCH output, training FDI link */
674cf967 2596 dev_priv->display.fdi_link_train(crtc);
2c07245f 2597
92f2584a 2598 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2599
c98e9dcf
JB		 2600 if (HAS_PCH_CPT(dev)) {
2601 /* Be sure PCH DPLL SEL is set */
2602 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2603 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2604 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2605 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf
JB		 2606 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2607 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2608 }
5eddb70b 2609
d9b6cb56
JB		 2610 /* set transcoder timing, panel must allow it */
2611 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2612 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2613 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2614 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2615
5eddb70b
CW		 2616 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2617 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2618 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2619
5e84e1a4
ZW		 2620 intel_fdi_normal_train(crtc);
2621
c98e9dcf
JB		 2622 /* For PCH DP, enable TRANS_DP_CTL */
2623 if (HAS_PCH_CPT(dev) &&
2624 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2625 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2626 reg = TRANS_DP_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2629 TRANS_DP_SYNC_MASK |
2630 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2631 temp |= (TRANS_DP_OUTPUT_ENABLE |
2632 TRANS_DP_ENH_FRAMING);
9325c9f0 2633 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2634
2635 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2636 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2637 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2638 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2639
2640 switch (intel_trans_dp_port_sel(crtc)) {
2641 case PCH_DP_B:
5eddb70b 2642 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2643 break;
2644 case PCH_DP_C:
5eddb70b 2645 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2646 break;
2647 case PCH_DP_D:
5eddb70b 2648 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2649 break;
2650 default:
2651 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2652 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2653 break;
32f9d658 2654 }
2c07245f 2655
5eddb70b 2656 I915_WRITE(reg, temp);
6be4a607 2657 }
b52eb4dc 2658
040484af 2659 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2660}
2661
2662static void ironlake_crtc_enable(struct drm_crtc *crtc)
2663{
2664 struct drm_device *dev = crtc->dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667 int pipe = intel_crtc->pipe;
2668 int plane = intel_crtc->plane;
2669 u32 temp;
2670 bool is_pch_port;
2671
2672 if (intel_crtc->active)
2673 return;
2674
2675 intel_crtc->active = true;
2676 intel_update_watermarks(dev);
2677
2678 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2679 temp = I915_READ(PCH_LVDS);
2680 if ((temp & LVDS_PORT_EN) == 0)
2681 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2682 }
2683
2684 is_pch_port = intel_crtc_driving_pch(crtc);
2685
2686 if (is_pch_port)
357555c0 2687 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2688 else
2689 ironlake_fdi_disable(crtc);
2690
2691 /* Enable panel fitting for LVDS */
2692 if (dev_priv->pch_pf_size &&
2693 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2694 /* Force use of hard-coded filter coefficients
2695 * as some pre-programmed values are broken,
2696 * e.g. x201.
2697 */
9db4a9c7
JB		 2698 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
2699 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
2700 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 2701 }
2702
2703 intel_enable_pipe(dev_priv, pipe, is_pch_port);
2704 intel_enable_plane(dev_priv, plane, pipe);
2705
2706 if (is_pch_port)
2707 ironlake_pch_enable(crtc);
c98e9dcf 2708
6be4a607 2709 intel_crtc_load_lut(crtc);
d1ebd816
BW		 2710
2711 mutex_lock(&dev->struct_mutex);
bed4a673 2712 intel_update_fbc(dev);
d1ebd816
BW		 2713 mutex_unlock(&dev->struct_mutex);
2714
6b383a7f 2715 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 2716}
2717
2718static void ironlake_crtc_disable(struct drm_crtc *crtc)
2719{
2720 struct drm_device *dev = crtc->dev;
2721 struct drm_i915_private *dev_priv = dev->dev_private;
2722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2723 int pipe = intel_crtc->pipe;
2724 int plane = intel_crtc->plane;
5eddb70b 2725 u32 reg, temp;
b52eb4dc 2726
f7abfe8b
CW		 2727 if (!intel_crtc->active)
2728 return;
2729
e6c3a2a6 2730 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 2731 drm_vblank_off(dev, pipe);
6b383a7f 2732 intel_crtc_update_cursor(crtc, false);
5eddb70b 2733
b24e7179 2734 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 2735
6be4a607
JB		 2736 if (dev_priv->cfb_plane == plane &&
2737 dev_priv->display.disable_fbc)
2738 dev_priv->display.disable_fbc(dev);
2c07245f 2739
b24e7179 2740 intel_disable_pipe(dev_priv, pipe);
32f9d658 2741
6be4a607 2742 /* Disable PF */
9db4a9c7
JB		 2743 I915_WRITE(PF_CTL(pipe), 0);
2744 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 2745
0fc932b8 2746 ironlake_fdi_disable(crtc);
2c07245f 2747
47a05eca
JB		 2748 /* This is a horrible layering violation; we should be doing this in
2749 * the connector/encoder ->prepare instead, but we don't always have
2750 * enough information there about the config to know whether it will
2751 * actually be necessary or just cause undesired flicker.
2752 */
2753 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 2754
040484af 2755 intel_disable_transcoder(dev_priv, pipe);
913d8d11 2756
6be4a607
JB		 2757 if (HAS_PCH_CPT(dev)) {
2758 /* disable TRANS_DP_CTL */
5eddb70b
CW		 2759 reg = TRANS_DP_CTL(pipe);
2760 temp = I915_READ(reg);
2761 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 2762 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 2763 I915_WRITE(reg, temp);
6be4a607
JB		 2764
2765 /* disable DPLL_SEL */
2766 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 2767 switch (pipe) {
2768 case 0:
2769 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2770 break;
2771 case 1:
6be4a607 2772 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 2773 break;
2774 case 2:
2775 /* FIXME: manage transcoder PLLs? */
2776 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
2777 break;
2778 default:
2779 BUG(); /* wtf */
2780 }
6be4a607 2781 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 2782 }
e3421a18 2783
6be4a607 2784 /* disable PCH DPLL */
92f2584a 2785 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 2786
6be4a607 2787 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 2788 reg = FDI_RX_CTL(pipe);
2789 temp = I915_READ(reg);
2790 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 2791
6be4a607 2792 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 2793 reg = FDI_TX_CTL(pipe);
2794 temp = I915_READ(reg);
2795 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2796
2797 POSTING_READ(reg);
6be4a607 2798 udelay(100);
8db9d77b 2799
5eddb70b
CW		 2800 reg = FDI_RX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 2803
6be4a607 2804 /* Wait for the clocks to turn off. */
5eddb70b 2805 POSTING_READ(reg);
6be4a607 2806 udelay(100);
6b383a7f 2807
f7abfe8b 2808 intel_crtc->active = false;
6b383a7f 2809 intel_update_watermarks(dev);
d1ebd816
BW		 2810
2811 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 2812 intel_update_fbc(dev);
2813 intel_clear_scanline_wait(dev);
d1ebd816 2814 mutex_unlock(&dev->struct_mutex);
6be4a607 2815}
1b3c7a47 2816
6be4a607
JB		 2817static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2818{
2819 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2820 int pipe = intel_crtc->pipe;
2821 int plane = intel_crtc->plane;
8db9d77b 2822
6be4a607
JB		 2823 /* XXX: When our outputs are all unaware of DPMS modes other than off
2824 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2825 */
2826 switch (mode) {
2827 case DRM_MODE_DPMS_ON:
2828 case DRM_MODE_DPMS_STANDBY:
2829 case DRM_MODE_DPMS_SUSPEND:
2830 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2831 ironlake_crtc_enable(crtc);
2832 break;
1b3c7a47 2833
6be4a607
JB		 2834 case DRM_MODE_DPMS_OFF:
2835 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2836 ironlake_crtc_disable(crtc);
2c07245f
ZW		 2837 break;
2838 }
2839}
2840
02e792fb
DV		 2841static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2842{
02e792fb 2843 if (!enable && intel_crtc->overlay) {
23f09ce3 2844 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 2845 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 2846
23f09ce3 2847 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 2848 dev_priv->mm.interruptible = false;
2849 (void) intel_overlay_switch_off(intel_crtc->overlay);
2850 dev_priv->mm.interruptible = true;
23f09ce3 2851 mutex_unlock(&dev->struct_mutex);
02e792fb 2852 }
02e792fb 2853
5dcdbcb0
CW		 2854 /* Let userspace switch the overlay on again. In most cases userspace
2855 * has to recompute where to put it anyway.
2856 */
02e792fb
DV		 2857}
2858
0b8765c6 2859static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 2860{
2861 struct drm_device *dev = crtc->dev;
79e53945
JB		 2862 struct drm_i915_private *dev_priv = dev->dev_private;
2863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2864 int pipe = intel_crtc->pipe;
80824003 2865 int plane = intel_crtc->plane;
79e53945 2866
f7abfe8b
CW		 2867 if (intel_crtc->active)
2868 return;
2869
2870 intel_crtc->active = true;
6b383a7f
CW		 2871 intel_update_watermarks(dev);
2872
63d7bbe9 2873 intel_enable_pll(dev_priv, pipe);
040484af 2874 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 2875 intel_enable_plane(dev_priv, plane, pipe);
79e53945 2876
0b8765c6 2877 intel_crtc_load_lut(crtc);
bed4a673 2878 intel_update_fbc(dev);
79e53945 2879
0b8765c6
JB		 2880 /* Give the overlay scaler a chance to enable if it's on this pipe */
2881 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 2882 intel_crtc_update_cursor(crtc, true);
0b8765c6 2883}
79e53945 2884
0b8765c6
JB		 2885static void i9xx_crtc_disable(struct drm_crtc *crtc)
2886{
2887 struct drm_device *dev = crtc->dev;
2888 struct drm_i915_private *dev_priv = dev->dev_private;
2889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2890 int pipe = intel_crtc->pipe;
2891 int plane = intel_crtc->plane;
b690e96c 2892
f7abfe8b
CW		 2893 if (!intel_crtc->active)
2894 return;
2895
0b8765c6 2896 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 2897 intel_crtc_wait_for_pending_flips(crtc);
2898 drm_vblank_off(dev, pipe);
0b8765c6 2899 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 2900 intel_crtc_update_cursor(crtc, false);
0b8765c6
JB		 2901
2902 if (dev_priv->cfb_plane == plane &&
2903 dev_priv->display.disable_fbc)
2904 dev_priv->display.disable_fbc(dev);
79e53945 2905
b24e7179 2906 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 2907 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 2908 intel_disable_pll(dev_priv, pipe);
0b8765c6 2909
f7abfe8b 2910 intel_crtc->active = false;
6b383a7f
CW		 2911 intel_update_fbc(dev);
2912 intel_update_watermarks(dev);
2913 intel_clear_scanline_wait(dev);
0b8765c6
JB		 2914}
2915
2916static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2917{
2918 /* XXX: When our outputs are all unaware of DPMS modes other than off
2919 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2920 */
2921 switch (mode) {
2922 case DRM_MODE_DPMS_ON:
2923 case DRM_MODE_DPMS_STANDBY:
2924 case DRM_MODE_DPMS_SUSPEND:
2925 i9xx_crtc_enable(crtc);
2926 break;
2927 case DRM_MODE_DPMS_OFF:
2928 i9xx_crtc_disable(crtc);
79e53945
JB		 2929 break;
2930 }
2c07245f
ZW		 2931}
2932
2933/**
2934 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 2935 */
2936static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2937{
2938 struct drm_device *dev = crtc->dev;
e70236a8 2939 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 2940 struct drm_i915_master_private *master_priv;
2941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2942 int pipe = intel_crtc->pipe;
2943 bool enabled;
2944
032d2a0d
CW		 2945 if (intel_crtc->dpms_mode == mode)
2946 return;
2947
65655d4a 2948 intel_crtc->dpms_mode = mode;
debcaddc 2949
e70236a8 2950 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 2951
2952 if (!dev->primary->master)
2953 return;
2954
2955 master_priv = dev->primary->master->driver_priv;
2956 if (!master_priv->sarea_priv)
2957 return;
2958
2959 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2960
2961 switch (pipe) {
2962 case 0:
2963 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2964 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2965 break;
2966 case 1:
2967 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2968 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2969 break;
2970 default:
9db4a9c7 2971 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 2972 break;
2973 }
79e53945
JB		 2974}
2975
cdd59983
CW		 2976static void intel_crtc_disable(struct drm_crtc *crtc)
2977{
2978 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2979 struct drm_device *dev = crtc->dev;
2980
2981 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2982
2983 if (crtc->fb) {
2984 mutex_lock(&dev->struct_mutex);
2985 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2986 mutex_unlock(&dev->struct_mutex);
2987 }
2988}
2989
7e7d76c3
JB		 2990/* Prepare for a mode set.
2991 *
2992 * Note we could be a lot smarter here. We need to figure out which outputs
2993 * will be enabled, which disabled (in short, how the config will changes)
2994 * and perform the minimum necessary steps to accomplish that, e.g. updating
2995 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2996 * panel fitting is in the proper state, etc.
2997 */
2998static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 2999{
7e7d76c3 3000 i9xx_crtc_disable(crtc);
79e53945
JB		 3001}
3002
7e7d76c3 3003static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3004{
7e7d76c3 3005 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3006}
3007
3008static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3009{
7e7d76c3 3010 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3011}
3012
3013static void ironlake_crtc_commit(struct drm_crtc *crtc)
3014{
7e7d76c3 3015 ironlake_crtc_enable(crtc);
79e53945
JB		 3016}
3017
3018void intel_encoder_prepare (struct drm_encoder *encoder)
3019{
3020 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3021 /* lvds has its own version of prepare see intel_lvds_prepare */
3022 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3023}
3024
3025void intel_encoder_commit (struct drm_encoder *encoder)
3026{
3027 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3028 /* lvds has its own version of commit see intel_lvds_commit */
3029 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3030}
3031
ea5b213a
CW		 3032void intel_encoder_destroy(struct drm_encoder *encoder)
3033{
4ef69c7a 3034 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3035
ea5b213a
CW		 3036 drm_encoder_cleanup(encoder);
3037 kfree(intel_encoder);
3038}
3039
79e53945
JB		 3040static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3041 struct drm_display_mode *mode,
3042 struct drm_display_mode *adjusted_mode)
3043{
2c07245f 3044 struct drm_device *dev = crtc->dev;
89749350 3045
bad720ff 3046 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3047 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3048 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3049 return false;
2c07245f 3050 }
89749350
CW		 3051
3052 /* XXX some encoders set the crtcinfo, others don't.
3053 * Obviously we need some form of conflict resolution here...
3054 */
3055 if (adjusted_mode->crtc_htotal == 0)
3056 drm_mode_set_crtcinfo(adjusted_mode, 0);
3057
79e53945
JB		 3058 return true;
3059}
3060
e70236a8
JB		 3061static int i945_get_display_clock_speed(struct drm_device *dev)
3062{
3063 return 400000;
3064}
79e53945 3065
e70236a8 3066static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3067{
e70236a8
JB		 3068 return 333000;
3069}
79e53945 3070
e70236a8
JB		 3071static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3072{
3073 return 200000;
3074}
79e53945 3075
e70236a8
JB		 3076static int i915gm_get_display_clock_speed(struct drm_device *dev)
3077{
3078 u16 gcfgc = 0;
79e53945 3079
e70236a8
JB		 3080 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3081
3082 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3083 return 133000;
3084 else {
3085 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3086 case GC_DISPLAY_CLOCK_333_MHZ:
3087 return 333000;
3088 default:
3089 case GC_DISPLAY_CLOCK_190_200_MHZ:
3090 return 190000;
79e53945 3091 }
e70236a8
JB		 3092 }
3093}
3094
3095static int i865_get_display_clock_speed(struct drm_device *dev)
3096{
3097 return 266000;
3098}
3099
3100static int i855_get_display_clock_speed(struct drm_device *dev)
3101{
3102 u16 hpllcc = 0;
3103 /* Assume that the hardware is in the high speed state. This
3104 * should be the default.
3105 */
3106 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3107 case GC_CLOCK_133_200:
3108 case GC_CLOCK_100_200:
3109 return 200000;
3110 case GC_CLOCK_166_250:
3111 return 250000;
3112 case GC_CLOCK_100_133:
79e53945 3113 return 133000;
e70236a8 3114 }
79e53945 3115
e70236a8
JB		 3116 /* Shouldn't happen */
3117 return 0;
3118}
79e53945 3119
e70236a8
JB		 3120static int i830_get_display_clock_speed(struct drm_device *dev)
3121{
3122 return 133000;
79e53945
JB		 3123}
3124
2c07245f
ZW		 3125struct fdi_m_n {
3126 u32 tu;
3127 u32 gmch_m;
3128 u32 gmch_n;
3129 u32 link_m;
3130 u32 link_n;
3131};
3132
3133static void
3134fdi_reduce_ratio(u32 *num, u32 *den)
3135{
3136 while (*num > 0xffffff || *den > 0xffffff) {
3137 *num >>= 1;
3138 *den >>= 1;
3139 }
3140}
3141
2c07245f 3142static void
f2b115e6
AJ		 3143ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3144 int link_clock, struct fdi_m_n *m_n)
2c07245f 3145{
2c07245f
ZW		 3146 m_n->tu = 64; /* default size */
3147
22ed1113
CW		 3148 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3149 m_n->gmch_m = bits_per_pixel * pixel_clock;
3150 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3151 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3152
22ed1113
CW		 3153 m_n->link_m = pixel_clock;
3154 m_n->link_n = link_clock;
2c07245f
ZW		 3155 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3156}
3157
3158
7662c8bd
SL		 3159struct intel_watermark_params {
3160 unsigned long fifo_size;
3161 unsigned long max_wm;
3162 unsigned long default_wm;
3163 unsigned long guard_size;
3164 unsigned long cacheline_size;
3165};
3166
f2b115e6 3167/* Pineview has different values for various configs */
d210246a 3168static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3169 PINEVIEW_DISPLAY_FIFO,
3170 PINEVIEW_MAX_WM,
3171 PINEVIEW_DFT_WM,
3172 PINEVIEW_GUARD_WM,
3173 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3174};
d210246a 3175static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3176 PINEVIEW_DISPLAY_FIFO,
3177 PINEVIEW_MAX_WM,
3178 PINEVIEW_DFT_HPLLOFF_WM,
3179 PINEVIEW_GUARD_WM,
3180 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3181};
d210246a 3182static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3183 PINEVIEW_CURSOR_FIFO,
3184 PINEVIEW_CURSOR_MAX_WM,
3185 PINEVIEW_CURSOR_DFT_WM,
3186 PINEVIEW_CURSOR_GUARD_WM,
3187 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3188};
d210246a 3189static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3190 PINEVIEW_CURSOR_FIFO,
3191 PINEVIEW_CURSOR_MAX_WM,
3192 PINEVIEW_CURSOR_DFT_WM,
3193 PINEVIEW_CURSOR_GUARD_WM,
3194 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3195};
d210246a 3196static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3197 G4X_FIFO_SIZE,
3198 G4X_MAX_WM,
3199 G4X_MAX_WM,
3200 2,
3201 G4X_FIFO_LINE_SIZE,
3202};
d210246a 3203static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3204 I965_CURSOR_FIFO,
3205 I965_CURSOR_MAX_WM,
3206 I965_CURSOR_DFT_WM,
3207 2,
3208 G4X_FIFO_LINE_SIZE,
3209};
d210246a 3210static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3211 I965_CURSOR_FIFO,
3212 I965_CURSOR_MAX_WM,
3213 I965_CURSOR_DFT_WM,
3214 2,
3215 I915_FIFO_LINE_SIZE,
3216};
d210246a 3217static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3218 I945_FIFO_SIZE,
7662c8bd
SL		 3219 I915_MAX_WM,
3220 1,
dff33cfc
JB		 3221 2,
3222 I915_FIFO_LINE_SIZE
7662c8bd 3223};
d210246a 3224static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3225 I915_FIFO_SIZE,
7662c8bd
SL		 3226 I915_MAX_WM,
3227 1,
dff33cfc 3228 2,
7662c8bd
SL		 3229 I915_FIFO_LINE_SIZE
3230};
d210246a 3231static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3232 I855GM_FIFO_SIZE,
3233 I915_MAX_WM,
3234 1,
dff33cfc 3235 2,
7662c8bd
SL		 3236 I830_FIFO_LINE_SIZE
3237};
d210246a 3238static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3239 I830_FIFO_SIZE,
3240 I915_MAX_WM,
3241 1,
dff33cfc 3242 2,
7662c8bd
SL		 3243 I830_FIFO_LINE_SIZE
3244};
3245
d210246a 3246static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3247 ILK_DISPLAY_FIFO,
3248 ILK_DISPLAY_MAXWM,
3249 ILK_DISPLAY_DFTWM,
3250 2,
3251 ILK_FIFO_LINE_SIZE
3252};
d210246a 3253static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3254 ILK_CURSOR_FIFO,
3255 ILK_CURSOR_MAXWM,
3256 ILK_CURSOR_DFTWM,
3257 2,
3258 ILK_FIFO_LINE_SIZE
3259};
d210246a 3260static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3261 ILK_DISPLAY_SR_FIFO,
3262 ILK_DISPLAY_MAX_SRWM,
3263 ILK_DISPLAY_DFT_SRWM,
3264 2,
3265 ILK_FIFO_LINE_SIZE
3266};
d210246a 3267static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3268 ILK_CURSOR_SR_FIFO,
3269 ILK_CURSOR_MAX_SRWM,
3270 ILK_CURSOR_DFT_SRWM,
3271 2,
3272 ILK_FIFO_LINE_SIZE
3273};
3274
d210246a 3275static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3276 SNB_DISPLAY_FIFO,
3277 SNB_DISPLAY_MAXWM,
3278 SNB_DISPLAY_DFTWM,
3279 2,
3280 SNB_FIFO_LINE_SIZE
3281};
d210246a 3282static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3283 SNB_CURSOR_FIFO,
3284 SNB_CURSOR_MAXWM,
3285 SNB_CURSOR_DFTWM,
3286 2,
3287 SNB_FIFO_LINE_SIZE
3288};
d210246a 3289static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3290 SNB_DISPLAY_SR_FIFO,
3291 SNB_DISPLAY_MAX_SRWM,
3292 SNB_DISPLAY_DFT_SRWM,
3293 2,
3294 SNB_FIFO_LINE_SIZE
3295};
d210246a 3296static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3297 SNB_CURSOR_SR_FIFO,
3298 SNB_CURSOR_MAX_SRWM,
3299 SNB_CURSOR_DFT_SRWM,
3300 2,
3301 SNB_FIFO_LINE_SIZE
3302};
3303
3304
dff33cfc
JB		 3305/**
3306 * intel_calculate_wm - calculate watermark level
3307 * @clock_in_khz: pixel clock
3308 * @wm: chip FIFO params
3309 * @pixel_size: display pixel size
3310 * @latency_ns: memory latency for the platform
3311 *
3312 * Calculate the watermark level (the level at which the display plane will
3313 * start fetching from memory again). Each chip has a different display
3314 * FIFO size and allocation, so the caller needs to figure that out and pass
3315 * in the correct intel_watermark_params structure.
3316 *
3317 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3318 * on the pixel size. When it reaches the watermark level, it'll start
3319 * fetching FIFO line sized based chunks from memory until the FIFO fills
3320 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3321 * will occur, and a display engine hang could result.
3322 */
7662c8bd 3323static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3324 const struct intel_watermark_params *wm,
3325 int fifo_size,
7662c8bd
SL		 3326 int pixel_size,
3327 unsigned long latency_ns)
3328{
390c4dd4 3329 long entries_required, wm_size;
dff33cfc 3330
d660467c
JB		 3331 /*
3332 * Note: we need to make sure we don't overflow for various clock &
3333 * latency values.
3334 * clocks go from a few thousand to several hundred thousand.
3335 * latency is usually a few thousand
3336 */
3337 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3338 1000;
8de9b311 3339 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3340
bbb0aef5 3341 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3342
d210246a 3343 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3344
bbb0aef5 3345 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3346
390c4dd4
JB		 3347 /* Don't promote wm_size to unsigned... */
3348 if (wm_size > (long)wm->max_wm)
7662c8bd 3349 wm_size = wm->max_wm;
c3add4b6 3350 if (wm_size <= 0)
7662c8bd
SL		 3351 wm_size = wm->default_wm;
3352 return wm_size;
3353}
3354
3355struct cxsr_latency {
3356 int is_desktop;
95534263 3357 int is_ddr3;
7662c8bd
SL		 3358 unsigned long fsb_freq;
3359 unsigned long mem_freq;
3360 unsigned long display_sr;
3361 unsigned long display_hpll_disable;
3362 unsigned long cursor_sr;
3363 unsigned long cursor_hpll_disable;
3364};
3365
403c89ff 3366static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3367 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3368 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3369 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3370 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3371 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3372
3373 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3374 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3375 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3376 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3377 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3378
3379 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3380 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3381 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3382 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3383 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3384
3385 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3386 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3387 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3388 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3389 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3390
3391 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3392 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3393 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3394 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3395 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3396
3397 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3398 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3399 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3400 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3401 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3402};
3403
403c89ff
CW		 3404static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3405 int is_ddr3,
3406 int fsb,
3407 int mem)
7662c8bd 3408{
403c89ff 3409 const struct cxsr_latency *latency;
7662c8bd 3410 int i;
7662c8bd
SL		 3411
3412 if (fsb == 0 || mem == 0)
3413 return NULL;
3414
3415 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3416 latency = &cxsr_latency_table[i];
3417 if (is_desktop == latency->is_desktop &&
95534263 3418 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3419 fsb == latency->fsb_freq && mem == latency->mem_freq)
3420 return latency;
7662c8bd 3421 }
decbbcda 3422
28c97730 3423 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3424
3425 return NULL;
7662c8bd
SL		 3426}
3427
f2b115e6 3428static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3429{
3430 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3431
3432 /* deactivate cxsr */
3e33d94d 3433 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3434}
3435
bcc24fb4
JB		 3436/*
3437 * Latency for FIFO fetches is dependent on several factors:
3438 * - memory configuration (speed, channels)
3439 * - chipset
3440 * - current MCH state
3441 * It can be fairly high in some situations, so here we assume a fairly
3442 * pessimal value. It's a tradeoff between extra memory fetches (if we
3443 * set this value too high, the FIFO will fetch frequently to stay full)
3444 * and power consumption (set it too low to save power and we might see
3445 * FIFO underruns and display "flicker").
3446 *
3447 * A value of 5us seems to be a good balance; safe for very low end
3448 * platforms but not overly aggressive on lower latency configs.
3449 */
69e302a9 3450static const int latency_ns = 5000;
7662c8bd 3451
e70236a8 3452static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3453{
3454 struct drm_i915_private *dev_priv = dev->dev_private;
3455 uint32_t dsparb = I915_READ(DSPARB);
3456 int size;
3457
8de9b311
CW		 3458 size = dsparb & 0x7f;
3459 if (plane)
3460 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3461
28c97730 3462 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3463 plane ? "B" : "A", size);
dff33cfc
JB		 3464
3465 return size;
3466}
7662c8bd 3467
e70236a8
JB		 3468static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3469{
3470 struct drm_i915_private *dev_priv = dev->dev_private;
3471 uint32_t dsparb = I915_READ(DSPARB);
3472 int size;
3473
8de9b311
CW		 3474 size = dsparb & 0x1ff;
3475 if (plane)
3476 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3477 size >>= 1; /* Convert to cachelines */
dff33cfc 3478
28c97730 3479 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3480 plane ? "B" : "A", size);
dff33cfc
JB		 3481
3482 return size;
3483}
7662c8bd 3484
e70236a8
JB		 3485static int i845_get_fifo_size(struct drm_device *dev, int plane)
3486{
3487 struct drm_i915_private *dev_priv = dev->dev_private;
3488 uint32_t dsparb = I915_READ(DSPARB);
3489 int size;
3490
3491 size = dsparb & 0x7f;
3492 size >>= 2; /* Convert to cachelines */
3493
28c97730 3494 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3495 plane ? "B" : "A",
3496 size);
e70236a8
JB		 3497
3498 return size;
3499}
3500
3501static int i830_get_fifo_size(struct drm_device *dev, int plane)
3502{
3503 struct drm_i915_private *dev_priv = dev->dev_private;
3504 uint32_t dsparb = I915_READ(DSPARB);
3505 int size;
3506
3507 size = dsparb & 0x7f;
3508 size >>= 1; /* Convert to cachelines */
3509
28c97730 3510 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3511 plane ? "B" : "A", size);
e70236a8
JB		 3512
3513 return size;
3514}
3515
d210246a
CW		 3516static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3517{
3518 struct drm_crtc *crtc, *enabled = NULL;
3519
3520 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3521 if (crtc->enabled && crtc->fb) {
3522 if (enabled)
3523 return NULL;
3524 enabled = crtc;
3525 }
3526 }
3527
3528 return enabled;
3529}
3530
3531static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3532{
3533 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3534 struct drm_crtc *crtc;
403c89ff 3535 const struct cxsr_latency *latency;
d4294342
ZY		 3536 u32 reg;
3537 unsigned long wm;
d4294342 3538
403c89ff 3539 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3540 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3541 if (!latency) {
3542 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3543 pineview_disable_cxsr(dev);
3544 return;
3545 }
3546
d210246a
CW		 3547 crtc = single_enabled_crtc(dev);
3548 if (crtc) {
3549 int clock = crtc->mode.clock;
3550 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3551
3552 /* Display SR */
d210246a
CW		 3553 wm = intel_calculate_wm(clock, &pineview_display_wm,
3554 pineview_display_wm.fifo_size,
d4294342
ZY		 3555 pixel_size, latency->display_sr);
3556 reg = I915_READ(DSPFW1);
3557 reg &= ~DSPFW_SR_MASK;
3558 reg |= wm << DSPFW_SR_SHIFT;
3559 I915_WRITE(DSPFW1, reg);
3560 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3561
3562 /* cursor SR */
d210246a
CW		 3563 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3564 pineview_display_wm.fifo_size,
d4294342
ZY		 3565 pixel_size, latency->cursor_sr);
3566 reg = I915_READ(DSPFW3);
3567 reg &= ~DSPFW_CURSOR_SR_MASK;
3568 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3569 I915_WRITE(DSPFW3, reg);
3570
3571 /* Display HPLL off SR */
d210246a
CW		 3572 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3573 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3574 pixel_size, latency->display_hpll_disable);
3575 reg = I915_READ(DSPFW3);
3576 reg &= ~DSPFW_HPLL_SR_MASK;
3577 reg |= wm & DSPFW_HPLL_SR_MASK;
3578 I915_WRITE(DSPFW3, reg);
3579
3580 /* cursor HPLL off SR */
d210246a
CW		 3581 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3582 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3583 pixel_size, latency->cursor_hpll_disable);
3584 reg = I915_READ(DSPFW3);
3585 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3586 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3587 I915_WRITE(DSPFW3, reg);
3588 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3589
3590 /* activate cxsr */
3e33d94d
CW		 3591 I915_WRITE(DSPFW3,
3592 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3593 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3594 } else {
3595 pineview_disable_cxsr(dev);
3596 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3597 }
3598}
3599
417ae147
CW		 3600static bool g4x_compute_wm0(struct drm_device *dev,
3601 int plane,
3602 const struct intel_watermark_params *display,
3603 int display_latency_ns,
3604 const struct intel_watermark_params *cursor,
3605 int cursor_latency_ns,
3606 int *plane_wm,
3607 int *cursor_wm)
3608{
3609 struct drm_crtc *crtc;
3610 int htotal, hdisplay, clock, pixel_size;
3611 int line_time_us, line_count;
3612 int entries, tlb_miss;
3613
3614 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3615 if (crtc->fb == NULL || !crtc->enabled) {
3616 *cursor_wm = cursor->guard_size;
3617 *plane_wm = display->guard_size;
417ae147 3618 return false;
5c72d064 3619 }
417ae147
CW		 3620
3621 htotal = crtc->mode.htotal;
3622 hdisplay = crtc->mode.hdisplay;
3623 clock = crtc->mode.clock;
3624 pixel_size = crtc->fb->bits_per_pixel / 8;
3625
3626 /* Use the small buffer method to calculate plane watermark */
3627 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3628 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3629 if (tlb_miss > 0)
3630 entries += tlb_miss;
3631 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3632 *plane_wm = entries + display->guard_size;
3633 if (*plane_wm > (int)display->max_wm)
3634 *plane_wm = display->max_wm;
3635
3636 /* Use the large buffer method to calculate cursor watermark */
3637 line_time_us = ((htotal * 1000) / clock);
3638 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3639 entries = line_count * 64 * pixel_size;
3640 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3641 if (tlb_miss > 0)
3642 entries += tlb_miss;
3643 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3644 *cursor_wm = entries + cursor->guard_size;
3645 if (*cursor_wm > (int)cursor->max_wm)
3646 *cursor_wm = (int)cursor->max_wm;
3647
3648 return true;
3649}
3650
3651/*
3652 * Check the wm result.
3653 *
3654 * If any calculated watermark values is larger than the maximum value that
3655 * can be programmed into the associated watermark register, that watermark
3656 * must be disabled.
3657 */
3658static bool g4x_check_srwm(struct drm_device *dev,
3659 int display_wm, int cursor_wm,
3660 const struct intel_watermark_params *display,
3661 const struct intel_watermark_params *cursor)
652c393a 3662{
417ae147
CW		 3663 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3664 display_wm, cursor_wm);
652c393a 3665
417ae147 3666 if (display_wm > display->max_wm) {
bbb0aef5 3667 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3668 display_wm, display->max_wm);
3669 return false;
3670 }
0e442c60 3671
417ae147 3672 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3673 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3674 cursor_wm, cursor->max_wm);
3675 return false;
3676 }
0e442c60 3677
417ae147
CW		 3678 if (!(display_wm || cursor_wm)) {
3679 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3680 return false;
3681 }
0e442c60 3682
417ae147
CW		 3683 return true;
3684}
0e442c60 3685
417ae147 3686static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3687 int plane,
3688 int latency_ns,
417ae147
CW		 3689 const struct intel_watermark_params *display,
3690 const struct intel_watermark_params *cursor,
3691 int *display_wm, int *cursor_wm)
3692{
d210246a
CW		 3693 struct drm_crtc *crtc;
3694 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 3695 unsigned long line_time_us;
3696 int line_count, line_size;
3697 int small, large;
3698 int entries;
0e442c60 3699
417ae147
CW		 3700 if (!latency_ns) {
3701 *display_wm = *cursor_wm = 0;
3702 return false;
3703 }
0e442c60 3704
d210246a
CW		 3705 crtc = intel_get_crtc_for_plane(dev, plane);
3706 hdisplay = crtc->mode.hdisplay;
3707 htotal = crtc->mode.htotal;
3708 clock = crtc->mode.clock;
3709 pixel_size = crtc->fb->bits_per_pixel / 8;
3710
417ae147
CW		 3711 line_time_us = (htotal * 1000) / clock;
3712 line_count = (latency_ns / line_time_us + 1000) / 1000;
3713 line_size = hdisplay * pixel_size;
0e442c60 3714
417ae147
CW		 3715 /* Use the minimum of the small and large buffer method for primary */
3716 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3717 large = line_count * line_size;
0e442c60 3718
417ae147
CW		 3719 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3720 *display_wm = entries + display->guard_size;
4fe5e611 3721
417ae147
CW		 3722 /* calculate the self-refresh watermark for display cursor */
3723 entries = line_count * pixel_size * 64;
3724 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3725 *cursor_wm = entries + cursor->guard_size;
4fe5e611 3726
417ae147
CW		 3727 return g4x_check_srwm(dev,
3728 *display_wm, *cursor_wm,
3729 display, cursor);
3730}
4fe5e611 3731
7ccb4a53 3732#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 3733
3734static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 3735{
3736 static const int sr_latency_ns = 12000;
3737 struct drm_i915_private *dev_priv = dev->dev_private;
3738 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 3739 int plane_sr, cursor_sr;
3740 unsigned int enabled = 0;
417ae147
CW		 3741
3742 if (g4x_compute_wm0(dev, 0,
3743 &g4x_wm_info, latency_ns,
3744 &g4x_cursor_wm_info, latency_ns,
3745 &planea_wm, &cursora_wm))
d210246a 3746 enabled |= 1;
417ae147
CW		 3747
3748 if (g4x_compute_wm0(dev, 1,
3749 &g4x_wm_info, latency_ns,
3750 &g4x_cursor_wm_info, latency_ns,
3751 &planeb_wm, &cursorb_wm))
d210246a 3752 enabled |= 2;
417ae147
CW		 3753
3754 plane_sr = cursor_sr = 0;
d210246a
CW		 3755 if (single_plane_enabled(enabled) &&
3756 g4x_compute_srwm(dev, ffs(enabled) - 1,
3757 sr_latency_ns,
417ae147
CW		 3758 &g4x_wm_info,
3759 &g4x_cursor_wm_info,
3760 &plane_sr, &cursor_sr))
0e442c60 3761 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 3762 else
3763 I915_WRITE(FW_BLC_SELF,
3764 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 3765
308977ac
CW		 3766 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
3767 planea_wm, cursora_wm,
3768 planeb_wm, cursorb_wm,
3769 plane_sr, cursor_sr);
0e442c60 3770
417ae147
CW		 3771 I915_WRITE(DSPFW1,
3772 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 3773 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 3774 (planeb_wm << DSPFW_PLANEB_SHIFT) |
3775 planea_wm);
3776 I915_WRITE(DSPFW2,
3777 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 3778 (cursora_wm << DSPFW_CURSORA_SHIFT));
3779 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 3780 I915_WRITE(DSPFW3,
3781 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 3782 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 3783}
3784
d210246a 3785static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 3786{
3787 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3788 struct drm_crtc *crtc;
3789 int srwm = 1;
4fe5e611 3790 int cursor_sr = 16;
1dc7546d
JB		 3791
3792 /* Calc sr entries for one plane configs */
d210246a
CW		 3793 crtc = single_enabled_crtc(dev);
3794 if (crtc) {
1dc7546d 3795 /* self-refresh has much higher latency */
69e302a9 3796 static const int sr_latency_ns = 12000;
d210246a
CW		 3797 int clock = crtc->mode.clock;
3798 int htotal = crtc->mode.htotal;
3799 int hdisplay = crtc->mode.hdisplay;
3800 int pixel_size = crtc->fb->bits_per_pixel / 8;
3801 unsigned long line_time_us;
3802 int entries;
1dc7546d 3803
d210246a 3804 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 3805
3806 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3807 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3808 pixel_size * hdisplay;
3809 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 3810 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 3811 if (srwm < 0)
3812 srwm = 1;
1b07e04e 3813 srwm &= 0x1ff;
308977ac
CW		 3814 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
3815 entries, srwm);
4fe5e611 3816
d210246a 3817 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 3818 pixel_size * 64;
d210246a 3819 entries = DIV_ROUND_UP(entries,
8de9b311 3820 i965_cursor_wm_info.cacheline_size);
4fe5e611 3821 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 3822 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 3823
3824 if (cursor_sr > i965_cursor_wm_info.max_wm)
3825 cursor_sr = i965_cursor_wm_info.max_wm;
3826
3827 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3828 "cursor %d\n", srwm, cursor_sr);
3829
a6c45cf0 3830 if (IS_CRESTLINE(dev))
adcdbc66 3831 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 3832 } else {
3833 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 3834 if (IS_CRESTLINE(dev))
adcdbc66
JB		 3835 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3836 & ~FW_BLC_SELF_EN);
1dc7546d 3837 }
7662c8bd 3838
1dc7546d
JB		 3839 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3840 srwm);
7662c8bd
SL		 3841
3842 /* 965 has limitations... */
417ae147
CW		 3843 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
3844 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 3845 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 3846 /* update cursor SR watermark */
3847 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 3848}
3849
d210246a 3850static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 3851{
3852 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3853 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 3854 uint32_t fwater_lo;
3855 uint32_t fwater_hi;
d210246a
CW		 3856 int cwm, srwm = 1;
3857 int fifo_size;
dff33cfc 3858 int planea_wm, planeb_wm;
d210246a 3859 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 3860
72557b4f 3861 if (IS_I945GM(dev))
d210246a 3862 wm_info = &i945_wm_info;
a6c45cf0 3863 else if (!IS_GEN2(dev))
d210246a 3864 wm_info = &i915_wm_info;
7662c8bd 3865 else
d210246a
CW		 3866 wm_info = &i855_wm_info;
3867
3868 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3869 crtc = intel_get_crtc_for_plane(dev, 0);
3870 if (crtc->enabled && crtc->fb) {
3871 planea_wm = intel_calculate_wm(crtc->mode.clock,
3872 wm_info, fifo_size,
3873 crtc->fb->bits_per_pixel / 8,
3874 latency_ns);
3875 enabled = crtc;
3876 } else
3877 planea_wm = fifo_size - wm_info->guard_size;
3878
3879 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3880 crtc = intel_get_crtc_for_plane(dev, 1);
3881 if (crtc->enabled && crtc->fb) {
3882 planeb_wm = intel_calculate_wm(crtc->mode.clock,
3883 wm_info, fifo_size,
3884 crtc->fb->bits_per_pixel / 8,
3885 latency_ns);
3886 if (enabled == NULL)
3887 enabled = crtc;
3888 else
3889 enabled = NULL;
3890 } else
3891 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 3892
28c97730 3893 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 3894
3895 /*
3896 * Overlay gets an aggressive default since video jitter is bad.
3897 */
3898 cwm = 2;
3899
18b2190c
AL		 3900 /* Play safe and disable self-refresh before adjusting watermarks. */
3901 if (IS_I945G(dev) || IS_I945GM(dev))
3902 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
3903 else if (IS_I915GM(dev))
3904 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3905
dff33cfc 3906 /* Calc sr entries for one plane configs */
d210246a 3907 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 3908 /* self-refresh has much higher latency */
69e302a9 3909 static const int sr_latency_ns = 6000;
d210246a
CW		 3910 int clock = enabled->mode.clock;
3911 int htotal = enabled->mode.htotal;
3912 int hdisplay = enabled->mode.hdisplay;
3913 int pixel_size = enabled->fb->bits_per_pixel / 8;
3914 unsigned long line_time_us;
3915 int entries;
dff33cfc 3916
d210246a 3917 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 3918
3919 /* Use ns/us then divide to preserve precision */
d210246a
CW		 3920 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3921 pixel_size * hdisplay;
3922 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
3923 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
3924 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 3925 if (srwm < 0)
3926 srwm = 1;
ee980b80
LP		 3927
3928 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 3929 I915_WRITE(FW_BLC_SELF,
3930 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3931 else if (IS_I915GM(dev))
ee980b80 3932 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 3933 }
3934
28c97730 3935 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 3936 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 3937
dff33cfc
JB		 3938 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3939 fwater_hi = (cwm & 0x1f);
3940
3941 /* Set request length to 8 cachelines per fetch */
3942 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3943 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 3944
3945 I915_WRITE(FW_BLC, fwater_lo);
3946 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 3947
d210246a
CW		 3948 if (HAS_FW_BLC(dev)) {
3949 if (enabled) {
3950 if (IS_I945G(dev) || IS_I945GM(dev))
3951 I915_WRITE(FW_BLC_SELF,
3952 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
3953 else if (IS_I915GM(dev))
3954 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3955 DRM_DEBUG_KMS("memory self refresh enabled\n");
3956 } else
3957 DRM_DEBUG_KMS("memory self refresh disabled\n");
3958 }
7662c8bd
SL		 3959}
3960
d210246a 3961static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 3962{
3963 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 3964 struct drm_crtc *crtc;
3965 uint32_t fwater_lo;
dff33cfc 3966 int planea_wm;
7662c8bd 3967
d210246a
CW		 3968 crtc = single_enabled_crtc(dev);
3969 if (crtc == NULL)
3970 return;
7662c8bd 3971
d210246a
CW		 3972 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
3973 dev_priv->display.get_fifo_size(dev, 0),
3974 crtc->fb->bits_per_pixel / 8,
3975 latency_ns);
3976 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 3977 fwater_lo |= (3<<8) | planea_wm;
3978
28c97730 3979 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 3980
3981 I915_WRITE(FW_BLC, fwater_lo);
3982}
3983
7f8a8569 3984#define ILK_LP0_PLANE_LATENCY 700
c936f44d 3985#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 3986
1398261a
YL		 3987/*
3988 * Check the wm result.
3989 *
3990 * If any calculated watermark values is larger than the maximum value that
3991 * can be programmed into the associated watermark register, that watermark
3992 * must be disabled.
1398261a 3993 */
b79d4990
JB		 3994static bool ironlake_check_srwm(struct drm_device *dev, int level,
3995 int fbc_wm, int display_wm, int cursor_wm,
3996 const struct intel_watermark_params *display,
3997 const struct intel_watermark_params *cursor)
1398261a
YL		 3998{
3999 struct drm_i915_private *dev_priv = dev->dev_private;
4000
4001 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4002 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4003
4004 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4005 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4006 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4007
4008 /* fbc has it's own way to disable FBC WM */
4009 I915_WRITE(DISP_ARB_CTL,
4010 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4011 return false;
4012 }
4013
b79d4990 4014 if (display_wm > display->max_wm) {
1398261a 4015 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4016 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4017 return false;
4018 }
4019
b79d4990 4020 if (cursor_wm > cursor->max_wm) {
1398261a 4021 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4022 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4023 return false;
4024 }
4025
4026 if (!(fbc_wm || display_wm || cursor_wm)) {
4027 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4028 return false;
4029 }
4030
4031 return true;
4032}
4033
4034/*
4035 * Compute watermark values of WM[1-3],
4036 */
d210246a
CW		 4037static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4038 int latency_ns,
b79d4990
JB		 4039 const struct intel_watermark_params *display,
4040 const struct intel_watermark_params *cursor,
4041 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4042{
d210246a 4043 struct drm_crtc *crtc;
1398261a 4044 unsigned long line_time_us;
d210246a 4045 int hdisplay, htotal, pixel_size, clock;
b79d4990 4046 int line_count, line_size;
1398261a
YL		 4047 int small, large;
4048 int entries;
1398261a
YL		 4049
4050 if (!latency_ns) {
4051 *fbc_wm = *display_wm = *cursor_wm = 0;
4052 return false;
4053 }
4054
d210246a
CW		 4055 crtc = intel_get_crtc_for_plane(dev, plane);
4056 hdisplay = crtc->mode.hdisplay;
4057 htotal = crtc->mode.htotal;
4058 clock = crtc->mode.clock;
4059 pixel_size = crtc->fb->bits_per_pixel / 8;
4060
1398261a
YL		 4061 line_time_us = (htotal * 1000) / clock;
4062 line_count = (latency_ns / line_time_us + 1000) / 1000;
4063 line_size = hdisplay * pixel_size;
4064
4065 /* Use the minimum of the small and large buffer method for primary */
4066 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4067 large = line_count * line_size;
4068
b79d4990
JB		 4069 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4070 *display_wm = entries + display->guard_size;
1398261a
YL		 4071
4072 /*
b79d4990 4073 * Spec says:
1398261a
YL		 4074 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4075 */
4076 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4077
4078 /* calculate the self-refresh watermark for display cursor */
4079 entries = line_count * pixel_size * 64;
b79d4990
JB		 4080 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4081 *cursor_wm = entries + cursor->guard_size;
1398261a 4082
b79d4990
JB		 4083 return ironlake_check_srwm(dev, level,
4084 *fbc_wm, *display_wm, *cursor_wm,
4085 display, cursor);
4086}
4087
d210246a 4088static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4089{
4090 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4091 int fbc_wm, plane_wm, cursor_wm;
4092 unsigned int enabled;
b79d4990
JB		 4093
4094 enabled = 0;
9f405100
CW		 4095 if (g4x_compute_wm0(dev, 0,
4096 &ironlake_display_wm_info,
4097 ILK_LP0_PLANE_LATENCY,
4098 &ironlake_cursor_wm_info,
4099 ILK_LP0_CURSOR_LATENCY,
4100 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4101 I915_WRITE(WM0_PIPEA_ILK,
4102 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4103 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4104 " plane %d, " "cursor: %d\n",
4105 plane_wm, cursor_wm);
d210246a 4106 enabled |= 1;
b79d4990
JB		 4107 }
4108
9f405100
CW		 4109 if (g4x_compute_wm0(dev, 1,
4110 &ironlake_display_wm_info,
4111 ILK_LP0_PLANE_LATENCY,
4112 &ironlake_cursor_wm_info,
4113 ILK_LP0_CURSOR_LATENCY,
4114 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4115 I915_WRITE(WM0_PIPEB_ILK,
4116 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4117 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4118 " plane %d, cursor: %d\n",
4119 plane_wm, cursor_wm);
d210246a 4120 enabled |= 2;
b79d4990
JB		 4121 }
4122
4123 /*
4124 * Calculate and update the self-refresh watermark only when one
4125 * display plane is used.
4126 */
4127 I915_WRITE(WM3_LP_ILK, 0);
4128 I915_WRITE(WM2_LP_ILK, 0);
4129 I915_WRITE(WM1_LP_ILK, 0);
4130
d210246a 4131 if (!single_plane_enabled(enabled))
b79d4990 4132 return;
d210246a 4133 enabled = ffs(enabled) - 1;
b79d4990
JB		 4134
4135 /* WM1 */
d210246a
CW		 4136 if (!ironlake_compute_srwm(dev, 1, enabled,
4137 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4138 &ironlake_display_srwm_info,
4139 &ironlake_cursor_srwm_info,
4140 &fbc_wm, &plane_wm, &cursor_wm))
4141 return;
4142
4143 I915_WRITE(WM1_LP_ILK,
4144 WM1_LP_SR_EN |
4145 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4146 (fbc_wm << WM1_LP_FBC_SHIFT) |
4147 (plane_wm << WM1_LP_SR_SHIFT) |
4148 cursor_wm);
4149
4150 /* WM2 */
d210246a
CW		 4151 if (!ironlake_compute_srwm(dev, 2, enabled,
4152 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4153 &ironlake_display_srwm_info,
4154 &ironlake_cursor_srwm_info,
4155 &fbc_wm, &plane_wm, &cursor_wm))
4156 return;
4157
4158 I915_WRITE(WM2_LP_ILK,
4159 WM2_LP_EN |
4160 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4161 (fbc_wm << WM1_LP_FBC_SHIFT) |
4162 (plane_wm << WM1_LP_SR_SHIFT) |
4163 cursor_wm);
4164
4165 /*
4166 * WM3 is unsupported on ILK, probably because we don't have latency
4167 * data for that power state
4168 */
1398261a
YL		 4169}
4170
d210246a 4171static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4172{
4173 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4174 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4175 int fbc_wm, plane_wm, cursor_wm;
4176 unsigned int enabled;
1398261a
YL		 4177
4178 enabled = 0;
9f405100
CW		 4179 if (g4x_compute_wm0(dev, 0,
4180 &sandybridge_display_wm_info, latency,
4181 &sandybridge_cursor_wm_info, latency,
4182 &plane_wm, &cursor_wm)) {
1398261a
YL		 4183 I915_WRITE(WM0_PIPEA_ILK,
4184 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4185 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4186 " plane %d, " "cursor: %d\n",
4187 plane_wm, cursor_wm);
d210246a 4188 enabled |= 1;
1398261a
YL		 4189 }
4190
9f405100
CW		 4191 if (g4x_compute_wm0(dev, 1,
4192 &sandybridge_display_wm_info, latency,
4193 &sandybridge_cursor_wm_info, latency,
4194 &plane_wm, &cursor_wm)) {
1398261a
YL		 4195 I915_WRITE(WM0_PIPEB_ILK,
4196 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4197 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4198 " plane %d, cursor: %d\n",
4199 plane_wm, cursor_wm);
d210246a 4200 enabled |= 2;
1398261a
YL		 4201 }
4202
4203 /*
4204 * Calculate and update the self-refresh watermark only when one
4205 * display plane is used.
4206 *
4207 * SNB support 3 levels of watermark.
4208 *
4209 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4210 * and disabled in the descending order
4211 *
4212 */
4213 I915_WRITE(WM3_LP_ILK, 0);
4214 I915_WRITE(WM2_LP_ILK, 0);
4215 I915_WRITE(WM1_LP_ILK, 0);
4216
d210246a 4217 if (!single_plane_enabled(enabled))
1398261a 4218 return;
d210246a 4219 enabled = ffs(enabled) - 1;
1398261a
YL		 4220
4221 /* WM1 */
d210246a
CW		 4222 if (!ironlake_compute_srwm(dev, 1, enabled,
4223 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4224 &sandybridge_display_srwm_info,
4225 &sandybridge_cursor_srwm_info,
4226 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4227 return;
4228
4229 I915_WRITE(WM1_LP_ILK,
4230 WM1_LP_SR_EN |
4231 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4232 (fbc_wm << WM1_LP_FBC_SHIFT) |
4233 (plane_wm << WM1_LP_SR_SHIFT) |
4234 cursor_wm);
4235
4236 /* WM2 */
d210246a
CW		 4237 if (!ironlake_compute_srwm(dev, 2, enabled,
4238 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4239 &sandybridge_display_srwm_info,
4240 &sandybridge_cursor_srwm_info,
4241 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4242 return;
4243
4244 I915_WRITE(WM2_LP_ILK,
4245 WM2_LP_EN |
4246 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4247 (fbc_wm << WM1_LP_FBC_SHIFT) |
4248 (plane_wm << WM1_LP_SR_SHIFT) |
4249 cursor_wm);
4250
4251 /* WM3 */
d210246a
CW		 4252 if (!ironlake_compute_srwm(dev, 3, enabled,
4253 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4254 &sandybridge_display_srwm_info,
4255 &sandybridge_cursor_srwm_info,
4256 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4257 return;
4258
4259 I915_WRITE(WM3_LP_ILK,
4260 WM3_LP_EN |
4261 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4262 (fbc_wm << WM1_LP_FBC_SHIFT) |
4263 (plane_wm << WM1_LP_SR_SHIFT) |
4264 cursor_wm);
4265}
4266
7662c8bd
SL		 4267/**
4268 * intel_update_watermarks - update FIFO watermark values based on current modes
4269 *
4270 * Calculate watermark values for the various WM regs based on current mode
4271 * and plane configuration.
4272 *
4273 * There are several cases to deal with here:
4274 * - normal (i.e. non-self-refresh)
4275 * - self-refresh (SR) mode
4276 * - lines are large relative to FIFO size (buffer can hold up to 2)
4277 * - lines are small relative to FIFO size (buffer can hold more than 2
4278 * lines), so need to account for TLB latency
4279 *
4280 * The normal calculation is:
4281 * watermark = dotclock * bytes per pixel * latency
4282 * where latency is platform & configuration dependent (we assume pessimal
4283 * values here).
4284 *
4285 * The SR calculation is:
4286 * watermark = (trunc(latency/line time)+1) * surface width *
4287 * bytes per pixel
4288 * where
4289 * line time = htotal / dotclock
fa143215 4290 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4291 * and latency is assumed to be high, as above.
4292 *
4293 * The final value programmed to the register should always be rounded up,
4294 * and include an extra 2 entries to account for clock crossings.
4295 *
4296 * We don't use the sprite, so we can ignore that. And on Crestline we have
4297 * to set the non-SR watermarks to 8.
5eddb70b 4298 */
7662c8bd
SL		 4299static void intel_update_watermarks(struct drm_device *dev)
4300{
e70236a8 4301 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4302
d210246a
CW		 4303 if (dev_priv->display.update_wm)
4304 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4305}
4306
a7615030
CW		 4307static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4308{
4309 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
4310}
4311
f564048e
EA		 4312static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4313 struct drm_display_mode *mode,
4314 struct drm_display_mode *adjusted_mode,
4315 int x, int y,
4316 struct drm_framebuffer *old_fb)
79e53945
JB		 4317{
4318 struct drm_device *dev = crtc->dev;
4319 struct drm_i915_private *dev_priv = dev->dev_private;
4320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4321 int pipe = intel_crtc->pipe;
80824003 4322 int plane = intel_crtc->plane;
c751ce4f 4323 int refclk, num_connectors = 0;
652c393a 4324 intel_clock_t clock, reduced_clock;
5eddb70b 4325 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4326 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4327 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4328 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4329 struct intel_encoder *encoder;
d4906093 4330 const intel_limit_t *limit;
5c3b82e2 4331 int ret;
fae14981 4332 u32 temp;
aa9b500d 4333 u32 lvds_sync = 0;
79e53945 4334
5eddb70b
CW		 4335 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4336 if (encoder->base.crtc != crtc)
79e53945
JB		 4337 continue;
4338
5eddb70b 4339 switch (encoder->type) {
79e53945
JB		 4340 case INTEL_OUTPUT_LVDS:
4341 is_lvds = true;
4342 break;
4343 case INTEL_OUTPUT_SDVO:
7d57382e 4344 case INTEL_OUTPUT_HDMI:
79e53945 4345 is_sdvo = true;
5eddb70b 4346 if (encoder->needs_tv_clock)
e2f0ba97 4347 is_tv = true;
79e53945
JB		 4348 break;
4349 case INTEL_OUTPUT_DVO:
4350 is_dvo = true;
4351 break;
4352 case INTEL_OUTPUT_TVOUT:
4353 is_tv = true;
4354 break;
4355 case INTEL_OUTPUT_ANALOG:
4356 is_crt = true;
4357 break;
a4fc5ed6
KP		 4358 case INTEL_OUTPUT_DISPLAYPORT:
4359 is_dp = true;
4360 break;
79e53945 4361 }
43565a06 4362
c751ce4f 4363 num_connectors++;
79e53945
JB		 4364 }
4365
a7615030 4366 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4367 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4368 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4369 refclk / 1000);
a6c45cf0 4370 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4371 refclk = 96000;
4372 } else {
4373 refclk = 48000;
4374 }
4375
d4906093
ML		 4376 /*
4377 * Returns a set of divisors for the desired target clock with the given
4378 * refclk, or FALSE. The returned values represent the clock equation:
4379 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4380 */
1b894b59 4381 limit = intel_limit(crtc, refclk);
d4906093 4382 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4383 if (!ok) {
4384 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4385 return -EINVAL;
79e53945
JB		 4386 }
4387
cda4b7d3 4388 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4389 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4390
ddc9003c
ZY		 4391 if (is_lvds && dev_priv->lvds_downclock_avail) {
4392 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4393 dev_priv->lvds_downclock,
4394 refclk,
4395 &reduced_clock);
18f9ed12
ZY		 4396 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4397 /*
4398 * If the different P is found, it means that we can't
4399 * switch the display clock by using the FP0/FP1.
4400 * In such case we will disable the LVDS downclock
4401 * feature.
4402 */
4403 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4404 "LVDS clock/downclock\n");
18f9ed12
ZY		 4405 has_reduced_clock = 0;
4406 }
652c393a 4407 }
7026d4ac
ZW		 4408 /* SDVO TV has fixed PLL values depend on its clock range,
4409 this mirrors vbios setting. */
4410 if (is_sdvo && is_tv) {
4411 if (adjusted_mode->clock >= 100000
5eddb70b 4412 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4413 clock.p1 = 2;
4414 clock.p2 = 10;
4415 clock.n = 3;
4416 clock.m1 = 16;
4417 clock.m2 = 8;
4418 } else if (adjusted_mode->clock >= 140500
5eddb70b 4419 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4420 clock.p1 = 1;
4421 clock.p2 = 10;
4422 clock.n = 6;
4423 clock.m1 = 12;
4424 clock.m2 = 8;
4425 }
4426 }
4427
f2b115e6 4428 if (IS_PINEVIEW(dev)) {
2177832f 4429 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4430 if (has_reduced_clock)
4431 fp2 = (1 << reduced_clock.n) << 16 |
4432 reduced_clock.m1 << 8 | reduced_clock.m2;
4433 } else {
2177832f 4434 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4435 if (has_reduced_clock)
4436 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4437 reduced_clock.m2;
4438 }
79e53945 4439
929c77fb 4440 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4441
a6c45cf0 4442 if (!IS_GEN2(dev)) {
79e53945
JB		 4443 if (is_lvds)
4444 dpll |= DPLLB_MODE_LVDS;
4445 else
4446 dpll |= DPLLB_MODE_DAC_SERIAL;
4447 if (is_sdvo) {
6c9547ff
CW		 4448 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4449 if (pixel_multiplier > 1) {
4450 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4451 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4452 }
79e53945 4453 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4454 }
929c77fb 4455 if (is_dp)
a4fc5ed6 4456 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4457
4458 /* compute bitmask from p1 value */
f2b115e6
AJ		 4459 if (IS_PINEVIEW(dev))
4460 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4461 else {
2177832f 4462 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4463 if (IS_G4X(dev) && has_reduced_clock)
4464 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4465 }
79e53945
JB		 4466 switch (clock.p2) {
4467 case 5:
4468 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4469 break;
4470 case 7:
4471 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4472 break;
4473 case 10:
4474 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4475 break;
4476 case 14:
4477 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4478 break;
4479 }
929c77fb 4480 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4481 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4482 } else {
4483 if (is_lvds) {
4484 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4485 } else {
4486 if (clock.p1 == 2)
4487 dpll |= PLL_P1_DIVIDE_BY_TWO;
4488 else
4489 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4490 if (clock.p2 == 4)
4491 dpll |= PLL_P2_DIVIDE_BY_4;
4492 }
4493 }
4494
43565a06
KH		 4495 if (is_sdvo && is_tv)
4496 dpll |= PLL_REF_INPUT_TVCLKINBC;
4497 else if (is_tv)
79e53945 4498 /* XXX: just matching BIOS for now */
43565a06 4499 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4500 dpll |= 3;
a7615030 4501 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4502 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4503 else
4504 dpll |= PLL_REF_INPUT_DREFCLK;
4505
4506 /* setup pipeconf */
5eddb70b 4507 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4508
4509 /* Set up the display plane register */
4510 dspcntr = DISPPLANE_GAMMA_ENABLE;
4511
f2b115e6 4512 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4513 enable color space conversion */
929c77fb
EA		 4514 if (pipe == 0)
4515 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4516 else
4517 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4518
a6c45cf0 4519 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4520 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4521 * core speed.
4522 *
4523 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4524 * pipe == 0 check?
4525 */
e70236a8
JB		 4526 if (mode->clock >
4527 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4528 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4529 else
5eddb70b 4530 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4531 }
4532
929c77fb 4533 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4534
28c97730 4535 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4536 drm_mode_debug_printmodeline(mode);
4537
fae14981
EA		 4538 I915_WRITE(FP0(pipe), fp);
4539 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4540
fae14981 4541 POSTING_READ(DPLL(pipe));
c713bb08 4542 udelay(150);
8db9d77b 4543
79e53945
JB		 4544 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4545 * This is an exception to the general rule that mode_set doesn't turn
4546 * things on.
4547 */
4548 if (is_lvds) {
fae14981 4549 temp = I915_READ(LVDS);
5eddb70b 4550 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4551 if (pipe == 1) {
929c77fb 4552 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4553 } else {
929c77fb 4554 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 4555 }
a3e17eb8 4556 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4557 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4558 /* Set the B0-B3 data pairs corresponding to whether we're going to
4559 * set the DPLLs for dual-channel mode or not.
4560 */
4561 if (clock.p2 == 7)
5eddb70b 4562 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4563 else
5eddb70b 4564 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4565
4566 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4567 * appropriately here, but we need to look more thoroughly into how
4568 * panels behave in the two modes.
4569 */
929c77fb
EA		 4570 /* set the dithering flag on LVDS as needed */
4571 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 4572 if (dev_priv->lvds_dither)
5eddb70b 4573 temp |= LVDS_ENABLE_DITHER;
434ed097 4574 else
5eddb70b 4575 temp &= ~LVDS_ENABLE_DITHER;
898822ce 4576 }
aa9b500d
BF		 4577 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4578 lvds_sync |= LVDS_HSYNC_POLARITY;
4579 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4580 lvds_sync |= LVDS_VSYNC_POLARITY;
4581 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
4582 != lvds_sync) {
4583 char flags[2] = "-+";
4584 DRM_INFO("Changing LVDS panel from "
4585 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
4586 flags[!(temp & LVDS_HSYNC_POLARITY)],
4587 flags[!(temp & LVDS_VSYNC_POLARITY)],
4588 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
4589 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
4590 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4591 temp |= lvds_sync;
4592 }
fae14981 4593 I915_WRITE(LVDS, temp);
79e53945 4594 }
434ed097 4595
929c77fb 4596 if (is_dp) {
a4fc5ed6 4597 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 4598 }
4599
fae14981 4600 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 4601
c713bb08 4602 /* Wait for the clocks to stabilize. */
fae14981 4603 POSTING_READ(DPLL(pipe));
c713bb08 4604 udelay(150);
32f9d658 4605
c713bb08
EA		 4606 if (INTEL_INFO(dev)->gen >= 4) {
4607 temp = 0;
4608 if (is_sdvo) {
4609 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4610 if (temp > 1)
4611 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4612 else
4613 temp = 0;
32f9d658 4614 }
c713bb08
EA		 4615 I915_WRITE(DPLL_MD(pipe), temp);
4616 } else {
4617 /* The pixel multiplier can only be updated once the
4618 * DPLL is enabled and the clocks are stable.
4619 *
4620 * So write it again.
4621 */
fae14981 4622 I915_WRITE(DPLL(pipe), dpll);
79e53945 4623 }
79e53945 4624
5eddb70b 4625 intel_crtc->lowfreq_avail = false;
652c393a 4626 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 4627 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 4628 intel_crtc->lowfreq_avail = true;
4629 if (HAS_PIPE_CXSR(dev)) {
28c97730 4630 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 4631 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4632 }
4633 } else {
fae14981 4634 I915_WRITE(FP1(pipe), fp);
652c393a 4635 if (HAS_PIPE_CXSR(dev)) {
28c97730 4636 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4637 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4638 }
4639 }
4640
734b4157
KH		 4641 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4642 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4643 /* the chip adds 2 halflines automatically */
4644 adjusted_mode->crtc_vdisplay -= 1;
4645 adjusted_mode->crtc_vtotal -= 1;
4646 adjusted_mode->crtc_vblank_start -= 1;
4647 adjusted_mode->crtc_vblank_end -= 1;
4648 adjusted_mode->crtc_vsync_end -= 1;
4649 adjusted_mode->crtc_vsync_start -= 1;
4650 } else
4651 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4652
5eddb70b
CW		 4653 I915_WRITE(HTOTAL(pipe),
4654 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4655 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4656 I915_WRITE(HBLANK(pipe),
4657 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4658 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4659 I915_WRITE(HSYNC(pipe),
4660 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4661 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4662
4663 I915_WRITE(VTOTAL(pipe),
4664 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4665 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4666 I915_WRITE(VBLANK(pipe),
4667 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4668 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4669 I915_WRITE(VSYNC(pipe),
4670 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4671 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4672
4673 /* pipesrc and dspsize control the size that is scaled from,
4674 * which should always be the user's requested size.
79e53945 4675 */
929c77fb
EA		 4676 I915_WRITE(DSPSIZE(plane),
4677 ((mode->vdisplay - 1) << 16) |
4678 (mode->hdisplay - 1));
4679 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4680 I915_WRITE(PIPESRC(pipe),
4681 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4682
f564048e
EA		 4683 I915_WRITE(PIPECONF(pipe), pipeconf);
4684 POSTING_READ(PIPECONF(pipe));
929c77fb 4685 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4686
4687 intel_wait_for_vblank(dev, pipe);
4688
f564048e
EA		 4689 I915_WRITE(DSPCNTR(plane), dspcntr);
4690 POSTING_READ(DSPCNTR(plane));
284d9529 4691 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 4692
4693 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4694
4695 intel_update_watermarks(dev);
4696
f564048e
EA		 4697 return ret;
4698}
4699
4700static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4701 struct drm_display_mode *mode,
4702 struct drm_display_mode *adjusted_mode,
4703 int x, int y,
4704 struct drm_framebuffer *old_fb)
79e53945
JB		 4705{
4706 struct drm_device *dev = crtc->dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4709 int pipe = intel_crtc->pipe;
80824003 4710 int plane = intel_crtc->plane;
c751ce4f 4711 int refclk, num_connectors = 0;
652c393a 4712 intel_clock_t clock, reduced_clock;
5eddb70b 4713 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4714 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4715 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 4716 struct intel_encoder *has_edp_encoder = NULL;
79e53945 4717 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4718 struct intel_encoder *encoder;
d4906093 4719 const intel_limit_t *limit;
5c3b82e2 4720 int ret;
2c07245f 4721 struct fdi_m_n m_n = {0};
fae14981 4722 u32 temp;
aa9b500d 4723 u32 lvds_sync = 0;
8febb297 4724 int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
79e53945 4725
5eddb70b
CW		 4726 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4727 if (encoder->base.crtc != crtc)
79e53945
JB		 4728 continue;
4729
5eddb70b 4730 switch (encoder->type) {
79e53945
JB		 4731 case INTEL_OUTPUT_LVDS:
4732 is_lvds = true;
4733 break;
4734 case INTEL_OUTPUT_SDVO:
7d57382e 4735 case INTEL_OUTPUT_HDMI:
79e53945 4736 is_sdvo = true;
5eddb70b 4737 if (encoder->needs_tv_clock)
e2f0ba97 4738 is_tv = true;
79e53945 4739 break;
79e53945
JB		 4740 case INTEL_OUTPUT_TVOUT:
4741 is_tv = true;
4742 break;
4743 case INTEL_OUTPUT_ANALOG:
4744 is_crt = true;
4745 break;
a4fc5ed6
KP		 4746 case INTEL_OUTPUT_DISPLAYPORT:
4747 is_dp = true;
4748 break;
32f9d658 4749 case INTEL_OUTPUT_EDP:
5eddb70b 4750 has_edp_encoder = encoder;
32f9d658 4751 break;
79e53945 4752 }
43565a06 4753
c751ce4f 4754 num_connectors++;
79e53945
JB		 4755 }
4756
a7615030 4757 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4758 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4759 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4760 refclk / 1000);
a07d6787 4761 } else {
79e53945 4762 refclk = 96000;
8febb297
EA		 4763 if (!has_edp_encoder ||
4764 intel_encoder_is_pch_edp(&has_edp_encoder->base))
2c07245f 4765 refclk = 120000; /* 120Mhz refclk */
79e53945
JB		 4766 }
4767
d4906093
ML		 4768 /*
4769 * Returns a set of divisors for the desired target clock with the given
4770 * refclk, or FALSE. The returned values represent the clock equation:
4771 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4772 */
1b894b59 4773 limit = intel_limit(crtc, refclk);
d4906093 4774 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4775 if (!ok) {
4776 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4777 return -EINVAL;
79e53945
JB		 4778 }
4779
cda4b7d3 4780 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4781 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4782
ddc9003c
ZY		 4783 if (is_lvds && dev_priv->lvds_downclock_avail) {
4784 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4785 dev_priv->lvds_downclock,
4786 refclk,
4787 &reduced_clock);
18f9ed12
ZY		 4788 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4789 /*
4790 * If the different P is found, it means that we can't
4791 * switch the display clock by using the FP0/FP1.
4792 * In such case we will disable the LVDS downclock
4793 * feature.
4794 */
4795 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4796 "LVDS clock/downclock\n");
18f9ed12
ZY		 4797 has_reduced_clock = 0;
4798 }
652c393a 4799 }
7026d4ac
ZW		 4800 /* SDVO TV has fixed PLL values depend on its clock range,
4801 this mirrors vbios setting. */
4802 if (is_sdvo && is_tv) {
4803 if (adjusted_mode->clock >= 100000
5eddb70b 4804 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4805 clock.p1 = 2;
4806 clock.p2 = 10;
4807 clock.n = 3;
4808 clock.m1 = 16;
4809 clock.m2 = 8;
4810 } else if (adjusted_mode->clock >= 140500
5eddb70b 4811 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4812 clock.p1 = 1;
4813 clock.p2 = 10;
4814 clock.n = 6;
4815 clock.m1 = 12;
4816 clock.m2 = 8;
4817 }
4818 }
4819
2c07245f 4820 /* FDI link */
8febb297
EA		 4821 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4822 lane = 0;
4823 /* CPU eDP doesn't require FDI link, so just set DP M/N
4824 according to current link config */
4825 if (has_edp_encoder &&
4826 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4827 target_clock = mode->clock;
4828 intel_edp_link_config(has_edp_encoder,
4829 &lane, &link_bw);
4830 } else {
4831 /* [e]DP over FDI requires target mode clock
4832 instead of link clock */
4833 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 4834 target_clock = mode->clock;
8febb297
EA		 4835 else
4836 target_clock = adjusted_mode->clock;
4837
4838 /* FDI is a binary signal running at ~2.7GHz, encoding
4839 * each output octet as 10 bits. The actual frequency
4840 * is stored as a divider into a 100MHz clock, and the
4841 * mode pixel clock is stored in units of 1KHz.
4842 * Hence the bw of each lane in terms of the mode signal
4843 * is:
4844 */
4845 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4846 }
58a27471 4847
8febb297
EA		 4848 /* determine panel color depth */
4849 temp = I915_READ(PIPECONF(pipe));
4850 temp &= ~PIPE_BPC_MASK;
4851 if (is_lvds) {
4852 /* the BPC will be 6 if it is 18-bit LVDS panel */
4853 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4854 temp |= PIPE_8BPC;
4855 else
4856 temp |= PIPE_6BPC;
4857 } else if (has_edp_encoder) {
4858 switch (dev_priv->edp.bpp/3) {
4859 case 8:
e5a95eb7 4860 temp |= PIPE_8BPC;
58a27471 4861 break;
8febb297
EA		 4862 case 10:
4863 temp |= PIPE_10BPC;
58a27471 4864 break;
8febb297
EA		 4865 case 6:
4866 temp |= PIPE_6BPC;
58a27471 4867 break;
8febb297
EA		 4868 case 12:
4869 temp |= PIPE_12BPC;
58a27471 4870 break;
77ffb597 4871 }
8febb297
EA		 4872 } else
4873 temp |= PIPE_8BPC;
4874 I915_WRITE(PIPECONF(pipe), temp);
77ffb597 4875
8febb297
EA		 4876 switch (temp & PIPE_BPC_MASK) {
4877 case PIPE_8BPC:
4878 bpp = 24;
4879 break;
4880 case PIPE_10BPC:
4881 bpp = 30;
4882 break;
4883 case PIPE_6BPC:
4884 bpp = 18;
4885 break;
4886 case PIPE_12BPC:
4887 bpp = 36;
4888 break;
4889 default:
4890 DRM_ERROR("unknown pipe bpc value\n");
4891 bpp = 24;
4892 }
77ffb597 4893
8febb297
EA		 4894 if (!lane) {
4895 /*
4896 * Account for spread spectrum to avoid
4897 * oversubscribing the link. Max center spread
4898 * is 2.5%; use 5% for safety's sake.
4899 */
4900 u32 bps = target_clock * bpp * 21 / 20;
4901 lane = bps / (link_bw * 8) + 1;
5eb08b69 4902 }
2c07245f 4903
8febb297
EA		 4904 intel_crtc->fdi_lanes = lane;
4905
4906 if (pixel_multiplier > 1)
4907 link_bw *= pixel_multiplier;
4908 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4909
c038e51e
ZW		 4910 /* Ironlake: try to setup display ref clock before DPLL
4911 * enabling. This is only under driver's control after
4912 * PCH B stepping, previous chipset stepping should be
4913 * ignoring this setting.
4914 */
8febb297
EA		 4915 temp = I915_READ(PCH_DREF_CONTROL);
4916 /* Always enable nonspread source */
4917 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4918 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4919 temp &= ~DREF_SSC_SOURCE_MASK;
4920 temp |= DREF_SSC_SOURCE_ENABLE;
4921 I915_WRITE(PCH_DREF_CONTROL, temp);
4922
4923 POSTING_READ(PCH_DREF_CONTROL);
4924 udelay(200);
fc9a2228 4925
8febb297
EA		 4926 if (has_edp_encoder) {
4927 if (intel_panel_use_ssc(dev_priv)) {
4928 temp |= DREF_SSC1_ENABLE;
fc9a2228 4929 I915_WRITE(PCH_DREF_CONTROL, temp);
8febb297 4930
fc9a2228
CW		 4931 POSTING_READ(PCH_DREF_CONTROL);
4932 udelay(200);
4933 }
8febb297
EA		 4934 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4935
4936 /* Enable CPU source on CPU attached eDP */
4937 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4938 if (intel_panel_use_ssc(dev_priv))
4939 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4940 else
4941 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4942 } else {
4943 /* Enable SSC on PCH eDP if needed */
4944 if (intel_panel_use_ssc(dev_priv)) {
4945 DRM_ERROR("enabling SSC on PCH\n");
4946 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4947 }
4948 }
4949 I915_WRITE(PCH_DREF_CONTROL, temp);
4950 POSTING_READ(PCH_DREF_CONTROL);
4951 udelay(200);
fc9a2228 4952 }
c038e51e 4953
a07d6787
EA		 4954 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4955 if (has_reduced_clock)
4956 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4957 reduced_clock.m2;
79e53945 4958
c1858123 4959 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4960 factor = 21;
4961 if (is_lvds) {
4962 if ((intel_panel_use_ssc(dev_priv) &&
4963 dev_priv->lvds_ssc_freq == 100) ||
4964 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4965 factor = 25;
4966 } else if (is_sdvo && is_tv)
4967 factor = 20;
c1858123 4968
8febb297
EA		 4969 if (clock.m1 < factor * clock.n)
4970 fp |= FP_CB_TUNE;
2c07245f 4971
5eddb70b 4972 dpll = 0;
2c07245f 4973
a07d6787
EA		 4974 if (is_lvds)
4975 dpll |= DPLLB_MODE_LVDS;
4976 else
4977 dpll |= DPLLB_MODE_DAC_SERIAL;
4978 if (is_sdvo) {
4979 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4980 if (pixel_multiplier > 1) {
4981 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4982 }
a07d6787
EA		 4983 dpll |= DPLL_DVO_HIGH_SPEED;
4984 }
4985 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4986 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4987
a07d6787
EA		 4988 /* compute bitmask from p1 value */
4989 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4990 /* also FPA1 */
4991 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4992
4993 switch (clock.p2) {
4994 case 5:
4995 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4996 break;
4997 case 7:
4998 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4999 break;
5000 case 10:
5001 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5002 break;
5003 case 14:
5004 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5005 break;
79e53945
JB		 5006 }
5007
43565a06
KH		 5008 if (is_sdvo && is_tv)
5009 dpll |= PLL_REF_INPUT_TVCLKINBC;
5010 else if (is_tv)
79e53945 5011 /* XXX: just matching BIOS for now */
43565a06 5012 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5013 dpll |= 3;
a7615030 5014 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5015 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5016 else
5017 dpll |= PLL_REF_INPUT_DREFCLK;
5018
5019 /* setup pipeconf */
5eddb70b 5020 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5021
5022 /* Set up the display plane register */
5023 dspcntr = DISPPLANE_GAMMA_ENABLE;
5024
28c97730 5025 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5026 drm_mode_debug_printmodeline(mode);
5027
5c5313c8
JB		 5028 /* PCH eDP needs FDI, but CPU eDP does not */
5029 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981
EA		 5030 I915_WRITE(PCH_FP0(pipe), fp);
5031 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5032
fae14981 5033 POSTING_READ(PCH_DPLL(pipe));
79e53945
JB		 5034 udelay(150);
5035 }
5036
8db9d77b
ZW		 5037 /* enable transcoder DPLL */
5038 if (HAS_PCH_CPT(dev)) {
5039 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5040 switch (pipe) {
5041 case 0:
5eddb70b 5042 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5043 break;
5044 case 1:
5eddb70b 5045 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5046 break;
5047 case 2:
5048 /* FIXME: manage transcoder PLLs? */
5049 temp |= TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL;
5050 break;
5051 default:
5052 BUG();
32f9d658 5053 }
8db9d77b 5054 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5055
5056 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5057 udelay(150);
5058 }
5059
79e53945
JB		 5060 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5061 * This is an exception to the general rule that mode_set doesn't turn
5062 * things on.
5063 */
5064 if (is_lvds) {
fae14981 5065 temp = I915_READ(PCH_LVDS);
5eddb70b 5066 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3
ZW		 5067 if (pipe == 1) {
5068 if (HAS_PCH_CPT(dev))
5eddb70b 5069 temp |= PORT_TRANS_B_SEL_CPT;
b3b095b3 5070 else
5eddb70b 5071 temp |= LVDS_PIPEB_SELECT;
b3b095b3
ZW		 5072 } else {
5073 if (HAS_PCH_CPT(dev))
5eddb70b 5074 temp &= ~PORT_TRANS_SEL_MASK;
b3b095b3 5075 else
5eddb70b 5076 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5077 }
a3e17eb8 5078 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5079 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5080 /* Set the B0-B3 data pairs corresponding to whether we're going to
5081 * set the DPLLs for dual-channel mode or not.
5082 */
5083 if (clock.p2 == 7)
5eddb70b 5084 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5085 else
5eddb70b 5086 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5087
5088 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5089 * appropriately here, but we need to look more thoroughly into how
5090 * panels behave in the two modes.
5091 */
aa9b500d
BF		 5092 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5093 lvds_sync |= LVDS_HSYNC_POLARITY;
5094 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5095 lvds_sync |= LVDS_VSYNC_POLARITY;
5096 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5097 != lvds_sync) {
5098 char flags[2] = "-+";
5099 DRM_INFO("Changing LVDS panel from "
5100 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5101 flags[!(temp & LVDS_HSYNC_POLARITY)],
5102 flags[!(temp & LVDS_VSYNC_POLARITY)],
5103 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5104 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5105 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5106 temp |= lvds_sync;
5107 }
fae14981 5108 I915_WRITE(PCH_LVDS, temp);
79e53945 5109 }
434ed097
JB		 5110
5111 /* set the dithering flag and clear for anything other than a panel. */
8febb297
EA		 5112 pipeconf &= ~PIPECONF_DITHER_EN;
5113 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5114 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
5115 pipeconf |= PIPECONF_DITHER_EN;
5116 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097
JB		 5117 }
5118
5c5313c8 5119 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5120 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5121 } else {
8db9d77b 5122 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5123 I915_WRITE(TRANSDATA_M1(pipe), 0);
5124 I915_WRITE(TRANSDATA_N1(pipe), 0);
5125 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5126 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5127 }
79e53945 5128
8febb297
EA		 5129 if (!has_edp_encoder ||
5130 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
fae14981 5131 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5132
32f9d658 5133 /* Wait for the clocks to stabilize. */
fae14981 5134 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5135 udelay(150);
5136
8febb297
EA		 5137 /* The pixel multiplier can only be updated once the
5138 * DPLL is enabled and the clocks are stable.
5139 *
5140 * So write it again.
5141 */
fae14981 5142 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5143 }
79e53945 5144
5eddb70b 5145 intel_crtc->lowfreq_avail = false;
652c393a 5146 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5147 I915_WRITE(PCH_FP1(pipe), fp2);
652c393a
JB		 5148 intel_crtc->lowfreq_avail = true;
5149 if (HAS_PIPE_CXSR(dev)) {
28c97730 5150 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5151 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5152 }
5153 } else {
fae14981 5154 I915_WRITE(PCH_FP1(pipe), fp);
652c393a 5155 if (HAS_PIPE_CXSR(dev)) {
28c97730 5156 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5157 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5158 }
5159 }
5160
734b4157
KH		 5161 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5162 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5163 /* the chip adds 2 halflines automatically */
5164 adjusted_mode->crtc_vdisplay -= 1;
5165 adjusted_mode->crtc_vtotal -= 1;
5166 adjusted_mode->crtc_vblank_start -= 1;
5167 adjusted_mode->crtc_vblank_end -= 1;
5168 adjusted_mode->crtc_vsync_end -= 1;
5169 adjusted_mode->crtc_vsync_start -= 1;
5170 } else
5171 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5172
5eddb70b
CW		 5173 I915_WRITE(HTOTAL(pipe),
5174 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5175 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5176 I915_WRITE(HBLANK(pipe),
5177 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5178 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5179 I915_WRITE(HSYNC(pipe),
5180 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5181 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5182
5183 I915_WRITE(VTOTAL(pipe),
5184 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5185 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5186 I915_WRITE(VBLANK(pipe),
5187 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5188 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5189 I915_WRITE(VSYNC(pipe),
5190 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5191 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5192
8febb297
EA		 5193 /* pipesrc controls the size that is scaled from, which should
5194 * always be the user's requested size.
79e53945 5195 */
5eddb70b
CW		 5196 I915_WRITE(PIPESRC(pipe),
5197 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5198
8febb297
EA		 5199 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5200 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5201 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5202 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5203
8febb297
EA		 5204 if (has_edp_encoder &&
5205 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5206 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5207 }
5208
5eddb70b
CW		 5209 I915_WRITE(PIPECONF(pipe), pipeconf);
5210 POSTING_READ(PIPECONF(pipe));
79e53945 5211
9d0498a2 5212 intel_wait_for_vblank(dev, pipe);
79e53945 5213
f00a3ddf 5214 if (IS_GEN5(dev)) {
553bd149
ZW		 5215 /* enable address swizzle for tiling buffer */
5216 temp = I915_READ(DISP_ARB_CTL);
5217 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5218 }
5219
5eddb70b 5220 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5221 POSTING_READ(DSPCNTR(plane));
79e53945 5222
5c3b82e2 5223 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5224
5225 intel_update_watermarks(dev);
5226
1f803ee5 5227 return ret;
79e53945
JB		 5228}
5229
f564048e
EA		 5230static int intel_crtc_mode_set(struct drm_crtc *crtc,
5231 struct drm_display_mode *mode,
5232 struct drm_display_mode *adjusted_mode,
5233 int x, int y,
5234 struct drm_framebuffer *old_fb)
5235{
5236 struct drm_device *dev = crtc->dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5239 int pipe = intel_crtc->pipe;
f564048e
EA		 5240 int ret;
5241
0b701d27 5242 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5243
f564048e
EA		 5244 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5245 x, y, old_fb);
7662c8bd 5246
79e53945 5247 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5248
1f803ee5 5249 return ret;
79e53945
JB		 5250}
5251
5252/** Loads the palette/gamma unit for the CRTC with the prepared values */
5253void intel_crtc_load_lut(struct drm_crtc *crtc)
5254{
5255 struct drm_device *dev = crtc->dev;
5256 struct drm_i915_private *dev_priv = dev->dev_private;
5257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5258 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5259 int i;
5260
5261 /* The clocks have to be on to load the palette. */
5262 if (!crtc->enabled)
5263 return;
5264
f2b115e6 5265 /* use legacy palette for Ironlake */
bad720ff 5266 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5267 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5268
79e53945
JB		 5269 for (i = 0; i < 256; i++) {
5270 I915_WRITE(palreg + 4 * i,
5271 (intel_crtc->lut_r[i] << 16) |
5272 (intel_crtc->lut_g[i] << 8) |
5273 intel_crtc->lut_b[i]);
5274 }
5275}
5276
560b85bb
CW		 5277static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5278{
5279 struct drm_device *dev = crtc->dev;
5280 struct drm_i915_private *dev_priv = dev->dev_private;
5281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5282 bool visible = base != 0;
5283 u32 cntl;
5284
5285 if (intel_crtc->cursor_visible == visible)
5286 return;
5287
9db4a9c7 5288 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5289 if (visible) {
5290 /* On these chipsets we can only modify the base whilst
5291 * the cursor is disabled.
5292 */
9db4a9c7 5293 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5294
5295 cntl &= ~(CURSOR_FORMAT_MASK);
5296 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5297 cntl |= CURSOR_ENABLE |
5298 CURSOR_GAMMA_ENABLE |
5299 CURSOR_FORMAT_ARGB;
5300 } else
5301 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5302 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5303
5304 intel_crtc->cursor_visible = visible;
5305}
5306
5307static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5308{
5309 struct drm_device *dev = crtc->dev;
5310 struct drm_i915_private *dev_priv = dev->dev_private;
5311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5312 int pipe = intel_crtc->pipe;
5313 bool visible = base != 0;
5314
5315 if (intel_crtc->cursor_visible != visible) {
548f245b 5316 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5317 if (base) {
5318 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5319 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5320 cntl |= pipe << 28; /* Connect to correct pipe */
5321 } else {
5322 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5323 cntl |= CURSOR_MODE_DISABLE;
5324 }
9db4a9c7 5325 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5326
5327 intel_crtc->cursor_visible = visible;
5328 }
5329 /* and commit changes on next vblank */
9db4a9c7 5330 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5331}
5332
cda4b7d3 5333/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5334static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5335 bool on)
cda4b7d3
CW		 5336{
5337 struct drm_device *dev = crtc->dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5340 int pipe = intel_crtc->pipe;
5341 int x = intel_crtc->cursor_x;
5342 int y = intel_crtc->cursor_y;
560b85bb 5343 u32 base, pos;
cda4b7d3
CW		 5344 bool visible;
5345
5346 pos = 0;
5347
6b383a7f 5348 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5349 base = intel_crtc->cursor_addr;
5350 if (x > (int) crtc->fb->width)
5351 base = 0;
5352
5353 if (y > (int) crtc->fb->height)
5354 base = 0;
5355 } else
5356 base = 0;
5357
5358 if (x < 0) {
5359 if (x + intel_crtc->cursor_width < 0)
5360 base = 0;
5361
5362 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5363 x = -x;
5364 }
5365 pos |= x << CURSOR_X_SHIFT;
5366
5367 if (y < 0) {
5368 if (y + intel_crtc->cursor_height < 0)
5369 base = 0;
5370
5371 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5372 y = -y;
5373 }
5374 pos |= y << CURSOR_Y_SHIFT;
5375
5376 visible = base != 0;
560b85bb 5377 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5378 return;
5379
9db4a9c7 5380 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 5381 if (IS_845G(dev) || IS_I865G(dev))
5382 i845_update_cursor(crtc, base);
5383 else
5384 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 5385
5386 if (visible)
5387 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
5388}
5389
79e53945 5390static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5391 struct drm_file *file,
79e53945
JB		 5392 uint32_t handle,
5393 uint32_t width, uint32_t height)
5394{
5395 struct drm_device *dev = crtc->dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5398 struct drm_i915_gem_object *obj;
cda4b7d3 5399 uint32_t addr;
3f8bc370 5400 int ret;
79e53945 5401
28c97730 5402 DRM_DEBUG_KMS("\n");
79e53945
JB		 5403
5404 /* if we want to turn off the cursor ignore width and height */
5405 if (!handle) {
28c97730 5406 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5407 addr = 0;
05394f39 5408 obj = NULL;
5004417d 5409 mutex_lock(&dev->struct_mutex);
3f8bc370 5410 goto finish;
79e53945
JB		 5411 }
5412
5413 /* Currently we only support 64x64 cursors */
5414 if (width != 64 || height != 64) {
5415 DRM_ERROR("we currently only support 64x64 cursors\n");
5416 return -EINVAL;
5417 }
5418
05394f39 5419 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5420 if (&obj->base == NULL)
79e53945
JB		 5421 return -ENOENT;
5422
05394f39 5423 if (obj->base.size < width * height * 4) {
79e53945 5424 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5425 ret = -ENOMEM;
5426 goto fail;
79e53945
JB		 5427 }
5428
71acb5eb 5429 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5430 mutex_lock(&dev->struct_mutex);
b295d1b6 5431 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5432 if (obj->tiling_mode) {
5433 DRM_ERROR("cursor cannot be tiled\n");
5434 ret = -EINVAL;
5435 goto fail_locked;
5436 }
5437
2da3b9b9 5438 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5439 if (ret) {
5440 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5441 goto fail_locked;
e7b526bb
CW		 5442 }
5443
d9e86c0e
CW		 5444 ret = i915_gem_object_put_fence(obj);
5445 if (ret) {
2da3b9b9 5446 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5447 goto fail_unpin;
5448 }
5449
05394f39 5450 addr = obj->gtt_offset;
71acb5eb 5451 } else {
6eeefaf3 5452 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5453 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5454 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5455 align);
71acb5eb
DA		 5456 if (ret) {
5457 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5458 goto fail_locked;
71acb5eb 5459 }
05394f39 5460 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5461 }
5462
a6c45cf0 5463 if (IS_GEN2(dev))
14b60391
JB		 5464 I915_WRITE(CURSIZE, (height << 12) | width);
5465
3f8bc370 5466 finish:
3f8bc370 5467 if (intel_crtc->cursor_bo) {
b295d1b6 5468 if (dev_priv->info->cursor_needs_physical) {
05394f39 5469 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5470 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5471 } else
5472 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5473 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5474 }
80824003 5475
7f9872e0 5476 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5477
5478 intel_crtc->cursor_addr = addr;
05394f39 5479 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5480 intel_crtc->cursor_width = width;
5481 intel_crtc->cursor_height = height;
5482
6b383a7f 5483 intel_crtc_update_cursor(crtc, true);
3f8bc370 5484
79e53945 5485 return 0;
e7b526bb 5486fail_unpin:
05394f39 5487 i915_gem_object_unpin(obj);
7f9872e0 5488fail_locked:
34b8686e 5489 mutex_unlock(&dev->struct_mutex);
bc9025bd 5490fail:
05394f39 5491 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5492 return ret;
79e53945
JB		 5493}
5494
5495static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5496{
79e53945 5497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5498
cda4b7d3
CW		 5499 intel_crtc->cursor_x = x;
5500 intel_crtc->cursor_y = y;
652c393a 5501
6b383a7f 5502 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5503
5504 return 0;
5505}
5506
5507/** Sets the color ramps on behalf of RandR */
5508void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5509 u16 blue, int regno)
5510{
5511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5512
5513 intel_crtc->lut_r[regno] = red >> 8;
5514 intel_crtc->lut_g[regno] = green >> 8;
5515 intel_crtc->lut_b[regno] = blue >> 8;
5516}
5517
b8c00ac5
DA		 5518void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5519 u16 *blue, int regno)
5520{
5521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5522
5523 *red = intel_crtc->lut_r[regno] << 8;
5524 *green = intel_crtc->lut_g[regno] << 8;
5525 *blue = intel_crtc->lut_b[regno] << 8;
5526}
5527
79e53945 5528static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5529 u16 *blue, uint32_t start, uint32_t size)
79e53945 5530{
7203425a 5531 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5532 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5533
7203425a 5534 for (i = start; i < end; i++) {
79e53945
JB		 5535 intel_crtc->lut_r[i] = red[i] >> 8;
5536 intel_crtc->lut_g[i] = green[i] >> 8;
5537 intel_crtc->lut_b[i] = blue[i] >> 8;
5538 }
5539
5540 intel_crtc_load_lut(crtc);
5541}
5542
5543/**
5544 * Get a pipe with a simple mode set on it for doing load-based monitor
5545 * detection.
5546 *
5547 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5548 * its requirements. The pipe will be connected to no other encoders.
79e53945 5549 *
c751ce4f 5550 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5551 * configured for it. In the future, it could choose to temporarily disable
5552 * some outputs to free up a pipe for its use.
5553 *
5554 * \return crtc, or NULL if no pipes are available.
5555 */
5556
5557/* VESA 640x480x72Hz mode to set on the pipe */
5558static struct drm_display_mode load_detect_mode = {
5559 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5560 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5561};
5562
d2dff872
CW		 5563static struct drm_framebuffer *
5564intel_framebuffer_create(struct drm_device *dev,
5565 struct drm_mode_fb_cmd *mode_cmd,
5566 struct drm_i915_gem_object *obj)
5567{
5568 struct intel_framebuffer *intel_fb;
5569 int ret;
5570
5571 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5572 if (!intel_fb) {
5573 drm_gem_object_unreference_unlocked(&obj->base);
5574 return ERR_PTR(-ENOMEM);
5575 }
5576
5577 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5578 if (ret) {
5579 drm_gem_object_unreference_unlocked(&obj->base);
5580 kfree(intel_fb);
5581 return ERR_PTR(ret);
5582 }
5583
5584 return &intel_fb->base;
5585}
5586
5587static u32
5588intel_framebuffer_pitch_for_width(int width, int bpp)
5589{
5590 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5591 return ALIGN(pitch, 64);
5592}
5593
5594static u32
5595intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5596{
5597 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5598 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5599}
5600
5601static struct drm_framebuffer *
5602intel_framebuffer_create_for_mode(struct drm_device *dev,
5603 struct drm_display_mode *mode,
5604 int depth, int bpp)
5605{
5606 struct drm_i915_gem_object *obj;
5607 struct drm_mode_fb_cmd mode_cmd;
5608
5609 obj = i915_gem_alloc_object(dev,
5610 intel_framebuffer_size_for_mode(mode, bpp));
5611 if (obj == NULL)
5612 return ERR_PTR(-ENOMEM);
5613
5614 mode_cmd.width = mode->hdisplay;
5615 mode_cmd.height = mode->vdisplay;
5616 mode_cmd.depth = depth;
5617 mode_cmd.bpp = bpp;
5618 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
5619
5620 return intel_framebuffer_create(dev, &mode_cmd, obj);
5621}
5622
5623static struct drm_framebuffer *
5624mode_fits_in_fbdev(struct drm_device *dev,
5625 struct drm_display_mode *mode)
5626{
5627 struct drm_i915_private *dev_priv = dev->dev_private;
5628 struct drm_i915_gem_object *obj;
5629 struct drm_framebuffer *fb;
5630
5631 if (dev_priv->fbdev == NULL)
5632 return NULL;
5633
5634 obj = dev_priv->fbdev->ifb.obj;
5635 if (obj == NULL)
5636 return NULL;
5637
5638 fb = &dev_priv->fbdev->ifb.base;
5639 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
5640 fb->bits_per_pixel))
5641 return NULL;
5642
5643 if (obj->base.size < mode->vdisplay * fb->pitch)
5644 return NULL;
5645
5646 return fb;
5647}
5648
7173188d
CW		 5649bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5650 struct drm_connector *connector,
5651 struct drm_display_mode *mode,
8261b191 5652 struct intel_load_detect_pipe *old)
79e53945
JB		 5653{
5654 struct intel_crtc *intel_crtc;
5655 struct drm_crtc *possible_crtc;
4ef69c7a 5656 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5657 struct drm_crtc *crtc = NULL;
5658 struct drm_device *dev = encoder->dev;
d2dff872 5659 struct drm_framebuffer *old_fb;
79e53945
JB		 5660 int i = -1;
5661
d2dff872
CW		 5662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5663 connector->base.id, drm_get_connector_name(connector),
5664 encoder->base.id, drm_get_encoder_name(encoder));
5665
79e53945
JB		 5666 /*
5667 * Algorithm gets a little messy:
7a5e4805 5668 *
79e53945
JB		 5669 * - if the connector already has an assigned crtc, use it (but make
5670 * sure it's on first)
7a5e4805 5671 *
79e53945
JB		 5672 * - try to find the first unused crtc that can drive this connector,
5673 * and use that if we find one
79e53945
JB		 5674 */
5675
5676 /* See if we already have a CRTC for this connector */
5677 if (encoder->crtc) {
5678 crtc = encoder->crtc;
8261b191 5679
79e53945 5680 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5681 old->dpms_mode = intel_crtc->dpms_mode;
5682 old->load_detect_temp = false;
5683
5684 /* Make sure the crtc and connector are running */
79e53945 5685 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5686 struct drm_encoder_helper_funcs *encoder_funcs;
5687 struct drm_crtc_helper_funcs *crtc_funcs;
5688
79e53945
JB		 5689 crtc_funcs = crtc->helper_private;
5690 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5691
5692 encoder_funcs = encoder->helper_private;
79e53945
JB		 5693 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5694 }
8261b191 5695
7173188d 5696 return true;
79e53945
JB		 5697 }
5698
5699 /* Find an unused one (if possible) */
5700 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5701 i++;
5702 if (!(encoder->possible_crtcs & (1 << i)))
5703 continue;
5704 if (!possible_crtc->enabled) {
5705 crtc = possible_crtc;
5706 break;
5707 }
79e53945
JB		 5708 }
5709
5710 /*
5711 * If we didn't find an unused CRTC, don't use any.
5712 */
5713 if (!crtc) {
7173188d
CW		 5714 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5715 return false;
79e53945
JB		 5716 }
5717
5718 encoder->crtc = crtc;
c1c43977 5719 connector->encoder = encoder;
79e53945
JB		 5720
5721 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5722 old->dpms_mode = intel_crtc->dpms_mode;
5723 old->load_detect_temp = true;
d2dff872 5724 old->release_fb = NULL;
79e53945 5725
6492711d
CW		 5726 if (!mode)
5727 mode = &load_detect_mode;
79e53945 5728
d2dff872
CW		 5729 old_fb = crtc->fb;
5730
5731 /* We need a framebuffer large enough to accommodate all accesses
5732 * that the plane may generate whilst we perform load detection.
5733 * We can not rely on the fbcon either being present (we get called
5734 * during its initialisation to detect all boot displays, or it may
5735 * not even exist) or that it is large enough to satisfy the
5736 * requested mode.
5737 */
5738 crtc->fb = mode_fits_in_fbdev(dev, mode);
5739 if (crtc->fb == NULL) {
5740 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5741 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5742 old->release_fb = crtc->fb;
5743 } else
5744 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5745 if (IS_ERR(crtc->fb)) {
5746 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5747 crtc->fb = old_fb;
5748 return false;
79e53945 5749 }
79e53945 5750
d2dff872 5751 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5752 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5753 if (old->release_fb)
5754 old->release_fb->funcs->destroy(old->release_fb);
5755 crtc->fb = old_fb;
6492711d 5756 return false;
79e53945 5757 }
7173188d 5758
79e53945 5759 /* let the connector get through one full cycle before testing */
9d0498a2 5760 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5761
7173188d 5762 return true;
79e53945
JB		 5763}
5764
c1c43977 5765void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5766 struct drm_connector *connector,
5767 struct intel_load_detect_pipe *old)
79e53945 5768{
4ef69c7a 5769 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5770 struct drm_device *dev = encoder->dev;
5771 struct drm_crtc *crtc = encoder->crtc;
5772 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5773 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5774
d2dff872
CW		 5775 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5776 connector->base.id, drm_get_connector_name(connector),
5777 encoder->base.id, drm_get_encoder_name(encoder));
5778
8261b191 5779 if (old->load_detect_temp) {
c1c43977 5780 connector->encoder = NULL;
79e53945 5781 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5782
5783 if (old->release_fb)
5784 old->release_fb->funcs->destroy(old->release_fb);
5785
0622a53c 5786 return;
79e53945
JB		 5787 }
5788
c751ce4f 5789 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5790 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5791 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5792 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5793 }
5794}
5795
5796/* Returns the clock of the currently programmed mode of the given pipe. */
5797static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5798{
5799 struct drm_i915_private *dev_priv = dev->dev_private;
5800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5801 int pipe = intel_crtc->pipe;
548f245b 5802 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5803 u32 fp;
5804 intel_clock_t clock;
5805
5806 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5807 fp = I915_READ(FP0(pipe));
79e53945 5808 else
39adb7a5 5809 fp = I915_READ(FP1(pipe));
79e53945
JB		 5810
5811 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5812 if (IS_PINEVIEW(dev)) {
5813 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5814 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5815 } else {
5816 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5817 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5818 }
5819
a6c45cf0 5820 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5821 if (IS_PINEVIEW(dev))
5822 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5823 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5824 else
5825 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5826 DPLL_FPA01_P1_POST_DIV_SHIFT);
5827
5828 switch (dpll & DPLL_MODE_MASK) {
5829 case DPLLB_MODE_DAC_SERIAL:
5830 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5831 5 : 10;
5832 break;
5833 case DPLLB_MODE_LVDS:
5834 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5835 7 : 14;
5836 break;
5837 default:
28c97730 5838 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5839 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5840 return 0;
5841 }
5842
5843 /* XXX: Handle the 100Mhz refclk */
2177832f 5844 intel_clock(dev, 96000, &clock);
79e53945
JB		 5845 } else {
5846 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5847
5848 if (is_lvds) {
5849 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5850 DPLL_FPA01_P1_POST_DIV_SHIFT);
5851 clock.p2 = 14;
5852
5853 if ((dpll & PLL_REF_INPUT_MASK) ==
5854 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5855 /* XXX: might not be 66MHz */
2177832f 5856 intel_clock(dev, 66000, &clock);
79e53945 5857 } else
2177832f 5858 intel_clock(dev, 48000, &clock);
79e53945
JB		 5859 } else {
5860 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5861 clock.p1 = 2;
5862 else {
5863 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5864 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5865 }
5866 if (dpll & PLL_P2_DIVIDE_BY_4)
5867 clock.p2 = 4;
5868 else
5869 clock.p2 = 2;
5870
2177832f 5871 intel_clock(dev, 48000, &clock);
79e53945
JB		 5872 }
5873 }
5874
5875 /* XXX: It would be nice to validate the clocks, but we can't reuse
5876 * i830PllIsValid() because it relies on the xf86_config connector
5877 * configuration being accurate, which it isn't necessarily.
5878 */
5879
5880 return clock.dot;
5881}
5882
5883/** Returns the currently programmed mode of the given pipe. */
5884struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5885 struct drm_crtc *crtc)
5886{
548f245b 5887 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5889 int pipe = intel_crtc->pipe;
5890 struct drm_display_mode *mode;
548f245b
JB		 5891 int htot = I915_READ(HTOTAL(pipe));
5892 int hsync = I915_READ(HSYNC(pipe));
5893 int vtot = I915_READ(VTOTAL(pipe));
5894 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5895
5896 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5897 if (!mode)
5898 return NULL;
5899
5900 mode->clock = intel_crtc_clock_get(dev, crtc);
5901 mode->hdisplay = (htot & 0xffff) + 1;
5902 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5903 mode->hsync_start = (hsync & 0xffff) + 1;
5904 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5905 mode->vdisplay = (vtot & 0xffff) + 1;
5906 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5907 mode->vsync_start = (vsync & 0xffff) + 1;
5908 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5909
5910 drm_mode_set_name(mode);
5911 drm_mode_set_crtcinfo(mode, 0);
5912
5913 return mode;
5914}
5915
652c393a
JB		 5916#define GPU_IDLE_TIMEOUT 500 /* ms */
5917
5918/* When this timer fires, we've been idle for awhile */
5919static void intel_gpu_idle_timer(unsigned long arg)
5920{
5921 struct drm_device *dev = (struct drm_device *)arg;
5922 drm_i915_private_t *dev_priv = dev->dev_private;
5923
ff7ea4c0
CW		 5924 if (!list_empty(&dev_priv->mm.active_list)) {
5925 /* Still processing requests, so just re-arm the timer. */
5926 mod_timer(&dev_priv->idle_timer, jiffies +
5927 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5928 return;
5929 }
652c393a 5930
ff7ea4c0 5931 dev_priv->busy = false;
01dfba93 5932 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5933}
5934
652c393a
JB		 5935#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5936
5937static void intel_crtc_idle_timer(unsigned long arg)
5938{
5939 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5940 struct drm_crtc *crtc = &intel_crtc->base;
5941 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5942 struct intel_framebuffer *intel_fb;
652c393a 5943
ff7ea4c0
CW		 5944 intel_fb = to_intel_framebuffer(crtc->fb);
5945 if (intel_fb && intel_fb->obj->active) {
5946 /* The framebuffer is still being accessed by the GPU. */
5947 mod_timer(&intel_crtc->idle_timer, jiffies +
5948 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5949 return;
5950 }
652c393a 5951
ff7ea4c0 5952 intel_crtc->busy = false;
01dfba93 5953 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5954}
5955
3dec0095 5956static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5957{
5958 struct drm_device *dev = crtc->dev;
5959 drm_i915_private_t *dev_priv = dev->dev_private;
5960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5961 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5962 int dpll_reg = DPLL(pipe);
5963 int dpll;
652c393a 5964
bad720ff 5965 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5966 return;
5967
5968 if (!dev_priv->lvds_downclock_avail)
5969 return;
5970
dbdc6479 5971 dpll = I915_READ(dpll_reg);
652c393a 5972 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5973 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 5974
5975 /* Unlock panel regs */
dbdc6479
JB		 5976 I915_WRITE(PP_CONTROL,
5977 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 5978
5979 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5980 I915_WRITE(dpll_reg, dpll);
9d0498a2 5981 intel_wait_for_vblank(dev, pipe);
dbdc6479 5982
652c393a
JB		 5983 dpll = I915_READ(dpll_reg);
5984 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5985 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5986
5987 /* ...and lock them again */
5988 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5989 }
5990
5991 /* Schedule downclock */
3dec0095
DV		 5992 mod_timer(&intel_crtc->idle_timer, jiffies +
5993 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5994}
5995
5996static void intel_decrease_pllclock(struct drm_crtc *crtc)
5997{
5998 struct drm_device *dev = crtc->dev;
5999 drm_i915_private_t *dev_priv = dev->dev_private;
6000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6001 int pipe = intel_crtc->pipe;
9db4a9c7 6002 int dpll_reg = DPLL(pipe);
652c393a
JB		 6003 int dpll = I915_READ(dpll_reg);
6004
bad720ff 6005 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6006 return;
6007
6008 if (!dev_priv->lvds_downclock_avail)
6009 return;
6010
6011 /*
6012 * Since this is called by a timer, we should never get here in
6013 * the manual case.
6014 */
6015 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6016 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6017
6018 /* Unlock panel regs */
4a655f04
JB		 6019 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6020 PANEL_UNLOCK_REGS);
652c393a
JB		 6021
6022 dpll |= DISPLAY_RATE_SELECT_FPA1;
6023 I915_WRITE(dpll_reg, dpll);
9d0498a2 6024 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6025 dpll = I915_READ(dpll_reg);
6026 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6027 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6028
6029 /* ...and lock them again */
6030 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6031 }
6032
6033}
6034
6035/**
6036 * intel_idle_update - adjust clocks for idleness
6037 * @work: work struct
6038 *
6039 * Either the GPU or display (or both) went idle. Check the busy status
6040 * here and adjust the CRTC and GPU clocks as necessary.
6041 */
6042static void intel_idle_update(struct work_struct *work)
6043{
6044 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6045 idle_work);
6046 struct drm_device *dev = dev_priv->dev;
6047 struct drm_crtc *crtc;
6048 struct intel_crtc *intel_crtc;
6049
6050 if (!i915_powersave)
6051 return;
6052
6053 mutex_lock(&dev->struct_mutex);
6054
7648fa99
JB		 6055 i915_update_gfx_val(dev_priv);
6056
652c393a
JB		 6057 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6058 /* Skip inactive CRTCs */
6059 if (!crtc->fb)
6060 continue;
6061
6062 intel_crtc = to_intel_crtc(crtc);
6063 if (!intel_crtc->busy)
6064 intel_decrease_pllclock(crtc);
6065 }
6066
45ac22c8 6067
652c393a
JB		 6068 mutex_unlock(&dev->struct_mutex);
6069}
6070
6071/**
6072 * intel_mark_busy - mark the GPU and possibly the display busy
6073 * @dev: drm device
6074 * @obj: object we're operating on
6075 *
6076 * Callers can use this function to indicate that the GPU is busy processing
6077 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6078 * buffer), we'll also mark the display as busy, so we know to increase its
6079 * clock frequency.
6080 */
05394f39 6081void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6082{
6083 drm_i915_private_t *dev_priv = dev->dev_private;
6084 struct drm_crtc *crtc = NULL;
6085 struct intel_framebuffer *intel_fb;
6086 struct intel_crtc *intel_crtc;
6087
5e17ee74
ZW		 6088 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6089 return;
6090
18b2190c 6091 if (!dev_priv->busy)
28cf798f 6092 dev_priv->busy = true;
18b2190c 6093 else
28cf798f
CW		 6094 mod_timer(&dev_priv->idle_timer, jiffies +
6095 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6096
6097 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6098 if (!crtc->fb)
6099 continue;
6100
6101 intel_crtc = to_intel_crtc(crtc);
6102 intel_fb = to_intel_framebuffer(crtc->fb);
6103 if (intel_fb->obj == obj) {
6104 if (!intel_crtc->busy) {
6105 /* Non-busy -> busy, upclock */
3dec0095 6106 intel_increase_pllclock(crtc);
652c393a
JB		 6107 intel_crtc->busy = true;
6108 } else {
6109 /* Busy -> busy, put off timer */
6110 mod_timer(&intel_crtc->idle_timer, jiffies +
6111 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6112 }
6113 }
6114 }
6115}
6116
79e53945
JB		 6117static void intel_crtc_destroy(struct drm_crtc *crtc)
6118{
6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6120 struct drm_device *dev = crtc->dev;
6121 struct intel_unpin_work *work;
6122 unsigned long flags;
6123
6124 spin_lock_irqsave(&dev->event_lock, flags);
6125 work = intel_crtc->unpin_work;
6126 intel_crtc->unpin_work = NULL;
6127 spin_unlock_irqrestore(&dev->event_lock, flags);
6128
6129 if (work) {
6130 cancel_work_sync(&work->work);
6131 kfree(work);
6132 }
79e53945
JB		 6133
6134 drm_crtc_cleanup(crtc);
67e77c5a 6135
79e53945
JB		 6136 kfree(intel_crtc);
6137}
6138
6b95a207
KH		 6139static void intel_unpin_work_fn(struct work_struct *__work)
6140{
6141 struct intel_unpin_work *work =
6142 container_of(__work, struct intel_unpin_work, work);
6143
6144 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6145 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6146 drm_gem_object_unreference(&work->pending_flip_obj->base);
6147 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6148
6b95a207
KH		 6149 mutex_unlock(&work->dev->struct_mutex);
6150 kfree(work);
6151}
6152
1afe3e9d 6153static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6154 struct drm_crtc *crtc)
6b95a207
KH		 6155{
6156 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6158 struct intel_unpin_work *work;
05394f39 6159 struct drm_i915_gem_object *obj;
6b95a207 6160 struct drm_pending_vblank_event *e;
49b14a5c 6161 struct timeval tnow, tvbl;
6b95a207
KH		 6162 unsigned long flags;
6163
6164 /* Ignore early vblank irqs */
6165 if (intel_crtc == NULL)
6166 return;
6167
49b14a5c
MK		 6168 do_gettimeofday(&tnow);
6169
6b95a207
KH		 6170 spin_lock_irqsave(&dev->event_lock, flags);
6171 work = intel_crtc->unpin_work;
6172 if (work == NULL || !work->pending) {
6173 spin_unlock_irqrestore(&dev->event_lock, flags);
6174 return;
6175 }
6176
6177 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6178
6179 if (work->event) {
6180 e = work->event;
49b14a5c 6181 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6182
6183 /* Called before vblank count and timestamps have
6184 * been updated for the vblank interval of flip
6185 * completion? Need to increment vblank count and
6186 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6187 * to account for this. We assume this happened if we
6188 * get called over 0.9 frame durations after the last
6189 * timestamped vblank.
6190 *
6191 * This calculation can not be used with vrefresh rates
6192 * below 5Hz (10Hz to be on the safe side) without
6193 * promoting to 64 integers.
0af7e4df 6194 */
49b14a5c
MK		 6195 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6196 9 * crtc->framedur_ns) {
0af7e4df 6197 e->event.sequence++;
49b14a5c
MK		 6198 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6199 crtc->framedur_ns);
0af7e4df
MK		 6200 }
6201
49b14a5c
MK		 6202 e->event.tv_sec = tvbl.tv_sec;
6203 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6204
6b95a207
KH		 6205 list_add_tail(&e->base.link,
6206 &e->base.file_priv->event_list);
6207 wake_up_interruptible(&e->base.file_priv->event_wait);
6208 }
6209
0af7e4df
MK		 6210 drm_vblank_put(dev, intel_crtc->pipe);
6211
6b95a207
KH		 6212 spin_unlock_irqrestore(&dev->event_lock, flags);
6213
05394f39 6214 obj = work->old_fb_obj;
d9e86c0e 6215
e59f2bac 6216 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6217 &obj->pending_flip.counter);
6218 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6219 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6220
6b95a207 6221 schedule_work(&work->work);
e5510fac
JB		 6222
6223 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6224}
6225
1afe3e9d
JB		 6226void intel_finish_page_flip(struct drm_device *dev, int pipe)
6227{
6228 drm_i915_private_t *dev_priv = dev->dev_private;
6229 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6230
49b14a5c 6231 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6232}
6233
6234void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6235{
6236 drm_i915_private_t *dev_priv = dev->dev_private;
6237 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6238
49b14a5c 6239 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6240}
6241
6b95a207
KH		 6242void intel_prepare_page_flip(struct drm_device *dev, int plane)
6243{
6244 drm_i915_private_t *dev_priv = dev->dev_private;
6245 struct intel_crtc *intel_crtc =
6246 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6247 unsigned long flags;
6248
6249 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6250 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6251 if ((++intel_crtc->unpin_work->pending) > 1)
6252 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6253 } else {
6254 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6255 }
6b95a207
KH		 6256 spin_unlock_irqrestore(&dev->event_lock, flags);
6257}
6258
8c9f3aaf
JB		 6259static int intel_gen2_queue_flip(struct drm_device *dev,
6260 struct drm_crtc *crtc,
6261 struct drm_framebuffer *fb,
6262 struct drm_i915_gem_object *obj)
6263{
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6266 unsigned long offset;
6267 u32 flip_mask;
6268 int ret;
6269
6270 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6271 if (ret)
6272 goto out;
6273
6274 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6275 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6276
6277 ret = BEGIN_LP_RING(6);
6278 if (ret)
6279 goto out;
6280
6281 /* Can't queue multiple flips, so wait for the previous
6282 * one to finish before executing the next.
6283 */
6284 if (intel_crtc->plane)
6285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6286 else
6287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6288 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6289 OUT_RING(MI_NOOP);
6290 OUT_RING(MI_DISPLAY_FLIP |
6291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6292 OUT_RING(fb->pitch);
6293 OUT_RING(obj->gtt_offset + offset);
6294 OUT_RING(MI_NOOP);
6295 ADVANCE_LP_RING();
6296out:
6297 return ret;
6298}
6299
6300static int intel_gen3_queue_flip(struct drm_device *dev,
6301 struct drm_crtc *crtc,
6302 struct drm_framebuffer *fb,
6303 struct drm_i915_gem_object *obj)
6304{
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307 unsigned long offset;
6308 u32 flip_mask;
6309 int ret;
6310
6311 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6312 if (ret)
6313 goto out;
6314
6315 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6316 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6317
6318 ret = BEGIN_LP_RING(6);
6319 if (ret)
6320 goto out;
6321
6322 if (intel_crtc->plane)
6323 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6324 else
6325 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6326 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6327 OUT_RING(MI_NOOP);
6328 OUT_RING(MI_DISPLAY_FLIP_I915 |
6329 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6330 OUT_RING(fb->pitch);
6331 OUT_RING(obj->gtt_offset + offset);
6332 OUT_RING(MI_NOOP);
6333
6334 ADVANCE_LP_RING();
6335out:
6336 return ret;
6337}
6338
6339static int intel_gen4_queue_flip(struct drm_device *dev,
6340 struct drm_crtc *crtc,
6341 struct drm_framebuffer *fb,
6342 struct drm_i915_gem_object *obj)
6343{
6344 struct drm_i915_private *dev_priv = dev->dev_private;
6345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6346 uint32_t pf, pipesrc;
6347 int ret;
6348
6349 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6350 if (ret)
6351 goto out;
6352
6353 ret = BEGIN_LP_RING(4);
6354 if (ret)
6355 goto out;
6356
6357 /* i965+ uses the linear or tiled offsets from the
6358 * Display Registers (which do not change across a page-flip)
6359 * so we need only reprogram the base address.
6360 */
6361 OUT_RING(MI_DISPLAY_FLIP |
6362 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6363 OUT_RING(fb->pitch);
6364 OUT_RING(obj->gtt_offset | obj->tiling_mode);
6365
6366 /* XXX Enabling the panel-fitter across page-flip is so far
6367 * untested on non-native modes, so ignore it for now.
6368 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6369 */
6370 pf = 0;
6371 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6372 OUT_RING(pf | pipesrc);
6373 ADVANCE_LP_RING();
6374out:
6375 return ret;
6376}
6377
6378static int intel_gen6_queue_flip(struct drm_device *dev,
6379 struct drm_crtc *crtc,
6380 struct drm_framebuffer *fb,
6381 struct drm_i915_gem_object *obj)
6382{
6383 struct drm_i915_private *dev_priv = dev->dev_private;
6384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6385 uint32_t pf, pipesrc;
6386 int ret;
6387
6388 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6389 if (ret)
6390 goto out;
6391
6392 ret = BEGIN_LP_RING(4);
6393 if (ret)
6394 goto out;
6395
6396 OUT_RING(MI_DISPLAY_FLIP |
6397 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6398 OUT_RING(fb->pitch | obj->tiling_mode);
6399 OUT_RING(obj->gtt_offset);
6400
6401 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6402 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6403 OUT_RING(pf | pipesrc);
6404 ADVANCE_LP_RING();
6405out:
6406 return ret;
6407}
6408
7c9017e5
JB		 6409/*
6410 * On gen7 we currently use the blit ring because (in early silicon at least)
6411 * the render ring doesn't give us interrpts for page flip completion, which
6412 * means clients will hang after the first flip is queued. Fortunately the
6413 * blit ring generates interrupts properly, so use it instead.
6414 */
6415static int intel_gen7_queue_flip(struct drm_device *dev,
6416 struct drm_crtc *crtc,
6417 struct drm_framebuffer *fb,
6418 struct drm_i915_gem_object *obj)
6419{
6420 struct drm_i915_private *dev_priv = dev->dev_private;
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6423 int ret;
6424
6425 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6426 if (ret)
6427 goto out;
6428
6429 ret = intel_ring_begin(ring, 4);
6430 if (ret)
6431 goto out;
6432
6433 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
6434 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
6435 intel_ring_emit(ring, (obj->gtt_offset));
6436 intel_ring_emit(ring, (MI_NOOP));
6437 intel_ring_advance(ring);
6438out:
6439 return ret;
6440}
6441
8c9f3aaf
JB		 6442static int intel_default_queue_flip(struct drm_device *dev,
6443 struct drm_crtc *crtc,
6444 struct drm_framebuffer *fb,
6445 struct drm_i915_gem_object *obj)
6446{
6447 return -ENODEV;
6448}
6449
6b95a207
KH		 6450static int intel_crtc_page_flip(struct drm_crtc *crtc,
6451 struct drm_framebuffer *fb,
6452 struct drm_pending_vblank_event *event)
6453{
6454 struct drm_device *dev = crtc->dev;
6455 struct drm_i915_private *dev_priv = dev->dev_private;
6456 struct intel_framebuffer *intel_fb;
05394f39 6457 struct drm_i915_gem_object *obj;
6b95a207
KH		 6458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6459 struct intel_unpin_work *work;
8c9f3aaf 6460 unsigned long flags;
52e68630 6461 int ret;
6b95a207
KH		 6462
6463 work = kzalloc(sizeof *work, GFP_KERNEL);
6464 if (work == NULL)
6465 return -ENOMEM;
6466
6b95a207
KH		 6467 work->event = event;
6468 work->dev = crtc->dev;
6469 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6470 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6471 INIT_WORK(&work->work, intel_unpin_work_fn);
6472
6473 /* We borrow the event spin lock for protecting unpin_work */
6474 spin_lock_irqsave(&dev->event_lock, flags);
6475 if (intel_crtc->unpin_work) {
6476 spin_unlock_irqrestore(&dev->event_lock, flags);
6477 kfree(work);
468f0b44
CW		 6478
6479 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6480 return -EBUSY;
6481 }
6482 intel_crtc->unpin_work = work;
6483 spin_unlock_irqrestore(&dev->event_lock, flags);
6484
6485 intel_fb = to_intel_framebuffer(fb);
6486 obj = intel_fb->obj;
6487
468f0b44 6488 mutex_lock(&dev->struct_mutex);
6b95a207 6489
75dfca80 6490 /* Reference the objects for the scheduled work. */
05394f39
CW		 6491 drm_gem_object_reference(&work->old_fb_obj->base);
6492 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6493
6494 crtc->fb = fb;
96b099fd
CW		 6495
6496 ret = drm_vblank_get(dev, intel_crtc->pipe);
6497 if (ret)
6498 goto cleanup_objs;
6499
e1f99ce6 6500 work->pending_flip_obj = obj;
e1f99ce6 6501
4e5359cd
SF		 6502 work->enable_stall_check = true;
6503
e1f99ce6
CW		 6504 /* Block clients from rendering to the new back buffer until
6505 * the flip occurs and the object is no longer visible.
6506 */
05394f39 6507 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6508
8c9f3aaf
JB		 6509 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6510 if (ret)
6511 goto cleanup_pending;
6b95a207
KH		 6512
6513 mutex_unlock(&dev->struct_mutex);
6514
e5510fac
JB		 6515 trace_i915_flip_request(intel_crtc->plane, obj);
6516
6b95a207 6517 return 0;
96b099fd 6518
8c9f3aaf
JB		 6519cleanup_pending:
6520 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 6521cleanup_objs:
05394f39
CW		 6522 drm_gem_object_unreference(&work->old_fb_obj->base);
6523 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6524 mutex_unlock(&dev->struct_mutex);
6525
6526 spin_lock_irqsave(&dev->event_lock, flags);
6527 intel_crtc->unpin_work = NULL;
6528 spin_unlock_irqrestore(&dev->event_lock, flags);
6529
6530 kfree(work);
6531
6532 return ret;
6b95a207
KH		 6533}
6534
47f1c6c9
CW		 6535static void intel_sanitize_modesetting(struct drm_device *dev,
6536 int pipe, int plane)
6537{
6538 struct drm_i915_private *dev_priv = dev->dev_private;
6539 u32 reg, val;
6540
6541 if (HAS_PCH_SPLIT(dev))
6542 return;
6543
6544 /* Who knows what state these registers were left in by the BIOS or
6545 * grub?
6546 *
6547 * If we leave the registers in a conflicting state (e.g. with the
6548 * display plane reading from the other pipe than the one we intend
6549 * to use) then when we attempt to teardown the active mode, we will
6550 * not disable the pipes and planes in the correct order -- leaving
6551 * a plane reading from a disabled pipe and possibly leading to
6552 * undefined behaviour.
6553 */
6554
6555 reg = DSPCNTR(plane);
6556 val = I915_READ(reg);
6557
6558 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6559 return;
6560 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6561 return;
6562
6563 /* This display plane is active and attached to the other CPU pipe. */
6564 pipe = !pipe;
6565
6566 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6567 intel_disable_plane(dev_priv, plane, pipe);
6568 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6569}
79e53945 6570
f6e5b160
CW		 6571static void intel_crtc_reset(struct drm_crtc *crtc)
6572{
6573 struct drm_device *dev = crtc->dev;
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575
6576 /* Reset flags back to the 'unknown' status so that they
6577 * will be correctly set on the initial modeset.
6578 */
6579 intel_crtc->dpms_mode = -1;
6580
6581 /* We need to fix up any BIOS configuration that conflicts with
6582 * our expectations.
6583 */
6584 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6585}
6586
6587static struct drm_crtc_helper_funcs intel_helper_funcs = {
6588 .dpms = intel_crtc_dpms,
6589 .mode_fixup = intel_crtc_mode_fixup,
6590 .mode_set = intel_crtc_mode_set,
6591 .mode_set_base = intel_pipe_set_base,
6592 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6593 .load_lut = intel_crtc_load_lut,
6594 .disable = intel_crtc_disable,
6595};
6596
6597static const struct drm_crtc_funcs intel_crtc_funcs = {
6598 .reset = intel_crtc_reset,
6599 .cursor_set = intel_crtc_cursor_set,
6600 .cursor_move = intel_crtc_cursor_move,
6601 .gamma_set = intel_crtc_gamma_set,
6602 .set_config = drm_crtc_helper_set_config,
6603 .destroy = intel_crtc_destroy,
6604 .page_flip = intel_crtc_page_flip,
6605};
6606
b358d0a6 6607static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6608{
22fd0fab 6609 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6610 struct intel_crtc *intel_crtc;
6611 int i;
6612
6613 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6614 if (intel_crtc == NULL)
6615 return;
6616
6617 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6618
6619 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6620 for (i = 0; i < 256; i++) {
6621 intel_crtc->lut_r[i] = i;
6622 intel_crtc->lut_g[i] = i;
6623 intel_crtc->lut_b[i] = i;
6624 }
6625
80824003
JB		 6626 /* Swap pipes & planes for FBC on pre-965 */
6627 intel_crtc->pipe = pipe;
6628 intel_crtc->plane = pipe;
e2e767ab 6629 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6630 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6631 intel_crtc->plane = !pipe;
80824003
JB		 6632 }
6633
22fd0fab
JB		 6634 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6635 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6636 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6637 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6638
5d1d0cc8 6639 intel_crtc_reset(&intel_crtc->base);
04dbff52 6640 intel_crtc->active = true; /* force the pipe off on setup_init_config */
7e7d76c3
JB		 6641
6642 if (HAS_PCH_SPLIT(dev)) {
6643 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6644 intel_helper_funcs.commit = ironlake_crtc_commit;
6645 } else {
6646 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6647 intel_helper_funcs.commit = i9xx_crtc_commit;
6648 }
6649
79e53945
JB		 6650 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6651
652c393a
JB		 6652 intel_crtc->busy = false;
6653
6654 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6655 (unsigned long)intel_crtc);
79e53945
JB		 6656}
6657
08d7b3d1 6658int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6659 struct drm_file *file)
08d7b3d1
CW		 6660{
6661 drm_i915_private_t *dev_priv = dev->dev_private;
6662 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6663 struct drm_mode_object *drmmode_obj;
6664 struct intel_crtc *crtc;
08d7b3d1
CW		 6665
6666 if (!dev_priv) {
6667 DRM_ERROR("called with no initialization\n");
6668 return -EINVAL;
6669 }
6670
c05422d5
DV		 6671 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6672 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6673
c05422d5 6674 if (!drmmode_obj) {
08d7b3d1
CW		 6675 DRM_ERROR("no such CRTC id\n");
6676 return -EINVAL;
6677 }
6678
c05422d5
DV		 6679 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6680 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6681
c05422d5 6682 return 0;
08d7b3d1
CW		 6683}
6684
c5e4df33 6685static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6686{
4ef69c7a 6687 struct intel_encoder *encoder;
79e53945 6688 int index_mask = 0;
79e53945
JB		 6689 int entry = 0;
6690
4ef69c7a
CW		 6691 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6692 if (type_mask & encoder->clone_mask)
79e53945
JB		 6693 index_mask |= (1 << entry);
6694 entry++;
6695 }
4ef69c7a 6696
79e53945
JB		 6697 return index_mask;
6698}
6699
4d302442
CW		 6700static bool has_edp_a(struct drm_device *dev)
6701{
6702 struct drm_i915_private *dev_priv = dev->dev_private;
6703
6704 if (!IS_MOBILE(dev))
6705 return false;
6706
6707 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6708 return false;
6709
6710 if (IS_GEN5(dev) &&
6711 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6712 return false;
6713
6714 return true;
6715}
6716
79e53945
JB		 6717static void intel_setup_outputs(struct drm_device *dev)
6718{
725e30ad 6719 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6720 struct intel_encoder *encoder;
cb0953d7 6721 bool dpd_is_edp = false;
c5d1b51d 6722 bool has_lvds = false;
79e53945 6723
541998a1 6724 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 6725 has_lvds = intel_lvds_init(dev);
6726 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6727 /* disable the panel fitter on everything but LVDS */
6728 I915_WRITE(PFIT_CONTROL, 0);
6729 }
79e53945 6730
bad720ff 6731 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6732 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6733
4d302442 6734 if (has_edp_a(dev))
32f9d658
ZW		 6735 intel_dp_init(dev, DP_A);
6736
cb0953d7
AJ		 6737 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6738 intel_dp_init(dev, PCH_DP_D);
6739 }
6740
6741 intel_crt_init(dev);
6742
6743 if (HAS_PCH_SPLIT(dev)) {
6744 int found;
6745
30ad48b7 6746 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 6747 /* PCH SDVOB multiplex with HDMIB */
6748 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 6749 if (!found)
6750 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6751 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6752 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6753 }
6754
6755 if (I915_READ(HDMIC) & PORT_DETECTED)
6756 intel_hdmi_init(dev, HDMIC);
6757
6758 if (I915_READ(HDMID) & PORT_DETECTED)
6759 intel_hdmi_init(dev, HDMID);
6760
5eb08b69
ZW		 6761 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6762 intel_dp_init(dev, PCH_DP_C);
6763
cb0953d7 6764 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6765 intel_dp_init(dev, PCH_DP_D);
6766
103a196f 6767 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6768 bool found = false;
7d57382e 6769
725e30ad 6770 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6771 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 6772 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 6773 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6774 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6775 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6776 }
27185ae1 6777
b01f2c3a
JB		 6778 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6779 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6780 intel_dp_init(dev, DP_B);
b01f2c3a 6781 }
725e30ad 6782 }
13520b05
KH		 6783
6784 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6785
b01f2c3a
JB		 6786 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6787 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 6788 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 6789 }
27185ae1
ML		 6790
6791 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6792
b01f2c3a
JB		 6793 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6794 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6795 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6796 }
6797 if (SUPPORTS_INTEGRATED_DP(dev)) {
6798 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6799 intel_dp_init(dev, DP_C);
b01f2c3a 6800 }
725e30ad 6801 }
27185ae1 6802
b01f2c3a
JB		 6803 if (SUPPORTS_INTEGRATED_DP(dev) &&
6804 (I915_READ(DP_D) & DP_DETECTED)) {
6805 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6806 intel_dp_init(dev, DP_D);
b01f2c3a 6807 }
bad720ff 6808 } else if (IS_GEN2(dev))
79e53945
JB		 6809 intel_dvo_init(dev);
6810
103a196f 6811 if (SUPPORTS_TV(dev))
79e53945
JB		 6812 intel_tv_init(dev);
6813
4ef69c7a
CW		 6814 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6815 encoder->base.possible_crtcs = encoder->crtc_mask;
6816 encoder->base.possible_clones =
6817 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6818 }
47356eb6
CW		 6819
6820 intel_panel_setup_backlight(dev);
2c7111db
CW		 6821
6822 /* disable all the possible outputs/crtcs before entering KMS mode */
6823 drm_helper_disable_unused_functions(dev);
79e53945
JB		 6824}
6825
6826static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6827{
6828 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6829
6830 drm_framebuffer_cleanup(fb);
05394f39 6831 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6832
6833 kfree(intel_fb);
6834}
6835
6836static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6837 struct drm_file *file,
79e53945
JB		 6838 unsigned int *handle)
6839{
6840 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6841 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6842
05394f39 6843 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6844}
6845
6846static const struct drm_framebuffer_funcs intel_fb_funcs = {
6847 .destroy = intel_user_framebuffer_destroy,
6848 .create_handle = intel_user_framebuffer_create_handle,
6849};
6850
38651674
DA		 6851int intel_framebuffer_init(struct drm_device *dev,
6852 struct intel_framebuffer *intel_fb,
6853 struct drm_mode_fb_cmd *mode_cmd,
05394f39 6854 struct drm_i915_gem_object *obj)
79e53945 6855{
79e53945
JB		 6856 int ret;
6857
05394f39 6858 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6859 return -EINVAL;
6860
6861 if (mode_cmd->pitch & 63)
6862 return -EINVAL;
6863
6864 switch (mode_cmd->bpp) {
6865 case 8:
6866 case 16:
6867 case 24:
6868 case 32:
6869 break;
6870 default:
6871 return -EINVAL;
6872 }
6873
79e53945
JB		 6874 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6875 if (ret) {
6876 DRM_ERROR("framebuffer init failed %d\n", ret);
6877 return ret;
6878 }
6879
6880 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6881 intel_fb->obj = obj;
79e53945
JB		 6882 return 0;
6883}
6884
79e53945
JB		 6885static struct drm_framebuffer *
6886intel_user_framebuffer_create(struct drm_device *dev,
6887 struct drm_file *filp,
6888 struct drm_mode_fb_cmd *mode_cmd)
6889{
05394f39 6890 struct drm_i915_gem_object *obj;
79e53945 6891
05394f39 6892 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 6893 if (&obj->base == NULL)
cce13ff7 6894 return ERR_PTR(-ENOENT);
79e53945 6895
d2dff872 6896 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6897}
6898
79e53945 6899static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6900 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6901 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6902};
6903
05394f39 6904static struct drm_i915_gem_object *
aa40d6bb 6905intel_alloc_context_page(struct drm_device *dev)
9ea8d059 6906{
05394f39 6907 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 6908 int ret;
6909
2c34b850
BW		 6910 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
6911
aa40d6bb
ZN		 6912 ctx = i915_gem_alloc_object(dev, 4096);
6913 if (!ctx) {
9ea8d059
CW		 6914 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
6915 return NULL;
6916 }
6917
75e9e915 6918 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 6919 if (ret) {
6920 DRM_ERROR("failed to pin power context: %d\n", ret);
6921 goto err_unref;
6922 }
6923
aa40d6bb 6924 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 6925 if (ret) {
6926 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
6927 goto err_unpin;
6928 }
9ea8d059 6929
aa40d6bb 6930 return ctx;
9ea8d059
CW		 6931
6932err_unpin:
aa40d6bb 6933 i915_gem_object_unpin(ctx);
9ea8d059 6934err_unref:
05394f39 6935 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 6936 mutex_unlock(&dev->struct_mutex);
6937 return NULL;
6938}
6939
7648fa99
JB		 6940bool ironlake_set_drps(struct drm_device *dev, u8 val)
6941{
6942 struct drm_i915_private *dev_priv = dev->dev_private;
6943 u16 rgvswctl;
6944
6945 rgvswctl = I915_READ16(MEMSWCTL);
6946 if (rgvswctl & MEMCTL_CMD_STS) {
6947 DRM_DEBUG("gpu busy, RCS change rejected\n");
6948 return false; /* still busy with another command */
6949 }
6950
6951 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
6952 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
6953 I915_WRITE16(MEMSWCTL, rgvswctl);
6954 POSTING_READ16(MEMSWCTL);
6955
6956 rgvswctl |= MEMCTL_CMD_STS;
6957 I915_WRITE16(MEMSWCTL, rgvswctl);
6958
6959 return true;
6960}
6961
f97108d1
JB		 6962void ironlake_enable_drps(struct drm_device *dev)
6963{
6964 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 6965 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 6966 u8 fmax, fmin, fstart, vstart;
f97108d1 6967
ea056c14
JB		 6968 /* Enable temp reporting */
6969 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
6970 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6971
f97108d1
JB		 6972 /* 100ms RC evaluation intervals */
6973 I915_WRITE(RCUPEI, 100000);
6974 I915_WRITE(RCDNEI, 100000);
6975
6976 /* Set max/min thresholds to 90ms and 80ms respectively */
6977 I915_WRITE(RCBMAXAVG, 90000);
6978 I915_WRITE(RCBMINAVG, 80000);
6979
6980 I915_WRITE(MEMIHYST, 1);
6981
6982 /* Set up min, max, and cur for interrupt handling */
6983 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6984 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6985 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6986 MEMMODE_FSTART_SHIFT;
7648fa99 6987
f97108d1
JB		 6988 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6989 PXVFREQ_PX_SHIFT;
6990
80dbf4b7 6991 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 6992 dev_priv->fstart = fstart;
6993
80dbf4b7 6994 dev_priv->max_delay = fstart;
f97108d1
JB		 6995 dev_priv->min_delay = fmin;
6996 dev_priv->cur_delay = fstart;
6997
80dbf4b7
JB		 6998 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6999 fmax, fmin, fstart);
7648fa99 7000
f97108d1
JB		 7001 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7002
7003 /*
7004 * Interrupts will be enabled in ironlake_irq_postinstall
7005 */
7006
7007 I915_WRITE(VIDSTART, vstart);
7008 POSTING_READ(VIDSTART);
7009
7010 rgvmodectl |= MEMMODE_SWMODE_EN;
7011 I915_WRITE(MEMMODECTL, rgvmodectl);
7012
481b6af3 7013 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7014 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7015 msleep(1);
7016
7648fa99 7017 ironlake_set_drps(dev, fstart);
f97108d1 7018
7648fa99
JB		 7019 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7020 I915_READ(0x112e0);
7021 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7022 dev_priv->last_count2 = I915_READ(0x112f4);
7023 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7024}
7025
7026void ironlake_disable_drps(struct drm_device *dev)
7027{
7028 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7029 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7030
7031 /* Ack interrupts, disable EFC interrupt */
7032 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7033 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7034 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7035 I915_WRITE(DEIIR, DE_PCU_EVENT);
7036 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7037
7038 /* Go back to the starting frequency */
7648fa99 7039 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7040 msleep(1);
7041 rgvswctl |= MEMCTL_CMD_STS;
7042 I915_WRITE(MEMSWCTL, rgvswctl);
7043 msleep(1);
7044
7045}
7046
3b8d8d91
JB		 7047void gen6_set_rps(struct drm_device *dev, u8 val)
7048{
7049 struct drm_i915_private *dev_priv = dev->dev_private;
7050 u32 swreq;
7051
7052 swreq = (val & 0x3ff) << 25;
7053 I915_WRITE(GEN6_RPNSWREQ, swreq);
7054}
7055
7056void gen6_disable_rps(struct drm_device *dev)
7057{
7058 struct drm_i915_private *dev_priv = dev->dev_private;
7059
7060 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7061 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7062 I915_WRITE(GEN6_PMIER, 0);
4912d041
BW		 7063
7064 spin_lock_irq(&dev_priv->rps_lock);
7065 dev_priv->pm_iir = 0;
7066 spin_unlock_irq(&dev_priv->rps_lock);
7067
3b8d8d91
JB		 7068 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7069}
7070
7648fa99
JB		 7071static unsigned long intel_pxfreq(u32 vidfreq)
7072{
7073 unsigned long freq;
7074 int div = (vidfreq & 0x3f0000) >> 16;
7075 int post = (vidfreq & 0x3000) >> 12;
7076 int pre = (vidfreq & 0x7);
7077
7078 if (!pre)
7079 return 0;
7080
7081 freq = ((div * 133333) / ((1<<post) * pre));
7082
7083 return freq;
7084}
7085
7086void intel_init_emon(struct drm_device *dev)
7087{
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089 u32 lcfuse;
7090 u8 pxw[16];
7091 int i;
7092
7093 /* Disable to program */
7094 I915_WRITE(ECR, 0);
7095 POSTING_READ(ECR);
7096
7097 /* Program energy weights for various events */
7098 I915_WRITE(SDEW, 0x15040d00);
7099 I915_WRITE(CSIEW0, 0x007f0000);
7100 I915_WRITE(CSIEW1, 0x1e220004);
7101 I915_WRITE(CSIEW2, 0x04000004);
7102
7103 for (i = 0; i < 5; i++)
7104 I915_WRITE(PEW + (i * 4), 0);
7105 for (i = 0; i < 3; i++)
7106 I915_WRITE(DEW + (i * 4), 0);
7107
7108 /* Program P-state weights to account for frequency power adjustment */
7109 for (i = 0; i < 16; i++) {
7110 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7111 unsigned long freq = intel_pxfreq(pxvidfreq);
7112 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7113 PXVFREQ_PX_SHIFT;
7114 unsigned long val;
7115
7116 val = vid * vid;
7117 val *= (freq / 1000);
7118 val *= 255;
7119 val /= (127*127*900);
7120 if (val > 0xff)
7121 DRM_ERROR("bad pxval: %ld\n", val);
7122 pxw[i] = val;
7123 }
7124 /* Render standby states get 0 weight */
7125 pxw[14] = 0;
7126 pxw[15] = 0;
7127
7128 for (i = 0; i < 4; i++) {
7129 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7130 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7131 I915_WRITE(PXW + (i * 4), val);
7132 }
7133
7134 /* Adjust magic regs to magic values (more experimental results) */
7135 I915_WRITE(OGW0, 0);
7136 I915_WRITE(OGW1, 0);
7137 I915_WRITE(EG0, 0x00007f00);
7138 I915_WRITE(EG1, 0x0000000e);
7139 I915_WRITE(EG2, 0x000e0000);
7140 I915_WRITE(EG3, 0x68000300);
7141 I915_WRITE(EG4, 0x42000000);
7142 I915_WRITE(EG5, 0x00140031);
7143 I915_WRITE(EG6, 0);
7144 I915_WRITE(EG7, 0);
7145
7146 for (i = 0; i < 8; i++)
7147 I915_WRITE(PXWL + (i * 4), 0);
7148
7149 /* Enable PMON + select events */
7150 I915_WRITE(ECR, 0x80000019);
7151
7152 lcfuse = I915_READ(LCFUSE02);
7153
7154 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7155}
7156
3b8d8d91 7157void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7158{
a6044e23
JB		 7159 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7160 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7161 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7162 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7163 int i;
7164
7165 /* Here begins a magic sequence of register writes to enable
7166 * auto-downclocking.
7167 *
7168 * Perhaps there might be some value in exposing these to
7169 * userspace...
7170 */
7171 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7172 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7173 gen6_gt_force_wake_get(dev_priv);
8fd26859 7174
3b8d8d91 7175 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7176 I915_WRITE(GEN6_RC_CONTROL, 0);
7177
7178 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7179 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7180 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7181 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7182 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7183
7184 for (i = 0; i < I915_NUM_RINGS; i++)
7185 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7186
7187 I915_WRITE(GEN6_RC_SLEEP, 0);
7188 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7189 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7190 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7191 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7192
7df8721b
JB		 7193 if (i915_enable_rc6)
7194 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7195 GEN6_RC_CTL_RC6_ENABLE;
7196
8fd26859 7197 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7198 rc6_mask |
9c3d2f7f 7199 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7200 GEN6_RC_CTL_HW_ENABLE);
7201
3b8d8d91 7202 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7203 GEN6_FREQUENCY(10) |
7204 GEN6_OFFSET(0) |
7205 GEN6_AGGRESSIVE_TURBO);
7206 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7207 GEN6_FREQUENCY(12));
7208
7209 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7210 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7211 18 << 24 |
7212 6 << 16);
ccab5c82
JB		 7213 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7214 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7215 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7216 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7217 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7218 I915_WRITE(GEN6_RP_CONTROL,
7219 GEN6_RP_MEDIA_TURBO |
7220 GEN6_RP_USE_NORMAL_FREQ |
7221 GEN6_RP_MEDIA_IS_GFX |
7222 GEN6_RP_ENABLE |
ccab5c82
JB		 7223 GEN6_RP_UP_BUSY_AVG |
7224 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7225
7226 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7227 500))
7228 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7229
7230 I915_WRITE(GEN6_PCODE_DATA, 0);
7231 I915_WRITE(GEN6_PCODE_MAILBOX,
7232 GEN6_PCODE_READY |
7233 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7234 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7235 500))
7236 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7237
a6044e23
JB		 7238 min_freq = (rp_state_cap & 0xff0000) >> 16;
7239 max_freq = rp_state_cap & 0xff;
7240 cur_freq = (gt_perf_status & 0xff00) >> 8;
7241
7242 /* Check for overclock support */
7243 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7244 500))
7245 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7246 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7247 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7248 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7249 500))
7250 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7251 if (pcu_mbox & (1<<31)) { /* OC supported */
7252 max_freq = pcu_mbox & 0xff;
e281fcaa 7253 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7254 }
7255
7256 /* In units of 100MHz */
7257 dev_priv->max_delay = max_freq;
7258 dev_priv->min_delay = min_freq;
7259 dev_priv->cur_delay = cur_freq;
7260
8fd26859
CW		 7261 /* requires MSI enabled */
7262 I915_WRITE(GEN6_PMIER,
7263 GEN6_PM_MBOX_EVENT |
7264 GEN6_PM_THERMAL_EVENT |
7265 GEN6_PM_RP_DOWN_TIMEOUT |
7266 GEN6_PM_RP_UP_THRESHOLD |
7267 GEN6_PM_RP_DOWN_THRESHOLD |
7268 GEN6_PM_RP_UP_EI_EXPIRED |
7269 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7270 spin_lock_irq(&dev_priv->rps_lock);
7271 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7272 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7273 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7274 /* enable all PM interrupts */
7275 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7276
fcca7926 7277 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7278 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7279}
7280
23b2f8bb
JB		 7281void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7282{
7283 int min_freq = 15;
7284 int gpu_freq, ia_freq, max_ia_freq;
7285 int scaling_factor = 180;
7286
7287 max_ia_freq = cpufreq_quick_get_max(0);
7288 /*
7289 * Default to measured freq if none found, PCU will ensure we don't go
7290 * over
7291 */
7292 if (!max_ia_freq)
7293 max_ia_freq = tsc_khz;
7294
7295 /* Convert from kHz to MHz */
7296 max_ia_freq /= 1000;
7297
7298 mutex_lock(&dev_priv->dev->struct_mutex);
7299
7300 /*
7301 * For each potential GPU frequency, load a ring frequency we'd like
7302 * to use for memory access. We do this by specifying the IA frequency
7303 * the PCU should use as a reference to determine the ring frequency.
7304 */
7305 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7306 gpu_freq--) {
7307 int diff = dev_priv->max_delay - gpu_freq;
7308
7309 /*
7310 * For GPU frequencies less than 750MHz, just use the lowest
7311 * ring freq.
7312 */
7313 if (gpu_freq < min_freq)
7314 ia_freq = 800;
7315 else
7316 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
7317 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
7318
7319 I915_WRITE(GEN6_PCODE_DATA,
7320 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
7321 gpu_freq);
7322 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
7323 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7324 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
7325 GEN6_PCODE_READY) == 0, 10)) {
7326 DRM_ERROR("pcode write of freq table timed out\n");
7327 continue;
7328 }
7329 }
7330
7331 mutex_unlock(&dev_priv->dev->struct_mutex);
7332}
7333
6067aaea
JB		 7334static void ironlake_init_clock_gating(struct drm_device *dev)
7335{
7336 struct drm_i915_private *dev_priv = dev->dev_private;
7337 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7338
7339 /* Required for FBC */
7340 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
7341 DPFCRUNIT_CLOCK_GATE_DISABLE |
7342 DPFDUNIT_CLOCK_GATE_DISABLE;
7343 /* Required for CxSR */
7344 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
7345
7346 I915_WRITE(PCH_3DCGDIS0,
7347 MARIUNIT_CLOCK_GATE_DISABLE |
7348 SVSMUNIT_CLOCK_GATE_DISABLE);
7349 I915_WRITE(PCH_3DCGDIS1,
7350 VFMUNIT_CLOCK_GATE_DISABLE);
7351
7352 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
7353
6067aaea
JB		 7354 /*
7355 * According to the spec the following bits should be set in
7356 * order to enable memory self-refresh
7357 * The bit 22/21 of 0x42004
7358 * The bit 5 of 0x42020
7359 * The bit 15 of 0x45000
7360 */
7361 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7362 (I915_READ(ILK_DISPLAY_CHICKEN2) |
7363 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
7364 I915_WRITE(ILK_DSPCLK_GATE,
7365 (I915_READ(ILK_DSPCLK_GATE) |
7366 ILK_DPARB_CLK_GATE));
7367 I915_WRITE(DISP_ARB_CTL,
7368 (I915_READ(DISP_ARB_CTL) |
7369 DISP_FBC_WM_DIS));
7370 I915_WRITE(WM3_LP_ILK, 0);
7371 I915_WRITE(WM2_LP_ILK, 0);
7372 I915_WRITE(WM1_LP_ILK, 0);
7373
7374 /*
7375 * Based on the document from hardware guys the following bits
7376 * should be set unconditionally in order to enable FBC.
7377 * The bit 22 of 0x42000
7378 * The bit 22 of 0x42004
7379 * The bit 7,8,9 of 0x42020.
7380 */
7381 if (IS_IRONLAKE_M(dev)) {
7382 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7383 I915_READ(ILK_DISPLAY_CHICKEN1) |
7384 ILK_FBCQ_DIS);
7385 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7386 I915_READ(ILK_DISPLAY_CHICKEN2) |
7387 ILK_DPARB_GATE);
7388 I915_WRITE(ILK_DSPCLK_GATE,
7389 I915_READ(ILK_DSPCLK_GATE) |
7390 ILK_DPFC_DIS1 |
7391 ILK_DPFC_DIS2 |
7392 ILK_CLK_FBC);
7393 }
7394
7395 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7396 I915_READ(ILK_DISPLAY_CHICKEN2) |
7397 ILK_ELPIN_409_SELECT);
7398 I915_WRITE(_3D_CHICKEN2,
7399 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
7400 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 7401}
7402
6067aaea 7403static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 7404{
7405 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 7406 int pipe;
6067aaea
JB		 7407 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7408
7409 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 7410
6067aaea
JB		 7411 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7412 I915_READ(ILK_DISPLAY_CHICKEN2) |
7413 ILK_ELPIN_409_SELECT);
8956c8bb 7414
6067aaea
JB		 7415 I915_WRITE(WM3_LP_ILK, 0);
7416 I915_WRITE(WM2_LP_ILK, 0);
7417 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 7418
7419 /*
6067aaea
JB		 7420 * According to the spec the following bits should be
7421 * set in order to enable memory self-refresh and fbc:
7422 * The bit21 and bit22 of 0x42000
7423 * The bit21 and bit22 of 0x42004
7424 * The bit5 and bit7 of 0x42020
7425 * The bit14 of 0x70180
7426 * The bit14 of 0x71180
652c393a 7427 */
6067aaea
JB		 7428 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7429 I915_READ(ILK_DISPLAY_CHICKEN1) |
7430 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7431 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7432 I915_READ(ILK_DISPLAY_CHICKEN2) |
7433 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
7434 I915_WRITE(ILK_DSPCLK_GATE,
7435 I915_READ(ILK_DSPCLK_GATE) |
7436 ILK_DPARB_CLK_GATE |
7437 ILK_DPFD_CLK_GATE);
8956c8bb 7438
6067aaea
JB		 7439 for_each_pipe(pipe)
7440 I915_WRITE(DSPCNTR(pipe),
7441 I915_READ(DSPCNTR(pipe)) |
7442 DISPPLANE_TRICKLE_FEED_DISABLE);
7443}
8956c8bb 7444
28963a3e
JB		 7445static void ivybridge_init_clock_gating(struct drm_device *dev)
7446{
7447 struct drm_i915_private *dev_priv = dev->dev_private;
7448 int pipe;
7449 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 7450
28963a3e 7451 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 7452
28963a3e
JB		 7453 I915_WRITE(WM3_LP_ILK, 0);
7454 I915_WRITE(WM2_LP_ILK, 0);
7455 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 7456
28963a3e 7457 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 7458
28963a3e
JB		 7459 for_each_pipe(pipe)
7460 I915_WRITE(DSPCNTR(pipe),
7461 I915_READ(DSPCNTR(pipe)) |
7462 DISPPLANE_TRICKLE_FEED_DISABLE);
7463}
7464
6067aaea
JB		 7465static void g4x_init_clock_gating(struct drm_device *dev)
7466{
7467 struct drm_i915_private *dev_priv = dev->dev_private;
7468 uint32_t dspclk_gate;
8fd26859 7469
6067aaea
JB		 7470 I915_WRITE(RENCLK_GATE_D1, 0);
7471 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7472 GS_UNIT_CLOCK_GATE_DISABLE |
7473 CL_UNIT_CLOCK_GATE_DISABLE);
7474 I915_WRITE(RAMCLK_GATE_D, 0);
7475 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7476 OVRUNIT_CLOCK_GATE_DISABLE |
7477 OVCUNIT_CLOCK_GATE_DISABLE;
7478 if (IS_GM45(dev))
7479 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7480 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
7481}
1398261a 7482
6067aaea
JB		 7483static void crestline_init_clock_gating(struct drm_device *dev)
7484{
7485 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7486
6067aaea
JB		 7487 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7488 I915_WRITE(RENCLK_GATE_D2, 0);
7489 I915_WRITE(DSPCLK_GATE_D, 0);
7490 I915_WRITE(RAMCLK_GATE_D, 0);
7491 I915_WRITE16(DEUC, 0);
7492}
652c393a 7493
6067aaea
JB		 7494static void broadwater_init_clock_gating(struct drm_device *dev)
7495{
7496 struct drm_i915_private *dev_priv = dev->dev_private;
7497
7498 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7499 I965_RCC_CLOCK_GATE_DISABLE |
7500 I965_RCPB_CLOCK_GATE_DISABLE |
7501 I965_ISC_CLOCK_GATE_DISABLE |
7502 I965_FBC_CLOCK_GATE_DISABLE);
7503 I915_WRITE(RENCLK_GATE_D2, 0);
7504}
7505
7506static void gen3_init_clock_gating(struct drm_device *dev)
7507{
7508 struct drm_i915_private *dev_priv = dev->dev_private;
7509 u32 dstate = I915_READ(D_STATE);
7510
7511 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7512 DSTATE_DOT_CLOCK_GATING;
7513 I915_WRITE(D_STATE, dstate);
7514}
7515
7516static void i85x_init_clock_gating(struct drm_device *dev)
7517{
7518 struct drm_i915_private *dev_priv = dev->dev_private;
7519
7520 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
7521}
7522
7523static void i830_init_clock_gating(struct drm_device *dev)
7524{
7525 struct drm_i915_private *dev_priv = dev->dev_private;
7526
7527 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 7528}
7529
645c62a5
JB		 7530static void ibx_init_clock_gating(struct drm_device *dev)
7531{
7532 struct drm_i915_private *dev_priv = dev->dev_private;
7533
7534 /*
7535 * On Ibex Peak and Cougar Point, we need to disable clock
7536 * gating for the panel power sequencer or it will fail to
7537 * start up when no ports are active.
7538 */
7539 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7540}
7541
7542static void cpt_init_clock_gating(struct drm_device *dev)
7543{
7544 struct drm_i915_private *dev_priv = dev->dev_private;
7545
7546 /*
7547 * On Ibex Peak and Cougar Point, we need to disable clock
7548 * gating for the panel power sequencer or it will fail to
7549 * start up when no ports are active.
7550 */
7551 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
7552 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
7553 DPLS_EDP_PPS_FIX_DIS);
652c393a
JB		 7554}
7555
ac668088 7556static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 7557{
7558 struct drm_i915_private *dev_priv = dev->dev_private;
7559
7560 if (dev_priv->renderctx) {
ac668088
CW		 7561 i915_gem_object_unpin(dev_priv->renderctx);
7562 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 7563 dev_priv->renderctx = NULL;
7564 }
7565
7566 if (dev_priv->pwrctx) {
ac668088
CW		 7567 i915_gem_object_unpin(dev_priv->pwrctx);
7568 drm_gem_object_unreference(&dev_priv->pwrctx->base);
7569 dev_priv->pwrctx = NULL;
7570 }
7571}
7572
7573static void ironlake_disable_rc6(struct drm_device *dev)
7574{
7575 struct drm_i915_private *dev_priv = dev->dev_private;
7576
7577 if (I915_READ(PWRCTXA)) {
7578 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
7579 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
7580 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
7581 50);
0cdab21f
CW		 7582
7583 I915_WRITE(PWRCTXA, 0);
7584 POSTING_READ(PWRCTXA);
7585
ac668088
CW		 7586 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
7587 POSTING_READ(RSTDBYCTL);
0cdab21f 7588 }
ac668088 7589
99507307 7590 ironlake_teardown_rc6(dev);
0cdab21f
CW		 7591}
7592
ac668088 7593static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 7594{
7595 struct drm_i915_private *dev_priv = dev->dev_private;
7596
ac668088
CW		 7597 if (dev_priv->renderctx == NULL)
7598 dev_priv->renderctx = intel_alloc_context_page(dev);
7599 if (!dev_priv->renderctx)
7600 return -ENOMEM;
7601
7602 if (dev_priv->pwrctx == NULL)
7603 dev_priv->pwrctx = intel_alloc_context_page(dev);
7604 if (!dev_priv->pwrctx) {
7605 ironlake_teardown_rc6(dev);
7606 return -ENOMEM;
7607 }
7608
7609 return 0;
d5bb081b
JB		 7610}
7611
7612void ironlake_enable_rc6(struct drm_device *dev)
7613{
7614 struct drm_i915_private *dev_priv = dev->dev_private;
7615 int ret;
7616
ac668088
CW		 7617 /* rc6 disabled by default due to repeated reports of hanging during
7618 * boot and resume.
7619 */
7620 if (!i915_enable_rc6)
7621 return;
7622
2c34b850 7623 mutex_lock(&dev->struct_mutex);
ac668088 7624 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 7625 if (ret) {
7626 mutex_unlock(&dev->struct_mutex);
ac668088 7627 return;
2c34b850 7628 }
ac668088 7629
d5bb081b
JB		 7630 /*
7631 * GPU can automatically power down the render unit if given a page
7632 * to save state.
7633 */
7634 ret = BEGIN_LP_RING(6);
7635 if (ret) {
ac668088 7636 ironlake_teardown_rc6(dev);
2c34b850 7637 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7638 return;
7639 }
ac668088 7640
d5bb081b
JB		 7641 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
7642 OUT_RING(MI_SET_CONTEXT);
7643 OUT_RING(dev_priv->renderctx->gtt_offset |
7644 MI_MM_SPACE_GTT |
7645 MI_SAVE_EXT_STATE_EN |
7646 MI_RESTORE_EXT_STATE_EN |
7647 MI_RESTORE_INHIBIT);
7648 OUT_RING(MI_SUSPEND_FLUSH);
7649 OUT_RING(MI_NOOP);
7650 OUT_RING(MI_FLUSH);
7651 ADVANCE_LP_RING();
7652
4a246cfc
BW		 7653 /*
7654 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
7655 * does an implicit flush, combined with MI_FLUSH above, it should be
7656 * safe to assume that renderctx is valid
7657 */
7658 ret = intel_wait_ring_idle(LP_RING(dev_priv));
7659 if (ret) {
7660 DRM_ERROR("failed to enable ironlake power power savings\n");
7661 ironlake_teardown_rc6(dev);
7662 mutex_unlock(&dev->struct_mutex);
7663 return;
7664 }
7665
d5bb081b
JB		 7666 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
7667 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 7668 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 7669}
7670
645c62a5
JB		 7671void intel_init_clock_gating(struct drm_device *dev)
7672{
7673 struct drm_i915_private *dev_priv = dev->dev_private;
7674
7675 dev_priv->display.init_clock_gating(dev);
7676
7677 if (dev_priv->display.init_pch_clock_gating)
7678 dev_priv->display.init_pch_clock_gating(dev);
7679}
ac668088 7680
e70236a8
JB		 7681/* Set up chip specific display functions */
7682static void intel_init_display(struct drm_device *dev)
7683{
7684 struct drm_i915_private *dev_priv = dev->dev_private;
7685
7686 /* We always want a DPMS function */
f564048e 7687 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7688 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e
EA		 7689 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
7690 } else {
e70236a8 7691 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e
EA		 7692 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7693 }
e70236a8 7694
ee5382ae 7695 if (I915_HAS_FBC(dev)) {
9c04f015 7696 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 7697 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
7698 dev_priv->display.enable_fbc = ironlake_enable_fbc;
7699 dev_priv->display.disable_fbc = ironlake_disable_fbc;
7700 } else if (IS_GM45(dev)) {
74dff282
JB		 7701 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
7702 dev_priv->display.enable_fbc = g4x_enable_fbc;
7703 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 7704 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 7705 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
7706 dev_priv->display.enable_fbc = i8xx_enable_fbc;
7707 dev_priv->display.disable_fbc = i8xx_disable_fbc;
7708 }
74dff282 7709 /* 855GM needs testing */
e70236a8
JB		 7710 }
7711
7712 /* Returns the core display clock speed */
f2b115e6 7713 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
e70236a8
JB		 7714 dev_priv->display.get_display_clock_speed =
7715 i945_get_display_clock_speed;
7716 else if (IS_I915G(dev))
7717 dev_priv->display.get_display_clock_speed =
7718 i915_get_display_clock_speed;
f2b115e6 7719 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7720 dev_priv->display.get_display_clock_speed =
7721 i9xx_misc_get_display_clock_speed;
7722 else if (IS_I915GM(dev))
7723 dev_priv->display.get_display_clock_speed =
7724 i915gm_get_display_clock_speed;
7725 else if (IS_I865G(dev))
7726 dev_priv->display.get_display_clock_speed =
7727 i865_get_display_clock_speed;
f0f8a9ce 7728 else if (IS_I85X(dev))
e70236a8
JB		 7729 dev_priv->display.get_display_clock_speed =
7730 i855_get_display_clock_speed;
7731 else /* 852, 830 */
7732 dev_priv->display.get_display_clock_speed =
7733 i830_get_display_clock_speed;
7734
7735 /* For FIFO watermark updates */
7f8a8569 7736 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 7737 if (HAS_PCH_IBX(dev))
7738 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
7739 else if (HAS_PCH_CPT(dev))
7740 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
7741
f00a3ddf 7742 if (IS_GEN5(dev)) {
7f8a8569
ZW		 7743 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
7744 dev_priv->display.update_wm = ironlake_update_wm;
7745 else {
7746 DRM_DEBUG_KMS("Failed to get proper latency. "
7747 "Disable CxSR\n");
7748 dev_priv->display.update_wm = NULL;
1398261a 7749 }
674cf967 7750 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 7751 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
1398261a
YL		 7752 } else if (IS_GEN6(dev)) {
7753 if (SNB_READ_WM0_LATENCY()) {
7754 dev_priv->display.update_wm = sandybridge_update_wm;
7755 } else {
7756 DRM_DEBUG_KMS("Failed to read display plane latency. "
7757 "Disable CxSR\n");
7758 dev_priv->display.update_wm = NULL;
7f8a8569 7759 }
674cf967 7760 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 7761 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
357555c0
JB		 7762 } else if (IS_IVYBRIDGE(dev)) {
7763 /* FIXME: detect B0+ stepping and use auto training */
7764 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 7765 if (SNB_READ_WM0_LATENCY()) {
7766 dev_priv->display.update_wm = sandybridge_update_wm;
7767 } else {
7768 DRM_DEBUG_KMS("Failed to read display plane latency. "
7769 "Disable CxSR\n");
7770 dev_priv->display.update_wm = NULL;
7771 }
28963a3e 7772 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6067aaea 7773
7f8a8569
ZW		 7774 } else
7775 dev_priv->display.update_wm = NULL;
7776 } else if (IS_PINEVIEW(dev)) {
d4294342 7777 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 7778 dev_priv->is_ddr3,
d4294342
ZY		 7779 dev_priv->fsb_freq,
7780 dev_priv->mem_freq)) {
7781 DRM_INFO("failed to find known CxSR latency "
95534263 7782 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 7783 "disabling CxSR\n",
95534263 7784 (dev_priv->is_ddr3 == 1) ? "3": "2",
d4294342
ZY		 7785 dev_priv->fsb_freq, dev_priv->mem_freq);
7786 /* Disable CxSR and never update its watermark again */
7787 pineview_disable_cxsr(dev);
7788 dev_priv->display.update_wm = NULL;
7789 } else
7790 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 7791 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 7792 } else if (IS_G4X(dev)) {
e70236a8 7793 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 7794 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7795 } else if (IS_GEN4(dev)) {
e70236a8 7796 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 7797 if (IS_CRESTLINE(dev))
7798 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7799 else if (IS_BROADWATER(dev))
7800 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7801 } else if (IS_GEN3(dev)) {
e70236a8
JB		 7802 dev_priv->display.update_wm = i9xx_update_wm;
7803 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 7804 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7805 } else if (IS_I865G(dev)) {
7806 dev_priv->display.update_wm = i830_update_wm;
7807 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7808 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 7809 } else if (IS_I85X(dev)) {
7810 dev_priv->display.update_wm = i9xx_update_wm;
7811 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 7812 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 7813 } else {
8f4695ed 7814 dev_priv->display.update_wm = i830_update_wm;
6067aaea 7815 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 7816 if (IS_845G(dev))
e70236a8
JB		 7817 dev_priv->display.get_fifo_size = i845_get_fifo_size;
7818 else
7819 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 7820 }
8c9f3aaf
JB		 7821
7822 /* Default just returns -ENODEV to indicate unsupported */
7823 dev_priv->display.queue_flip = intel_default_queue_flip;
7824
7825 switch (INTEL_INFO(dev)->gen) {
7826 case 2:
7827 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7828 break;
7829
7830 case 3:
7831 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7832 break;
7833
7834 case 4:
7835 case 5:
7836 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7837 break;
7838
7839 case 6:
7840 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7841 break;
7c9017e5
JB		 7842 case 7:
7843 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7844 break;
8c9f3aaf 7845 }
e70236a8
JB		 7846}
7847
b690e96c
JB		 7848/*
7849 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7850 * resume, or other times. This quirk makes sure that's the case for
7851 * affected systems.
7852 */
7853static void quirk_pipea_force (struct drm_device *dev)
7854{
7855 struct drm_i915_private *dev_priv = dev->dev_private;
7856
7857 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7858 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
7859}
7860
7861struct intel_quirk {
7862 int device;
7863 int subsystem_vendor;
7864 int subsystem_device;
7865 void (*hook)(struct drm_device *dev);
7866};
7867
7868struct intel_quirk intel_quirks[] = {
7869 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
7870 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
7871 /* HP Mini needs pipe A force quirk (LP: #322104) */
7872 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
7873
7874 /* Thinkpad R31 needs pipe A force quirk */
7875 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7876 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7877 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7878
7879 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7880 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7881 /* ThinkPad X40 needs pipe A force quirk */
7882
7883 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7884 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7885
7886 /* 855 & before need to leave pipe A & dpll A up */
7887 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7888 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7889};
7890
7891static void intel_init_quirks(struct drm_device *dev)
7892{
7893 struct pci_dev *d = dev->pdev;
7894 int i;
7895
7896 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7897 struct intel_quirk *q = &intel_quirks[i];
7898
7899 if (d->device == q->device &&
7900 (d->subsystem_vendor == q->subsystem_vendor ||
7901 q->subsystem_vendor == PCI_ANY_ID) &&
7902 (d->subsystem_device == q->subsystem_device ||
7903 q->subsystem_device == PCI_ANY_ID))
7904 q->hook(dev);
7905 }
7906}
7907
9cce37f4
JB		 7908/* Disable the VGA plane that we never use */
7909static void i915_disable_vga(struct drm_device *dev)
7910{
7911 struct drm_i915_private *dev_priv = dev->dev_private;
7912 u8 sr1;
7913 u32 vga_reg;
7914
7915 if (HAS_PCH_SPLIT(dev))
7916 vga_reg = CPU_VGACNTRL;
7917 else
7918 vga_reg = VGACNTRL;
7919
7920 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7921 outb(1, VGA_SR_INDEX);
7922 sr1 = inb(VGA_SR_DATA);
7923 outb(sr1 | 1<<5, VGA_SR_DATA);
7924 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7925 udelay(300);
7926
7927 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7928 POSTING_READ(vga_reg);
7929}
7930
79e53945
JB		 7931void intel_modeset_init(struct drm_device *dev)
7932{
652c393a 7933 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 7934 int i;
7935
7936 drm_mode_config_init(dev);
7937
7938 dev->mode_config.min_width = 0;
7939 dev->mode_config.min_height = 0;
7940
7941 dev->mode_config.funcs = (void *)&intel_mode_funcs;
7942
b690e96c
JB		 7943 intel_init_quirks(dev);
7944
e70236a8
JB		 7945 intel_init_display(dev);
7946
a6c45cf0
CW		 7947 if (IS_GEN2(dev)) {
7948 dev->mode_config.max_width = 2048;
7949 dev->mode_config.max_height = 2048;
7950 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7951 dev->mode_config.max_width = 4096;
7952 dev->mode_config.max_height = 4096;
79e53945 7953 } else {
a6c45cf0
CW		 7954 dev->mode_config.max_width = 8192;
7955 dev->mode_config.max_height = 8192;
79e53945 7956 }
35c3047a 7957 dev->mode_config.fb_base = dev->agp->base;
79e53945 7958
28c97730 7959 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7960 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7961
a3524f1b 7962 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 7963 intel_crtc_init(dev, i);
7964 }
7965
9cce37f4
JB		 7966 /* Just disable it once at startup */
7967 i915_disable_vga(dev);
79e53945 7968 intel_setup_outputs(dev);
652c393a 7969
645c62a5 7970 intel_init_clock_gating(dev);
9cce37f4 7971
7648fa99 7972 if (IS_IRONLAKE_M(dev)) {
f97108d1 7973 ironlake_enable_drps(dev);
7648fa99
JB		 7974 intel_init_emon(dev);
7975 }
f97108d1 7976
1c70c0ce 7977 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 7978 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 7979 gen6_update_ring_freq(dev_priv);
7980 }
3b8d8d91 7981
652c393a
JB		 7982 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7983 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7984 (unsigned long)dev);
2c7111db
CW		 7985}
7986
7987void intel_modeset_gem_init(struct drm_device *dev)
7988{
7989 if (IS_IRONLAKE_M(dev))
7990 ironlake_enable_rc6(dev);
02e792fb
DV		 7991
7992 intel_setup_overlay(dev);
79e53945
JB		 7993}
7994
7995void intel_modeset_cleanup(struct drm_device *dev)
7996{
652c393a
JB		 7997 struct drm_i915_private *dev_priv = dev->dev_private;
7998 struct drm_crtc *crtc;
7999 struct intel_crtc *intel_crtc;
8000
f87ea761 8001 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8002 mutex_lock(&dev->struct_mutex);
8003
723bfd70
JB		 8004 intel_unregister_dsm_handler();
8005
8006
652c393a
JB		 8007 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8008 /* Skip inactive CRTCs */
8009 if (!crtc->fb)
8010 continue;
8011
8012 intel_crtc = to_intel_crtc(crtc);
3dec0095 8013 intel_increase_pllclock(crtc);
652c393a
JB		 8014 }
8015
e70236a8
JB		 8016 if (dev_priv->display.disable_fbc)
8017 dev_priv->display.disable_fbc(dev);
8018
f97108d1
JB		 8019 if (IS_IRONLAKE_M(dev))
8020 ironlake_disable_drps(dev);
1c70c0ce 8021 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8022 gen6_disable_rps(dev);
f97108d1 8023
d5bb081b
JB		 8024 if (IS_IRONLAKE_M(dev))
8025 ironlake_disable_rc6(dev);
0cdab21f 8026
69341a5e
KH		 8027 mutex_unlock(&dev->struct_mutex);
8028
6c0d9350
DV		 8029 /* Disable the irq before mode object teardown, for the irq might
8030 * enqueue unpin/hotplug work. */
8031 drm_irq_uninstall(dev);
8032 cancel_work_sync(&dev_priv->hotplug_work);
8033
3dec0095
DV		 8034 /* Shut off idle work before the crtcs get freed. */
8035 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8036 intel_crtc = to_intel_crtc(crtc);
8037 del_timer_sync(&intel_crtc->idle_timer);
8038 }
8039 del_timer_sync(&dev_priv->idle_timer);
8040 cancel_work_sync(&dev_priv->idle_work);
8041
79e53945
JB		 8042 drm_mode_config_cleanup(dev);
8043}
8044
f1c79df3
ZW		 8045/*
8046 * Return which encoder is currently attached for connector.
8047 */
df0e9248 8048struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8049{
df0e9248
CW		 8050 return &intel_attached_encoder(connector)->base;
8051}
f1c79df3 8052
df0e9248
CW		 8053void intel_connector_attach_encoder(struct intel_connector *connector,
8054 struct intel_encoder *encoder)
8055{
8056 connector->encoder = encoder;
8057 drm_mode_connector_attach_encoder(&connector->base,
8058 &encoder->base);
79e53945 8059}
28d52043
DA		 8060
8061/*
8062 * set vga decode state - true == enable VGA decode
8063 */
8064int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8065{
8066 struct drm_i915_private *dev_priv = dev->dev_private;
8067 u16 gmch_ctrl;
8068
8069 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8070 if (state)
8071 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8072 else
8073 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8074 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8075 return 0;
8076}
c4a1d9e4
CW		 8077
8078#ifdef CONFIG_DEBUG_FS
8079#include <linux/seq_file.h>
8080
8081struct intel_display_error_state {
8082 struct intel_cursor_error_state {
8083 u32 control;
8084 u32 position;
8085 u32 base;
8086 u32 size;
8087 } cursor[2];
8088
8089 struct intel_pipe_error_state {
8090 u32 conf;
8091 u32 source;
8092
8093 u32 htotal;
8094 u32 hblank;
8095 u32 hsync;
8096 u32 vtotal;
8097 u32 vblank;
8098 u32 vsync;
8099 } pipe[2];
8100
8101 struct intel_plane_error_state {
8102 u32 control;
8103 u32 stride;
8104 u32 size;
8105 u32 pos;
8106 u32 addr;
8107 u32 surface;
8108 u32 tile_offset;
8109 } plane[2];
8110};
8111
8112struct intel_display_error_state *
8113intel_display_capture_error_state(struct drm_device *dev)
8114{
8115 drm_i915_private_t *dev_priv = dev->dev_private;
8116 struct intel_display_error_state *error;
8117 int i;
8118
8119 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8120 if (error == NULL)
8121 return NULL;
8122
8123 for (i = 0; i < 2; i++) {
8124 error->cursor[i].control = I915_READ(CURCNTR(i));
8125 error->cursor[i].position = I915_READ(CURPOS(i));
8126 error->cursor[i].base = I915_READ(CURBASE(i));
8127
8128 error->plane[i].control = I915_READ(DSPCNTR(i));
8129 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8130 error->plane[i].size = I915_READ(DSPSIZE(i));
8131 error->plane[i].pos= I915_READ(DSPPOS(i));
8132 error->plane[i].addr = I915_READ(DSPADDR(i));
8133 if (INTEL_INFO(dev)->gen >= 4) {
8134 error->plane[i].surface = I915_READ(DSPSURF(i));
8135 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8136 }
8137
8138 error->pipe[i].conf = I915_READ(PIPECONF(i));
8139 error->pipe[i].source = I915_READ(PIPESRC(i));
8140 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8141 error->pipe[i].hblank = I915_READ(HBLANK(i));
8142 error->pipe[i].hsync = I915_READ(HSYNC(i));
8143 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8144 error->pipe[i].vblank = I915_READ(VBLANK(i));
8145 error->pipe[i].vsync = I915_READ(VSYNC(i));
8146 }
8147
8148 return error;
8149}
8150
8151void
8152intel_display_print_error_state(struct seq_file *m,
8153 struct drm_device *dev,
8154 struct intel_display_error_state *error)
8155{
8156 int i;
8157
8158 for (i = 0; i < 2; i++) {
8159 seq_printf(m, "Pipe [%d]:\n", i);
8160 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8161 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8162 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8163 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8164 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8165 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8166 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8167 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8168
8169 seq_printf(m, "Plane [%d]:\n", i);
8170 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8171 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8172 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8173 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8174 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8175 if (INTEL_INFO(dev)->gen >= 4) {
8176 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8177 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8178 }
8179
8180 seq_printf(m, "Cursor [%d]:\n", i);
8181 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8182 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8183 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8184 }
8185}
8186#endif
kernel source for telekom puls (alcatel/mediatek)