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drm/i915: remove ironlake bits from lpt_pch_enable
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d2acd215
DV		 83int
84intel_pch_rawclk(struct drm_device *dev)
85{
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91}
92
d4906093
ML		 93static bool
94intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
d4906093
ML		 97static bool
98intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
79e53945 101
a4fc5ed6
KP		 102static bool
103intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
5eb08b69 106static bool
f2b115e6 107intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
a4fc5ed6 110
a0c4da24
JB		 111static bool
112intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
021357ac
CW		 116static inline u32 /* units of 100MHz */
117intel_fdi_link_freq(struct drm_device *dev)
118{
8b99e68c
CW		 119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
021357ac
CW		 124}
125
e4b36699 126static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699
KP		 138};
139
140static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699 152};
273e27ca 153
e4b36699 154static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
d4906093 179 .find_pll = intel_find_best_PLL,
e4b36699
KP		 180};
181
273e27ca 182
e4b36699 183static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
044c7c41 195 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
044c7c41 239 },
d4906093 240 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
273e27ca 253 .p2_slow = 10, .p2_fast = 10 },
0206e353 254 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 255};
256
f2b115e6 257static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 260 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
273e27ca 263 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
f2b115e6 273static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
6115707b 284 .find_pll = intel_find_best_PLL,
e4b36699
KP		 285};
286
273e27ca
EA		 287/* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
4547668a 303 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 304};
305
b91ad0ec 306static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
320static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
273e27ca 334/* LVDS 100mhz refclk limits. */
b91ad0ec 335static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
0206e353 343 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
0206e353 357 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 360 .find_pll = intel_g4x_find_best_PLL,
361};
362
363static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
273e27ca 373 .p2_slow = 10, .p2_fast = 10 },
0206e353 374 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 375};
376
a0c4da24
JB		 377static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389};
390
391static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
17dc9257 393 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403};
404
405static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 408 .n = { .min = 1, .max = 7 },
74a4dd2e 409 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417};
418
57f350b6
JB		 419u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420{
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442}
443
a0c4da24
JB		 444static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446{
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464}
465
57f350b6
JB		 466static void vlv_init_dpio(struct drm_device *dev)
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475}
476
618563e3
DV		 477static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478{
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481}
482
483static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493};
494
b0354385
TI		 495static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497{
498 unsigned int val;
499
121d527a
TI		 500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
618563e3
DV		 504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
b0354385
TI		 507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
14d94a3d 516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521}
522
1b894b59
CW		 523static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
2c07245f 525{
b91ad0ec
ZW		 526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 528 const intel_limit_t *limit;
b91ad0ec
ZW		 529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 532 /* LVDS dual channel */
1b894b59 533 if (refclk == 100000)
b91ad0ec
ZW		 534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
1b894b59 538 if (refclk == 100000)
b91ad0ec
ZW		 539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
2c07245f 546 else
b91ad0ec 547 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 548
549 return limit;
550}
551
044c7c41
ML		 552static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553{
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 559 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 560 /* LVDS with dual channel */
e4b36699 561 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 562 else
563 /* LVDS with dual channel */
e4b36699 564 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 567 limit = &intel_limits_g4x_hdmi;
044c7c41 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 569 limit = &intel_limits_g4x_sdvo;
0206e353 570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 571 limit = &intel_limits_g4x_display_port;
044c7c41 572 } else /* The option is for other outputs */
e4b36699 573 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 574
575 return limit;
576}
577
1b894b59 578static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 579{
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
bad720ff 583 if (HAS_PCH_SPLIT(dev))
1b894b59 584 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 585 else if (IS_G4X(dev)) {
044c7c41 586 limit = intel_g4x_limit(crtc);
f2b115e6 587 } else if (IS_PINEVIEW(dev)) {
2177832f 588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 589 limit = &intel_limits_pineview_lvds;
2177832f 590 else
f2b115e6 591 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 606 limit = &intel_limits_i8xx_lvds;
79e53945 607 else
e4b36699 608 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 609 }
610 return limit;
611}
612
f2b115e6
AJ		 613/* m1 is reserved as 0 in Pineview, n is a ring counter */
614static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 615{
2177832f
SL		 616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620}
621
622static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623{
f2b115e6
AJ		 624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
2177832f
SL		 626 return;
627 }
79e53945
JB		 628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632}
633
79e53945
JB		 634/**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
4ef69c7a 637bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 638{
4ef69c7a 639 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 640 struct intel_encoder *encoder;
641
6c2b7c12
DV		 642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
4ef69c7a
CW		 644 return true;
645
646 return false;
79e53945
JB		 647}
648
7c04d1d9 649#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 650/**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
1b894b59
CW		 655static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
79e53945 658{
79e53945 659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 660 INTELPllInvalid("p1 out of range\n");
79e53945 661 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 662 INTELPllInvalid("p out of range\n");
79e53945 663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 664 INTELPllInvalid("m2 out of range\n");
79e53945 665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 666 INTELPllInvalid("m1 out of range\n");
f2b115e6 667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 668 INTELPllInvalid("m1 <= m2\n");
79e53945 669 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 670 INTELPllInvalid("m out of range\n");
79e53945 671 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 672 INTELPllInvalid("n out of range\n");
79e53945 673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 674 INTELPllInvalid("vco out of range\n");
79e53945
JB		 675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 679 INTELPllInvalid("dot out of range\n");
79e53945
JB		 680
681 return true;
682}
683
d4906093
ML		 684static bool
685intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
d4906093 688
79e53945
JB		 689{
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
79e53945
JB		 693 int err = target;
694
bc5e5718 695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 696 (I915_READ(LVDS)) != 0) {
79e53945
JB		 697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
b0354385 703 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
0206e353 714 memset(best_clock, 0, sizeof(*best_clock));
79e53945 715
42158660
ZY		 716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 727 int this_err;
728
2177832f 729 intel_clock(dev, refclk, &clock);
1b894b59
CW		 730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
79e53945 732 continue;
cec2f356
SP		 733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
79e53945
JB		 736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748}
749
d4906093
ML		 750static bool
751intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
d4906093
ML		 754{
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
6ba770dc
AJ		 760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 765 int lvds_reg;
766
c619eed4 767 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
f77f13e2 785 /* based on hardware requirement, prefer smaller n to precision */
d4906093 786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 787 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
2177832f 796 intel_clock(dev, refclk, &clock);
1b894b59
CW		 797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
d4906093 799 continue;
cec2f356
SP		 800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
1b894b59
CW		 803
804 this_err = abs(clock.dot - target);
d4906093
ML		 805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
2c07245f
ZW		 815 return found;
816}
817
5eb08b69 818static bool
f2b115e6 819intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
5eb08b69
ZW		 822{
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
4547668a 825
5eb08b69
ZW		 826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842}
843
a4fc5ed6
KP		 844/* DisplayPort has only two frequencies, 162MHz and 270MHz */
845static bool
846intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
a4fc5ed6 849{
5eddb70b
CW		 850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
a4fc5ed6 870}
a0c4da24
JB		 871static bool
872intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
af447bd3 882 flag = 0;
a0c4da24
JB		 883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938}
a4fc5ed6 939
a5c961d1
PZ		 940enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942{
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947}
948
a928d536
PZ		 949static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950{
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958}
959
9d0498a2
JB		 960/**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 969{
9d0498a2 970 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 971 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 972
a928d536
PZ		 973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
300387c0
CW		 978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
9d0498a2 994 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
9d0498a2
JB		 998 DRM_DEBUG_KMS("vblank wait timed out\n");
999}
1000
ab7ad7f6
KP		 1001/*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
ab7ad7f6
KP		 1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
58e10eb9 1016 *
9d0498a2 1017 */
58e10eb9 1018void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1019{
1020 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
ab7ad7f6
KP		 1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1025 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1026
1027 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
284637d9 1030 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1031 } else {
837ba00f 1032 u32 last_line, line_mask;
58e10eb9 1033 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
837ba00f
PZ		 1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
ab7ad7f6
KP		 1041 /* Wait for the display line to settle */
1042 do {
837ba00f 1043 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1044 mdelay(5);
837ba00f 1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
284637d9 1048 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1049 }
79e53945
JB		 1050}
1051
b24e7179
JB		 1052static const char *state_string(bool enabled)
1053{
1054 return enabled ? "on" : "off";
1055}
1056
1057/* Only for pre-ILK configs */
1058static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060{
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071}
1072#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
040484af
JB		 1075/* For ILK+ */
1076static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
040484af 1080{
040484af
JB		 1081 u32 val;
1082 bool cur_state;
1083
9d82aa17
ED		 1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
92b27b08
CW		 1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1091 return;
ee7b9f93 1092
92b27b08
CW		 1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
d3ccbe86 1116 }
040484af 1117}
92b27b08
CW		 1118#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1120
1121static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123{
1124 int reg;
1125 u32 val;
1126 bool cur_state;
ad80a810
PZ		 1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
040484af 1129
bf507ef7
ED		 1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1133 val = I915_READ(reg);
ad80a810 1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
040484af
JB		 1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143}
1144#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149{
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
59c859d6
ED		 1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
040484af
JB		 1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
bf507ef7
ED		 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186}
1187
1188static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190{
1191 int reg;
1192 u32 val;
1193
59c859d6
ED		 1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
040484af
JB		 1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201}
1202
ea0760cf
JB		 1203static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
0de3b485 1209 bool locked = true;
ea0760cf
JB		 1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1229 pipe_name(pipe));
ea0760cf
JB		 1230}
1231
b840d907
JB		 1232void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
b24e7179
JB		 1234{
1235 int reg;
1236 u32 val;
63d7bbe9 1237 bool cur_state;
702e7a56
PZ		 1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
b24e7179 1240
8e636784
DV		 1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
702e7a56 1245 reg = PIPECONF(cpu_transcoder);
b24e7179 1246 val = I915_READ(reg);
63d7bbe9
JB		 1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1250 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1251}
1252
931872fc
CW		 1253static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
b24e7179
JB		 1255{
1256 int reg;
1257 u32 val;
931872fc 1258 bool cur_state;
b24e7179
JB		 1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
931872fc
CW		 1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1266}
1267
931872fc
CW		 1268#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
b24e7179
JB		 1271static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273{
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
19ec1358 1278 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
19ec1358 1285 return;
28c05794 1286 }
19ec1358 1287
b24e7179
JB		 1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1297 }
1298}
1299
92f2584a
JB		 1300static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301{
1302 u32 val;
1303 bool enabled;
1304
9d82aa17
ED		 1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
92f2584a
JB		 1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314}
1315
1316static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318{
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
92f2584a
JB		 1329}
1330
4e634389
KP		 1331static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1333{
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347}
1348
1519b995
KP		 1349static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351{
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363}
1364
1365static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367{
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379}
1380
1381static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383{
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394}
1395
291906f1 1396static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1397 enum pipe pipe, int reg, u32 port_sel)
291906f1 1398{
47a05eca 1399 u32 val = I915_READ(reg);
4e634389 1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1402 reg, pipe_name(pipe));
de9a35ab 1403
75c5da27
DV		 1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
de9a35ab 1406 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1407}
1408
1409static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411{
47a05eca 1412 u32 val = I915_READ(reg);
e9a851ed 1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 reg, pipe_name(pipe));
de9a35ab 1416
75c5da27
DV		 1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1419 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1420}
1421
1422static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424{
1425 int reg;
1426 u32 val;
291906f1 1427
f0575e92
KP		 1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
e9a851ed 1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1436 pipe_name(pipe));
291906f1
JB		 1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
e9a851ed 1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1442 pipe_name(pipe));
291906f1
JB		 1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447}
1448
63d7bbe9
JB		 1449/**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
7434a255
TR		 1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1461 */
a37b9b34 1462static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1463{
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
a0c4da24 1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488}
1489
1490/**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500{
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516}
1517
a416edef
ED		 1518/* SBI access */
1519static void
1520intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521{
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547}
1548
1549static u32
1550intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551{
1552 unsigned long flags;
39fb50f6 1553 u32 value = 0;
a416edef
ED		 1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
39fb50f6 1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579}
1580
92f2584a
JB		 1581/**
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
ee7b9f93 1589static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1590{
ee7b9f93 1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1592 struct intel_pch_pll *pll;
92f2584a
JB		 1593 int reg;
1594 u32 val;
1595
48da64a8 1596 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1597 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
ee7b9f93
JB		 1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
92f2584a
JB		 1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
ee7b9f93 1612 if (pll->active++ && pll->on) {
92b27b08 1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
92f2584a
JB		 1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
ee7b9f93
JB		 1625
1626 pll->on = true;
92f2584a
JB		 1627}
1628
ee7b9f93 1629static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1630{
ee7b9f93
JB		 1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1633 int reg;
ee7b9f93 1634 u32 val;
4c609cb8 1635
92f2584a
JB		 1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1638 if (pll == NULL)
1639 return;
92f2584a 1640
48da64a8
CW		 1641 if (WARN_ON(pll->refcount == 0))
1642 return;
7a419866 1643
ee7b9f93
JB		 1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
7a419866 1647
48da64a8 1648 if (WARN_ON(pll->active == 0)) {
92b27b08 1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1650 return;
1651 }
1652
ee7b9f93 1653 if (--pll->active) {
92b27b08 1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1655 return;
ee7b9f93
JB		 1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1662
ee7b9f93 1663 reg = pll->pll_reg;
92f2584a
JB		 1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
ee7b9f93
JB		 1669
1670 pll->on = false;
92f2584a
JB		 1671}
1672
040484af
JB		 1673static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675{
1676 int reg;
5f7f726d 1677 u32 val, pipeconf_val;
7c26e5c6 1678 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
040484af
JB		 1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
59c859d6
ED		 1692 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1694 return;
1695 }
040484af
JB		 1696 reg = TRANSCONF(pipe);
1697 val = I915_READ(reg);
5f7f726d 1698 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1699
1700 if (HAS_PCH_IBX(dev_priv->dev)) {
1701 /*
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1704 */
1705 val &= ~PIPE_BPC_MASK;
5f7f726d 1706 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1707 }
5f7f726d
PZ		 1708
1709 val &= ~TRANS_INTERLACE_MASK;
1710 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1711 if (HAS_PCH_IBX(dev_priv->dev) &&
1712 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1713 val |= TRANS_LEGACY_INTERLACED_ILK;
1714 else
1715 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1716 else
1717 val |= TRANS_PROGRESSIVE;
1718
040484af
JB		 1719 I915_WRITE(reg, val | TRANS_ENABLE);
1720 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1722}
1723
1724static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 int reg;
1728 u32 val;
1729
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv, pipe);
1732 assert_fdi_rx_disabled(dev_priv, pipe);
1733
291906f1
JB		 1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv, pipe);
1736
040484af
JB		 1737 reg = TRANSCONF(pipe);
1738 val = I915_READ(reg);
1739 val &= ~TRANS_ENABLE;
1740 I915_WRITE(reg, val);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1743 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1744}
1745
b24e7179 1746/**
309cfea8 1747 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
040484af 1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1751 *
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1758 * returning.
1759 */
040484af
JB		 1760static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1761 bool pch_port)
b24e7179 1762{
702e7a56
PZ		 1763 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1764 pipe);
b24e7179
JB		 1765 int reg;
1766 u32 val;
1767
1768 /*
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1771 * need the check.
1772 */
1773 if (!HAS_PCH_SPLIT(dev_priv->dev))
1774 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1775 else {
1776 if (pch_port) {
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1779 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1780 }
1781 /* FIXME: assert CPU port conditions for SNB+ */
1782 }
b24e7179 1783
702e7a56 1784 reg = PIPECONF(cpu_transcoder);
b24e7179 1785 val = I915_READ(reg);
00d70b15
CW		 1786 if (val & PIPECONF_ENABLE)
1787 return;
1788
1789 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1790 intel_wait_for_vblank(dev_priv->dev, pipe);
1791}
1792
1793/**
309cfea8 1794 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1797 *
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1800 *
1801 * @pipe should be %PIPE_A or %PIPE_B.
1802 *
1803 * Will wait until the pipe has shut down before returning.
1804 */
1805static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1806 enum pipe pipe)
1807{
702e7a56
PZ		 1808 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1809 pipe);
b24e7179
JB		 1810 int reg;
1811 u32 val;
1812
1813 /*
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1816 */
1817 assert_planes_disabled(dev_priv, pipe);
1818
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1821 return;
1822
702e7a56 1823 reg = PIPECONF(cpu_transcoder);
b24e7179 1824 val = I915_READ(reg);
00d70b15
CW		 1825 if ((val & PIPECONF_ENABLE) == 0)
1826 return;
1827
1828 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1829 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1830}
1831
d74362c9
KP		 1832/*
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1835 */
6f1d69b0 1836void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1837 enum plane plane)
1838{
14f86147
DL		 1839 if (dev_priv->info->gen >= 4)
1840 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1841 else
1842 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1843}
1844
b24e7179
JB		 1845/**
1846 * intel_enable_plane - enable a display plane on a given pipe
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to enable
1849 * @pipe: pipe being fed
1850 *
1851 * Enable @plane on @pipe, making sure that @pipe is running first.
1852 */
1853static void intel_enable_plane(struct drm_i915_private *dev_priv,
1854 enum plane plane, enum pipe pipe)
1855{
1856 int reg;
1857 u32 val;
1858
1859 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860 assert_pipe_enabled(dev_priv, pipe);
1861
1862 reg = DSPCNTR(plane);
1863 val = I915_READ(reg);
00d70b15
CW		 1864 if (val & DISPLAY_PLANE_ENABLE)
1865 return;
1866
1867 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1868 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1869 intel_wait_for_vblank(dev_priv->dev, pipe);
1870}
1871
b24e7179
JB		 1872/**
1873 * intel_disable_plane - disable a display plane
1874 * @dev_priv: i915 private structure
1875 * @plane: plane to disable
1876 * @pipe: pipe consuming the data
1877 *
1878 * Disable @plane; should be an independent operation.
1879 */
1880static void intel_disable_plane(struct drm_i915_private *dev_priv,
1881 enum plane plane, enum pipe pipe)
1882{
1883 int reg;
1884 u32 val;
1885
1886 reg = DSPCNTR(plane);
1887 val = I915_READ(reg);
00d70b15
CW		 1888 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1889 return;
1890
1891 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1892 intel_flush_display_plane(dev_priv, plane);
1893 intel_wait_for_vblank(dev_priv->dev, pipe);
1894}
1895
127bd2ac 1896int
48b956c5 1897intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1898 struct drm_i915_gem_object *obj,
919926ae 1899 struct intel_ring_buffer *pipelined)
6b95a207 1900{
ce453d81 1901 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1902 u32 alignment;
1903 int ret;
1904
05394f39 1905 switch (obj->tiling_mode) {
6b95a207 1906 case I915_TILING_NONE:
534843da
CW		 1907 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1908 alignment = 128 * 1024;
a6c45cf0 1909 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1910 alignment = 4 * 1024;
1911 else
1912 alignment = 64 * 1024;
6b95a207
KH		 1913 break;
1914 case I915_TILING_X:
1915 /* pin() will align the object as required by fence */
1916 alignment = 0;
1917 break;
1918 case I915_TILING_Y:
1919 /* FIXME: Is this true? */
1920 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1921 return -EINVAL;
1922 default:
1923 BUG();
1924 }
1925
ce453d81 1926 dev_priv->mm.interruptible = false;
2da3b9b9 1927 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1928 if (ret)
ce453d81 1929 goto err_interruptible;
6b95a207
KH		 1930
1931 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932 * fence, whereas 965+ only requires a fence if using
1933 * framebuffer compression. For simplicity, we always install
1934 * a fence as the cost is not that onerous.
1935 */
06d98131 1936 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1937 if (ret)
1938 goto err_unpin;
1690e1eb 1939
9a5a53b3 1940 i915_gem_object_pin_fence(obj);
6b95a207 1941
ce453d81 1942 dev_priv->mm.interruptible = true;
6b95a207 1943 return 0;
48b956c5
CW		 1944
1945err_unpin:
1946 i915_gem_object_unpin(obj);
ce453d81
CW		 1947err_interruptible:
1948 dev_priv->mm.interruptible = true;
48b956c5 1949 return ret;
6b95a207
KH		 1950}
1951
1690e1eb
CW		 1952void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1953{
1954 i915_gem_object_unpin_fence(obj);
1955 i915_gem_object_unpin(obj);
1956}
1957
c2c75131
DV		 1958/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959 * is assumed to be a power-of-two. */
5a35e99e
DL		 1960unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1961 unsigned int bpp,
1962 unsigned int pitch)
c2c75131
DV		 1963{
1964 int tile_rows, tiles;
1965
1966 tile_rows = *y / 8;
1967 *y %= 8;
1968 tiles = *x / (512/bpp);
1969 *x %= 512/bpp;
1970
1971 return tile_rows * pitch * 8 + tiles * 4096;
1972}
1973
17638cd6
JB		 1974static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1975 int x, int y)
81255565
JB		 1976{
1977 struct drm_device *dev = crtc->dev;
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1980 struct intel_framebuffer *intel_fb;
05394f39 1981 struct drm_i915_gem_object *obj;
81255565 1982 int plane = intel_crtc->plane;
e506a0c6 1983 unsigned long linear_offset;
81255565 1984 u32 dspcntr;
5eddb70b 1985 u32 reg;
81255565
JB		 1986
1987 switch (plane) {
1988 case 0:
1989 case 1:
1990 break;
1991 default:
1992 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1993 return -EINVAL;
1994 }
1995
1996 intel_fb = to_intel_framebuffer(fb);
1997 obj = intel_fb->obj;
81255565 1998
5eddb70b
CW		 1999 reg = DSPCNTR(plane);
2000 dspcntr = I915_READ(reg);
81255565
JB		 2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2003 switch (fb->pixel_format) {
2004 case DRM_FORMAT_C8:
81255565
JB		 2005 dspcntr |= DISPPLANE_8BPP;
2006 break;
57779d06
VS		 2007 case DRM_FORMAT_XRGB1555:
2008 case DRM_FORMAT_ARGB1555:
2009 dspcntr |= DISPPLANE_BGRX555;
81255565 2010 break;
57779d06
VS		 2011 case DRM_FORMAT_RGB565:
2012 dspcntr |= DISPPLANE_BGRX565;
2013 break;
2014 case DRM_FORMAT_XRGB8888:
2015 case DRM_FORMAT_ARGB8888:
2016 dspcntr |= DISPPLANE_BGRX888;
2017 break;
2018 case DRM_FORMAT_XBGR8888:
2019 case DRM_FORMAT_ABGR8888:
2020 dspcntr |= DISPPLANE_RGBX888;
2021 break;
2022 case DRM_FORMAT_XRGB2101010:
2023 case DRM_FORMAT_ARGB2101010:
2024 dspcntr |= DISPPLANE_BGRX101010;
2025 break;
2026 case DRM_FORMAT_XBGR2101010:
2027 case DRM_FORMAT_ABGR2101010:
2028 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2029 break;
2030 default:
57779d06 2031 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2032 return -EINVAL;
2033 }
57779d06 2034
a6c45cf0 2035 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2036 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2037 dspcntr |= DISPPLANE_TILED;
2038 else
2039 dspcntr &= ~DISPPLANE_TILED;
2040 }
2041
5eddb70b 2042 I915_WRITE(reg, dspcntr);
81255565 2043
e506a0c6 2044 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2045
c2c75131
DV		 2046 if (INTEL_INFO(dev)->gen >= 4) {
2047 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2048 intel_gen4_compute_offset_xtiled(&x, &y,
2049 fb->bits_per_pixel / 8,
2050 fb->pitches[0]);
c2c75131
DV		 2051 linear_offset -= intel_crtc->dspaddr_offset;
2052 } else {
e506a0c6 2053 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2054 }
e506a0c6
DV		 2055
2056 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2057 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2058 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2059 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2060 I915_MODIFY_DISPBASE(DSPSURF(plane),
2061 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2062 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2063 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2064 } else
e506a0c6 2065 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2066 POSTING_READ(reg);
81255565 2067
17638cd6
JB		 2068 return 0;
2069}
2070
2071static int ironlake_update_plane(struct drm_crtc *crtc,
2072 struct drm_framebuffer *fb, int x, int y)
2073{
2074 struct drm_device *dev = crtc->dev;
2075 struct drm_i915_private *dev_priv = dev->dev_private;
2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2077 struct intel_framebuffer *intel_fb;
2078 struct drm_i915_gem_object *obj;
2079 int plane = intel_crtc->plane;
e506a0c6 2080 unsigned long linear_offset;
17638cd6
JB		 2081 u32 dspcntr;
2082 u32 reg;
2083
2084 switch (plane) {
2085 case 0:
2086 case 1:
27f8227b 2087 case 2:
17638cd6
JB		 2088 break;
2089 default:
2090 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2091 return -EINVAL;
2092 }
2093
2094 intel_fb = to_intel_framebuffer(fb);
2095 obj = intel_fb->obj;
2096
2097 reg = DSPCNTR(plane);
2098 dspcntr = I915_READ(reg);
2099 /* Mask out pixel format bits in case we change it */
2100 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2101 switch (fb->pixel_format) {
2102 case DRM_FORMAT_C8:
17638cd6
JB		 2103 dspcntr |= DISPPLANE_8BPP;
2104 break;
57779d06
VS		 2105 case DRM_FORMAT_RGB565:
2106 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2107 break;
57779d06
VS		 2108 case DRM_FORMAT_XRGB8888:
2109 case DRM_FORMAT_ARGB8888:
2110 dspcntr |= DISPPLANE_BGRX888;
2111 break;
2112 case DRM_FORMAT_XBGR8888:
2113 case DRM_FORMAT_ABGR8888:
2114 dspcntr |= DISPPLANE_RGBX888;
2115 break;
2116 case DRM_FORMAT_XRGB2101010:
2117 case DRM_FORMAT_ARGB2101010:
2118 dspcntr |= DISPPLANE_BGRX101010;
2119 break;
2120 case DRM_FORMAT_XBGR2101010:
2121 case DRM_FORMAT_ABGR2101010:
2122 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2123 break;
2124 default:
57779d06 2125 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2126 return -EINVAL;
2127 }
2128
2129 if (obj->tiling_mode != I915_TILING_NONE)
2130 dspcntr |= DISPPLANE_TILED;
2131 else
2132 dspcntr &= ~DISPPLANE_TILED;
2133
2134 /* must disable */
2135 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137 I915_WRITE(reg, dspcntr);
2138
e506a0c6 2139 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2140 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2141 intel_gen4_compute_offset_xtiled(&x, &y,
2142 fb->bits_per_pixel / 8,
2143 fb->pitches[0]);
c2c75131 2144 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2145
e506a0c6
DV		 2146 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2148 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2149 I915_MODIFY_DISPBASE(DSPSURF(plane),
2150 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2151 if (IS_HASWELL(dev)) {
2152 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2153 } else {
2154 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2155 I915_WRITE(DSPLINOFF(plane), linear_offset);
2156 }
17638cd6
JB		 2157 POSTING_READ(reg);
2158
2159 return 0;
2160}
2161
2162/* Assume fb object is pinned & idle & fenced and just update base pointers */
2163static int
2164intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2165 int x, int y, enum mode_set_atomic state)
2166{
2167 struct drm_device *dev = crtc->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2169
6b8e6ed0
CW		 2170 if (dev_priv->display.disable_fbc)
2171 dev_priv->display.disable_fbc(dev);
3dec0095 2172 intel_increase_pllclock(crtc);
81255565 2173
6b8e6ed0 2174 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2175}
2176
14667a4b
CW		 2177static int
2178intel_finish_fb(struct drm_framebuffer *old_fb)
2179{
2180 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2181 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2182 bool was_interruptible = dev_priv->mm.interruptible;
2183 int ret;
2184
2185 wait_event(dev_priv->pending_flip_queue,
2186 atomic_read(&dev_priv->mm.wedged) ||
2187 atomic_read(&obj->pending_flip) == 0);
2188
2189 /* Big Hammer, we also need to ensure that any pending
2190 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2191 * current scanout is retired before unpinning the old
2192 * framebuffer.
2193 *
2194 * This should only fail upon a hung GPU, in which case we
2195 * can safely continue.
2196 */
2197 dev_priv->mm.interruptible = false;
2198 ret = i915_gem_object_finish_gpu(obj);
2199 dev_priv->mm.interruptible = was_interruptible;
2200
2201 return ret;
2202}
2203
198598d0
VS		 2204static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2205{
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_master_private *master_priv;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2209
2210 if (!dev->primary->master)
2211 return;
2212
2213 master_priv = dev->primary->master->driver_priv;
2214 if (!master_priv->sarea_priv)
2215 return;
2216
2217 switch (intel_crtc->pipe) {
2218 case 0:
2219 master_priv->sarea_priv->pipeA_x = x;
2220 master_priv->sarea_priv->pipeA_y = y;
2221 break;
2222 case 1:
2223 master_priv->sarea_priv->pipeB_x = x;
2224 master_priv->sarea_priv->pipeB_y = y;
2225 break;
2226 default:
2227 break;
2228 }
2229}
2230
5c3b82e2 2231static int
3c4fdcfb 2232intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2233 struct drm_framebuffer *fb)
79e53945
JB		 2234{
2235 struct drm_device *dev = crtc->dev;
6b8e6ed0 2236 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2238 struct drm_framebuffer *old_fb;
5c3b82e2 2239 int ret;
79e53945
JB		 2240
2241 /* no fb bound */
94352cf9 2242 if (!fb) {
a5071c2f 2243 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2244 return 0;
2245 }
2246
5826eca5
ED		 2247 if(intel_crtc->plane > dev_priv->num_pipe) {
2248 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2249 intel_crtc->plane,
2250 dev_priv->num_pipe);
5c3b82e2 2251 return -EINVAL;
79e53945
JB		 2252 }
2253
5c3b82e2 2254 mutex_lock(&dev->struct_mutex);
265db958 2255 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2256 to_intel_framebuffer(fb)->obj,
919926ae 2257 NULL);
5c3b82e2
CW		 2258 if (ret != 0) {
2259 mutex_unlock(&dev->struct_mutex);
a5071c2f 2260 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2261 return ret;
2262 }
79e53945 2263
94352cf9
DV		 2264 if (crtc->fb)
2265 intel_finish_fb(crtc->fb);
265db958 2266
94352cf9 2267 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2268 if (ret) {
94352cf9 2269 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2270 mutex_unlock(&dev->struct_mutex);
a5071c2f 2271 DRM_ERROR("failed to update base address\n");
4e6cfefc 2272 return ret;
79e53945 2273 }
3c4fdcfb 2274
94352cf9
DV		 2275 old_fb = crtc->fb;
2276 crtc->fb = fb;
6c4c86f5
DV		 2277 crtc->x = x;
2278 crtc->y = y;
94352cf9 2279
b7f1de28
CW		 2280 if (old_fb) {
2281 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2282 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2283 }
652c393a 2284
6b8e6ed0 2285 intel_update_fbc(dev);
5c3b82e2 2286 mutex_unlock(&dev->struct_mutex);
79e53945 2287
198598d0 2288 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2289
2290 return 0;
79e53945
JB		 2291}
2292
5eddb70b 2293static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2294{
2295 struct drm_device *dev = crtc->dev;
2296 struct drm_i915_private *dev_priv = dev->dev_private;
2297 u32 dpa_ctl;
2298
28c97730 2299 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2300 dpa_ctl = I915_READ(DP_A);
2301 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2302
2303 if (clock < 200000) {
2304 u32 temp;
2305 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2306 /* workaround for 160Mhz:
2307 1) program 0x4600c bits 15:0 = 0x8124
2308 2) program 0x46010 bit 0 = 1
2309 3) program 0x46034 bit 24 = 1
2310 4) program 0x64000 bit 14 = 1
2311 */
2312 temp = I915_READ(0x4600c);
2313 temp &= 0xffff0000;
2314 I915_WRITE(0x4600c, temp | 0x8124);
2315
2316 temp = I915_READ(0x46010);
2317 I915_WRITE(0x46010, temp | 1);
2318
2319 temp = I915_READ(0x46034);
2320 I915_WRITE(0x46034, temp | (1 << 24));
2321 } else {
2322 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2323 }
2324 I915_WRITE(DP_A, dpa_ctl);
2325
5eddb70b 2326 POSTING_READ(DP_A);
32f9d658
ZW		 2327 udelay(500);
2328}
2329
5e84e1a4
ZW		 2330static void intel_fdi_normal_train(struct drm_crtc *crtc)
2331{
2332 struct drm_device *dev = crtc->dev;
2333 struct drm_i915_private *dev_priv = dev->dev_private;
2334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2335 int pipe = intel_crtc->pipe;
2336 u32 reg, temp;
2337
2338 /* enable normal train */
2339 reg = FDI_TX_CTL(pipe);
2340 temp = I915_READ(reg);
61e499bf 2341 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2342 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2343 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2344 } else {
2345 temp &= ~FDI_LINK_TRAIN_NONE;
2346 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2347 }
5e84e1a4
ZW		 2348 I915_WRITE(reg, temp);
2349
2350 reg = FDI_RX_CTL(pipe);
2351 temp = I915_READ(reg);
2352 if (HAS_PCH_CPT(dev)) {
2353 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2354 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2355 } else {
2356 temp &= ~FDI_LINK_TRAIN_NONE;
2357 temp |= FDI_LINK_TRAIN_NONE;
2358 }
2359 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2360
2361 /* wait one idle pattern time */
2362 POSTING_READ(reg);
2363 udelay(1000);
357555c0
JB		 2364
2365 /* IVB wants error correction enabled */
2366 if (IS_IVYBRIDGE(dev))
2367 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2368 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2369}
2370
291427f5
JB		 2371static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2372{
2373 struct drm_i915_private *dev_priv = dev->dev_private;
2374 u32 flags = I915_READ(SOUTH_CHICKEN1);
2375
2376 flags |= FDI_PHASE_SYNC_OVR(pipe);
2377 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2378 flags |= FDI_PHASE_SYNC_EN(pipe);
2379 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2380 POSTING_READ(SOUTH_CHICKEN1);
2381}
2382
01a415fd
DV		 2383static void ivb_modeset_global_resources(struct drm_device *dev)
2384{
2385 struct drm_i915_private *dev_priv = dev->dev_private;
2386 struct intel_crtc *pipe_B_crtc =
2387 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2388 struct intel_crtc *pipe_C_crtc =
2389 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2390 uint32_t temp;
2391
2392 /* When everything is off disable fdi C so that we could enable fdi B
2393 * with all lanes. XXX: This misses the case where a pipe is not using
2394 * any pch resources and so doesn't need any fdi lanes. */
2395 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2396 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2397 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2398
2399 temp = I915_READ(SOUTH_CHICKEN1);
2400 temp &= ~FDI_BC_BIFURCATION_SELECT;
2401 DRM_DEBUG_KMS("disabling fdi C rx\n");
2402 I915_WRITE(SOUTH_CHICKEN1, temp);
2403 }
2404}
2405
8db9d77b
ZW		 2406/* The FDI link training functions for ILK/Ibexpeak. */
2407static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
0fc932b8 2413 int plane = intel_crtc->plane;
5eddb70b 2414 u32 reg, temp, tries;
8db9d77b 2415
0fc932b8
JB		 2416 /* FDI needs bits from pipe & plane first */
2417 assert_pipe_enabled(dev_priv, pipe);
2418 assert_plane_enabled(dev_priv, plane);
2419
e1a44743
AJ		 2420 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2421 for train result */
5eddb70b
CW		 2422 reg = FDI_RX_IMR(pipe);
2423 temp = I915_READ(reg);
e1a44743
AJ		 2424 temp &= ~FDI_RX_SYMBOL_LOCK;
2425 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2426 I915_WRITE(reg, temp);
2427 I915_READ(reg);
e1a44743
AJ		 2428 udelay(150);
2429
8db9d77b 2430 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2431 reg = FDI_TX_CTL(pipe);
2432 temp = I915_READ(reg);
77ffb597
AJ		 2433 temp &= ~(7 << 19);
2434 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2435 temp &= ~FDI_LINK_TRAIN_NONE;
2436 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2437 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2438
5eddb70b
CW		 2439 reg = FDI_RX_CTL(pipe);
2440 temp = I915_READ(reg);
8db9d77b
ZW		 2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2443 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2444
2445 POSTING_READ(reg);
8db9d77b
ZW		 2446 udelay(150);
2447
5b2adf89 2448 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2449 if (HAS_PCH_IBX(dev)) {
2450 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2451 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2452 FDI_RX_PHASE_SYNC_POINTER_EN);
2453 }
5b2adf89 2454
5eddb70b 2455 reg = FDI_RX_IIR(pipe);
e1a44743 2456 for (tries = 0; tries < 5; tries++) {
5eddb70b 2457 temp = I915_READ(reg);
8db9d77b
ZW		 2458 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2459
2460 if ((temp & FDI_RX_BIT_LOCK)) {
2461 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2462 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2463 break;
2464 }
8db9d77b 2465 }
e1a44743 2466 if (tries == 5)
5eddb70b 2467 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2468
2469 /* Train 2 */
5eddb70b
CW		 2470 reg = FDI_TX_CTL(pipe);
2471 temp = I915_READ(reg);
8db9d77b
ZW		 2472 temp &= ~FDI_LINK_TRAIN_NONE;
2473 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2474 I915_WRITE(reg, temp);
8db9d77b 2475
5eddb70b
CW		 2476 reg = FDI_RX_CTL(pipe);
2477 temp = I915_READ(reg);
8db9d77b
ZW		 2478 temp &= ~FDI_LINK_TRAIN_NONE;
2479 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2480 I915_WRITE(reg, temp);
8db9d77b 2481
5eddb70b
CW		 2482 POSTING_READ(reg);
2483 udelay(150);
8db9d77b 2484
5eddb70b 2485 reg = FDI_RX_IIR(pipe);
e1a44743 2486 for (tries = 0; tries < 5; tries++) {
5eddb70b 2487 temp = I915_READ(reg);
8db9d77b
ZW		 2488 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2489
2490 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2491 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2492 DRM_DEBUG_KMS("FDI train 2 done.\n");
2493 break;
2494 }
8db9d77b 2495 }
e1a44743 2496 if (tries == 5)
5eddb70b 2497 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2498
2499 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2500
8db9d77b
ZW		 2501}
2502
0206e353 2503static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2504 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2505 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2506 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2507 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2508};
2509
2510/* The FDI link training functions for SNB/Cougarpoint. */
2511static void gen6_fdi_link_train(struct drm_crtc *crtc)
2512{
2513 struct drm_device *dev = crtc->dev;
2514 struct drm_i915_private *dev_priv = dev->dev_private;
2515 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2516 int pipe = intel_crtc->pipe;
fa37d39e 2517 u32 reg, temp, i, retry;
8db9d77b 2518
e1a44743
AJ		 2519 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2520 for train result */
5eddb70b
CW		 2521 reg = FDI_RX_IMR(pipe);
2522 temp = I915_READ(reg);
e1a44743
AJ		 2523 temp &= ~FDI_RX_SYMBOL_LOCK;
2524 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2525 I915_WRITE(reg, temp);
2526
2527 POSTING_READ(reg);
e1a44743
AJ		 2528 udelay(150);
2529
8db9d77b 2530 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2531 reg = FDI_TX_CTL(pipe);
2532 temp = I915_READ(reg);
77ffb597
AJ		 2533 temp &= ~(7 << 19);
2534 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2538 /* SNB-B */
2539 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2540 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2541
d74cf324
DV		 2542 I915_WRITE(FDI_RX_MISC(pipe),
2543 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2544
5eddb70b
CW		 2545 reg = FDI_RX_CTL(pipe);
2546 temp = I915_READ(reg);
8db9d77b
ZW		 2547 if (HAS_PCH_CPT(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2549 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2550 } else {
2551 temp &= ~FDI_LINK_TRAIN_NONE;
2552 temp |= FDI_LINK_TRAIN_PATTERN_1;
2553 }
5eddb70b
CW		 2554 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2555
2556 POSTING_READ(reg);
8db9d77b
ZW		 2557 udelay(150);
2558
291427f5
JB		 2559 if (HAS_PCH_CPT(dev))
2560 cpt_phase_pointer_enable(dev, pipe);
2561
0206e353 2562 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2563 reg = FDI_TX_CTL(pipe);
2564 temp = I915_READ(reg);
8db9d77b
ZW		 2565 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
8db9d77b
ZW		 2570 udelay(500);
2571
fa37d39e
SP		 2572 for (retry = 0; retry < 5; retry++) {
2573 reg = FDI_RX_IIR(pipe);
2574 temp = I915_READ(reg);
2575 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576 if (temp & FDI_RX_BIT_LOCK) {
2577 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579 break;
2580 }
2581 udelay(50);
8db9d77b 2582 }
fa37d39e
SP		 2583 if (retry < 5)
2584 break;
8db9d77b
ZW		 2585 }
2586 if (i == 4)
5eddb70b 2587 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2588
2589 /* Train 2 */
5eddb70b
CW		 2590 reg = FDI_TX_CTL(pipe);
2591 temp = I915_READ(reg);
8db9d77b
ZW		 2592 temp &= ~FDI_LINK_TRAIN_NONE;
2593 temp |= FDI_LINK_TRAIN_PATTERN_2;
2594 if (IS_GEN6(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 /* SNB-B */
2597 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598 }
5eddb70b 2599 I915_WRITE(reg, temp);
8db9d77b 2600
5eddb70b
CW		 2601 reg = FDI_RX_CTL(pipe);
2602 temp = I915_READ(reg);
8db9d77b
ZW		 2603 if (HAS_PCH_CPT(dev)) {
2604 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606 } else {
2607 temp &= ~FDI_LINK_TRAIN_NONE;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609 }
5eddb70b
CW		 2610 I915_WRITE(reg, temp);
2611
2612 POSTING_READ(reg);
8db9d77b
ZW		 2613 udelay(150);
2614
0206e353 2615 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2616 reg = FDI_TX_CTL(pipe);
2617 temp = I915_READ(reg);
8db9d77b
ZW		 2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
8db9d77b
ZW		 2623 udelay(500);
2624
fa37d39e
SP		 2625 for (retry = 0; retry < 5; retry++) {
2626 reg = FDI_RX_IIR(pipe);
2627 temp = I915_READ(reg);
2628 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629 if (temp & FDI_RX_SYMBOL_LOCK) {
2630 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632 break;
2633 }
2634 udelay(50);
8db9d77b 2635 }
fa37d39e
SP		 2636 if (retry < 5)
2637 break;
8db9d77b
ZW		 2638 }
2639 if (i == 4)
5eddb70b 2640 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2641
2642 DRM_DEBUG_KMS("FDI train done.\n");
2643}
2644
357555c0
JB		 2645/* Manual link training for Ivy Bridge A0 parts */
2646static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651 int pipe = intel_crtc->pipe;
2652 u32 reg, temp, i;
2653
2654 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655 for train result */
2656 reg = FDI_RX_IMR(pipe);
2657 temp = I915_READ(reg);
2658 temp &= ~FDI_RX_SYMBOL_LOCK;
2659 temp &= ~FDI_RX_BIT_LOCK;
2660 I915_WRITE(reg, temp);
2661
2662 POSTING_READ(reg);
2663 udelay(150);
2664
01a415fd
DV		 2665 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666 I915_READ(FDI_RX_IIR(pipe)));
2667
357555c0
JB		 2668 /* enable CPU FDI TX and PCH FDI RX */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~(7 << 19);
2672 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2677 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2678 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
d74cf324
DV		 2680 I915_WRITE(FDI_RX_MISC(pipe),
2681 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
357555c0
JB		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
2685 temp &= ~FDI_LINK_TRAIN_AUTO;
2686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2688 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2689 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691 POSTING_READ(reg);
2692 udelay(150);
2693
291427f5
JB		 2694 if (HAS_PCH_CPT(dev))
2695 cpt_phase_pointer_enable(dev, pipe);
2696
0206e353 2697 for (i = 0; i < 4; i++) {
357555c0
JB		 2698 reg = FDI_TX_CTL(pipe);
2699 temp = I915_READ(reg);
2700 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2701 temp |= snb_b_fdi_train_param[i];
2702 I915_WRITE(reg, temp);
2703
2704 POSTING_READ(reg);
2705 udelay(500);
2706
2707 reg = FDI_RX_IIR(pipe);
2708 temp = I915_READ(reg);
2709 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2710
2711 if (temp & FDI_RX_BIT_LOCK ||
2712 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2713 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2714 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2715 break;
2716 }
2717 }
2718 if (i == 4)
2719 DRM_ERROR("FDI train 1 fail!\n");
2720
2721 /* Train 2 */
2722 reg = FDI_TX_CTL(pipe);
2723 temp = I915_READ(reg);
2724 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2725 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2726 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2727 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2728 I915_WRITE(reg, temp);
2729
2730 reg = FDI_RX_CTL(pipe);
2731 temp = I915_READ(reg);
2732 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2733 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2734 I915_WRITE(reg, temp);
2735
2736 POSTING_READ(reg);
2737 udelay(150);
2738
0206e353 2739 for (i = 0; i < 4; i++) {
357555c0
JB		 2740 reg = FDI_TX_CTL(pipe);
2741 temp = I915_READ(reg);
2742 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2743 temp |= snb_b_fdi_train_param[i];
2744 I915_WRITE(reg, temp);
2745
2746 POSTING_READ(reg);
2747 udelay(500);
2748
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2752
2753 if (temp & FDI_RX_SYMBOL_LOCK) {
2754 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2755 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2756 break;
2757 }
2758 }
2759 if (i == 4)
2760 DRM_ERROR("FDI train 2 fail!\n");
2761
2762 DRM_DEBUG_KMS("FDI train done.\n");
2763}
2764
88cefb6c 2765static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2766{
88cefb6c 2767 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2768 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2769 int pipe = intel_crtc->pipe;
5eddb70b 2770 u32 reg, temp;
79e53945 2771
c64e311e 2772
c98e9dcf 2773 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2777 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2778 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2779 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2780
2781 POSTING_READ(reg);
c98e9dcf
JB		 2782 udelay(200);
2783
2784 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2785 temp = I915_READ(reg);
2786 I915_WRITE(reg, temp | FDI_PCDCLK);
2787
2788 POSTING_READ(reg);
c98e9dcf
JB		 2789 udelay(200);
2790
bf507ef7
ED		 2791 /* On Haswell, the PLL configuration for ports and pipes is handled
2792 * separately, as part of DDI setup */
2793 if (!IS_HASWELL(dev)) {
2794 /* Enable CPU FDI TX PLL, always on for Ironlake */
2795 reg = FDI_TX_CTL(pipe);
2796 temp = I915_READ(reg);
2797 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2798 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2799
bf507ef7
ED		 2800 POSTING_READ(reg);
2801 udelay(100);
2802 }
6be4a607 2803 }
0e23b99d
JB		 2804}
2805
88cefb6c
DV		 2806static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2807{
2808 struct drm_device *dev = intel_crtc->base.dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 int pipe = intel_crtc->pipe;
2811 u32 reg, temp;
2812
2813 /* Switch from PCDclk to Rawclk */
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2817
2818 /* Disable CPU FDI TX PLL */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2822
2823 POSTING_READ(reg);
2824 udelay(100);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2829
2830 /* Wait for the clocks to turn off. */
2831 POSTING_READ(reg);
2832 udelay(100);
2833}
2834
291427f5
JB		 2835static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2836{
2837 struct drm_i915_private *dev_priv = dev->dev_private;
2838 u32 flags = I915_READ(SOUTH_CHICKEN1);
2839
2840 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2841 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2842 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2843 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2844 POSTING_READ(SOUTH_CHICKEN1);
2845}
0fc932b8
JB		 2846static void ironlake_fdi_disable(struct drm_crtc *crtc)
2847{
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp;
2853
2854 /* disable CPU FDI tx and PCH FDI rx */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2858 POSTING_READ(reg);
2859
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~(0x7 << 16);
2863 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2864 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2865
2866 POSTING_READ(reg);
2867 udelay(100);
2868
2869 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2870 if (HAS_PCH_IBX(dev)) {
2871 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2872 I915_WRITE(FDI_RX_CHICKEN(pipe),
2873 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2874 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2875 } else if (HAS_PCH_CPT(dev)) {
2876 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2877 }
0fc932b8
JB		 2878
2879 /* still set train pattern 1 */
2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 temp &= ~FDI_LINK_TRAIN_NONE;
2883 temp |= FDI_LINK_TRAIN_PATTERN_1;
2884 I915_WRITE(reg, temp);
2885
2886 reg = FDI_RX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 if (HAS_PCH_CPT(dev)) {
2889 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2890 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2891 } else {
2892 temp &= ~FDI_LINK_TRAIN_NONE;
2893 temp |= FDI_LINK_TRAIN_PATTERN_1;
2894 }
2895 /* BPC in FDI rx is consistent with that in PIPECONF */
2896 temp &= ~(0x07 << 16);
2897 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2898 I915_WRITE(reg, temp);
2899
2900 POSTING_READ(reg);
2901 udelay(100);
2902}
2903
5bb61643
CW		 2904static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2905{
2906 struct drm_device *dev = crtc->dev;
2907 struct drm_i915_private *dev_priv = dev->dev_private;
2908 unsigned long flags;
2909 bool pending;
2910
2911 if (atomic_read(&dev_priv->mm.wedged))
2912 return false;
2913
2914 spin_lock_irqsave(&dev->event_lock, flags);
2915 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2916 spin_unlock_irqrestore(&dev->event_lock, flags);
2917
2918 return pending;
2919}
2920
e6c3a2a6
CW		 2921static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2922{
0f91128d 2923 struct drm_device *dev = crtc->dev;
5bb61643 2924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2925
2926 if (crtc->fb == NULL)
2927 return;
2928
5bb61643
CW		 2929 wait_event(dev_priv->pending_flip_queue,
2930 !intel_crtc_has_pending_flip(crtc));
2931
0f91128d
CW		 2932 mutex_lock(&dev->struct_mutex);
2933 intel_finish_fb(crtc->fb);
2934 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2935}
2936
fc316cbe 2937static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2938{
2939 struct drm_device *dev = crtc->dev;
228d3e36 2940 struct intel_encoder *intel_encoder;
040484af
JB		 2941
2942 /*
2943 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2944 * must be driven by its own crtc; no sharing is possible.
2945 */
228d3e36 2946 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2947 switch (intel_encoder->type) {
040484af 2948 case INTEL_OUTPUT_EDP:
228d3e36 2949 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2950 return false;
2951 continue;
2952 }
2953 }
2954
2955 return true;
2956}
2957
fc316cbe
PZ		 2958static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2959{
2960 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2961}
2962
e615efe4
ED		 2963/* Program iCLKIP clock to the desired frequency */
2964static void lpt_program_iclkip(struct drm_crtc *crtc)
2965{
2966 struct drm_device *dev = crtc->dev;
2967 struct drm_i915_private *dev_priv = dev->dev_private;
2968 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2969 u32 temp;
2970
2971 /* It is necessary to ungate the pixclk gate prior to programming
2972 * the divisors, and gate it back when it is done.
2973 */
2974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2975
2976 /* Disable SSCCTL */
2977 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2978 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2979 SBI_SSCCTL_DISABLE);
2980
2981 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2982 if (crtc->mode.clock == 20000) {
2983 auxdiv = 1;
2984 divsel = 0x41;
2985 phaseinc = 0x20;
2986 } else {
2987 /* The iCLK virtual clock root frequency is in MHz,
2988 * but the crtc->mode.clock in in KHz. To get the divisors,
2989 * it is necessary to divide one by another, so we
2990 * convert the virtual clock precision to KHz here for higher
2991 * precision.
2992 */
2993 u32 iclk_virtual_root_freq = 172800 * 1000;
2994 u32 iclk_pi_range = 64;
2995 u32 desired_divisor, msb_divisor_value, pi_value;
2996
2997 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2998 msb_divisor_value = desired_divisor / iclk_pi_range;
2999 pi_value = desired_divisor % iclk_pi_range;
3000
3001 auxdiv = 0;
3002 divsel = msb_divisor_value - 2;
3003 phaseinc = pi_value;
3004 }
3005
3006 /* This should not happen with any sane values */
3007 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3008 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3009 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3010 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3011
3012 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3013 crtc->mode.clock,
3014 auxdiv,
3015 divsel,
3016 phasedir,
3017 phaseinc);
3018
3019 /* Program SSCDIVINTPHASE6 */
3020 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3021 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3022 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3023 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3024 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3025 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3026 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3027
3028 intel_sbi_write(dev_priv,
3029 SBI_SSCDIVINTPHASE6,
3030 temp);
3031
3032 /* Program SSCAUXDIV */
3033 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3034 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3035 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3036 intel_sbi_write(dev_priv,
3037 SBI_SSCAUXDIV6,
3038 temp);
3039
3040
3041 /* Enable modulator and associated divider */
3042 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3043 temp &= ~SBI_SSCCTL_DISABLE;
3044 intel_sbi_write(dev_priv,
3045 SBI_SSCCTL6,
3046 temp);
3047
3048 /* Wait for initialization time */
3049 udelay(24);
3050
3051 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3052}
3053
f67a559d
JB		 3054/*
3055 * Enable PCH resources required for PCH ports:
3056 * - PCH PLLs
3057 * - FDI training & RX/TX
3058 * - update transcoder timings
3059 * - DP transcoding bits
3060 * - transcoder
3061 */
3062static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3063{
3064 struct drm_device *dev = crtc->dev;
3065 struct drm_i915_private *dev_priv = dev->dev_private;
3066 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3067 int pipe = intel_crtc->pipe;
ee7b9f93 3068 u32 reg, temp;
2c07245f 3069
e7e164db
CW		 3070 assert_transcoder_disabled(dev_priv, pipe);
3071
cd986abb
DV		 3072 /* Write the TU size bits before fdi link training, so that error
3073 * detection works. */
3074 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3075 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3076
c98e9dcf 3077 /* For PCH output, training FDI link */
674cf967 3078 dev_priv->display.fdi_link_train(crtc);
2c07245f 3079
572deb37
DV		 3080 /* XXX: pch pll's can be enabled any time before we enable the PCH
3081 * transcoder, and we actually should do this to not upset any PCH
3082 * transcoder that already use the clock when we share it.
3083 *
3084 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3085 * unconditionally resets the pll - we need that to have the right LVDS
3086 * enable sequence. */
6f13b7b5
CW		 3087 intel_enable_pch_pll(intel_crtc);
3088
303b81e0 3089 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3090 u32 sel;
4b645f14 3091
c98e9dcf 3092 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3093 switch (pipe) {
3094 default:
3095 case 0:
3096 temp |= TRANSA_DPLL_ENABLE;
3097 sel = TRANSA_DPLLB_SEL;
3098 break;
3099 case 1:
3100 temp |= TRANSB_DPLL_ENABLE;
3101 sel = TRANSB_DPLLB_SEL;
3102 break;
3103 case 2:
3104 temp |= TRANSC_DPLL_ENABLE;
3105 sel = TRANSC_DPLLB_SEL;
3106 break;
d64311ab 3107 }
ee7b9f93
JB		 3108 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3109 temp |= sel;
3110 else
3111 temp &= ~sel;
c98e9dcf 3112 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3113 }
5eddb70b 3114
d9b6cb56
JB		 3115 /* set transcoder timing, panel must allow it */
3116 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3117 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3118 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3119 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3120
5eddb70b
CW		 3121 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3122 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3123 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3124 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3125
303b81e0 3126 intel_fdi_normal_train(crtc);
5e84e1a4 3127
c98e9dcf
JB		 3128 /* For PCH DP, enable TRANS_DP_CTL */
3129 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3130 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3131 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3132 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3133 reg = TRANS_DP_CTL(pipe);
3134 temp = I915_READ(reg);
3135 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3136 TRANS_DP_SYNC_MASK |
3137 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3138 temp |= (TRANS_DP_OUTPUT_ENABLE |
3139 TRANS_DP_ENH_FRAMING);
9325c9f0 3140 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3141
3142 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3143 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3144 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3145 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3146
3147 switch (intel_trans_dp_port_sel(crtc)) {
3148 case PCH_DP_B:
5eddb70b 3149 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3150 break;
3151 case PCH_DP_C:
5eddb70b 3152 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3153 break;
3154 case PCH_DP_D:
5eddb70b 3155 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3156 break;
3157 default:
e95d41e1 3158 BUG();
32f9d658 3159 }
2c07245f 3160
5eddb70b 3161 I915_WRITE(reg, temp);
6be4a607 3162 }
b52eb4dc 3163
040484af 3164 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3165}
3166
1507e5bd
PZ		 3167static void lpt_pch_enable(struct drm_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3172 int pipe = intel_crtc->pipe;
1507e5bd
PZ		 3173
3174 assert_transcoder_disabled(dev_priv, pipe);
3175
3176 /* Write the TU size bits before fdi link training, so that error
3177 * detection works. */
3178 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3179 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3180
3181 /* For PCH output, training FDI link */
3182 dev_priv->display.fdi_link_train(crtc);
3183
3184 /* XXX: pch pll's can be enabled any time before we enable the PCH
3185 * transcoder, and we actually should do this to not upset any PCH
3186 * transcoder that already use the clock when we share it.
3187 *
3188 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3189 * unconditionally resets the pll - we need that to have the right LVDS
3190 * enable sequence. */
3191 intel_enable_pch_pll(intel_crtc);
3192
8c52b5e8 3193 lpt_program_iclkip(crtc);
1507e5bd
PZ		 3194
3195 /* set transcoder timing, panel must allow it */
3196 assert_panel_unlocked(dev_priv, pipe);
3197 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3198 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3199 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3200
3201 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3202 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3203 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3204 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3205
1507e5bd
PZ		 3206 intel_enable_transcoder(dev_priv, pipe);
3207}
3208
ee7b9f93
JB		 3209static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3210{
3211 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3212
3213 if (pll == NULL)
3214 return;
3215
3216 if (pll->refcount == 0) {
3217 WARN(1, "bad PCH PLL refcount\n");
3218 return;
3219 }
3220
3221 --pll->refcount;
3222 intel_crtc->pch_pll = NULL;
3223}
3224
3225static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3226{
3227 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3228 struct intel_pch_pll *pll;
3229 int i;
3230
3231 pll = intel_crtc->pch_pll;
3232 if (pll) {
3233 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3234 intel_crtc->base.base.id, pll->pll_reg);
3235 goto prepare;
3236 }
3237
98b6bd99
DV		 3238 if (HAS_PCH_IBX(dev_priv->dev)) {
3239 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3240 i = intel_crtc->pipe;
3241 pll = &dev_priv->pch_plls[i];
3242
3243 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3244 intel_crtc->base.base.id, pll->pll_reg);
3245
3246 goto found;
3247 }
3248
ee7b9f93
JB		 3249 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3250 pll = &dev_priv->pch_plls[i];
3251
3252 /* Only want to check enabled timings first */
3253 if (pll->refcount == 0)
3254 continue;
3255
3256 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3257 fp == I915_READ(pll->fp0_reg)) {
3258 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3259 intel_crtc->base.base.id,
3260 pll->pll_reg, pll->refcount, pll->active);
3261
3262 goto found;
3263 }
3264 }
3265
3266 /* Ok no matching timings, maybe there's a free one? */
3267 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3268 pll = &dev_priv->pch_plls[i];
3269 if (pll->refcount == 0) {
3270 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3271 intel_crtc->base.base.id, pll->pll_reg);
3272 goto found;
3273 }
3274 }
3275
3276 return NULL;
3277
3278found:
3279 intel_crtc->pch_pll = pll;
3280 pll->refcount++;
3281 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3282prepare: /* separate function? */
3283 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3284
e04c7350
CW		 3285 /* Wait for the clocks to stabilize before rewriting the regs */
3286 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3287 POSTING_READ(pll->pll_reg);
3288 udelay(150);
e04c7350
CW		 3289
3290 I915_WRITE(pll->fp0_reg, fp);
3291 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3292 pll->on = false;
3293 return pll;
3294}
3295
d4270e57
JB		 3296void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3297{
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3300 u32 temp;
3301
3302 temp = I915_READ(dslreg);
3303 udelay(500);
3304 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3305 /* Without this, mode sets may fail silently on FDI */
3306 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3307 udelay(250);
3308 I915_WRITE(tc2reg, 0);
3309 if (wait_for(I915_READ(dslreg) != temp, 5))
3310 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3311 }
3312}
3313
f67a559d
JB		 3314static void ironlake_crtc_enable(struct drm_crtc *crtc)
3315{
3316 struct drm_device *dev = crtc->dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3319 struct intel_encoder *encoder;
f67a559d
JB		 3320 int pipe = intel_crtc->pipe;
3321 int plane = intel_crtc->plane;
3322 u32 temp;
3323 bool is_pch_port;
3324
08a48469
DV		 3325 WARN_ON(!crtc->enabled);
3326
f67a559d
JB		 3327 if (intel_crtc->active)
3328 return;
3329
3330 intel_crtc->active = true;
3331 intel_update_watermarks(dev);
3332
3333 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3334 temp = I915_READ(PCH_LVDS);
3335 if ((temp & LVDS_PORT_EN) == 0)
3336 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3337 }
3338
fc316cbe 3339 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3340
46b6f814 3341 if (is_pch_port) {
fff367c7
DV		 3342 /* Note: FDI PLL enabling _must_ be done before we enable the
3343 * cpu pipes, hence this is separate from all the other fdi/pch
3344 * enabling. */
88cefb6c 3345 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3346 } else {
3347 assert_fdi_tx_disabled(dev_priv, pipe);
3348 assert_fdi_rx_disabled(dev_priv, pipe);
3349 }
f67a559d 3350
bf49ec8c
DV		 3351 for_each_encoder_on_crtc(dev, crtc, encoder)
3352 if (encoder->pre_enable)
3353 encoder->pre_enable(encoder);
3354
f67a559d
JB		 3355 /* Enable panel fitting for LVDS */
3356 if (dev_priv->pch_pf_size &&
3357 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3358 /* Force use of hard-coded filter coefficients
3359 * as some pre-programmed values are broken,
3360 * e.g. x201.
3361 */
9db4a9c7
JB		 3362 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3363 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3364 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3365 }
3366
9c54c0dd
JB		 3367 /*
3368 * On ILK+ LUT must be loaded before the pipe is running but with
3369 * clocks enabled
3370 */
3371 intel_crtc_load_lut(crtc);
3372
f67a559d
JB		 3373 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3374 intel_enable_plane(dev_priv, plane, pipe);
3375
3376 if (is_pch_port)
3377 ironlake_pch_enable(crtc);
c98e9dcf 3378
d1ebd816 3379 mutex_lock(&dev->struct_mutex);
bed4a673 3380 intel_update_fbc(dev);
d1ebd816
BW		 3381 mutex_unlock(&dev->struct_mutex);
3382
6b383a7f 3383 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3384
fa5c73b1
DV		 3385 for_each_encoder_on_crtc(dev, crtc, encoder)
3386 encoder->enable(encoder);
61b77ddd
DV		 3387
3388 if (HAS_PCH_CPT(dev))
3389 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3390
3391 /*
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3397 * happening.
3398 */
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3400}
3401
4f771f10
PZ		 3402static void haswell_crtc_enable(struct drm_crtc *crtc)
3403{
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 struct intel_encoder *encoder;
3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
4f771f10
PZ		 3410 bool is_pch_port;
3411
3412 WARN_ON(!crtc->enabled);
3413
3414 if (intel_crtc->active)
3415 return;
3416
3417 intel_crtc->active = true;
3418 intel_update_watermarks(dev);
3419
fc316cbe 3420 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3421
83616634 3422 if (is_pch_port)
4f771f10 3423 ironlake_fdi_pll_enable(intel_crtc);
4f771f10
PZ		 3424
3425 for_each_encoder_on_crtc(dev, crtc, encoder)
3426 if (encoder->pre_enable)
3427 encoder->pre_enable(encoder);
3428
1f544388 3429 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3430
1f544388
PZ		 3431 /* Enable panel fitting for eDP */
3432 if (dev_priv->pch_pf_size && HAS_eDP) {
4f771f10
PZ		 3433 /* Force use of hard-coded filter coefficients
3434 * as some pre-programmed values are broken,
3435 * e.g. x201.
3436 */
3437 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3438 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3439 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3440 }
3441
3442 /*
3443 * On ILK+ LUT must be loaded before the pipe is running but with
3444 * clocks enabled
3445 */
3446 intel_crtc_load_lut(crtc);
3447
1f544388
PZ		 3448 intel_ddi_set_pipe_settings(crtc);
3449 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3450
3451 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3452 intel_enable_plane(dev_priv, plane, pipe);
3453
3454 if (is_pch_port)
1507e5bd 3455 lpt_pch_enable(crtc);
4f771f10
PZ		 3456
3457 mutex_lock(&dev->struct_mutex);
3458 intel_update_fbc(dev);
3459 mutex_unlock(&dev->struct_mutex);
3460
3461 intel_crtc_update_cursor(crtc, true);
3462
3463 for_each_encoder_on_crtc(dev, crtc, encoder)
3464 encoder->enable(encoder);
3465
4f771f10
PZ		 3466 /*
3467 * There seems to be a race in PCH platform hw (at least on some
3468 * outputs) where an enabled pipe still completes any pageflip right
3469 * away (as if the pipe is off) instead of waiting for vblank. As soon
3470 * as the first vblank happend, everything works as expected. Hence just
3471 * wait for one vblank before returning to avoid strange things
3472 * happening.
3473 */
3474 intel_wait_for_vblank(dev, intel_crtc->pipe);
3475}
3476
6be4a607
JB		 3477static void ironlake_crtc_disable(struct drm_crtc *crtc)
3478{
3479 struct drm_device *dev = crtc->dev;
3480 struct drm_i915_private *dev_priv = dev->dev_private;
3481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3482 struct intel_encoder *encoder;
6be4a607
JB		 3483 int pipe = intel_crtc->pipe;
3484 int plane = intel_crtc->plane;
5eddb70b 3485 u32 reg, temp;
b52eb4dc 3486
ef9c3aee 3487
f7abfe8b
CW		 3488 if (!intel_crtc->active)
3489 return;
3490
ea9d758d
DV		 3491 for_each_encoder_on_crtc(dev, crtc, encoder)
3492 encoder->disable(encoder);
3493
e6c3a2a6 3494 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3495 drm_vblank_off(dev, pipe);
6b383a7f 3496 intel_crtc_update_cursor(crtc, false);
5eddb70b 3497
b24e7179 3498 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3499
973d04f9
CW		 3500 if (dev_priv->cfb_plane == plane)
3501 intel_disable_fbc(dev);
2c07245f 3502
b24e7179 3503 intel_disable_pipe(dev_priv, pipe);
32f9d658 3504
6be4a607 3505 /* Disable PF */
9db4a9c7
JB		 3506 I915_WRITE(PF_CTL(pipe), 0);
3507 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3508
bf49ec8c
DV		 3509 for_each_encoder_on_crtc(dev, crtc, encoder)
3510 if (encoder->post_disable)
3511 encoder->post_disable(encoder);
3512
0fc932b8 3513 ironlake_fdi_disable(crtc);
2c07245f 3514
040484af 3515 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3516
6be4a607
JB		 3517 if (HAS_PCH_CPT(dev)) {
3518 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3519 reg = TRANS_DP_CTL(pipe);
3520 temp = I915_READ(reg);
3521 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3522 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3523 I915_WRITE(reg, temp);
6be4a607
JB		 3524
3525 /* disable DPLL_SEL */
3526 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3527 switch (pipe) {
3528 case 0:
d64311ab 3529 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3530 break;
3531 case 1:
6be4a607 3532 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3533 break;
3534 case 2:
4b645f14 3535 /* C shares PLL A or B */
d64311ab 3536 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3537 break;
3538 default:
3539 BUG(); /* wtf */
3540 }
6be4a607 3541 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3542 }
e3421a18 3543
6be4a607 3544 /* disable PCH DPLL */
ee7b9f93 3545 intel_disable_pch_pll(intel_crtc);
8db9d77b 3546
88cefb6c 3547 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3548
f7abfe8b 3549 intel_crtc->active = false;
6b383a7f 3550 intel_update_watermarks(dev);
d1ebd816
BW		 3551
3552 mutex_lock(&dev->struct_mutex);
6b383a7f 3553 intel_update_fbc(dev);
d1ebd816 3554 mutex_unlock(&dev->struct_mutex);
6be4a607 3555}
1b3c7a47 3556
4f771f10
PZ		 3557static void haswell_crtc_disable(struct drm_crtc *crtc)
3558{
3559 struct drm_device *dev = crtc->dev;
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3562 struct intel_encoder *encoder;
3563 int pipe = intel_crtc->pipe;
3564 int plane = intel_crtc->plane;
ad80a810 3565 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3566 bool is_pch_port;
4f771f10
PZ		 3567
3568 if (!intel_crtc->active)
3569 return;
3570
83616634
PZ		 3571 is_pch_port = haswell_crtc_driving_pch(crtc);
3572
4f771f10
PZ		 3573 for_each_encoder_on_crtc(dev, crtc, encoder)
3574 encoder->disable(encoder);
3575
3576 intel_crtc_wait_for_pending_flips(crtc);
3577 drm_vblank_off(dev, pipe);
3578 intel_crtc_update_cursor(crtc, false);
3579
3580 intel_disable_plane(dev_priv, plane, pipe);
3581
3582 if (dev_priv->cfb_plane == plane)
3583 intel_disable_fbc(dev);
3584
3585 intel_disable_pipe(dev_priv, pipe);
3586
ad80a810 3587 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3588
3589 /* Disable PF */
3590 I915_WRITE(PF_CTL(pipe), 0);
3591 I915_WRITE(PF_WIN_SZ(pipe), 0);
3592
1f544388 3593 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3598
83616634
PZ		 3599 if (is_pch_port) {
3600 ironlake_fdi_disable(crtc);
3601 intel_disable_transcoder(dev_priv, pipe);
3602 intel_disable_pch_pll(intel_crtc);
3603 ironlake_fdi_pll_disable(intel_crtc);
3604 }
4f771f10
PZ		 3605
3606 intel_crtc->active = false;
3607 intel_update_watermarks(dev);
3608
3609 mutex_lock(&dev->struct_mutex);
3610 intel_update_fbc(dev);
3611 mutex_unlock(&dev->struct_mutex);
3612}
3613
ee7b9f93
JB		 3614static void ironlake_crtc_off(struct drm_crtc *crtc)
3615{
3616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3617 intel_put_pch_pll(intel_crtc);
3618}
3619
6441ab5f
PZ		 3620static void haswell_crtc_off(struct drm_crtc *crtc)
3621{
a5c961d1
PZ		 3622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3623
3624 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3625 * start using it. */
3626 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3627
6441ab5f
PZ		 3628 intel_ddi_put_crtc_pll(crtc);
3629}
3630
02e792fb
DV		 3631static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3632{
02e792fb 3633 if (!enable && intel_crtc->overlay) {
23f09ce3 3634 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3635 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3636
23f09ce3 3637 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3638 dev_priv->mm.interruptible = false;
3639 (void) intel_overlay_switch_off(intel_crtc->overlay);
3640 dev_priv->mm.interruptible = true;
23f09ce3 3641 mutex_unlock(&dev->struct_mutex);
02e792fb 3642 }
02e792fb 3643
5dcdbcb0
CW		 3644 /* Let userspace switch the overlay on again. In most cases userspace
3645 * has to recompute where to put it anyway.
3646 */
02e792fb
DV		 3647}
3648
0b8765c6 3649static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3650{
3651 struct drm_device *dev = crtc->dev;
79e53945
JB		 3652 struct drm_i915_private *dev_priv = dev->dev_private;
3653 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3654 struct intel_encoder *encoder;
79e53945 3655 int pipe = intel_crtc->pipe;
80824003 3656 int plane = intel_crtc->plane;
79e53945 3657
08a48469
DV		 3658 WARN_ON(!crtc->enabled);
3659
f7abfe8b
CW		 3660 if (intel_crtc->active)
3661 return;
3662
3663 intel_crtc->active = true;
6b383a7f
CW		 3664 intel_update_watermarks(dev);
3665
63d7bbe9 3666 intel_enable_pll(dev_priv, pipe);
040484af 3667 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3668 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3669
0b8765c6 3670 intel_crtc_load_lut(crtc);
bed4a673 3671 intel_update_fbc(dev);
79e53945 3672
0b8765c6
JB		 3673 /* Give the overlay scaler a chance to enable if it's on this pipe */
3674 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3675 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3676
fa5c73b1
DV		 3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 encoder->enable(encoder);
0b8765c6 3679}
79e53945 3680
0b8765c6
JB		 3681static void i9xx_crtc_disable(struct drm_crtc *crtc)
3682{
3683 struct drm_device *dev = crtc->dev;
3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3686 struct intel_encoder *encoder;
0b8765c6
JB		 3687 int pipe = intel_crtc->pipe;
3688 int plane = intel_crtc->plane;
b690e96c 3689
ef9c3aee 3690
f7abfe8b
CW		 3691 if (!intel_crtc->active)
3692 return;
3693
ea9d758d
DV		 3694 for_each_encoder_on_crtc(dev, crtc, encoder)
3695 encoder->disable(encoder);
3696
0b8765c6 3697 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3698 intel_crtc_wait_for_pending_flips(crtc);
3699 drm_vblank_off(dev, pipe);
0b8765c6 3700 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3701 intel_crtc_update_cursor(crtc, false);
0b8765c6 3702
973d04f9
CW		 3703 if (dev_priv->cfb_plane == plane)
3704 intel_disable_fbc(dev);
79e53945 3705
b24e7179 3706 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3707 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3708 intel_disable_pll(dev_priv, pipe);
0b8765c6 3709
f7abfe8b 3710 intel_crtc->active = false;
6b383a7f
CW		 3711 intel_update_fbc(dev);
3712 intel_update_watermarks(dev);
0b8765c6
JB		 3713}
3714
ee7b9f93
JB		 3715static void i9xx_crtc_off(struct drm_crtc *crtc)
3716{
3717}
3718
976f8a20
DV		 3719static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3720 bool enabled)
2c07245f
ZW		 3721{
3722 struct drm_device *dev = crtc->dev;
3723 struct drm_i915_master_private *master_priv;
3724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3725 int pipe = intel_crtc->pipe;
79e53945
JB		 3726
3727 if (!dev->primary->master)
3728 return;
3729
3730 master_priv = dev->primary->master->driver_priv;
3731 if (!master_priv->sarea_priv)
3732 return;
3733
79e53945
JB		 3734 switch (pipe) {
3735 case 0:
3736 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3737 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3738 break;
3739 case 1:
3740 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3741 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3742 break;
3743 default:
9db4a9c7 3744 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3745 break;
3746 }
79e53945
JB		 3747}
3748
976f8a20
DV		 3749/**
3750 * Sets the power management mode of the pipe and plane.
3751 */
3752void intel_crtc_update_dpms(struct drm_crtc *crtc)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_encoder *intel_encoder;
3757 bool enable = false;
3758
3759 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3760 enable |= intel_encoder->connectors_active;
3761
3762 if (enable)
3763 dev_priv->display.crtc_enable(crtc);
3764 else
3765 dev_priv->display.crtc_disable(crtc);
3766
3767 intel_crtc_update_sarea(crtc, enable);
3768}
3769
3770static void intel_crtc_noop(struct drm_crtc *crtc)
3771{
3772}
3773
cdd59983
CW		 3774static void intel_crtc_disable(struct drm_crtc *crtc)
3775{
cdd59983 3776 struct drm_device *dev = crtc->dev;
976f8a20 3777 struct drm_connector *connector;
ee7b9f93 3778 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3779
976f8a20
DV		 3780 /* crtc should still be enabled when we disable it. */
3781 WARN_ON(!crtc->enabled);
3782
3783 dev_priv->display.crtc_disable(crtc);
3784 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3785 dev_priv->display.off(crtc);
3786
931872fc
CW		 3787 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3788 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3789
3790 if (crtc->fb) {
3791 mutex_lock(&dev->struct_mutex);
1690e1eb 3792 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3793 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3794 crtc->fb = NULL;
3795 }
3796
3797 /* Update computed state. */
3798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3799 if (!connector->encoder || !connector->encoder->crtc)
3800 continue;
3801
3802 if (connector->encoder->crtc != crtc)
3803 continue;
3804
3805 connector->dpms = DRM_MODE_DPMS_OFF;
3806 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3807 }
3808}
3809
a261b246 3810void intel_modeset_disable(struct drm_device *dev)
79e53945 3811{
a261b246
DV		 3812 struct drm_crtc *crtc;
3813
3814 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3815 if (crtc->enabled)
3816 intel_crtc_disable(crtc);
3817 }
79e53945
JB		 3818}
3819
1f703855 3820void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3821{
7e7d76c3
JB		 3822}
3823
ea5b213a 3824void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3825{
4ef69c7a 3826 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3827
ea5b213a
CW		 3828 drm_encoder_cleanup(encoder);
3829 kfree(intel_encoder);
7e7d76c3
JB		 3830}
3831
5ab432ef
DV		 3832/* Simple dpms helper for encodres with just one connector, no cloning and only
3833 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3834 * state of the entire output pipe. */
3835void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3836{
5ab432ef
DV		 3837 if (mode == DRM_MODE_DPMS_ON) {
3838 encoder->connectors_active = true;
3839
b2cabb0e 3840 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3841 } else {
3842 encoder->connectors_active = false;
3843
b2cabb0e 3844 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3845 }
79e53945
JB		 3846}
3847
0a91ca29
DV		 3848/* Cross check the actual hw state with our own modeset state tracking (and it's
3849 * internal consistency). */
b980514c 3850static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3851{
0a91ca29
DV		 3852 if (connector->get_hw_state(connector)) {
3853 struct intel_encoder *encoder = connector->encoder;
3854 struct drm_crtc *crtc;
3855 bool encoder_enabled;
3856 enum pipe pipe;
3857
3858 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3859 connector->base.base.id,
3860 drm_get_connector_name(&connector->base));
3861
3862 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3863 "wrong connector dpms state\n");
3864 WARN(connector->base.encoder != &encoder->base,
3865 "active connector not linked to encoder\n");
3866 WARN(!encoder->connectors_active,
3867 "encoder->connectors_active not set\n");
3868
3869 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3870 WARN(!encoder_enabled, "encoder not enabled\n");
3871 if (WARN_ON(!encoder->base.crtc))
3872 return;
3873
3874 crtc = encoder->base.crtc;
3875
3876 WARN(!crtc->enabled, "crtc not enabled\n");
3877 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3878 WARN(pipe != to_intel_crtc(crtc)->pipe,
3879 "encoder active on the wrong pipe\n");
3880 }
79e53945
JB		 3881}
3882
5ab432ef
DV		 3883/* Even simpler default implementation, if there's really no special case to
3884 * consider. */
3885void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3886{
5ab432ef 3887 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3888
5ab432ef
DV		 3889 /* All the simple cases only support two dpms states. */
3890 if (mode != DRM_MODE_DPMS_ON)
3891 mode = DRM_MODE_DPMS_OFF;
d4270e57 3892
5ab432ef
DV		 3893 if (mode == connector->dpms)
3894 return;
3895
3896 connector->dpms = mode;
3897
3898 /* Only need to change hw state when actually enabled */
3899 if (encoder->base.crtc)
3900 intel_encoder_dpms(encoder, mode);
3901 else
8af6cf88 3902 WARN_ON(encoder->connectors_active != false);
0a91ca29 3903
b980514c 3904 intel_modeset_check_state(connector->dev);
79e53945
JB		 3905}
3906
f0947c37
DV		 3907/* Simple connector->get_hw_state implementation for encoders that support only
3908 * one connector and no cloning and hence the encoder state determines the state
3909 * of the connector. */
3910bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3911{
24929352 3912 enum pipe pipe = 0;
f0947c37 3913 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3914
f0947c37 3915 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3916}
3917
79e53945 3918static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3919 const struct drm_display_mode *mode,
79e53945
JB		 3920 struct drm_display_mode *adjusted_mode)
3921{
2c07245f 3922 struct drm_device *dev = crtc->dev;
89749350 3923
bad720ff 3924 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3925 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3926 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3927 return false;
2c07245f 3928 }
89749350 3929
f9bef081
DV		 3930 /* All interlaced capable intel hw wants timings in frames. Note though
3931 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3932 * timings, so we need to be careful not to clobber these.*/
3933 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3934 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3935
44f46b42
CW		 3936 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3937 * with a hsync front porch of 0.
3938 */
3939 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3940 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3941 return false;
3942
79e53945
JB		 3943 return true;
3944}
3945
25eb05fc
JB		 3946static int valleyview_get_display_clock_speed(struct drm_device *dev)
3947{
3948 return 400000; /* FIXME */
3949}
3950
e70236a8
JB		 3951static int i945_get_display_clock_speed(struct drm_device *dev)
3952{
3953 return 400000;
3954}
79e53945 3955
e70236a8 3956static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3957{
e70236a8
JB		 3958 return 333000;
3959}
79e53945 3960
e70236a8
JB		 3961static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3962{
3963 return 200000;
3964}
79e53945 3965
e70236a8
JB		 3966static int i915gm_get_display_clock_speed(struct drm_device *dev)
3967{
3968 u16 gcfgc = 0;
79e53945 3969
e70236a8
JB		 3970 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3971
3972 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3973 return 133000;
3974 else {
3975 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3976 case GC_DISPLAY_CLOCK_333_MHZ:
3977 return 333000;
3978 default:
3979 case GC_DISPLAY_CLOCK_190_200_MHZ:
3980 return 190000;
79e53945 3981 }
e70236a8
JB		 3982 }
3983}
3984
3985static int i865_get_display_clock_speed(struct drm_device *dev)
3986{
3987 return 266000;
3988}
3989
3990static int i855_get_display_clock_speed(struct drm_device *dev)
3991{
3992 u16 hpllcc = 0;
3993 /* Assume that the hardware is in the high speed state. This
3994 * should be the default.
3995 */
3996 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3997 case GC_CLOCK_133_200:
3998 case GC_CLOCK_100_200:
3999 return 200000;
4000 case GC_CLOCK_166_250:
4001 return 250000;
4002 case GC_CLOCK_100_133:
79e53945 4003 return 133000;
e70236a8 4004 }
79e53945 4005
e70236a8
JB		 4006 /* Shouldn't happen */
4007 return 0;
4008}
79e53945 4009
e70236a8
JB		 4010static int i830_get_display_clock_speed(struct drm_device *dev)
4011{
4012 return 133000;
79e53945
JB		 4013}
4014
2c07245f
ZW		 4015struct fdi_m_n {
4016 u32 tu;
4017 u32 gmch_m;
4018 u32 gmch_n;
4019 u32 link_m;
4020 u32 link_n;
4021};
4022
4023static void
4024fdi_reduce_ratio(u32 *num, u32 *den)
4025{
4026 while (*num > 0xffffff || *den > 0xffffff) {
4027 *num >>= 1;
4028 *den >>= 1;
4029 }
4030}
4031
2c07245f 4032static void
f2b115e6
AJ		 4033ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4034 int link_clock, struct fdi_m_n *m_n)
2c07245f 4035{
2c07245f
ZW		 4036 m_n->tu = 64; /* default size */
4037
22ed1113
CW		 4038 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4039 m_n->gmch_m = bits_per_pixel * pixel_clock;
4040 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4041 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4042
22ed1113
CW		 4043 m_n->link_m = pixel_clock;
4044 m_n->link_n = link_clock;
2c07245f
ZW		 4045 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4046}
4047
a7615030
CW		 4048static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4049{
72bbe58c
KP		 4050 if (i915_panel_use_ssc >= 0)
4051 return i915_panel_use_ssc != 0;
4052 return dev_priv->lvds_use_ssc
435793df 4053 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4054}
4055
5a354204
JB		 4056/**
4057 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4058 * @crtc: CRTC structure
3b5c78a3 4059 * @mode: requested mode
5a354204
JB		 4060 *
4061 * A pipe may be connected to one or more outputs. Based on the depth of the
4062 * attached framebuffer, choose a good color depth to use on the pipe.
4063 *
4064 * If possible, match the pipe depth to the fb depth. In some cases, this
4065 * isn't ideal, because the connected output supports a lesser or restricted
4066 * set of depths. Resolve that here:
4067 * LVDS typically supports only 6bpc, so clamp down in that case
4068 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4069 * Displays may support a restricted set as well, check EDID and clamp as
4070 * appropriate.
3b5c78a3 4071 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4072 *
4073 * RETURNS:
4074 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4075 * true if they don't match).
4076 */
4077static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4078 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4079 unsigned int *pipe_bpp,
4080 struct drm_display_mode *mode)
5a354204
JB		 4081{
4082 struct drm_device *dev = crtc->dev;
4083 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4084 struct drm_connector *connector;
6c2b7c12 4085 struct intel_encoder *intel_encoder;
5a354204
JB		 4086 unsigned int display_bpc = UINT_MAX, bpc;
4087
4088 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4089 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4090
4091 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4092 unsigned int lvds_bpc;
4093
4094 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4095 LVDS_A3_POWER_UP)
4096 lvds_bpc = 8;
4097 else
4098 lvds_bpc = 6;
4099
4100 if (lvds_bpc < display_bpc) {
82820490 4101 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4102 display_bpc = lvds_bpc;
4103 }
4104 continue;
4105 }
4106
5a354204
JB		 4107 /* Not one of the known troublemakers, check the EDID */
4108 list_for_each_entry(connector, &dev->mode_config.connector_list,
4109 head) {
6c2b7c12 4110 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4111 continue;
4112
62ac41a6
JB		 4113 /* Don't use an invalid EDID bpc value */
4114 if (connector->display_info.bpc &&
4115 connector->display_info.bpc < display_bpc) {
82820490 4116 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4117 display_bpc = connector->display_info.bpc;
4118 }
4119 }
4120
4121 /*
4122 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4123 * through, clamp it down. (Note: >12bpc will be caught below.)
4124 */
4125 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4126 if (display_bpc > 8 && display_bpc < 12) {
82820490 4127 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4128 display_bpc = 12;
4129 } else {
82820490 4130 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4131 display_bpc = 8;
4132 }
4133 }
4134 }
4135
3b5c78a3
AJ		 4136 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4137 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4138 display_bpc = 6;
4139 }
4140
5a354204
JB		 4141 /*
4142 * We could just drive the pipe at the highest bpc all the time and
4143 * enable dithering as needed, but that costs bandwidth. So choose
4144 * the minimum value that expresses the full color range of the fb but
4145 * also stays within the max display bpc discovered above.
4146 */
4147
94352cf9 4148 switch (fb->depth) {
5a354204
JB		 4149 case 8:
4150 bpc = 8; /* since we go through a colormap */
4151 break;
4152 case 15:
4153 case 16:
4154 bpc = 6; /* min is 18bpp */
4155 break;
4156 case 24:
578393cd 4157 bpc = 8;
5a354204
JB		 4158 break;
4159 case 30:
578393cd 4160 bpc = 10;
5a354204
JB		 4161 break;
4162 case 48:
578393cd 4163 bpc = 12;
5a354204
JB		 4164 break;
4165 default:
4166 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4167 bpc = min((unsigned int)8, display_bpc);
4168 break;
4169 }
4170
578393cd
KP		 4171 display_bpc = min(display_bpc, bpc);
4172
82820490
AJ		 4173 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4174 bpc, display_bpc);
5a354204 4175
578393cd 4176 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4177
4178 return display_bpc != bpc;
4179}
4180
a0c4da24
JB		 4181static int vlv_get_refclk(struct drm_crtc *crtc)
4182{
4183 struct drm_device *dev = crtc->dev;
4184 struct drm_i915_private *dev_priv = dev->dev_private;
4185 int refclk = 27000; /* for DP & HDMI */
4186
4187 return 100000; /* only one validated so far */
4188
4189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4190 refclk = 96000;
4191 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4192 if (intel_panel_use_ssc(dev_priv))
4193 refclk = 100000;
4194 else
4195 refclk = 96000;
4196 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4197 refclk = 100000;
4198 }
4199
4200 return refclk;
4201}
4202
c65d77d8
JB		 4203static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4204{
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 int refclk;
4208
a0c4da24
JB		 4209 if (IS_VALLEYVIEW(dev)) {
4210 refclk = vlv_get_refclk(crtc);
4211 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4212 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4213 refclk = dev_priv->lvds_ssc_freq * 1000;
4214 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4215 refclk / 1000);
4216 } else if (!IS_GEN2(dev)) {
4217 refclk = 96000;
4218 } else {
4219 refclk = 48000;
4220 }
4221
4222 return refclk;
4223}
4224
4225static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4226 intel_clock_t *clock)
4227{
4228 /* SDVO TV has fixed PLL values depend on its clock range,
4229 this mirrors vbios setting. */
4230 if (adjusted_mode->clock >= 100000
4231 && adjusted_mode->clock < 140500) {
4232 clock->p1 = 2;
4233 clock->p2 = 10;
4234 clock->n = 3;
4235 clock->m1 = 16;
4236 clock->m2 = 8;
4237 } else if (adjusted_mode->clock >= 140500
4238 && adjusted_mode->clock <= 200000) {
4239 clock->p1 = 1;
4240 clock->p2 = 10;
4241 clock->n = 6;
4242 clock->m1 = 12;
4243 clock->m2 = 8;
4244 }
4245}
4246
a7516a05
JB		 4247static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4248 intel_clock_t *clock,
4249 intel_clock_t *reduced_clock)
4250{
4251 struct drm_device *dev = crtc->dev;
4252 struct drm_i915_private *dev_priv = dev->dev_private;
4253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4254 int pipe = intel_crtc->pipe;
4255 u32 fp, fp2 = 0;
4256
4257 if (IS_PINEVIEW(dev)) {
4258 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4259 if (reduced_clock)
4260 fp2 = (1 << reduced_clock->n) << 16 |
4261 reduced_clock->m1 << 8 | reduced_clock->m2;
4262 } else {
4263 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4264 if (reduced_clock)
4265 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4266 reduced_clock->m2;
4267 }
4268
4269 I915_WRITE(FP0(pipe), fp);
4270
4271 intel_crtc->lowfreq_avail = false;
4272 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4273 reduced_clock && i915_powersave) {
4274 I915_WRITE(FP1(pipe), fp2);
4275 intel_crtc->lowfreq_avail = true;
4276 } else {
4277 I915_WRITE(FP1(pipe), fp);
4278 }
4279}
4280
93e537a1
DV		 4281static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4282 struct drm_display_mode *adjusted_mode)
4283{
4284 struct drm_device *dev = crtc->dev;
4285 struct drm_i915_private *dev_priv = dev->dev_private;
4286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4287 int pipe = intel_crtc->pipe;
284d5df5 4288 u32 temp;
93e537a1
DV		 4289
4290 temp = I915_READ(LVDS);
4291 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4292 if (pipe == 1) {
4293 temp |= LVDS_PIPEB_SELECT;
4294 } else {
4295 temp &= ~LVDS_PIPEB_SELECT;
4296 }
4297 /* set the corresponsding LVDS_BORDER bit */
4298 temp |= dev_priv->lvds_border_bits;
4299 /* Set the B0-B3 data pairs corresponding to whether we're going to
4300 * set the DPLLs for dual-channel mode or not.
4301 */
4302 if (clock->p2 == 7)
4303 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4304 else
4305 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4306
4307 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4308 * appropriately here, but we need to look more thoroughly into how
4309 * panels behave in the two modes.
4310 */
4311 /* set the dithering flag on LVDS as needed */
4312 if (INTEL_INFO(dev)->gen >= 4) {
4313 if (dev_priv->lvds_dither)
4314 temp |= LVDS_ENABLE_DITHER;
4315 else
4316 temp &= ~LVDS_ENABLE_DITHER;
4317 }
284d5df5 4318 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4319 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4320 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4321 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4322 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4323 I915_WRITE(LVDS, temp);
4324}
4325
a0c4da24
JB		 4326static void vlv_update_pll(struct drm_crtc *crtc,
4327 struct drm_display_mode *mode,
4328 struct drm_display_mode *adjusted_mode,
4329 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4330 int num_connectors)
a0c4da24
JB		 4331{
4332 struct drm_device *dev = crtc->dev;
4333 struct drm_i915_private *dev_priv = dev->dev_private;
4334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4335 int pipe = intel_crtc->pipe;
4336 u32 dpll, mdiv, pdiv;
4337 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4338 bool is_sdvo;
4339 u32 temp;
4340
4341 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4342 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4343
2a8f64ca
VP		 4344 dpll = DPLL_VGA_MODE_DIS;
4345 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4346 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4347 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4348
4349 I915_WRITE(DPLL(pipe), dpll);
4350 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4351
4352 bestn = clock->n;
4353 bestm1 = clock->m1;
4354 bestm2 = clock->m2;
4355 bestp1 = clock->p1;
4356 bestp2 = clock->p2;
4357
2a8f64ca
VP		 4358 /*
4359 * In Valleyview PLL and program lane counter registers are exposed
4360 * through DPIO interface
4361 */
a0c4da24
JB		 4362 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4363 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4364 mdiv |= ((bestn << DPIO_N_SHIFT));
4365 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4366 mdiv |= (1 << DPIO_K_SHIFT);
4367 mdiv |= DPIO_ENABLE_CALIBRATION;
4368 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4369
4370 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4371
2a8f64ca 4372 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4373 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4374 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4375 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4376 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4377
2a8f64ca 4378 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4379
4380 dpll |= DPLL_VCO_ENABLE;
4381 I915_WRITE(DPLL(pipe), dpll);
4382 POSTING_READ(DPLL(pipe));
4383 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4384 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4385
2a8f64ca
VP		 4386 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4387
4388 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4389 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4390
4391 I915_WRITE(DPLL(pipe), dpll);
4392
4393 /* Wait for the clocks to stabilize. */
4394 POSTING_READ(DPLL(pipe));
4395 udelay(150);
a0c4da24 4396
2a8f64ca
VP		 4397 temp = 0;
4398 if (is_sdvo) {
4399 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4400 if (temp > 1)
4401 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4402 else
4403 temp = 0;
a0c4da24 4404 }
2a8f64ca
VP		 4405 I915_WRITE(DPLL_MD(pipe), temp);
4406 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4407
2a8f64ca
VP		 4408 /* Now program lane control registers */
4409 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4410 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4411 {
4412 temp = 0x1000C4;
4413 if(pipe == 1)
4414 temp |= (1 << 21);
4415 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4416 }
4417 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4418 {
4419 temp = 0x1000C4;
4420 if(pipe == 1)
4421 temp |= (1 << 21);
4422 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4423 }
a0c4da24
JB		 4424}
4425
eb1cbe48
DV		 4426static void i9xx_update_pll(struct drm_crtc *crtc,
4427 struct drm_display_mode *mode,
4428 struct drm_display_mode *adjusted_mode,
4429 intel_clock_t *clock, intel_clock_t *reduced_clock,
4430 int num_connectors)
4431{
4432 struct drm_device *dev = crtc->dev;
4433 struct drm_i915_private *dev_priv = dev->dev_private;
4434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435 int pipe = intel_crtc->pipe;
4436 u32 dpll;
4437 bool is_sdvo;
4438
2a8f64ca
VP		 4439 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4440
eb1cbe48
DV		 4441 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4442 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4443
4444 dpll = DPLL_VGA_MODE_DIS;
4445
4446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4447 dpll |= DPLLB_MODE_LVDS;
4448 else
4449 dpll |= DPLLB_MODE_DAC_SERIAL;
4450 if (is_sdvo) {
4451 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4452 if (pixel_multiplier > 1) {
4453 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4454 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4455 }
4456 dpll |= DPLL_DVO_HIGH_SPEED;
4457 }
4458 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4459 dpll |= DPLL_DVO_HIGH_SPEED;
4460
4461 /* compute bitmask from p1 value */
4462 if (IS_PINEVIEW(dev))
4463 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4464 else {
4465 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4466 if (IS_G4X(dev) && reduced_clock)
4467 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4468 }
4469 switch (clock->p2) {
4470 case 5:
4471 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4472 break;
4473 case 7:
4474 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4475 break;
4476 case 10:
4477 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4478 break;
4479 case 14:
4480 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4481 break;
4482 }
4483 if (INTEL_INFO(dev)->gen >= 4)
4484 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4485
4486 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4487 dpll |= PLL_REF_INPUT_TVCLKINBC;
4488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4489 /* XXX: just matching BIOS for now */
4490 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4491 dpll |= 3;
4492 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4493 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4494 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4495 else
4496 dpll |= PLL_REF_INPUT_DREFCLK;
4497
4498 dpll |= DPLL_VCO_ENABLE;
4499 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4500 POSTING_READ(DPLL(pipe));
4501 udelay(150);
4502
4503 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4504 * This is an exception to the general rule that mode_set doesn't turn
4505 * things on.
4506 */
4507 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4508 intel_update_lvds(crtc, clock, adjusted_mode);
4509
4510 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4511 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4512
4513 I915_WRITE(DPLL(pipe), dpll);
4514
4515 /* Wait for the clocks to stabilize. */
4516 POSTING_READ(DPLL(pipe));
4517 udelay(150);
4518
4519 if (INTEL_INFO(dev)->gen >= 4) {
4520 u32 temp = 0;
4521 if (is_sdvo) {
4522 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4523 if (temp > 1)
4524 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4525 else
4526 temp = 0;
4527 }
4528 I915_WRITE(DPLL_MD(pipe), temp);
4529 } else {
4530 /* The pixel multiplier can only be updated once the
4531 * DPLL is enabled and the clocks are stable.
4532 *
4533 * So write it again.
4534 */
4535 I915_WRITE(DPLL(pipe), dpll);
4536 }
4537}
4538
4539static void i8xx_update_pll(struct drm_crtc *crtc,
4540 struct drm_display_mode *adjusted_mode,
2a8f64ca 4541 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4542 int num_connectors)
4543{
4544 struct drm_device *dev = crtc->dev;
4545 struct drm_i915_private *dev_priv = dev->dev_private;
4546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4547 int pipe = intel_crtc->pipe;
4548 u32 dpll;
4549
2a8f64ca
VP		 4550 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4551
eb1cbe48
DV		 4552 dpll = DPLL_VGA_MODE_DIS;
4553
4554 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4556 } else {
4557 if (clock->p1 == 2)
4558 dpll |= PLL_P1_DIVIDE_BY_TWO;
4559 else
4560 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4561 if (clock->p2 == 4)
4562 dpll |= PLL_P2_DIVIDE_BY_4;
4563 }
4564
4565 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4566 /* XXX: just matching BIOS for now */
4567 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4568 dpll |= 3;
4569 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4570 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4571 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4572 else
4573 dpll |= PLL_REF_INPUT_DREFCLK;
4574
4575 dpll |= DPLL_VCO_ENABLE;
4576 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4577 POSTING_READ(DPLL(pipe));
4578 udelay(150);
4579
eb1cbe48
DV		 4580 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4581 * This is an exception to the general rule that mode_set doesn't turn
4582 * things on.
4583 */
4584 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4585 intel_update_lvds(crtc, clock, adjusted_mode);
4586
5b5896e4
DV		 4587 I915_WRITE(DPLL(pipe), dpll);
4588
4589 /* Wait for the clocks to stabilize. */
4590 POSTING_READ(DPLL(pipe));
4591 udelay(150);
4592
eb1cbe48
DV		 4593 /* The pixel multiplier can only be updated once the
4594 * DPLL is enabled and the clocks are stable.
4595 *
4596 * So write it again.
4597 */
4598 I915_WRITE(DPLL(pipe), dpll);
4599}
4600
b0e77b9c
PZ		 4601static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4602 struct drm_display_mode *mode,
4603 struct drm_display_mode *adjusted_mode)
4604{
4605 struct drm_device *dev = intel_crtc->base.dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4608 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4609 uint32_t vsyncshift;
4610
4611 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4612 /* the chip adds 2 halflines automatically */
4613 adjusted_mode->crtc_vtotal -= 1;
4614 adjusted_mode->crtc_vblank_end -= 1;
4615 vsyncshift = adjusted_mode->crtc_hsync_start
4616 - adjusted_mode->crtc_htotal / 2;
4617 } else {
4618 vsyncshift = 0;
4619 }
4620
4621 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4622 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4623
fe2b8f9d 4624 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4625 (adjusted_mode->crtc_hdisplay - 1) |
4626 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4627 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4628 (adjusted_mode->crtc_hblank_start - 1) |
4629 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4630 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4631 (adjusted_mode->crtc_hsync_start - 1) |
4632 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4633
fe2b8f9d 4634 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4635 (adjusted_mode->crtc_vdisplay - 1) |
4636 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4637 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4638 (adjusted_mode->crtc_vblank_start - 1) |
4639 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4640 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4641 (adjusted_mode->crtc_vsync_start - 1) |
4642 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4643
b5e508d4
PZ		 4644 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4645 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4646 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4647 * bits. */
4648 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4649 (pipe == PIPE_B || pipe == PIPE_C))
4650 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4651
b0e77b9c
PZ		 4652 /* pipesrc controls the size that is scaled from, which should
4653 * always be the user's requested size.
4654 */
4655 I915_WRITE(PIPESRC(pipe),
4656 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4657}
4658
f564048e
EA		 4659static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4660 struct drm_display_mode *mode,
4661 struct drm_display_mode *adjusted_mode,
4662 int x, int y,
94352cf9 4663 struct drm_framebuffer *fb)
79e53945
JB		 4664{
4665 struct drm_device *dev = crtc->dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4668 int pipe = intel_crtc->pipe;
80824003 4669 int plane = intel_crtc->plane;
c751ce4f 4670 int refclk, num_connectors = 0;
652c393a 4671 intel_clock_t clock, reduced_clock;
b0e77b9c 4672 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4673 bool ok, has_reduced_clock = false, is_sdvo = false;
4674 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4675 struct intel_encoder *encoder;
d4906093 4676 const intel_limit_t *limit;
5c3b82e2 4677 int ret;
79e53945 4678
6c2b7c12 4679 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4680 switch (encoder->type) {
79e53945
JB		 4681 case INTEL_OUTPUT_LVDS:
4682 is_lvds = true;
4683 break;
4684 case INTEL_OUTPUT_SDVO:
7d57382e 4685 case INTEL_OUTPUT_HDMI:
79e53945 4686 is_sdvo = true;
5eddb70b 4687 if (encoder->needs_tv_clock)
e2f0ba97 4688 is_tv = true;
79e53945 4689 break;
79e53945
JB		 4690 case INTEL_OUTPUT_TVOUT:
4691 is_tv = true;
4692 break;
a4fc5ed6
KP		 4693 case INTEL_OUTPUT_DISPLAYPORT:
4694 is_dp = true;
4695 break;
79e53945 4696 }
43565a06 4697
c751ce4f 4698 num_connectors++;
79e53945
JB		 4699 }
4700
c65d77d8 4701 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4702
d4906093
ML		 4703 /*
4704 * Returns a set of divisors for the desired target clock with the given
4705 * refclk, or FALSE. The returned values represent the clock equation:
4706 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4707 */
1b894b59 4708 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4709 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4710 &clock);
79e53945
JB		 4711 if (!ok) {
4712 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4713 return -EINVAL;
79e53945
JB		 4714 }
4715
cda4b7d3 4716 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4717 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4718
ddc9003c 4719 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4720 /*
4721 * Ensure we match the reduced clock's P to the target clock.
4722 * If the clocks don't match, we can't switch the display clock
4723 * by using the FP0/FP1. In such case we will disable the LVDS
4724 * downclock feature.
4725 */
ddc9003c 4726 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4727 dev_priv->lvds_downclock,
4728 refclk,
cec2f356 4729 &clock,
5eddb70b 4730 &reduced_clock);
7026d4ac
ZW		 4731 }
4732
c65d77d8
JB		 4733 if (is_sdvo && is_tv)
4734 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4735
eb1cbe48 4736 if (IS_GEN2(dev))
2a8f64ca
VP		 4737 i8xx_update_pll(crtc, adjusted_mode, &clock,
4738 has_reduced_clock ? &reduced_clock : NULL,
4739 num_connectors);
a0c4da24 4740 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4741 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4742 has_reduced_clock ? &reduced_clock : NULL,
4743 num_connectors);
79e53945 4744 else
eb1cbe48
DV		 4745 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4746 has_reduced_clock ? &reduced_clock : NULL,
4747 num_connectors);
79e53945
JB		 4748
4749 /* setup pipeconf */
5eddb70b 4750 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4751
4752 /* Set up the display plane register */
4753 dspcntr = DISPPLANE_GAMMA_ENABLE;
4754
929c77fb
EA		 4755 if (pipe == 0)
4756 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4757 else
4758 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4759
a6c45cf0 4760 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4761 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4762 * core speed.
4763 *
4764 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4765 * pipe == 0 check?
4766 */
e70236a8
JB		 4767 if (mode->clock >
4768 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4769 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4770 else
5eddb70b 4771 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4772 }
4773
3b5c78a3
AJ		 4774 /* default to 8bpc */
4775 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4776 if (is_dp) {
0c96c65b 4777 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4778 pipeconf |= PIPECONF_BPP_6 |
4779 PIPECONF_DITHER_EN |
4780 PIPECONF_DITHER_TYPE_SP;
4781 }
4782 }
4783
19c03924
GB		 4784 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4785 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4786 pipeconf |= PIPECONF_BPP_6 |
4787 PIPECONF_ENABLE |
4788 I965_PIPECONF_ACTIVE;
4789 }
4790 }
4791
28c97730 4792 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4793 drm_mode_debug_printmodeline(mode);
4794
a7516a05
JB		 4795 if (HAS_PIPE_CXSR(dev)) {
4796 if (intel_crtc->lowfreq_avail) {
28c97730 4797 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4798 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4799 } else {
28c97730 4800 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4801 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4802 }
4803 }
4804
617cf884 4805 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4806 if (!IS_GEN2(dev) &&
b0e77b9c 4807 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4808 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4809 else
617cf884 4810 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4811
b0e77b9c 4812 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4813
4814 /* pipesrc and dspsize control the size that is scaled from,
4815 * which should always be the user's requested size.
79e53945 4816 */
929c77fb
EA		 4817 I915_WRITE(DSPSIZE(plane),
4818 ((mode->vdisplay - 1) << 16) |
4819 (mode->hdisplay - 1));
4820 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4821
f564048e
EA		 4822 I915_WRITE(PIPECONF(pipe), pipeconf);
4823 POSTING_READ(PIPECONF(pipe));
929c77fb 4824 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4825
4826 intel_wait_for_vblank(dev, pipe);
4827
f564048e
EA		 4828 I915_WRITE(DSPCNTR(plane), dspcntr);
4829 POSTING_READ(DSPCNTR(plane));
4830
94352cf9 4831 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4832
4833 intel_update_watermarks(dev);
4834
f564048e
EA		 4835 return ret;
4836}
4837
9fb526db
KP		 4838/*
4839 * Initialize reference clocks when the driver loads
4840 */
4841void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4842{
4843 struct drm_i915_private *dev_priv = dev->dev_private;
4844 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4845 struct intel_encoder *encoder;
13d83a67
JB		 4846 u32 temp;
4847 bool has_lvds = false;
199e5d79
KP		 4848 bool has_cpu_edp = false;
4849 bool has_pch_edp = false;
4850 bool has_panel = false;
99eb6a01
KP		 4851 bool has_ck505 = false;
4852 bool can_ssc = false;
13d83a67
JB		 4853
4854 /* We need to take the global config into account */
199e5d79
KP		 4855 list_for_each_entry(encoder, &mode_config->encoder_list,
4856 base.head) {
4857 switch (encoder->type) {
4858 case INTEL_OUTPUT_LVDS:
4859 has_panel = true;
4860 has_lvds = true;
4861 break;
4862 case INTEL_OUTPUT_EDP:
4863 has_panel = true;
4864 if (intel_encoder_is_pch_edp(&encoder->base))
4865 has_pch_edp = true;
4866 else
4867 has_cpu_edp = true;
4868 break;
13d83a67
JB		 4869 }
4870 }
4871
99eb6a01
KP		 4872 if (HAS_PCH_IBX(dev)) {
4873 has_ck505 = dev_priv->display_clock_mode;
4874 can_ssc = has_ck505;
4875 } else {
4876 has_ck505 = false;
4877 can_ssc = true;
4878 }
4879
4880 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4881 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4882 has_ck505);
13d83a67
JB		 4883
4884 /* Ironlake: try to setup display ref clock before DPLL
4885 * enabling. This is only under driver's control after
4886 * PCH B stepping, previous chipset stepping should be
4887 * ignoring this setting.
4888 */
4889 temp = I915_READ(PCH_DREF_CONTROL);
4890 /* Always enable nonspread source */
4891 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4892
99eb6a01
KP		 4893 if (has_ck505)
4894 temp |= DREF_NONSPREAD_CK505_ENABLE;
4895 else
4896 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4897
199e5d79
KP		 4898 if (has_panel) {
4899 temp &= ~DREF_SSC_SOURCE_MASK;
4900 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4901
199e5d79 4902 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4903 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4904 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4905 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4906 } else
4907 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4908
4909 /* Get SSC going before enabling the outputs */
4910 I915_WRITE(PCH_DREF_CONTROL, temp);
4911 POSTING_READ(PCH_DREF_CONTROL);
4912 udelay(200);
4913
13d83a67
JB		 4914 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4915
4916 /* Enable CPU source on CPU attached eDP */
199e5d79 4917 if (has_cpu_edp) {
99eb6a01 4918 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4919 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4920 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4921 }
13d83a67
JB		 4922 else
4923 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4924 } else
4925 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4926
4927 I915_WRITE(PCH_DREF_CONTROL, temp);
4928 POSTING_READ(PCH_DREF_CONTROL);
4929 udelay(200);
4930 } else {
4931 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4932
4933 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4934
4935 /* Turn off CPU output */
4936 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4937
4938 I915_WRITE(PCH_DREF_CONTROL, temp);
4939 POSTING_READ(PCH_DREF_CONTROL);
4940 udelay(200);
4941
4942 /* Turn off the SSC source */
4943 temp &= ~DREF_SSC_SOURCE_MASK;
4944 temp |= DREF_SSC_SOURCE_DISABLE;
4945
4946 /* Turn off SSC1 */
4947 temp &= ~ DREF_SSC1_ENABLE;
4948
13d83a67
JB		 4949 I915_WRITE(PCH_DREF_CONTROL, temp);
4950 POSTING_READ(PCH_DREF_CONTROL);
4951 udelay(200);
4952 }
4953}
4954
d9d444cb
JB		 4955static int ironlake_get_refclk(struct drm_crtc *crtc)
4956{
4957 struct drm_device *dev = crtc->dev;
4958 struct drm_i915_private *dev_priv = dev->dev_private;
4959 struct intel_encoder *encoder;
d9d444cb
JB		 4960 struct intel_encoder *edp_encoder = NULL;
4961 int num_connectors = 0;
4962 bool is_lvds = false;
4963
6c2b7c12 4964 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4965 switch (encoder->type) {
4966 case INTEL_OUTPUT_LVDS:
4967 is_lvds = true;
4968 break;
4969 case INTEL_OUTPUT_EDP:
4970 edp_encoder = encoder;
4971 break;
4972 }
4973 num_connectors++;
4974 }
4975
4976 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4977 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4978 dev_priv->lvds_ssc_freq);
4979 return dev_priv->lvds_ssc_freq * 1000;
4980 }
4981
4982 return 120000;
4983}
4984
c8203565
PZ		 4985static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4986 struct drm_display_mode *adjusted_mode,
4987 bool dither)
4988{
4989 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4991 int pipe = intel_crtc->pipe;
4992 uint32_t val;
4993
4994 val = I915_READ(PIPECONF(pipe));
4995
4996 val &= ~PIPE_BPC_MASK;
4997 switch (intel_crtc->bpp) {
4998 case 18:
4999 val |= PIPE_6BPC;
5000 break;
5001 case 24:
5002 val |= PIPE_8BPC;
5003 break;
5004 case 30:
5005 val |= PIPE_10BPC;
5006 break;
5007 case 36:
5008 val |= PIPE_12BPC;
5009 break;
5010 default:
cc769b62
PZ		 5011 /* Case prevented by intel_choose_pipe_bpp_dither. */
5012 BUG();
c8203565
PZ		 5013 }
5014
5015 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5016 if (dither)
5017 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5018
5019 val &= ~PIPECONF_INTERLACE_MASK;
5020 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5021 val |= PIPECONF_INTERLACED_ILK;
5022 else
5023 val |= PIPECONF_PROGRESSIVE;
5024
5025 I915_WRITE(PIPECONF(pipe), val);
5026 POSTING_READ(PIPECONF(pipe));
5027}
5028
ee2b0b38
PZ		 5029static void haswell_set_pipeconf(struct drm_crtc *crtc,
5030 struct drm_display_mode *adjusted_mode,
5031 bool dither)
5032{
5033 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5035 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5036 uint32_t val;
5037
702e7a56 5038 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5039
5040 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5041 if (dither)
5042 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5043
5044 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5045 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5046 val |= PIPECONF_INTERLACED_ILK;
5047 else
5048 val |= PIPECONF_PROGRESSIVE;
5049
702e7a56
PZ		 5050 I915_WRITE(PIPECONF(cpu_transcoder), val);
5051 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5052}
5053
6591c6e4
PZ		 5054static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5055 struct drm_display_mode *adjusted_mode,
5056 intel_clock_t *clock,
5057 bool *has_reduced_clock,
5058 intel_clock_t *reduced_clock)
5059{
5060 struct drm_device *dev = crtc->dev;
5061 struct drm_i915_private *dev_priv = dev->dev_private;
5062 struct intel_encoder *intel_encoder;
5063 int refclk;
5064 const intel_limit_t *limit;
5065 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5066
5067 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5068 switch (intel_encoder->type) {
5069 case INTEL_OUTPUT_LVDS:
5070 is_lvds = true;
5071 break;
5072 case INTEL_OUTPUT_SDVO:
5073 case INTEL_OUTPUT_HDMI:
5074 is_sdvo = true;
5075 if (intel_encoder->needs_tv_clock)
5076 is_tv = true;
5077 break;
5078 case INTEL_OUTPUT_TVOUT:
5079 is_tv = true;
5080 break;
5081 }
5082 }
5083
5084 refclk = ironlake_get_refclk(crtc);
5085
5086 /*
5087 * Returns a set of divisors for the desired target clock with the given
5088 * refclk, or FALSE. The returned values represent the clock equation:
5089 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5090 */
5091 limit = intel_limit(crtc, refclk);
5092 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5093 clock);
5094 if (!ret)
5095 return false;
5096
5097 if (is_lvds && dev_priv->lvds_downclock_avail) {
5098 /*
5099 * Ensure we match the reduced clock's P to the target clock.
5100 * If the clocks don't match, we can't switch the display clock
5101 * by using the FP0/FP1. In such case we will disable the LVDS
5102 * downclock feature.
5103 */
5104 *has_reduced_clock = limit->find_pll(limit, crtc,
5105 dev_priv->lvds_downclock,
5106 refclk,
5107 clock,
5108 reduced_clock);
5109 }
5110
5111 if (is_sdvo && is_tv)
5112 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5113
5114 return true;
5115}
5116
01a415fd
DV		 5117static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5118{
5119 struct drm_i915_private *dev_priv = dev->dev_private;
5120 uint32_t temp;
5121
5122 temp = I915_READ(SOUTH_CHICKEN1);
5123 if (temp & FDI_BC_BIFURCATION_SELECT)
5124 return;
5125
5126 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5127 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5128
5129 temp |= FDI_BC_BIFURCATION_SELECT;
5130 DRM_DEBUG_KMS("enabling fdi C rx\n");
5131 I915_WRITE(SOUTH_CHICKEN1, temp);
5132 POSTING_READ(SOUTH_CHICKEN1);
5133}
5134
5135static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5136{
5137 struct drm_device *dev = intel_crtc->base.dev;
5138 struct drm_i915_private *dev_priv = dev->dev_private;
5139 struct intel_crtc *pipe_B_crtc =
5140 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5141
5142 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5143 intel_crtc->pipe, intel_crtc->fdi_lanes);
5144 if (intel_crtc->fdi_lanes > 4) {
5145 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5146 intel_crtc->pipe, intel_crtc->fdi_lanes);
5147 /* Clamp lanes to avoid programming the hw with bogus values. */
5148 intel_crtc->fdi_lanes = 4;
5149
5150 return false;
5151 }
5152
5153 if (dev_priv->num_pipe == 2)
5154 return true;
5155
5156 switch (intel_crtc->pipe) {
5157 case PIPE_A:
5158 return true;
5159 case PIPE_B:
5160 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5161 intel_crtc->fdi_lanes > 2) {
5162 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5163 intel_crtc->pipe, intel_crtc->fdi_lanes);
5164 /* Clamp lanes to avoid programming the hw with bogus values. */
5165 intel_crtc->fdi_lanes = 2;
5166
5167 return false;
5168 }
5169
5170 if (intel_crtc->fdi_lanes > 2)
5171 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5172 else
5173 cpt_enable_fdi_bc_bifurcation(dev);
5174
5175 return true;
5176 case PIPE_C:
5177 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5178 if (intel_crtc->fdi_lanes > 2) {
5179 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5180 intel_crtc->pipe, intel_crtc->fdi_lanes);
5181 /* Clamp lanes to avoid programming the hw with bogus values. */
5182 intel_crtc->fdi_lanes = 2;
5183
5184 return false;
5185 }
5186 } else {
5187 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5188 return false;
5189 }
5190
5191 cpt_enable_fdi_bc_bifurcation(dev);
5192
5193 return true;
5194 default:
5195 BUG();
5196 }
5197}
5198
f48d8f23
PZ		 5199static void ironlake_set_m_n(struct drm_crtc *crtc,
5200 struct drm_display_mode *mode,
5201 struct drm_display_mode *adjusted_mode)
5202{
5203 struct drm_device *dev = crtc->dev;
5204 struct drm_i915_private *dev_priv = dev->dev_private;
5205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5206 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23
PZ		 5207 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5208 struct fdi_m_n m_n = {0};
5209 int target_clock, pixel_multiplier, lane, link_bw;
5210 bool is_dp = false, is_cpu_edp = false;
5211
5212 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5213 switch (intel_encoder->type) {
5214 case INTEL_OUTPUT_DISPLAYPORT:
5215 is_dp = true;
5216 break;
5217 case INTEL_OUTPUT_EDP:
5218 is_dp = true;
5219 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5220 is_cpu_edp = true;
5221 edp_encoder = intel_encoder;
5222 break;
5223 }
5224 }
5225
5226 /* FDI link */
5227 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5228 lane = 0;
5229 /* CPU eDP doesn't require FDI link, so just set DP M/N
5230 according to current link config */
5231 if (is_cpu_edp) {
5232 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5233 } else {
5234 /* FDI is a binary signal running at ~2.7GHz, encoding
5235 * each output octet as 10 bits. The actual frequency
5236 * is stored as a divider into a 100MHz clock, and the
5237 * mode pixel clock is stored in units of 1KHz.
5238 * Hence the bw of each lane in terms of the mode signal
5239 * is:
5240 */
5241 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5242 }
5243
5244 /* [e]DP over FDI requires target mode clock instead of link clock. */
5245 if (edp_encoder)
5246 target_clock = intel_edp_target_clock(edp_encoder, mode);
5247 else if (is_dp)
5248 target_clock = mode->clock;
5249 else
5250 target_clock = adjusted_mode->clock;
5251
5252 if (!lane) {
5253 /*
5254 * Account for spread spectrum to avoid
5255 * oversubscribing the link. Max center spread
5256 * is 2.5%; use 5% for safety's sake.
5257 */
5258 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5259 lane = bps / (link_bw * 8) + 1;
5260 }
5261
5262 intel_crtc->fdi_lanes = lane;
5263
5264 if (pixel_multiplier > 1)
5265 link_bw *= pixel_multiplier;
5266 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5267 &m_n);
5268
afe2fcf5
PZ		 5269 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5270 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5271 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5272 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5273}
5274
de13a2e3
PZ		 5275static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5276 struct drm_display_mode *adjusted_mode,
5277 intel_clock_t *clock, u32 fp)
79e53945 5278{
de13a2e3 5279 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5280 struct drm_device *dev = crtc->dev;
5281 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5282 struct intel_encoder *intel_encoder;
5283 uint32_t dpll;
5284 int factor, pixel_multiplier, num_connectors = 0;
5285 bool is_lvds = false, is_sdvo = false, is_tv = false;
5286 bool is_dp = false, is_cpu_edp = false;
79e53945 5287
de13a2e3
PZ		 5288 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5289 switch (intel_encoder->type) {
79e53945
JB		 5290 case INTEL_OUTPUT_LVDS:
5291 is_lvds = true;
5292 break;
5293 case INTEL_OUTPUT_SDVO:
7d57382e 5294 case INTEL_OUTPUT_HDMI:
79e53945 5295 is_sdvo = true;
de13a2e3 5296 if (intel_encoder->needs_tv_clock)
e2f0ba97 5297 is_tv = true;
79e53945 5298 break;
79e53945
JB		 5299 case INTEL_OUTPUT_TVOUT:
5300 is_tv = true;
5301 break;
a4fc5ed6
KP		 5302 case INTEL_OUTPUT_DISPLAYPORT:
5303 is_dp = true;
5304 break;
32f9d658 5305 case INTEL_OUTPUT_EDP:
e3aef172 5306 is_dp = true;
de13a2e3 5307 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5308 is_cpu_edp = true;
32f9d658 5309 break;
79e53945 5310 }
43565a06 5311
c751ce4f 5312 num_connectors++;
79e53945
JB		 5313 }
5314
c1858123 5315 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5316 factor = 21;
5317 if (is_lvds) {
5318 if ((intel_panel_use_ssc(dev_priv) &&
5319 dev_priv->lvds_ssc_freq == 100) ||
5320 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5321 factor = 25;
5322 } else if (is_sdvo && is_tv)
5323 factor = 20;
c1858123 5324
de13a2e3 5325 if (clock->m < factor * clock->n)
8febb297 5326 fp |= FP_CB_TUNE;
2c07245f 5327
5eddb70b 5328 dpll = 0;
2c07245f 5329
a07d6787
EA		 5330 if (is_lvds)
5331 dpll |= DPLLB_MODE_LVDS;
5332 else
5333 dpll |= DPLLB_MODE_DAC_SERIAL;
5334 if (is_sdvo) {
de13a2e3 5335 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5336 if (pixel_multiplier > 1) {
5337 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5338 }
a07d6787
EA		 5339 dpll |= DPLL_DVO_HIGH_SPEED;
5340 }
e3aef172 5341 if (is_dp && !is_cpu_edp)
a07d6787 5342 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5343
a07d6787 5344 /* compute bitmask from p1 value */
de13a2e3 5345 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5346 /* also FPA1 */
de13a2e3 5347 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5348
de13a2e3 5349 switch (clock->p2) {
a07d6787
EA		 5350 case 5:
5351 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5352 break;
5353 case 7:
5354 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5355 break;
5356 case 10:
5357 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5358 break;
5359 case 14:
5360 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5361 break;
79e53945
JB		 5362 }
5363
43565a06
KH		 5364 if (is_sdvo && is_tv)
5365 dpll |= PLL_REF_INPUT_TVCLKINBC;
5366 else if (is_tv)
79e53945 5367 /* XXX: just matching BIOS for now */
43565a06 5368 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5369 dpll |= 3;
a7615030 5370 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5371 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5372 else
5373 dpll |= PLL_REF_INPUT_DREFCLK;
5374
de13a2e3
PZ		 5375 return dpll;
5376}
5377
5378static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5379 struct drm_display_mode *mode,
5380 struct drm_display_mode *adjusted_mode,
5381 int x, int y,
5382 struct drm_framebuffer *fb)
5383{
5384 struct drm_device *dev = crtc->dev;
5385 struct drm_i915_private *dev_priv = dev->dev_private;
5386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5387 int pipe = intel_crtc->pipe;
5388 int plane = intel_crtc->plane;
5389 int num_connectors = 0;
5390 intel_clock_t clock, reduced_clock;
5391 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5392 bool ok, has_reduced_clock = false;
5393 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5394 struct intel_encoder *encoder;
5395 u32 temp;
5396 int ret;
01a415fd 5397 bool dither, fdi_config_ok;
de13a2e3
PZ		 5398
5399 for_each_encoder_on_crtc(dev, crtc, encoder) {
5400 switch (encoder->type) {
5401 case INTEL_OUTPUT_LVDS:
5402 is_lvds = true;
5403 break;
de13a2e3
PZ		 5404 case INTEL_OUTPUT_DISPLAYPORT:
5405 is_dp = true;
5406 break;
5407 case INTEL_OUTPUT_EDP:
5408 is_dp = true;
e2f12b07 5409 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5410 is_cpu_edp = true;
5411 break;
5412 }
5413
5414 num_connectors++;
5415 }
5416
5dc5298b
PZ		 5417 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5418 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5419
de13a2e3
PZ		 5420 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5421 &has_reduced_clock, &reduced_clock);
5422 if (!ok) {
5423 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5424 return -EINVAL;
5425 }
5426
5427 /* Ensure that the cursor is valid for the new mode before changing... */
5428 intel_crtc_update_cursor(crtc, true);
5429
5430 /* determine panel color depth */
c8241969
JN		 5431 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5432 adjusted_mode);
de13a2e3
PZ		 5433 if (is_lvds && dev_priv->lvds_dither)
5434 dither = true;
5435
5436 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5437 if (has_reduced_clock)
5438 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5439 reduced_clock.m2;
5440
5441 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5442
f7cb34d4 5443 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5444 drm_mode_debug_printmodeline(mode);
5445
5dc5298b
PZ		 5446 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5447 if (!is_cpu_edp) {
ee7b9f93 5448 struct intel_pch_pll *pll;
4b645f14 5449
ee7b9f93
JB		 5450 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5451 if (pll == NULL) {
5452 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5453 pipe);
4b645f14
JB		 5454 return -EINVAL;
5455 }
ee7b9f93
JB		 5456 } else
5457 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5458
5459 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5460 * This is an exception to the general rule that mode_set doesn't turn
5461 * things on.
5462 */
5463 if (is_lvds) {
fae14981 5464 temp = I915_READ(PCH_LVDS);
5eddb70b 5465 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5466 if (HAS_PCH_CPT(dev)) {
5467 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5468 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5469 } else {
5470 if (pipe == 1)
5471 temp |= LVDS_PIPEB_SELECT;
5472 else
5473 temp &= ~LVDS_PIPEB_SELECT;
5474 }
4b645f14 5475
a3e17eb8 5476 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5477 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5478 /* Set the B0-B3 data pairs corresponding to whether we're going to
5479 * set the DPLLs for dual-channel mode or not.
5480 */
5481 if (clock.p2 == 7)
5eddb70b 5482 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5483 else
5eddb70b 5484 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5485
5486 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5487 * appropriately here, but we need to look more thoroughly into how
5488 * panels behave in the two modes.
5489 */
284d5df5 5490 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5491 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5492 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5493 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5494 temp |= LVDS_VSYNC_POLARITY;
fae14981 5495 I915_WRITE(PCH_LVDS, temp);
79e53945 5496 }
434ed097 5497
e3aef172 5498 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5499 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5500 } else {
8db9d77b 5501 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5502 I915_WRITE(TRANSDATA_M1(pipe), 0);
5503 I915_WRITE(TRANSDATA_N1(pipe), 0);
5504 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5505 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5506 }
79e53945 5507
ee7b9f93
JB		 5508 if (intel_crtc->pch_pll) {
5509 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5510
32f9d658 5511 /* Wait for the clocks to stabilize. */
ee7b9f93 5512 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5513 udelay(150);
5514
8febb297
EA		 5515 /* The pixel multiplier can only be updated once the
5516 * DPLL is enabled and the clocks are stable.
5517 *
5518 * So write it again.
5519 */
ee7b9f93 5520 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5521 }
79e53945 5522
5eddb70b 5523 intel_crtc->lowfreq_avail = false;
ee7b9f93 5524 if (intel_crtc->pch_pll) {
4b645f14 5525 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5526 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5527 intel_crtc->lowfreq_avail = true;
4b645f14 5528 } else {
ee7b9f93 5529 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5530 }
5531 }
5532
b0e77b9c 5533 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
2c07245f 5534
01a415fd
DV		 5535 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5536 * ironlake_check_fdi_lanes. */
f48d8f23 5537 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5538
01a415fd
DV		 5539 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5540
e3aef172 5541 if (is_cpu_edp)
8febb297 5542 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5543
c8203565 5544 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5545
9d0498a2 5546 intel_wait_for_vblank(dev, pipe);
79e53945 5547
a1f9e77e
PZ		 5548 /* Set up the display plane register */
5549 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5550 POSTING_READ(DSPCNTR(plane));
79e53945 5551
94352cf9 5552 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5553
5554 intel_update_watermarks(dev);
5555
1f8eeabf
ED		 5556 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5557
01a415fd 5558 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5559}
5560
09b4ddf9
PZ		 5561static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5562 struct drm_display_mode *mode,
5563 struct drm_display_mode *adjusted_mode,
5564 int x, int y,
5565 struct drm_framebuffer *fb)
5566{
5567 struct drm_device *dev = crtc->dev;
5568 struct drm_i915_private *dev_priv = dev->dev_private;
5569 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5570 int pipe = intel_crtc->pipe;
5571 int plane = intel_crtc->plane;
5572 int num_connectors = 0;
5573 intel_clock_t clock, reduced_clock;
5dc5298b 5574 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5575 bool ok, has_reduced_clock = false;
5576 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5577 struct intel_encoder *encoder;
5578 u32 temp;
5579 int ret;
5580 bool dither;
5581
5582 for_each_encoder_on_crtc(dev, crtc, encoder) {
5583 switch (encoder->type) {
5584 case INTEL_OUTPUT_LVDS:
5585 is_lvds = true;
5586 break;
5587 case INTEL_OUTPUT_DISPLAYPORT:
5588 is_dp = true;
5589 break;
5590 case INTEL_OUTPUT_EDP:
5591 is_dp = true;
5592 if (!intel_encoder_is_pch_edp(&encoder->base))
5593 is_cpu_edp = true;
5594 break;
5595 }
5596
5597 num_connectors++;
5598 }
5599
a5c961d1
PZ		 5600 if (is_cpu_edp)
5601 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5602 else
5603 intel_crtc->cpu_transcoder = pipe;
5604
5dc5298b
PZ		 5605 /* We are not sure yet this won't happen. */
5606 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5607 INTEL_PCH_TYPE(dev));
5608
5609 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5610 num_connectors, pipe_name(pipe));
5611
702e7a56 5612 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5613 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5614
5615 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5616
6441ab5f
PZ		 5617 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5618 return -EINVAL;
5619
5dc5298b
PZ		 5620 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5621 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5622 &has_reduced_clock,
5623 &reduced_clock);
5624 if (!ok) {
5625 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5626 return -EINVAL;
5627 }
09b4ddf9
PZ		 5628 }
5629
5630 /* Ensure that the cursor is valid for the new mode before changing... */
5631 intel_crtc_update_cursor(crtc, true);
5632
5633 /* determine panel color depth */
c8241969
JN		 5634 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5635 adjusted_mode);
09b4ddf9
PZ		 5636 if (is_lvds && dev_priv->lvds_dither)
5637 dither = true;
5638
09b4ddf9
PZ		 5639 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5640 drm_mode_debug_printmodeline(mode);
5641
5dc5298b
PZ		 5642 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5643 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5644 if (has_reduced_clock)
5645 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5646 reduced_clock.m2;
5647
5648 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5649 fp);
5650
5651 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5652 * own on pre-Haswell/LPT generation */
5653 if (!is_cpu_edp) {
5654 struct intel_pch_pll *pll;
5655
5656 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5657 if (pll == NULL) {
5658 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5659 pipe);
5660 return -EINVAL;
5661 }
5662 } else
5663 intel_put_pch_pll(intel_crtc);
09b4ddf9 5664
5dc5298b
PZ		 5665 /* The LVDS pin pair needs to be on before the DPLLs are
5666 * enabled. This is an exception to the general rule that
5667 * mode_set doesn't turn things on.
5668 */
5669 if (is_lvds) {
5670 temp = I915_READ(PCH_LVDS);
5671 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5672 if (HAS_PCH_CPT(dev)) {
5673 temp &= ~PORT_TRANS_SEL_MASK;
5674 temp |= PORT_TRANS_SEL_CPT(pipe);
5675 } else {
5676 if (pipe == 1)
5677 temp |= LVDS_PIPEB_SELECT;
5678 else
5679 temp &= ~LVDS_PIPEB_SELECT;
5680 }
09b4ddf9 5681
5dc5298b
PZ		 5682 /* set the corresponsding LVDS_BORDER bit */
5683 temp |= dev_priv->lvds_border_bits;
5684 /* Set the B0-B3 data pairs corresponding to whether
5685 * we're going to set the DPLLs for dual-channel mode or
5686 * not.
5687 */
5688 if (clock.p2 == 7)
5689 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5690 else
5dc5298b
PZ		 5691 temp &= ~(LVDS_B0B3_POWER_UP |
5692 LVDS_CLKB_POWER_UP);
5693
5694 /* It would be nice to set 24 vs 18-bit mode
5695 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5696 * look more thoroughly into how panels behave in the
5697 * two modes.
5698 */
5699 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5700 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5701 temp |= LVDS_HSYNC_POLARITY;
5702 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5703 temp |= LVDS_VSYNC_POLARITY;
5704 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5705 }
09b4ddf9
PZ		 5706 }
5707
5708 if (is_dp && !is_cpu_edp) {
5709 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5710 } else {
5dc5298b
PZ		 5711 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5712 /* For non-DP output, clear any trans DP clock recovery
5713 * setting.*/
5714 I915_WRITE(TRANSDATA_M1(pipe), 0);
5715 I915_WRITE(TRANSDATA_N1(pipe), 0);
5716 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5717 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5718 }
09b4ddf9
PZ		 5719 }
5720
5721 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5722 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5723 if (intel_crtc->pch_pll) {
5724 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5725
5726 /* Wait for the clocks to stabilize. */
5727 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5728 udelay(150);
5729
5730 /* The pixel multiplier can only be updated once the
5731 * DPLL is enabled and the clocks are stable.
5732 *
5733 * So write it again.
5734 */
5735 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5736 }
5737
5738 if (intel_crtc->pch_pll) {
5739 if (is_lvds && has_reduced_clock && i915_powersave) {
5740 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5741 intel_crtc->lowfreq_avail = true;
5742 } else {
5743 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5744 }
09b4ddf9
PZ		 5745 }
5746 }
5747
5748 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5749
1eb8dfec
PZ		 5750 if (!is_dp || is_cpu_edp)
5751 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5752
5dc5298b
PZ		 5753 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5754 if (is_cpu_edp)
5755 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5756
ee2b0b38 5757 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5758
09b4ddf9
PZ		 5759 /* Set up the display plane register */
5760 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5761 POSTING_READ(DSPCNTR(plane));
5762
5763 ret = intel_pipe_set_base(crtc, x, y, fb);
5764
5765 intel_update_watermarks(dev);
5766
5767 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5768
5769 return ret;
5770}
5771
f564048e
EA		 5772static int intel_crtc_mode_set(struct drm_crtc *crtc,
5773 struct drm_display_mode *mode,
5774 struct drm_display_mode *adjusted_mode,
5775 int x, int y,
94352cf9 5776 struct drm_framebuffer *fb)
f564048e
EA		 5777{
5778 struct drm_device *dev = crtc->dev;
5779 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5780 struct drm_encoder_helper_funcs *encoder_funcs;
5781 struct intel_encoder *encoder;
0b701d27
EA		 5782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5783 int pipe = intel_crtc->pipe;
f564048e
EA		 5784 int ret;
5785
0b701d27 5786 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5787
f564048e 5788 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5789 x, y, fb);
79e53945 5790 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5791
9256aa19
DV		 5792 if (ret != 0)
5793 return ret;
5794
5795 for_each_encoder_on_crtc(dev, crtc, encoder) {
5796 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5797 encoder->base.base.id,
5798 drm_get_encoder_name(&encoder->base),
5799 mode->base.id, mode->name);
5800 encoder_funcs = encoder->base.helper_private;
5801 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5802 }
5803
5804 return 0;
79e53945
JB		 5805}
5806
3a9627f4
WF		 5807static bool intel_eld_uptodate(struct drm_connector *connector,
5808 int reg_eldv, uint32_t bits_eldv,
5809 int reg_elda, uint32_t bits_elda,
5810 int reg_edid)
5811{
5812 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5813 uint8_t *eld = connector->eld;
5814 uint32_t i;
5815
5816 i = I915_READ(reg_eldv);
5817 i &= bits_eldv;
5818
5819 if (!eld[0])
5820 return !i;
5821
5822 if (!i)
5823 return false;
5824
5825 i = I915_READ(reg_elda);
5826 i &= ~bits_elda;
5827 I915_WRITE(reg_elda, i);
5828
5829 for (i = 0; i < eld[2]; i++)
5830 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5831 return false;
5832
5833 return true;
5834}
5835
e0dac65e
WF		 5836static void g4x_write_eld(struct drm_connector *connector,
5837 struct drm_crtc *crtc)
5838{
5839 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5840 uint8_t *eld = connector->eld;
5841 uint32_t eldv;
5842 uint32_t len;
5843 uint32_t i;
5844
5845 i = I915_READ(G4X_AUD_VID_DID);
5846
5847 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5848 eldv = G4X_ELDV_DEVCL_DEVBLC;
5849 else
5850 eldv = G4X_ELDV_DEVCTG;
5851
3a9627f4
WF		 5852 if (intel_eld_uptodate(connector,
5853 G4X_AUD_CNTL_ST, eldv,
5854 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5855 G4X_HDMIW_HDMIEDID))
5856 return;
5857
e0dac65e
WF		 5858 i = I915_READ(G4X_AUD_CNTL_ST);
5859 i &= ~(eldv | G4X_ELD_ADDR);
5860 len = (i >> 9) & 0x1f; /* ELD buffer size */
5861 I915_WRITE(G4X_AUD_CNTL_ST, i);
5862
5863 if (!eld[0])
5864 return;
5865
5866 len = min_t(uint8_t, eld[2], len);
5867 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5868 for (i = 0; i < len; i++)
5869 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5870
5871 i = I915_READ(G4X_AUD_CNTL_ST);
5872 i |= eldv;
5873 I915_WRITE(G4X_AUD_CNTL_ST, i);
5874}
5875
83358c85
WX		 5876static void haswell_write_eld(struct drm_connector *connector,
5877 struct drm_crtc *crtc)
5878{
5879 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5880 uint8_t *eld = connector->eld;
5881 struct drm_device *dev = crtc->dev;
5882 uint32_t eldv;
5883 uint32_t i;
5884 int len;
5885 int pipe = to_intel_crtc(crtc)->pipe;
5886 int tmp;
5887
5888 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5889 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5890 int aud_config = HSW_AUD_CFG(pipe);
5891 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5892
5893
5894 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5895
5896 /* Audio output enable */
5897 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5898 tmp = I915_READ(aud_cntrl_st2);
5899 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5900 I915_WRITE(aud_cntrl_st2, tmp);
5901
5902 /* Wait for 1 vertical blank */
5903 intel_wait_for_vblank(dev, pipe);
5904
5905 /* Set ELD valid state */
5906 tmp = I915_READ(aud_cntrl_st2);
5907 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5908 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5909 I915_WRITE(aud_cntrl_st2, tmp);
5910 tmp = I915_READ(aud_cntrl_st2);
5911 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5912
5913 /* Enable HDMI mode */
5914 tmp = I915_READ(aud_config);
5915 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5916 /* clear N_programing_enable and N_value_index */
5917 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5918 I915_WRITE(aud_config, tmp);
5919
5920 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5921
5922 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5923
5924 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5925 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5926 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5927 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5928 } else
5929 I915_WRITE(aud_config, 0);
5930
5931 if (intel_eld_uptodate(connector,
5932 aud_cntrl_st2, eldv,
5933 aud_cntl_st, IBX_ELD_ADDRESS,
5934 hdmiw_hdmiedid))
5935 return;
5936
5937 i = I915_READ(aud_cntrl_st2);
5938 i &= ~eldv;
5939 I915_WRITE(aud_cntrl_st2, i);
5940
5941 if (!eld[0])
5942 return;
5943
5944 i = I915_READ(aud_cntl_st);
5945 i &= ~IBX_ELD_ADDRESS;
5946 I915_WRITE(aud_cntl_st, i);
5947 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5948 DRM_DEBUG_DRIVER("port num:%d\n", i);
5949
5950 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5951 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5952 for (i = 0; i < len; i++)
5953 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5954
5955 i = I915_READ(aud_cntrl_st2);
5956 i |= eldv;
5957 I915_WRITE(aud_cntrl_st2, i);
5958
5959}
5960
e0dac65e
WF		 5961static void ironlake_write_eld(struct drm_connector *connector,
5962 struct drm_crtc *crtc)
5963{
5964 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5965 uint8_t *eld = connector->eld;
5966 uint32_t eldv;
5967 uint32_t i;
5968 int len;
5969 int hdmiw_hdmiedid;
b6daa025 5970 int aud_config;
e0dac65e
WF		 5971 int aud_cntl_st;
5972 int aud_cntrl_st2;
9b138a83 5973 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5974
b3f33cbf 5975 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5976 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5977 aud_config = IBX_AUD_CFG(pipe);
5978 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5979 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5980 } else {
9b138a83
WX		 5981 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5982 aud_config = CPT_AUD_CFG(pipe);
5983 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5984 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5985 }
5986
9b138a83 5987 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5988
5989 i = I915_READ(aud_cntl_st);
9b138a83 5990 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5991 if (!i) {
5992 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5993 /* operate blindly on all ports */
1202b4c6
WF		 5994 eldv = IBX_ELD_VALIDB;
5995 eldv |= IBX_ELD_VALIDB << 4;
5996 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5997 } else {
5998 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5999 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6000 }
6001
3a9627f4
WF		 6002 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6003 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6004 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6005 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6006 } else
6007 I915_WRITE(aud_config, 0);
e0dac65e 6008
3a9627f4
WF		 6009 if (intel_eld_uptodate(connector,
6010 aud_cntrl_st2, eldv,
6011 aud_cntl_st, IBX_ELD_ADDRESS,
6012 hdmiw_hdmiedid))
6013 return;
6014
e0dac65e
WF		 6015 i = I915_READ(aud_cntrl_st2);
6016 i &= ~eldv;
6017 I915_WRITE(aud_cntrl_st2, i);
6018
6019 if (!eld[0])
6020 return;
6021
e0dac65e 6022 i = I915_READ(aud_cntl_st);
1202b4c6 6023 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6024 I915_WRITE(aud_cntl_st, i);
6025
6026 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6027 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6028 for (i = 0; i < len; i++)
6029 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6030
6031 i = I915_READ(aud_cntrl_st2);
6032 i |= eldv;
6033 I915_WRITE(aud_cntrl_st2, i);
6034}
6035
6036void intel_write_eld(struct drm_encoder *encoder,
6037 struct drm_display_mode *mode)
6038{
6039 struct drm_crtc *crtc = encoder->crtc;
6040 struct drm_connector *connector;
6041 struct drm_device *dev = encoder->dev;
6042 struct drm_i915_private *dev_priv = dev->dev_private;
6043
6044 connector = drm_select_eld(encoder, mode);
6045 if (!connector)
6046 return;
6047
6048 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6049 connector->base.id,
6050 drm_get_connector_name(connector),
6051 connector->encoder->base.id,
6052 drm_get_encoder_name(connector->encoder));
6053
6054 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6055
6056 if (dev_priv->display.write_eld)
6057 dev_priv->display.write_eld(connector, crtc);
6058}
6059
79e53945
JB		 6060/** Loads the palette/gamma unit for the CRTC with the prepared values */
6061void intel_crtc_load_lut(struct drm_crtc *crtc)
6062{
6063 struct drm_device *dev = crtc->dev;
6064 struct drm_i915_private *dev_priv = dev->dev_private;
6065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6066 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6067 int i;
6068
6069 /* The clocks have to be on to load the palette. */
aed3f09d 6070 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6071 return;
6072
f2b115e6 6073 /* use legacy palette for Ironlake */
bad720ff 6074 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6075 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6076
79e53945
JB		 6077 for (i = 0; i < 256; i++) {
6078 I915_WRITE(palreg + 4 * i,
6079 (intel_crtc->lut_r[i] << 16) |
6080 (intel_crtc->lut_g[i] << 8) |
6081 intel_crtc->lut_b[i]);
6082 }
6083}
6084
560b85bb
CW		 6085static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6086{
6087 struct drm_device *dev = crtc->dev;
6088 struct drm_i915_private *dev_priv = dev->dev_private;
6089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6090 bool visible = base != 0;
6091 u32 cntl;
6092
6093 if (intel_crtc->cursor_visible == visible)
6094 return;
6095
9db4a9c7 6096 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6097 if (visible) {
6098 /* On these chipsets we can only modify the base whilst
6099 * the cursor is disabled.
6100 */
9db4a9c7 6101 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6102
6103 cntl &= ~(CURSOR_FORMAT_MASK);
6104 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6105 cntl |= CURSOR_ENABLE |
6106 CURSOR_GAMMA_ENABLE |
6107 CURSOR_FORMAT_ARGB;
6108 } else
6109 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6110 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6111
6112 intel_crtc->cursor_visible = visible;
6113}
6114
6115static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6116{
6117 struct drm_device *dev = crtc->dev;
6118 struct drm_i915_private *dev_priv = dev->dev_private;
6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120 int pipe = intel_crtc->pipe;
6121 bool visible = base != 0;
6122
6123 if (intel_crtc->cursor_visible != visible) {
548f245b 6124 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6125 if (base) {
6126 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6127 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6128 cntl |= pipe << 28; /* Connect to correct pipe */
6129 } else {
6130 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6131 cntl |= CURSOR_MODE_DISABLE;
6132 }
9db4a9c7 6133 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6134
6135 intel_crtc->cursor_visible = visible;
6136 }
6137 /* and commit changes on next vblank */
9db4a9c7 6138 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6139}
6140
65a21cd6
JB		 6141static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6142{
6143 struct drm_device *dev = crtc->dev;
6144 struct drm_i915_private *dev_priv = dev->dev_private;
6145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6146 int pipe = intel_crtc->pipe;
6147 bool visible = base != 0;
6148
6149 if (intel_crtc->cursor_visible != visible) {
6150 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6151 if (base) {
6152 cntl &= ~CURSOR_MODE;
6153 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6154 } else {
6155 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6156 cntl |= CURSOR_MODE_DISABLE;
6157 }
6158 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6159
6160 intel_crtc->cursor_visible = visible;
6161 }
6162 /* and commit changes on next vblank */
6163 I915_WRITE(CURBASE_IVB(pipe), base);
6164}
6165
cda4b7d3 6166/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6167static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6168 bool on)
cda4b7d3
CW		 6169{
6170 struct drm_device *dev = crtc->dev;
6171 struct drm_i915_private *dev_priv = dev->dev_private;
6172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6173 int pipe = intel_crtc->pipe;
6174 int x = intel_crtc->cursor_x;
6175 int y = intel_crtc->cursor_y;
560b85bb 6176 u32 base, pos;
cda4b7d3
CW		 6177 bool visible;
6178
6179 pos = 0;
6180
6b383a7f 6181 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6182 base = intel_crtc->cursor_addr;
6183 if (x > (int) crtc->fb->width)
6184 base = 0;
6185
6186 if (y > (int) crtc->fb->height)
6187 base = 0;
6188 } else
6189 base = 0;
6190
6191 if (x < 0) {
6192 if (x + intel_crtc->cursor_width < 0)
6193 base = 0;
6194
6195 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6196 x = -x;
6197 }
6198 pos |= x << CURSOR_X_SHIFT;
6199
6200 if (y < 0) {
6201 if (y + intel_crtc->cursor_height < 0)
6202 base = 0;
6203
6204 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6205 y = -y;
6206 }
6207 pos |= y << CURSOR_Y_SHIFT;
6208
6209 visible = base != 0;
560b85bb 6210 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6211 return;
6212
0cd83aa9 6213 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6214 I915_WRITE(CURPOS_IVB(pipe), pos);
6215 ivb_update_cursor(crtc, base);
6216 } else {
6217 I915_WRITE(CURPOS(pipe), pos);
6218 if (IS_845G(dev) || IS_I865G(dev))
6219 i845_update_cursor(crtc, base);
6220 else
6221 i9xx_update_cursor(crtc, base);
6222 }
cda4b7d3
CW		 6223}
6224
79e53945 6225static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6226 struct drm_file *file,
79e53945
JB		 6227 uint32_t handle,
6228 uint32_t width, uint32_t height)
6229{
6230 struct drm_device *dev = crtc->dev;
6231 struct drm_i915_private *dev_priv = dev->dev_private;
6232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6233 struct drm_i915_gem_object *obj;
cda4b7d3 6234 uint32_t addr;
3f8bc370 6235 int ret;
79e53945 6236
79e53945
JB		 6237 /* if we want to turn off the cursor ignore width and height */
6238 if (!handle) {
28c97730 6239 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6240 addr = 0;
05394f39 6241 obj = NULL;
5004417d 6242 mutex_lock(&dev->struct_mutex);
3f8bc370 6243 goto finish;
79e53945
JB		 6244 }
6245
6246 /* Currently we only support 64x64 cursors */
6247 if (width != 64 || height != 64) {
6248 DRM_ERROR("we currently only support 64x64 cursors\n");
6249 return -EINVAL;
6250 }
6251
05394f39 6252 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6253 if (&obj->base == NULL)
79e53945
JB		 6254 return -ENOENT;
6255
05394f39 6256 if (obj->base.size < width * height * 4) {
79e53945 6257 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6258 ret = -ENOMEM;
6259 goto fail;
79e53945
JB		 6260 }
6261
71acb5eb 6262 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6263 mutex_lock(&dev->struct_mutex);
b295d1b6 6264 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6265 if (obj->tiling_mode) {
6266 DRM_ERROR("cursor cannot be tiled\n");
6267 ret = -EINVAL;
6268 goto fail_locked;
6269 }
6270
2da3b9b9 6271 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6272 if (ret) {
6273 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6274 goto fail_locked;
e7b526bb
CW		 6275 }
6276
d9e86c0e
CW		 6277 ret = i915_gem_object_put_fence(obj);
6278 if (ret) {
2da3b9b9 6279 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6280 goto fail_unpin;
6281 }
6282
05394f39 6283 addr = obj->gtt_offset;
71acb5eb 6284 } else {
6eeefaf3 6285 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6286 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6287 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6288 align);
71acb5eb
DA		 6289 if (ret) {
6290 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6291 goto fail_locked;
71acb5eb 6292 }
05394f39 6293 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6294 }
6295
a6c45cf0 6296 if (IS_GEN2(dev))
14b60391
JB		 6297 I915_WRITE(CURSIZE, (height << 12) | width);
6298
3f8bc370 6299 finish:
3f8bc370 6300 if (intel_crtc->cursor_bo) {
b295d1b6 6301 if (dev_priv->info->cursor_needs_physical) {
05394f39 6302 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6303 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6304 } else
6305 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6306 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6307 }
80824003 6308
7f9872e0 6309 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6310
6311 intel_crtc->cursor_addr = addr;
05394f39 6312 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6313 intel_crtc->cursor_width = width;
6314 intel_crtc->cursor_height = height;
6315
6b383a7f 6316 intel_crtc_update_cursor(crtc, true);
3f8bc370 6317
79e53945 6318 return 0;
e7b526bb 6319fail_unpin:
05394f39 6320 i915_gem_object_unpin(obj);
7f9872e0 6321fail_locked:
34b8686e 6322 mutex_unlock(&dev->struct_mutex);
bc9025bd 6323fail:
05394f39 6324 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6325 return ret;
79e53945
JB		 6326}
6327
6328static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6329{
79e53945 6330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6331
cda4b7d3
CW		 6332 intel_crtc->cursor_x = x;
6333 intel_crtc->cursor_y = y;
652c393a 6334
6b383a7f 6335 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6336
6337 return 0;
6338}
6339
6340/** Sets the color ramps on behalf of RandR */
6341void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6342 u16 blue, int regno)
6343{
6344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6345
6346 intel_crtc->lut_r[regno] = red >> 8;
6347 intel_crtc->lut_g[regno] = green >> 8;
6348 intel_crtc->lut_b[regno] = blue >> 8;
6349}
6350
b8c00ac5
DA		 6351void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6352 u16 *blue, int regno)
6353{
6354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6355
6356 *red = intel_crtc->lut_r[regno] << 8;
6357 *green = intel_crtc->lut_g[regno] << 8;
6358 *blue = intel_crtc->lut_b[regno] << 8;
6359}
6360
79e53945 6361static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6362 u16 *blue, uint32_t start, uint32_t size)
79e53945 6363{
7203425a 6364 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6366
7203425a 6367 for (i = start; i < end; i++) {
79e53945
JB		 6368 intel_crtc->lut_r[i] = red[i] >> 8;
6369 intel_crtc->lut_g[i] = green[i] >> 8;
6370 intel_crtc->lut_b[i] = blue[i] >> 8;
6371 }
6372
6373 intel_crtc_load_lut(crtc);
6374}
6375
6376/**
6377 * Get a pipe with a simple mode set on it for doing load-based monitor
6378 * detection.
6379 *
6380 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6381 * its requirements. The pipe will be connected to no other encoders.
79e53945 6382 *
c751ce4f 6383 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6384 * configured for it. In the future, it could choose to temporarily disable
6385 * some outputs to free up a pipe for its use.
6386 *
6387 * \return crtc, or NULL if no pipes are available.
6388 */
6389
6390/* VESA 640x480x72Hz mode to set on the pipe */
6391static struct drm_display_mode load_detect_mode = {
6392 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6393 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6394};
6395
d2dff872
CW		 6396static struct drm_framebuffer *
6397intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6398 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6399 struct drm_i915_gem_object *obj)
6400{
6401 struct intel_framebuffer *intel_fb;
6402 int ret;
6403
6404 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6405 if (!intel_fb) {
6406 drm_gem_object_unreference_unlocked(&obj->base);
6407 return ERR_PTR(-ENOMEM);
6408 }
6409
6410 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6411 if (ret) {
6412 drm_gem_object_unreference_unlocked(&obj->base);
6413 kfree(intel_fb);
6414 return ERR_PTR(ret);
6415 }
6416
6417 return &intel_fb->base;
6418}
6419
6420static u32
6421intel_framebuffer_pitch_for_width(int width, int bpp)
6422{
6423 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6424 return ALIGN(pitch, 64);
6425}
6426
6427static u32
6428intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6429{
6430 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6431 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6432}
6433
6434static struct drm_framebuffer *
6435intel_framebuffer_create_for_mode(struct drm_device *dev,
6436 struct drm_display_mode *mode,
6437 int depth, int bpp)
6438{
6439 struct drm_i915_gem_object *obj;
308e5bcb 6440 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6441
6442 obj = i915_gem_alloc_object(dev,
6443 intel_framebuffer_size_for_mode(mode, bpp));
6444 if (obj == NULL)
6445 return ERR_PTR(-ENOMEM);
6446
6447 mode_cmd.width = mode->hdisplay;
6448 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6449 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6450 bpp);
5ca0c34a 6451 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6452
6453 return intel_framebuffer_create(dev, &mode_cmd, obj);
6454}
6455
6456static struct drm_framebuffer *
6457mode_fits_in_fbdev(struct drm_device *dev,
6458 struct drm_display_mode *mode)
6459{
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct drm_i915_gem_object *obj;
6462 struct drm_framebuffer *fb;
6463
6464 if (dev_priv->fbdev == NULL)
6465 return NULL;
6466
6467 obj = dev_priv->fbdev->ifb.obj;
6468 if (obj == NULL)
6469 return NULL;
6470
6471 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6472 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6473 fb->bits_per_pixel))
d2dff872
CW		 6474 return NULL;
6475
01f2c773 6476 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6477 return NULL;
6478
6479 return fb;
6480}
6481
d2434ab7 6482bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6483 struct drm_display_mode *mode,
8261b191 6484 struct intel_load_detect_pipe *old)
79e53945
JB		 6485{
6486 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6487 struct intel_encoder *intel_encoder =
6488 intel_attached_encoder(connector);
79e53945 6489 struct drm_crtc *possible_crtc;
4ef69c7a 6490 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6491 struct drm_crtc *crtc = NULL;
6492 struct drm_device *dev = encoder->dev;
94352cf9 6493 struct drm_framebuffer *fb;
79e53945
JB		 6494 int i = -1;
6495
d2dff872
CW		 6496 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6497 connector->base.id, drm_get_connector_name(connector),
6498 encoder->base.id, drm_get_encoder_name(encoder));
6499
79e53945
JB		 6500 /*
6501 * Algorithm gets a little messy:
7a5e4805 6502 *
79e53945
JB		 6503 * - if the connector already has an assigned crtc, use it (but make
6504 * sure it's on first)
7a5e4805 6505 *
79e53945
JB		 6506 * - try to find the first unused crtc that can drive this connector,
6507 * and use that if we find one
79e53945
JB		 6508 */
6509
6510 /* See if we already have a CRTC for this connector */
6511 if (encoder->crtc) {
6512 crtc = encoder->crtc;
8261b191 6513
24218aac 6514 old->dpms_mode = connector->dpms;
8261b191
CW		 6515 old->load_detect_temp = false;
6516
6517 /* Make sure the crtc and connector are running */
24218aac
DV		 6518 if (connector->dpms != DRM_MODE_DPMS_ON)
6519 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6520
7173188d 6521 return true;
79e53945
JB		 6522 }
6523
6524 /* Find an unused one (if possible) */
6525 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6526 i++;
6527 if (!(encoder->possible_crtcs & (1 << i)))
6528 continue;
6529 if (!possible_crtc->enabled) {
6530 crtc = possible_crtc;
6531 break;
6532 }
79e53945
JB		 6533 }
6534
6535 /*
6536 * If we didn't find an unused CRTC, don't use any.
6537 */
6538 if (!crtc) {
7173188d
CW		 6539 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6540 return false;
79e53945
JB		 6541 }
6542
fc303101
DV		 6543 intel_encoder->new_crtc = to_intel_crtc(crtc);
6544 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6545
6546 intel_crtc = to_intel_crtc(crtc);
24218aac 6547 old->dpms_mode = connector->dpms;
8261b191 6548 old->load_detect_temp = true;
d2dff872 6549 old->release_fb = NULL;
79e53945 6550
6492711d
CW		 6551 if (!mode)
6552 mode = &load_detect_mode;
79e53945 6553
d2dff872
CW		 6554 /* We need a framebuffer large enough to accommodate all accesses
6555 * that the plane may generate whilst we perform load detection.
6556 * We can not rely on the fbcon either being present (we get called
6557 * during its initialisation to detect all boot displays, or it may
6558 * not even exist) or that it is large enough to satisfy the
6559 * requested mode.
6560 */
94352cf9
DV		 6561 fb = mode_fits_in_fbdev(dev, mode);
6562 if (fb == NULL) {
d2dff872 6563 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6564 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6565 old->release_fb = fb;
d2dff872
CW		 6566 } else
6567 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6568 if (IS_ERR(fb)) {
d2dff872 6569 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 6570 goto fail;
79e53945 6571 }
79e53945 6572
94352cf9 6573 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6574 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6575 if (old->release_fb)
6576 old->release_fb->funcs->destroy(old->release_fb);
24218aac 6577 goto fail;
79e53945 6578 }
7173188d 6579
79e53945 6580 /* let the connector get through one full cycle before testing */
9d0498a2 6581 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6582
7173188d 6583 return true;
24218aac
DV		 6584fail:
6585 connector->encoder = NULL;
6586 encoder->crtc = NULL;
24218aac 6587 return false;
79e53945
JB		 6588}
6589
d2434ab7 6590void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6591 struct intel_load_detect_pipe *old)
79e53945 6592{
d2434ab7
DV		 6593 struct intel_encoder *intel_encoder =
6594 intel_attached_encoder(connector);
4ef69c7a 6595 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6596
d2dff872
CW		 6597 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6598 connector->base.id, drm_get_connector_name(connector),
6599 encoder->base.id, drm_get_encoder_name(encoder));
6600
8261b191 6601 if (old->load_detect_temp) {
fc303101
DV		 6602 struct drm_crtc *crtc = encoder->crtc;
6603
6604 to_intel_connector(connector)->new_encoder = NULL;
6605 intel_encoder->new_crtc = NULL;
6606 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6607
6608 if (old->release_fb)
6609 old->release_fb->funcs->destroy(old->release_fb);
6610
0622a53c 6611 return;
79e53945
JB		 6612 }
6613
c751ce4f 6614 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6615 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6616 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6617}
6618
6619/* Returns the clock of the currently programmed mode of the given pipe. */
6620static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6621{
6622 struct drm_i915_private *dev_priv = dev->dev_private;
6623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6624 int pipe = intel_crtc->pipe;
548f245b 6625 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6626 u32 fp;
6627 intel_clock_t clock;
6628
6629 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6630 fp = I915_READ(FP0(pipe));
79e53945 6631 else
39adb7a5 6632 fp = I915_READ(FP1(pipe));
79e53945
JB		 6633
6634 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6635 if (IS_PINEVIEW(dev)) {
6636 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6637 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6638 } else {
6639 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6640 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6641 }
6642
a6c45cf0 6643 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6644 if (IS_PINEVIEW(dev))
6645 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6646 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6647 else
6648 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6649 DPLL_FPA01_P1_POST_DIV_SHIFT);
6650
6651 switch (dpll & DPLL_MODE_MASK) {
6652 case DPLLB_MODE_DAC_SERIAL:
6653 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6654 5 : 10;
6655 break;
6656 case DPLLB_MODE_LVDS:
6657 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6658 7 : 14;
6659 break;
6660 default:
28c97730 6661 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6662 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6663 return 0;
6664 }
6665
6666 /* XXX: Handle the 100Mhz refclk */
2177832f 6667 intel_clock(dev, 96000, &clock);
79e53945
JB		 6668 } else {
6669 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6670
6671 if (is_lvds) {
6672 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6673 DPLL_FPA01_P1_POST_DIV_SHIFT);
6674 clock.p2 = 14;
6675
6676 if ((dpll & PLL_REF_INPUT_MASK) ==
6677 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6678 /* XXX: might not be 66MHz */
2177832f 6679 intel_clock(dev, 66000, &clock);
79e53945 6680 } else
2177832f 6681 intel_clock(dev, 48000, &clock);
79e53945
JB		 6682 } else {
6683 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6684 clock.p1 = 2;
6685 else {
6686 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6687 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6688 }
6689 if (dpll & PLL_P2_DIVIDE_BY_4)
6690 clock.p2 = 4;
6691 else
6692 clock.p2 = 2;
6693
2177832f 6694 intel_clock(dev, 48000, &clock);
79e53945
JB		 6695 }
6696 }
6697
6698 /* XXX: It would be nice to validate the clocks, but we can't reuse
6699 * i830PllIsValid() because it relies on the xf86_config connector
6700 * configuration being accurate, which it isn't necessarily.
6701 */
6702
6703 return clock.dot;
6704}
6705
6706/** Returns the currently programmed mode of the given pipe. */
6707struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6708 struct drm_crtc *crtc)
6709{
548f245b 6710 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6712 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6713 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6714 int htot = I915_READ(HTOTAL(cpu_transcoder));
6715 int hsync = I915_READ(HSYNC(cpu_transcoder));
6716 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6717 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6718
6719 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6720 if (!mode)
6721 return NULL;
6722
6723 mode->clock = intel_crtc_clock_get(dev, crtc);
6724 mode->hdisplay = (htot & 0xffff) + 1;
6725 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6726 mode->hsync_start = (hsync & 0xffff) + 1;
6727 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6728 mode->vdisplay = (vtot & 0xffff) + 1;
6729 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6730 mode->vsync_start = (vsync & 0xffff) + 1;
6731 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6732
6733 drm_mode_set_name(mode);
79e53945
JB		 6734
6735 return mode;
6736}
6737
3dec0095 6738static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6739{
6740 struct drm_device *dev = crtc->dev;
6741 drm_i915_private_t *dev_priv = dev->dev_private;
6742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6743 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6744 int dpll_reg = DPLL(pipe);
6745 int dpll;
652c393a 6746
bad720ff 6747 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6748 return;
6749
6750 if (!dev_priv->lvds_downclock_avail)
6751 return;
6752
dbdc6479 6753 dpll = I915_READ(dpll_reg);
652c393a 6754 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6755 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6756
8ac5a6d5 6757 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6758
6759 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6760 I915_WRITE(dpll_reg, dpll);
9d0498a2 6761 intel_wait_for_vblank(dev, pipe);
dbdc6479 6762
652c393a
JB		 6763 dpll = I915_READ(dpll_reg);
6764 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6765 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6766 }
652c393a
JB		 6767}
6768
6769static void intel_decrease_pllclock(struct drm_crtc *crtc)
6770{
6771 struct drm_device *dev = crtc->dev;
6772 drm_i915_private_t *dev_priv = dev->dev_private;
6773 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6774
bad720ff 6775 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6776 return;
6777
6778 if (!dev_priv->lvds_downclock_avail)
6779 return;
6780
6781 /*
6782 * Since this is called by a timer, we should never get here in
6783 * the manual case.
6784 */
6785 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6786 int pipe = intel_crtc->pipe;
6787 int dpll_reg = DPLL(pipe);
6788 int dpll;
f6e5b160 6789
44d98a61 6790 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6791
8ac5a6d5 6792 assert_panel_unlocked(dev_priv, pipe);
652c393a 6793
dc257cf1 6794 dpll = I915_READ(dpll_reg);
652c393a
JB		 6795 dpll |= DISPLAY_RATE_SELECT_FPA1;
6796 I915_WRITE(dpll_reg, dpll);
9d0498a2 6797 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6798 dpll = I915_READ(dpll_reg);
6799 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6800 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6801 }
6802
6803}
6804
f047e395
CW		 6805void intel_mark_busy(struct drm_device *dev)
6806{
f047e395
CW		 6807 i915_update_gfx_val(dev->dev_private);
6808}
6809
6810void intel_mark_idle(struct drm_device *dev)
652c393a 6811{
f047e395
CW		 6812}
6813
6814void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6815{
6816 struct drm_device *dev = obj->base.dev;
652c393a 6817 struct drm_crtc *crtc;
652c393a
JB		 6818
6819 if (!i915_powersave)
6820 return;
6821
652c393a 6822 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6823 if (!crtc->fb)
6824 continue;
6825
f047e395
CW		 6826 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6827 intel_increase_pllclock(crtc);
652c393a 6828 }
652c393a
JB		 6829}
6830
f047e395 6831void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6832{
f047e395
CW		 6833 struct drm_device *dev = obj->base.dev;
6834 struct drm_crtc *crtc;
652c393a 6835
f047e395 6836 if (!i915_powersave)
acb87dfb
CW		 6837 return;
6838
652c393a
JB		 6839 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6840 if (!crtc->fb)
6841 continue;
6842
f047e395
CW		 6843 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6844 intel_decrease_pllclock(crtc);
652c393a
JB		 6845 }
6846}
6847
79e53945
JB		 6848static void intel_crtc_destroy(struct drm_crtc *crtc)
6849{
6850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6851 struct drm_device *dev = crtc->dev;
6852 struct intel_unpin_work *work;
6853 unsigned long flags;
6854
6855 spin_lock_irqsave(&dev->event_lock, flags);
6856 work = intel_crtc->unpin_work;
6857 intel_crtc->unpin_work = NULL;
6858 spin_unlock_irqrestore(&dev->event_lock, flags);
6859
6860 if (work) {
6861 cancel_work_sync(&work->work);
6862 kfree(work);
6863 }
79e53945
JB		 6864
6865 drm_crtc_cleanup(crtc);
67e77c5a 6866
79e53945
JB		 6867 kfree(intel_crtc);
6868}
6869
6b95a207
KH		 6870static void intel_unpin_work_fn(struct work_struct *__work)
6871{
6872 struct intel_unpin_work *work =
6873 container_of(__work, struct intel_unpin_work, work);
6874
6875 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6876 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6877 drm_gem_object_unreference(&work->pending_flip_obj->base);
6878 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6879
7782de3b 6880 intel_update_fbc(work->dev);
6b95a207
KH		 6881 mutex_unlock(&work->dev->struct_mutex);
6882 kfree(work);
6883}
6884
1afe3e9d 6885static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6886 struct drm_crtc *crtc)
6b95a207
KH		 6887{
6888 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6890 struct intel_unpin_work *work;
05394f39 6891 struct drm_i915_gem_object *obj;
6b95a207 6892 struct drm_pending_vblank_event *e;
95cb1b02 6893 struct timeval tvbl;
6b95a207
KH		 6894 unsigned long flags;
6895
6896 /* Ignore early vblank irqs */
6897 if (intel_crtc == NULL)
6898 return;
6899
6900 spin_lock_irqsave(&dev->event_lock, flags);
6901 work = intel_crtc->unpin_work;
6902 if (work == NULL || !work->pending) {
6903 spin_unlock_irqrestore(&dev->event_lock, flags);
6904 return;
6905 }
6906
6907 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6908
6909 if (work->event) {
6910 e = work->event;
49b14a5c 6911 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df 6912
49b14a5c
MK		 6913 e->event.tv_sec = tvbl.tv_sec;
6914 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6915
6b95a207
KH		 6916 list_add_tail(&e->base.link,
6917 &e->base.file_priv->event_list);
6918 wake_up_interruptible(&e->base.file_priv->event_wait);
6919 }
6920
0af7e4df
MK		 6921 drm_vblank_put(dev, intel_crtc->pipe);
6922
6b95a207
KH		 6923 spin_unlock_irqrestore(&dev->event_lock, flags);
6924
05394f39 6925 obj = work->old_fb_obj;
d9e86c0e 6926
e59f2bac 6927 atomic_clear_mask(1 << intel_crtc->plane,
05394f39 6928 &obj->pending_flip.counter);
d9e86c0e 6929
5bb61643 6930 wake_up(&dev_priv->pending_flip_queue);
6b95a207 6931 schedule_work(&work->work);
e5510fac
JB		 6932
6933 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6934}
6935
1afe3e9d
JB		 6936void intel_finish_page_flip(struct drm_device *dev, int pipe)
6937{
6938 drm_i915_private_t *dev_priv = dev->dev_private;
6939 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6940
49b14a5c 6941 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6942}
6943
6944void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6945{
6946 drm_i915_private_t *dev_priv = dev->dev_private;
6947 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6948
49b14a5c 6949 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6950}
6951
6b95a207
KH		 6952void intel_prepare_page_flip(struct drm_device *dev, int plane)
6953{
6954 drm_i915_private_t *dev_priv = dev->dev_private;
6955 struct intel_crtc *intel_crtc =
6956 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6957 unsigned long flags;
6958
6959 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6960 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6961 if ((++intel_crtc->unpin_work->pending) > 1)
6962 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6963 } else {
6964 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6965 }
6b95a207
KH		 6966 spin_unlock_irqrestore(&dev->event_lock, flags);
6967}
6968
8c9f3aaf
JB		 6969static int intel_gen2_queue_flip(struct drm_device *dev,
6970 struct drm_crtc *crtc,
6971 struct drm_framebuffer *fb,
6972 struct drm_i915_gem_object *obj)
6973{
6974 struct drm_i915_private *dev_priv = dev->dev_private;
6975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6976 u32 flip_mask;
6d90c952 6977 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6978 int ret;
6979
6d90c952 6980 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6981 if (ret)
83d4092b 6982 goto err;
8c9f3aaf 6983
6d90c952 6984 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6985 if (ret)
83d4092b 6986 goto err_unpin;
8c9f3aaf
JB		 6987
6988 /* Can't queue multiple flips, so wait for the previous
6989 * one to finish before executing the next.
6990 */
6991 if (intel_crtc->plane)
6992 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6993 else
6994 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6995 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6996 intel_ring_emit(ring, MI_NOOP);
6997 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6998 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6999 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7000 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7001 intel_ring_emit(ring, 0); /* aux display base address, unused */
7002 intel_ring_advance(ring);
83d4092b
CW		 7003 return 0;
7004
7005err_unpin:
7006 intel_unpin_fb_obj(obj);
7007err:
8c9f3aaf
JB		 7008 return ret;
7009}
7010
7011static int intel_gen3_queue_flip(struct drm_device *dev,
7012 struct drm_crtc *crtc,
7013 struct drm_framebuffer *fb,
7014 struct drm_i915_gem_object *obj)
7015{
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7018 u32 flip_mask;
6d90c952 7019 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7020 int ret;
7021
6d90c952 7022 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7023 if (ret)
83d4092b 7024 goto err;
8c9f3aaf 7025
6d90c952 7026 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7027 if (ret)
83d4092b 7028 goto err_unpin;
8c9f3aaf
JB		 7029
7030 if (intel_crtc->plane)
7031 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7032 else
7033 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7034 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7035 intel_ring_emit(ring, MI_NOOP);
7036 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7037 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7038 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7039 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7040 intel_ring_emit(ring, MI_NOOP);
7041
7042 intel_ring_advance(ring);
83d4092b
CW		 7043 return 0;
7044
7045err_unpin:
7046 intel_unpin_fb_obj(obj);
7047err:
8c9f3aaf
JB		 7048 return ret;
7049}
7050
7051static int intel_gen4_queue_flip(struct drm_device *dev,
7052 struct drm_crtc *crtc,
7053 struct drm_framebuffer *fb,
7054 struct drm_i915_gem_object *obj)
7055{
7056 struct drm_i915_private *dev_priv = dev->dev_private;
7057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7058 uint32_t pf, pipesrc;
6d90c952 7059 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7060 int ret;
7061
6d90c952 7062 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7063 if (ret)
83d4092b 7064 goto err;
8c9f3aaf 7065
6d90c952 7066 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7067 if (ret)
83d4092b 7068 goto err_unpin;
8c9f3aaf
JB		 7069
7070 /* i965+ uses the linear or tiled offsets from the
7071 * Display Registers (which do not change across a page-flip)
7072 * so we need only reprogram the base address.
7073 */
6d90c952
DV		 7074 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7075 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7076 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7077 intel_ring_emit(ring,
7078 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7079 obj->tiling_mode);
8c9f3aaf
JB		 7080
7081 /* XXX Enabling the panel-fitter across page-flip is so far
7082 * untested on non-native modes, so ignore it for now.
7083 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7084 */
7085 pf = 0;
7086 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7087 intel_ring_emit(ring, pf | pipesrc);
7088 intel_ring_advance(ring);
83d4092b
CW		 7089 return 0;
7090
7091err_unpin:
7092 intel_unpin_fb_obj(obj);
7093err:
8c9f3aaf
JB		 7094 return ret;
7095}
7096
7097static int intel_gen6_queue_flip(struct drm_device *dev,
7098 struct drm_crtc *crtc,
7099 struct drm_framebuffer *fb,
7100 struct drm_i915_gem_object *obj)
7101{
7102 struct drm_i915_private *dev_priv = dev->dev_private;
7103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7104 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7105 uint32_t pf, pipesrc;
7106 int ret;
7107
6d90c952 7108 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7109 if (ret)
83d4092b 7110 goto err;
8c9f3aaf 7111
6d90c952 7112 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7113 if (ret)
83d4092b 7114 goto err_unpin;
8c9f3aaf 7115
6d90c952
DV		 7116 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7117 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7118 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7119 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7120
dc257cf1
DV		 7121 /* Contrary to the suggestions in the documentation,
7122 * "Enable Panel Fitter" does not seem to be required when page
7123 * flipping with a non-native mode, and worse causes a normal
7124 * modeset to fail.
7125 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7126 */
7127 pf = 0;
8c9f3aaf 7128 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7129 intel_ring_emit(ring, pf | pipesrc);
7130 intel_ring_advance(ring);
83d4092b
CW		 7131 return 0;
7132
7133err_unpin:
7134 intel_unpin_fb_obj(obj);
7135err:
8c9f3aaf
JB		 7136 return ret;
7137}
7138
7c9017e5
JB		 7139/*
7140 * On gen7 we currently use the blit ring because (in early silicon at least)
7141 * the render ring doesn't give us interrpts for page flip completion, which
7142 * means clients will hang after the first flip is queued. Fortunately the
7143 * blit ring generates interrupts properly, so use it instead.
7144 */
7145static int intel_gen7_queue_flip(struct drm_device *dev,
7146 struct drm_crtc *crtc,
7147 struct drm_framebuffer *fb,
7148 struct drm_i915_gem_object *obj)
7149{
7150 struct drm_i915_private *dev_priv = dev->dev_private;
7151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7152 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7153 uint32_t plane_bit = 0;
7c9017e5
JB		 7154 int ret;
7155
7156 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7157 if (ret)
83d4092b 7158 goto err;
7c9017e5 7159
cb05d8de
DV		 7160 switch(intel_crtc->plane) {
7161 case PLANE_A:
7162 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7163 break;
7164 case PLANE_B:
7165 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7166 break;
7167 case PLANE_C:
7168 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7169 break;
7170 default:
7171 WARN_ONCE(1, "unknown plane in flip command\n");
7172 ret = -ENODEV;
ab3951eb 7173 goto err_unpin;
cb05d8de
DV		 7174 }
7175
7c9017e5
JB		 7176 ret = intel_ring_begin(ring, 4);
7177 if (ret)
83d4092b 7178 goto err_unpin;
7c9017e5 7179
cb05d8de 7180 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7181 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7182 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7183 intel_ring_emit(ring, (MI_NOOP));
7184 intel_ring_advance(ring);
83d4092b
CW		 7185 return 0;
7186
7187err_unpin:
7188 intel_unpin_fb_obj(obj);
7189err:
7c9017e5
JB		 7190 return ret;
7191}
7192
8c9f3aaf
JB		 7193static int intel_default_queue_flip(struct drm_device *dev,
7194 struct drm_crtc *crtc,
7195 struct drm_framebuffer *fb,
7196 struct drm_i915_gem_object *obj)
7197{
7198 return -ENODEV;
7199}
7200
6b95a207
KH		 7201static int intel_crtc_page_flip(struct drm_crtc *crtc,
7202 struct drm_framebuffer *fb,
7203 struct drm_pending_vblank_event *event)
7204{
7205 struct drm_device *dev = crtc->dev;
7206 struct drm_i915_private *dev_priv = dev->dev_private;
7207 struct intel_framebuffer *intel_fb;
05394f39 7208 struct drm_i915_gem_object *obj;
6b95a207
KH		 7209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7210 struct intel_unpin_work *work;
8c9f3aaf 7211 unsigned long flags;
52e68630 7212 int ret;
6b95a207 7213
e6a595d2
VS		 7214 /* Can't change pixel format via MI display flips. */
7215 if (fb->pixel_format != crtc->fb->pixel_format)
7216 return -EINVAL;
7217
7218 /*
7219 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7220 * Note that pitch changes could also affect these register.
7221 */
7222 if (INTEL_INFO(dev)->gen > 3 &&
7223 (fb->offsets[0] != crtc->fb->offsets[0] ||
7224 fb->pitches[0] != crtc->fb->pitches[0]))
7225 return -EINVAL;
7226
6b95a207
KH		 7227 work = kzalloc(sizeof *work, GFP_KERNEL);
7228 if (work == NULL)
7229 return -ENOMEM;
7230
6b95a207
KH		 7231 work->event = event;
7232 work->dev = crtc->dev;
7233 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7234 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7235 INIT_WORK(&work->work, intel_unpin_work_fn);
7236
7317c75e
JB		 7237 ret = drm_vblank_get(dev, intel_crtc->pipe);
7238 if (ret)
7239 goto free_work;
7240
6b95a207
KH		 7241 /* We borrow the event spin lock for protecting unpin_work */
7242 spin_lock_irqsave(&dev->event_lock, flags);
7243 if (intel_crtc->unpin_work) {
7244 spin_unlock_irqrestore(&dev->event_lock, flags);
7245 kfree(work);
7317c75e 7246 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7247
7248 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7249 return -EBUSY;
7250 }
7251 intel_crtc->unpin_work = work;
7252 spin_unlock_irqrestore(&dev->event_lock, flags);
7253
7254 intel_fb = to_intel_framebuffer(fb);
7255 obj = intel_fb->obj;
7256
79158103
CW		 7257 ret = i915_mutex_lock_interruptible(dev);
7258 if (ret)
7259 goto cleanup;
6b95a207 7260
75dfca80 7261 /* Reference the objects for the scheduled work. */
05394f39
CW		 7262 drm_gem_object_reference(&work->old_fb_obj->base);
7263 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7264
7265 crtc->fb = fb;
96b099fd 7266
e1f99ce6 7267 work->pending_flip_obj = obj;
e1f99ce6 7268
4e5359cd
SF		 7269 work->enable_stall_check = true;
7270
e1f99ce6
CW		 7271 /* Block clients from rendering to the new back buffer until
7272 * the flip occurs and the object is no longer visible.
7273 */
05394f39 7274 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7275
8c9f3aaf
JB		 7276 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7277 if (ret)
7278 goto cleanup_pending;
6b95a207 7279
7782de3b 7280 intel_disable_fbc(dev);
f047e395 7281 intel_mark_fb_busy(obj);
6b95a207
KH		 7282 mutex_unlock(&dev->struct_mutex);
7283
e5510fac
JB		 7284 trace_i915_flip_request(intel_crtc->plane, obj);
7285
6b95a207 7286 return 0;
96b099fd 7287
8c9f3aaf
JB		 7288cleanup_pending:
7289 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7290 drm_gem_object_unreference(&work->old_fb_obj->base);
7291 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7292 mutex_unlock(&dev->struct_mutex);
7293
79158103 7294cleanup:
96b099fd
CW		 7295 spin_lock_irqsave(&dev->event_lock, flags);
7296 intel_crtc->unpin_work = NULL;
7297 spin_unlock_irqrestore(&dev->event_lock, flags);
7298
7317c75e
JB		 7299 drm_vblank_put(dev, intel_crtc->pipe);
7300free_work:
96b099fd
CW		 7301 kfree(work);
7302
7303 return ret;
6b95a207
KH		 7304}
7305
f6e5b160 7306static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7307 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7308 .load_lut = intel_crtc_load_lut,
976f8a20 7309 .disable = intel_crtc_noop,
f6e5b160
CW		 7310};
7311
6ed0f796 7312bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7313{
6ed0f796
DV		 7314 struct intel_encoder *other_encoder;
7315 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7316
6ed0f796
DV		 7317 if (WARN_ON(!crtc))
7318 return false;
7319
7320 list_for_each_entry(other_encoder,
7321 &crtc->dev->mode_config.encoder_list,
7322 base.head) {
7323
7324 if (&other_encoder->new_crtc->base != crtc ||
7325 encoder == other_encoder)
7326 continue;
7327 else
7328 return true;
f47166d2
CW		 7329 }
7330
6ed0f796
DV		 7331 return false;
7332}
47f1c6c9 7333
50f56119
DV		 7334static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7335 struct drm_crtc *crtc)
7336{
7337 struct drm_device *dev;
7338 struct drm_crtc *tmp;
7339 int crtc_mask = 1;
47f1c6c9 7340
50f56119 7341 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7342
50f56119 7343 dev = crtc->dev;
47f1c6c9 7344
50f56119
DV		 7345 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7346 if (tmp == crtc)
7347 break;
7348 crtc_mask <<= 1;
7349 }
47f1c6c9 7350
50f56119
DV		 7351 if (encoder->possible_crtcs & crtc_mask)
7352 return true;
7353 return false;
47f1c6c9 7354}
79e53945 7355
9a935856
DV		 7356/**
7357 * intel_modeset_update_staged_output_state
7358 *
7359 * Updates the staged output configuration state, e.g. after we've read out the
7360 * current hw state.
7361 */
7362static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7363{
9a935856
DV		 7364 struct intel_encoder *encoder;
7365 struct intel_connector *connector;
f6e5b160 7366
9a935856
DV		 7367 list_for_each_entry(connector, &dev->mode_config.connector_list,
7368 base.head) {
7369 connector->new_encoder =
7370 to_intel_encoder(connector->base.encoder);
7371 }
f6e5b160 7372
9a935856
DV		 7373 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7374 base.head) {
7375 encoder->new_crtc =
7376 to_intel_crtc(encoder->base.crtc);
7377 }
f6e5b160
CW		 7378}
7379
9a935856
DV		 7380/**
7381 * intel_modeset_commit_output_state
7382 *
7383 * This function copies the stage display pipe configuration to the real one.
7384 */
7385static void intel_modeset_commit_output_state(struct drm_device *dev)
7386{
7387 struct intel_encoder *encoder;
7388 struct intel_connector *connector;
f6e5b160 7389
9a935856
DV		 7390 list_for_each_entry(connector, &dev->mode_config.connector_list,
7391 base.head) {
7392 connector->base.encoder = &connector->new_encoder->base;
7393 }
f6e5b160 7394
9a935856
DV		 7395 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7396 base.head) {
7397 encoder->base.crtc = &encoder->new_crtc->base;
7398 }
7399}
7400
7758a113
DV		 7401static struct drm_display_mode *
7402intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7403 struct drm_display_mode *mode)
ee7b9f93 7404{
7758a113
DV		 7405 struct drm_device *dev = crtc->dev;
7406 struct drm_display_mode *adjusted_mode;
7407 struct drm_encoder_helper_funcs *encoder_funcs;
7408 struct intel_encoder *encoder;
ee7b9f93 7409
7758a113
DV		 7410 adjusted_mode = drm_mode_duplicate(dev, mode);
7411 if (!adjusted_mode)
7412 return ERR_PTR(-ENOMEM);
7413
7414 /* Pass our mode to the connectors and the CRTC to give them a chance to
7415 * adjust it according to limitations or connector properties, and also
7416 * a chance to reject the mode entirely.
7417 */
7418 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7419 base.head) {
7420
7421 if (&encoder->new_crtc->base != crtc)
7422 continue;
7423 encoder_funcs = encoder->base.helper_private;
7424 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7425 adjusted_mode))) {
7426 DRM_DEBUG_KMS("Encoder fixup failed\n");
7427 goto fail;
7428 }
ee7b9f93
JB		 7429 }
7430
7758a113
DV		 7431 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7432 DRM_DEBUG_KMS("CRTC fixup failed\n");
7433 goto fail;
ee7b9f93 7434 }
7758a113
DV		 7435 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7436
7437 return adjusted_mode;
7438fail:
7439 drm_mode_destroy(dev, adjusted_mode);
7440 return ERR_PTR(-EINVAL);
ee7b9f93
JB		 7441}
7442
e2e1ed41
DV		 7443/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7444 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7445static void
7446intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7447 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7448{
7449 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7450 struct drm_device *dev = crtc->dev;
7451 struct intel_encoder *encoder;
7452 struct intel_connector *connector;
7453 struct drm_crtc *tmp_crtc;
79e53945 7454
e2e1ed41 7455 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7456
e2e1ed41
DV		 7457 /* Check which crtcs have changed outputs connected to them, these need
7458 * to be part of the prepare_pipes mask. We don't (yet) support global
7459 * modeset across multiple crtcs, so modeset_pipes will only have one
7460 * bit set at most. */
7461 list_for_each_entry(connector, &dev->mode_config.connector_list,
7462 base.head) {
7463 if (connector->base.encoder == &connector->new_encoder->base)
7464 continue;
79e53945 7465
e2e1ed41
DV		 7466 if (connector->base.encoder) {
7467 tmp_crtc = connector->base.encoder->crtc;
7468
7469 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7470 }
7471
7472 if (connector->new_encoder)
7473 *prepare_pipes |=
7474 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7475 }
7476
e2e1ed41
DV		 7477 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7478 base.head) {
7479 if (encoder->base.crtc == &encoder->new_crtc->base)
7480 continue;
7481
7482 if (encoder->base.crtc) {
7483 tmp_crtc = encoder->base.crtc;
7484
7485 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7486 }
7487
7488 if (encoder->new_crtc)
7489 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7490 }
7491
e2e1ed41
DV		 7492 /* Check for any pipes that will be fully disabled ... */
7493 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7494 base.head) {
7495 bool used = false;
22fd0fab 7496
e2e1ed41
DV		 7497 /* Don't try to disable disabled crtcs. */
7498 if (!intel_crtc->base.enabled)
7499 continue;
7e7d76c3 7500
e2e1ed41
DV		 7501 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7502 base.head) {
7503 if (encoder->new_crtc == intel_crtc)
7504 used = true;
7505 }
7506
7507 if (!used)
7508 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7509 }
7510
e2e1ed41
DV		 7511
7512 /* set_mode is also used to update properties on life display pipes. */
7513 intel_crtc = to_intel_crtc(crtc);
7514 if (crtc->enabled)
7515 *prepare_pipes |= 1 << intel_crtc->pipe;
7516
7517 /* We only support modeset on one single crtc, hence we need to do that
7518 * only for the passed in crtc iff we change anything else than just
7519 * disable crtcs.
7520 *
7521 * This is actually not true, to be fully compatible with the old crtc
7522 * helper we automatically disable _any_ output (i.e. doesn't need to be
7523 * connected to the crtc we're modesetting on) if it's disconnected.
7524 * Which is a rather nutty api (since changed the output configuration
7525 * without userspace's explicit request can lead to confusion), but
7526 * alas. Hence we currently need to modeset on all pipes we prepare. */
7527 if (*prepare_pipes)
7528 *modeset_pipes = *prepare_pipes;
7529
7530 /* ... and mask these out. */
7531 *modeset_pipes &= ~(*disable_pipes);
7532 *prepare_pipes &= ~(*disable_pipes);
7533}
7534
ea9d758d
DV		 7535static bool intel_crtc_in_use(struct drm_crtc *crtc)
7536{
7537 struct drm_encoder *encoder;
7538 struct drm_device *dev = crtc->dev;
7539
7540 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7541 if (encoder->crtc == crtc)
7542 return true;
7543
7544 return false;
7545}
7546
7547static void
7548intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7549{
7550 struct intel_encoder *intel_encoder;
7551 struct intel_crtc *intel_crtc;
7552 struct drm_connector *connector;
7553
7554 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7555 base.head) {
7556 if (!intel_encoder->base.crtc)
7557 continue;
7558
7559 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7560
7561 if (prepare_pipes & (1 << intel_crtc->pipe))
7562 intel_encoder->connectors_active = false;
7563 }
7564
7565 intel_modeset_commit_output_state(dev);
7566
7567 /* Update computed state. */
7568 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7569 base.head) {
7570 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7571 }
7572
7573 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7574 if (!connector->encoder || !connector->encoder->crtc)
7575 continue;
7576
7577 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7578
7579 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7580 struct drm_property *dpms_property =
7581 dev->mode_config.dpms_property;
7582
ea9d758d 7583 connector->dpms = DRM_MODE_DPMS_ON;
68d34720
DV		 7584 drm_connector_property_set_value(connector,
7585 dpms_property,
7586 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7587
7588 intel_encoder = to_intel_encoder(connector->encoder);
7589 intel_encoder->connectors_active = true;
7590 }
7591 }
7592
7593}
7594
25c5b266
DV		 7595#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7596 list_for_each_entry((intel_crtc), \
7597 &(dev)->mode_config.crtc_list, \
7598 base.head) \
7599 if (mask & (1 <<(intel_crtc)->pipe)) \
7600
b980514c 7601void
8af6cf88
DV		 7602intel_modeset_check_state(struct drm_device *dev)
7603{
7604 struct intel_crtc *crtc;
7605 struct intel_encoder *encoder;
7606 struct intel_connector *connector;
7607
7608 list_for_each_entry(connector, &dev->mode_config.connector_list,
7609 base.head) {
7610 /* This also checks the encoder/connector hw state with the
7611 * ->get_hw_state callbacks. */
7612 intel_connector_check_state(connector);
7613
7614 WARN(&connector->new_encoder->base != connector->base.encoder,
7615 "connector's staged encoder doesn't match current encoder\n");
7616 }
7617
7618 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7619 base.head) {
7620 bool enabled = false;
7621 bool active = false;
7622 enum pipe pipe, tracked_pipe;
7623
7624 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7625 encoder->base.base.id,
7626 drm_get_encoder_name(&encoder->base));
7627
7628 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7629 "encoder's stage crtc doesn't match current crtc\n");
7630 WARN(encoder->connectors_active && !encoder->base.crtc,
7631 "encoder's active_connectors set, but no crtc\n");
7632
7633 list_for_each_entry(connector, &dev->mode_config.connector_list,
7634 base.head) {
7635 if (connector->base.encoder != &encoder->base)
7636 continue;
7637 enabled = true;
7638 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7639 active = true;
7640 }
7641 WARN(!!encoder->base.crtc != enabled,
7642 "encoder's enabled state mismatch "
7643 "(expected %i, found %i)\n",
7644 !!encoder->base.crtc, enabled);
7645 WARN(active && !encoder->base.crtc,
7646 "active encoder with no crtc\n");
7647
7648 WARN(encoder->connectors_active != active,
7649 "encoder's computed active state doesn't match tracked active state "
7650 "(expected %i, found %i)\n", active, encoder->connectors_active);
7651
7652 active = encoder->get_hw_state(encoder, &pipe);
7653 WARN(active != encoder->connectors_active,
7654 "encoder's hw state doesn't match sw tracking "
7655 "(expected %i, found %i)\n",
7656 encoder->connectors_active, active);
7657
7658 if (!encoder->base.crtc)
7659 continue;
7660
7661 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7662 WARN(active && pipe != tracked_pipe,
7663 "active encoder's pipe doesn't match"
7664 "(expected %i, found %i)\n",
7665 tracked_pipe, pipe);
7666
7667 }
7668
7669 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7670 base.head) {
7671 bool enabled = false;
7672 bool active = false;
7673
7674 DRM_DEBUG_KMS("[CRTC:%d]\n",
7675 crtc->base.base.id);
7676
7677 WARN(crtc->active && !crtc->base.enabled,
7678 "active crtc, but not enabled in sw tracking\n");
7679
7680 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7681 base.head) {
7682 if (encoder->base.crtc != &crtc->base)
7683 continue;
7684 enabled = true;
7685 if (encoder->connectors_active)
7686 active = true;
7687 }
7688 WARN(active != crtc->active,
7689 "crtc's computed active state doesn't match tracked active state "
7690 "(expected %i, found %i)\n", active, crtc->active);
7691 WARN(enabled != crtc->base.enabled,
7692 "crtc's computed enabled state doesn't match tracked enabled state "
7693 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7694
7695 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7696 }
7697}
7698
a6778b3c
DV		 7699bool intel_set_mode(struct drm_crtc *crtc,
7700 struct drm_display_mode *mode,
94352cf9 7701 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7702{
7703 struct drm_device *dev = crtc->dev;
dbf2b54e 7704 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7705 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7706 struct intel_crtc *intel_crtc;
7707 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7708 bool ret = true;
7709
e2e1ed41 7710 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7711 &prepare_pipes, &disable_pipes);
7712
7713 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7714 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7715
976f8a20
DV		 7716 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7717 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7718
a6778b3c
DV		 7719 saved_hwmode = crtc->hwmode;
7720 saved_mode = crtc->mode;
a6778b3c 7721
25c5b266
DV		 7722 /* Hack: Because we don't (yet) support global modeset on multiple
7723 * crtcs, we don't keep track of the new mode for more than one crtc.
7724 * Hence simply check whether any bit is set in modeset_pipes in all the
7725 * pieces of code that are not yet converted to deal with mutliple crtcs
7726 * changing their mode at the same time. */
7727 adjusted_mode = NULL;
7728 if (modeset_pipes) {
7729 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7730 if (IS_ERR(adjusted_mode)) {
7731 return false;
7732 }
25c5b266 7733 }
a6778b3c 7734
ea9d758d
DV		 7735 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7736 if (intel_crtc->base.enabled)
7737 dev_priv->display.crtc_disable(&intel_crtc->base);
7738 }
a6778b3c 7739
6c4c86f5
DV		 7740 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7741 * to set it here already despite that we pass it down the callchain.
7742 */
7743 if (modeset_pipes)
25c5b266 7744 crtc->mode = *mode;
7758a113 7745
ea9d758d
DV		 7746 /* Only after disabling all output pipelines that will be changed can we
7747 * update the the output configuration. */
7748 intel_modeset_update_state(dev, prepare_pipes);
7749
47fab737
DV		 7750 if (dev_priv->display.modeset_global_resources)
7751 dev_priv->display.modeset_global_resources(dev);
7752
a6778b3c
DV		 7753 /* Set up the DPLL and any encoders state that needs to adjust or depend
7754 * on the DPLL.
7755 */
25c5b266
DV		 7756 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7757 ret = !intel_crtc_mode_set(&intel_crtc->base,
7758 mode, adjusted_mode,
7759 x, y, fb);
7760 if (!ret)
7761 goto done;
a6778b3c
DV		 7762 }
7763
7764 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7765 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7766 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7767
25c5b266
DV		 7768 if (modeset_pipes) {
7769 /* Store real post-adjustment hardware mode. */
7770 crtc->hwmode = *adjusted_mode;
a6778b3c 7771
25c5b266
DV		 7772 /* Calculate and store various constants which
7773 * are later needed by vblank and swap-completion
7774 * timestamping. They are derived from true hwmode.
7775 */
7776 drm_calc_timestamping_constants(crtc);
7777 }
a6778b3c
DV		 7778
7779 /* FIXME: add subpixel order */
7780done:
7781 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7782 if (!ret && crtc->enabled) {
a6778b3c
DV		 7783 crtc->hwmode = saved_hwmode;
7784 crtc->mode = saved_mode;
8af6cf88
DV		 7785 } else {
7786 intel_modeset_check_state(dev);
a6778b3c
DV		 7787 }
7788
7789 return ret;
7790}
7791
25c5b266
DV		 7792#undef for_each_intel_crtc_masked
7793
d9e55608
DV		 7794static void intel_set_config_free(struct intel_set_config *config)
7795{
7796 if (!config)
7797 return;
7798
1aa4b628
DV		 7799 kfree(config->save_connector_encoders);
7800 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7801 kfree(config);
7802}
7803
85f9eb71
DV		 7804static int intel_set_config_save_state(struct drm_device *dev,
7805 struct intel_set_config *config)
7806{
85f9eb71
DV		 7807 struct drm_encoder *encoder;
7808 struct drm_connector *connector;
7809 int count;
7810
1aa4b628
DV		 7811 config->save_encoder_crtcs =
7812 kcalloc(dev->mode_config.num_encoder,
7813 sizeof(struct drm_crtc *), GFP_KERNEL);
7814 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7815 return -ENOMEM;
7816
1aa4b628
DV		 7817 config->save_connector_encoders =
7818 kcalloc(dev->mode_config.num_connector,
7819 sizeof(struct drm_encoder *), GFP_KERNEL);
7820 if (!config->save_connector_encoders)
85f9eb71
DV		 7821 return -ENOMEM;
7822
7823 /* Copy data. Note that driver private data is not affected.
7824 * Should anything bad happen only the expected state is
7825 * restored, not the drivers personal bookkeeping.
7826 */
85f9eb71
DV		 7827 count = 0;
7828 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7829 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7830 }
7831
7832 count = 0;
7833 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7834 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7835 }
7836
7837 return 0;
7838}
7839
7840static void intel_set_config_restore_state(struct drm_device *dev,
7841 struct intel_set_config *config)
7842{
9a935856
DV		 7843 struct intel_encoder *encoder;
7844 struct intel_connector *connector;
85f9eb71
DV		 7845 int count;
7846
85f9eb71 7847 count = 0;
9a935856
DV		 7848 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7849 encoder->new_crtc =
7850 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7851 }
7852
7853 count = 0;
9a935856
DV		 7854 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7855 connector->new_encoder =
7856 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7857 }
7858}
7859
5e2b584e
DV		 7860static void
7861intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7862 struct intel_set_config *config)
7863{
7864
7865 /* We should be able to check here if the fb has the same properties
7866 * and then just flip_or_move it */
7867 if (set->crtc->fb != set->fb) {
7868 /* If we have no fb then treat it as a full mode set */
7869 if (set->crtc->fb == NULL) {
7870 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7871 config->mode_changed = true;
7872 } else if (set->fb == NULL) {
7873 config->mode_changed = true;
7874 } else if (set->fb->depth != set->crtc->fb->depth) {
7875 config->mode_changed = true;
7876 } else if (set->fb->bits_per_pixel !=
7877 set->crtc->fb->bits_per_pixel) {
7878 config->mode_changed = true;
7879 } else
7880 config->fb_changed = true;
7881 }
7882
835c5873 7883 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7884 config->fb_changed = true;
7885
7886 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7887 DRM_DEBUG_KMS("modes are different, full mode set\n");
7888 drm_mode_debug_printmodeline(&set->crtc->mode);
7889 drm_mode_debug_printmodeline(set->mode);
7890 config->mode_changed = true;
7891 }
7892}
7893
2e431051 7894static int
9a935856
DV		 7895intel_modeset_stage_output_state(struct drm_device *dev,
7896 struct drm_mode_set *set,
7897 struct intel_set_config *config)
50f56119 7898{
85f9eb71 7899 struct drm_crtc *new_crtc;
9a935856
DV		 7900 struct intel_connector *connector;
7901 struct intel_encoder *encoder;
2e431051 7902 int count, ro;
50f56119 7903
9a935856
DV		 7904 /* The upper layers ensure that we either disabl a crtc or have a list
7905 * of connectors. For paranoia, double-check this. */
7906 WARN_ON(!set->fb && (set->num_connectors != 0));
7907 WARN_ON(set->fb && (set->num_connectors == 0));
7908
50f56119 7909 count = 0;
9a935856
DV		 7910 list_for_each_entry(connector, &dev->mode_config.connector_list,
7911 base.head) {
7912 /* Otherwise traverse passed in connector list and get encoders
7913 * for them. */
50f56119 7914 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7915 if (set->connectors[ro] == &connector->base) {
7916 connector->new_encoder = connector->encoder;
50f56119
DV		 7917 break;
7918 }
7919 }
7920
9a935856
DV		 7921 /* If we disable the crtc, disable all its connectors. Also, if
7922 * the connector is on the changing crtc but not on the new
7923 * connector list, disable it. */
7924 if ((!set->fb || ro == set->num_connectors) &&
7925 connector->base.encoder &&
7926 connector->base.encoder->crtc == set->crtc) {
7927 connector->new_encoder = NULL;
7928
7929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7930 connector->base.base.id,
7931 drm_get_connector_name(&connector->base));
7932 }
7933
7934
7935 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7936 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7937 config->mode_changed = true;
50f56119 7938 }
9a935856
DV		 7939
7940 /* Disable all disconnected encoders. */
7941 if (connector->base.status == connector_status_disconnected)
7942 connector->new_encoder = NULL;
50f56119 7943 }
9a935856 7944 /* connector->new_encoder is now updated for all connectors. */
50f56119 7945
9a935856 7946 /* Update crtc of enabled connectors. */
50f56119 7947 count = 0;
9a935856
DV		 7948 list_for_each_entry(connector, &dev->mode_config.connector_list,
7949 base.head) {
7950 if (!connector->new_encoder)
50f56119
DV		 7951 continue;
7952
9a935856 7953 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7954
7955 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7956 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7957 new_crtc = set->crtc;
7958 }
7959
7960 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7961 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7962 new_crtc)) {
5e2b584e 7963 return -EINVAL;
50f56119 7964 }
9a935856
DV		 7965 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7966
7967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7968 connector->base.base.id,
7969 drm_get_connector_name(&connector->base),
7970 new_crtc->base.id);
7971 }
7972
7973 /* Check for any encoders that needs to be disabled. */
7974 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7975 base.head) {
7976 list_for_each_entry(connector,
7977 &dev->mode_config.connector_list,
7978 base.head) {
7979 if (connector->new_encoder == encoder) {
7980 WARN_ON(!connector->new_encoder->new_crtc);
7981
7982 goto next_encoder;
7983 }
7984 }
7985 encoder->new_crtc = NULL;
7986next_encoder:
7987 /* Only now check for crtc changes so we don't miss encoders
7988 * that will be disabled. */
7989 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7990 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7991 config->mode_changed = true;
50f56119
DV		 7992 }
7993 }
9a935856 7994 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7995
2e431051
DV		 7996 return 0;
7997}
7998
7999static int intel_crtc_set_config(struct drm_mode_set *set)
8000{
8001 struct drm_device *dev;
2e431051
DV		 8002 struct drm_mode_set save_set;
8003 struct intel_set_config *config;
8004 int ret;
2e431051 8005
8d3e375e
DV		 8006 BUG_ON(!set);
8007 BUG_ON(!set->crtc);
8008 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8009
8010 if (!set->mode)
8011 set->fb = NULL;
8012
431e50f7
DV		 8013 /* The fb helper likes to play gross jokes with ->mode_set_config.
8014 * Unfortunately the crtc helper doesn't do much at all for this case,
8015 * so we have to cope with this madness until the fb helper is fixed up. */
8016 if (set->fb && set->num_connectors == 0)
8017 return 0;
8018
2e431051
DV		 8019 if (set->fb) {
8020 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8021 set->crtc->base.id, set->fb->base.id,
8022 (int)set->num_connectors, set->x, set->y);
8023 } else {
8024 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8025 }
8026
8027 dev = set->crtc->dev;
8028
8029 ret = -ENOMEM;
8030 config = kzalloc(sizeof(*config), GFP_KERNEL);
8031 if (!config)
8032 goto out_config;
8033
8034 ret = intel_set_config_save_state(dev, config);
8035 if (ret)
8036 goto out_config;
8037
8038 save_set.crtc = set->crtc;
8039 save_set.mode = &set->crtc->mode;
8040 save_set.x = set->crtc->x;
8041 save_set.y = set->crtc->y;
8042 save_set.fb = set->crtc->fb;
8043
8044 /* Compute whether we need a full modeset, only an fb base update or no
8045 * change at all. In the future we might also check whether only the
8046 * mode changed, e.g. for LVDS where we only change the panel fitter in
8047 * such cases. */
8048 intel_set_config_compute_mode_changes(set, config);
8049
9a935856 8050 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8051 if (ret)
8052 goto fail;
8053
5e2b584e 8054 if (config->mode_changed) {
87f1faa6 8055 if (set->mode) {
50f56119
DV		 8056 DRM_DEBUG_KMS("attempting to set mode from"
8057 " userspace\n");
8058 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8059 }
8060
8061 if (!intel_set_mode(set->crtc, set->mode,
8062 set->x, set->y, set->fb)) {
8063 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8064 set->crtc->base.id);
8065 ret = -EINVAL;
8066 goto fail;
8067 }
5e2b584e 8068 } else if (config->fb_changed) {
4f660f49 8069 ret = intel_pipe_set_base(set->crtc,
94352cf9 8070 set->x, set->y, set->fb);
50f56119
DV		 8071 }
8072
d9e55608
DV		 8073 intel_set_config_free(config);
8074
50f56119
DV		 8075 return 0;
8076
8077fail:
85f9eb71 8078 intel_set_config_restore_state(dev, config);
50f56119
DV		 8079
8080 /* Try to restore the config */
5e2b584e 8081 if (config->mode_changed &&
a6778b3c
DV		 8082 !intel_set_mode(save_set.crtc, save_set.mode,
8083 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8084 DRM_ERROR("failed to restore config after modeset failure\n");
8085
d9e55608
DV		 8086out_config:
8087 intel_set_config_free(config);
50f56119
DV		 8088 return ret;
8089}
8090
f6e5b160 8091static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8092 .cursor_set = intel_crtc_cursor_set,
8093 .cursor_move = intel_crtc_cursor_move,
8094 .gamma_set = intel_crtc_gamma_set,
50f56119 8095 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8096 .destroy = intel_crtc_destroy,
8097 .page_flip = intel_crtc_page_flip,
8098};
8099
79f689aa
PZ		 8100static void intel_cpu_pll_init(struct drm_device *dev)
8101{
8102 if (IS_HASWELL(dev))
8103 intel_ddi_pll_init(dev);
8104}
8105
ee7b9f93
JB		 8106static void intel_pch_pll_init(struct drm_device *dev)
8107{
8108 drm_i915_private_t *dev_priv = dev->dev_private;
8109 int i;
8110
8111 if (dev_priv->num_pch_pll == 0) {
8112 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8113 return;
8114 }
8115
8116 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8117 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8118 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8119 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8120 }
8121}
8122
b358d0a6 8123static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8124{
22fd0fab 8125 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8126 struct intel_crtc *intel_crtc;
8127 int i;
8128
8129 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8130 if (intel_crtc == NULL)
8131 return;
8132
8133 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8134
8135 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8136 for (i = 0; i < 256; i++) {
8137 intel_crtc->lut_r[i] = i;
8138 intel_crtc->lut_g[i] = i;
8139 intel_crtc->lut_b[i] = i;
8140 }
8141
80824003
JB		 8142 /* Swap pipes & planes for FBC on pre-965 */
8143 intel_crtc->pipe = pipe;
8144 intel_crtc->plane = pipe;
a5c961d1 8145 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8146 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8147 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8148 intel_crtc->plane = !pipe;
80824003
JB		 8149 }
8150
22fd0fab
JB		 8151 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8152 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8153 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8154 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8155
5a354204 8156 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8157
79e53945 8158 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8159}
8160
08d7b3d1 8161int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8162 struct drm_file *file)
08d7b3d1 8163{
08d7b3d1 8164 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8165 struct drm_mode_object *drmmode_obj;
8166 struct intel_crtc *crtc;
08d7b3d1 8167
1cff8f6b
DV		 8168 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8169 return -ENODEV;
08d7b3d1 8170
c05422d5
DV		 8171 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8172 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8173
c05422d5 8174 if (!drmmode_obj) {
08d7b3d1
CW		 8175 DRM_ERROR("no such CRTC id\n");
8176 return -EINVAL;
8177 }
8178
c05422d5
DV		 8179 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8180 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8181
c05422d5 8182 return 0;
08d7b3d1
CW		 8183}
8184
66a9278e 8185static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8186{
66a9278e
DV		 8187 struct drm_device *dev = encoder->base.dev;
8188 struct intel_encoder *source_encoder;
79e53945 8189 int index_mask = 0;
79e53945
JB		 8190 int entry = 0;
8191
66a9278e
DV		 8192 list_for_each_entry(source_encoder,
8193 &dev->mode_config.encoder_list, base.head) {
8194
8195 if (encoder == source_encoder)
79e53945 8196 index_mask |= (1 << entry);
66a9278e
DV		 8197
8198 /* Intel hw has only one MUX where enocoders could be cloned. */
8199 if (encoder->cloneable && source_encoder->cloneable)
8200 index_mask |= (1 << entry);
8201
79e53945
JB		 8202 entry++;
8203 }
4ef69c7a 8204
79e53945
JB		 8205 return index_mask;
8206}
8207
4d302442
CW		 8208static bool has_edp_a(struct drm_device *dev)
8209{
8210 struct drm_i915_private *dev_priv = dev->dev_private;
8211
8212 if (!IS_MOBILE(dev))
8213 return false;
8214
8215 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8216 return false;
8217
8218 if (IS_GEN5(dev) &&
8219 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8220 return false;
8221
8222 return true;
8223}
8224
79e53945
JB		 8225static void intel_setup_outputs(struct drm_device *dev)
8226{
725e30ad 8227 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8228 struct intel_encoder *encoder;
cb0953d7 8229 bool dpd_is_edp = false;
f3cfcba6 8230 bool has_lvds;
79e53945 8231
f3cfcba6 8232 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8233 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8234 /* disable the panel fitter on everything but LVDS */
8235 I915_WRITE(PFIT_CONTROL, 0);
8236 }
79e53945 8237
bad720ff 8238 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8239 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 8240
4d302442 8241 if (has_edp_a(dev))
ab9d7c30 8242 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 8243
cb0953d7 8244 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8245 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 8246 }
8247
8248 intel_crt_init(dev);
8249
0e72a5b5
ED		 8250 if (IS_HASWELL(dev)) {
8251 int found;
8252
8253 /* Haswell uses DDI functions to detect digital outputs */
8254 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8255 /* DDI A only supports eDP */
8256 if (found)
8257 intel_ddi_init(dev, PORT_A);
8258
8259 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8260 * register */
8261 found = I915_READ(SFUSE_STRAP);
8262
8263 if (found & SFUSE_STRAP_DDIB_DETECTED)
8264 intel_ddi_init(dev, PORT_B);
8265 if (found & SFUSE_STRAP_DDIC_DETECTED)
8266 intel_ddi_init(dev, PORT_C);
8267 if (found & SFUSE_STRAP_DDID_DETECTED)
8268 intel_ddi_init(dev, PORT_D);
8269 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 8270 int found;
8271
30ad48b7 8272 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8273 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8274 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8275 if (!found)
08d644ad 8276 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8277 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8278 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8279 }
8280
8281 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8282 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8283
b708a1d5 8284 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8285 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8286
5eb08b69 8287 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8288 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8289
cb0953d7 8290 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 8291 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8292 } else if (IS_VALLEYVIEW(dev)) {
8293 int found;
8294
19c03924
GB		 8295 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8296 if (I915_READ(DP_C) & DP_DETECTED)
8297 intel_dp_init(dev, DP_C, PORT_C);
8298
4a87d65d
JB		 8299 if (I915_READ(SDVOB) & PORT_DETECTED) {
8300 /* SDVOB multiplex with HDMIB */
8301 found = intel_sdvo_init(dev, SDVOB, true);
8302 if (!found)
08d644ad 8303 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8304 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8305 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8306 }
8307
8308 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8309 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8310
103a196f 8311 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8312 bool found = false;
7d57382e 8313
725e30ad 8314 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8315 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8316 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8317 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8318 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8319 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8320 }
27185ae1 8321
b01f2c3a
JB		 8322 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8323 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8324 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8325 }
725e30ad 8326 }
13520b05
KH		 8327
8328 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8329
b01f2c3a
JB		 8330 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8331 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8332 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8333 }
27185ae1
ML		 8334
8335 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8336
b01f2c3a
JB		 8337 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8338 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8339 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8340 }
8341 if (SUPPORTS_INTEGRATED_DP(dev)) {
8342 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8343 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8344 }
725e30ad 8345 }
27185ae1 8346
b01f2c3a
JB		 8347 if (SUPPORTS_INTEGRATED_DP(dev) &&
8348 (I915_READ(DP_D) & DP_DETECTED)) {
8349 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8350 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8351 }
bad720ff 8352 } else if (IS_GEN2(dev))
79e53945
JB		 8353 intel_dvo_init(dev);
8354
103a196f 8355 if (SUPPORTS_TV(dev))
79e53945
JB		 8356 intel_tv_init(dev);
8357
4ef69c7a
CW		 8358 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8359 encoder->base.possible_crtcs = encoder->crtc_mask;
8360 encoder->base.possible_clones =
66a9278e 8361 intel_encoder_clones(encoder);
79e53945 8362 }
47356eb6 8363
40579abe 8364 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8365 ironlake_init_pch_refclk(dev);
79e53945
JB		 8366}
8367
8368static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8369{
8370 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8371
8372 drm_framebuffer_cleanup(fb);
05394f39 8373 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8374
8375 kfree(intel_fb);
8376}
8377
8378static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8379 struct drm_file *file,
79e53945
JB		 8380 unsigned int *handle)
8381{
8382 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8383 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8384
05394f39 8385 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8386}
8387
8388static const struct drm_framebuffer_funcs intel_fb_funcs = {
8389 .destroy = intel_user_framebuffer_destroy,
8390 .create_handle = intel_user_framebuffer_create_handle,
8391};
8392
38651674
DA		 8393int intel_framebuffer_init(struct drm_device *dev,
8394 struct intel_framebuffer *intel_fb,
308e5bcb 8395 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8396 struct drm_i915_gem_object *obj)
79e53945 8397{
79e53945
JB		 8398 int ret;
8399
05394f39 8400 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8401 return -EINVAL;
8402
308e5bcb 8403 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8404 return -EINVAL;
8405
5d7bd705
VS		 8406 /* FIXME <= Gen4 stride limits are bit unclear */
8407 if (mode_cmd->pitches[0] > 32768)
8408 return -EINVAL;
8409
8410 if (obj->tiling_mode != I915_TILING_NONE &&
8411 mode_cmd->pitches[0] != obj->stride)
8412 return -EINVAL;
8413
57779d06 8414 /* Reject formats not supported by any plane early. */
308e5bcb 8415 switch (mode_cmd->pixel_format) {
57779d06 8416 case DRM_FORMAT_C8:
04b3924d
VS		 8417 case DRM_FORMAT_RGB565:
8418 case DRM_FORMAT_XRGB8888:
8419 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8420 break;
8421 case DRM_FORMAT_XRGB1555:
8422 case DRM_FORMAT_ARGB1555:
8423 if (INTEL_INFO(dev)->gen > 3)
8424 return -EINVAL;
8425 break;
8426 case DRM_FORMAT_XBGR8888:
8427 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8428 case DRM_FORMAT_XRGB2101010:
8429 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8430 case DRM_FORMAT_XBGR2101010:
8431 case DRM_FORMAT_ABGR2101010:
8432 if (INTEL_INFO(dev)->gen < 4)
8433 return -EINVAL;
b5626747 8434 break;
04b3924d
VS		 8435 case DRM_FORMAT_YUYV:
8436 case DRM_FORMAT_UYVY:
8437 case DRM_FORMAT_YVYU:
8438 case DRM_FORMAT_VYUY:
57779d06
VS		 8439 if (INTEL_INFO(dev)->gen < 6)
8440 return -EINVAL;
57cd6508
CW		 8441 break;
8442 default:
57779d06 8443 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8444 return -EINVAL;
8445 }
8446
90f9a336
VS		 8447 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8448 if (mode_cmd->offsets[0] != 0)
8449 return -EINVAL;
8450
79e53945
JB		 8451 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8452 if (ret) {
8453 DRM_ERROR("framebuffer init failed %d\n", ret);
8454 return ret;
8455 }
8456
8457 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8458 intel_fb->obj = obj;
79e53945
JB		 8459 return 0;
8460}
8461
79e53945
JB		 8462static struct drm_framebuffer *
8463intel_user_framebuffer_create(struct drm_device *dev,
8464 struct drm_file *filp,
308e5bcb 8465 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8466{
05394f39 8467 struct drm_i915_gem_object *obj;
79e53945 8468
308e5bcb
JB		 8469 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8470 mode_cmd->handles[0]));
c8725226 8471 if (&obj->base == NULL)
cce13ff7 8472 return ERR_PTR(-ENOENT);
79e53945 8473
d2dff872 8474 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8475}
8476
79e53945 8477static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8478 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8479 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8480};
8481
e70236a8
JB		 8482/* Set up chip specific display functions */
8483static void intel_init_display(struct drm_device *dev)
8484{
8485 struct drm_i915_private *dev_priv = dev->dev_private;
8486
8487 /* We always want a DPMS function */
09b4ddf9
PZ		 8488 if (IS_HASWELL(dev)) {
8489 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8490 dev_priv->display.crtc_enable = haswell_crtc_enable;
8491 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8492 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8493 dev_priv->display.update_plane = ironlake_update_plane;
8494 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8495 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8496 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8497 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8498 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8499 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8500 } else {
f564048e 8501 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8502 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8503 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8504 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8505 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8506 }
e70236a8 8507
e70236a8 8508 /* Returns the core display clock speed */
25eb05fc
JB		 8509 if (IS_VALLEYVIEW(dev))
8510 dev_priv->display.get_display_clock_speed =
8511 valleyview_get_display_clock_speed;
8512 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8513 dev_priv->display.get_display_clock_speed =
8514 i945_get_display_clock_speed;
8515 else if (IS_I915G(dev))
8516 dev_priv->display.get_display_clock_speed =
8517 i915_get_display_clock_speed;
f2b115e6 8518 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8519 dev_priv->display.get_display_clock_speed =
8520 i9xx_misc_get_display_clock_speed;
8521 else if (IS_I915GM(dev))
8522 dev_priv->display.get_display_clock_speed =
8523 i915gm_get_display_clock_speed;
8524 else if (IS_I865G(dev))
8525 dev_priv->display.get_display_clock_speed =
8526 i865_get_display_clock_speed;
f0f8a9ce 8527 else if (IS_I85X(dev))
e70236a8
JB		 8528 dev_priv->display.get_display_clock_speed =
8529 i855_get_display_clock_speed;
8530 else /* 852, 830 */
8531 dev_priv->display.get_display_clock_speed =
8532 i830_get_display_clock_speed;
8533
7f8a8569 8534 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8535 if (IS_GEN5(dev)) {
674cf967 8536 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8537 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8538 } else if (IS_GEN6(dev)) {
674cf967 8539 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8540 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8541 } else if (IS_IVYBRIDGE(dev)) {
8542 /* FIXME: detect B0+ stepping and use auto training */
8543 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8544 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8545 dev_priv->display.modeset_global_resources =
8546 ivb_modeset_global_resources;
c82e4d26
ED		 8547 } else if (IS_HASWELL(dev)) {
8548 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8549 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8550 } else
8551 dev_priv->display.update_wm = NULL;
6067aaea 8552 } else if (IS_G4X(dev)) {
e0dac65e 8553 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8554 }
8c9f3aaf
JB		 8555
8556 /* Default just returns -ENODEV to indicate unsupported */
8557 dev_priv->display.queue_flip = intel_default_queue_flip;
8558
8559 switch (INTEL_INFO(dev)->gen) {
8560 case 2:
8561 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8562 break;
8563
8564 case 3:
8565 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8566 break;
8567
8568 case 4:
8569 case 5:
8570 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8571 break;
8572
8573 case 6:
8574 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8575 break;
7c9017e5
JB		 8576 case 7:
8577 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8578 break;
8c9f3aaf 8579 }
e70236a8
JB		 8580}
8581
b690e96c
JB		 8582/*
8583 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8584 * resume, or other times. This quirk makes sure that's the case for
8585 * affected systems.
8586 */
0206e353 8587static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8588{
8589 struct drm_i915_private *dev_priv = dev->dev_private;
8590
8591 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8592 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8593}
8594
435793df
KP		 8595/*
8596 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8597 */
8598static void quirk_ssc_force_disable(struct drm_device *dev)
8599{
8600 struct drm_i915_private *dev_priv = dev->dev_private;
8601 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8602 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8603}
8604
4dca20ef 8605/*
5a15ab5b
CE		 8606 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8607 * brightness value
4dca20ef
CE		 8608 */
8609static void quirk_invert_brightness(struct drm_device *dev)
8610{
8611 struct drm_i915_private *dev_priv = dev->dev_private;
8612 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8613 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8614}
8615
b690e96c
JB		 8616struct intel_quirk {
8617 int device;
8618 int subsystem_vendor;
8619 int subsystem_device;
8620 void (*hook)(struct drm_device *dev);
8621};
8622
c43b5634 8623static struct intel_quirk intel_quirks[] = {
b690e96c 8624 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8625 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8626
b690e96c
JB		 8627 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8628 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8629
b690e96c
JB		 8630 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8631 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8632
ccd0d36e 8633 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8634 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8635 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8636
8637 /* Lenovo U160 cannot use SSC on LVDS */
8638 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8639
8640 /* Sony Vaio Y cannot use SSC on LVDS */
8641 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8642
8643 /* Acer Aspire 5734Z must invert backlight brightness */
8644 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8645};
8646
8647static void intel_init_quirks(struct drm_device *dev)
8648{
8649 struct pci_dev *d = dev->pdev;
8650 int i;
8651
8652 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8653 struct intel_quirk *q = &intel_quirks[i];
8654
8655 if (d->device == q->device &&
8656 (d->subsystem_vendor == q->subsystem_vendor ||
8657 q->subsystem_vendor == PCI_ANY_ID) &&
8658 (d->subsystem_device == q->subsystem_device ||
8659 q->subsystem_device == PCI_ANY_ID))
8660 q->hook(dev);
8661 }
8662}
8663
9cce37f4
JB		 8664/* Disable the VGA plane that we never use */
8665static void i915_disable_vga(struct drm_device *dev)
8666{
8667 struct drm_i915_private *dev_priv = dev->dev_private;
8668 u8 sr1;
8669 u32 vga_reg;
8670
8671 if (HAS_PCH_SPLIT(dev))
8672 vga_reg = CPU_VGACNTRL;
8673 else
8674 vga_reg = VGACNTRL;
8675
8676 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8677 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8678 sr1 = inb(VGA_SR_DATA);
8679 outb(sr1 | 1<<5, VGA_SR_DATA);
8680 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8681 udelay(300);
8682
8683 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8684 POSTING_READ(vga_reg);
8685}
8686
f817586c
DV		 8687void intel_modeset_init_hw(struct drm_device *dev)
8688{
0232e927
ED		 8689 /* We attempt to init the necessary power wells early in the initialization
8690 * time, so the subsystems that expect power to be enabled can work.
8691 */
8692 intel_init_power_wells(dev);
8693
a8f78b58
ED		 8694 intel_prepare_ddi(dev);
8695
f817586c
DV		 8696 intel_init_clock_gating(dev);
8697
79f5b2c7 8698 mutex_lock(&dev->struct_mutex);
8090c6b9 8699 intel_enable_gt_powersave(dev);
79f5b2c7 8700 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8701}
8702
79e53945
JB		 8703void intel_modeset_init(struct drm_device *dev)
8704{
652c393a 8705 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8706 int i, ret;
79e53945
JB		 8707
8708 drm_mode_config_init(dev);
8709
8710 dev->mode_config.min_width = 0;
8711 dev->mode_config.min_height = 0;
8712
019d96cb
DA		 8713 dev->mode_config.preferred_depth = 24;
8714 dev->mode_config.prefer_shadow = 1;
8715
e6ecefaa 8716 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8717
b690e96c
JB		 8718 intel_init_quirks(dev);
8719
1fa61106
ED		 8720 intel_init_pm(dev);
8721
e70236a8
JB		 8722 intel_init_display(dev);
8723
a6c45cf0
CW		 8724 if (IS_GEN2(dev)) {
8725 dev->mode_config.max_width = 2048;
8726 dev->mode_config.max_height = 2048;
8727 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8728 dev->mode_config.max_width = 4096;
8729 dev->mode_config.max_height = 4096;
79e53945 8730 } else {
a6c45cf0
CW		 8731 dev->mode_config.max_width = 8192;
8732 dev->mode_config.max_height = 8192;
79e53945 8733 }
dd2757f8 8734 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8735
28c97730 8736 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8737 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8738
a3524f1b 8739 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8740 intel_crtc_init(dev, i);
00c2064b
JB		 8741 ret = intel_plane_init(dev, i);
8742 if (ret)
8743 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8744 }
8745
79f689aa 8746 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8747 intel_pch_pll_init(dev);
8748
9cce37f4
JB		 8749 /* Just disable it once at startup */
8750 i915_disable_vga(dev);
79e53945 8751 intel_setup_outputs(dev);
2c7111db
CW		 8752}
8753
24929352
DV		 8754static void
8755intel_connector_break_all_links(struct intel_connector *connector)
8756{
8757 connector->base.dpms = DRM_MODE_DPMS_OFF;
8758 connector->base.encoder = NULL;
8759 connector->encoder->connectors_active = false;
8760 connector->encoder->base.crtc = NULL;
8761}
8762
7fad798e
DV		 8763static void intel_enable_pipe_a(struct drm_device *dev)
8764{
8765 struct intel_connector *connector;
8766 struct drm_connector *crt = NULL;
8767 struct intel_load_detect_pipe load_detect_temp;
8768
8769 /* We can't just switch on the pipe A, we need to set things up with a
8770 * proper mode and output configuration. As a gross hack, enable pipe A
8771 * by enabling the load detect pipe once. */
8772 list_for_each_entry(connector,
8773 &dev->mode_config.connector_list,
8774 base.head) {
8775 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8776 crt = &connector->base;
8777 break;
8778 }
8779 }
8780
8781 if (!crt)
8782 return;
8783
8784 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8785 intel_release_load_detect_pipe(crt, &load_detect_temp);
8786
8787
8788}
8789
fa555837
DV		 8790static bool
8791intel_check_plane_mapping(struct intel_crtc *crtc)
8792{
8793 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8794 u32 reg, val;
8795
8796 if (dev_priv->num_pipe == 1)
8797 return true;
8798
8799 reg = DSPCNTR(!crtc->plane);
8800 val = I915_READ(reg);
8801
8802 if ((val & DISPLAY_PLANE_ENABLE) &&
8803 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8804 return false;
8805
8806 return true;
8807}
8808
24929352
DV		 8809static void intel_sanitize_crtc(struct intel_crtc *crtc)
8810{
8811 struct drm_device *dev = crtc->base.dev;
8812 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8813 u32 reg;
24929352 8814
24929352 8815 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8816 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8817 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8818
8819 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8820 * disable the crtc (and hence change the state) if it is wrong. Note
8821 * that gen4+ has a fixed plane -> pipe mapping. */
8822 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8823 struct intel_connector *connector;
8824 bool plane;
8825
24929352
DV		 8826 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8827 crtc->base.base.id);
8828
8829 /* Pipe has the wrong plane attached and the plane is active.
8830 * Temporarily change the plane mapping and disable everything
8831 * ... */
8832 plane = crtc->plane;
8833 crtc->plane = !plane;
8834 dev_priv->display.crtc_disable(&crtc->base);
8835 crtc->plane = plane;
8836
8837 /* ... and break all links. */
8838 list_for_each_entry(connector, &dev->mode_config.connector_list,
8839 base.head) {
8840 if (connector->encoder->base.crtc != &crtc->base)
8841 continue;
8842
8843 intel_connector_break_all_links(connector);
8844 }
8845
8846 WARN_ON(crtc->active);
8847 crtc->base.enabled = false;
8848 }
24929352 8849
7fad798e
DV		 8850 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8851 crtc->pipe == PIPE_A && !crtc->active) {
8852 /* BIOS forgot to enable pipe A, this mostly happens after
8853 * resume. Force-enable the pipe to fix this, the update_dpms
8854 * call below we restore the pipe to the right state, but leave
8855 * the required bits on. */
8856 intel_enable_pipe_a(dev);
8857 }
8858
24929352
DV		 8859 /* Adjust the state of the output pipe according to whether we
8860 * have active connectors/encoders. */
8861 intel_crtc_update_dpms(&crtc->base);
8862
8863 if (crtc->active != crtc->base.enabled) {
8864 struct intel_encoder *encoder;
8865
8866 /* This can happen either due to bugs in the get_hw_state
8867 * functions or because the pipe is force-enabled due to the
8868 * pipe A quirk. */
8869 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8870 crtc->base.base.id,
8871 crtc->base.enabled ? "enabled" : "disabled",
8872 crtc->active ? "enabled" : "disabled");
8873
8874 crtc->base.enabled = crtc->active;
8875
8876 /* Because we only establish the connector -> encoder ->
8877 * crtc links if something is active, this means the
8878 * crtc is now deactivated. Break the links. connector
8879 * -> encoder links are only establish when things are
8880 * actually up, hence no need to break them. */
8881 WARN_ON(crtc->active);
8882
8883 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8884 WARN_ON(encoder->connectors_active);
8885 encoder->base.crtc = NULL;
8886 }
8887 }
8888}
8889
8890static void intel_sanitize_encoder(struct intel_encoder *encoder)
8891{
8892 struct intel_connector *connector;
8893 struct drm_device *dev = encoder->base.dev;
8894
8895 /* We need to check both for a crtc link (meaning that the
8896 * encoder is active and trying to read from a pipe) and the
8897 * pipe itself being active. */
8898 bool has_active_crtc = encoder->base.crtc &&
8899 to_intel_crtc(encoder->base.crtc)->active;
8900
8901 if (encoder->connectors_active && !has_active_crtc) {
8902 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8903 encoder->base.base.id,
8904 drm_get_encoder_name(&encoder->base));
8905
8906 /* Connector is active, but has no active pipe. This is
8907 * fallout from our resume register restoring. Disable
8908 * the encoder manually again. */
8909 if (encoder->base.crtc) {
8910 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8911 encoder->base.base.id,
8912 drm_get_encoder_name(&encoder->base));
8913 encoder->disable(encoder);
8914 }
8915
8916 /* Inconsistent output/port/pipe state happens presumably due to
8917 * a bug in one of the get_hw_state functions. Or someplace else
8918 * in our code, like the register restore mess on resume. Clamp
8919 * things to off as a safer default. */
8920 list_for_each_entry(connector,
8921 &dev->mode_config.connector_list,
8922 base.head) {
8923 if (connector->encoder != encoder)
8924 continue;
8925
8926 intel_connector_break_all_links(connector);
8927 }
8928 }
8929 /* Enabled encoders without active connectors will be fixed in
8930 * the crtc fixup. */
8931}
8932
8933/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8934 * and i915 state tracking structures. */
8935void intel_modeset_setup_hw_state(struct drm_device *dev)
8936{
8937 struct drm_i915_private *dev_priv = dev->dev_private;
8938 enum pipe pipe;
8939 u32 tmp;
8940 struct intel_crtc *crtc;
8941 struct intel_encoder *encoder;
8942 struct intel_connector *connector;
8943
e28d54cb
PZ		 8944 if (IS_HASWELL(dev)) {
8945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8946
8947 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8948 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8949 case TRANS_DDI_EDP_INPUT_A_ON:
8950 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8951 pipe = PIPE_A;
8952 break;
8953 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8954 pipe = PIPE_B;
8955 break;
8956 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8957 pipe = PIPE_C;
8958 break;
8959 }
8960
8961 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8962 crtc->cpu_transcoder = TRANSCODER_EDP;
8963
8964 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8965 pipe_name(pipe));
8966 }
8967 }
8968
24929352
DV		 8969 for_each_pipe(pipe) {
8970 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8971
702e7a56 8972 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8973 if (tmp & PIPECONF_ENABLE)
8974 crtc->active = true;
8975 else
8976 crtc->active = false;
8977
8978 crtc->base.enabled = crtc->active;
8979
8980 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8981 crtc->base.base.id,
8982 crtc->active ? "enabled" : "disabled");
8983 }
8984
6441ab5f
PZ		 8985 if (IS_HASWELL(dev))
8986 intel_ddi_setup_hw_pll_state(dev);
8987
24929352
DV		 8988 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8989 base.head) {
8990 pipe = 0;
8991
8992 if (encoder->get_hw_state(encoder, &pipe)) {
8993 encoder->base.crtc =
8994 dev_priv->pipe_to_crtc_mapping[pipe];
8995 } else {
8996 encoder->base.crtc = NULL;
8997 }
8998
8999 encoder->connectors_active = false;
9000 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9001 encoder->base.base.id,
9002 drm_get_encoder_name(&encoder->base),
9003 encoder->base.crtc ? "enabled" : "disabled",
9004 pipe);
9005 }
9006
9007 list_for_each_entry(connector, &dev->mode_config.connector_list,
9008 base.head) {
9009 if (connector->get_hw_state(connector)) {
9010 connector->base.dpms = DRM_MODE_DPMS_ON;
9011 connector->encoder->connectors_active = true;
9012 connector->base.encoder = &connector->encoder->base;
9013 } else {
9014 connector->base.dpms = DRM_MODE_DPMS_OFF;
9015 connector->base.encoder = NULL;
9016 }
9017 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9018 connector->base.base.id,
9019 drm_get_connector_name(&connector->base),
9020 connector->base.encoder ? "enabled" : "disabled");
9021 }
9022
9023 /* HW state is read out, now we need to sanitize this mess. */
9024 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9025 base.head) {
9026 intel_sanitize_encoder(encoder);
9027 }
9028
9029 for_each_pipe(pipe) {
9030 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9031 intel_sanitize_crtc(crtc);
9032 }
9a935856
DV		 9033
9034 intel_modeset_update_staged_output_state(dev);
8af6cf88
DV		 9035
9036 intel_modeset_check_state(dev);
2e938892
DV		 9037
9038 drm_mode_config_reset(dev);
24929352
DV		 9039}
9040
2c7111db
CW		 9041void intel_modeset_gem_init(struct drm_device *dev)
9042{
1833b134 9043 intel_modeset_init_hw(dev);
02e792fb
DV		 9044
9045 intel_setup_overlay(dev);
24929352
DV		 9046
9047 intel_modeset_setup_hw_state(dev);
79e53945
JB		 9048}
9049
9050void intel_modeset_cleanup(struct drm_device *dev)
9051{
652c393a
JB		 9052 struct drm_i915_private *dev_priv = dev->dev_private;
9053 struct drm_crtc *crtc;
9054 struct intel_crtc *intel_crtc;
9055
f87ea761 9056 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9057 mutex_lock(&dev->struct_mutex);
9058
723bfd70
JB		 9059 intel_unregister_dsm_handler();
9060
9061
652c393a
JB		 9062 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9063 /* Skip inactive CRTCs */
9064 if (!crtc->fb)
9065 continue;
9066
9067 intel_crtc = to_intel_crtc(crtc);
3dec0095 9068 intel_increase_pllclock(crtc);
652c393a
JB		 9069 }
9070
973d04f9 9071 intel_disable_fbc(dev);
e70236a8 9072
8090c6b9 9073 intel_disable_gt_powersave(dev);
0cdab21f 9074
930ebb46
DV		 9075 ironlake_teardown_rc6(dev);
9076
57f350b6
JB		 9077 if (IS_VALLEYVIEW(dev))
9078 vlv_init_dpio(dev);
9079
69341a5e
KH		 9080 mutex_unlock(&dev->struct_mutex);
9081
6c0d9350
DV		 9082 /* Disable the irq before mode object teardown, for the irq might
9083 * enqueue unpin/hotplug work. */
9084 drm_irq_uninstall(dev);
9085 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9086 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9087
1630fe75
CW		 9088 /* flush any delayed tasks or pending work */
9089 flush_scheduled_work();
9090
79e53945
JB		 9091 drm_mode_config_cleanup(dev);
9092}
9093
f1c79df3
ZW		 9094/*
9095 * Return which encoder is currently attached for connector.
9096 */
df0e9248 9097struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9098{
df0e9248
CW		 9099 return &intel_attached_encoder(connector)->base;
9100}
f1c79df3 9101
df0e9248
CW		 9102void intel_connector_attach_encoder(struct intel_connector *connector,
9103 struct intel_encoder *encoder)
9104{
9105 connector->encoder = encoder;
9106 drm_mode_connector_attach_encoder(&connector->base,
9107 &encoder->base);
79e53945 9108}
28d52043
DA		 9109
9110/*
9111 * set vga decode state - true == enable VGA decode
9112 */
9113int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9114{
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9116 u16 gmch_ctrl;
9117
9118 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9119 if (state)
9120 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9121 else
9122 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9123 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9124 return 0;
9125}
c4a1d9e4
CW		 9126
9127#ifdef CONFIG_DEBUG_FS
9128#include <linux/seq_file.h>
9129
9130struct intel_display_error_state {
9131 struct intel_cursor_error_state {
9132 u32 control;
9133 u32 position;
9134 u32 base;
9135 u32 size;
52331309 9136 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9137
9138 struct intel_pipe_error_state {
9139 u32 conf;
9140 u32 source;
9141
9142 u32 htotal;
9143 u32 hblank;
9144 u32 hsync;
9145 u32 vtotal;
9146 u32 vblank;
9147 u32 vsync;
52331309 9148 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9149
9150 struct intel_plane_error_state {
9151 u32 control;
9152 u32 stride;
9153 u32 size;
9154 u32 pos;
9155 u32 addr;
9156 u32 surface;
9157 u32 tile_offset;
52331309 9158 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9159};
9160
9161struct intel_display_error_state *
9162intel_display_capture_error_state(struct drm_device *dev)
9163{
0206e353 9164 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9165 struct intel_display_error_state *error;
702e7a56 9166 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9167 int i;
9168
9169 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9170 if (error == NULL)
9171 return NULL;
9172
52331309 9173 for_each_pipe(i) {
702e7a56
PZ		 9174 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9175
c4a1d9e4
CW		 9176 error->cursor[i].control = I915_READ(CURCNTR(i));
9177 error->cursor[i].position = I915_READ(CURPOS(i));
9178 error->cursor[i].base = I915_READ(CURBASE(i));
9179
9180 error->plane[i].control = I915_READ(DSPCNTR(i));
9181 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9182 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9183 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9184 error->plane[i].addr = I915_READ(DSPADDR(i));
9185 if (INTEL_INFO(dev)->gen >= 4) {
9186 error->plane[i].surface = I915_READ(DSPSURF(i));
9187 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9188 }
9189
702e7a56 9190 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9191 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9192 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9193 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9194 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9195 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9196 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9197 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9198 }
9199
9200 return error;
9201}
9202
9203void
9204intel_display_print_error_state(struct seq_file *m,
9205 struct drm_device *dev,
9206 struct intel_display_error_state *error)
9207{
52331309 9208 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9209 int i;
9210
52331309
DL		 9211 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9212 for_each_pipe(i) {
c4a1d9e4
CW		 9213 seq_printf(m, "Pipe [%d]:\n", i);
9214 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9215 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9216 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9217 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9218 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9219 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9220 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9221 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9222
9223 seq_printf(m, "Plane [%d]:\n", i);
9224 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9225 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9226 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9227 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9228 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9229 if (INTEL_INFO(dev)->gen >= 4) {
9230 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9231 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9232 }
9233
9234 seq_printf(m, "Cursor [%d]:\n", i);
9235 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9236 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9237 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9238 }
9239}
9240#endif
kernel source for telekom puls (alcatel/mediatek)