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drm/i915: implement hsw_write_infoframe
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
021357ac
CW		 101static inline u32 /* units of 100MHz */
102intel_fdi_link_freq(struct drm_device *dev)
103{
8b99e68c
CW		 104 if (IS_GEN5(dev)) {
105 struct drm_i915_private *dev_priv = dev->dev_private;
106 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
107 } else
108 return 27;
021357ac
CW		 109}
110
e4b36699 111static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 112 .dot = { .min = 25000, .max = 350000 },
113 .vco = { .min = 930000, .max = 1400000 },
114 .n = { .min = 3, .max = 16 },
115 .m = { .min = 96, .max = 140 },
116 .m1 = { .min = 18, .max = 26 },
117 .m2 = { .min = 6, .max = 16 },
118 .p = { .min = 4, .max = 128 },
119 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 120 .p2 = { .dot_limit = 165000,
121 .p2_slow = 4, .p2_fast = 2 },
d4906093 122 .find_pll = intel_find_best_PLL,
e4b36699
KP		 123};
124
125static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 126 .dot = { .min = 25000, .max = 350000 },
127 .vco = { .min = 930000, .max = 1400000 },
128 .n = { .min = 3, .max = 16 },
129 .m = { .min = 96, .max = 140 },
130 .m1 = { .min = 18, .max = 26 },
131 .m2 = { .min = 6, .max = 16 },
132 .p = { .min = 4, .max = 128 },
133 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 134 .p2 = { .dot_limit = 165000,
135 .p2_slow = 14, .p2_fast = 7 },
d4906093 136 .find_pll = intel_find_best_PLL,
e4b36699 137};
273e27ca 138
e4b36699 139static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 140 .dot = { .min = 20000, .max = 400000 },
141 .vco = { .min = 1400000, .max = 2800000 },
142 .n = { .min = 1, .max = 6 },
143 .m = { .min = 70, .max = 120 },
144 .m1 = { .min = 10, .max = 22 },
145 .m2 = { .min = 5, .max = 9 },
146 .p = { .min = 5, .max = 80 },
147 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 148 .p2 = { .dot_limit = 200000,
149 .p2_slow = 10, .p2_fast = 5 },
d4906093 150 .find_pll = intel_find_best_PLL,
e4b36699
KP		 151};
152
153static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 154 .dot = { .min = 20000, .max = 400000 },
155 .vco = { .min = 1400000, .max = 2800000 },
156 .n = { .min = 1, .max = 6 },
157 .m = { .min = 70, .max = 120 },
158 .m1 = { .min = 10, .max = 22 },
159 .m2 = { .min = 5, .max = 9 },
160 .p = { .min = 7, .max = 98 },
161 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 162 .p2 = { .dot_limit = 112000,
163 .p2_slow = 14, .p2_fast = 7 },
d4906093 164 .find_pll = intel_find_best_PLL,
e4b36699
KP		 165};
166
273e27ca 167
e4b36699 168static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 169 .dot = { .min = 25000, .max = 270000 },
170 .vco = { .min = 1750000, .max = 3500000},
171 .n = { .min = 1, .max = 4 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 10, .max = 30 },
176 .p1 = { .min = 1, .max = 3},
177 .p2 = { .dot_limit = 270000,
178 .p2_slow = 10,
179 .p2_fast = 10
044c7c41 180 },
d4906093 181 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 182};
183
184static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 185 .dot = { .min = 22000, .max = 400000 },
186 .vco = { .min = 1750000, .max = 3500000},
187 .n = { .min = 1, .max = 4 },
188 .m = { .min = 104, .max = 138 },
189 .m1 = { .min = 16, .max = 23 },
190 .m2 = { .min = 5, .max = 11 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8},
193 .p2 = { .dot_limit = 165000,
194 .p2_slow = 10, .p2_fast = 5 },
d4906093 195 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 196};
197
198static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 199 .dot = { .min = 20000, .max = 115000 },
200 .vco = { .min = 1750000, .max = 3500000 },
201 .n = { .min = 1, .max = 3 },
202 .m = { .min = 104, .max = 138 },
203 .m1 = { .min = 17, .max = 23 },
204 .m2 = { .min = 5, .max = 11 },
205 .p = { .min = 28, .max = 112 },
206 .p1 = { .min = 2, .max = 8 },
207 .p2 = { .dot_limit = 0,
208 .p2_slow = 14, .p2_fast = 14
044c7c41 209 },
d4906093 210 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 211};
212
213static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 214 .dot = { .min = 80000, .max = 224000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 14, .max = 42 },
221 .p1 = { .min = 2, .max = 6 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 7, .p2_fast = 7
044c7c41 224 },
d4906093 225 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 226};
227
228static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 229 .dot = { .min = 161670, .max = 227000 },
230 .vco = { .min = 1750000, .max = 3500000},
231 .n = { .min = 1, .max = 2 },
232 .m = { .min = 97, .max = 108 },
233 .m1 = { .min = 0x10, .max = 0x12 },
234 .m2 = { .min = 0x05, .max = 0x06 },
235 .p = { .min = 10, .max = 20 },
236 .p1 = { .min = 1, .max = 2},
237 .p2 = { .dot_limit = 0,
273e27ca 238 .p2_slow = 10, .p2_fast = 10 },
0206e353 239 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 240};
241
f2b115e6 242static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 243 .dot = { .min = 20000, .max = 400000},
244 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 245 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
273e27ca 248 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 249 .m1 = { .min = 0, .max = 0 },
250 .m2 = { .min = 0, .max = 254 },
251 .p = { .min = 5, .max = 80 },
252 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 253 .p2 = { .dot_limit = 200000,
254 .p2_slow = 10, .p2_fast = 5 },
6115707b 255 .find_pll = intel_find_best_PLL,
e4b36699
KP		 256};
257
f2b115e6 258static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 259 .dot = { .min = 20000, .max = 400000 },
260 .vco = { .min = 1700000, .max = 3500000 },
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 .m1 = { .min = 0, .max = 0 },
264 .m2 = { .min = 0, .max = 254 },
265 .p = { .min = 7, .max = 112 },
266 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 267 .p2 = { .dot_limit = 112000,
268 .p2_slow = 14, .p2_fast = 14 },
6115707b 269 .find_pll = intel_find_best_PLL,
e4b36699
KP		 270};
271
273e27ca
EA		 272/* Ironlake / Sandybridge
273 *
274 * We calculate clock using (register_value + 2) for N/M1/M2, so here
275 * the range value for them is (actual_value - 2).
276 */
b91ad0ec 277static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 278 .dot = { .min = 25000, .max = 350000 },
279 .vco = { .min = 1760000, .max = 3510000 },
280 .n = { .min = 1, .max = 5 },
281 .m = { .min = 79, .max = 127 },
282 .m1 = { .min = 12, .max = 22 },
283 .m2 = { .min = 5, .max = 9 },
284 .p = { .min = 5, .max = 80 },
285 .p1 = { .min = 1, .max = 8 },
286 .p2 = { .dot_limit = 225000,
287 .p2_slow = 10, .p2_fast = 5 },
4547668a 288 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 289};
290
b91ad0ec 291static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 292 .dot = { .min = 25000, .max = 350000 },
293 .vco = { .min = 1760000, .max = 3510000 },
294 .n = { .min = 1, .max = 3 },
295 .m = { .min = 79, .max = 118 },
296 .m1 = { .min = 12, .max = 22 },
297 .m2 = { .min = 5, .max = 9 },
298 .p = { .min = 28, .max = 112 },
299 .p1 = { .min = 2, .max = 8 },
300 .p2 = { .dot_limit = 225000,
301 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 302 .find_pll = intel_g4x_find_best_PLL,
303};
304
305static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 306 .dot = { .min = 25000, .max = 350000 },
307 .vco = { .min = 1760000, .max = 3510000 },
308 .n = { .min = 1, .max = 3 },
309 .m = { .min = 79, .max = 127 },
310 .m1 = { .min = 12, .max = 22 },
311 .m2 = { .min = 5, .max = 9 },
312 .p = { .min = 14, .max = 56 },
313 .p1 = { .min = 2, .max = 8 },
314 .p2 = { .dot_limit = 225000,
315 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 316 .find_pll = intel_g4x_find_best_PLL,
317};
318
273e27ca 319/* LVDS 100mhz refclk limits. */
b91ad0ec 320static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 2 },
324 .m = { .min = 79, .max = 126 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
0206e353 328 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 331 .find_pll = intel_g4x_find_best_PLL,
332};
333
334static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 42 },
0206e353 342 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 345 .find_pll = intel_g4x_find_best_PLL,
346};
347
348static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 349 .dot = { .min = 25000, .max = 350000 },
350 .vco = { .min = 1760000, .max = 3510000},
351 .n = { .min = 1, .max = 2 },
352 .m = { .min = 81, .max = 90 },
353 .m1 = { .min = 12, .max = 22 },
354 .m2 = { .min = 5, .max = 9 },
355 .p = { .min = 10, .max = 20 },
356 .p1 = { .min = 1, .max = 2},
357 .p2 = { .dot_limit = 0,
273e27ca 358 .p2_slow = 10, .p2_fast = 10 },
0206e353 359 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 360};
361
57f350b6
JB		 362u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
363{
364 unsigned long flags;
365 u32 val = 0;
366
367 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
368 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
369 DRM_ERROR("DPIO idle wait timed out\n");
370 goto out_unlock;
371 }
372
373 I915_WRITE(DPIO_REG, reg);
374 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
375 DPIO_BYTE);
376 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
377 DRM_ERROR("DPIO read wait timed out\n");
378 goto out_unlock;
379 }
380 val = I915_READ(DPIO_DATA);
381
382out_unlock:
383 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
384 return val;
385}
386
57f350b6
JB		 387static void vlv_init_dpio(struct drm_device *dev)
388{
389 struct drm_i915_private *dev_priv = dev->dev_private;
390
391 /* Reset the DPIO config */
392 I915_WRITE(DPIO_CTL, 0);
393 POSTING_READ(DPIO_CTL);
394 I915_WRITE(DPIO_CTL, 1);
395 POSTING_READ(DPIO_CTL);
396}
397
618563e3
DV		 398static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
399{
400 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
401 return 1;
402}
403
404static const struct dmi_system_id intel_dual_link_lvds[] = {
405 {
406 .callback = intel_dual_link_lvds_callback,
407 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
408 .matches = {
409 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
410 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
411 },
412 },
413 { } /* terminating entry */
414};
415
b0354385
TI		 416static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
417 unsigned int reg)
418{
419 unsigned int val;
420
121d527a
TI		 421 /* use the module option value if specified */
422 if (i915_lvds_channel_mode > 0)
423 return i915_lvds_channel_mode == 2;
424
618563e3
DV		 425 if (dmi_check_system(intel_dual_link_lvds))
426 return true;
427
b0354385
TI		 428 if (dev_priv->lvds_val)
429 val = dev_priv->lvds_val;
430 else {
431 /* BIOS should set the proper LVDS register value at boot, but
432 * in reality, it doesn't set the value when the lid is closed;
433 * we need to check "the value to be set" in VBT when LVDS
434 * register is uninitialized.
435 */
436 val = I915_READ(reg);
437 if (!(val & ~LVDS_DETECTED))
438 val = dev_priv->bios_lvds_val;
439 dev_priv->lvds_val = val;
440 }
441 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
442}
443
1b894b59
CW		 444static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
445 int refclk)
2c07245f 446{
b91ad0ec
ZW		 447 struct drm_device *dev = crtc->dev;
448 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec
ZW		 450
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 452 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 453 /* LVDS dual channel */
1b894b59 454 if (refclk == 100000)
b91ad0ec
ZW		 455 limit = &intel_limits_ironlake_dual_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_dual_lvds;
458 } else {
1b894b59 459 if (refclk == 100000)
b91ad0ec
ZW		 460 limit = &intel_limits_ironlake_single_lvds_100m;
461 else
462 limit = &intel_limits_ironlake_single_lvds;
463 }
464 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 465 HAS_eDP)
466 limit = &intel_limits_ironlake_display_port;
2c07245f 467 else
b91ad0ec 468 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 469
470 return limit;
471}
472
044c7c41
ML		 473static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
474{
475 struct drm_device *dev = crtc->dev;
476 struct drm_i915_private *dev_priv = dev->dev_private;
477 const intel_limit_t *limit;
478
479 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 480 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 481 /* LVDS with dual channel */
e4b36699 482 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 483 else
484 /* LVDS with dual channel */
e4b36699 485 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 486 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
487 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 488 limit = &intel_limits_g4x_hdmi;
044c7c41 489 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 490 limit = &intel_limits_g4x_sdvo;
0206e353 491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 492 limit = &intel_limits_g4x_display_port;
044c7c41 493 } else /* The option is for other outputs */
e4b36699 494 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 495
496 return limit;
497}
498
1b894b59 499static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 500{
501 struct drm_device *dev = crtc->dev;
502 const intel_limit_t *limit;
503
bad720ff 504 if (HAS_PCH_SPLIT(dev))
1b894b59 505 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 506 else if (IS_G4X(dev)) {
044c7c41 507 limit = intel_g4x_limit(crtc);
f2b115e6 508 } else if (IS_PINEVIEW(dev)) {
2177832f 509 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 510 limit = &intel_limits_pineview_lvds;
2177832f 511 else
f2b115e6 512 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 513 } else if (!IS_GEN2(dev)) {
514 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i9xx_lvds;
516 else
517 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 518 } else {
519 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 520 limit = &intel_limits_i8xx_lvds;
79e53945 521 else
e4b36699 522 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 523 }
524 return limit;
525}
526
f2b115e6
AJ		 527/* m1 is reserved as 0 in Pineview, n is a ring counter */
528static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 529{
2177832f
SL		 530 clock->m = clock->m2 + 2;
531 clock->p = clock->p1 * clock->p2;
532 clock->vco = refclk * clock->m / clock->n;
533 clock->dot = clock->vco / clock->p;
534}
535
536static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
537{
f2b115e6
AJ		 538 if (IS_PINEVIEW(dev)) {
539 pineview_clock(refclk, clock);
2177832f
SL		 540 return;
541 }
79e53945
JB		 542 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
543 clock->p = clock->p1 * clock->p2;
544 clock->vco = refclk * clock->m / (clock->n + 2);
545 clock->dot = clock->vco / clock->p;
546}
547
79e53945
JB		 548/**
549 * Returns whether any output on the specified pipe is of the specified type
550 */
4ef69c7a 551bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 552{
4ef69c7a
CW		 553 struct drm_device *dev = crtc->dev;
554 struct drm_mode_config *mode_config = &dev->mode_config;
555 struct intel_encoder *encoder;
556
557 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
558 if (encoder->base.crtc == crtc && encoder->type == type)
559 return true;
560
561 return false;
79e53945
JB		 562}
563
7c04d1d9 564#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 565/**
566 * Returns whether the given set of divisors are valid for a given refclk with
567 * the given connectors.
568 */
569
1b894b59
CW		 570static bool intel_PLL_is_valid(struct drm_device *dev,
571 const intel_limit_t *limit,
572 const intel_clock_t *clock)
79e53945 573{
79e53945 574 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 575 INTELPllInvalid("p1 out of range\n");
79e53945 576 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 577 INTELPllInvalid("p out of range\n");
79e53945 578 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 579 INTELPllInvalid("m2 out of range\n");
79e53945 580 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 581 INTELPllInvalid("m1 out of range\n");
f2b115e6 582 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 583 INTELPllInvalid("m1 <= m2\n");
79e53945 584 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 585 INTELPllInvalid("m out of range\n");
79e53945 586 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 587 INTELPllInvalid("n out of range\n");
79e53945 588 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 589 INTELPllInvalid("vco out of range\n");
79e53945
JB		 590 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
591 * connector, etc., rather than just a single range.
592 */
593 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 594 INTELPllInvalid("dot out of range\n");
79e53945
JB		 595
596 return true;
597}
598
d4906093
ML		 599static bool
600intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 601 int target, int refclk, intel_clock_t *match_clock,
602 intel_clock_t *best_clock)
d4906093 603
79e53945
JB		 604{
605 struct drm_device *dev = crtc->dev;
606 struct drm_i915_private *dev_priv = dev->dev_private;
607 intel_clock_t clock;
79e53945
JB		 608 int err = target;
609
bc5e5718 610 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 611 (I915_READ(LVDS)) != 0) {
79e53945
JB		 612 /*
613 * For LVDS, if the panel is on, just rely on its current
614 * settings for dual-channel. We haven't figured out how to
615 * reliably set up different single/dual channel state, if we
616 * even can.
617 */
b0354385 618 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 619 clock.p2 = limit->p2.p2_fast;
620 else
621 clock.p2 = limit->p2.p2_slow;
622 } else {
623 if (target < limit->p2.dot_limit)
624 clock.p2 = limit->p2.p2_slow;
625 else
626 clock.p2 = limit->p2.p2_fast;
627 }
628
0206e353 629 memset(best_clock, 0, sizeof(*best_clock));
79e53945 630
42158660
ZY		 631 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
632 clock.m1++) {
633 for (clock.m2 = limit->m2.min;
634 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 635 /* m1 is always 0 in Pineview */
636 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 637 break;
638 for (clock.n = limit->n.min;
639 clock.n <= limit->n.max; clock.n++) {
640 for (clock.p1 = limit->p1.min;
641 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 642 int this_err;
643
2177832f 644 intel_clock(dev, refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
79e53945 647 continue;
cec2f356
SP		 648 if (match_clock &&
649 clock.p != match_clock->p)
650 continue;
79e53945
JB		 651
652 this_err = abs(clock.dot - target);
653 if (this_err < err) {
654 *best_clock = clock;
655 err = this_err;
656 }
657 }
658 }
659 }
660 }
661
662 return (err != target);
663}
664
d4906093
ML		 665static bool
666intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 667 int target, int refclk, intel_clock_t *match_clock,
668 intel_clock_t *best_clock)
d4906093
ML		 669{
670 struct drm_device *dev = crtc->dev;
671 struct drm_i915_private *dev_priv = dev->dev_private;
672 intel_clock_t clock;
673 int max_n;
674 bool found;
6ba770dc
AJ		 675 /* approximately equals target * 0.00585 */
676 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 677 found = false;
678
679 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 680 int lvds_reg;
681
c619eed4 682 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 683 lvds_reg = PCH_LVDS;
684 else
685 lvds_reg = LVDS;
686 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 687 LVDS_CLKB_POWER_UP)
688 clock.p2 = limit->p2.p2_fast;
689 else
690 clock.p2 = limit->p2.p2_slow;
691 } else {
692 if (target < limit->p2.dot_limit)
693 clock.p2 = limit->p2.p2_slow;
694 else
695 clock.p2 = limit->p2.p2_fast;
696 }
697
698 memset(best_clock, 0, sizeof(*best_clock));
699 max_n = limit->n.max;
f77f13e2 700 /* based on hardware requirement, prefer smaller n to precision */
d4906093 701 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 702 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 703 for (clock.m1 = limit->m1.max;
704 clock.m1 >= limit->m1.min; clock.m1--) {
705 for (clock.m2 = limit->m2.max;
706 clock.m2 >= limit->m2.min; clock.m2--) {
707 for (clock.p1 = limit->p1.max;
708 clock.p1 >= limit->p1.min; clock.p1--) {
709 int this_err;
710
2177832f 711 intel_clock(dev, refclk, &clock);
1b894b59
CW		 712 if (!intel_PLL_is_valid(dev, limit,
713 &clock))
d4906093 714 continue;
cec2f356
SP		 715 if (match_clock &&
716 clock.p != match_clock->p)
717 continue;
1b894b59
CW		 718
719 this_err = abs(clock.dot - target);
d4906093
ML		 720 if (this_err < err_most) {
721 *best_clock = clock;
722 err_most = this_err;
723 max_n = clock.n;
724 found = true;
725 }
726 }
727 }
728 }
729 }
2c07245f
ZW		 730 return found;
731}
732
5eb08b69 733static bool
f2b115e6 734intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 735 int target, int refclk, intel_clock_t *match_clock,
736 intel_clock_t *best_clock)
5eb08b69
ZW		 737{
738 struct drm_device *dev = crtc->dev;
739 intel_clock_t clock;
4547668a 740
5eb08b69
ZW		 741 if (target < 200000) {
742 clock.n = 1;
743 clock.p1 = 2;
744 clock.p2 = 10;
745 clock.m1 = 12;
746 clock.m2 = 9;
747 } else {
748 clock.n = 2;
749 clock.p1 = 1;
750 clock.p2 = 10;
751 clock.m1 = 14;
752 clock.m2 = 8;
753 }
754 intel_clock(dev, refclk, &clock);
755 memcpy(best_clock, &clock, sizeof(intel_clock_t));
756 return true;
757}
758
a4fc5ed6
KP		 759/* DisplayPort has only two frequencies, 162MHz and 270MHz */
760static bool
761intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 762 int target, int refclk, intel_clock_t *match_clock,
763 intel_clock_t *best_clock)
a4fc5ed6 764{
5eddb70b
CW		 765 intel_clock_t clock;
766 if (target < 200000) {
767 clock.p1 = 2;
768 clock.p2 = 10;
769 clock.n = 2;
770 clock.m1 = 23;
771 clock.m2 = 8;
772 } else {
773 clock.p1 = 1;
774 clock.p2 = 10;
775 clock.n = 1;
776 clock.m1 = 14;
777 clock.m2 = 2;
778 }
779 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
780 clock.p = (clock.p1 * clock.p2);
781 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
782 clock.vco = 0;
783 memcpy(best_clock, &clock, sizeof(intel_clock_t));
784 return true;
a4fc5ed6
KP		 785}
786
a928d536
PZ		 787static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
788{
789 struct drm_i915_private *dev_priv = dev->dev_private;
790 u32 frame, frame_reg = PIPEFRAME(pipe);
791
792 frame = I915_READ(frame_reg);
793
794 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
9d0498a2
JB		 798/**
799 * intel_wait_for_vblank - wait for vblank on a given pipe
800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * Wait for vblank to occur on a given pipe. Needed for various bits of
804 * mode setting code.
805 */
806void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 807{
9d0498a2 808 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 809 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 810
a928d536
PZ		 811 if (INTEL_INFO(dev)->gen >= 5) {
812 ironlake_wait_for_vblank(dev, pipe);
813 return;
814 }
815
300387c0
CW		 816 /* Clear existing vblank status. Note this will clear any other
817 * sticky status fields as well.
818 *
819 * This races with i915_driver_irq_handler() with the result
820 * that either function could miss a vblank event. Here it is not
821 * fatal, as we will either wait upon the next vblank interrupt or
822 * timeout. Generally speaking intel_wait_for_vblank() is only
823 * called during modeset at which time the GPU should be idle and
824 * should *not* be performing page flips and thus not waiting on
825 * vblanks...
826 * Currently, the result of us stealing a vblank from the irq
827 * handler is that a single frame will be skipped during swapbuffers.
828 */
829 I915_WRITE(pipestat_reg,
830 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
831
9d0498a2 832 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 833 if (wait_for(I915_READ(pipestat_reg) &
834 PIPE_VBLANK_INTERRUPT_STATUS,
835 50))
9d0498a2
JB		 836 DRM_DEBUG_KMS("vblank wait timed out\n");
837}
838
ab7ad7f6
KP		 839/*
840 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 841 * @dev: drm device
842 * @pipe: pipe to wait for
843 *
844 * After disabling a pipe, we can't wait for vblank in the usual way,
845 * spinning on the vblank interrupt status bit, since we won't actually
846 * see an interrupt when the pipe is disabled.
847 *
ab7ad7f6
KP		 848 * On Gen4 and above:
849 * wait for the pipe register state bit to turn off
850 *
851 * Otherwise:
852 * wait for the display line value to settle (it usually
853 * ends up stopping at the start of the next frame).
58e10eb9 854 *
9d0498a2 855 */
58e10eb9 856void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 857{
858 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 859
860 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 861 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 862
863 /* Wait for the Pipe State to go off */
58e10eb9
CW		 864 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
865 100))
ab7ad7f6
KP		 866 DRM_DEBUG_KMS("pipe_off wait timed out\n");
867 } else {
837ba00f 868 u32 last_line, line_mask;
58e10eb9 869 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 870 unsigned long timeout = jiffies + msecs_to_jiffies(100);
871
837ba00f
PZ		 872 if (IS_GEN2(dev))
873 line_mask = DSL_LINEMASK_GEN2;
874 else
875 line_mask = DSL_LINEMASK_GEN3;
876
ab7ad7f6
KP		 877 /* Wait for the display line to settle */
878 do {
837ba00f 879 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 880 mdelay(5);
837ba00f 881 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 882 time_after(timeout, jiffies));
883 if (time_after(jiffies, timeout))
884 DRM_DEBUG_KMS("pipe_off wait timed out\n");
885 }
79e53945
JB		 886}
887
b24e7179
JB		 888static const char *state_string(bool enabled)
889{
890 return enabled ? "on" : "off";
891}
892
893/* Only for pre-ILK configs */
894static void assert_pll(struct drm_i915_private *dev_priv,
895 enum pipe pipe, bool state)
896{
897 int reg;
898 u32 val;
899 bool cur_state;
900
901 reg = DPLL(pipe);
902 val = I915_READ(reg);
903 cur_state = !!(val & DPLL_VCO_ENABLE);
904 WARN(cur_state != state,
905 "PLL state assertion failure (expected %s, current %s)\n",
906 state_string(state), state_string(cur_state));
907}
908#define assert_pll_enabled(d, p) assert_pll(d, p, true)
909#define assert_pll_disabled(d, p) assert_pll(d, p, false)
910
040484af
JB		 911/* For ILK+ */
912static void assert_pch_pll(struct drm_i915_private *dev_priv,
ee7b9f93 913 struct intel_crtc *intel_crtc, bool state)
040484af
JB		 914{
915 int reg;
916 u32 val;
917 bool cur_state;
918
9d82aa17
ED		 919 if (HAS_PCH_LPT(dev_priv->dev)) {
920 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
921 return;
922 }
923
ee7b9f93
JB		 924 if (!intel_crtc->pch_pll) {
925 WARN(1, "asserting PCH PLL enabled with no PLL\n");
926 return;
927 }
928
d3ccbe86
JB		 929 if (HAS_PCH_CPT(dev_priv->dev)) {
930 u32 pch_dpll;
931
932 pch_dpll = I915_READ(PCH_DPLL_SEL);
933
934 /* Make sure the selected PLL is enabled to the transcoder */
ee7b9f93
JB		 935 WARN(!((pch_dpll >> (4 * intel_crtc->pipe)) & 8),
936 "transcoder %d PLL not enabled\n", intel_crtc->pipe);
d3ccbe86
JB		 937 }
938
ee7b9f93 939 reg = intel_crtc->pch_pll->pll_reg;
040484af
JB		 940 val = I915_READ(reg);
941 cur_state = !!(val & DPLL_VCO_ENABLE);
942 WARN(cur_state != state,
943 "PCH PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
947#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
955
bf507ef7
ED		 956 if (IS_HASWELL(dev_priv->dev)) {
957 /* On Haswell, DDI is used instead of FDI_TX_CTL */
958 reg = DDI_FUNC_CTL(pipe);
959 val = I915_READ(reg);
960 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
961 } else {
962 reg = FDI_TX_CTL(pipe);
963 val = I915_READ(reg);
964 cur_state = !!(val & FDI_TX_ENABLE);
965 }
040484af
JB		 966 WARN(cur_state != state,
967 "FDI TX state assertion failure (expected %s, current %s)\n",
968 state_string(state), state_string(cur_state));
969}
970#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
971#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
972
973static void assert_fdi_rx(struct drm_i915_private *dev_priv,
974 enum pipe pipe, bool state)
975{
976 int reg;
977 u32 val;
978 bool cur_state;
979
59c859d6
ED		 980 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
981 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
982 return;
983 } else {
984 reg = FDI_RX_CTL(pipe);
985 val = I915_READ(reg);
986 cur_state = !!(val & FDI_RX_ENABLE);
987 }
040484af
JB		 988 WARN(cur_state != state,
989 "FDI RX state assertion failure (expected %s, current %s)\n",
990 state_string(state), state_string(cur_state));
991}
992#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
993#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
994
995static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
996 enum pipe pipe)
997{
998 int reg;
999 u32 val;
1000
1001 /* ILK FDI PLL is always enabled */
1002 if (dev_priv->info->gen == 5)
1003 return;
1004
bf507ef7
ED		 1005 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1006 if (IS_HASWELL(dev_priv->dev))
1007 return;
1008
040484af
JB		 1009 reg = FDI_TX_CTL(pipe);
1010 val = I915_READ(reg);
1011 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1012}
1013
1014static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1015 enum pipe pipe)
1016{
1017 int reg;
1018 u32 val;
1019
59c859d6
ED		 1020 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1021 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1022 return;
1023 }
040484af
JB		 1024 reg = FDI_RX_CTL(pipe);
1025 val = I915_READ(reg);
1026 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1027}
1028
ea0760cf
JB		 1029static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1030 enum pipe pipe)
1031{
1032 int pp_reg, lvds_reg;
1033 u32 val;
1034 enum pipe panel_pipe = PIPE_A;
0de3b485 1035 bool locked = true;
ea0760cf
JB		 1036
1037 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1038 pp_reg = PCH_PP_CONTROL;
1039 lvds_reg = PCH_LVDS;
1040 } else {
1041 pp_reg = PP_CONTROL;
1042 lvds_reg = LVDS;
1043 }
1044
1045 val = I915_READ(pp_reg);
1046 if (!(val & PANEL_POWER_ON) ||
1047 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1048 locked = false;
1049
1050 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1051 panel_pipe = PIPE_B;
1052
1053 WARN(panel_pipe == pipe && locked,
1054 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1055 pipe_name(pipe));
ea0760cf
JB		 1056}
1057
b840d907
JB		 1058void assert_pipe(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
b24e7179
JB		 1060{
1061 int reg;
1062 u32 val;
63d7bbe9 1063 bool cur_state;
b24e7179 1064
8e636784
DV		 1065 /* if we need the pipe A quirk it must be always on */
1066 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1067 state = true;
1068
b24e7179
JB		 1069 reg = PIPECONF(pipe);
1070 val = I915_READ(reg);
63d7bbe9
JB		 1071 cur_state = !!(val & PIPECONF_ENABLE);
1072 WARN(cur_state != state,
1073 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1074 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1075}
1076
931872fc
CW		 1077static void assert_plane(struct drm_i915_private *dev_priv,
1078 enum plane plane, bool state)
b24e7179
JB		 1079{
1080 int reg;
1081 u32 val;
931872fc 1082 bool cur_state;
b24e7179
JB		 1083
1084 reg = DSPCNTR(plane);
1085 val = I915_READ(reg);
931872fc
CW		 1086 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1087 WARN(cur_state != state,
1088 "plane %c assertion failure (expected %s, current %s)\n",
1089 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1090}
1091
931872fc
CW		 1092#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1093#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1094
b24e7179
JB		 1095static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1096 enum pipe pipe)
1097{
1098 int reg, i;
1099 u32 val;
1100 int cur_pipe;
1101
19ec1358 1102 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1103 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1104 reg = DSPCNTR(pipe);
1105 val = I915_READ(reg);
1106 WARN((val & DISPLAY_PLANE_ENABLE),
1107 "plane %c assertion failure, should be disabled but not\n",
1108 plane_name(pipe));
19ec1358 1109 return;
28c05794 1110 }
19ec1358 1111
b24e7179
JB		 1112 /* Need to check both planes against the pipe */
1113 for (i = 0; i < 2; i++) {
1114 reg = DSPCNTR(i);
1115 val = I915_READ(reg);
1116 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1117 DISPPLANE_SEL_PIPE_SHIFT;
1118 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1119 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1120 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1121 }
1122}
1123
92f2584a
JB		 1124static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1125{
1126 u32 val;
1127 bool enabled;
1128
9d82aa17
ED		 1129 if (HAS_PCH_LPT(dev_priv->dev)) {
1130 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1131 return;
1132 }
1133
92f2584a
JB		 1134 val = I915_READ(PCH_DREF_CONTROL);
1135 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1136 DREF_SUPERSPREAD_SOURCE_MASK));
1137 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1138}
1139
1140static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1141 enum pipe pipe)
1142{
1143 int reg;
1144 u32 val;
1145 bool enabled;
1146
1147 reg = TRANSCONF(pipe);
1148 val = I915_READ(reg);
1149 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1150 WARN(enabled,
1151 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1152 pipe_name(pipe));
92f2584a
JB		 1153}
1154
4e634389
KP		 1155static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1157{
1158 if ((val & DP_PORT_EN) == 0)
1159 return false;
1160
1161 if (HAS_PCH_CPT(dev_priv->dev)) {
1162 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1163 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1164 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1165 return false;
1166 } else {
1167 if ((val & DP_PIPE_MASK) != (pipe << 30))
1168 return false;
1169 }
1170 return true;
1171}
1172
1519b995
KP		 1173static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1174 enum pipe pipe, u32 val)
1175{
1176 if ((val & PORT_ENABLE) == 0)
1177 return false;
1178
1179 if (HAS_PCH_CPT(dev_priv->dev)) {
1180 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1181 return false;
1182 } else {
1183 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1184 return false;
1185 }
1186 return true;
1187}
1188
1189static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1190 enum pipe pipe, u32 val)
1191{
1192 if ((val & LVDS_PORT_EN) == 0)
1193 return false;
1194
1195 if (HAS_PCH_CPT(dev_priv->dev)) {
1196 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1197 return false;
1198 } else {
1199 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1200 return false;
1201 }
1202 return true;
1203}
1204
1205static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, u32 val)
1207{
1208 if ((val & ADPA_DAC_ENABLE) == 0)
1209 return false;
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
1211 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1212 return false;
1213 } else {
1214 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1215 return false;
1216 }
1217 return true;
1218}
1219
291906f1 1220static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1221 enum pipe pipe, int reg, u32 port_sel)
291906f1 1222{
47a05eca 1223 u32 val = I915_READ(reg);
4e634389 1224 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1225 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1226 reg, pipe_name(pipe));
291906f1
JB		 1227}
1228
1229static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1230 enum pipe pipe, int reg)
1231{
47a05eca 1232 u32 val = I915_READ(reg);
1519b995 1233 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1234 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1235 reg, pipe_name(pipe));
291906f1
JB		 1236}
1237
1238static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1239 enum pipe pipe)
1240{
1241 int reg;
1242 u32 val;
291906f1 1243
f0575e92
KP		 1244 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1245 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1246 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1247
1248 reg = PCH_ADPA;
1249 val = I915_READ(reg);
1519b995 1250 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1251 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1252 pipe_name(pipe));
291906f1
JB		 1253
1254 reg = PCH_LVDS;
1255 val = I915_READ(reg);
1519b995 1256 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1257 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1258 pipe_name(pipe));
291906f1
JB		 1259
1260 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1261 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1262 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1263}
1264
63d7bbe9
JB		 1265/**
1266 * intel_enable_pll - enable a PLL
1267 * @dev_priv: i915 private structure
1268 * @pipe: pipe PLL to enable
1269 *
1270 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1271 * make sure the PLL reg is writable first though, since the panel write
1272 * protect mechanism may be enabled.
1273 *
1274 * Note! This is for pre-ILK only.
1275 */
1276static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1277{
1278 int reg;
1279 u32 val;
1280
1281 /* No really, not for ILK+ */
1282 BUG_ON(dev_priv->info->gen >= 5);
1283
1284 /* PLL is protected by panel, make sure we can write it */
1285 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1286 assert_panel_unlocked(dev_priv, pipe);
1287
1288 reg = DPLL(pipe);
1289 val = I915_READ(reg);
1290 val |= DPLL_VCO_ENABLE;
1291
1292 /* We do this three times for luck */
1293 I915_WRITE(reg, val);
1294 POSTING_READ(reg);
1295 udelay(150); /* wait for warmup */
1296 I915_WRITE(reg, val);
1297 POSTING_READ(reg);
1298 udelay(150); /* wait for warmup */
1299 I915_WRITE(reg, val);
1300 POSTING_READ(reg);
1301 udelay(150); /* wait for warmup */
1302}
1303
1304/**
1305 * intel_disable_pll - disable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to disable
1308 *
1309 * Disable the PLL for @pipe, making sure the pipe is off first.
1310 *
1311 * Note! This is for pre-ILK only.
1312 */
1313static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1314{
1315 int reg;
1316 u32 val;
1317
1318 /* Don't disable pipe A or pipe A PLLs if needed */
1319 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1320 return;
1321
1322 /* Make sure the pipe isn't still relying on us */
1323 assert_pipe_disabled(dev_priv, pipe);
1324
1325 reg = DPLL(pipe);
1326 val = I915_READ(reg);
1327 val &= ~DPLL_VCO_ENABLE;
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330}
1331
a416edef
ED		 1332/* SBI access */
1333static void
1334intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1335{
1336 unsigned long flags;
1337
1338 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1339 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1340 100)) {
1341 DRM_ERROR("timeout waiting for SBI to become ready\n");
1342 goto out_unlock;
1343 }
1344
1345 I915_WRITE(SBI_ADDR,
1346 (reg << 16));
1347 I915_WRITE(SBI_DATA,
1348 value);
1349 I915_WRITE(SBI_CTL_STAT,
1350 SBI_BUSY |
1351 SBI_CTL_OP_CRWR);
1352
1353 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1354 100)) {
1355 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1356 goto out_unlock;
1357 }
1358
1359out_unlock:
1360 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1361}
1362
1363static u32
1364intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1365{
1366 unsigned long flags;
1367 u32 value;
1368
1369 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1370 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_READY) == 0,
1371 100)) {
1372 DRM_ERROR("timeout waiting for SBI to become ready\n");
1373 goto out_unlock;
1374 }
1375
1376 I915_WRITE(SBI_ADDR,
1377 (reg << 16));
1378 I915_WRITE(SBI_CTL_STAT,
1379 SBI_BUSY |
1380 SBI_CTL_OP_CRRD);
1381
1382 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_READY | SBI_RESPONSE_SUCCESS)) == 0,
1383 100)) {
1384 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1385 goto out_unlock;
1386 }
1387
1388 value = I915_READ(SBI_DATA);
1389
1390out_unlock:
1391 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1392 return value;
1393}
1394
92f2584a
JB		 1395/**
1396 * intel_enable_pch_pll - enable PCH PLL
1397 * @dev_priv: i915 private structure
1398 * @pipe: pipe PLL to enable
1399 *
1400 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1401 * drives the transcoder clock.
1402 */
ee7b9f93 1403static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1404{
ee7b9f93 1405 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1406 struct intel_pch_pll *pll;
92f2584a
JB		 1407 int reg;
1408 u32 val;
1409
48da64a8 1410 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1411 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1412 pll = intel_crtc->pch_pll;
1413 if (pll == NULL)
1414 return;
1415
1416 if (WARN_ON(pll->refcount == 0))
1417 return;
ee7b9f93
JB		 1418
1419 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1420 pll->pll_reg, pll->active, pll->on,
1421 intel_crtc->base.base.id);
92f2584a
JB		 1422
1423 /* PCH refclock must be enabled first */
1424 assert_pch_refclk_enabled(dev_priv);
1425
ee7b9f93
JB		 1426 if (pll->active++ && pll->on) {
1427 assert_pch_pll_enabled(dev_priv, intel_crtc);
1428 return;
1429 }
1430
1431 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1432
1433 reg = pll->pll_reg;
92f2584a
JB		 1434 val = I915_READ(reg);
1435 val |= DPLL_VCO_ENABLE;
1436 I915_WRITE(reg, val);
1437 POSTING_READ(reg);
1438 udelay(200);
ee7b9f93
JB		 1439
1440 pll->on = true;
92f2584a
JB		 1441}
1442
ee7b9f93 1443static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1444{
ee7b9f93
JB		 1445 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1446 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1447 int reg;
ee7b9f93 1448 u32 val;
4c609cb8 1449
92f2584a
JB		 1450 /* PCH only available on ILK+ */
1451 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1452 if (pll == NULL)
1453 return;
92f2584a 1454
48da64a8
CW		 1455 if (WARN_ON(pll->refcount == 0))
1456 return;
7a419866 1457
ee7b9f93
JB		 1458 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1459 pll->pll_reg, pll->active, pll->on,
1460 intel_crtc->base.base.id);
7a419866 1461
48da64a8
CW		 1462 if (WARN_ON(pll->active == 0)) {
1463 assert_pch_pll_disabled(dev_priv, intel_crtc);
1464 return;
1465 }
1466
ee7b9f93
JB		 1467 if (--pll->active) {
1468 assert_pch_pll_enabled(dev_priv, intel_crtc);
7a419866 1469 return;
ee7b9f93
JB		 1470 }
1471
1472 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1473
1474 /* Make sure transcoder isn't still depending on us */
1475 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1476
ee7b9f93 1477 reg = pll->pll_reg;
92f2584a
JB		 1478 val = I915_READ(reg);
1479 val &= ~DPLL_VCO_ENABLE;
1480 I915_WRITE(reg, val);
1481 POSTING_READ(reg);
1482 udelay(200);
ee7b9f93
JB		 1483
1484 pll->on = false;
92f2584a
JB		 1485}
1486
040484af
JB		 1487static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1488 enum pipe pipe)
1489{
1490 int reg;
5f7f726d 1491 u32 val, pipeconf_val;
7c26e5c6 1492 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1493
1494 /* PCH only available on ILK+ */
1495 BUG_ON(dev_priv->info->gen < 5);
1496
1497 /* Make sure PCH DPLL is enabled */
ee7b9f93 1498 assert_pch_pll_enabled(dev_priv, to_intel_crtc(crtc));
040484af
JB		 1499
1500 /* FDI must be feeding us bits for PCH ports */
1501 assert_fdi_tx_enabled(dev_priv, pipe);
1502 assert_fdi_rx_enabled(dev_priv, pipe);
1503
59c859d6
ED		 1504 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1505 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1506 return;
1507 }
040484af
JB		 1508 reg = TRANSCONF(pipe);
1509 val = I915_READ(reg);
5f7f726d 1510 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1511
1512 if (HAS_PCH_IBX(dev_priv->dev)) {
1513 /*
1514 * make the BPC in transcoder be consistent with
1515 * that in pipeconf reg.
1516 */
1517 val &= ~PIPE_BPC_MASK;
5f7f726d 1518 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1519 }
5f7f726d
PZ		 1520
1521 val &= ~TRANS_INTERLACE_MASK;
1522 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1523 if (HAS_PCH_IBX(dev_priv->dev) &&
1524 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1525 val |= TRANS_LEGACY_INTERLACED_ILK;
1526 else
1527 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1528 else
1529 val |= TRANS_PROGRESSIVE;
1530
040484af
JB		 1531 I915_WRITE(reg, val | TRANS_ENABLE);
1532 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1533 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1534}
1535
1536static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1537 enum pipe pipe)
1538{
1539 int reg;
1540 u32 val;
1541
1542 /* FDI relies on the transcoder */
1543 assert_fdi_tx_disabled(dev_priv, pipe);
1544 assert_fdi_rx_disabled(dev_priv, pipe);
1545
291906f1
JB		 1546 /* Ports must be off as well */
1547 assert_pch_ports_disabled(dev_priv, pipe);
1548
040484af
JB		 1549 reg = TRANSCONF(pipe);
1550 val = I915_READ(reg);
1551 val &= ~TRANS_ENABLE;
1552 I915_WRITE(reg, val);
1553 /* wait for PCH transcoder off, transcoder state */
1554 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1555 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1556}
1557
b24e7179 1558/**
309cfea8 1559 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1560 * @dev_priv: i915 private structure
1561 * @pipe: pipe to enable
040484af 1562 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1563 *
1564 * Enable @pipe, making sure that various hardware specific requirements
1565 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1566 *
1567 * @pipe should be %PIPE_A or %PIPE_B.
1568 *
1569 * Will wait until the pipe is actually running (i.e. first vblank) before
1570 * returning.
1571 */
040484af
JB		 1572static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1573 bool pch_port)
b24e7179
JB		 1574{
1575 int reg;
1576 u32 val;
1577
1578 /*
1579 * A pipe without a PLL won't actually be able to drive bits from
1580 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1581 * need the check.
1582 */
1583 if (!HAS_PCH_SPLIT(dev_priv->dev))
1584 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1585 else {
1586 if (pch_port) {
1587 /* if driving the PCH, we need FDI enabled */
1588 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1589 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1590 }
1591 /* FIXME: assert CPU port conditions for SNB+ */
1592 }
b24e7179
JB		 1593
1594 reg = PIPECONF(pipe);
1595 val = I915_READ(reg);
00d70b15
CW		 1596 if (val & PIPECONF_ENABLE)
1597 return;
1598
1599 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1600 intel_wait_for_vblank(dev_priv->dev, pipe);
1601}
1602
1603/**
309cfea8 1604 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1605 * @dev_priv: i915 private structure
1606 * @pipe: pipe to disable
1607 *
1608 * Disable @pipe, making sure that various hardware specific requirements
1609 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1610 *
1611 * @pipe should be %PIPE_A or %PIPE_B.
1612 *
1613 * Will wait until the pipe has shut down before returning.
1614 */
1615static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1616 enum pipe pipe)
1617{
1618 int reg;
1619 u32 val;
1620
1621 /*
1622 * Make sure planes won't keep trying to pump pixels to us,
1623 * or we might hang the display.
1624 */
1625 assert_planes_disabled(dev_priv, pipe);
1626
1627 /* Don't disable pipe A or pipe A PLLs if needed */
1628 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1629 return;
1630
1631 reg = PIPECONF(pipe);
1632 val = I915_READ(reg);
00d70b15
CW		 1633 if ((val & PIPECONF_ENABLE) == 0)
1634 return;
1635
1636 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1637 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1638}
1639
d74362c9
KP		 1640/*
1641 * Plane regs are double buffered, going from enabled->disabled needs a
1642 * trigger in order to latch. The display address reg provides this.
1643 */
6f1d69b0 1644void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1645 enum plane plane)
1646{
1647 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1648 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1649}
1650
b24e7179
JB		 1651/**
1652 * intel_enable_plane - enable a display plane on a given pipe
1653 * @dev_priv: i915 private structure
1654 * @plane: plane to enable
1655 * @pipe: pipe being fed
1656 *
1657 * Enable @plane on @pipe, making sure that @pipe is running first.
1658 */
1659static void intel_enable_plane(struct drm_i915_private *dev_priv,
1660 enum plane plane, enum pipe pipe)
1661{
1662 int reg;
1663 u32 val;
1664
1665 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1666 assert_pipe_enabled(dev_priv, pipe);
1667
1668 reg = DSPCNTR(plane);
1669 val = I915_READ(reg);
00d70b15
CW		 1670 if (val & DISPLAY_PLANE_ENABLE)
1671 return;
1672
1673 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1674 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1675 intel_wait_for_vblank(dev_priv->dev, pipe);
1676}
1677
b24e7179
JB		 1678/**
1679 * intel_disable_plane - disable a display plane
1680 * @dev_priv: i915 private structure
1681 * @plane: plane to disable
1682 * @pipe: pipe consuming the data
1683 *
1684 * Disable @plane; should be an independent operation.
1685 */
1686static void intel_disable_plane(struct drm_i915_private *dev_priv,
1687 enum plane plane, enum pipe pipe)
1688{
1689 int reg;
1690 u32 val;
1691
1692 reg = DSPCNTR(plane);
1693 val = I915_READ(reg);
00d70b15
CW		 1694 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1695 return;
1696
1697 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1698 intel_flush_display_plane(dev_priv, plane);
1699 intel_wait_for_vblank(dev_priv->dev, pipe);
1700}
1701
47a05eca 1702static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1703 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1704{
1705 u32 val = I915_READ(reg);
4e634389 1706 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1707 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1708 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1709 }
47a05eca
JB		 1710}
1711
1712static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1713 enum pipe pipe, int reg)
1714{
1715 u32 val = I915_READ(reg);
1519b995 1716 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1717 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1718 reg, pipe);
47a05eca 1719 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1720 }
47a05eca
JB		 1721}
1722
1723/* Disable any ports connected to this transcoder */
1724static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1725 enum pipe pipe)
1726{
1727 u32 reg, val;
1728
1729 val = I915_READ(PCH_PP_CONTROL);
1730 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1731
f0575e92
KP		 1732 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1733 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1734 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1735
1736 reg = PCH_ADPA;
1737 val = I915_READ(reg);
1519b995 1738 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1739 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1740
1741 reg = PCH_LVDS;
1742 val = I915_READ(reg);
1519b995
KP		 1743 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1744 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1745 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1746 POSTING_READ(reg);
1747 udelay(100);
1748 }
1749
1750 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1751 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1752 disable_pch_hdmi(dev_priv, pipe, HDMID);
1753}
1754
127bd2ac 1755int
48b956c5 1756intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1757 struct drm_i915_gem_object *obj,
919926ae 1758 struct intel_ring_buffer *pipelined)
6b95a207 1759{
ce453d81 1760 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1761 u32 alignment;
1762 int ret;
1763
05394f39 1764 switch (obj->tiling_mode) {
6b95a207 1765 case I915_TILING_NONE:
534843da
CW		 1766 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1767 alignment = 128 * 1024;
a6c45cf0 1768 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1769 alignment = 4 * 1024;
1770 else
1771 alignment = 64 * 1024;
6b95a207
KH		 1772 break;
1773 case I915_TILING_X:
1774 /* pin() will align the object as required by fence */
1775 alignment = 0;
1776 break;
1777 case I915_TILING_Y:
1778 /* FIXME: Is this true? */
1779 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1780 return -EINVAL;
1781 default:
1782 BUG();
1783 }
1784
ce453d81 1785 dev_priv->mm.interruptible = false;
2da3b9b9 1786 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1787 if (ret)
ce453d81 1788 goto err_interruptible;
6b95a207
KH		 1789
1790 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1791 * fence, whereas 965+ only requires a fence if using
1792 * framebuffer compression. For simplicity, we always install
1793 * a fence as the cost is not that onerous.
1794 */
06d98131 1795 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1796 if (ret)
1797 goto err_unpin;
1690e1eb 1798
9a5a53b3 1799 i915_gem_object_pin_fence(obj);
6b95a207 1800
ce453d81 1801 dev_priv->mm.interruptible = true;
6b95a207 1802 return 0;
48b956c5
CW		 1803
1804err_unpin:
1805 i915_gem_object_unpin(obj);
ce453d81
CW		 1806err_interruptible:
1807 dev_priv->mm.interruptible = true;
48b956c5 1808 return ret;
6b95a207
KH		 1809}
1810
1690e1eb
CW		 1811void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1812{
1813 i915_gem_object_unpin_fence(obj);
1814 i915_gem_object_unpin(obj);
1815}
1816
17638cd6
JB		 1817static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1818 int x, int y)
81255565
JB		 1819{
1820 struct drm_device *dev = crtc->dev;
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1823 struct intel_framebuffer *intel_fb;
05394f39 1824 struct drm_i915_gem_object *obj;
81255565
JB		 1825 int plane = intel_crtc->plane;
1826 unsigned long Start, Offset;
81255565 1827 u32 dspcntr;
5eddb70b 1828 u32 reg;
81255565
JB		 1829
1830 switch (plane) {
1831 case 0:
1832 case 1:
1833 break;
1834 default:
1835 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1836 return -EINVAL;
1837 }
1838
1839 intel_fb = to_intel_framebuffer(fb);
1840 obj = intel_fb->obj;
81255565 1841
5eddb70b
CW		 1842 reg = DSPCNTR(plane);
1843 dspcntr = I915_READ(reg);
81255565
JB		 1844 /* Mask out pixel format bits in case we change it */
1845 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1846 switch (fb->bits_per_pixel) {
1847 case 8:
1848 dspcntr |= DISPPLANE_8BPP;
1849 break;
1850 case 16:
1851 if (fb->depth == 15)
1852 dspcntr |= DISPPLANE_15_16BPP;
1853 else
1854 dspcntr |= DISPPLANE_16BPP;
1855 break;
1856 case 24:
1857 case 32:
1858 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1859 break;
1860 default:
17638cd6 1861 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 1862 return -EINVAL;
1863 }
a6c45cf0 1864 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1865 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1866 dspcntr |= DISPPLANE_TILED;
1867 else
1868 dspcntr &= ~DISPPLANE_TILED;
1869 }
1870
5eddb70b 1871 I915_WRITE(reg, dspcntr);
81255565 1872
05394f39 1873 Start = obj->gtt_offset;
01f2c773 1874 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1875
4e6cfefc 1876 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1877 Start, Offset, x, y, fb->pitches[0]);
1878 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1879 if (INTEL_INFO(dev)->gen >= 4) {
446f2545 1880 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
5eddb70b
CW		 1881 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1882 I915_WRITE(DSPADDR(plane), Offset);
1883 } else
1884 I915_WRITE(DSPADDR(plane), Start + Offset);
1885 POSTING_READ(reg);
81255565 1886
17638cd6
JB		 1887 return 0;
1888}
1889
1890static int ironlake_update_plane(struct drm_crtc *crtc,
1891 struct drm_framebuffer *fb, int x, int y)
1892{
1893 struct drm_device *dev = crtc->dev;
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1896 struct intel_framebuffer *intel_fb;
1897 struct drm_i915_gem_object *obj;
1898 int plane = intel_crtc->plane;
1899 unsigned long Start, Offset;
1900 u32 dspcntr;
1901 u32 reg;
1902
1903 switch (plane) {
1904 case 0:
1905 case 1:
27f8227b 1906 case 2:
17638cd6
JB		 1907 break;
1908 default:
1909 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1910 return -EINVAL;
1911 }
1912
1913 intel_fb = to_intel_framebuffer(fb);
1914 obj = intel_fb->obj;
1915
1916 reg = DSPCNTR(plane);
1917 dspcntr = I915_READ(reg);
1918 /* Mask out pixel format bits in case we change it */
1919 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1920 switch (fb->bits_per_pixel) {
1921 case 8:
1922 dspcntr |= DISPPLANE_8BPP;
1923 break;
1924 case 16:
1925 if (fb->depth != 16)
1926 return -EINVAL;
1927
1928 dspcntr |= DISPPLANE_16BPP;
1929 break;
1930 case 24:
1931 case 32:
1932 if (fb->depth == 24)
1933 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1934 else if (fb->depth == 30)
1935 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1936 else
1937 return -EINVAL;
1938 break;
1939 default:
1940 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
1941 return -EINVAL;
1942 }
1943
1944 if (obj->tiling_mode != I915_TILING_NONE)
1945 dspcntr |= DISPPLANE_TILED;
1946 else
1947 dspcntr &= ~DISPPLANE_TILED;
1948
1949 /* must disable */
1950 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1951
1952 I915_WRITE(reg, dspcntr);
1953
1954 Start = obj->gtt_offset;
01f2c773 1955 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 1956
1957 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 1958 Start, Offset, x, y, fb->pitches[0]);
1959 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
446f2545 1960 I915_MODIFY_DISPBASE(DSPSURF(plane), Start);
17638cd6
JB		 1961 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1962 I915_WRITE(DSPADDR(plane), Offset);
1963 POSTING_READ(reg);
1964
1965 return 0;
1966}
1967
1968/* Assume fb object is pinned & idle & fenced and just update base pointers */
1969static int
1970intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1971 int x, int y, enum mode_set_atomic state)
1972{
1973 struct drm_device *dev = crtc->dev;
1974 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 1975
6b8e6ed0
CW		 1976 if (dev_priv->display.disable_fbc)
1977 dev_priv->display.disable_fbc(dev);
3dec0095 1978 intel_increase_pllclock(crtc);
81255565 1979
6b8e6ed0 1980 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 1981}
1982
14667a4b
CW		 1983static int
1984intel_finish_fb(struct drm_framebuffer *old_fb)
1985{
1986 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1987 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1988 bool was_interruptible = dev_priv->mm.interruptible;
1989 int ret;
1990
1991 wait_event(dev_priv->pending_flip_queue,
1992 atomic_read(&dev_priv->mm.wedged) ||
1993 atomic_read(&obj->pending_flip) == 0);
1994
1995 /* Big Hammer, we also need to ensure that any pending
1996 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1997 * current scanout is retired before unpinning the old
1998 * framebuffer.
1999 *
2000 * This should only fail upon a hung GPU, in which case we
2001 * can safely continue.
2002 */
2003 dev_priv->mm.interruptible = false;
2004 ret = i915_gem_object_finish_gpu(obj);
2005 dev_priv->mm.interruptible = was_interruptible;
2006
2007 return ret;
2008}
2009
5c3b82e2 2010static int
3c4fdcfb
KH		 2011intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2012 struct drm_framebuffer *old_fb)
79e53945
JB		 2013{
2014 struct drm_device *dev = crtc->dev;
6b8e6ed0 2015 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2016 struct drm_i915_master_private *master_priv;
2017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2018 int ret;
79e53945
JB		 2019
2020 /* no fb bound */
2021 if (!crtc->fb) {
a5071c2f 2022 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2023 return 0;
2024 }
2025
5826eca5
ED		 2026 if(intel_crtc->plane > dev_priv->num_pipe) {
2027 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2028 intel_crtc->plane,
2029 dev_priv->num_pipe);
5c3b82e2 2030 return -EINVAL;
79e53945
JB		 2031 }
2032
5c3b82e2 2033 mutex_lock(&dev->struct_mutex);
265db958
CW		 2034 ret = intel_pin_and_fence_fb_obj(dev,
2035 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2036 NULL);
5c3b82e2
CW		 2037 if (ret != 0) {
2038 mutex_unlock(&dev->struct_mutex);
a5071c2f 2039 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2040 return ret;
2041 }
79e53945 2042
14667a4b
CW		 2043 if (old_fb)
2044 intel_finish_fb(old_fb);
265db958 2045
6b8e6ed0 2046 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2047 if (ret) {
1690e1eb 2048 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2049 mutex_unlock(&dev->struct_mutex);
a5071c2f 2050 DRM_ERROR("failed to update base address\n");
4e6cfefc 2051 return ret;
79e53945 2052 }
3c4fdcfb 2053
b7f1de28
CW		 2054 if (old_fb) {
2055 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2056 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2057 }
652c393a 2058
6b8e6ed0 2059 intel_update_fbc(dev);
5c3b82e2 2060 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2061
2062 if (!dev->primary->master)
5c3b82e2 2063 return 0;
79e53945
JB		 2064
2065 master_priv = dev->primary->master->driver_priv;
2066 if (!master_priv->sarea_priv)
5c3b82e2 2067 return 0;
79e53945 2068
265db958 2069 if (intel_crtc->pipe) {
79e53945
JB		 2070 master_priv->sarea_priv->pipeB_x = x;
2071 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2072 } else {
2073 master_priv->sarea_priv->pipeA_x = x;
2074 master_priv->sarea_priv->pipeA_y = y;
79e53945 2075 }
5c3b82e2
CW		 2076
2077 return 0;
79e53945
JB		 2078}
2079
5eddb70b 2080static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 u32 dpa_ctl;
2085
28c97730 2086 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2087 dpa_ctl = I915_READ(DP_A);
2088 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2089
2090 if (clock < 200000) {
2091 u32 temp;
2092 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2093 /* workaround for 160Mhz:
2094 1) program 0x4600c bits 15:0 = 0x8124
2095 2) program 0x46010 bit 0 = 1
2096 3) program 0x46034 bit 24 = 1
2097 4) program 0x64000 bit 14 = 1
2098 */
2099 temp = I915_READ(0x4600c);
2100 temp &= 0xffff0000;
2101 I915_WRITE(0x4600c, temp | 0x8124);
2102
2103 temp = I915_READ(0x46010);
2104 I915_WRITE(0x46010, temp | 1);
2105
2106 temp = I915_READ(0x46034);
2107 I915_WRITE(0x46034, temp | (1 << 24));
2108 } else {
2109 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2110 }
2111 I915_WRITE(DP_A, dpa_ctl);
2112
5eddb70b 2113 POSTING_READ(DP_A);
32f9d658
ZW		 2114 udelay(500);
2115}
2116
5e84e1a4
ZW		 2117static void intel_fdi_normal_train(struct drm_crtc *crtc)
2118{
2119 struct drm_device *dev = crtc->dev;
2120 struct drm_i915_private *dev_priv = dev->dev_private;
2121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2122 int pipe = intel_crtc->pipe;
2123 u32 reg, temp;
2124
2125 /* enable normal train */
2126 reg = FDI_TX_CTL(pipe);
2127 temp = I915_READ(reg);
61e499bf 2128 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2129 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2130 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2131 } else {
2132 temp &= ~FDI_LINK_TRAIN_NONE;
2133 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2134 }
5e84e1a4
ZW		 2135 I915_WRITE(reg, temp);
2136
2137 reg = FDI_RX_CTL(pipe);
2138 temp = I915_READ(reg);
2139 if (HAS_PCH_CPT(dev)) {
2140 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2141 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2142 } else {
2143 temp &= ~FDI_LINK_TRAIN_NONE;
2144 temp |= FDI_LINK_TRAIN_NONE;
2145 }
2146 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2147
2148 /* wait one idle pattern time */
2149 POSTING_READ(reg);
2150 udelay(1000);
357555c0
JB		 2151
2152 /* IVB wants error correction enabled */
2153 if (IS_IVYBRIDGE(dev))
2154 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2155 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2156}
2157
291427f5
JB		 2158static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2159{
2160 struct drm_i915_private *dev_priv = dev->dev_private;
2161 u32 flags = I915_READ(SOUTH_CHICKEN1);
2162
2163 flags |= FDI_PHASE_SYNC_OVR(pipe);
2164 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2165 flags |= FDI_PHASE_SYNC_EN(pipe);
2166 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2167 POSTING_READ(SOUTH_CHICKEN1);
2168}
2169
8db9d77b
ZW		 2170/* The FDI link training functions for ILK/Ibexpeak. */
2171static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2172{
2173 struct drm_device *dev = crtc->dev;
2174 struct drm_i915_private *dev_priv = dev->dev_private;
2175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2176 int pipe = intel_crtc->pipe;
0fc932b8 2177 int plane = intel_crtc->plane;
5eddb70b 2178 u32 reg, temp, tries;
8db9d77b 2179
0fc932b8
JB		 2180 /* FDI needs bits from pipe & plane first */
2181 assert_pipe_enabled(dev_priv, pipe);
2182 assert_plane_enabled(dev_priv, plane);
2183
e1a44743
AJ		 2184 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2185 for train result */
5eddb70b
CW		 2186 reg = FDI_RX_IMR(pipe);
2187 temp = I915_READ(reg);
e1a44743
AJ		 2188 temp &= ~FDI_RX_SYMBOL_LOCK;
2189 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2190 I915_WRITE(reg, temp);
2191 I915_READ(reg);
e1a44743
AJ		 2192 udelay(150);
2193
8db9d77b 2194 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2195 reg = FDI_TX_CTL(pipe);
2196 temp = I915_READ(reg);
77ffb597
AJ		 2197 temp &= ~(7 << 19);
2198 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2199 temp &= ~FDI_LINK_TRAIN_NONE;
2200 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2201 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2202
5eddb70b
CW		 2203 reg = FDI_RX_CTL(pipe);
2204 temp = I915_READ(reg);
8db9d77b
ZW		 2205 temp &= ~FDI_LINK_TRAIN_NONE;
2206 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2207 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2208
2209 POSTING_READ(reg);
8db9d77b
ZW		 2210 udelay(150);
2211
5b2adf89 2212 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2213 if (HAS_PCH_IBX(dev)) {
2214 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2215 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2216 FDI_RX_PHASE_SYNC_POINTER_EN);
2217 }
5b2adf89 2218
5eddb70b 2219 reg = FDI_RX_IIR(pipe);
e1a44743 2220 for (tries = 0; tries < 5; tries++) {
5eddb70b 2221 temp = I915_READ(reg);
8db9d77b
ZW		 2222 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2223
2224 if ((temp & FDI_RX_BIT_LOCK)) {
2225 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2226 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2227 break;
2228 }
8db9d77b 2229 }
e1a44743 2230 if (tries == 5)
5eddb70b 2231 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2232
2233 /* Train 2 */
5eddb70b
CW		 2234 reg = FDI_TX_CTL(pipe);
2235 temp = I915_READ(reg);
8db9d77b
ZW		 2236 temp &= ~FDI_LINK_TRAIN_NONE;
2237 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2238 I915_WRITE(reg, temp);
8db9d77b 2239
5eddb70b
CW		 2240 reg = FDI_RX_CTL(pipe);
2241 temp = I915_READ(reg);
8db9d77b
ZW		 2242 temp &= ~FDI_LINK_TRAIN_NONE;
2243 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2244 I915_WRITE(reg, temp);
8db9d77b 2245
5eddb70b
CW		 2246 POSTING_READ(reg);
2247 udelay(150);
8db9d77b 2248
5eddb70b 2249 reg = FDI_RX_IIR(pipe);
e1a44743 2250 for (tries = 0; tries < 5; tries++) {
5eddb70b 2251 temp = I915_READ(reg);
8db9d77b
ZW		 2252 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2253
2254 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2255 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2256 DRM_DEBUG_KMS("FDI train 2 done.\n");
2257 break;
2258 }
8db9d77b 2259 }
e1a44743 2260 if (tries == 5)
5eddb70b 2261 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2262
2263 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2264
8db9d77b
ZW		 2265}
2266
0206e353 2267static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2268 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2269 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2270 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2271 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2272};
2273
2274/* The FDI link training functions for SNB/Cougarpoint. */
2275static void gen6_fdi_link_train(struct drm_crtc *crtc)
2276{
2277 struct drm_device *dev = crtc->dev;
2278 struct drm_i915_private *dev_priv = dev->dev_private;
2279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2280 int pipe = intel_crtc->pipe;
fa37d39e 2281 u32 reg, temp, i, retry;
8db9d77b 2282
e1a44743
AJ		 2283 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2284 for train result */
5eddb70b
CW		 2285 reg = FDI_RX_IMR(pipe);
2286 temp = I915_READ(reg);
e1a44743
AJ		 2287 temp &= ~FDI_RX_SYMBOL_LOCK;
2288 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2289 I915_WRITE(reg, temp);
2290
2291 POSTING_READ(reg);
e1a44743
AJ		 2292 udelay(150);
2293
8db9d77b 2294 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2295 reg = FDI_TX_CTL(pipe);
2296 temp = I915_READ(reg);
77ffb597
AJ		 2297 temp &= ~(7 << 19);
2298 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2299 temp &= ~FDI_LINK_TRAIN_NONE;
2300 temp |= FDI_LINK_TRAIN_PATTERN_1;
2301 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2302 /* SNB-B */
2303 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2304 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2305
5eddb70b
CW		 2306 reg = FDI_RX_CTL(pipe);
2307 temp = I915_READ(reg);
8db9d77b
ZW		 2308 if (HAS_PCH_CPT(dev)) {
2309 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2310 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2311 } else {
2312 temp &= ~FDI_LINK_TRAIN_NONE;
2313 temp |= FDI_LINK_TRAIN_PATTERN_1;
2314 }
5eddb70b
CW		 2315 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2316
2317 POSTING_READ(reg);
8db9d77b
ZW		 2318 udelay(150);
2319
291427f5
JB		 2320 if (HAS_PCH_CPT(dev))
2321 cpt_phase_pointer_enable(dev, pipe);
2322
0206e353 2323 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2324 reg = FDI_TX_CTL(pipe);
2325 temp = I915_READ(reg);
8db9d77b
ZW		 2326 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2327 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2328 I915_WRITE(reg, temp);
2329
2330 POSTING_READ(reg);
8db9d77b
ZW		 2331 udelay(500);
2332
fa37d39e
SP		 2333 for (retry = 0; retry < 5; retry++) {
2334 reg = FDI_RX_IIR(pipe);
2335 temp = I915_READ(reg);
2336 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2337 if (temp & FDI_RX_BIT_LOCK) {
2338 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2339 DRM_DEBUG_KMS("FDI train 1 done.\n");
2340 break;
2341 }
2342 udelay(50);
8db9d77b 2343 }
fa37d39e
SP		 2344 if (retry < 5)
2345 break;
8db9d77b
ZW		 2346 }
2347 if (i == 4)
5eddb70b 2348 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2349
2350 /* Train 2 */
5eddb70b
CW		 2351 reg = FDI_TX_CTL(pipe);
2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 temp &= ~FDI_LINK_TRAIN_NONE;
2354 temp |= FDI_LINK_TRAIN_PATTERN_2;
2355 if (IS_GEN6(dev)) {
2356 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2357 /* SNB-B */
2358 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2359 }
5eddb70b 2360 I915_WRITE(reg, temp);
8db9d77b 2361
5eddb70b
CW		 2362 reg = FDI_RX_CTL(pipe);
2363 temp = I915_READ(reg);
8db9d77b
ZW		 2364 if (HAS_PCH_CPT(dev)) {
2365 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2366 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2367 } else {
2368 temp &= ~FDI_LINK_TRAIN_NONE;
2369 temp |= FDI_LINK_TRAIN_PATTERN_2;
2370 }
5eddb70b
CW		 2371 I915_WRITE(reg, temp);
2372
2373 POSTING_READ(reg);
8db9d77b
ZW		 2374 udelay(150);
2375
0206e353 2376 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2377 reg = FDI_TX_CTL(pipe);
2378 temp = I915_READ(reg);
8db9d77b
ZW		 2379 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2380 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2381 I915_WRITE(reg, temp);
2382
2383 POSTING_READ(reg);
8db9d77b
ZW		 2384 udelay(500);
2385
fa37d39e
SP		 2386 for (retry = 0; retry < 5; retry++) {
2387 reg = FDI_RX_IIR(pipe);
2388 temp = I915_READ(reg);
2389 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2390 if (temp & FDI_RX_SYMBOL_LOCK) {
2391 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2392 DRM_DEBUG_KMS("FDI train 2 done.\n");
2393 break;
2394 }
2395 udelay(50);
8db9d77b 2396 }
fa37d39e
SP		 2397 if (retry < 5)
2398 break;
8db9d77b
ZW		 2399 }
2400 if (i == 4)
5eddb70b 2401 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2402
2403 DRM_DEBUG_KMS("FDI train done.\n");
2404}
2405
357555c0
JB		 2406/* Manual link training for Ivy Bridge A0 parts */
2407static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2408{
2409 struct drm_device *dev = crtc->dev;
2410 struct drm_i915_private *dev_priv = dev->dev_private;
2411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2412 int pipe = intel_crtc->pipe;
2413 u32 reg, temp, i;
2414
2415 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2416 for train result */
2417 reg = FDI_RX_IMR(pipe);
2418 temp = I915_READ(reg);
2419 temp &= ~FDI_RX_SYMBOL_LOCK;
2420 temp &= ~FDI_RX_BIT_LOCK;
2421 I915_WRITE(reg, temp);
2422
2423 POSTING_READ(reg);
2424 udelay(150);
2425
2426 /* enable CPU FDI TX and PCH FDI RX */
2427 reg = FDI_TX_CTL(pipe);
2428 temp = I915_READ(reg);
2429 temp &= ~(7 << 19);
2430 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2431 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2432 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2433 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2435 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2436 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2437
2438 reg = FDI_RX_CTL(pipe);
2439 temp = I915_READ(reg);
2440 temp &= ~FDI_LINK_TRAIN_AUTO;
2441 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2442 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2443 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2444 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2445
2446 POSTING_READ(reg);
2447 udelay(150);
2448
291427f5
JB		 2449 if (HAS_PCH_CPT(dev))
2450 cpt_phase_pointer_enable(dev, pipe);
2451
0206e353 2452 for (i = 0; i < 4; i++) {
357555c0
JB		 2453 reg = FDI_TX_CTL(pipe);
2454 temp = I915_READ(reg);
2455 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2456 temp |= snb_b_fdi_train_param[i];
2457 I915_WRITE(reg, temp);
2458
2459 POSTING_READ(reg);
2460 udelay(500);
2461
2462 reg = FDI_RX_IIR(pipe);
2463 temp = I915_READ(reg);
2464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2465
2466 if (temp & FDI_RX_BIT_LOCK ||
2467 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2468 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2469 DRM_DEBUG_KMS("FDI train 1 done.\n");
2470 break;
2471 }
2472 }
2473 if (i == 4)
2474 DRM_ERROR("FDI train 1 fail!\n");
2475
2476 /* Train 2 */
2477 reg = FDI_TX_CTL(pipe);
2478 temp = I915_READ(reg);
2479 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2480 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2481 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2482 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2483 I915_WRITE(reg, temp);
2484
2485 reg = FDI_RX_CTL(pipe);
2486 temp = I915_READ(reg);
2487 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2488 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2489 I915_WRITE(reg, temp);
2490
2491 POSTING_READ(reg);
2492 udelay(150);
2493
0206e353 2494 for (i = 0; i < 4; i++) {
357555c0
JB		 2495 reg = FDI_TX_CTL(pipe);
2496 temp = I915_READ(reg);
2497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2498 temp |= snb_b_fdi_train_param[i];
2499 I915_WRITE(reg, temp);
2500
2501 POSTING_READ(reg);
2502 udelay(500);
2503
2504 reg = FDI_RX_IIR(pipe);
2505 temp = I915_READ(reg);
2506 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2507
2508 if (temp & FDI_RX_SYMBOL_LOCK) {
2509 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2510 DRM_DEBUG_KMS("FDI train 2 done.\n");
2511 break;
2512 }
2513 }
2514 if (i == 4)
2515 DRM_ERROR("FDI train 2 fail!\n");
2516
2517 DRM_DEBUG_KMS("FDI train done.\n");
2518}
2519
2520static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2521{
2522 struct drm_device *dev = crtc->dev;
2523 struct drm_i915_private *dev_priv = dev->dev_private;
2524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2525 int pipe = intel_crtc->pipe;
5eddb70b 2526 u32 reg, temp;
79e53945 2527
c64e311e 2528 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2529 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2530 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2531
c98e9dcf 2532 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2533 reg = FDI_RX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2536 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2537 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2538 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2539
2540 POSTING_READ(reg);
c98e9dcf
JB		 2541 udelay(200);
2542
2543 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2544 temp = I915_READ(reg);
2545 I915_WRITE(reg, temp | FDI_PCDCLK);
2546
2547 POSTING_READ(reg);
c98e9dcf
JB		 2548 udelay(200);
2549
bf507ef7
ED		 2550 /* On Haswell, the PLL configuration for ports and pipes is handled
2551 * separately, as part of DDI setup */
2552 if (!IS_HASWELL(dev)) {
2553 /* Enable CPU FDI TX PLL, always on for Ironlake */
2554 reg = FDI_TX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2557 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2558
bf507ef7
ED		 2559 POSTING_READ(reg);
2560 udelay(100);
2561 }
6be4a607 2562 }
0e23b99d
JB		 2563}
2564
291427f5
JB		 2565static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2566{
2567 struct drm_i915_private *dev_priv = dev->dev_private;
2568 u32 flags = I915_READ(SOUTH_CHICKEN1);
2569
2570 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2571 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2572 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2573 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2574 POSTING_READ(SOUTH_CHICKEN1);
2575}
0fc932b8
JB		 2576static void ironlake_fdi_disable(struct drm_crtc *crtc)
2577{
2578 struct drm_device *dev = crtc->dev;
2579 struct drm_i915_private *dev_priv = dev->dev_private;
2580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2581 int pipe = intel_crtc->pipe;
2582 u32 reg, temp;
2583
2584 /* disable CPU FDI tx and PCH FDI rx */
2585 reg = FDI_TX_CTL(pipe);
2586 temp = I915_READ(reg);
2587 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2588 POSTING_READ(reg);
2589
2590 reg = FDI_RX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 temp &= ~(0x7 << 16);
2593 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2594 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2595
2596 POSTING_READ(reg);
2597 udelay(100);
2598
2599 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2600 if (HAS_PCH_IBX(dev)) {
2601 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2602 I915_WRITE(FDI_RX_CHICKEN(pipe),
2603 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2604 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2605 } else if (HAS_PCH_CPT(dev)) {
2606 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2607 }
0fc932b8
JB		 2608
2609 /* still set train pattern 1 */
2610 reg = FDI_TX_CTL(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_LINK_TRAIN_NONE;
2613 temp |= FDI_LINK_TRAIN_PATTERN_1;
2614 I915_WRITE(reg, temp);
2615
2616 reg = FDI_RX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 if (HAS_PCH_CPT(dev)) {
2619 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2620 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2621 } else {
2622 temp &= ~FDI_LINK_TRAIN_NONE;
2623 temp |= FDI_LINK_TRAIN_PATTERN_1;
2624 }
2625 /* BPC in FDI rx is consistent with that in PIPECONF */
2626 temp &= ~(0x07 << 16);
2627 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2628 I915_WRITE(reg, temp);
2629
2630 POSTING_READ(reg);
2631 udelay(100);
2632}
2633
e6c3a2a6
CW		 2634static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2635{
0f91128d 2636 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2637
2638 if (crtc->fb == NULL)
2639 return;
2640
0f91128d
CW		 2641 mutex_lock(&dev->struct_mutex);
2642 intel_finish_fb(crtc->fb);
2643 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2644}
2645
040484af
JB		 2646static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2647{
2648 struct drm_device *dev = crtc->dev;
2649 struct drm_mode_config *mode_config = &dev->mode_config;
2650 struct intel_encoder *encoder;
2651
2652 /*
2653 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2654 * must be driven by its own crtc; no sharing is possible.
2655 */
2656 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2657 if (encoder->base.crtc != crtc)
2658 continue;
2659
6ee8bab0
ED		 2660 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2661 * CPU handles all others */
2662 if (IS_HASWELL(dev)) {
2663 /* It is still unclear how this will work on PPT, so throw up a warning */
2664 WARN_ON(!HAS_PCH_LPT(dev));
2665
2666 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2667 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2668 return true;
2669 } else {
2670 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2671 encoder->type);
2672 return false;
2673 }
2674 }
2675
040484af
JB		 2676 switch (encoder->type) {
2677 case INTEL_OUTPUT_EDP:
2678 if (!intel_encoder_is_pch_edp(&encoder->base))
2679 return false;
2680 continue;
2681 }
2682 }
2683
2684 return true;
2685}
2686
e615efe4
ED		 2687/* Program iCLKIP clock to the desired frequency */
2688static void lpt_program_iclkip(struct drm_crtc *crtc)
2689{
2690 struct drm_device *dev = crtc->dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2693 u32 temp;
2694
2695 /* It is necessary to ungate the pixclk gate prior to programming
2696 * the divisors, and gate it back when it is done.
2697 */
2698 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2699
2700 /* Disable SSCCTL */
2701 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2702 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2703 SBI_SSCCTL_DISABLE);
2704
2705 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2706 if (crtc->mode.clock == 20000) {
2707 auxdiv = 1;
2708 divsel = 0x41;
2709 phaseinc = 0x20;
2710 } else {
2711 /* The iCLK virtual clock root frequency is in MHz,
2712 * but the crtc->mode.clock in in KHz. To get the divisors,
2713 * it is necessary to divide one by another, so we
2714 * convert the virtual clock precision to KHz here for higher
2715 * precision.
2716 */
2717 u32 iclk_virtual_root_freq = 172800 * 1000;
2718 u32 iclk_pi_range = 64;
2719 u32 desired_divisor, msb_divisor_value, pi_value;
2720
2721 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2722 msb_divisor_value = desired_divisor / iclk_pi_range;
2723 pi_value = desired_divisor % iclk_pi_range;
2724
2725 auxdiv = 0;
2726 divsel = msb_divisor_value - 2;
2727 phaseinc = pi_value;
2728 }
2729
2730 /* This should not happen with any sane values */
2731 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2732 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2733 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2734 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2735
2736 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2737 crtc->mode.clock,
2738 auxdiv,
2739 divsel,
2740 phasedir,
2741 phaseinc);
2742
2743 /* Program SSCDIVINTPHASE6 */
2744 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2745 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2746 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2747 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2748 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2749 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2750 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2751
2752 intel_sbi_write(dev_priv,
2753 SBI_SSCDIVINTPHASE6,
2754 temp);
2755
2756 /* Program SSCAUXDIV */
2757 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2758 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2759 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2760 intel_sbi_write(dev_priv,
2761 SBI_SSCAUXDIV6,
2762 temp);
2763
2764
2765 /* Enable modulator and associated divider */
2766 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2767 temp &= ~SBI_SSCCTL_DISABLE;
2768 intel_sbi_write(dev_priv,
2769 SBI_SSCCTL6,
2770 temp);
2771
2772 /* Wait for initialization time */
2773 udelay(24);
2774
2775 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2776}
2777
f67a559d
JB		 2778/*
2779 * Enable PCH resources required for PCH ports:
2780 * - PCH PLLs
2781 * - FDI training & RX/TX
2782 * - update transcoder timings
2783 * - DP transcoding bits
2784 * - transcoder
2785 */
2786static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2787{
2788 struct drm_device *dev = crtc->dev;
2789 struct drm_i915_private *dev_priv = dev->dev_private;
2790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2791 int pipe = intel_crtc->pipe;
ee7b9f93 2792 u32 reg, temp;
2c07245f 2793
e7e164db
CW		 2794 assert_transcoder_disabled(dev_priv, pipe);
2795
c98e9dcf 2796 /* For PCH output, training FDI link */
674cf967 2797 dev_priv->display.fdi_link_train(crtc);
2c07245f 2798
6f13b7b5
CW		 2799 intel_enable_pch_pll(intel_crtc);
2800
e615efe4
ED		 2801 if (HAS_PCH_LPT(dev)) {
2802 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2803 lpt_program_iclkip(crtc);
2804 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2805 u32 sel;
4b645f14 2806
c98e9dcf 2807 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2808 switch (pipe) {
2809 default:
2810 case 0:
2811 temp |= TRANSA_DPLL_ENABLE;
2812 sel = TRANSA_DPLLB_SEL;
2813 break;
2814 case 1:
2815 temp |= TRANSB_DPLL_ENABLE;
2816 sel = TRANSB_DPLLB_SEL;
2817 break;
2818 case 2:
2819 temp |= TRANSC_DPLL_ENABLE;
2820 sel = TRANSC_DPLLB_SEL;
2821 break;
d64311ab 2822 }
ee7b9f93
JB		 2823 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2824 temp |= sel;
2825 else
2826 temp &= ~sel;
c98e9dcf 2827 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2828 }
5eddb70b 2829
d9b6cb56
JB		 2830 /* set transcoder timing, panel must allow it */
2831 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2832 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2833 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2834 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2835
5eddb70b
CW		 2836 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2837 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2838 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 2839 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 2840
f57e1e3a
ED		 2841 if (!IS_HASWELL(dev))
2842 intel_fdi_normal_train(crtc);
5e84e1a4 2843
c98e9dcf
JB		 2844 /* For PCH DP, enable TRANS_DP_CTL */
2845 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2846 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2847 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2848 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2849 reg = TRANS_DP_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2852 TRANS_DP_SYNC_MASK |
2853 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2854 temp |= (TRANS_DP_OUTPUT_ENABLE |
2855 TRANS_DP_ENH_FRAMING);
9325c9f0 2856 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2857
2858 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2859 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2860 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2861 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2862
2863 switch (intel_trans_dp_port_sel(crtc)) {
2864 case PCH_DP_B:
5eddb70b 2865 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2866 break;
2867 case PCH_DP_C:
5eddb70b 2868 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2869 break;
2870 case PCH_DP_D:
5eddb70b 2871 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2872 break;
2873 default:
2874 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2875 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2876 break;
32f9d658 2877 }
2c07245f 2878
5eddb70b 2879 I915_WRITE(reg, temp);
6be4a607 2880 }
b52eb4dc 2881
040484af 2882 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2883}
2884
ee7b9f93
JB		 2885static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
2886{
2887 struct intel_pch_pll *pll = intel_crtc->pch_pll;
2888
2889 if (pll == NULL)
2890 return;
2891
2892 if (pll->refcount == 0) {
2893 WARN(1, "bad PCH PLL refcount\n");
2894 return;
2895 }
2896
2897 --pll->refcount;
2898 intel_crtc->pch_pll = NULL;
2899}
2900
2901static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
2902{
2903 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
2904 struct intel_pch_pll *pll;
2905 int i;
2906
2907 pll = intel_crtc->pch_pll;
2908 if (pll) {
2909 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
2910 intel_crtc->base.base.id, pll->pll_reg);
2911 goto prepare;
2912 }
2913
2914 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2915 pll = &dev_priv->pch_plls[i];
2916
2917 /* Only want to check enabled timings first */
2918 if (pll->refcount == 0)
2919 continue;
2920
2921 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
2922 fp == I915_READ(pll->fp0_reg)) {
2923 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
2924 intel_crtc->base.base.id,
2925 pll->pll_reg, pll->refcount, pll->active);
2926
2927 goto found;
2928 }
2929 }
2930
2931 /* Ok no matching timings, maybe there's a free one? */
2932 for (i = 0; i < dev_priv->num_pch_pll; i++) {
2933 pll = &dev_priv->pch_plls[i];
2934 if (pll->refcount == 0) {
2935 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
2936 intel_crtc->base.base.id, pll->pll_reg);
2937 goto found;
2938 }
2939 }
2940
2941 return NULL;
2942
2943found:
2944 intel_crtc->pch_pll = pll;
2945 pll->refcount++;
2946 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
2947prepare: /* separate function? */
2948 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 2949
e04c7350
CW		 2950 /* Wait for the clocks to stabilize before rewriting the regs */
2951 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2952 POSTING_READ(pll->pll_reg);
2953 udelay(150);
e04c7350
CW		 2954
2955 I915_WRITE(pll->fp0_reg, fp);
2956 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 2957 pll->on = false;
2958 return pll;
2959}
2960
d4270e57
JB		 2961void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2962{
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2965 u32 temp;
2966
2967 temp = I915_READ(dslreg);
2968 udelay(500);
2969 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2970 /* Without this, mode sets may fail silently on FDI */
2971 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2972 udelay(250);
2973 I915_WRITE(tc2reg, 0);
2974 if (wait_for(I915_READ(dslreg) != temp, 5))
2975 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2976 }
2977}
2978
f67a559d
JB		 2979static void ironlake_crtc_enable(struct drm_crtc *crtc)
2980{
2981 struct drm_device *dev = crtc->dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2984 int pipe = intel_crtc->pipe;
2985 int plane = intel_crtc->plane;
2986 u32 temp;
2987 bool is_pch_port;
2988
2989 if (intel_crtc->active)
2990 return;
2991
2992 intel_crtc->active = true;
2993 intel_update_watermarks(dev);
2994
2995 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2996 temp = I915_READ(PCH_LVDS);
2997 if ((temp & LVDS_PORT_EN) == 0)
2998 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2999 }
3000
3001 is_pch_port = intel_crtc_driving_pch(crtc);
3002
3003 if (is_pch_port)
357555c0 3004 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3005 else
3006 ironlake_fdi_disable(crtc);
3007
3008 /* Enable panel fitting for LVDS */
3009 if (dev_priv->pch_pf_size &&
3010 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3011 /* Force use of hard-coded filter coefficients
3012 * as some pre-programmed values are broken,
3013 * e.g. x201.
3014 */
9db4a9c7
JB		 3015 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3016 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3017 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3018 }
3019
9c54c0dd
JB		 3020 /*
3021 * On ILK+ LUT must be loaded before the pipe is running but with
3022 * clocks enabled
3023 */
3024 intel_crtc_load_lut(crtc);
3025
f67a559d
JB		 3026 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3027 intel_enable_plane(dev_priv, plane, pipe);
3028
3029 if (is_pch_port)
3030 ironlake_pch_enable(crtc);
c98e9dcf 3031
d1ebd816 3032 mutex_lock(&dev->struct_mutex);
bed4a673 3033 intel_update_fbc(dev);
d1ebd816
BW		 3034 mutex_unlock(&dev->struct_mutex);
3035
6b383a7f 3036 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3037}
3038
3039static void ironlake_crtc_disable(struct drm_crtc *crtc)
3040{
3041 struct drm_device *dev = crtc->dev;
3042 struct drm_i915_private *dev_priv = dev->dev_private;
3043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3044 int pipe = intel_crtc->pipe;
3045 int plane = intel_crtc->plane;
5eddb70b 3046 u32 reg, temp;
b52eb4dc 3047
f7abfe8b
CW		 3048 if (!intel_crtc->active)
3049 return;
3050
e6c3a2a6 3051 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3052 drm_vblank_off(dev, pipe);
6b383a7f 3053 intel_crtc_update_cursor(crtc, false);
5eddb70b 3054
b24e7179 3055 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3056
973d04f9
CW		 3057 if (dev_priv->cfb_plane == plane)
3058 intel_disable_fbc(dev);
2c07245f 3059
b24e7179 3060 intel_disable_pipe(dev_priv, pipe);
32f9d658 3061
6be4a607 3062 /* Disable PF */
9db4a9c7
JB		 3063 I915_WRITE(PF_CTL(pipe), 0);
3064 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3065
0fc932b8 3066 ironlake_fdi_disable(crtc);
2c07245f 3067
47a05eca
JB		 3068 /* This is a horrible layering violation; we should be doing this in
3069 * the connector/encoder ->prepare instead, but we don't always have
3070 * enough information there about the config to know whether it will
3071 * actually be necessary or just cause undesired flicker.
3072 */
3073 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3074
040484af 3075 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3076
6be4a607
JB		 3077 if (HAS_PCH_CPT(dev)) {
3078 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3079 reg = TRANS_DP_CTL(pipe);
3080 temp = I915_READ(reg);
3081 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3082 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3083 I915_WRITE(reg, temp);
6be4a607
JB		 3084
3085 /* disable DPLL_SEL */
3086 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3087 switch (pipe) {
3088 case 0:
d64311ab 3089 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3090 break;
3091 case 1:
6be4a607 3092 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3093 break;
3094 case 2:
4b645f14 3095 /* C shares PLL A or B */
d64311ab 3096 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3097 break;
3098 default:
3099 BUG(); /* wtf */
3100 }
6be4a607 3101 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3102 }
e3421a18 3103
6be4a607 3104 /* disable PCH DPLL */
ee7b9f93 3105 intel_disable_pch_pll(intel_crtc);
8db9d77b 3106
6be4a607 3107 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3108 reg = FDI_RX_CTL(pipe);
3109 temp = I915_READ(reg);
3110 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3111
6be4a607 3112 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3113 reg = FDI_TX_CTL(pipe);
3114 temp = I915_READ(reg);
3115 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3116
3117 POSTING_READ(reg);
6be4a607 3118 udelay(100);
8db9d77b 3119
5eddb70b
CW		 3120 reg = FDI_RX_CTL(pipe);
3121 temp = I915_READ(reg);
3122 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3123
6be4a607 3124 /* Wait for the clocks to turn off. */
5eddb70b 3125 POSTING_READ(reg);
6be4a607 3126 udelay(100);
6b383a7f 3127
f7abfe8b 3128 intel_crtc->active = false;
6b383a7f 3129 intel_update_watermarks(dev);
d1ebd816
BW		 3130
3131 mutex_lock(&dev->struct_mutex);
6b383a7f 3132 intel_update_fbc(dev);
d1ebd816 3133 mutex_unlock(&dev->struct_mutex);
6be4a607 3134}
1b3c7a47 3135
6be4a607
JB		 3136static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3137{
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 int pipe = intel_crtc->pipe;
3140 int plane = intel_crtc->plane;
8db9d77b 3141
6be4a607
JB		 3142 /* XXX: When our outputs are all unaware of DPMS modes other than off
3143 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3144 */
3145 switch (mode) {
3146 case DRM_MODE_DPMS_ON:
3147 case DRM_MODE_DPMS_STANDBY:
3148 case DRM_MODE_DPMS_SUSPEND:
3149 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3150 ironlake_crtc_enable(crtc);
3151 break;
1b3c7a47 3152
6be4a607
JB		 3153 case DRM_MODE_DPMS_OFF:
3154 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3155 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3156 break;
3157 }
3158}
3159
ee7b9f93
JB		 3160static void ironlake_crtc_off(struct drm_crtc *crtc)
3161{
3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163 intel_put_pch_pll(intel_crtc);
3164}
3165
02e792fb
DV		 3166static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3167{
02e792fb 3168 if (!enable && intel_crtc->overlay) {
23f09ce3 3169 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3170 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3171
23f09ce3 3172 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3173 dev_priv->mm.interruptible = false;
3174 (void) intel_overlay_switch_off(intel_crtc->overlay);
3175 dev_priv->mm.interruptible = true;
23f09ce3 3176 mutex_unlock(&dev->struct_mutex);
02e792fb 3177 }
02e792fb 3178
5dcdbcb0
CW		 3179 /* Let userspace switch the overlay on again. In most cases userspace
3180 * has to recompute where to put it anyway.
3181 */
02e792fb
DV		 3182}
3183
0b8765c6 3184static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3185{
3186 struct drm_device *dev = crtc->dev;
79e53945
JB		 3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 int pipe = intel_crtc->pipe;
80824003 3190 int plane = intel_crtc->plane;
79e53945 3191
f7abfe8b
CW		 3192 if (intel_crtc->active)
3193 return;
3194
3195 intel_crtc->active = true;
6b383a7f
CW		 3196 intel_update_watermarks(dev);
3197
63d7bbe9 3198 intel_enable_pll(dev_priv, pipe);
040484af 3199 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3200 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3201
0b8765c6 3202 intel_crtc_load_lut(crtc);
bed4a673 3203 intel_update_fbc(dev);
79e53945 3204
0b8765c6
JB		 3205 /* Give the overlay scaler a chance to enable if it's on this pipe */
3206 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3207 intel_crtc_update_cursor(crtc, true);
0b8765c6 3208}
79e53945 3209
0b8765c6
JB		 3210static void i9xx_crtc_disable(struct drm_crtc *crtc)
3211{
3212 struct drm_device *dev = crtc->dev;
3213 struct drm_i915_private *dev_priv = dev->dev_private;
3214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3215 int pipe = intel_crtc->pipe;
3216 int plane = intel_crtc->plane;
b690e96c 3217
f7abfe8b
CW		 3218 if (!intel_crtc->active)
3219 return;
3220
0b8765c6 3221 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3222 intel_crtc_wait_for_pending_flips(crtc);
3223 drm_vblank_off(dev, pipe);
0b8765c6 3224 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3225 intel_crtc_update_cursor(crtc, false);
0b8765c6 3226
973d04f9
CW		 3227 if (dev_priv->cfb_plane == plane)
3228 intel_disable_fbc(dev);
79e53945 3229
b24e7179 3230 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3231 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3232 intel_disable_pll(dev_priv, pipe);
0b8765c6 3233
f7abfe8b 3234 intel_crtc->active = false;
6b383a7f
CW		 3235 intel_update_fbc(dev);
3236 intel_update_watermarks(dev);
0b8765c6
JB		 3237}
3238
3239static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3240{
3241 /* XXX: When our outputs are all unaware of DPMS modes other than off
3242 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3243 */
3244 switch (mode) {
3245 case DRM_MODE_DPMS_ON:
3246 case DRM_MODE_DPMS_STANDBY:
3247 case DRM_MODE_DPMS_SUSPEND:
3248 i9xx_crtc_enable(crtc);
3249 break;
3250 case DRM_MODE_DPMS_OFF:
3251 i9xx_crtc_disable(crtc);
79e53945
JB		 3252 break;
3253 }
2c07245f
ZW		 3254}
3255
ee7b9f93
JB		 3256static void i9xx_crtc_off(struct drm_crtc *crtc)
3257{
3258}
3259
2c07245f
ZW		 3260/**
3261 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3262 */
3263static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3264{
3265 struct drm_device *dev = crtc->dev;
e70236a8 3266 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3267 struct drm_i915_master_private *master_priv;
3268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3269 int pipe = intel_crtc->pipe;
3270 bool enabled;
3271
032d2a0d
CW		 3272 if (intel_crtc->dpms_mode == mode)
3273 return;
3274
65655d4a 3275 intel_crtc->dpms_mode = mode;
debcaddc 3276
e70236a8 3277 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3278
3279 if (!dev->primary->master)
3280 return;
3281
3282 master_priv = dev->primary->master->driver_priv;
3283 if (!master_priv->sarea_priv)
3284 return;
3285
3286 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3287
3288 switch (pipe) {
3289 case 0:
3290 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3291 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3292 break;
3293 case 1:
3294 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3295 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3296 break;
3297 default:
9db4a9c7 3298 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3299 break;
3300 }
79e53945
JB		 3301}
3302
cdd59983
CW		 3303static void intel_crtc_disable(struct drm_crtc *crtc)
3304{
3305 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3306 struct drm_device *dev = crtc->dev;
ee7b9f93 3307 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3308
3309 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3310 dev_priv->display.off(crtc);
3311
931872fc
CW		 3312 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3313 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3314
3315 if (crtc->fb) {
3316 mutex_lock(&dev->struct_mutex);
1690e1eb 3317 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3318 mutex_unlock(&dev->struct_mutex);
3319 }
3320}
3321
7e7d76c3
JB		 3322/* Prepare for a mode set.
3323 *
3324 * Note we could be a lot smarter here. We need to figure out which outputs
3325 * will be enabled, which disabled (in short, how the config will changes)
3326 * and perform the minimum necessary steps to accomplish that, e.g. updating
3327 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3328 * panel fitting is in the proper state, etc.
3329 */
3330static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3331{
7e7d76c3 3332 i9xx_crtc_disable(crtc);
79e53945
JB		 3333}
3334
7e7d76c3 3335static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3336{
7e7d76c3 3337 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3338}
3339
3340static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3341{
7e7d76c3 3342 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3343}
3344
3345static void ironlake_crtc_commit(struct drm_crtc *crtc)
3346{
7e7d76c3 3347 ironlake_crtc_enable(crtc);
79e53945
JB		 3348}
3349
0206e353 3350void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3351{
3352 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3353 /* lvds has its own version of prepare see intel_lvds_prepare */
3354 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3355}
3356
0206e353 3357void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3358{
3359 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3360 struct drm_device *dev = encoder->dev;
d47d7cb8 3361 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3362
79e53945
JB		 3363 /* lvds has its own version of commit see intel_lvds_commit */
3364 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3365
3366 if (HAS_PCH_CPT(dev))
3367 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3368}
3369
ea5b213a
CW		 3370void intel_encoder_destroy(struct drm_encoder *encoder)
3371{
4ef69c7a 3372 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3373
ea5b213a
CW		 3374 drm_encoder_cleanup(encoder);
3375 kfree(intel_encoder);
3376}
3377
79e53945
JB		 3378static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3379 struct drm_display_mode *mode,
3380 struct drm_display_mode *adjusted_mode)
3381{
2c07245f 3382 struct drm_device *dev = crtc->dev;
89749350 3383
bad720ff 3384 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3385 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3386 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3387 return false;
2c07245f 3388 }
89749350 3389
f9bef081
DV		 3390 /* All interlaced capable intel hw wants timings in frames. Note though
3391 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3392 * timings, so we need to be careful not to clobber these.*/
3393 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3394 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3395
79e53945
JB		 3396 return true;
3397}
3398
25eb05fc
JB		 3399static int valleyview_get_display_clock_speed(struct drm_device *dev)
3400{
3401 return 400000; /* FIXME */
3402}
3403
e70236a8
JB		 3404static int i945_get_display_clock_speed(struct drm_device *dev)
3405{
3406 return 400000;
3407}
79e53945 3408
e70236a8 3409static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3410{
e70236a8
JB		 3411 return 333000;
3412}
79e53945 3413
e70236a8
JB		 3414static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3415{
3416 return 200000;
3417}
79e53945 3418
e70236a8
JB		 3419static int i915gm_get_display_clock_speed(struct drm_device *dev)
3420{
3421 u16 gcfgc = 0;
79e53945 3422
e70236a8
JB		 3423 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3424
3425 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3426 return 133000;
3427 else {
3428 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3429 case GC_DISPLAY_CLOCK_333_MHZ:
3430 return 333000;
3431 default:
3432 case GC_DISPLAY_CLOCK_190_200_MHZ:
3433 return 190000;
79e53945 3434 }
e70236a8
JB		 3435 }
3436}
3437
3438static int i865_get_display_clock_speed(struct drm_device *dev)
3439{
3440 return 266000;
3441}
3442
3443static int i855_get_display_clock_speed(struct drm_device *dev)
3444{
3445 u16 hpllcc = 0;
3446 /* Assume that the hardware is in the high speed state. This
3447 * should be the default.
3448 */
3449 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3450 case GC_CLOCK_133_200:
3451 case GC_CLOCK_100_200:
3452 return 200000;
3453 case GC_CLOCK_166_250:
3454 return 250000;
3455 case GC_CLOCK_100_133:
79e53945 3456 return 133000;
e70236a8 3457 }
79e53945 3458
e70236a8
JB		 3459 /* Shouldn't happen */
3460 return 0;
3461}
79e53945 3462
e70236a8
JB		 3463static int i830_get_display_clock_speed(struct drm_device *dev)
3464{
3465 return 133000;
79e53945
JB		 3466}
3467
2c07245f
ZW		 3468struct fdi_m_n {
3469 u32 tu;
3470 u32 gmch_m;
3471 u32 gmch_n;
3472 u32 link_m;
3473 u32 link_n;
3474};
3475
3476static void
3477fdi_reduce_ratio(u32 *num, u32 *den)
3478{
3479 while (*num > 0xffffff || *den > 0xffffff) {
3480 *num >>= 1;
3481 *den >>= 1;
3482 }
3483}
3484
2c07245f 3485static void
f2b115e6
AJ		 3486ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3487 int link_clock, struct fdi_m_n *m_n)
2c07245f 3488{
2c07245f
ZW		 3489 m_n->tu = 64; /* default size */
3490
22ed1113
CW		 3491 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3492 m_n->gmch_m = bits_per_pixel * pixel_clock;
3493 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3494 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3495
22ed1113
CW		 3496 m_n->link_m = pixel_clock;
3497 m_n->link_n = link_clock;
2c07245f
ZW		 3498 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3499}
3500
a7615030
CW		 3501static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3502{
72bbe58c
KP		 3503 if (i915_panel_use_ssc >= 0)
3504 return i915_panel_use_ssc != 0;
3505 return dev_priv->lvds_use_ssc
435793df 3506 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3507}
3508
5a354204
JB		 3509/**
3510 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3511 * @crtc: CRTC structure
3b5c78a3 3512 * @mode: requested mode
5a354204
JB		 3513 *
3514 * A pipe may be connected to one or more outputs. Based on the depth of the
3515 * attached framebuffer, choose a good color depth to use on the pipe.
3516 *
3517 * If possible, match the pipe depth to the fb depth. In some cases, this
3518 * isn't ideal, because the connected output supports a lesser or restricted
3519 * set of depths. Resolve that here:
3520 * LVDS typically supports only 6bpc, so clamp down in that case
3521 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3522 * Displays may support a restricted set as well, check EDID and clamp as
3523 * appropriate.
3b5c78a3 3524 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3525 *
3526 * RETURNS:
3527 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3528 * true if they don't match).
3529 */
3530static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3531 unsigned int *pipe_bpp,
3532 struct drm_display_mode *mode)
5a354204
JB		 3533{
3534 struct drm_device *dev = crtc->dev;
3535 struct drm_i915_private *dev_priv = dev->dev_private;
3536 struct drm_encoder *encoder;
3537 struct drm_connector *connector;
3538 unsigned int display_bpc = UINT_MAX, bpc;
3539
3540 /* Walk the encoders & connectors on this crtc, get min bpc */
3541 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3542 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3543
3544 if (encoder->crtc != crtc)
3545 continue;
3546
3547 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3548 unsigned int lvds_bpc;
3549
3550 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3551 LVDS_A3_POWER_UP)
3552 lvds_bpc = 8;
3553 else
3554 lvds_bpc = 6;
3555
3556 if (lvds_bpc < display_bpc) {
82820490 3557 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3558 display_bpc = lvds_bpc;
3559 }
3560 continue;
3561 }
3562
3563 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3564 /* Use VBT settings if we have an eDP panel */
3565 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3566
3567 if (edp_bpc < display_bpc) {
82820490 3568 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3569 display_bpc = edp_bpc;
3570 }
3571 continue;
3572 }
3573
3574 /* Not one of the known troublemakers, check the EDID */
3575 list_for_each_entry(connector, &dev->mode_config.connector_list,
3576 head) {
3577 if (connector->encoder != encoder)
3578 continue;
3579
62ac41a6
JB		 3580 /* Don't use an invalid EDID bpc value */
3581 if (connector->display_info.bpc &&
3582 connector->display_info.bpc < display_bpc) {
82820490 3583 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3584 display_bpc = connector->display_info.bpc;
3585 }
3586 }
3587
3588 /*
3589 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3590 * through, clamp it down. (Note: >12bpc will be caught below.)
3591 */
3592 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3593 if (display_bpc > 8 && display_bpc < 12) {
82820490 3594 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3595 display_bpc = 12;
3596 } else {
82820490 3597 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3598 display_bpc = 8;
3599 }
3600 }
3601 }
3602
3b5c78a3
AJ		 3603 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3604 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3605 display_bpc = 6;
3606 }
3607
5a354204
JB		 3608 /*
3609 * We could just drive the pipe at the highest bpc all the time and
3610 * enable dithering as needed, but that costs bandwidth. So choose
3611 * the minimum value that expresses the full color range of the fb but
3612 * also stays within the max display bpc discovered above.
3613 */
3614
3615 switch (crtc->fb->depth) {
3616 case 8:
3617 bpc = 8; /* since we go through a colormap */
3618 break;
3619 case 15:
3620 case 16:
3621 bpc = 6; /* min is 18bpp */
3622 break;
3623 case 24:
578393cd 3624 bpc = 8;
5a354204
JB		 3625 break;
3626 case 30:
578393cd 3627 bpc = 10;
5a354204
JB		 3628 break;
3629 case 48:
578393cd 3630 bpc = 12;
5a354204
JB		 3631 break;
3632 default:
3633 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3634 bpc = min((unsigned int)8, display_bpc);
3635 break;
3636 }
3637
578393cd
KP		 3638 display_bpc = min(display_bpc, bpc);
3639
82820490
AJ		 3640 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3641 bpc, display_bpc);
5a354204 3642
578393cd 3643 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3644
3645 return display_bpc != bpc;
3646}
3647
c65d77d8
JB		 3648static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3649{
3650 struct drm_device *dev = crtc->dev;
3651 struct drm_i915_private *dev_priv = dev->dev_private;
3652 int refclk;
3653
3654 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3655 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3656 refclk = dev_priv->lvds_ssc_freq * 1000;
3657 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3658 refclk / 1000);
3659 } else if (!IS_GEN2(dev)) {
3660 refclk = 96000;
3661 } else {
3662 refclk = 48000;
3663 }
3664
3665 return refclk;
3666}
3667
3668static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3669 intel_clock_t *clock)
3670{
3671 /* SDVO TV has fixed PLL values depend on its clock range,
3672 this mirrors vbios setting. */
3673 if (adjusted_mode->clock >= 100000
3674 && adjusted_mode->clock < 140500) {
3675 clock->p1 = 2;
3676 clock->p2 = 10;
3677 clock->n = 3;
3678 clock->m1 = 16;
3679 clock->m2 = 8;
3680 } else if (adjusted_mode->clock >= 140500
3681 && adjusted_mode->clock <= 200000) {
3682 clock->p1 = 1;
3683 clock->p2 = 10;
3684 clock->n = 6;
3685 clock->m1 = 12;
3686 clock->m2 = 8;
3687 }
3688}
3689
a7516a05
JB		 3690static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3691 intel_clock_t *clock,
3692 intel_clock_t *reduced_clock)
3693{
3694 struct drm_device *dev = crtc->dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697 int pipe = intel_crtc->pipe;
3698 u32 fp, fp2 = 0;
3699
3700 if (IS_PINEVIEW(dev)) {
3701 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3702 if (reduced_clock)
3703 fp2 = (1 << reduced_clock->n) << 16 |
3704 reduced_clock->m1 << 8 | reduced_clock->m2;
3705 } else {
3706 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3707 if (reduced_clock)
3708 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3709 reduced_clock->m2;
3710 }
3711
3712 I915_WRITE(FP0(pipe), fp);
3713
3714 intel_crtc->lowfreq_avail = false;
3715 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3716 reduced_clock && i915_powersave) {
3717 I915_WRITE(FP1(pipe), fp2);
3718 intel_crtc->lowfreq_avail = true;
3719 } else {
3720 I915_WRITE(FP1(pipe), fp);
3721 }
3722}
3723
93e537a1
DV		 3724static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3725 struct drm_display_mode *adjusted_mode)
3726{
3727 struct drm_device *dev = crtc->dev;
3728 struct drm_i915_private *dev_priv = dev->dev_private;
3729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3730 int pipe = intel_crtc->pipe;
284d5df5 3731 u32 temp;
93e537a1
DV		 3732
3733 temp = I915_READ(LVDS);
3734 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3735 if (pipe == 1) {
3736 temp |= LVDS_PIPEB_SELECT;
3737 } else {
3738 temp &= ~LVDS_PIPEB_SELECT;
3739 }
3740 /* set the corresponsding LVDS_BORDER bit */
3741 temp |= dev_priv->lvds_border_bits;
3742 /* Set the B0-B3 data pairs corresponding to whether we're going to
3743 * set the DPLLs for dual-channel mode or not.
3744 */
3745 if (clock->p2 == 7)
3746 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3747 else
3748 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3749
3750 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3751 * appropriately here, but we need to look more thoroughly into how
3752 * panels behave in the two modes.
3753 */
3754 /* set the dithering flag on LVDS as needed */
3755 if (INTEL_INFO(dev)->gen >= 4) {
3756 if (dev_priv->lvds_dither)
3757 temp |= LVDS_ENABLE_DITHER;
3758 else
3759 temp &= ~LVDS_ENABLE_DITHER;
3760 }
284d5df5 3761 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3762 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3763 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3764 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3765 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3766 I915_WRITE(LVDS, temp);
3767}
3768
eb1cbe48
DV		 3769static void i9xx_update_pll(struct drm_crtc *crtc,
3770 struct drm_display_mode *mode,
3771 struct drm_display_mode *adjusted_mode,
3772 intel_clock_t *clock, intel_clock_t *reduced_clock,
3773 int num_connectors)
3774{
3775 struct drm_device *dev = crtc->dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3778 int pipe = intel_crtc->pipe;
3779 u32 dpll;
3780 bool is_sdvo;
3781
3782 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
3783 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
3784
3785 dpll = DPLL_VGA_MODE_DIS;
3786
3787 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3788 dpll |= DPLLB_MODE_LVDS;
3789 else
3790 dpll |= DPLLB_MODE_DAC_SERIAL;
3791 if (is_sdvo) {
3792 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3793 if (pixel_multiplier > 1) {
3794 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3795 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3796 }
3797 dpll |= DPLL_DVO_HIGH_SPEED;
3798 }
3799 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3800 dpll |= DPLL_DVO_HIGH_SPEED;
3801
3802 /* compute bitmask from p1 value */
3803 if (IS_PINEVIEW(dev))
3804 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3805 else {
3806 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3807 if (IS_G4X(dev) && reduced_clock)
3808 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3809 }
3810 switch (clock->p2) {
3811 case 5:
3812 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3813 break;
3814 case 7:
3815 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3816 break;
3817 case 10:
3818 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3819 break;
3820 case 14:
3821 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3822 break;
3823 }
3824 if (INTEL_INFO(dev)->gen >= 4)
3825 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3826
3827 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3828 dpll |= PLL_REF_INPUT_TVCLKINBC;
3829 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3830 /* XXX: just matching BIOS for now */
3831 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3832 dpll |= 3;
3833 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3834 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3835 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3836 else
3837 dpll |= PLL_REF_INPUT_DREFCLK;
3838
3839 dpll |= DPLL_VCO_ENABLE;
3840 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3841 POSTING_READ(DPLL(pipe));
3842 udelay(150);
3843
3844 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3845 * This is an exception to the general rule that mode_set doesn't turn
3846 * things on.
3847 */
3848 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3849 intel_update_lvds(crtc, clock, adjusted_mode);
3850
3851 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
3852 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3853
3854 I915_WRITE(DPLL(pipe), dpll);
3855
3856 /* Wait for the clocks to stabilize. */
3857 POSTING_READ(DPLL(pipe));
3858 udelay(150);
3859
3860 if (INTEL_INFO(dev)->gen >= 4) {
3861 u32 temp = 0;
3862 if (is_sdvo) {
3863 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
3864 if (temp > 1)
3865 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
3866 else
3867 temp = 0;
3868 }
3869 I915_WRITE(DPLL_MD(pipe), temp);
3870 } else {
3871 /* The pixel multiplier can only be updated once the
3872 * DPLL is enabled and the clocks are stable.
3873 *
3874 * So write it again.
3875 */
3876 I915_WRITE(DPLL(pipe), dpll);
3877 }
3878}
3879
3880static void i8xx_update_pll(struct drm_crtc *crtc,
3881 struct drm_display_mode *adjusted_mode,
3882 intel_clock_t *clock,
3883 int num_connectors)
3884{
3885 struct drm_device *dev = crtc->dev;
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3888 int pipe = intel_crtc->pipe;
3889 u32 dpll;
3890
3891 dpll = DPLL_VGA_MODE_DIS;
3892
3893 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3894 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3895 } else {
3896 if (clock->p1 == 2)
3897 dpll |= PLL_P1_DIVIDE_BY_TWO;
3898 else
3899 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3900 if (clock->p2 == 4)
3901 dpll |= PLL_P2_DIVIDE_BY_4;
3902 }
3903
3904 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
3905 /* XXX: just matching BIOS for now */
3906 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3907 dpll |= 3;
3908 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3909 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
3910 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3911 else
3912 dpll |= PLL_REF_INPUT_DREFCLK;
3913
3914 dpll |= DPLL_VCO_ENABLE;
3915 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
3916 POSTING_READ(DPLL(pipe));
3917 udelay(150);
3918
3919 I915_WRITE(DPLL(pipe), dpll);
3920
3921 /* Wait for the clocks to stabilize. */
3922 POSTING_READ(DPLL(pipe));
3923 udelay(150);
3924
3925 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3926 * This is an exception to the general rule that mode_set doesn't turn
3927 * things on.
3928 */
3929 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
3930 intel_update_lvds(crtc, clock, adjusted_mode);
3931
3932 /* The pixel multiplier can only be updated once the
3933 * DPLL is enabled and the clocks are stable.
3934 *
3935 * So write it again.
3936 */
3937 I915_WRITE(DPLL(pipe), dpll);
3938}
3939
f564048e
EA		 3940static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
3941 struct drm_display_mode *mode,
3942 struct drm_display_mode *adjusted_mode,
3943 int x, int y,
3944 struct drm_framebuffer *old_fb)
79e53945
JB		 3945{
3946 struct drm_device *dev = crtc->dev;
3947 struct drm_i915_private *dev_priv = dev->dev_private;
3948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3949 int pipe = intel_crtc->pipe;
80824003 3950 int plane = intel_crtc->plane;
c751ce4f 3951 int refclk, num_connectors = 0;
652c393a 3952 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 3953 u32 dspcntr, pipeconf, vsyncshift;
3954 bool ok, has_reduced_clock = false, is_sdvo = false;
3955 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 3956 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 3957 struct intel_encoder *encoder;
d4906093 3958 const intel_limit_t *limit;
5c3b82e2 3959 int ret;
79e53945 3960
5eddb70b
CW		 3961 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3962 if (encoder->base.crtc != crtc)
79e53945
JB		 3963 continue;
3964
5eddb70b 3965 switch (encoder->type) {
79e53945
JB		 3966 case INTEL_OUTPUT_LVDS:
3967 is_lvds = true;
3968 break;
3969 case INTEL_OUTPUT_SDVO:
7d57382e 3970 case INTEL_OUTPUT_HDMI:
79e53945 3971 is_sdvo = true;
5eddb70b 3972 if (encoder->needs_tv_clock)
e2f0ba97 3973 is_tv = true;
79e53945 3974 break;
79e53945
JB		 3975 case INTEL_OUTPUT_TVOUT:
3976 is_tv = true;
3977 break;
a4fc5ed6
KP		 3978 case INTEL_OUTPUT_DISPLAYPORT:
3979 is_dp = true;
3980 break;
79e53945 3981 }
43565a06 3982
c751ce4f 3983 num_connectors++;
79e53945
JB		 3984 }
3985
c65d77d8 3986 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 3987
d4906093
ML		 3988 /*
3989 * Returns a set of divisors for the desired target clock with the given
3990 * refclk, or FALSE. The returned values represent the clock equation:
3991 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3992 */
1b894b59 3993 limit = intel_limit(crtc, refclk);
cec2f356
SP		 3994 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
3995 &clock);
79e53945
JB		 3996 if (!ok) {
3997 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 3998 return -EINVAL;
79e53945
JB		 3999 }
4000
cda4b7d3 4001 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4002 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4003
ddc9003c 4004 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4005 /*
4006 * Ensure we match the reduced clock's P to the target clock.
4007 * If the clocks don't match, we can't switch the display clock
4008 * by using the FP0/FP1. In such case we will disable the LVDS
4009 * downclock feature.
4010 */
ddc9003c 4011 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4012 dev_priv->lvds_downclock,
4013 refclk,
cec2f356 4014 &clock,
5eddb70b 4015 &reduced_clock);
7026d4ac
ZW		 4016 }
4017
c65d77d8
JB		 4018 if (is_sdvo && is_tv)
4019 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4020
a7516a05
JB		 4021 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4022 &reduced_clock : NULL);
79e53945 4023
eb1cbe48
DV		 4024 if (IS_GEN2(dev))
4025 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
79e53945 4026 else
eb1cbe48
DV		 4027 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4028 has_reduced_clock ? &reduced_clock : NULL,
4029 num_connectors);
79e53945
JB		 4030
4031 /* setup pipeconf */
5eddb70b 4032 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4033
4034 /* Set up the display plane register */
4035 dspcntr = DISPPLANE_GAMMA_ENABLE;
4036
929c77fb
EA		 4037 if (pipe == 0)
4038 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4039 else
4040 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4041
a6c45cf0 4042 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4043 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4044 * core speed.
4045 *
4046 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4047 * pipe == 0 check?
4048 */
e70236a8
JB		 4049 if (mode->clock >
4050 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4051 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4052 else
5eddb70b 4053 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4054 }
4055
3b5c78a3
AJ		 4056 /* default to 8bpc */
4057 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4058 if (is_dp) {
4059 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4060 pipeconf |= PIPECONF_BPP_6 |
4061 PIPECONF_DITHER_EN |
4062 PIPECONF_DITHER_TYPE_SP;
4063 }
4064 }
4065
28c97730 4066 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4067 drm_mode_debug_printmodeline(mode);
4068
a7516a05
JB		 4069 if (HAS_PIPE_CXSR(dev)) {
4070 if (intel_crtc->lowfreq_avail) {
28c97730 4071 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4072 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4073 } else {
28c97730 4074 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4075 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4076 }
4077 }
4078
617cf884 4079 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4080 if (!IS_GEN2(dev) &&
4081 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4082 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4083 /* the chip adds 2 halflines automatically */
734b4157 4084 adjusted_mode->crtc_vtotal -= 1;
734b4157 4085 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4086 vsyncshift = adjusted_mode->crtc_hsync_start
4087 - adjusted_mode->crtc_htotal/2;
4088 } else {
617cf884 4089 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4090 vsyncshift = 0;
4091 }
4092
4093 if (!IS_GEN3(dev))
4094 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4095
5eddb70b
CW		 4096 I915_WRITE(HTOTAL(pipe),
4097 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4098 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4099 I915_WRITE(HBLANK(pipe),
4100 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4101 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4102 I915_WRITE(HSYNC(pipe),
4103 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4104 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4105
4106 I915_WRITE(VTOTAL(pipe),
4107 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4108 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4109 I915_WRITE(VBLANK(pipe),
4110 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4111 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4112 I915_WRITE(VSYNC(pipe),
4113 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4114 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4115
4116 /* pipesrc and dspsize control the size that is scaled from,
4117 * which should always be the user's requested size.
79e53945 4118 */
929c77fb
EA		 4119 I915_WRITE(DSPSIZE(plane),
4120 ((mode->vdisplay - 1) << 16) |
4121 (mode->hdisplay - 1));
4122 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4123 I915_WRITE(PIPESRC(pipe),
4124 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4125
f564048e
EA		 4126 I915_WRITE(PIPECONF(pipe), pipeconf);
4127 POSTING_READ(PIPECONF(pipe));
929c77fb 4128 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4129
4130 intel_wait_for_vblank(dev, pipe);
4131
f564048e
EA		 4132 I915_WRITE(DSPCNTR(plane), dspcntr);
4133 POSTING_READ(DSPCNTR(plane));
4134
4135 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4136
4137 intel_update_watermarks(dev);
4138
f564048e
EA		 4139 return ret;
4140}
4141
9fb526db
KP		 4142/*
4143 * Initialize reference clocks when the driver loads
4144 */
4145void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4146{
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4149 struct intel_encoder *encoder;
13d83a67
JB		 4150 u32 temp;
4151 bool has_lvds = false;
199e5d79
KP		 4152 bool has_cpu_edp = false;
4153 bool has_pch_edp = false;
4154 bool has_panel = false;
99eb6a01
KP		 4155 bool has_ck505 = false;
4156 bool can_ssc = false;
13d83a67
JB		 4157
4158 /* We need to take the global config into account */
199e5d79
KP		 4159 list_for_each_entry(encoder, &mode_config->encoder_list,
4160 base.head) {
4161 switch (encoder->type) {
4162 case INTEL_OUTPUT_LVDS:
4163 has_panel = true;
4164 has_lvds = true;
4165 break;
4166 case INTEL_OUTPUT_EDP:
4167 has_panel = true;
4168 if (intel_encoder_is_pch_edp(&encoder->base))
4169 has_pch_edp = true;
4170 else
4171 has_cpu_edp = true;
4172 break;
13d83a67
JB		 4173 }
4174 }
4175
99eb6a01
KP		 4176 if (HAS_PCH_IBX(dev)) {
4177 has_ck505 = dev_priv->display_clock_mode;
4178 can_ssc = has_ck505;
4179 } else {
4180 has_ck505 = false;
4181 can_ssc = true;
4182 }
4183
4184 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4185 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4186 has_ck505);
13d83a67
JB		 4187
4188 /* Ironlake: try to setup display ref clock before DPLL
4189 * enabling. This is only under driver's control after
4190 * PCH B stepping, previous chipset stepping should be
4191 * ignoring this setting.
4192 */
4193 temp = I915_READ(PCH_DREF_CONTROL);
4194 /* Always enable nonspread source */
4195 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4196
99eb6a01
KP		 4197 if (has_ck505)
4198 temp |= DREF_NONSPREAD_CK505_ENABLE;
4199 else
4200 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4201
199e5d79
KP		 4202 if (has_panel) {
4203 temp &= ~DREF_SSC_SOURCE_MASK;
4204 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4205
199e5d79 4206 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4207 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4208 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4209 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4210 } else
4211 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4212
4213 /* Get SSC going before enabling the outputs */
4214 I915_WRITE(PCH_DREF_CONTROL, temp);
4215 POSTING_READ(PCH_DREF_CONTROL);
4216 udelay(200);
4217
13d83a67
JB		 4218 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4219
4220 /* Enable CPU source on CPU attached eDP */
199e5d79 4221 if (has_cpu_edp) {
99eb6a01 4222 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4223 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4224 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4225 }
13d83a67
JB		 4226 else
4227 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4228 } else
4229 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4230
4231 I915_WRITE(PCH_DREF_CONTROL, temp);
4232 POSTING_READ(PCH_DREF_CONTROL);
4233 udelay(200);
4234 } else {
4235 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4236
4237 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4238
4239 /* Turn off CPU output */
4240 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4241
4242 I915_WRITE(PCH_DREF_CONTROL, temp);
4243 POSTING_READ(PCH_DREF_CONTROL);
4244 udelay(200);
4245
4246 /* Turn off the SSC source */
4247 temp &= ~DREF_SSC_SOURCE_MASK;
4248 temp |= DREF_SSC_SOURCE_DISABLE;
4249
4250 /* Turn off SSC1 */
4251 temp &= ~ DREF_SSC1_ENABLE;
4252
13d83a67
JB		 4253 I915_WRITE(PCH_DREF_CONTROL, temp);
4254 POSTING_READ(PCH_DREF_CONTROL);
4255 udelay(200);
4256 }
4257}
4258
d9d444cb
JB		 4259static int ironlake_get_refclk(struct drm_crtc *crtc)
4260{
4261 struct drm_device *dev = crtc->dev;
4262 struct drm_i915_private *dev_priv = dev->dev_private;
4263 struct intel_encoder *encoder;
4264 struct drm_mode_config *mode_config = &dev->mode_config;
4265 struct intel_encoder *edp_encoder = NULL;
4266 int num_connectors = 0;
4267 bool is_lvds = false;
4268
4269 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4270 if (encoder->base.crtc != crtc)
4271 continue;
4272
4273 switch (encoder->type) {
4274 case INTEL_OUTPUT_LVDS:
4275 is_lvds = true;
4276 break;
4277 case INTEL_OUTPUT_EDP:
4278 edp_encoder = encoder;
4279 break;
4280 }
4281 num_connectors++;
4282 }
4283
4284 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4285 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4286 dev_priv->lvds_ssc_freq);
4287 return dev_priv->lvds_ssc_freq * 1000;
4288 }
4289
4290 return 120000;
4291}
4292
f564048e
EA		 4293static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4294 struct drm_display_mode *mode,
4295 struct drm_display_mode *adjusted_mode,
4296 int x, int y,
4297 struct drm_framebuffer *old_fb)
79e53945
JB		 4298{
4299 struct drm_device *dev = crtc->dev;
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4302 int pipe = intel_crtc->pipe;
80824003 4303 int plane = intel_crtc->plane;
c751ce4f 4304 int refclk, num_connectors = 0;
652c393a 4305 intel_clock_t clock, reduced_clock;
5eddb70b 4306 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4307 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4308 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4309 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4310 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4311 const intel_limit_t *limit;
5c3b82e2 4312 int ret;
2c07245f 4313 struct fdi_m_n m_n = {0};
fae14981 4314 u32 temp;
5a354204
JB		 4315 int target_clock, pixel_multiplier, lane, link_bw, factor;
4316 unsigned int pipe_bpp;
4317 bool dither;
e3aef172 4318 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4319
5eddb70b
CW		 4320 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4321 if (encoder->base.crtc != crtc)
79e53945
JB		 4322 continue;
4323
5eddb70b 4324 switch (encoder->type) {
79e53945
JB		 4325 case INTEL_OUTPUT_LVDS:
4326 is_lvds = true;
4327 break;
4328 case INTEL_OUTPUT_SDVO:
7d57382e 4329 case INTEL_OUTPUT_HDMI:
79e53945 4330 is_sdvo = true;
5eddb70b 4331 if (encoder->needs_tv_clock)
e2f0ba97 4332 is_tv = true;
79e53945 4333 break;
79e53945
JB		 4334 case INTEL_OUTPUT_TVOUT:
4335 is_tv = true;
4336 break;
4337 case INTEL_OUTPUT_ANALOG:
4338 is_crt = true;
4339 break;
a4fc5ed6
KP		 4340 case INTEL_OUTPUT_DISPLAYPORT:
4341 is_dp = true;
4342 break;
32f9d658 4343 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4344 is_dp = true;
4345 if (intel_encoder_is_pch_edp(&encoder->base))
4346 is_pch_edp = true;
4347 else
4348 is_cpu_edp = true;
4349 edp_encoder = encoder;
32f9d658 4350 break;
79e53945 4351 }
43565a06 4352
c751ce4f 4353 num_connectors++;
79e53945
JB		 4354 }
4355
d9d444cb 4356 refclk = ironlake_get_refclk(crtc);
79e53945 4357
d4906093
ML		 4358 /*
4359 * Returns a set of divisors for the desired target clock with the given
4360 * refclk, or FALSE. The returned values represent the clock equation:
4361 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4362 */
1b894b59 4363 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4364 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4365 &clock);
79e53945
JB		 4366 if (!ok) {
4367 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4368 return -EINVAL;
79e53945
JB		 4369 }
4370
cda4b7d3 4371 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4372 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4373
ddc9003c 4374 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4375 /*
4376 * Ensure we match the reduced clock's P to the target clock.
4377 * If the clocks don't match, we can't switch the display clock
4378 * by using the FP0/FP1. In such case we will disable the LVDS
4379 * downclock feature.
4380 */
ddc9003c 4381 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4382 dev_priv->lvds_downclock,
4383 refclk,
cec2f356 4384 &clock,
5eddb70b 4385 &reduced_clock);
652c393a 4386 }
7026d4ac
ZW		 4387 /* SDVO TV has fixed PLL values depend on its clock range,
4388 this mirrors vbios setting. */
4389 if (is_sdvo && is_tv) {
4390 if (adjusted_mode->clock >= 100000
5eddb70b 4391 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4392 clock.p1 = 2;
4393 clock.p2 = 10;
4394 clock.n = 3;
4395 clock.m1 = 16;
4396 clock.m2 = 8;
4397 } else if (adjusted_mode->clock >= 140500
5eddb70b 4398 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4399 clock.p1 = 1;
4400 clock.p2 = 10;
4401 clock.n = 6;
4402 clock.m1 = 12;
4403 clock.m2 = 8;
4404 }
4405 }
4406
2c07245f 4407 /* FDI link */
8febb297
EA		 4408 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4409 lane = 0;
4410 /* CPU eDP doesn't require FDI link, so just set DP M/N
4411 according to current link config */
e3aef172 4412 if (is_cpu_edp) {
8febb297 4413 target_clock = mode->clock;
e3aef172 4414 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297
EA		 4415 } else {
4416 /* [e]DP over FDI requires target mode clock
4417 instead of link clock */
e3aef172 4418 if (is_dp)
5eb08b69 4419 target_clock = mode->clock;
8febb297
EA		 4420 else
4421 target_clock = adjusted_mode->clock;
4422
4423 /* FDI is a binary signal running at ~2.7GHz, encoding
4424 * each output octet as 10 bits. The actual frequency
4425 * is stored as a divider into a 100MHz clock, and the
4426 * mode pixel clock is stored in units of 1KHz.
4427 * Hence the bw of each lane in terms of the mode signal
4428 * is:
4429 */
4430 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4431 }
58a27471 4432
8febb297
EA		 4433 /* determine panel color depth */
4434 temp = I915_READ(PIPECONF(pipe));
4435 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4436 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4437 switch (pipe_bpp) {
4438 case 18:
4439 temp |= PIPE_6BPC;
8febb297 4440 break;
5a354204
JB		 4441 case 24:
4442 temp |= PIPE_8BPC;
8febb297 4443 break;
5a354204
JB		 4444 case 30:
4445 temp |= PIPE_10BPC;
8febb297 4446 break;
5a354204
JB		 4447 case 36:
4448 temp |= PIPE_12BPC;
8febb297
EA		 4449 break;
4450 default:
62ac41a6
JB		 4451 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4452 pipe_bpp);
5a354204
JB		 4453 temp |= PIPE_8BPC;
4454 pipe_bpp = 24;
4455 break;
8febb297 4456 }
77ffb597 4457
5a354204
JB		 4458 intel_crtc->bpp = pipe_bpp;
4459 I915_WRITE(PIPECONF(pipe), temp);
4460
8febb297
EA		 4461 if (!lane) {
4462 /*
4463 * Account for spread spectrum to avoid
4464 * oversubscribing the link. Max center spread
4465 * is 2.5%; use 5% for safety's sake.
4466 */
5a354204 4467 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4468 lane = bps / (link_bw * 8) + 1;
5eb08b69 4469 }
2c07245f 4470
8febb297
EA		 4471 intel_crtc->fdi_lanes = lane;
4472
4473 if (pixel_multiplier > 1)
4474 link_bw *= pixel_multiplier;
5a354204
JB		 4475 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4476 &m_n);
8febb297 4477
a07d6787
EA		 4478 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4479 if (has_reduced_clock)
4480 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4481 reduced_clock.m2;
79e53945 4482
c1858123 4483 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4484 factor = 21;
4485 if (is_lvds) {
4486 if ((intel_panel_use_ssc(dev_priv) &&
4487 dev_priv->lvds_ssc_freq == 100) ||
4488 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4489 factor = 25;
4490 } else if (is_sdvo && is_tv)
4491 factor = 20;
c1858123 4492
cb0e0931 4493 if (clock.m < factor * clock.n)
8febb297 4494 fp |= FP_CB_TUNE;
2c07245f 4495
5eddb70b 4496 dpll = 0;
2c07245f 4497
a07d6787
EA		 4498 if (is_lvds)
4499 dpll |= DPLLB_MODE_LVDS;
4500 else
4501 dpll |= DPLLB_MODE_DAC_SERIAL;
4502 if (is_sdvo) {
4503 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4504 if (pixel_multiplier > 1) {
4505 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4506 }
a07d6787
EA		 4507 dpll |= DPLL_DVO_HIGH_SPEED;
4508 }
e3aef172 4509 if (is_dp && !is_cpu_edp)
a07d6787 4510 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4511
a07d6787
EA		 4512 /* compute bitmask from p1 value */
4513 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4514 /* also FPA1 */
4515 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4516
4517 switch (clock.p2) {
4518 case 5:
4519 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4520 break;
4521 case 7:
4522 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4523 break;
4524 case 10:
4525 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4526 break;
4527 case 14:
4528 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4529 break;
79e53945
JB		 4530 }
4531
43565a06
KH		 4532 if (is_sdvo && is_tv)
4533 dpll |= PLL_REF_INPUT_TVCLKINBC;
4534 else if (is_tv)
79e53945 4535 /* XXX: just matching BIOS for now */
43565a06 4536 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4537 dpll |= 3;
a7615030 4538 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4539 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4540 else
4541 dpll |= PLL_REF_INPUT_DREFCLK;
4542
4543 /* setup pipeconf */
5eddb70b 4544 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4545
4546 /* Set up the display plane register */
4547 dspcntr = DISPPLANE_GAMMA_ENABLE;
4548
f7cb34d4 4549 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4550 drm_mode_debug_printmodeline(mode);
4551
9d82aa17
ED		 4552 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4553 * pre-Haswell/LPT generation */
4554 if (HAS_PCH_LPT(dev)) {
4555 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4556 pipe);
4557 } else if (!is_cpu_edp) {
ee7b9f93 4558 struct intel_pch_pll *pll;
4b645f14 4559
ee7b9f93
JB		 4560 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4561 if (pll == NULL) {
4562 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4563 pipe);
4b645f14
JB		 4564 return -EINVAL;
4565 }
ee7b9f93
JB		 4566 } else
4567 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4568
4569 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4570 * This is an exception to the general rule that mode_set doesn't turn
4571 * things on.
4572 */
4573 if (is_lvds) {
fae14981 4574 temp = I915_READ(PCH_LVDS);
5eddb70b 4575 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4576 if (HAS_PCH_CPT(dev)) {
4577 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4578 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4579 } else {
4580 if (pipe == 1)
4581 temp |= LVDS_PIPEB_SELECT;
4582 else
4583 temp &= ~LVDS_PIPEB_SELECT;
4584 }
4b645f14 4585
a3e17eb8 4586 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4587 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4588 /* Set the B0-B3 data pairs corresponding to whether we're going to
4589 * set the DPLLs for dual-channel mode or not.
4590 */
4591 if (clock.p2 == 7)
5eddb70b 4592 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4593 else
5eddb70b 4594 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4595
4596 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4597 * appropriately here, but we need to look more thoroughly into how
4598 * panels behave in the two modes.
4599 */
284d5df5 4600 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4601 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4602 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4603 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4604 temp |= LVDS_VSYNC_POLARITY;
fae14981 4605 I915_WRITE(PCH_LVDS, temp);
79e53945 4606 }
434ed097 4607
8febb297
EA		 4608 pipeconf &= ~PIPECONF_DITHER_EN;
4609 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4610 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4611 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4612 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4613 }
e3aef172 4614 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4615 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4616 } else {
8db9d77b 4617 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4618 I915_WRITE(TRANSDATA_M1(pipe), 0);
4619 I915_WRITE(TRANSDATA_N1(pipe), 0);
4620 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4621 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4622 }
79e53945 4623
ee7b9f93
JB		 4624 if (intel_crtc->pch_pll) {
4625 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4626
32f9d658 4627 /* Wait for the clocks to stabilize. */
ee7b9f93 4628 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4629 udelay(150);
4630
8febb297
EA		 4631 /* The pixel multiplier can only be updated once the
4632 * DPLL is enabled and the clocks are stable.
4633 *
4634 * So write it again.
4635 */
ee7b9f93 4636 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4637 }
79e53945 4638
5eddb70b 4639 intel_crtc->lowfreq_avail = false;
ee7b9f93 4640 if (intel_crtc->pch_pll) {
4b645f14 4641 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4642 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14
JB		 4643 intel_crtc->lowfreq_avail = true;
4644 if (HAS_PIPE_CXSR(dev)) {
4645 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4646 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4647 }
4648 } else {
ee7b9f93 4649 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4b645f14
JB		 4650 if (HAS_PIPE_CXSR(dev)) {
4651 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4652 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4653 }
652c393a
JB		 4654 }
4655 }
4656
617cf884 4657 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4658 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4659 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4660 /* the chip adds 2 halflines automatically */
734b4157 4661 adjusted_mode->crtc_vtotal -= 1;
734b4157 4662 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4663 I915_WRITE(VSYNCSHIFT(pipe),
4664 adjusted_mode->crtc_hsync_start
4665 - adjusted_mode->crtc_htotal/2);
4666 } else {
617cf884 4667 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4668 I915_WRITE(VSYNCSHIFT(pipe), 0);
4669 }
734b4157 4670
5eddb70b
CW		 4671 I915_WRITE(HTOTAL(pipe),
4672 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4673 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4674 I915_WRITE(HBLANK(pipe),
4675 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4676 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4677 I915_WRITE(HSYNC(pipe),
4678 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4679 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4680
4681 I915_WRITE(VTOTAL(pipe),
4682 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4683 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4684 I915_WRITE(VBLANK(pipe),
4685 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4686 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4687 I915_WRITE(VSYNC(pipe),
4688 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4689 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4690
8febb297
EA		 4691 /* pipesrc controls the size that is scaled from, which should
4692 * always be the user's requested size.
79e53945 4693 */
5eddb70b
CW		 4694 I915_WRITE(PIPESRC(pipe),
4695 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4696
8febb297
EA		 4697 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4698 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4699 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4700 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4701
e3aef172 4702 if (is_cpu_edp)
8febb297 4703 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4704
5eddb70b
CW		 4705 I915_WRITE(PIPECONF(pipe), pipeconf);
4706 POSTING_READ(PIPECONF(pipe));
79e53945 4707
9d0498a2 4708 intel_wait_for_vblank(dev, pipe);
79e53945 4709
5eddb70b 4710 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4711 POSTING_READ(DSPCNTR(plane));
79e53945 4712
5c3b82e2 4713 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4714
4715 intel_update_watermarks(dev);
4716
1f8eeabf
ED		 4717 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4718
1f803ee5 4719 return ret;
79e53945
JB		 4720}
4721
f564048e
EA		 4722static int intel_crtc_mode_set(struct drm_crtc *crtc,
4723 struct drm_display_mode *mode,
4724 struct drm_display_mode *adjusted_mode,
4725 int x, int y,
4726 struct drm_framebuffer *old_fb)
4727{
4728 struct drm_device *dev = crtc->dev;
4729 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4731 int pipe = intel_crtc->pipe;
f564048e
EA		 4732 int ret;
4733
0b701d27 4734 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4735
f564048e
EA		 4736 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4737 x, y, old_fb);
79e53945 4738 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4739
d8e70a25
JB		 4740 if (ret)
4741 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4742 else
4743 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4744
1f803ee5 4745 return ret;
79e53945
JB		 4746}
4747
3a9627f4
WF		 4748static bool intel_eld_uptodate(struct drm_connector *connector,
4749 int reg_eldv, uint32_t bits_eldv,
4750 int reg_elda, uint32_t bits_elda,
4751 int reg_edid)
4752{
4753 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4754 uint8_t *eld = connector->eld;
4755 uint32_t i;
4756
4757 i = I915_READ(reg_eldv);
4758 i &= bits_eldv;
4759
4760 if (!eld[0])
4761 return !i;
4762
4763 if (!i)
4764 return false;
4765
4766 i = I915_READ(reg_elda);
4767 i &= ~bits_elda;
4768 I915_WRITE(reg_elda, i);
4769
4770 for (i = 0; i < eld[2]; i++)
4771 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
4772 return false;
4773
4774 return true;
4775}
4776
e0dac65e
WF		 4777static void g4x_write_eld(struct drm_connector *connector,
4778 struct drm_crtc *crtc)
4779{
4780 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4781 uint8_t *eld = connector->eld;
4782 uint32_t eldv;
4783 uint32_t len;
4784 uint32_t i;
4785
4786 i = I915_READ(G4X_AUD_VID_DID);
4787
4788 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
4789 eldv = G4X_ELDV_DEVCL_DEVBLC;
4790 else
4791 eldv = G4X_ELDV_DEVCTG;
4792
3a9627f4
WF		 4793 if (intel_eld_uptodate(connector,
4794 G4X_AUD_CNTL_ST, eldv,
4795 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
4796 G4X_HDMIW_HDMIEDID))
4797 return;
4798
e0dac65e
WF		 4799 i = I915_READ(G4X_AUD_CNTL_ST);
4800 i &= ~(eldv | G4X_ELD_ADDR);
4801 len = (i >> 9) & 0x1f; /* ELD buffer size */
4802 I915_WRITE(G4X_AUD_CNTL_ST, i);
4803
4804 if (!eld[0])
4805 return;
4806
4807 len = min_t(uint8_t, eld[2], len);
4808 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4809 for (i = 0; i < len; i++)
4810 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
4811
4812 i = I915_READ(G4X_AUD_CNTL_ST);
4813 i |= eldv;
4814 I915_WRITE(G4X_AUD_CNTL_ST, i);
4815}
4816
4817static void ironlake_write_eld(struct drm_connector *connector,
4818 struct drm_crtc *crtc)
4819{
4820 struct drm_i915_private *dev_priv = connector->dev->dev_private;
4821 uint8_t *eld = connector->eld;
4822 uint32_t eldv;
4823 uint32_t i;
4824 int len;
4825 int hdmiw_hdmiedid;
b6daa025 4826 int aud_config;
e0dac65e
WF		 4827 int aud_cntl_st;
4828 int aud_cntrl_st2;
4829
b3f33cbf 4830 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 4831 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 4832 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 4833 aud_cntl_st = IBX_AUD_CNTL_ST_A;
4834 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 4835 } else {
1202b4c6 4836 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 4837 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 4838 aud_cntl_st = CPT_AUD_CNTL_ST_A;
4839 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 4840 }
4841
4842 i = to_intel_crtc(crtc)->pipe;
4843 hdmiw_hdmiedid += i * 0x100;
4844 aud_cntl_st += i * 0x100;
b6daa025 4845 aud_config += i * 0x100;
e0dac65e
WF		 4846
4847 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
4848
4849 i = I915_READ(aud_cntl_st);
4850 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
4851 if (!i) {
4852 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
4853 /* operate blindly on all ports */
1202b4c6
WF		 4854 eldv = IBX_ELD_VALIDB;
4855 eldv |= IBX_ELD_VALIDB << 4;
4856 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 4857 } else {
4858 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 4859 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 4860 }
4861
3a9627f4
WF		 4862 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
4863 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
4864 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 4865 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
4866 } else
4867 I915_WRITE(aud_config, 0);
e0dac65e 4868
3a9627f4
WF		 4869 if (intel_eld_uptodate(connector,
4870 aud_cntrl_st2, eldv,
4871 aud_cntl_st, IBX_ELD_ADDRESS,
4872 hdmiw_hdmiedid))
4873 return;
4874
e0dac65e
WF		 4875 i = I915_READ(aud_cntrl_st2);
4876 i &= ~eldv;
4877 I915_WRITE(aud_cntrl_st2, i);
4878
4879 if (!eld[0])
4880 return;
4881
e0dac65e 4882 i = I915_READ(aud_cntl_st);
1202b4c6 4883 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 4884 I915_WRITE(aud_cntl_st, i);
4885
4886 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
4887 DRM_DEBUG_DRIVER("ELD size %d\n", len);
4888 for (i = 0; i < len; i++)
4889 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
4890
4891 i = I915_READ(aud_cntrl_st2);
4892 i |= eldv;
4893 I915_WRITE(aud_cntrl_st2, i);
4894}
4895
4896void intel_write_eld(struct drm_encoder *encoder,
4897 struct drm_display_mode *mode)
4898{
4899 struct drm_crtc *crtc = encoder->crtc;
4900 struct drm_connector *connector;
4901 struct drm_device *dev = encoder->dev;
4902 struct drm_i915_private *dev_priv = dev->dev_private;
4903
4904 connector = drm_select_eld(encoder, mode);
4905 if (!connector)
4906 return;
4907
4908 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
4909 connector->base.id,
4910 drm_get_connector_name(connector),
4911 connector->encoder->base.id,
4912 drm_get_encoder_name(connector->encoder));
4913
4914 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
4915
4916 if (dev_priv->display.write_eld)
4917 dev_priv->display.write_eld(connector, crtc);
4918}
4919
79e53945
JB		 4920/** Loads the palette/gamma unit for the CRTC with the prepared values */
4921void intel_crtc_load_lut(struct drm_crtc *crtc)
4922{
4923 struct drm_device *dev = crtc->dev;
4924 struct drm_i915_private *dev_priv = dev->dev_private;
4925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 4926 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 4927 int i;
4928
4929 /* The clocks have to be on to load the palette. */
aed3f09d 4930 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 4931 return;
4932
f2b115e6 4933 /* use legacy palette for Ironlake */
bad720ff 4934 if (HAS_PCH_SPLIT(dev))
9db4a9c7 4935 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 4936
79e53945
JB		 4937 for (i = 0; i < 256; i++) {
4938 I915_WRITE(palreg + 4 * i,
4939 (intel_crtc->lut_r[i] << 16) |
4940 (intel_crtc->lut_g[i] << 8) |
4941 intel_crtc->lut_b[i]);
4942 }
4943}
4944
560b85bb
CW		 4945static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4946{
4947 struct drm_device *dev = crtc->dev;
4948 struct drm_i915_private *dev_priv = dev->dev_private;
4949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4950 bool visible = base != 0;
4951 u32 cntl;
4952
4953 if (intel_crtc->cursor_visible == visible)
4954 return;
4955
9db4a9c7 4956 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 4957 if (visible) {
4958 /* On these chipsets we can only modify the base whilst
4959 * the cursor is disabled.
4960 */
9db4a9c7 4961 I915_WRITE(_CURABASE, base);
560b85bb
CW		 4962
4963 cntl &= ~(CURSOR_FORMAT_MASK);
4964 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4965 cntl |= CURSOR_ENABLE |
4966 CURSOR_GAMMA_ENABLE |
4967 CURSOR_FORMAT_ARGB;
4968 } else
4969 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 4970 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 4971
4972 intel_crtc->cursor_visible = visible;
4973}
4974
4975static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4976{
4977 struct drm_device *dev = crtc->dev;
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980 int pipe = intel_crtc->pipe;
4981 bool visible = base != 0;
4982
4983 if (intel_crtc->cursor_visible != visible) {
548f245b 4984 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 4985 if (base) {
4986 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4987 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4988 cntl |= pipe << 28; /* Connect to correct pipe */
4989 } else {
4990 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4991 cntl |= CURSOR_MODE_DISABLE;
4992 }
9db4a9c7 4993 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 4994
4995 intel_crtc->cursor_visible = visible;
4996 }
4997 /* and commit changes on next vblank */
9db4a9c7 4998 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 4999}
5000
65a21cd6
JB		 5001static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5002{
5003 struct drm_device *dev = crtc->dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5006 int pipe = intel_crtc->pipe;
5007 bool visible = base != 0;
5008
5009 if (intel_crtc->cursor_visible != visible) {
5010 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5011 if (base) {
5012 cntl &= ~CURSOR_MODE;
5013 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5014 } else {
5015 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5016 cntl |= CURSOR_MODE_DISABLE;
5017 }
5018 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5019
5020 intel_crtc->cursor_visible = visible;
5021 }
5022 /* and commit changes on next vblank */
5023 I915_WRITE(CURBASE_IVB(pipe), base);
5024}
5025
cda4b7d3 5026/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5027static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5028 bool on)
cda4b7d3
CW		 5029{
5030 struct drm_device *dev = crtc->dev;
5031 struct drm_i915_private *dev_priv = dev->dev_private;
5032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5033 int pipe = intel_crtc->pipe;
5034 int x = intel_crtc->cursor_x;
5035 int y = intel_crtc->cursor_y;
560b85bb 5036 u32 base, pos;
cda4b7d3
CW		 5037 bool visible;
5038
5039 pos = 0;
5040
6b383a7f 5041 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5042 base = intel_crtc->cursor_addr;
5043 if (x > (int) crtc->fb->width)
5044 base = 0;
5045
5046 if (y > (int) crtc->fb->height)
5047 base = 0;
5048 } else
5049 base = 0;
5050
5051 if (x < 0) {
5052 if (x + intel_crtc->cursor_width < 0)
5053 base = 0;
5054
5055 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5056 x = -x;
5057 }
5058 pos |= x << CURSOR_X_SHIFT;
5059
5060 if (y < 0) {
5061 if (y + intel_crtc->cursor_height < 0)
5062 base = 0;
5063
5064 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5065 y = -y;
5066 }
5067 pos |= y << CURSOR_Y_SHIFT;
5068
5069 visible = base != 0;
560b85bb 5070 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5071 return;
5072
0cd83aa9 5073 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5074 I915_WRITE(CURPOS_IVB(pipe), pos);
5075 ivb_update_cursor(crtc, base);
5076 } else {
5077 I915_WRITE(CURPOS(pipe), pos);
5078 if (IS_845G(dev) || IS_I865G(dev))
5079 i845_update_cursor(crtc, base);
5080 else
5081 i9xx_update_cursor(crtc, base);
5082 }
cda4b7d3
CW		 5083}
5084
79e53945 5085static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5086 struct drm_file *file,
79e53945
JB		 5087 uint32_t handle,
5088 uint32_t width, uint32_t height)
5089{
5090 struct drm_device *dev = crtc->dev;
5091 struct drm_i915_private *dev_priv = dev->dev_private;
5092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5093 struct drm_i915_gem_object *obj;
cda4b7d3 5094 uint32_t addr;
3f8bc370 5095 int ret;
79e53945 5096
28c97730 5097 DRM_DEBUG_KMS("\n");
79e53945
JB		 5098
5099 /* if we want to turn off the cursor ignore width and height */
5100 if (!handle) {
28c97730 5101 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5102 addr = 0;
05394f39 5103 obj = NULL;
5004417d 5104 mutex_lock(&dev->struct_mutex);
3f8bc370 5105 goto finish;
79e53945
JB		 5106 }
5107
5108 /* Currently we only support 64x64 cursors */
5109 if (width != 64 || height != 64) {
5110 DRM_ERROR("we currently only support 64x64 cursors\n");
5111 return -EINVAL;
5112 }
5113
05394f39 5114 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5115 if (&obj->base == NULL)
79e53945
JB		 5116 return -ENOENT;
5117
05394f39 5118 if (obj->base.size < width * height * 4) {
79e53945 5119 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5120 ret = -ENOMEM;
5121 goto fail;
79e53945
JB		 5122 }
5123
71acb5eb 5124 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5125 mutex_lock(&dev->struct_mutex);
b295d1b6 5126 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5127 if (obj->tiling_mode) {
5128 DRM_ERROR("cursor cannot be tiled\n");
5129 ret = -EINVAL;
5130 goto fail_locked;
5131 }
5132
2da3b9b9 5133 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5134 if (ret) {
5135 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5136 goto fail_locked;
e7b526bb
CW		 5137 }
5138
d9e86c0e
CW		 5139 ret = i915_gem_object_put_fence(obj);
5140 if (ret) {
2da3b9b9 5141 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5142 goto fail_unpin;
5143 }
5144
05394f39 5145 addr = obj->gtt_offset;
71acb5eb 5146 } else {
6eeefaf3 5147 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5148 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5149 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5150 align);
71acb5eb
DA		 5151 if (ret) {
5152 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5153 goto fail_locked;
71acb5eb 5154 }
05394f39 5155 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5156 }
5157
a6c45cf0 5158 if (IS_GEN2(dev))
14b60391
JB		 5159 I915_WRITE(CURSIZE, (height << 12) | width);
5160
3f8bc370 5161 finish:
3f8bc370 5162 if (intel_crtc->cursor_bo) {
b295d1b6 5163 if (dev_priv->info->cursor_needs_physical) {
05394f39 5164 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5165 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5166 } else
5167 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5168 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5169 }
80824003 5170
7f9872e0 5171 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5172
5173 intel_crtc->cursor_addr = addr;
05394f39 5174 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5175 intel_crtc->cursor_width = width;
5176 intel_crtc->cursor_height = height;
5177
6b383a7f 5178 intel_crtc_update_cursor(crtc, true);
3f8bc370 5179
79e53945 5180 return 0;
e7b526bb 5181fail_unpin:
05394f39 5182 i915_gem_object_unpin(obj);
7f9872e0 5183fail_locked:
34b8686e 5184 mutex_unlock(&dev->struct_mutex);
bc9025bd 5185fail:
05394f39 5186 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5187 return ret;
79e53945
JB		 5188}
5189
5190static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5191{
79e53945 5192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5193
cda4b7d3
CW		 5194 intel_crtc->cursor_x = x;
5195 intel_crtc->cursor_y = y;
652c393a 5196
6b383a7f 5197 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5198
5199 return 0;
5200}
5201
5202/** Sets the color ramps on behalf of RandR */
5203void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5204 u16 blue, int regno)
5205{
5206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5207
5208 intel_crtc->lut_r[regno] = red >> 8;
5209 intel_crtc->lut_g[regno] = green >> 8;
5210 intel_crtc->lut_b[regno] = blue >> 8;
5211}
5212
b8c00ac5
DA		 5213void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5214 u16 *blue, int regno)
5215{
5216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5217
5218 *red = intel_crtc->lut_r[regno] << 8;
5219 *green = intel_crtc->lut_g[regno] << 8;
5220 *blue = intel_crtc->lut_b[regno] << 8;
5221}
5222
79e53945 5223static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5224 u16 *blue, uint32_t start, uint32_t size)
79e53945 5225{
7203425a 5226 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5228
7203425a 5229 for (i = start; i < end; i++) {
79e53945
JB		 5230 intel_crtc->lut_r[i] = red[i] >> 8;
5231 intel_crtc->lut_g[i] = green[i] >> 8;
5232 intel_crtc->lut_b[i] = blue[i] >> 8;
5233 }
5234
5235 intel_crtc_load_lut(crtc);
5236}
5237
5238/**
5239 * Get a pipe with a simple mode set on it for doing load-based monitor
5240 * detection.
5241 *
5242 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5243 * its requirements. The pipe will be connected to no other encoders.
79e53945 5244 *
c751ce4f 5245 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5246 * configured for it. In the future, it could choose to temporarily disable
5247 * some outputs to free up a pipe for its use.
5248 *
5249 * \return crtc, or NULL if no pipes are available.
5250 */
5251
5252/* VESA 640x480x72Hz mode to set on the pipe */
5253static struct drm_display_mode load_detect_mode = {
5254 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5255 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5256};
5257
d2dff872
CW		 5258static struct drm_framebuffer *
5259intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5260 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5261 struct drm_i915_gem_object *obj)
5262{
5263 struct intel_framebuffer *intel_fb;
5264 int ret;
5265
5266 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5267 if (!intel_fb) {
5268 drm_gem_object_unreference_unlocked(&obj->base);
5269 return ERR_PTR(-ENOMEM);
5270 }
5271
5272 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5273 if (ret) {
5274 drm_gem_object_unreference_unlocked(&obj->base);
5275 kfree(intel_fb);
5276 return ERR_PTR(ret);
5277 }
5278
5279 return &intel_fb->base;
5280}
5281
5282static u32
5283intel_framebuffer_pitch_for_width(int width, int bpp)
5284{
5285 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5286 return ALIGN(pitch, 64);
5287}
5288
5289static u32
5290intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5291{
5292 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5293 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5294}
5295
5296static struct drm_framebuffer *
5297intel_framebuffer_create_for_mode(struct drm_device *dev,
5298 struct drm_display_mode *mode,
5299 int depth, int bpp)
5300{
5301 struct drm_i915_gem_object *obj;
308e5bcb 5302 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5303
5304 obj = i915_gem_alloc_object(dev,
5305 intel_framebuffer_size_for_mode(mode, bpp));
5306 if (obj == NULL)
5307 return ERR_PTR(-ENOMEM);
5308
5309 mode_cmd.width = mode->hdisplay;
5310 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5311 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5312 bpp);
5ca0c34a 5313 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5314
5315 return intel_framebuffer_create(dev, &mode_cmd, obj);
5316}
5317
5318static struct drm_framebuffer *
5319mode_fits_in_fbdev(struct drm_device *dev,
5320 struct drm_display_mode *mode)
5321{
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 struct drm_i915_gem_object *obj;
5324 struct drm_framebuffer *fb;
5325
5326 if (dev_priv->fbdev == NULL)
5327 return NULL;
5328
5329 obj = dev_priv->fbdev->ifb.obj;
5330 if (obj == NULL)
5331 return NULL;
5332
5333 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5334 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5335 fb->bits_per_pixel))
d2dff872
CW		 5336 return NULL;
5337
01f2c773 5338 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5339 return NULL;
5340
5341 return fb;
5342}
5343
7173188d
CW		 5344bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5345 struct drm_connector *connector,
5346 struct drm_display_mode *mode,
8261b191 5347 struct intel_load_detect_pipe *old)
79e53945
JB		 5348{
5349 struct intel_crtc *intel_crtc;
5350 struct drm_crtc *possible_crtc;
4ef69c7a 5351 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5352 struct drm_crtc *crtc = NULL;
5353 struct drm_device *dev = encoder->dev;
d2dff872 5354 struct drm_framebuffer *old_fb;
79e53945
JB		 5355 int i = -1;
5356
d2dff872
CW		 5357 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5358 connector->base.id, drm_get_connector_name(connector),
5359 encoder->base.id, drm_get_encoder_name(encoder));
5360
79e53945
JB		 5361 /*
5362 * Algorithm gets a little messy:
7a5e4805 5363 *
79e53945
JB		 5364 * - if the connector already has an assigned crtc, use it (but make
5365 * sure it's on first)
7a5e4805 5366 *
79e53945
JB		 5367 * - try to find the first unused crtc that can drive this connector,
5368 * and use that if we find one
79e53945
JB		 5369 */
5370
5371 /* See if we already have a CRTC for this connector */
5372 if (encoder->crtc) {
5373 crtc = encoder->crtc;
8261b191 5374
79e53945 5375 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5376 old->dpms_mode = intel_crtc->dpms_mode;
5377 old->load_detect_temp = false;
5378
5379 /* Make sure the crtc and connector are running */
79e53945 5380 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5381 struct drm_encoder_helper_funcs *encoder_funcs;
5382 struct drm_crtc_helper_funcs *crtc_funcs;
5383
79e53945
JB		 5384 crtc_funcs = crtc->helper_private;
5385 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5386
5387 encoder_funcs = encoder->helper_private;
79e53945
JB		 5388 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5389 }
8261b191 5390
7173188d 5391 return true;
79e53945
JB		 5392 }
5393
5394 /* Find an unused one (if possible) */
5395 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5396 i++;
5397 if (!(encoder->possible_crtcs & (1 << i)))
5398 continue;
5399 if (!possible_crtc->enabled) {
5400 crtc = possible_crtc;
5401 break;
5402 }
79e53945
JB		 5403 }
5404
5405 /*
5406 * If we didn't find an unused CRTC, don't use any.
5407 */
5408 if (!crtc) {
7173188d
CW		 5409 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5410 return false;
79e53945
JB		 5411 }
5412
5413 encoder->crtc = crtc;
c1c43977 5414 connector->encoder = encoder;
79e53945
JB		 5415
5416 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5417 old->dpms_mode = intel_crtc->dpms_mode;
5418 old->load_detect_temp = true;
d2dff872 5419 old->release_fb = NULL;
79e53945 5420
6492711d
CW		 5421 if (!mode)
5422 mode = &load_detect_mode;
79e53945 5423
d2dff872
CW		 5424 old_fb = crtc->fb;
5425
5426 /* We need a framebuffer large enough to accommodate all accesses
5427 * that the plane may generate whilst we perform load detection.
5428 * We can not rely on the fbcon either being present (we get called
5429 * during its initialisation to detect all boot displays, or it may
5430 * not even exist) or that it is large enough to satisfy the
5431 * requested mode.
5432 */
5433 crtc->fb = mode_fits_in_fbdev(dev, mode);
5434 if (crtc->fb == NULL) {
5435 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5436 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5437 old->release_fb = crtc->fb;
5438 } else
5439 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5440 if (IS_ERR(crtc->fb)) {
5441 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5442 crtc->fb = old_fb;
5443 return false;
79e53945 5444 }
79e53945 5445
d2dff872 5446 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5447 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5448 if (old->release_fb)
5449 old->release_fb->funcs->destroy(old->release_fb);
5450 crtc->fb = old_fb;
6492711d 5451 return false;
79e53945 5452 }
7173188d 5453
79e53945 5454 /* let the connector get through one full cycle before testing */
9d0498a2 5455 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5456
7173188d 5457 return true;
79e53945
JB		 5458}
5459
c1c43977 5460void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5461 struct drm_connector *connector,
5462 struct intel_load_detect_pipe *old)
79e53945 5463{
4ef69c7a 5464 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5465 struct drm_device *dev = encoder->dev;
5466 struct drm_crtc *crtc = encoder->crtc;
5467 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5468 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5469
d2dff872
CW		 5470 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5471 connector->base.id, drm_get_connector_name(connector),
5472 encoder->base.id, drm_get_encoder_name(encoder));
5473
8261b191 5474 if (old->load_detect_temp) {
c1c43977 5475 connector->encoder = NULL;
79e53945 5476 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5477
5478 if (old->release_fb)
5479 old->release_fb->funcs->destroy(old->release_fb);
5480
0622a53c 5481 return;
79e53945
JB		 5482 }
5483
c751ce4f 5484 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5485 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5486 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5487 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5488 }
5489}
5490
5491/* Returns the clock of the currently programmed mode of the given pipe. */
5492static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5493{
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5496 int pipe = intel_crtc->pipe;
548f245b 5497 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5498 u32 fp;
5499 intel_clock_t clock;
5500
5501 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5502 fp = I915_READ(FP0(pipe));
79e53945 5503 else
39adb7a5 5504 fp = I915_READ(FP1(pipe));
79e53945
JB		 5505
5506 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5507 if (IS_PINEVIEW(dev)) {
5508 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5509 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5510 } else {
5511 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5512 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5513 }
5514
a6c45cf0 5515 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5516 if (IS_PINEVIEW(dev))
5517 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5518 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5519 else
5520 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5521 DPLL_FPA01_P1_POST_DIV_SHIFT);
5522
5523 switch (dpll & DPLL_MODE_MASK) {
5524 case DPLLB_MODE_DAC_SERIAL:
5525 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5526 5 : 10;
5527 break;
5528 case DPLLB_MODE_LVDS:
5529 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5530 7 : 14;
5531 break;
5532 default:
28c97730 5533 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5534 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5535 return 0;
5536 }
5537
5538 /* XXX: Handle the 100Mhz refclk */
2177832f 5539 intel_clock(dev, 96000, &clock);
79e53945
JB		 5540 } else {
5541 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5542
5543 if (is_lvds) {
5544 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5545 DPLL_FPA01_P1_POST_DIV_SHIFT);
5546 clock.p2 = 14;
5547
5548 if ((dpll & PLL_REF_INPUT_MASK) ==
5549 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5550 /* XXX: might not be 66MHz */
2177832f 5551 intel_clock(dev, 66000, &clock);
79e53945 5552 } else
2177832f 5553 intel_clock(dev, 48000, &clock);
79e53945
JB		 5554 } else {
5555 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5556 clock.p1 = 2;
5557 else {
5558 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5559 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5560 }
5561 if (dpll & PLL_P2_DIVIDE_BY_4)
5562 clock.p2 = 4;
5563 else
5564 clock.p2 = 2;
5565
2177832f 5566 intel_clock(dev, 48000, &clock);
79e53945
JB		 5567 }
5568 }
5569
5570 /* XXX: It would be nice to validate the clocks, but we can't reuse
5571 * i830PllIsValid() because it relies on the xf86_config connector
5572 * configuration being accurate, which it isn't necessarily.
5573 */
5574
5575 return clock.dot;
5576}
5577
5578/** Returns the currently programmed mode of the given pipe. */
5579struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5580 struct drm_crtc *crtc)
5581{
548f245b 5582 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5584 int pipe = intel_crtc->pipe;
5585 struct drm_display_mode *mode;
548f245b
JB		 5586 int htot = I915_READ(HTOTAL(pipe));
5587 int hsync = I915_READ(HSYNC(pipe));
5588 int vtot = I915_READ(VTOTAL(pipe));
5589 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5590
5591 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5592 if (!mode)
5593 return NULL;
5594
5595 mode->clock = intel_crtc_clock_get(dev, crtc);
5596 mode->hdisplay = (htot & 0xffff) + 1;
5597 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5598 mode->hsync_start = (hsync & 0xffff) + 1;
5599 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5600 mode->vdisplay = (vtot & 0xffff) + 1;
5601 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5602 mode->vsync_start = (vsync & 0xffff) + 1;
5603 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5604
5605 drm_mode_set_name(mode);
79e53945
JB		 5606
5607 return mode;
5608}
5609
652c393a
JB		 5610#define GPU_IDLE_TIMEOUT 500 /* ms */
5611
5612/* When this timer fires, we've been idle for awhile */
5613static void intel_gpu_idle_timer(unsigned long arg)
5614{
5615 struct drm_device *dev = (struct drm_device *)arg;
5616 drm_i915_private_t *dev_priv = dev->dev_private;
5617
ff7ea4c0
CW		 5618 if (!list_empty(&dev_priv->mm.active_list)) {
5619 /* Still processing requests, so just re-arm the timer. */
5620 mod_timer(&dev_priv->idle_timer, jiffies +
5621 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5622 return;
5623 }
652c393a 5624
ff7ea4c0 5625 dev_priv->busy = false;
01dfba93 5626 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5627}
5628
652c393a
JB		 5629#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5630
5631static void intel_crtc_idle_timer(unsigned long arg)
5632{
5633 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5634 struct drm_crtc *crtc = &intel_crtc->base;
5635 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5636 struct intel_framebuffer *intel_fb;
652c393a 5637
ff7ea4c0
CW		 5638 intel_fb = to_intel_framebuffer(crtc->fb);
5639 if (intel_fb && intel_fb->obj->active) {
5640 /* The framebuffer is still being accessed by the GPU. */
5641 mod_timer(&intel_crtc->idle_timer, jiffies +
5642 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5643 return;
5644 }
652c393a 5645
ff7ea4c0 5646 intel_crtc->busy = false;
01dfba93 5647 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5648}
5649
3dec0095 5650static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5651{
5652 struct drm_device *dev = crtc->dev;
5653 drm_i915_private_t *dev_priv = dev->dev_private;
5654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5655 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5656 int dpll_reg = DPLL(pipe);
5657 int dpll;
652c393a 5658
bad720ff 5659 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5660 return;
5661
5662 if (!dev_priv->lvds_downclock_avail)
5663 return;
5664
dbdc6479 5665 dpll = I915_READ(dpll_reg);
652c393a 5666 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5667 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5668
8ac5a6d5 5669 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5670
5671 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5672 I915_WRITE(dpll_reg, dpll);
9d0498a2 5673 intel_wait_for_vblank(dev, pipe);
dbdc6479 5674
652c393a
JB		 5675 dpll = I915_READ(dpll_reg);
5676 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5677 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5678 }
5679
5680 /* Schedule downclock */
3dec0095
DV		 5681 mod_timer(&intel_crtc->idle_timer, jiffies +
5682 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5683}
5684
5685static void intel_decrease_pllclock(struct drm_crtc *crtc)
5686{
5687 struct drm_device *dev = crtc->dev;
5688 drm_i915_private_t *dev_priv = dev->dev_private;
5689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5690
bad720ff 5691 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5692 return;
5693
5694 if (!dev_priv->lvds_downclock_avail)
5695 return;
5696
5697 /*
5698 * Since this is called by a timer, we should never get here in
5699 * the manual case.
5700 */
5701 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5702 int pipe = intel_crtc->pipe;
5703 int dpll_reg = DPLL(pipe);
5704 int dpll;
f6e5b160 5705
44d98a61 5706 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5707
8ac5a6d5 5708 assert_panel_unlocked(dev_priv, pipe);
652c393a 5709
dc257cf1 5710 dpll = I915_READ(dpll_reg);
652c393a
JB		 5711 dpll |= DISPLAY_RATE_SELECT_FPA1;
5712 I915_WRITE(dpll_reg, dpll);
9d0498a2 5713 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5714 dpll = I915_READ(dpll_reg);
5715 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5716 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5717 }
5718
5719}
5720
5721/**
5722 * intel_idle_update - adjust clocks for idleness
5723 * @work: work struct
5724 *
5725 * Either the GPU or display (or both) went idle. Check the busy status
5726 * here and adjust the CRTC and GPU clocks as necessary.
5727 */
5728static void intel_idle_update(struct work_struct *work)
5729{
5730 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5731 idle_work);
5732 struct drm_device *dev = dev_priv->dev;
5733 struct drm_crtc *crtc;
5734 struct intel_crtc *intel_crtc;
5735
5736 if (!i915_powersave)
5737 return;
5738
5739 mutex_lock(&dev->struct_mutex);
5740
7648fa99
JB		 5741 i915_update_gfx_val(dev_priv);
5742
652c393a
JB		 5743 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5744 /* Skip inactive CRTCs */
5745 if (!crtc->fb)
5746 continue;
5747
5748 intel_crtc = to_intel_crtc(crtc);
5749 if (!intel_crtc->busy)
5750 intel_decrease_pllclock(crtc);
5751 }
5752
45ac22c8 5753
652c393a
JB		 5754 mutex_unlock(&dev->struct_mutex);
5755}
5756
5757/**
5758 * intel_mark_busy - mark the GPU and possibly the display busy
5759 * @dev: drm device
5760 * @obj: object we're operating on
5761 *
5762 * Callers can use this function to indicate that the GPU is busy processing
5763 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5764 * buffer), we'll also mark the display as busy, so we know to increase its
5765 * clock frequency.
5766 */
05394f39 5767void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 5768{
5769 drm_i915_private_t *dev_priv = dev->dev_private;
5770 struct drm_crtc *crtc = NULL;
5771 struct intel_framebuffer *intel_fb;
5772 struct intel_crtc *intel_crtc;
5773
5e17ee74
ZW		 5774 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5775 return;
5776
9104183d
CW		 5777 if (!dev_priv->busy) {
5778 intel_sanitize_pm(dev);
28cf798f 5779 dev_priv->busy = true;
9104183d 5780 } else
28cf798f
CW		 5781 mod_timer(&dev_priv->idle_timer, jiffies +
5782 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 5783
acb87dfb
CW		 5784 if (obj == NULL)
5785 return;
5786
652c393a
JB		 5787 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5788 if (!crtc->fb)
5789 continue;
5790
5791 intel_crtc = to_intel_crtc(crtc);
5792 intel_fb = to_intel_framebuffer(crtc->fb);
5793 if (intel_fb->obj == obj) {
5794 if (!intel_crtc->busy) {
5795 /* Non-busy -> busy, upclock */
3dec0095 5796 intel_increase_pllclock(crtc);
652c393a
JB		 5797 intel_crtc->busy = true;
5798 } else {
5799 /* Busy -> busy, put off timer */
5800 mod_timer(&intel_crtc->idle_timer, jiffies +
5801 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5802 }
5803 }
5804 }
5805}
5806
79e53945
JB		 5807static void intel_crtc_destroy(struct drm_crtc *crtc)
5808{
5809 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 5810 struct drm_device *dev = crtc->dev;
5811 struct intel_unpin_work *work;
5812 unsigned long flags;
5813
5814 spin_lock_irqsave(&dev->event_lock, flags);
5815 work = intel_crtc->unpin_work;
5816 intel_crtc->unpin_work = NULL;
5817 spin_unlock_irqrestore(&dev->event_lock, flags);
5818
5819 if (work) {
5820 cancel_work_sync(&work->work);
5821 kfree(work);
5822 }
79e53945
JB		 5823
5824 drm_crtc_cleanup(crtc);
67e77c5a 5825
79e53945
JB		 5826 kfree(intel_crtc);
5827}
5828
6b95a207
KH		 5829static void intel_unpin_work_fn(struct work_struct *__work)
5830{
5831 struct intel_unpin_work *work =
5832 container_of(__work, struct intel_unpin_work, work);
5833
5834 mutex_lock(&work->dev->struct_mutex);
1690e1eb 5835 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 5836 drm_gem_object_unreference(&work->pending_flip_obj->base);
5837 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 5838
7782de3b 5839 intel_update_fbc(work->dev);
6b95a207
KH		 5840 mutex_unlock(&work->dev->struct_mutex);
5841 kfree(work);
5842}
5843
1afe3e9d 5844static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 5845 struct drm_crtc *crtc)
6b95a207
KH		 5846{
5847 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 5848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5849 struct intel_unpin_work *work;
05394f39 5850 struct drm_i915_gem_object *obj;
6b95a207 5851 struct drm_pending_vblank_event *e;
49b14a5c 5852 struct timeval tnow, tvbl;
6b95a207
KH		 5853 unsigned long flags;
5854
5855 /* Ignore early vblank irqs */
5856 if (intel_crtc == NULL)
5857 return;
5858
49b14a5c
MK		 5859 do_gettimeofday(&tnow);
5860
6b95a207
KH		 5861 spin_lock_irqsave(&dev->event_lock, flags);
5862 work = intel_crtc->unpin_work;
5863 if (work == NULL || !work->pending) {
5864 spin_unlock_irqrestore(&dev->event_lock, flags);
5865 return;
5866 }
5867
5868 intel_crtc->unpin_work = NULL;
6b95a207
KH		 5869
5870 if (work->event) {
5871 e = work->event;
49b14a5c 5872 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 5873
5874 /* Called before vblank count and timestamps have
5875 * been updated for the vblank interval of flip
5876 * completion? Need to increment vblank count and
5877 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 5878 * to account for this. We assume this happened if we
5879 * get called over 0.9 frame durations after the last
5880 * timestamped vblank.
5881 *
5882 * This calculation can not be used with vrefresh rates
5883 * below 5Hz (10Hz to be on the safe side) without
5884 * promoting to 64 integers.
0af7e4df 5885 */
49b14a5c
MK		 5886 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5887 9 * crtc->framedur_ns) {
0af7e4df 5888 e->event.sequence++;
49b14a5c
MK		 5889 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5890 crtc->framedur_ns);
0af7e4df
MK		 5891 }
5892
49b14a5c
MK		 5893 e->event.tv_sec = tvbl.tv_sec;
5894 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 5895
6b95a207
KH		 5896 list_add_tail(&e->base.link,
5897 &e->base.file_priv->event_list);
5898 wake_up_interruptible(&e->base.file_priv->event_wait);
5899 }
5900
0af7e4df
MK		 5901 drm_vblank_put(dev, intel_crtc->pipe);
5902
6b95a207
KH		 5903 spin_unlock_irqrestore(&dev->event_lock, flags);
5904
05394f39 5905 obj = work->old_fb_obj;
d9e86c0e 5906
e59f2bac 5907 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 5908 &obj->pending_flip.counter);
5909 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 5910 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 5911
6b95a207 5912 schedule_work(&work->work);
e5510fac
JB		 5913
5914 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 5915}
5916
1afe3e9d
JB		 5917void intel_finish_page_flip(struct drm_device *dev, int pipe)
5918{
5919 drm_i915_private_t *dev_priv = dev->dev_private;
5920 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5921
49b14a5c 5922 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5923}
5924
5925void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5926{
5927 drm_i915_private_t *dev_priv = dev->dev_private;
5928 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5929
49b14a5c 5930 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 5931}
5932
6b95a207
KH		 5933void intel_prepare_page_flip(struct drm_device *dev, int plane)
5934{
5935 drm_i915_private_t *dev_priv = dev->dev_private;
5936 struct intel_crtc *intel_crtc =
5937 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5938 unsigned long flags;
5939
5940 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 5941 if (intel_crtc->unpin_work) {
4e5359cd
SF		 5942 if ((++intel_crtc->unpin_work->pending) > 1)
5943 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 5944 } else {
5945 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5946 }
6b95a207
KH		 5947 spin_unlock_irqrestore(&dev->event_lock, flags);
5948}
5949
8c9f3aaf
JB		 5950static int intel_gen2_queue_flip(struct drm_device *dev,
5951 struct drm_crtc *crtc,
5952 struct drm_framebuffer *fb,
5953 struct drm_i915_gem_object *obj)
5954{
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5957 unsigned long offset;
5958 u32 flip_mask;
6d90c952 5959 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 5960 int ret;
5961
6d90c952 5962 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 5963 if (ret)
83d4092b 5964 goto err;
8c9f3aaf
JB		 5965
5966 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 5967 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 5968
6d90c952 5969 ret = intel_ring_begin(ring, 6);
8c9f3aaf 5970 if (ret)
83d4092b 5971 goto err_unpin;
8c9f3aaf
JB		 5972
5973 /* Can't queue multiple flips, so wait for the previous
5974 * one to finish before executing the next.
5975 */
5976 if (intel_crtc->plane)
5977 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5978 else
5979 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 5980 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
5981 intel_ring_emit(ring, MI_NOOP);
5982 intel_ring_emit(ring, MI_DISPLAY_FLIP |
5983 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5984 intel_ring_emit(ring, fb->pitches[0]);
5985 intel_ring_emit(ring, obj->gtt_offset + offset);
5986 intel_ring_emit(ring, 0); /* aux display base address, unused */
5987 intel_ring_advance(ring);
83d4092b
CW		 5988 return 0;
5989
5990err_unpin:
5991 intel_unpin_fb_obj(obj);
5992err:
8c9f3aaf
JB		 5993 return ret;
5994}
5995
5996static int intel_gen3_queue_flip(struct drm_device *dev,
5997 struct drm_crtc *crtc,
5998 struct drm_framebuffer *fb,
5999 struct drm_i915_gem_object *obj)
6000{
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6003 unsigned long offset;
6004 u32 flip_mask;
6d90c952 6005 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6006 int ret;
6007
6d90c952 6008 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6009 if (ret)
83d4092b 6010 goto err;
8c9f3aaf
JB		 6011
6012 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 6013 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf 6014
6d90c952 6015 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6016 if (ret)
83d4092b 6017 goto err_unpin;
8c9f3aaf
JB		 6018
6019 if (intel_crtc->plane)
6020 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6021 else
6022 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6023 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6024 intel_ring_emit(ring, MI_NOOP);
6025 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6026 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6027 intel_ring_emit(ring, fb->pitches[0]);
6028 intel_ring_emit(ring, obj->gtt_offset + offset);
6029 intel_ring_emit(ring, MI_NOOP);
6030
6031 intel_ring_advance(ring);
83d4092b
CW		 6032 return 0;
6033
6034err_unpin:
6035 intel_unpin_fb_obj(obj);
6036err:
8c9f3aaf
JB		 6037 return ret;
6038}
6039
6040static int intel_gen4_queue_flip(struct drm_device *dev,
6041 struct drm_crtc *crtc,
6042 struct drm_framebuffer *fb,
6043 struct drm_i915_gem_object *obj)
6044{
6045 struct drm_i915_private *dev_priv = dev->dev_private;
6046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6047 uint32_t pf, pipesrc;
6d90c952 6048 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6049 int ret;
6050
6d90c952 6051 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6052 if (ret)
83d4092b 6053 goto err;
8c9f3aaf 6054
6d90c952 6055 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6056 if (ret)
83d4092b 6057 goto err_unpin;
8c9f3aaf
JB		 6058
6059 /* i965+ uses the linear or tiled offsets from the
6060 * Display Registers (which do not change across a page-flip)
6061 * so we need only reprogram the base address.
6062 */
6d90c952
DV		 6063 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6064 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6065 intel_ring_emit(ring, fb->pitches[0]);
6066 intel_ring_emit(ring, obj->gtt_offset | obj->tiling_mode);
8c9f3aaf
JB		 6067
6068 /* XXX Enabling the panel-fitter across page-flip is so far
6069 * untested on non-native modes, so ignore it for now.
6070 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6071 */
6072 pf = 0;
6073 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6074 intel_ring_emit(ring, pf | pipesrc);
6075 intel_ring_advance(ring);
83d4092b
CW		 6076 return 0;
6077
6078err_unpin:
6079 intel_unpin_fb_obj(obj);
6080err:
8c9f3aaf
JB		 6081 return ret;
6082}
6083
6084static int intel_gen6_queue_flip(struct drm_device *dev,
6085 struct drm_crtc *crtc,
6086 struct drm_framebuffer *fb,
6087 struct drm_i915_gem_object *obj)
6088{
6089 struct drm_i915_private *dev_priv = dev->dev_private;
6090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6091 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6092 uint32_t pf, pipesrc;
6093 int ret;
6094
6d90c952 6095 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6096 if (ret)
83d4092b 6097 goto err;
8c9f3aaf 6098
6d90c952 6099 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6100 if (ret)
83d4092b 6101 goto err_unpin;
8c9f3aaf 6102
6d90c952
DV		 6103 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6104 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6105 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6106 intel_ring_emit(ring, obj->gtt_offset);
8c9f3aaf 6107
dc257cf1
DV		 6108 /* Contrary to the suggestions in the documentation,
6109 * "Enable Panel Fitter" does not seem to be required when page
6110 * flipping with a non-native mode, and worse causes a normal
6111 * modeset to fail.
6112 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6113 */
6114 pf = 0;
8c9f3aaf 6115 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6116 intel_ring_emit(ring, pf | pipesrc);
6117 intel_ring_advance(ring);
83d4092b
CW		 6118 return 0;
6119
6120err_unpin:
6121 intel_unpin_fb_obj(obj);
6122err:
8c9f3aaf
JB		 6123 return ret;
6124}
6125
7c9017e5
JB		 6126/*
6127 * On gen7 we currently use the blit ring because (in early silicon at least)
6128 * the render ring doesn't give us interrpts for page flip completion, which
6129 * means clients will hang after the first flip is queued. Fortunately the
6130 * blit ring generates interrupts properly, so use it instead.
6131 */
6132static int intel_gen7_queue_flip(struct drm_device *dev,
6133 struct drm_crtc *crtc,
6134 struct drm_framebuffer *fb,
6135 struct drm_i915_gem_object *obj)
6136{
6137 struct drm_i915_private *dev_priv = dev->dev_private;
6138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6139 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6140 int ret;
6141
6142 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6143 if (ret)
83d4092b 6144 goto err;
7c9017e5
JB		 6145
6146 ret = intel_ring_begin(ring, 4);
6147 if (ret)
83d4092b 6148 goto err_unpin;
7c9017e5
JB		 6149
6150 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 6151 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 6152 intel_ring_emit(ring, (obj->gtt_offset));
6153 intel_ring_emit(ring, (MI_NOOP));
6154 intel_ring_advance(ring);
83d4092b
CW		 6155 return 0;
6156
6157err_unpin:
6158 intel_unpin_fb_obj(obj);
6159err:
7c9017e5
JB		 6160 return ret;
6161}
6162
8c9f3aaf
JB		 6163static int intel_default_queue_flip(struct drm_device *dev,
6164 struct drm_crtc *crtc,
6165 struct drm_framebuffer *fb,
6166 struct drm_i915_gem_object *obj)
6167{
6168 return -ENODEV;
6169}
6170
6b95a207
KH		 6171static int intel_crtc_page_flip(struct drm_crtc *crtc,
6172 struct drm_framebuffer *fb,
6173 struct drm_pending_vblank_event *event)
6174{
6175 struct drm_device *dev = crtc->dev;
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177 struct intel_framebuffer *intel_fb;
05394f39 6178 struct drm_i915_gem_object *obj;
6b95a207
KH		 6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180 struct intel_unpin_work *work;
8c9f3aaf 6181 unsigned long flags;
52e68630 6182 int ret;
6b95a207
KH		 6183
6184 work = kzalloc(sizeof *work, GFP_KERNEL);
6185 if (work == NULL)
6186 return -ENOMEM;
6187
6b95a207
KH		 6188 work->event = event;
6189 work->dev = crtc->dev;
6190 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6191 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6192 INIT_WORK(&work->work, intel_unpin_work_fn);
6193
7317c75e
JB		 6194 ret = drm_vblank_get(dev, intel_crtc->pipe);
6195 if (ret)
6196 goto free_work;
6197
6b95a207
KH		 6198 /* We borrow the event spin lock for protecting unpin_work */
6199 spin_lock_irqsave(&dev->event_lock, flags);
6200 if (intel_crtc->unpin_work) {
6201 spin_unlock_irqrestore(&dev->event_lock, flags);
6202 kfree(work);
7317c75e 6203 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6204
6205 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6206 return -EBUSY;
6207 }
6208 intel_crtc->unpin_work = work;
6209 spin_unlock_irqrestore(&dev->event_lock, flags);
6210
6211 intel_fb = to_intel_framebuffer(fb);
6212 obj = intel_fb->obj;
6213
468f0b44 6214 mutex_lock(&dev->struct_mutex);
6b95a207 6215
75dfca80 6216 /* Reference the objects for the scheduled work. */
05394f39
CW		 6217 drm_gem_object_reference(&work->old_fb_obj->base);
6218 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6219
6220 crtc->fb = fb;
96b099fd 6221
e1f99ce6 6222 work->pending_flip_obj = obj;
e1f99ce6 6223
4e5359cd
SF		 6224 work->enable_stall_check = true;
6225
e1f99ce6
CW		 6226 /* Block clients from rendering to the new back buffer until
6227 * the flip occurs and the object is no longer visible.
6228 */
05394f39 6229 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6230
8c9f3aaf
JB		 6231 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6232 if (ret)
6233 goto cleanup_pending;
6b95a207 6234
7782de3b 6235 intel_disable_fbc(dev);
acb87dfb 6236 intel_mark_busy(dev, obj);
6b95a207
KH		 6237 mutex_unlock(&dev->struct_mutex);
6238
e5510fac
JB		 6239 trace_i915_flip_request(intel_crtc->plane, obj);
6240
6b95a207 6241 return 0;
96b099fd 6242
8c9f3aaf
JB		 6243cleanup_pending:
6244 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6245 drm_gem_object_unreference(&work->old_fb_obj->base);
6246 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6247 mutex_unlock(&dev->struct_mutex);
6248
6249 spin_lock_irqsave(&dev->event_lock, flags);
6250 intel_crtc->unpin_work = NULL;
6251 spin_unlock_irqrestore(&dev->event_lock, flags);
6252
7317c75e
JB		 6253 drm_vblank_put(dev, intel_crtc->pipe);
6254free_work:
96b099fd
CW		 6255 kfree(work);
6256
6257 return ret;
6b95a207
KH		 6258}
6259
47f1c6c9
CW		 6260static void intel_sanitize_modesetting(struct drm_device *dev,
6261 int pipe, int plane)
6262{
6263 struct drm_i915_private *dev_priv = dev->dev_private;
6264 u32 reg, val;
a9dcf84b 6265 int i;
47f1c6c9 6266
f47166d2 6267 /* Clear any frame start delays used for debugging left by the BIOS */
a9dcf84b
DV		 6268 for_each_pipe(i) {
6269 reg = PIPECONF(i);
f47166d2
CW		 6270 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6271 }
6272
47f1c6c9
CW		 6273 if (HAS_PCH_SPLIT(dev))
6274 return;
6275
6276 /* Who knows what state these registers were left in by the BIOS or
6277 * grub?
6278 *
6279 * If we leave the registers in a conflicting state (e.g. with the
6280 * display plane reading from the other pipe than the one we intend
6281 * to use) then when we attempt to teardown the active mode, we will
6282 * not disable the pipes and planes in the correct order -- leaving
6283 * a plane reading from a disabled pipe and possibly leading to
6284 * undefined behaviour.
6285 */
6286
6287 reg = DSPCNTR(plane);
6288 val = I915_READ(reg);
6289
6290 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6291 return;
6292 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6293 return;
6294
6295 /* This display plane is active and attached to the other CPU pipe. */
6296 pipe = !pipe;
6297
6298 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6299 intel_disable_plane(dev_priv, plane, pipe);
6300 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6301}
79e53945 6302
f6e5b160
CW		 6303static void intel_crtc_reset(struct drm_crtc *crtc)
6304{
6305 struct drm_device *dev = crtc->dev;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307
6308 /* Reset flags back to the 'unknown' status so that they
6309 * will be correctly set on the initial modeset.
6310 */
6311 intel_crtc->dpms_mode = -1;
6312
6313 /* We need to fix up any BIOS configuration that conflicts with
6314 * our expectations.
6315 */
6316 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6317}
6318
6319static struct drm_crtc_helper_funcs intel_helper_funcs = {
6320 .dpms = intel_crtc_dpms,
6321 .mode_fixup = intel_crtc_mode_fixup,
6322 .mode_set = intel_crtc_mode_set,
6323 .mode_set_base = intel_pipe_set_base,
6324 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6325 .load_lut = intel_crtc_load_lut,
6326 .disable = intel_crtc_disable,
6327};
6328
6329static const struct drm_crtc_funcs intel_crtc_funcs = {
6330 .reset = intel_crtc_reset,
6331 .cursor_set = intel_crtc_cursor_set,
6332 .cursor_move = intel_crtc_cursor_move,
6333 .gamma_set = intel_crtc_gamma_set,
6334 .set_config = drm_crtc_helper_set_config,
6335 .destroy = intel_crtc_destroy,
6336 .page_flip = intel_crtc_page_flip,
6337};
6338
ee7b9f93
JB		 6339static void intel_pch_pll_init(struct drm_device *dev)
6340{
6341 drm_i915_private_t *dev_priv = dev->dev_private;
6342 int i;
6343
6344 if (dev_priv->num_pch_pll == 0) {
6345 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6346 return;
6347 }
6348
6349 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6350 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6351 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6352 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6353 }
6354}
6355
b358d0a6 6356static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6357{
22fd0fab 6358 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6359 struct intel_crtc *intel_crtc;
6360 int i;
6361
6362 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6363 if (intel_crtc == NULL)
6364 return;
6365
6366 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6367
6368 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6369 for (i = 0; i < 256; i++) {
6370 intel_crtc->lut_r[i] = i;
6371 intel_crtc->lut_g[i] = i;
6372 intel_crtc->lut_b[i] = i;
6373 }
6374
80824003
JB		 6375 /* Swap pipes & planes for FBC on pre-965 */
6376 intel_crtc->pipe = pipe;
6377 intel_crtc->plane = pipe;
e2e767ab 6378 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6379 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6380 intel_crtc->plane = !pipe;
80824003
JB		 6381 }
6382
22fd0fab
JB		 6383 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6384 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6385 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6386 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6387
5d1d0cc8 6388 intel_crtc_reset(&intel_crtc->base);
04dbff52 6389 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6390 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6391
6392 if (HAS_PCH_SPLIT(dev)) {
6393 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6394 intel_helper_funcs.commit = ironlake_crtc_commit;
6395 } else {
6396 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6397 intel_helper_funcs.commit = i9xx_crtc_commit;
6398 }
6399
79e53945
JB		 6400 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6401
652c393a
JB		 6402 intel_crtc->busy = false;
6403
6404 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6405 (unsigned long)intel_crtc);
79e53945
JB		 6406}
6407
08d7b3d1 6408int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6409 struct drm_file *file)
08d7b3d1 6410{
08d7b3d1 6411 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6412 struct drm_mode_object *drmmode_obj;
6413 struct intel_crtc *crtc;
08d7b3d1 6414
1cff8f6b
DV		 6415 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6416 return -ENODEV;
08d7b3d1 6417
c05422d5
DV		 6418 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6419 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6420
c05422d5 6421 if (!drmmode_obj) {
08d7b3d1
CW		 6422 DRM_ERROR("no such CRTC id\n");
6423 return -EINVAL;
6424 }
6425
c05422d5
DV		 6426 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6427 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6428
c05422d5 6429 return 0;
08d7b3d1
CW		 6430}
6431
c5e4df33 6432static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6433{
4ef69c7a 6434 struct intel_encoder *encoder;
79e53945 6435 int index_mask = 0;
79e53945
JB		 6436 int entry = 0;
6437
4ef69c7a
CW		 6438 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6439 if (type_mask & encoder->clone_mask)
79e53945
JB		 6440 index_mask |= (1 << entry);
6441 entry++;
6442 }
4ef69c7a 6443
79e53945
JB		 6444 return index_mask;
6445}
6446
4d302442
CW		 6447static bool has_edp_a(struct drm_device *dev)
6448{
6449 struct drm_i915_private *dev_priv = dev->dev_private;
6450
6451 if (!IS_MOBILE(dev))
6452 return false;
6453
6454 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6455 return false;
6456
6457 if (IS_GEN5(dev) &&
6458 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6459 return false;
6460
6461 return true;
6462}
6463
79e53945
JB		 6464static void intel_setup_outputs(struct drm_device *dev)
6465{
725e30ad 6466 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6467 struct intel_encoder *encoder;
cb0953d7 6468 bool dpd_is_edp = false;
f3cfcba6 6469 bool has_lvds;
79e53945 6470
f3cfcba6 6471 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6472 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6473 /* disable the panel fitter on everything but LVDS */
6474 I915_WRITE(PFIT_CONTROL, 0);
6475 }
79e53945 6476
bad720ff 6477 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6478 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6479
4d302442 6480 if (has_edp_a(dev))
32f9d658
ZW		 6481 intel_dp_init(dev, DP_A);
6482
cb0953d7
AJ		 6483 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6484 intel_dp_init(dev, PCH_DP_D);
6485 }
6486
6487 intel_crt_init(dev);
6488
0e72a5b5
ED		 6489 if (IS_HASWELL(dev)) {
6490 int found;
6491
6492 /* Haswell uses DDI functions to detect digital outputs */
6493 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6494 /* DDI A only supports eDP */
6495 if (found)
6496 intel_ddi_init(dev, PORT_A);
6497
6498 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6499 * register */
6500 found = I915_READ(SFUSE_STRAP);
6501
6502 if (found & SFUSE_STRAP_DDIB_DETECTED)
6503 intel_ddi_init(dev, PORT_B);
6504 if (found & SFUSE_STRAP_DDIC_DETECTED)
6505 intel_ddi_init(dev, PORT_C);
6506 if (found & SFUSE_STRAP_DDID_DETECTED)
6507 intel_ddi_init(dev, PORT_D);
6508 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 6509 int found;
6510
30ad48b7 6511 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6512 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6513 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6514 if (!found)
6515 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6516 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6517 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6518 }
6519
6520 if (I915_READ(HDMIC) & PORT_DETECTED)
6521 intel_hdmi_init(dev, HDMIC);
6522
6523 if (I915_READ(HDMID) & PORT_DETECTED)
6524 intel_hdmi_init(dev, HDMID);
6525
5eb08b69
ZW		 6526 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6527 intel_dp_init(dev, PCH_DP_C);
6528
cb0953d7 6529 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 6530 intel_dp_init(dev, PCH_DP_D);
6531
103a196f 6532 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6533 bool found = false;
7d57382e 6534
725e30ad 6535 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6536 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6537 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6538 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6539 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6540 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6541 }
27185ae1 6542
b01f2c3a
JB		 6543 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6544 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6545 intel_dp_init(dev, DP_B);
b01f2c3a 6546 }
725e30ad 6547 }
13520b05
KH		 6548
6549 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6550
b01f2c3a
JB		 6551 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6552 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6553 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6554 }
27185ae1
ML		 6555
6556 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6557
b01f2c3a
JB		 6558 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6559 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6560 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6561 }
6562 if (SUPPORTS_INTEGRATED_DP(dev)) {
6563 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6564 intel_dp_init(dev, DP_C);
b01f2c3a 6565 }
725e30ad 6566 }
27185ae1 6567
b01f2c3a
JB		 6568 if (SUPPORTS_INTEGRATED_DP(dev) &&
6569 (I915_READ(DP_D) & DP_DETECTED)) {
6570 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6571 intel_dp_init(dev, DP_D);
b01f2c3a 6572 }
bad720ff 6573 } else if (IS_GEN2(dev))
79e53945
JB		 6574 intel_dvo_init(dev);
6575
103a196f 6576 if (SUPPORTS_TV(dev))
79e53945
JB		 6577 intel_tv_init(dev);
6578
4ef69c7a
CW		 6579 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6580 encoder->base.possible_crtcs = encoder->crtc_mask;
6581 encoder->base.possible_clones =
6582 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6583 }
47356eb6 6584
2c7111db
CW		 6585 /* disable all the possible outputs/crtcs before entering KMS mode */
6586 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 6587
6588 if (HAS_PCH_SPLIT(dev))
6589 ironlake_init_pch_refclk(dev);
79e53945
JB		 6590}
6591
6592static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6593{
6594 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6595
6596 drm_framebuffer_cleanup(fb);
05394f39 6597 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6598
6599 kfree(intel_fb);
6600}
6601
6602static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6603 struct drm_file *file,
79e53945
JB		 6604 unsigned int *handle)
6605{
6606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6607 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6608
05394f39 6609 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6610}
6611
6612static const struct drm_framebuffer_funcs intel_fb_funcs = {
6613 .destroy = intel_user_framebuffer_destroy,
6614 .create_handle = intel_user_framebuffer_create_handle,
6615};
6616
38651674
DA		 6617int intel_framebuffer_init(struct drm_device *dev,
6618 struct intel_framebuffer *intel_fb,
308e5bcb 6619 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6620 struct drm_i915_gem_object *obj)
79e53945 6621{
79e53945
JB		 6622 int ret;
6623
05394f39 6624 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6625 return -EINVAL;
6626
308e5bcb 6627 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6628 return -EINVAL;
6629
308e5bcb 6630 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6631 case DRM_FORMAT_RGB332:
6632 case DRM_FORMAT_RGB565:
6633 case DRM_FORMAT_XRGB8888:
b250da79 6634 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6635 case DRM_FORMAT_ARGB8888:
6636 case DRM_FORMAT_XRGB2101010:
6637 case DRM_FORMAT_ARGB2101010:
308e5bcb 6638 /* RGB formats are common across chipsets */
b5626747 6639 break;
04b3924d
VS		 6640 case DRM_FORMAT_YUYV:
6641 case DRM_FORMAT_UYVY:
6642 case DRM_FORMAT_YVYU:
6643 case DRM_FORMAT_VYUY:
57cd6508
CW		 6644 break;
6645 default:
aca25848
ED		 6646 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6647 mode_cmd->pixel_format);
57cd6508
CW		 6648 return -EINVAL;
6649 }
6650
79e53945
JB		 6651 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6652 if (ret) {
6653 DRM_ERROR("framebuffer init failed %d\n", ret);
6654 return ret;
6655 }
6656
6657 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6658 intel_fb->obj = obj;
79e53945
JB		 6659 return 0;
6660}
6661
79e53945
JB		 6662static struct drm_framebuffer *
6663intel_user_framebuffer_create(struct drm_device *dev,
6664 struct drm_file *filp,
308e5bcb 6665 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6666{
05394f39 6667 struct drm_i915_gem_object *obj;
79e53945 6668
308e5bcb
JB		 6669 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6670 mode_cmd->handles[0]));
c8725226 6671 if (&obj->base == NULL)
cce13ff7 6672 return ERR_PTR(-ENOENT);
79e53945 6673
d2dff872 6674 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6675}
6676
79e53945 6677static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6678 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6679 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6680};
6681
e70236a8
JB		 6682/* Set up chip specific display functions */
6683static void intel_init_display(struct drm_device *dev)
6684{
6685 struct drm_i915_private *dev_priv = dev->dev_private;
6686
6687 /* We always want a DPMS function */
f564048e 6688 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6689 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6690 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6691 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6692 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6693 } else {
e70236a8 6694 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 6695 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 6696 dev_priv->display.off = i9xx_crtc_off;
17638cd6 6697 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 6698 }
e70236a8 6699
e70236a8 6700 /* Returns the core display clock speed */
25eb05fc
JB		 6701 if (IS_VALLEYVIEW(dev))
6702 dev_priv->display.get_display_clock_speed =
6703 valleyview_get_display_clock_speed;
6704 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 6705 dev_priv->display.get_display_clock_speed =
6706 i945_get_display_clock_speed;
6707 else if (IS_I915G(dev))
6708 dev_priv->display.get_display_clock_speed =
6709 i915_get_display_clock_speed;
f2b115e6 6710 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 6711 dev_priv->display.get_display_clock_speed =
6712 i9xx_misc_get_display_clock_speed;
6713 else if (IS_I915GM(dev))
6714 dev_priv->display.get_display_clock_speed =
6715 i915gm_get_display_clock_speed;
6716 else if (IS_I865G(dev))
6717 dev_priv->display.get_display_clock_speed =
6718 i865_get_display_clock_speed;
f0f8a9ce 6719 else if (IS_I85X(dev))
e70236a8
JB		 6720 dev_priv->display.get_display_clock_speed =
6721 i855_get_display_clock_speed;
6722 else /* 852, 830 */
6723 dev_priv->display.get_display_clock_speed =
6724 i830_get_display_clock_speed;
6725
7f8a8569 6726 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 6727 if (IS_GEN5(dev)) {
674cf967 6728 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 6729 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 6730 } else if (IS_GEN6(dev)) {
674cf967 6731 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 6732 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 6733 } else if (IS_IVYBRIDGE(dev)) {
6734 /* FIXME: detect B0+ stepping and use auto training */
6735 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 6736 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 6737 } else if (IS_HASWELL(dev)) {
6738 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
4abb3c8c 6739 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 6740 } else
6741 dev_priv->display.update_wm = NULL;
ceb04246 6742 } else if (IS_VALLEYVIEW(dev)) {
575155a9
JB		 6743 dev_priv->display.force_wake_get = vlv_force_wake_get;
6744 dev_priv->display.force_wake_put = vlv_force_wake_put;
6067aaea 6745 } else if (IS_G4X(dev)) {
e0dac65e 6746 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 6747 }
8c9f3aaf
JB		 6748
6749 /* Default just returns -ENODEV to indicate unsupported */
6750 dev_priv->display.queue_flip = intel_default_queue_flip;
6751
6752 switch (INTEL_INFO(dev)->gen) {
6753 case 2:
6754 dev_priv->display.queue_flip = intel_gen2_queue_flip;
6755 break;
6756
6757 case 3:
6758 dev_priv->display.queue_flip = intel_gen3_queue_flip;
6759 break;
6760
6761 case 4:
6762 case 5:
6763 dev_priv->display.queue_flip = intel_gen4_queue_flip;
6764 break;
6765
6766 case 6:
6767 dev_priv->display.queue_flip = intel_gen6_queue_flip;
6768 break;
7c9017e5
JB		 6769 case 7:
6770 dev_priv->display.queue_flip = intel_gen7_queue_flip;
6771 break;
8c9f3aaf 6772 }
e70236a8
JB		 6773}
6774
b690e96c
JB		 6775/*
6776 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6777 * resume, or other times. This quirk makes sure that's the case for
6778 * affected systems.
6779 */
0206e353 6780static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 6781{
6782 struct drm_i915_private *dev_priv = dev->dev_private;
6783
6784 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 6785 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 6786}
6787
435793df
KP		 6788/*
6789 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
6790 */
6791static void quirk_ssc_force_disable(struct drm_device *dev)
6792{
6793 struct drm_i915_private *dev_priv = dev->dev_private;
6794 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 6795 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 6796}
6797
4dca20ef 6798/*
5a15ab5b
CE		 6799 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
6800 * brightness value
4dca20ef
CE		 6801 */
6802static void quirk_invert_brightness(struct drm_device *dev)
6803{
6804 struct drm_i915_private *dev_priv = dev->dev_private;
6805 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 6806 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 6807}
6808
b690e96c
JB		 6809struct intel_quirk {
6810 int device;
6811 int subsystem_vendor;
6812 int subsystem_device;
6813 void (*hook)(struct drm_device *dev);
6814};
6815
c43b5634 6816static struct intel_quirk intel_quirks[] = {
b690e96c 6817 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 6818 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 6819
6820 /* Thinkpad R31 needs pipe A force quirk */
6821 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6822 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6823 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6824
6825 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6826 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6827 /* ThinkPad X40 needs pipe A force quirk */
6828
6829 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6830 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6831
6832 /* 855 & before need to leave pipe A & dpll A up */
6833 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6834 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 6835
6836 /* Lenovo U160 cannot use SSC on LVDS */
6837 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 6838
6839 /* Sony Vaio Y cannot use SSC on LVDS */
6840 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 6841
6842 /* Acer Aspire 5734Z must invert backlight brightness */
6843 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 6844};
6845
6846static void intel_init_quirks(struct drm_device *dev)
6847{
6848 struct pci_dev *d = dev->pdev;
6849 int i;
6850
6851 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6852 struct intel_quirk *q = &intel_quirks[i];
6853
6854 if (d->device == q->device &&
6855 (d->subsystem_vendor == q->subsystem_vendor ||
6856 q->subsystem_vendor == PCI_ANY_ID) &&
6857 (d->subsystem_device == q->subsystem_device ||
6858 q->subsystem_device == PCI_ANY_ID))
6859 q->hook(dev);
6860 }
6861}
6862
9cce37f4
JB		 6863/* Disable the VGA plane that we never use */
6864static void i915_disable_vga(struct drm_device *dev)
6865{
6866 struct drm_i915_private *dev_priv = dev->dev_private;
6867 u8 sr1;
6868 u32 vga_reg;
6869
6870 if (HAS_PCH_SPLIT(dev))
6871 vga_reg = CPU_VGACNTRL;
6872 else
6873 vga_reg = VGACNTRL;
6874
6875 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 6876 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 6877 sr1 = inb(VGA_SR_DATA);
6878 outb(sr1 | 1<<5, VGA_SR_DATA);
6879 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6880 udelay(300);
6881
6882 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6883 POSTING_READ(vga_reg);
6884}
6885
f82cfb6b
JB		 6886static void ivb_pch_pwm_override(struct drm_device *dev)
6887{
6888 struct drm_i915_private *dev_priv = dev->dev_private;
6889
6890 /*
6891 * IVB has CPU eDP backlight regs too, set things up to let the
6892 * PCH regs control the backlight
6893 */
6894 I915_WRITE(BLC_PWM_CPU_CTL2, PWM_ENABLE);
6895 I915_WRITE(BLC_PWM_CPU_CTL, 0);
6896 I915_WRITE(BLC_PWM_PCH_CTL1, PWM_ENABLE | (1<<30));
6897}
6898
f817586c
DV		 6899void intel_modeset_init_hw(struct drm_device *dev)
6900{
6901 struct drm_i915_private *dev_priv = dev->dev_private;
6902
6903 intel_init_clock_gating(dev);
6904
6905 if (IS_IRONLAKE_M(dev)) {
6906 ironlake_enable_drps(dev);
1833b134 6907 ironlake_enable_rc6(dev);
f817586c
DV		 6908 intel_init_emon(dev);
6909 }
6910
b6834bd6 6911 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
f817586c
DV		 6912 gen6_enable_rps(dev_priv);
6913 gen6_update_ring_freq(dev_priv);
6914 }
f82cfb6b
JB		 6915
6916 if (IS_IVYBRIDGE(dev))
6917 ivb_pch_pwm_override(dev);
f817586c
DV		 6918}
6919
79e53945
JB		 6920void intel_modeset_init(struct drm_device *dev)
6921{
652c393a 6922 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 6923 int i, ret;
79e53945
JB		 6924
6925 drm_mode_config_init(dev);
6926
6927 dev->mode_config.min_width = 0;
6928 dev->mode_config.min_height = 0;
6929
019d96cb
DA		 6930 dev->mode_config.preferred_depth = 24;
6931 dev->mode_config.prefer_shadow = 1;
6932
79e53945
JB		 6933 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6934
b690e96c
JB		 6935 intel_init_quirks(dev);
6936
1fa61106
ED		 6937 intel_init_pm(dev);
6938
45244b87
ED		 6939 intel_prepare_ddi(dev);
6940
e70236a8
JB		 6941 intel_init_display(dev);
6942
a6c45cf0
CW		 6943 if (IS_GEN2(dev)) {
6944 dev->mode_config.max_width = 2048;
6945 dev->mode_config.max_height = 2048;
6946 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 6947 dev->mode_config.max_width = 4096;
6948 dev->mode_config.max_height = 4096;
79e53945 6949 } else {
a6c45cf0
CW		 6950 dev->mode_config.max_width = 8192;
6951 dev->mode_config.max_height = 8192;
79e53945 6952 }
35c3047a 6953 dev->mode_config.fb_base = dev->agp->base;
79e53945 6954
28c97730 6955 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 6956 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 6957
a3524f1b 6958 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 6959 intel_crtc_init(dev, i);
00c2064b
JB		 6960 ret = intel_plane_init(dev, i);
6961 if (ret)
6962 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 6963 }
6964
ee7b9f93
JB		 6965 intel_pch_pll_init(dev);
6966
9cce37f4
JB		 6967 /* Just disable it once at startup */
6968 i915_disable_vga(dev);
79e53945 6969 intel_setup_outputs(dev);
652c393a 6970
652c393a
JB		 6971 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6972 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6973 (unsigned long)dev);
2c7111db
CW		 6974}
6975
6976void intel_modeset_gem_init(struct drm_device *dev)
6977{
1833b134 6978 intel_modeset_init_hw(dev);
02e792fb
DV		 6979
6980 intel_setup_overlay(dev);
79e53945
JB		 6981}
6982
6983void intel_modeset_cleanup(struct drm_device *dev)
6984{
652c393a
JB		 6985 struct drm_i915_private *dev_priv = dev->dev_private;
6986 struct drm_crtc *crtc;
6987 struct intel_crtc *intel_crtc;
6988
f87ea761 6989 drm_kms_helper_poll_fini(dev);
652c393a
JB		 6990 mutex_lock(&dev->struct_mutex);
6991
723bfd70
JB		 6992 intel_unregister_dsm_handler();
6993
6994
652c393a
JB		 6995 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6996 /* Skip inactive CRTCs */
6997 if (!crtc->fb)
6998 continue;
6999
7000 intel_crtc = to_intel_crtc(crtc);
3dec0095 7001 intel_increase_pllclock(crtc);
652c393a
JB		 7002 }
7003
973d04f9 7004 intel_disable_fbc(dev);
e70236a8 7005
f97108d1
JB		 7006 if (IS_IRONLAKE_M(dev))
7007 ironlake_disable_drps(dev);
b6834bd6 7008 if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev))
3b8d8d91 7009 gen6_disable_rps(dev);
f97108d1 7010
d5bb081b
JB		 7011 if (IS_IRONLAKE_M(dev))
7012 ironlake_disable_rc6(dev);
0cdab21f 7013
57f350b6
JB		 7014 if (IS_VALLEYVIEW(dev))
7015 vlv_init_dpio(dev);
7016
69341a5e
KH		 7017 mutex_unlock(&dev->struct_mutex);
7018
6c0d9350
DV		 7019 /* Disable the irq before mode object teardown, for the irq might
7020 * enqueue unpin/hotplug work. */
7021 drm_irq_uninstall(dev);
7022 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 7023 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 7024
1630fe75
CW		 7025 /* flush any delayed tasks or pending work */
7026 flush_scheduled_work();
7027
3dec0095
DV		 7028 /* Shut off idle work before the crtcs get freed. */
7029 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7030 intel_crtc = to_intel_crtc(crtc);
7031 del_timer_sync(&intel_crtc->idle_timer);
7032 }
7033 del_timer_sync(&dev_priv->idle_timer);
7034 cancel_work_sync(&dev_priv->idle_work);
7035
79e53945
JB		 7036 drm_mode_config_cleanup(dev);
7037}
7038
f1c79df3
ZW		 7039/*
7040 * Return which encoder is currently attached for connector.
7041 */
df0e9248 7042struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7043{
df0e9248
CW		 7044 return &intel_attached_encoder(connector)->base;
7045}
f1c79df3 7046
df0e9248
CW		 7047void intel_connector_attach_encoder(struct intel_connector *connector,
7048 struct intel_encoder *encoder)
7049{
7050 connector->encoder = encoder;
7051 drm_mode_connector_attach_encoder(&connector->base,
7052 &encoder->base);
79e53945 7053}
28d52043
DA		 7054
7055/*
7056 * set vga decode state - true == enable VGA decode
7057 */
7058int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7059{
7060 struct drm_i915_private *dev_priv = dev->dev_private;
7061 u16 gmch_ctrl;
7062
7063 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7064 if (state)
7065 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7066 else
7067 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7068 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7069 return 0;
7070}
c4a1d9e4
CW		 7071
7072#ifdef CONFIG_DEBUG_FS
7073#include <linux/seq_file.h>
7074
7075struct intel_display_error_state {
7076 struct intel_cursor_error_state {
7077 u32 control;
7078 u32 position;
7079 u32 base;
7080 u32 size;
7081 } cursor[2];
7082
7083 struct intel_pipe_error_state {
7084 u32 conf;
7085 u32 source;
7086
7087 u32 htotal;
7088 u32 hblank;
7089 u32 hsync;
7090 u32 vtotal;
7091 u32 vblank;
7092 u32 vsync;
7093 } pipe[2];
7094
7095 struct intel_plane_error_state {
7096 u32 control;
7097 u32 stride;
7098 u32 size;
7099 u32 pos;
7100 u32 addr;
7101 u32 surface;
7102 u32 tile_offset;
7103 } plane[2];
7104};
7105
7106struct intel_display_error_state *
7107intel_display_capture_error_state(struct drm_device *dev)
7108{
0206e353 7109 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7110 struct intel_display_error_state *error;
7111 int i;
7112
7113 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7114 if (error == NULL)
7115 return NULL;
7116
7117 for (i = 0; i < 2; i++) {
7118 error->cursor[i].control = I915_READ(CURCNTR(i));
7119 error->cursor[i].position = I915_READ(CURPOS(i));
7120 error->cursor[i].base = I915_READ(CURBASE(i));
7121
7122 error->plane[i].control = I915_READ(DSPCNTR(i));
7123 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7124 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7125 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7126 error->plane[i].addr = I915_READ(DSPADDR(i));
7127 if (INTEL_INFO(dev)->gen >= 4) {
7128 error->plane[i].surface = I915_READ(DSPSURF(i));
7129 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7130 }
7131
7132 error->pipe[i].conf = I915_READ(PIPECONF(i));
7133 error->pipe[i].source = I915_READ(PIPESRC(i));
7134 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7135 error->pipe[i].hblank = I915_READ(HBLANK(i));
7136 error->pipe[i].hsync = I915_READ(HSYNC(i));
7137 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7138 error->pipe[i].vblank = I915_READ(VBLANK(i));
7139 error->pipe[i].vsync = I915_READ(VSYNC(i));
7140 }
7141
7142 return error;
7143}
7144
7145void
7146intel_display_print_error_state(struct seq_file *m,
7147 struct drm_device *dev,
7148 struct intel_display_error_state *error)
7149{
7150 int i;
7151
7152 for (i = 0; i < 2; i++) {
7153 seq_printf(m, "Pipe [%d]:\n", i);
7154 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7155 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7156 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7157 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7158 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7159 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7160 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7161 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7162
7163 seq_printf(m, "Plane [%d]:\n", i);
7164 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7165 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7166 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7167 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7168 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7169 if (INTEL_INFO(dev)->gen >= 4) {
7170 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7171 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7172 }
7173
7174 seq_printf(m, "Cursor [%d]:\n", i);
7175 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7176 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7177 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7178 }
7179}
7180#endif
kernel source for telekom puls (alcatel/mediatek)