UAPI: (Scripted) Convert #include "..." to #include <path/...> in drivers/gpu/
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / intel_crt.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
8ca4013d 27#include <linux/dmi.h>
79e53945 28#include <linux/i2c.h>
5a0e3ad6 29#include <linux/slab.h>
760285e7
DH
30#include <drm/drmP.h>
31#include <drm/drm_crtc.h>
32#include <drm/drm_crtc_helper.h>
33#include <drm/drm_edid.h>
79e53945 34#include "intel_drv.h"
760285e7 35#include <drm/i915_drm.h>
79e53945
JB
36#include "i915_drv.h"
37
e7dbb2f2
KP
38/* Here's the desired hotplug mode */
39#define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \
40 ADPA_CRT_HOTPLUG_WARMUP_10MS | \
41 ADPA_CRT_HOTPLUG_SAMPLE_4S | \
42 ADPA_CRT_HOTPLUG_VOLTAGE_50 | \
43 ADPA_CRT_HOTPLUG_VOLREF_325MV | \
44 ADPA_CRT_HOTPLUG_ENABLE)
45
c9a1c4cd
CW
46struct intel_crt {
47 struct intel_encoder base;
e7dbb2f2 48 bool force_hotplug_required;
c9a1c4cd
CW
49};
50
51static struct intel_crt *intel_attached_crt(struct drm_connector *connector)
52{
53 return container_of(intel_attached_encoder(connector),
54 struct intel_crt, base);
55}
56
df0323c4 57static void pch_crt_dpms(struct drm_encoder *encoder, int mode)
79e53945
JB
58{
59 struct drm_device *dev = encoder->dev;
60 struct drm_i915_private *dev_priv = dev->dev_private;
df0323c4 61 u32 temp;
79e53945 62
df0323c4
JB
63 temp = I915_READ(PCH_ADPA);
64 temp &= ~ADPA_DAC_ENABLE;
65
66 switch (mode) {
67 case DRM_MODE_DPMS_ON:
68 temp |= ADPA_DAC_ENABLE;
69 break;
70 case DRM_MODE_DPMS_STANDBY:
71 case DRM_MODE_DPMS_SUSPEND:
72 case DRM_MODE_DPMS_OFF:
73 /* Just leave port enable cleared */
74 break;
75 }
76
77 I915_WRITE(PCH_ADPA, temp);
78}
2c07245f 79
df0323c4
JB
80static void gmch_crt_dpms(struct drm_encoder *encoder, int mode)
81{
82 struct drm_device *dev = encoder->dev;
83 struct drm_i915_private *dev_priv = dev->dev_private;
84 u32 temp;
85
86 temp = I915_READ(ADPA);
79e53945 87 temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
febc7694 88 temp &= ~ADPA_DAC_ENABLE;
79e53945 89
bd9e8413
JB
90 if (IS_VALLEYVIEW(dev) && mode != DRM_MODE_DPMS_ON)
91 mode = DRM_MODE_DPMS_OFF;
92
0206e353 93 switch (mode) {
79e53945
JB
94 case DRM_MODE_DPMS_ON:
95 temp |= ADPA_DAC_ENABLE;
96 break;
97 case DRM_MODE_DPMS_STANDBY:
98 temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
99 break;
100 case DRM_MODE_DPMS_SUSPEND:
101 temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
102 break;
103 case DRM_MODE_DPMS_OFF:
104 temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
105 break;
106 }
107
df0323c4 108 I915_WRITE(ADPA, temp);
79e53945
JB
109}
110
111static int intel_crt_mode_valid(struct drm_connector *connector,
112 struct drm_display_mode *mode)
113{
6bcdcd9e
ZY
114 struct drm_device *dev = connector->dev;
115
116 int max_clock = 0;
79e53945
JB
117 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
118 return MODE_NO_DBLESCAN;
119
6bcdcd9e
ZY
120 if (mode->clock < 25000)
121 return MODE_CLOCK_LOW;
122
a6c45cf0 123 if (IS_GEN2(dev))
6bcdcd9e
ZY
124 max_clock = 350000;
125 else
126 max_clock = 400000;
127 if (mode->clock > max_clock)
128 return MODE_CLOCK_HIGH;
79e53945
JB
129
130 return MODE_OK;
131}
132
133static bool intel_crt_mode_fixup(struct drm_encoder *encoder,
e811f5ae 134 const struct drm_display_mode *mode,
79e53945
JB
135 struct drm_display_mode *adjusted_mode)
136{
137 return true;
138}
139
140static void intel_crt_mode_set(struct drm_encoder *encoder,
141 struct drm_display_mode *mode,
142 struct drm_display_mode *adjusted_mode)
143{
144
145 struct drm_device *dev = encoder->dev;
146 struct drm_crtc *crtc = encoder->crtc;
147 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 int dpll_md_reg;
150 u32 adpa, dpll_md;
2c07245f 151 u32 adpa_reg;
79e53945 152
9db4a9c7 153 dpll_md_reg = DPLL_MD(intel_crtc->pipe);
79e53945 154
bad720ff 155 if (HAS_PCH_SPLIT(dev))
2c07245f
ZW
156 adpa_reg = PCH_ADPA;
157 else
158 adpa_reg = ADPA;
159
79e53945
JB
160 /*
161 * Disable separate mode multiplier used when cloning SDVO to CRT
162 * XXX this needs to be adjusted when we really are cloning
163 */
a6c45cf0 164 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
79e53945
JB
165 dpll_md = I915_READ(dpll_md_reg);
166 I915_WRITE(dpll_md_reg,
167 dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
168 }
169
e7dbb2f2 170 adpa = ADPA_HOTPLUG_BITS;
79e53945
JB
171 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
172 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
173 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
174 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
175
75770564
JB
176 /* For CPT allow 3 pipe config, for others just use A or B */
177 if (HAS_PCH_CPT(dev))
178 adpa |= PORT_TRANS_SEL_CPT(intel_crtc->pipe);
179 else if (intel_crtc->pipe == 0)
180 adpa |= ADPA_PIPE_A_SELECT;
181 else
182 adpa |= ADPA_PIPE_B_SELECT;
79e53945 183
9db4a9c7
JB
184 if (!HAS_PCH_SPLIT(dev))
185 I915_WRITE(BCLRPAT(intel_crtc->pipe), 0);
186
2c07245f
ZW
187 I915_WRITE(adpa_reg, adpa);
188}
189
f2b115e6 190static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector)
2c07245f
ZW
191{
192 struct drm_device *dev = connector->dev;
e7dbb2f2 193 struct intel_crt *crt = intel_attached_crt(connector);
2c07245f 194 struct drm_i915_private *dev_priv = dev->dev_private;
e7dbb2f2 195 u32 adpa;
2c07245f
ZW
196 bool ret;
197
e7dbb2f2
KP
198 /* The first time through, trigger an explicit detection cycle */
199 if (crt->force_hotplug_required) {
200 bool turn_off_dac = HAS_PCH_SPLIT(dev);
201 u32 save_adpa;
67941da2 202
e7dbb2f2
KP
203 crt->force_hotplug_required = 0;
204
205 save_adpa = adpa = I915_READ(PCH_ADPA);
206 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
207
208 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
209 if (turn_off_dac)
210 adpa &= ~ADPA_DAC_ENABLE;
211
212 I915_WRITE(PCH_ADPA, adpa);
213
214 if (wait_for((I915_READ(PCH_ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
215 1000))
216 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
217
218 if (turn_off_dac) {
219 I915_WRITE(PCH_ADPA, save_adpa);
220 POSTING_READ(PCH_ADPA);
221 }
a4a6b901
ZW
222 }
223
2c07245f
ZW
224 /* Check the status to see if both blue and green are on now */
225 adpa = I915_READ(PCH_ADPA);
e7dbb2f2 226 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
2c07245f
ZW
227 ret = true;
228 else
229 ret = false;
e7dbb2f2 230 DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret);
2c07245f 231
2c07245f 232 return ret;
79e53945
JB
233}
234
7d2c24e8
JB
235static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
236{
237 struct drm_device *dev = connector->dev;
238 struct drm_i915_private *dev_priv = dev->dev_private;
239 u32 adpa;
240 bool ret;
241 u32 save_adpa;
242
243 save_adpa = adpa = I915_READ(ADPA);
244 DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa);
245
246 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
247
248 I915_WRITE(ADPA, adpa);
249
250 if (wait_for((I915_READ(ADPA) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0,
251 1000)) {
252 DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER");
253 I915_WRITE(ADPA, save_adpa);
254 }
255
256 /* Check the status to see if both blue and green are on now */
257 adpa = I915_READ(ADPA);
258 if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
259 ret = true;
260 else
261 ret = false;
262
263 DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
264
265 /* FIXME: debug force function and remove */
266 ret = true;
267
268 return ret;
269}
270
79e53945
JB
271/**
272 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
273 *
274 * Not for i915G/i915GM
275 *
276 * \return true if CRT is connected.
277 * \return false if CRT is disconnected.
278 */
279static bool intel_crt_detect_hotplug(struct drm_connector *connector)
280{
281 struct drm_device *dev = connector->dev;
282 struct drm_i915_private *dev_priv = dev->dev_private;
7a772c49
AJ
283 u32 hotplug_en, orig, stat;
284 bool ret = false;
771cb081 285 int i, tries = 0;
2c07245f 286
bad720ff 287 if (HAS_PCH_SPLIT(dev))
f2b115e6 288 return intel_ironlake_crt_detect_hotplug(connector);
2c07245f 289
7d2c24e8
JB
290 if (IS_VALLEYVIEW(dev))
291 return valleyview_crt_detect_hotplug(connector);
292
771cb081
ZY
293 /*
294 * On 4 series desktop, CRT detect sequence need to be done twice
295 * to get a reliable result.
296 */
79e53945 297
771cb081
ZY
298 if (IS_G4X(dev) && !IS_GM45(dev))
299 tries = 2;
300 else
301 tries = 1;
7a772c49 302 hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN);
771cb081
ZY
303 hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
304
771cb081 305 for (i = 0; i < tries ; i++) {
771cb081
ZY
306 /* turn on the FORCE_DETECT */
307 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
771cb081 308 /* wait for FORCE_DETECT to go off */
913d8d11
CW
309 if (wait_for((I915_READ(PORT_HOTPLUG_EN) &
310 CRT_HOTPLUG_FORCE_DETECT) == 0,
481b6af3 311 1000))
79077319 312 DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off");
771cb081 313 }
79e53945 314
7a772c49
AJ
315 stat = I915_READ(PORT_HOTPLUG_STAT);
316 if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
317 ret = true;
318
319 /* clear the interrupt we just generated, if any */
320 I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
79e53945 321
7a772c49
AJ
322 /* and put the bits back */
323 I915_WRITE(PORT_HOTPLUG_EN, orig);
324
325 return ret;
79e53945
JB
326}
327
f1a2f5b7
JN
328static struct edid *intel_crt_get_edid(struct drm_connector *connector,
329 struct i2c_adapter *i2c)
330{
331 struct edid *edid;
332
333 edid = drm_get_edid(connector, i2c);
334
335 if (!edid && !intel_gmbus_is_forced_bit(i2c)) {
336 DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
337 intel_gmbus_force_bit(i2c, true);
338 edid = drm_get_edid(connector, i2c);
339 intel_gmbus_force_bit(i2c, false);
340 }
341
342 return edid;
343}
344
345/* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
346static int intel_crt_ddc_get_modes(struct drm_connector *connector,
347 struct i2c_adapter *adapter)
348{
349 struct edid *edid;
350
351 edid = intel_crt_get_edid(connector, adapter);
352 if (!edid)
353 return 0;
354
355 return intel_connector_update_modes(connector, edid);
356}
357
f5afcd3d 358static bool intel_crt_detect_ddc(struct drm_connector *connector)
79e53945 359{
f5afcd3d 360 struct intel_crt *crt = intel_attached_crt(connector);
c9a1c4cd 361 struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private;
a2bd1f54
DV
362 struct edid *edid;
363 struct i2c_adapter *i2c;
79e53945 364
a2bd1f54 365 BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG);
79e53945 366
a2bd1f54 367 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
f1a2f5b7 368 edid = intel_crt_get_edid(connector, i2c);
a2bd1f54
DV
369
370 if (edid) {
371 bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL;
f5afcd3d 372
f5afcd3d
DM
373 /*
374 * This may be a DVI-I connector with a shared DDC
375 * link between analog and digital outputs, so we
376 * have to check the EDID input spec of the attached device.
377 */
f5afcd3d
DM
378 if (!is_digital) {
379 DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n");
380 return true;
381 }
a2bd1f54
DV
382
383 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
384 } else {
385 DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n");
6ec3d0c0
CW
386 }
387
a2bd1f54
DV
388 kfree(edid);
389
6ec3d0c0 390 return false;
79e53945
JB
391}
392
e4a5d54f 393static enum drm_connector_status
7173188d 394intel_crt_load_detect(struct intel_crt *crt)
e4a5d54f 395{
7173188d 396 struct drm_device *dev = crt->base.base.dev;
e4a5d54f 397 struct drm_i915_private *dev_priv = dev->dev_private;
7173188d 398 uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
e4a5d54f
ML
399 uint32_t save_bclrpat;
400 uint32_t save_vtotal;
401 uint32_t vtotal, vactive;
402 uint32_t vsample;
403 uint32_t vblank, vblank_start, vblank_end;
404 uint32_t dsl;
405 uint32_t bclrpat_reg;
406 uint32_t vtotal_reg;
407 uint32_t vblank_reg;
408 uint32_t vsync_reg;
409 uint32_t pipeconf_reg;
410 uint32_t pipe_dsl_reg;
411 uint8_t st00;
412 enum drm_connector_status status;
413
6ec3d0c0
CW
414 DRM_DEBUG_KMS("starting load-detect on CRT\n");
415
9db4a9c7
JB
416 bclrpat_reg = BCLRPAT(pipe);
417 vtotal_reg = VTOTAL(pipe);
418 vblank_reg = VBLANK(pipe);
419 vsync_reg = VSYNC(pipe);
420 pipeconf_reg = PIPECONF(pipe);
421 pipe_dsl_reg = PIPEDSL(pipe);
e4a5d54f
ML
422
423 save_bclrpat = I915_READ(bclrpat_reg);
424 save_vtotal = I915_READ(vtotal_reg);
425 vblank = I915_READ(vblank_reg);
426
427 vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
428 vactive = (save_vtotal & 0x7ff) + 1;
429
430 vblank_start = (vblank & 0xfff) + 1;
431 vblank_end = ((vblank >> 16) & 0xfff) + 1;
432
433 /* Set the border color to purple. */
434 I915_WRITE(bclrpat_reg, 0x500050);
435
a6c45cf0 436 if (!IS_GEN2(dev)) {
e4a5d54f
ML
437 uint32_t pipeconf = I915_READ(pipeconf_reg);
438 I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
19c55da1 439 POSTING_READ(pipeconf_reg);
e4a5d54f
ML
440 /* Wait for next Vblank to substitue
441 * border color for Color info */
9d0498a2 442 intel_wait_for_vblank(dev, pipe);
e4a5d54f
ML
443 st00 = I915_READ8(VGA_MSR_WRITE);
444 status = ((st00 & (1 << 4)) != 0) ?
445 connector_status_connected :
446 connector_status_disconnected;
447
448 I915_WRITE(pipeconf_reg, pipeconf);
449 } else {
450 bool restore_vblank = false;
451 int count, detect;
452
453 /*
454 * If there isn't any border, add some.
455 * Yes, this will flicker
456 */
457 if (vblank_start <= vactive && vblank_end >= vtotal) {
458 uint32_t vsync = I915_READ(vsync_reg);
459 uint32_t vsync_start = (vsync & 0xffff) + 1;
460
461 vblank_start = vsync_start;
462 I915_WRITE(vblank_reg,
463 (vblank_start - 1) |
464 ((vblank_end - 1) << 16));
465 restore_vblank = true;
466 }
467 /* sample in the vertical border, selecting the larger one */
468 if (vblank_start - vactive >= vtotal - vblank_end)
469 vsample = (vblank_start + vactive) >> 1;
470 else
471 vsample = (vtotal + vblank_end) >> 1;
472
473 /*
474 * Wait for the border to be displayed
475 */
476 while (I915_READ(pipe_dsl_reg) >= vactive)
477 ;
478 while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample)
479 ;
480 /*
481 * Watch ST00 for an entire scanline
482 */
483 detect = 0;
484 count = 0;
485 do {
486 count++;
487 /* Read the ST00 VGA status register */
488 st00 = I915_READ8(VGA_MSR_WRITE);
489 if (st00 & (1 << 4))
490 detect++;
491 } while ((I915_READ(pipe_dsl_reg) == dsl));
492
493 /* restore vblank if necessary */
494 if (restore_vblank)
495 I915_WRITE(vblank_reg, vblank);
496 /*
497 * If more than 3/4 of the scanline detected a monitor,
498 * then it is assumed to be present. This works even on i830,
499 * where there isn't any way to force the border color across
500 * the screen
501 */
502 status = detect * 4 > count * 3 ?
503 connector_status_connected :
504 connector_status_disconnected;
505 }
506
507 /* Restore previous settings */
508 I915_WRITE(bclrpat_reg, save_bclrpat);
509
510 return status;
511}
512
7b334fcb 513static enum drm_connector_status
930a9e28 514intel_crt_detect(struct drm_connector *connector, bool force)
79e53945
JB
515{
516 struct drm_device *dev = connector->dev;
c9a1c4cd 517 struct intel_crt *crt = intel_attached_crt(connector);
e4a5d54f 518 enum drm_connector_status status;
e95c8438 519 struct intel_load_detect_pipe tmp;
79e53945 520
a6c45cf0 521 if (I915_HAS_HOTPLUG(dev)) {
aaa37730
DV
522 /* We can not rely on the HPD pin always being correctly wired
523 * up, for example many KVM do not pass it through, and so
524 * only trust an assertion that the monitor is connected.
525 */
6ec3d0c0
CW
526 if (intel_crt_detect_hotplug(connector)) {
527 DRM_DEBUG_KMS("CRT detected via hotplug\n");
79e53945 528 return connector_status_connected;
aaa37730 529 } else
e7dbb2f2 530 DRM_DEBUG_KMS("CRT not detected via hotplug\n");
79e53945
JB
531 }
532
f5afcd3d 533 if (intel_crt_detect_ddc(connector))
79e53945
JB
534 return connector_status_connected;
535
aaa37730
DV
536 /* Load detection is broken on HPD capable machines. Whoever wants a
537 * broken monitor (without edid) to work behind a broken kvm (that fails
538 * to have the right resistors for HP detection) needs to fix this up.
539 * For now just bail out. */
540 if (I915_HAS_HOTPLUG(dev))
541 return connector_status_disconnected;
542
930a9e28 543 if (!force)
7b334fcb
CW
544 return connector->status;
545
e4a5d54f 546 /* for pre-945g platforms use load detect */
e95c8438
DV
547 if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
548 &tmp)) {
549 if (intel_crt_detect_ddc(connector))
550 status = connector_status_connected;
551 else
552 status = intel_crt_load_detect(crt);
553 intel_release_load_detect_pipe(&crt->base, connector,
554 &tmp);
555 } else
556 status = connector_status_unknown;
e4a5d54f
ML
557
558 return status;
79e53945
JB
559}
560
561static void intel_crt_destroy(struct drm_connector *connector)
562{
79e53945
JB
563 drm_sysfs_connector_remove(connector);
564 drm_connector_cleanup(connector);
565 kfree(connector);
566}
567
568static int intel_crt_get_modes(struct drm_connector *connector)
569{
8e4d36b9 570 struct drm_device *dev = connector->dev;
f899fc64 571 struct drm_i915_private *dev_priv = dev->dev_private;
890f3359 572 int ret;
3bd7d909 573 struct i2c_adapter *i2c;
8e4d36b9 574
3bd7d909 575 i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->crt_ddc_pin);
f1a2f5b7 576 ret = intel_crt_ddc_get_modes(connector, i2c);
8e4d36b9 577 if (ret || !IS_G4X(dev))
f899fc64 578 return ret;
8e4d36b9 579
8e4d36b9 580 /* Try to probe digital port for output in DVI-I -> VGA mode. */
3bd7d909 581 i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB);
f1a2f5b7 582 return intel_crt_ddc_get_modes(connector, i2c);
79e53945
JB
583}
584
585static int intel_crt_set_property(struct drm_connector *connector,
586 struct drm_property *property,
587 uint64_t value)
588{
79e53945
JB
589 return 0;
590}
591
f3269058
CW
592static void intel_crt_reset(struct drm_connector *connector)
593{
594 struct drm_device *dev = connector->dev;
595 struct intel_crt *crt = intel_attached_crt(connector);
596
597 if (HAS_PCH_SPLIT(dev))
598 crt->force_hotplug_required = 1;
599}
600
79e53945
JB
601/*
602 * Routines for controlling stuff on the analog port
603 */
604
df0323c4
JB
605static const struct drm_encoder_helper_funcs pch_encoder_funcs = {
606 .mode_fixup = intel_crt_mode_fixup,
607 .prepare = intel_encoder_prepare,
608 .commit = intel_encoder_commit,
609 .mode_set = intel_crt_mode_set,
610 .dpms = pch_crt_dpms,
611};
612
613static const struct drm_encoder_helper_funcs gmch_encoder_funcs = {
79e53945
JB
614 .mode_fixup = intel_crt_mode_fixup,
615 .prepare = intel_encoder_prepare,
616 .commit = intel_encoder_commit,
617 .mode_set = intel_crt_mode_set,
df0323c4 618 .dpms = gmch_crt_dpms,
79e53945
JB
619};
620
621static const struct drm_connector_funcs intel_crt_connector_funcs = {
f3269058 622 .reset = intel_crt_reset,
c9fb15f6 623 .dpms = drm_helper_connector_dpms,
79e53945
JB
624 .detect = intel_crt_detect,
625 .fill_modes = drm_helper_probe_single_connector_modes,
626 .destroy = intel_crt_destroy,
627 .set_property = intel_crt_set_property,
628};
629
630static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
631 .mode_valid = intel_crt_mode_valid,
632 .get_modes = intel_crt_get_modes,
df0e9248 633 .best_encoder = intel_best_encoder,
79e53945
JB
634};
635
79e53945 636static const struct drm_encoder_funcs intel_crt_enc_funcs = {
ea5b213a 637 .destroy = intel_encoder_destroy,
79e53945
JB
638};
639
8ca4013d
DL
640static int __init intel_no_crt_dmi_callback(const struct dmi_system_id *id)
641{
bc0daf48 642 DRM_INFO("Skipping CRT initialization for %s\n", id->ident);
8ca4013d
DL
643 return 1;
644}
645
646static const struct dmi_system_id intel_no_crt[] = {
647 {
648 .callback = intel_no_crt_dmi_callback,
649 .ident = "ACER ZGB",
650 .matches = {
651 DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
652 DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
653 },
654 },
655 { }
656};
657
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JB
658void intel_crt_init(struct drm_device *dev)
659{
660 struct drm_connector *connector;
c9a1c4cd 661 struct intel_crt *crt;
454c1ca8 662 struct intel_connector *intel_connector;
db545019 663 struct drm_i915_private *dev_priv = dev->dev_private;
df0323c4 664 const struct drm_encoder_helper_funcs *encoder_helper_funcs;
79e53945 665
8ca4013d
DL
666 /* Skip machines without VGA that falsely report hotplug events */
667 if (dmi_check_system(intel_no_crt))
668 return;
669
c9a1c4cd
CW
670 crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
671 if (!crt)
79e53945
JB
672 return;
673
454c1ca8
ZW
674 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
675 if (!intel_connector) {
c9a1c4cd 676 kfree(crt);
454c1ca8
ZW
677 return;
678 }
679
680 connector = &intel_connector->base;
681 drm_connector_init(dev, &intel_connector->base,
79e53945
JB
682 &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
683
c9a1c4cd 684 drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs,
79e53945
JB
685 DRM_MODE_ENCODER_DAC);
686
c9a1c4cd 687 intel_connector_attach_encoder(intel_connector, &crt->base);
79e53945 688
c9a1c4cd
CW
689 crt->base.type = INTEL_OUTPUT_ANALOG;
690 crt->base.clone_mask = (1 << INTEL_SDVO_NON_TV_CLONE_BIT |
691 1 << INTEL_ANALOG_CLONE_BIT |
692 1 << INTEL_SDVO_LVDS_CLONE_BIT);
59c859d6
ED
693 if (IS_HASWELL(dev))
694 crt->base.crtc_mask = (1 << 0);
695 else
696 crt->base.crtc_mask = (1 << 0) | (1 << 1);
697
dbb02575
DV
698 if (IS_GEN2(dev))
699 connector->interlace_allowed = 0;
700 else
701 connector->interlace_allowed = 1;
79e53945
JB
702 connector->doublescan_allowed = 0;
703
df0323c4
JB
704 if (HAS_PCH_SPLIT(dev))
705 encoder_helper_funcs = &pch_encoder_funcs;
706 else
707 encoder_helper_funcs = &gmch_encoder_funcs;
708
709 drm_encoder_helper_add(&crt->base.base, encoder_helper_funcs);
79e53945
JB
710 drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
711
712 drm_sysfs_connector_add(connector);
b01f2c3a 713
eb1f8e4f
DA
714 if (I915_HAS_HOTPLUG(dev))
715 connector->polled = DRM_CONNECTOR_POLL_HPD;
716 else
717 connector->polled = DRM_CONNECTOR_POLL_CONNECT;
718
e7dbb2f2
KP
719 /*
720 * Configure the automatic hotplug detection stuff
721 */
722 crt->force_hotplug_required = 0;
723 if (HAS_PCH_SPLIT(dev)) {
724 u32 adpa;
725
726 adpa = I915_READ(PCH_ADPA);
727 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
728 adpa |= ADPA_HOTPLUG_BITS;
729 I915_WRITE(PCH_ADPA, adpa);
730 POSTING_READ(PCH_ADPA);
731
732 DRM_DEBUG_KMS("pch crt adpa set to 0x%x\n", adpa);
733 crt->force_hotplug_required = 1;
734 }
735
b01f2c3a 736 dev_priv->hotplug_supported_mask |= CRT_HOTPLUG_INT_STATUS;
79e53945 737}