[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / gpu / drm / i915 / i915_pvinfo.h

/*
 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef _I915_PVINFO_H_
#define _I915_PVINFO_H_

/* The MMIO offset of the shared info between guest and host emulator */
#define VGT_PVINFO_PAGE	0x78000
#define VGT_PVINFO_SIZE	0x1000

/*
 * The following structure pages are defined in GEN MMIO space
 * for virtualization. (One page for now)
 */
#define VGT_MAGIC         0x4776544776544776ULL	/* 'vGTvGTvG' */
#define VGT_VERSION_MAJOR 1
#define VGT_VERSION_MINOR 0

/*
 * notifications from guest to vgpu device model
 */
enum vgt_g2v_type {
	VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
	VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
	VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
	VGT_G2V_EXECLIST_CONTEXT_CREATE,
	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
	VGT_G2V_MAX,
};

struct vgt_if {
	u64 magic;		/* VGT_MAGIC */
	u16 version_major;
	u16 version_minor;
	u32 vgt_id;		/* ID of vGT instance */
	u32 rsv1[12];		/* pad to offset 0x40 */
	/*
	 *  Data structure to describe the balooning info of resources.
	 *  Each VM can only have one portion of continuous area for now.
	 *  (May support scattered resource in future)
	 *  (starting from offset 0x40)
	 */
	struct {
		/* Aperture register balooning */
		struct {
			u32 base;
			u32 size;
		} mappable_gmadr;	/* aperture */
		/* GMADR register balooning */
		struct {
			u32 base;
			u32 size;
		} nonmappable_gmadr;	/* non aperture */
		/* allowed fence registers */
		u32 fence_num;
		u32 rsv2[3];
	} avail_rs;		/* available/assigned resource */
	u32 rsv3[0x200 - 24];	/* pad to half page */
	/*
	 * The bottom half page is for response from Gfx driver to hypervisor.
	 */
	u32 rsv4;
	u32 display_ready;	/* ready for display owner switch */

	u32 rsv5[4];

	u32 g2v_notify;
	u32 rsv6[7];

	struct {
		u32 lo;
		u32 hi;
	} pdp[4];

	u32 execlist_context_descriptor_lo;
	u32 execlist_context_descriptor_hi;

	u32  rsv7[0x200 - 24];    /* pad to one page */
} __packed;

#define vgtif_reg(x) \
	_MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))

/* vGPU display status to be used by the host side */
#define VGT_DRV_DISPLAY_NOT_READY 0
#define VGT_DRV_DISPLAY_READY     1  /* ready for display switch */

#endif /* _I915_PVINFO_H_ */
Commit	Line	Data
87da603c ZW	1	/*
	2	* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining a
	5	* copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice (including the next
	12	* paragraph) shall be included in all copies or substantial portions of the
	13	* Software.
	14	*
	15	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	16	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	17	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	18	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	19	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	20	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	21	* SOFTWARE.
	22	*/
	23
	24	#ifndef _I915_PVINFO_H_
	25	#define _I915_PVINFO_H_
	26
	27	/* The MMIO offset of the shared info between guest and host emulator */
	28	#define VGT_PVINFO_PAGE 0x78000
	29	#define VGT_PVINFO_SIZE 0x1000
	30
	31	/*
	32	* The following structure pages are defined in GEN MMIO space
	33	* for virtualization. (One page for now)
	34	*/
	35	#define VGT_MAGIC 0x4776544776544776ULL /* 'vGTvGTvG' */
	36	#define VGT_VERSION_MAJOR 1
	37	#define VGT_VERSION_MINOR 0
	38
87da603c ZW	39	/*
	40	* notifications from guest to vgpu device model
	41	*/
	42	enum vgt_g2v_type {
	43	VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE = 2,
	44	VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY,
	45	VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE,
	46	VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY,
	47	VGT_G2V_EXECLIST_CONTEXT_CREATE,
	48	VGT_G2V_EXECLIST_CONTEXT_DESTROY,
	49	VGT_G2V_MAX,
	50	};
	51
	52	struct vgt_if {
	53	u64 magic; /* VGT_MAGIC */
c380f681 ZW	54	u16 version_major;
c380f681 ZW	55	u16 version_minor;
87da603c ZW	56	u32 vgt_id; /* ID of vGT instance */
	57	u32 rsv1[12]; /* pad to offset 0x40 */
	58	/*
	59	* Data structure to describe the balooning info of resources.
	60	* Each VM can only have one portion of continuous area for now.
	61	* (May support scattered resource in future)
	62	* (starting from offset 0x40)
	63	*/
	64	struct {
	65	/* Aperture register balooning */
	66	struct {
	67	u32 base;
	68	u32 size;
	69	} mappable_gmadr; /* aperture */
	70	/* GMADR register balooning */
	71	struct {
	72	u32 base;
	73	u32 size;
	74	} nonmappable_gmadr; /* non aperture */
	75	/* allowed fence registers */
	76	u32 fence_num;
	77	u32 rsv2[3];
	78	} avail_rs; /* available/assigned resource */
	79	u32 rsv3[0x200 - 24]; /* pad to half page */
	80	/*
	81	* The bottom half page is for response from Gfx driver to hypervisor.
	82	*/
	83	u32 rsv4;
	84	u32 display_ready; /* ready for display owner switch */
	85
	86	u32 rsv5[4];
	87
	88	u32 g2v_notify;
	89	u32 rsv6[7];
	90
	91	struct {
	92	u32 lo;
	93	u32 hi;
	94	} pdp[4];
	95
	96	u32 execlist_context_descriptor_lo;
	97	u32 execlist_context_descriptor_hi;
	98
	99	u32 rsv7[0x200 - 24]; /* pad to one page */
	100	} __packed;
	101
	102	#define vgtif_reg(x) \
b2a5d1e7	103	_MMIO((VGT_PVINFO_PAGE + offsetof(struct vgt_if, x)))
87da603c ZW	104
	105	/* vGPU display status to be used by the host side */
	106	#define VGT_DRV_DISPLAY_NOT_READY 0
	107	#define VGT_DRV_DISPLAY_READY 1 /* ready for display switch */
	108
	109	#endif /* _I915_PVINFO_H_ */