Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | /* For display hotplug interrupt */ |
995b6762 | 68 | static void |
f2b115e6 | 69 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 70 | { |
1ec14ad3 CW |
71 | if ((dev_priv->irq_mask & mask) != 0) { |
72 | dev_priv->irq_mask &= ~mask; | |
73 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 74 | POSTING_READ(DEIMR); |
036a4a7d ZW |
75 | } |
76 | } | |
77 | ||
78 | static inline void | |
f2b115e6 | 79 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d | 80 | { |
1ec14ad3 CW |
81 | if ((dev_priv->irq_mask & mask) != mask) { |
82 | dev_priv->irq_mask |= mask; | |
83 | I915_WRITE(DEIMR, dev_priv->irq_mask); | |
3143a2bf | 84 | POSTING_READ(DEIMR); |
036a4a7d ZW |
85 | } |
86 | } | |
87 | ||
7c463586 KP |
88 | void |
89 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
90 | { | |
91 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
9db4a9c7 | 92 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
93 | |
94 | dev_priv->pipestat[pipe] |= mask; | |
95 | /* Enable the interrupt, clear any pending status */ | |
96 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 97 | POSTING_READ(reg); |
7c463586 KP |
98 | } |
99 | } | |
100 | ||
101 | void | |
102 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
103 | { | |
104 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
9db4a9c7 | 105 | u32 reg = PIPESTAT(pipe); |
7c463586 KP |
106 | |
107 | dev_priv->pipestat[pipe] &= ~mask; | |
108 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 109 | POSTING_READ(reg); |
7c463586 KP |
110 | } |
111 | } | |
112 | ||
01c66889 ZY |
113 | /** |
114 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
115 | */ | |
1ec14ad3 | 116 | void intel_enable_asle(struct drm_device *dev) |
01c66889 | 117 | { |
1ec14ad3 CW |
118 | drm_i915_private_t *dev_priv = dev->dev_private; |
119 | unsigned long irqflags; | |
120 | ||
121 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); | |
01c66889 | 122 | |
c619eed4 | 123 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 124 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 125 | else { |
01c66889 | 126 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 127 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 128 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 129 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 130 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 131 | } |
1ec14ad3 CW |
132 | |
133 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); | |
01c66889 ZY |
134 | } |
135 | ||
0a3e67a4 JB |
136 | /** |
137 | * i915_pipe_enabled - check if a pipe is enabled | |
138 | * @dev: DRM device | |
139 | * @pipe: pipe to check | |
140 | * | |
141 | * Reading certain registers when the pipe is disabled can hang the chip. | |
142 | * Use this routine to make sure the PLL is running and the pipe is active | |
143 | * before reading such registers if unsure. | |
144 | */ | |
145 | static int | |
146 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
147 | { | |
148 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 149 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
150 | } |
151 | ||
42f52ef8 KP |
152 | /* Called from drm generic code, passed a 'crtc', which |
153 | * we use as a pipe index | |
154 | */ | |
155 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
156 | { |
157 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
158 | unsigned long high_frame; | |
159 | unsigned long low_frame; | |
5eddb70b | 160 | u32 high1, high2, low; |
0a3e67a4 JB |
161 | |
162 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 163 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 164 | "pipe %c\n", pipe_name(pipe)); |
0a3e67a4 JB |
165 | return 0; |
166 | } | |
167 | ||
9db4a9c7 JB |
168 | high_frame = PIPEFRAME(pipe); |
169 | low_frame = PIPEFRAMEPIXEL(pipe); | |
5eddb70b | 170 | |
0a3e67a4 JB |
171 | /* |
172 | * High & low register fields aren't synchronized, so make sure | |
173 | * we get a low value that's stable across two reads of the high | |
174 | * register. | |
175 | */ | |
176 | do { | |
5eddb70b CW |
177 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
178 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
179 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
180 | } while (high1 != high2); |
181 | ||
5eddb70b CW |
182 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
183 | low >>= PIPE_FRAME_LOW_SHIFT; | |
184 | return (high1 << 8) | low; | |
0a3e67a4 JB |
185 | } |
186 | ||
9880b7a5 JB |
187 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
188 | { | |
189 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 190 | int reg = PIPE_FRMCOUNT_GM45(pipe); |
9880b7a5 JB |
191 | |
192 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 | 193 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
9db4a9c7 | 194 | "pipe %c\n", pipe_name(pipe)); |
9880b7a5 JB |
195 | return 0; |
196 | } | |
197 | ||
198 | return I915_READ(reg); | |
199 | } | |
200 | ||
0af7e4df MK |
201 | int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, |
202 | int *vpos, int *hpos) | |
203 | { | |
204 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
205 | u32 vbl = 0, position = 0; | |
206 | int vbl_start, vbl_end, htotal, vtotal; | |
207 | bool in_vbl = true; | |
208 | int ret = 0; | |
209 | ||
210 | if (!i915_pipe_enabled(dev, pipe)) { | |
211 | DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled " | |
9db4a9c7 | 212 | "pipe %c\n", pipe_name(pipe)); |
0af7e4df MK |
213 | return 0; |
214 | } | |
215 | ||
216 | /* Get vtotal. */ | |
217 | vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff); | |
218 | ||
219 | if (INTEL_INFO(dev)->gen >= 4) { | |
220 | /* No obvious pixelcount register. Only query vertical | |
221 | * scanout position from Display scan line register. | |
222 | */ | |
223 | position = I915_READ(PIPEDSL(pipe)); | |
224 | ||
225 | /* Decode into vertical scanout position. Don't have | |
226 | * horizontal scanout position. | |
227 | */ | |
228 | *vpos = position & 0x1fff; | |
229 | *hpos = 0; | |
230 | } else { | |
231 | /* Have access to pixelcount since start of frame. | |
232 | * We can split this into vertical and horizontal | |
233 | * scanout position. | |
234 | */ | |
235 | position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT; | |
236 | ||
237 | htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff); | |
238 | *vpos = position / htotal; | |
239 | *hpos = position - (*vpos * htotal); | |
240 | } | |
241 | ||
242 | /* Query vblank area. */ | |
243 | vbl = I915_READ(VBLANK(pipe)); | |
244 | ||
245 | /* Test position against vblank region. */ | |
246 | vbl_start = vbl & 0x1fff; | |
247 | vbl_end = (vbl >> 16) & 0x1fff; | |
248 | ||
249 | if ((*vpos < vbl_start) || (*vpos > vbl_end)) | |
250 | in_vbl = false; | |
251 | ||
252 | /* Inside "upper part" of vblank area? Apply corrective offset: */ | |
253 | if (in_vbl && (*vpos >= vbl_start)) | |
254 | *vpos = *vpos - vtotal; | |
255 | ||
256 | /* Readouts valid? */ | |
257 | if (vbl > 0) | |
258 | ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE; | |
259 | ||
260 | /* In vblank? */ | |
261 | if (in_vbl) | |
262 | ret |= DRM_SCANOUTPOS_INVBL; | |
263 | ||
264 | return ret; | |
265 | } | |
266 | ||
4041b853 | 267 | int i915_get_vblank_timestamp(struct drm_device *dev, int pipe, |
0af7e4df MK |
268 | int *max_error, |
269 | struct timeval *vblank_time, | |
270 | unsigned flags) | |
271 | { | |
4041b853 CW |
272 | struct drm_i915_private *dev_priv = dev->dev_private; |
273 | struct drm_crtc *crtc; | |
0af7e4df | 274 | |
4041b853 CW |
275 | if (pipe < 0 || pipe >= dev_priv->num_pipe) { |
276 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
0af7e4df MK |
277 | return -EINVAL; |
278 | } | |
279 | ||
280 | /* Get drm_crtc to timestamp: */ | |
4041b853 CW |
281 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
282 | if (crtc == NULL) { | |
283 | DRM_ERROR("Invalid crtc %d\n", pipe); | |
284 | return -EINVAL; | |
285 | } | |
286 | ||
287 | if (!crtc->enabled) { | |
288 | DRM_DEBUG_KMS("crtc %d is disabled\n", pipe); | |
289 | return -EBUSY; | |
290 | } | |
0af7e4df MK |
291 | |
292 | /* Helper routine in DRM core does all the work: */ | |
4041b853 CW |
293 | return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, |
294 | vblank_time, flags, | |
295 | crtc); | |
0af7e4df MK |
296 | } |
297 | ||
5ca58282 JB |
298 | /* |
299 | * Handle hotplug events outside the interrupt handler proper. | |
300 | */ | |
301 | static void i915_hotplug_work_func(struct work_struct *work) | |
302 | { | |
303 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
304 | hotplug_work); | |
305 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 306 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
307 | struct intel_encoder *encoder; |
308 | ||
309 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
310 | if (encoder->hot_plug) | |
311 | encoder->hot_plug(encoder); | |
312 | ||
5ca58282 | 313 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 314 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
315 | } |
316 | ||
f97108d1 JB |
317 | static void i915_handle_rps_change(struct drm_device *dev) |
318 | { | |
319 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 320 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
321 | u8 new_delay = dev_priv->cur_delay; |
322 | ||
7648fa99 | 323 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
324 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
325 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
326 | max_avg = I915_READ(RCBMAXAVG); |
327 | min_avg = I915_READ(RCBMINAVG); | |
328 | ||
329 | /* Handle RCS change request from hw */ | |
b5b72e89 | 330 | if (busy_up > max_avg) { |
f97108d1 JB |
331 | if (dev_priv->cur_delay != dev_priv->max_delay) |
332 | new_delay = dev_priv->cur_delay - 1; | |
333 | if (new_delay < dev_priv->max_delay) | |
334 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 335 | } else if (busy_down < min_avg) { |
f97108d1 JB |
336 | if (dev_priv->cur_delay != dev_priv->min_delay) |
337 | new_delay = dev_priv->cur_delay + 1; | |
338 | if (new_delay > dev_priv->min_delay) | |
339 | new_delay = dev_priv->min_delay; | |
340 | } | |
341 | ||
7648fa99 JB |
342 | if (ironlake_set_drps(dev, new_delay)) |
343 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
344 | |
345 | return; | |
346 | } | |
347 | ||
549f7365 CW |
348 | static void notify_ring(struct drm_device *dev, |
349 | struct intel_ring_buffer *ring) | |
350 | { | |
351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
475553de | 352 | u32 seqno; |
9862e600 | 353 | |
475553de CW |
354 | if (ring->obj == NULL) |
355 | return; | |
356 | ||
357 | seqno = ring->get_seqno(ring); | |
db53a302 | 358 | trace_i915_gem_request_complete(ring, seqno); |
9862e600 CW |
359 | |
360 | ring->irq_seqno = seqno; | |
549f7365 | 361 | wake_up_all(&ring->irq_queue); |
9862e600 | 362 | |
549f7365 CW |
363 | dev_priv->hangcheck_count = 0; |
364 | mod_timer(&dev_priv->hangcheck_timer, | |
365 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
366 | } | |
367 | ||
3b8d8d91 JB |
368 | static void gen6_pm_irq_handler(struct drm_device *dev) |
369 | { | |
370 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
371 | u8 new_delay = dev_priv->cur_delay; | |
372 | u32 pm_iir; | |
373 | ||
374 | pm_iir = I915_READ(GEN6_PMIIR); | |
375 | if (!pm_iir) | |
376 | return; | |
377 | ||
378 | if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { | |
379 | if (dev_priv->cur_delay != dev_priv->max_delay) | |
380 | new_delay = dev_priv->cur_delay + 1; | |
381 | if (new_delay > dev_priv->max_delay) | |
382 | new_delay = dev_priv->max_delay; | |
383 | } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) { | |
384 | if (dev_priv->cur_delay != dev_priv->min_delay) | |
385 | new_delay = dev_priv->cur_delay - 1; | |
386 | if (new_delay < dev_priv->min_delay) { | |
387 | new_delay = dev_priv->min_delay; | |
388 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
389 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) | | |
390 | ((new_delay << 16) & 0x3f0000)); | |
391 | } else { | |
392 | /* Make sure we continue to get down interrupts | |
393 | * until we hit the minimum frequency */ | |
394 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
395 | I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000); | |
396 | } | |
397 | ||
398 | } | |
399 | ||
400 | gen6_set_rps(dev, new_delay); | |
401 | dev_priv->cur_delay = new_delay; | |
402 | ||
403 | I915_WRITE(GEN6_PMIIR, pm_iir); | |
404 | } | |
405 | ||
776ad806 JB |
406 | static void pch_irq_handler(struct drm_device *dev) |
407 | { | |
408 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
409 | u32 pch_iir; | |
9db4a9c7 | 410 | int pipe; |
776ad806 JB |
411 | |
412 | pch_iir = I915_READ(SDEIIR); | |
413 | ||
414 | if (pch_iir & SDE_AUDIO_POWER_MASK) | |
415 | DRM_DEBUG_DRIVER("PCH audio power change on port %d\n", | |
416 | (pch_iir & SDE_AUDIO_POWER_MASK) >> | |
417 | SDE_AUDIO_POWER_SHIFT); | |
418 | ||
419 | if (pch_iir & SDE_GMBUS) | |
420 | DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n"); | |
421 | ||
422 | if (pch_iir & SDE_AUDIO_HDCP_MASK) | |
423 | DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n"); | |
424 | ||
425 | if (pch_iir & SDE_AUDIO_TRANS_MASK) | |
426 | DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); | |
427 | ||
428 | if (pch_iir & SDE_POISON) | |
429 | DRM_ERROR("PCH poison interrupt\n"); | |
430 | ||
9db4a9c7 JB |
431 | if (pch_iir & SDE_FDI_MASK) |
432 | for_each_pipe(pipe) | |
433 | DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n", | |
434 | pipe_name(pipe), | |
435 | I915_READ(FDI_RX_IIR(pipe))); | |
776ad806 JB |
436 | |
437 | if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE)) | |
438 | DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); | |
439 | ||
440 | if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR)) | |
441 | DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); | |
442 | ||
443 | if (pch_iir & SDE_TRANSB_FIFO_UNDER) | |
444 | DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n"); | |
445 | if (pch_iir & SDE_TRANSA_FIFO_UNDER) | |
446 | DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n"); | |
447 | } | |
448 | ||
995b6762 | 449 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
450 | { |
451 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
452 | int ret = IRQ_NONE; | |
3b8d8d91 | 453 | u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir; |
2d7b8366 | 454 | u32 hotplug_mask; |
036a4a7d | 455 | struct drm_i915_master_private *master_priv; |
881f47b6 XH |
456 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
457 | ||
458 | if (IS_GEN6(dev)) | |
459 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | |
036a4a7d | 460 | |
2d109a84 ZN |
461 | /* disable master interrupt before clearing iir */ |
462 | de_ier = I915_READ(DEIER); | |
463 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 464 | POSTING_READ(DEIER); |
2d109a84 | 465 | |
036a4a7d ZW |
466 | de_iir = I915_READ(DEIIR); |
467 | gt_iir = I915_READ(GTIIR); | |
c650156a | 468 | pch_iir = I915_READ(SDEIIR); |
3b8d8d91 | 469 | pm_iir = I915_READ(GEN6_PMIIR); |
036a4a7d | 470 | |
3b8d8d91 JB |
471 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && |
472 | (!IS_GEN6(dev) || pm_iir == 0)) | |
c7c85101 | 473 | goto done; |
036a4a7d | 474 | |
2d7b8366 YL |
475 | if (HAS_PCH_CPT(dev)) |
476 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
477 | else | |
478 | hotplug_mask = SDE_HOTPLUG_MASK; | |
479 | ||
c7c85101 | 480 | ret = IRQ_HANDLED; |
036a4a7d | 481 | |
c7c85101 ZN |
482 | if (dev->primary->master) { |
483 | master_priv = dev->primary->master->driver_priv; | |
484 | if (master_priv->sarea_priv) | |
485 | master_priv->sarea_priv->last_dispatch = | |
486 | READ_BREADCRUMB(dev_priv); | |
487 | } | |
036a4a7d | 488 | |
c6df541c | 489 | if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY)) |
1ec14ad3 | 490 | notify_ring(dev, &dev_priv->ring[RCS]); |
881f47b6 | 491 | if (gt_iir & bsd_usr_interrupt) |
1ec14ad3 CW |
492 | notify_ring(dev, &dev_priv->ring[VCS]); |
493 | if (gt_iir & GT_BLT_USER_INTERRUPT) | |
494 | notify_ring(dev, &dev_priv->ring[BCS]); | |
01c66889 | 495 | |
c7c85101 | 496 | if (de_iir & DE_GSE) |
3b617967 | 497 | intel_opregion_gse_intr(dev); |
c650156a | 498 | |
f072d2e7 | 499 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 500 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 501 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 502 | } |
013d5aa2 | 503 | |
f072d2e7 | 504 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 505 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 506 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 507 | } |
013d5aa2 | 508 | |
f072d2e7 | 509 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
510 | drm_handle_vblank(dev, 0); |
511 | ||
f072d2e7 | 512 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
513 | drm_handle_vblank(dev, 1); |
514 | ||
c7c85101 | 515 | /* check event from PCH */ |
776ad806 JB |
516 | if (de_iir & DE_PCH_EVENT) { |
517 | if (pch_iir & hotplug_mask) | |
518 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
519 | pch_irq_handler(dev); | |
520 | } | |
036a4a7d | 521 | |
f97108d1 | 522 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 523 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
524 | i915_handle_rps_change(dev); |
525 | } | |
526 | ||
3b8d8d91 JB |
527 | if (IS_GEN6(dev)) |
528 | gen6_pm_irq_handler(dev); | |
529 | ||
c7c85101 ZN |
530 | /* should clear PCH hotplug event before clear CPU irq */ |
531 | I915_WRITE(SDEIIR, pch_iir); | |
532 | I915_WRITE(GTIIR, gt_iir); | |
533 | I915_WRITE(DEIIR, de_iir); | |
534 | ||
535 | done: | |
2d109a84 | 536 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 537 | POSTING_READ(DEIER); |
2d109a84 | 538 | |
036a4a7d ZW |
539 | return ret; |
540 | } | |
541 | ||
8a905236 JB |
542 | /** |
543 | * i915_error_work_func - do process context error handling work | |
544 | * @work: work struct | |
545 | * | |
546 | * Fire an error uevent so userspace can see that a hang or error | |
547 | * was detected. | |
548 | */ | |
549 | static void i915_error_work_func(struct work_struct *work) | |
550 | { | |
551 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
552 | error_work); | |
553 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
554 | char *error_event[] = { "ERROR=1", NULL }; |
555 | char *reset_event[] = { "RESET=1", NULL }; | |
556 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 557 | |
f316a42c BG |
558 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
559 | ||
ba1234d1 | 560 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
561 | DRM_DEBUG_DRIVER("resetting chip\n"); |
562 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
563 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
564 | atomic_set(&dev_priv->mm.wedged, 0); | |
565 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 566 | } |
30dbf0c0 | 567 | complete_all(&dev_priv->error_completion); |
f316a42c | 568 | } |
8a905236 JB |
569 | } |
570 | ||
3bd3c932 | 571 | #ifdef CONFIG_DEBUG_FS |
9df30794 | 572 | static struct drm_i915_error_object * |
bcfb2e28 | 573 | i915_error_object_create(struct drm_i915_private *dev_priv, |
05394f39 | 574 | struct drm_i915_gem_object *src) |
9df30794 CW |
575 | { |
576 | struct drm_i915_error_object *dst; | |
9df30794 | 577 | int page, page_count; |
e56660dd | 578 | u32 reloc_offset; |
9df30794 | 579 | |
05394f39 | 580 | if (src == NULL || src->pages == NULL) |
9df30794 CW |
581 | return NULL; |
582 | ||
05394f39 | 583 | page_count = src->base.size / PAGE_SIZE; |
9df30794 CW |
584 | |
585 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
586 | if (dst == NULL) | |
587 | return NULL; | |
588 | ||
05394f39 | 589 | reloc_offset = src->gtt_offset; |
9df30794 | 590 | for (page = 0; page < page_count; page++) { |
788885ae | 591 | unsigned long flags; |
e56660dd CW |
592 | void __iomem *s; |
593 | void *d; | |
788885ae | 594 | |
e56660dd | 595 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
596 | if (d == NULL) |
597 | goto unwind; | |
e56660dd | 598 | |
788885ae | 599 | local_irq_save(flags); |
e56660dd | 600 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3e4d3af5 | 601 | reloc_offset); |
e56660dd | 602 | memcpy_fromio(d, s, PAGE_SIZE); |
3e4d3af5 | 603 | io_mapping_unmap_atomic(s); |
788885ae | 604 | local_irq_restore(flags); |
e56660dd | 605 | |
9df30794 | 606 | dst->pages[page] = d; |
e56660dd CW |
607 | |
608 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
609 | } |
610 | dst->page_count = page_count; | |
05394f39 | 611 | dst->gtt_offset = src->gtt_offset; |
9df30794 CW |
612 | |
613 | return dst; | |
614 | ||
615 | unwind: | |
616 | while (page--) | |
617 | kfree(dst->pages[page]); | |
618 | kfree(dst); | |
619 | return NULL; | |
620 | } | |
621 | ||
622 | static void | |
623 | i915_error_object_free(struct drm_i915_error_object *obj) | |
624 | { | |
625 | int page; | |
626 | ||
627 | if (obj == NULL) | |
628 | return; | |
629 | ||
630 | for (page = 0; page < obj->page_count; page++) | |
631 | kfree(obj->pages[page]); | |
632 | ||
633 | kfree(obj); | |
634 | } | |
635 | ||
636 | static void | |
637 | i915_error_state_free(struct drm_device *dev, | |
638 | struct drm_i915_error_state *error) | |
639 | { | |
e2f973d5 CW |
640 | int i; |
641 | ||
642 | for (i = 0; i < ARRAY_SIZE(error->batchbuffer); i++) | |
643 | i915_error_object_free(error->batchbuffer[i]); | |
644 | ||
645 | for (i = 0; i < ARRAY_SIZE(error->ringbuffer); i++) | |
646 | i915_error_object_free(error->ringbuffer[i]); | |
647 | ||
9df30794 | 648 | kfree(error->active_bo); |
6ef3d427 | 649 | kfree(error->overlay); |
9df30794 CW |
650 | kfree(error); |
651 | } | |
652 | ||
c724e8a9 CW |
653 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
654 | int count, | |
655 | struct list_head *head) | |
656 | { | |
657 | struct drm_i915_gem_object *obj; | |
658 | int i = 0; | |
659 | ||
660 | list_for_each_entry(obj, head, mm_list) { | |
661 | err->size = obj->base.size; | |
662 | err->name = obj->base.name; | |
663 | err->seqno = obj->last_rendering_seqno; | |
664 | err->gtt_offset = obj->gtt_offset; | |
665 | err->read_domains = obj->base.read_domains; | |
666 | err->write_domain = obj->base.write_domain; | |
667 | err->fence_reg = obj->fence_reg; | |
668 | err->pinned = 0; | |
669 | if (obj->pin_count > 0) | |
670 | err->pinned = 1; | |
671 | if (obj->user_pin_count > 0) | |
672 | err->pinned = -1; | |
673 | err->tiling = obj->tiling_mode; | |
674 | err->dirty = obj->dirty; | |
675 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
3685092b | 676 | err->ring = obj->ring ? obj->ring->id : 0; |
a779e5ab | 677 | err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY; |
c724e8a9 CW |
678 | |
679 | if (++i == count) | |
680 | break; | |
681 | ||
682 | err++; | |
683 | } | |
684 | ||
685 | return i; | |
686 | } | |
687 | ||
748ebc60 CW |
688 | static void i915_gem_record_fences(struct drm_device *dev, |
689 | struct drm_i915_error_state *error) | |
690 | { | |
691 | struct drm_i915_private *dev_priv = dev->dev_private; | |
692 | int i; | |
693 | ||
694 | /* Fences */ | |
695 | switch (INTEL_INFO(dev)->gen) { | |
696 | case 6: | |
697 | for (i = 0; i < 16; i++) | |
698 | error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8)); | |
699 | break; | |
700 | case 5: | |
701 | case 4: | |
702 | for (i = 0; i < 16; i++) | |
703 | error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8)); | |
704 | break; | |
705 | case 3: | |
706 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
707 | for (i = 0; i < 8; i++) | |
708 | error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4)); | |
709 | case 2: | |
710 | for (i = 0; i < 8; i++) | |
711 | error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4)); | |
712 | break; | |
713 | ||
714 | } | |
715 | } | |
716 | ||
bcfb2e28 CW |
717 | static struct drm_i915_error_object * |
718 | i915_error_first_batchbuffer(struct drm_i915_private *dev_priv, | |
719 | struct intel_ring_buffer *ring) | |
720 | { | |
721 | struct drm_i915_gem_object *obj; | |
722 | u32 seqno; | |
723 | ||
724 | if (!ring->get_seqno) | |
725 | return NULL; | |
726 | ||
727 | seqno = ring->get_seqno(ring); | |
728 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) { | |
729 | if (obj->ring != ring) | |
730 | continue; | |
731 | ||
c37d9a5d | 732 | if (i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
bcfb2e28 CW |
733 | continue; |
734 | ||
735 | if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0) | |
736 | continue; | |
737 | ||
738 | /* We need to copy these to an anonymous buffer as the simplest | |
739 | * method to avoid being overwritten by userspace. | |
740 | */ | |
741 | return i915_error_object_create(dev_priv, obj); | |
742 | } | |
743 | ||
744 | return NULL; | |
745 | } | |
746 | ||
8a905236 JB |
747 | /** |
748 | * i915_capture_error_state - capture an error record for later analysis | |
749 | * @dev: drm device | |
750 | * | |
751 | * Should be called when an error is detected (either a hang or an error | |
752 | * interrupt) to capture error state from the time of the error. Fills | |
753 | * out a structure which becomes available in debugfs for user level tools | |
754 | * to pick up. | |
755 | */ | |
63eeaf38 JB |
756 | static void i915_capture_error_state(struct drm_device *dev) |
757 | { | |
758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
05394f39 | 759 | struct drm_i915_gem_object *obj; |
63eeaf38 JB |
760 | struct drm_i915_error_state *error; |
761 | unsigned long flags; | |
9db4a9c7 | 762 | int i, pipe; |
63eeaf38 JB |
763 | |
764 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
765 | error = dev_priv->first_error; |
766 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
767 | if (error) | |
768 | return; | |
63eeaf38 | 769 | |
9db4a9c7 | 770 | /* Account for pipe specific data like PIPE*STAT */ |
63eeaf38 JB |
771 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
772 | if (!error) { | |
9df30794 CW |
773 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
774 | return; | |
63eeaf38 JB |
775 | } |
776 | ||
b6f7833b CW |
777 | DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n", |
778 | dev->primary->index); | |
2fa772f3 | 779 | |
1ec14ad3 | 780 | error->seqno = dev_priv->ring[RCS].get_seqno(&dev_priv->ring[RCS]); |
63eeaf38 JB |
781 | error->eir = I915_READ(EIR); |
782 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
9db4a9c7 JB |
783 | for_each_pipe(pipe) |
784 | error->pipestat[pipe] = I915_READ(PIPESTAT(pipe)); | |
63eeaf38 | 785 | error->instpm = I915_READ(INSTPM); |
f406839f CW |
786 | error->error = 0; |
787 | if (INTEL_INFO(dev)->gen >= 6) { | |
788 | error->error = I915_READ(ERROR_GEN6); | |
add354dd | 789 | |
1d8f38f4 CW |
790 | error->bcs_acthd = I915_READ(BCS_ACTHD); |
791 | error->bcs_ipehr = I915_READ(BCS_IPEHR); | |
792 | error->bcs_ipeir = I915_READ(BCS_IPEIR); | |
793 | error->bcs_instdone = I915_READ(BCS_INSTDONE); | |
794 | error->bcs_seqno = 0; | |
1ec14ad3 CW |
795 | if (dev_priv->ring[BCS].get_seqno) |
796 | error->bcs_seqno = dev_priv->ring[BCS].get_seqno(&dev_priv->ring[BCS]); | |
add354dd CW |
797 | |
798 | error->vcs_acthd = I915_READ(VCS_ACTHD); | |
799 | error->vcs_ipehr = I915_READ(VCS_IPEHR); | |
800 | error->vcs_ipeir = I915_READ(VCS_IPEIR); | |
801 | error->vcs_instdone = I915_READ(VCS_INSTDONE); | |
802 | error->vcs_seqno = 0; | |
1ec14ad3 CW |
803 | if (dev_priv->ring[VCS].get_seqno) |
804 | error->vcs_seqno = dev_priv->ring[VCS].get_seqno(&dev_priv->ring[VCS]); | |
f406839f CW |
805 | } |
806 | if (INTEL_INFO(dev)->gen >= 4) { | |
63eeaf38 JB |
807 | error->ipeir = I915_READ(IPEIR_I965); |
808 | error->ipehr = I915_READ(IPEHR_I965); | |
809 | error->instdone = I915_READ(INSTDONE_I965); | |
810 | error->instps = I915_READ(INSTPS); | |
811 | error->instdone1 = I915_READ(INSTDONE1); | |
812 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 813 | error->bbaddr = I915_READ64(BB_ADDR); |
f406839f CW |
814 | } else { |
815 | error->ipeir = I915_READ(IPEIR); | |
816 | error->ipehr = I915_READ(IPEHR); | |
817 | error->instdone = I915_READ(INSTDONE); | |
818 | error->acthd = I915_READ(ACTHD); | |
819 | error->bbaddr = 0; | |
63eeaf38 | 820 | } |
748ebc60 | 821 | i915_gem_record_fences(dev, error); |
63eeaf38 | 822 | |
e2f973d5 CW |
823 | /* Record the active batch and ring buffers */ |
824 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
bcfb2e28 CW |
825 | error->batchbuffer[i] = |
826 | i915_error_first_batchbuffer(dev_priv, | |
827 | &dev_priv->ring[i]); | |
9df30794 | 828 | |
e2f973d5 CW |
829 | error->ringbuffer[i] = |
830 | i915_error_object_create(dev_priv, | |
831 | dev_priv->ring[i].obj); | |
832 | } | |
9df30794 | 833 | |
c724e8a9 | 834 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 835 | error->active_bo = NULL; |
c724e8a9 | 836 | error->pinned_bo = NULL; |
9df30794 | 837 | |
bcfb2e28 CW |
838 | i = 0; |
839 | list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) | |
840 | i++; | |
841 | error->active_bo_count = i; | |
05394f39 | 842 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
bcfb2e28 CW |
843 | i++; |
844 | error->pinned_bo_count = i - error->active_bo_count; | |
c724e8a9 | 845 | |
8e934dbf CW |
846 | error->active_bo = NULL; |
847 | error->pinned_bo = NULL; | |
bcfb2e28 CW |
848 | if (i) { |
849 | error->active_bo = kmalloc(sizeof(*error->active_bo)*i, | |
9df30794 | 850 | GFP_ATOMIC); |
c724e8a9 CW |
851 | if (error->active_bo) |
852 | error->pinned_bo = | |
853 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
854 | } |
855 | ||
c724e8a9 CW |
856 | if (error->active_bo) |
857 | error->active_bo_count = | |
858 | capture_bo_list(error->active_bo, | |
859 | error->active_bo_count, | |
860 | &dev_priv->mm.active_list); | |
861 | ||
862 | if (error->pinned_bo) | |
863 | error->pinned_bo_count = | |
864 | capture_bo_list(error->pinned_bo, | |
865 | error->pinned_bo_count, | |
866 | &dev_priv->mm.pinned_list); | |
867 | ||
9df30794 CW |
868 | do_gettimeofday(&error->time); |
869 | ||
6ef3d427 | 870 | error->overlay = intel_overlay_capture_error_state(dev); |
c4a1d9e4 | 871 | error->display = intel_display_capture_error_state(dev); |
6ef3d427 | 872 | |
9df30794 CW |
873 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
874 | if (dev_priv->first_error == NULL) { | |
875 | dev_priv->first_error = error; | |
876 | error = NULL; | |
877 | } | |
63eeaf38 | 878 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
879 | |
880 | if (error) | |
881 | i915_error_state_free(dev, error); | |
882 | } | |
883 | ||
884 | void i915_destroy_error_state(struct drm_device *dev) | |
885 | { | |
886 | struct drm_i915_private *dev_priv = dev->dev_private; | |
887 | struct drm_i915_error_state *error; | |
888 | ||
889 | spin_lock(&dev_priv->error_lock); | |
890 | error = dev_priv->first_error; | |
891 | dev_priv->first_error = NULL; | |
892 | spin_unlock(&dev_priv->error_lock); | |
893 | ||
894 | if (error) | |
895 | i915_error_state_free(dev, error); | |
63eeaf38 | 896 | } |
3bd3c932 CW |
897 | #else |
898 | #define i915_capture_error_state(x) | |
899 | #endif | |
63eeaf38 | 900 | |
35aed2e6 | 901 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
902 | { |
903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
904 | u32 eir = I915_READ(EIR); | |
9db4a9c7 | 905 | int pipe; |
8a905236 | 906 | |
35aed2e6 CW |
907 | if (!eir) |
908 | return; | |
8a905236 JB |
909 | |
910 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
911 | eir); | |
912 | ||
913 | if (IS_G4X(dev)) { | |
914 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
915 | u32 ipeir = I915_READ(IPEIR_I965); | |
916 | ||
917 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
918 | I915_READ(IPEIR_I965)); | |
919 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
920 | I915_READ(IPEHR_I965)); | |
921 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
922 | I915_READ(INSTDONE_I965)); | |
923 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
924 | I915_READ(INSTPS)); | |
925 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
926 | I915_READ(INSTDONE1)); | |
927 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
928 | I915_READ(ACTHD_I965)); | |
929 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 930 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
931 | } |
932 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
933 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
934 | printk(KERN_ERR "page table error\n"); | |
935 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
936 | pgtbl_err); | |
937 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 938 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
939 | } |
940 | } | |
941 | ||
a6c45cf0 | 942 | if (!IS_GEN2(dev)) { |
8a905236 JB |
943 | if (eir & I915_ERROR_PAGE_TABLE) { |
944 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
945 | printk(KERN_ERR "page table error\n"); | |
946 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
947 | pgtbl_err); | |
948 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 949 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
950 | } |
951 | } | |
952 | ||
953 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
9db4a9c7 JB |
954 | printk(KERN_ERR "memory refresh error:\n"); |
955 | for_each_pipe(pipe) | |
956 | printk(KERN_ERR "pipe %c stat: 0x%08x\n", | |
957 | pipe_name(pipe), I915_READ(PIPESTAT(pipe))); | |
8a905236 JB |
958 | /* pipestat has already been acked */ |
959 | } | |
960 | if (eir & I915_ERROR_INSTRUCTION) { | |
961 | printk(KERN_ERR "instruction error\n"); | |
962 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
963 | I915_READ(INSTPM)); | |
a6c45cf0 | 964 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
965 | u32 ipeir = I915_READ(IPEIR); |
966 | ||
967 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
968 | I915_READ(IPEIR)); | |
969 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
970 | I915_READ(IPEHR)); | |
971 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
972 | I915_READ(INSTDONE)); | |
973 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
974 | I915_READ(ACTHD)); | |
975 | I915_WRITE(IPEIR, ipeir); | |
3143a2bf | 976 | POSTING_READ(IPEIR); |
8a905236 JB |
977 | } else { |
978 | u32 ipeir = I915_READ(IPEIR_I965); | |
979 | ||
980 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
981 | I915_READ(IPEIR_I965)); | |
982 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
983 | I915_READ(IPEHR_I965)); | |
984 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
985 | I915_READ(INSTDONE_I965)); | |
986 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
987 | I915_READ(INSTPS)); | |
988 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
989 | I915_READ(INSTDONE1)); | |
990 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
991 | I915_READ(ACTHD_I965)); | |
992 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 993 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
994 | } |
995 | } | |
996 | ||
997 | I915_WRITE(EIR, eir); | |
3143a2bf | 998 | POSTING_READ(EIR); |
8a905236 JB |
999 | eir = I915_READ(EIR); |
1000 | if (eir) { | |
1001 | /* | |
1002 | * some errors might have become stuck, | |
1003 | * mask them. | |
1004 | */ | |
1005 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
1006 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
1007 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
1008 | } | |
35aed2e6 CW |
1009 | } |
1010 | ||
1011 | /** | |
1012 | * i915_handle_error - handle an error interrupt | |
1013 | * @dev: drm device | |
1014 | * | |
1015 | * Do some basic checking of regsiter state at error interrupt time and | |
1016 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
1017 | * sure we get a record and make it available in debugfs. Fire a uevent | |
1018 | * so userspace knows something bad happened (should trigger collection | |
1019 | * of a ring dump etc.). | |
1020 | */ | |
527f9e90 | 1021 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
1022 | { |
1023 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1024 | ||
1025 | i915_capture_error_state(dev); | |
1026 | i915_report_and_clear_eir(dev); | |
8a905236 | 1027 | |
ba1234d1 | 1028 | if (wedged) { |
30dbf0c0 | 1029 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
1030 | atomic_set(&dev_priv->mm.wedged, 1); |
1031 | ||
11ed50ec BG |
1032 | /* |
1033 | * Wakeup waiting processes so they don't hang | |
1034 | */ | |
1ec14ad3 | 1035 | wake_up_all(&dev_priv->ring[RCS].irq_queue); |
f787a5f5 | 1036 | if (HAS_BSD(dev)) |
1ec14ad3 | 1037 | wake_up_all(&dev_priv->ring[VCS].irq_queue); |
549f7365 | 1038 | if (HAS_BLT(dev)) |
1ec14ad3 | 1039 | wake_up_all(&dev_priv->ring[BCS].irq_queue); |
11ed50ec BG |
1040 | } |
1041 | ||
9c9fe1f8 | 1042 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
1043 | } |
1044 | ||
4e5359cd SF |
1045 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
1046 | { | |
1047 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1048 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
1049 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
05394f39 | 1050 | struct drm_i915_gem_object *obj; |
4e5359cd SF |
1051 | struct intel_unpin_work *work; |
1052 | unsigned long flags; | |
1053 | bool stall_detected; | |
1054 | ||
1055 | /* Ignore early vblank irqs */ | |
1056 | if (intel_crtc == NULL) | |
1057 | return; | |
1058 | ||
1059 | spin_lock_irqsave(&dev->event_lock, flags); | |
1060 | work = intel_crtc->unpin_work; | |
1061 | ||
1062 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
1063 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
1064 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1065 | return; | |
1066 | } | |
1067 | ||
1068 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
05394f39 | 1069 | obj = work->pending_flip_obj; |
a6c45cf0 | 1070 | if (INTEL_INFO(dev)->gen >= 4) { |
9db4a9c7 | 1071 | int dspsurf = DSPSURF(intel_crtc->plane); |
05394f39 | 1072 | stall_detected = I915_READ(dspsurf) == obj->gtt_offset; |
4e5359cd | 1073 | } else { |
9db4a9c7 | 1074 | int dspaddr = DSPADDR(intel_crtc->plane); |
05394f39 | 1075 | stall_detected = I915_READ(dspaddr) == (obj->gtt_offset + |
4e5359cd SF |
1076 | crtc->y * crtc->fb->pitch + |
1077 | crtc->x * crtc->fb->bits_per_pixel/8); | |
1078 | } | |
1079 | ||
1080 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
1081 | ||
1082 | if (stall_detected) { | |
1083 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
1084 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
1085 | } | |
1086 | } | |
1087 | ||
1da177e4 LT |
1088 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
1089 | { | |
84b1fd10 | 1090 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 1091 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 1092 | struct drm_i915_master_private *master_priv; |
cdfbc41f | 1093 | u32 iir, new_iir; |
9db4a9c7 | 1094 | u32 pipe_stats[I915_MAX_PIPES]; |
05eff845 | 1095 | u32 vblank_status; |
0a3e67a4 | 1096 | int vblank = 0; |
7c463586 | 1097 | unsigned long irqflags; |
05eff845 | 1098 | int irq_received; |
9db4a9c7 JB |
1099 | int ret = IRQ_NONE, pipe; |
1100 | bool blc_event = false; | |
6e5fca53 | 1101 | |
630681d9 EA |
1102 | atomic_inc(&dev_priv->irq_received); |
1103 | ||
bad720ff | 1104 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1105 | return ironlake_irq_handler(dev); |
036a4a7d | 1106 | |
ed4cb414 | 1107 | iir = I915_READ(IIR); |
a6b54f3f | 1108 | |
a6c45cf0 | 1109 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 1110 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 1111 | else |
d874bcff | 1112 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 1113 | |
05eff845 KP |
1114 | for (;;) { |
1115 | irq_received = iir != 0; | |
1116 | ||
1117 | /* Can't rely on pipestat interrupt bit in iir as it might | |
1118 | * have been cleared after the pipestat interrupt was received. | |
1119 | * It doesn't set the bit in iir again, but it still produces | |
1120 | * interrupts (for non-MSI). | |
1121 | */ | |
1ec14ad3 | 1122 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
8a905236 | 1123 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 1124 | i915_handle_error(dev, false); |
8a905236 | 1125 | |
9db4a9c7 JB |
1126 | for_each_pipe(pipe) { |
1127 | int reg = PIPESTAT(pipe); | |
1128 | pipe_stats[pipe] = I915_READ(reg); | |
1129 | ||
1130 | /* | |
1131 | * Clear the PIPE*STAT regs before the IIR | |
1132 | */ | |
1133 | if (pipe_stats[pipe] & 0x8000ffff) { | |
1134 | if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS) | |
1135 | DRM_DEBUG_DRIVER("pipe %c underrun\n", | |
1136 | pipe_name(pipe)); | |
1137 | I915_WRITE(reg, pipe_stats[pipe]); | |
1138 | irq_received = 1; | |
1139 | } | |
cdfbc41f | 1140 | } |
1ec14ad3 | 1141 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
05eff845 KP |
1142 | |
1143 | if (!irq_received) | |
1144 | break; | |
1145 | ||
1146 | ret = IRQ_HANDLED; | |
8ee1c3db | 1147 | |
5ca58282 JB |
1148 | /* Consume port. Then clear IIR or we'll miss events */ |
1149 | if ((I915_HAS_HOTPLUG(dev)) && | |
1150 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1151 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1152 | ||
44d98a61 | 1153 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1154 | hotplug_status); |
1155 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1156 | queue_work(dev_priv->wq, |
1157 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1158 | |
1159 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1160 | I915_READ(PORT_HOTPLUG_STAT); | |
1161 | } | |
1162 | ||
cdfbc41f EA |
1163 | I915_WRITE(IIR, iir); |
1164 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1165 | |
7c1c2871 DA |
1166 | if (dev->primary->master) { |
1167 | master_priv = dev->primary->master->driver_priv; | |
1168 | if (master_priv->sarea_priv) | |
1169 | master_priv->sarea_priv->last_dispatch = | |
1170 | READ_BREADCRUMB(dev_priv); | |
1171 | } | |
0a3e67a4 | 1172 | |
549f7365 | 1173 | if (iir & I915_USER_INTERRUPT) |
1ec14ad3 CW |
1174 | notify_ring(dev, &dev_priv->ring[RCS]); |
1175 | if (iir & I915_BSD_USER_INTERRUPT) | |
1176 | notify_ring(dev, &dev_priv->ring[VCS]); | |
d1b851fc | 1177 | |
1afe3e9d | 1178 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1179 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1180 | if (dev_priv->flip_pending_is_done) |
1181 | intel_finish_page_flip_plane(dev, 0); | |
1182 | } | |
6b95a207 | 1183 | |
1afe3e9d | 1184 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1185 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1186 | if (dev_priv->flip_pending_is_done) |
1187 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1188 | } |
6b95a207 | 1189 | |
9db4a9c7 JB |
1190 | for_each_pipe(pipe) { |
1191 | if (pipe_stats[pipe] & vblank_status && | |
1192 | drm_handle_vblank(dev, pipe)) { | |
1193 | vblank++; | |
1194 | if (!dev_priv->flip_pending_is_done) { | |
1195 | i915_pageflip_stall_check(dev, pipe); | |
1196 | intel_finish_page_flip(dev, pipe); | |
1197 | } | |
4e5359cd | 1198 | } |
7c463586 | 1199 | |
9db4a9c7 JB |
1200 | if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS) |
1201 | blc_event = true; | |
cdfbc41f | 1202 | } |
7c463586 | 1203 | |
9db4a9c7 JB |
1204 | |
1205 | if (blc_event || (iir & I915_ASLE_INTERRUPT)) | |
3b617967 | 1206 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1207 | |
1208 | /* With MSI, interrupts are only generated when iir | |
1209 | * transitions from zero to nonzero. If another bit got | |
1210 | * set while we were handling the existing iir bits, then | |
1211 | * we would never get another interrupt. | |
1212 | * | |
1213 | * This is fine on non-MSI as well, as if we hit this path | |
1214 | * we avoid exiting the interrupt handler only to generate | |
1215 | * another one. | |
1216 | * | |
1217 | * Note that for MSI this could cause a stray interrupt report | |
1218 | * if an interrupt landed in the time between writing IIR and | |
1219 | * the posting read. This should be rare enough to never | |
1220 | * trigger the 99% of 100,000 interrupts test for disabling | |
1221 | * stray interrupts. | |
1222 | */ | |
1223 | iir = new_iir; | |
05eff845 | 1224 | } |
0a3e67a4 | 1225 | |
05eff845 | 1226 | return ret; |
1da177e4 LT |
1227 | } |
1228 | ||
af6061af | 1229 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1230 | { |
1231 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1232 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1233 | |
1234 | i915_kernel_lost_context(dev); | |
1235 | ||
44d98a61 | 1236 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1237 | |
c99b058f | 1238 | dev_priv->counter++; |
c29b669c | 1239 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1240 | dev_priv->counter = 1; |
7c1c2871 DA |
1241 | if (master_priv->sarea_priv) |
1242 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1243 | |
e1f99ce6 CW |
1244 | if (BEGIN_LP_RING(4) == 0) { |
1245 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1246 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1247 | OUT_RING(dev_priv->counter); | |
1248 | OUT_RING(MI_USER_INTERRUPT); | |
1249 | ADVANCE_LP_RING(); | |
1250 | } | |
bc5f4523 | 1251 | |
c29b669c | 1252 | return dev_priv->counter; |
1da177e4 LT |
1253 | } |
1254 | ||
84b1fd10 | 1255 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1256 | { |
1257 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1258 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1259 | int ret = 0; |
1ec14ad3 | 1260 | struct intel_ring_buffer *ring = LP_RING(dev_priv); |
1da177e4 | 1261 | |
44d98a61 | 1262 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1263 | READ_BREADCRUMB(dev_priv)); |
1264 | ||
ed4cb414 | 1265 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1266 | if (master_priv->sarea_priv) |
1267 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1268 | return 0; |
ed4cb414 | 1269 | } |
1da177e4 | 1270 | |
7c1c2871 DA |
1271 | if (master_priv->sarea_priv) |
1272 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1273 | |
b13c2b96 CW |
1274 | if (ring->irq_get(ring)) { |
1275 | DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ, | |
1276 | READ_BREADCRUMB(dev_priv) >= irq_nr); | |
1277 | ring->irq_put(ring); | |
5a9a8d1a CW |
1278 | } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000)) |
1279 | ret = -EBUSY; | |
1da177e4 | 1280 | |
20caafa6 | 1281 | if (ret == -EBUSY) { |
3e684eae | 1282 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1283 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1284 | } | |
1285 | ||
af6061af DA |
1286 | return ret; |
1287 | } | |
1288 | ||
1da177e4 LT |
1289 | /* Needs the lock as it touches the ring. |
1290 | */ | |
c153f45f EA |
1291 | int i915_irq_emit(struct drm_device *dev, void *data, |
1292 | struct drm_file *file_priv) | |
1da177e4 | 1293 | { |
1da177e4 | 1294 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1295 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1296 | int result; |
1297 | ||
1ec14ad3 | 1298 | if (!dev_priv || !LP_RING(dev_priv)->virtual_start) { |
3e684eae | 1299 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1300 | return -EINVAL; |
1da177e4 | 1301 | } |
299eb93c EA |
1302 | |
1303 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1304 | ||
546b0974 | 1305 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1306 | result = i915_emit_irq(dev); |
546b0974 | 1307 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1308 | |
c153f45f | 1309 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1310 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1311 | return -EFAULT; |
1da177e4 LT |
1312 | } |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
1317 | /* Doesn't need the hardware lock. | |
1318 | */ | |
c153f45f EA |
1319 | int i915_irq_wait(struct drm_device *dev, void *data, |
1320 | struct drm_file *file_priv) | |
1da177e4 | 1321 | { |
1da177e4 | 1322 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1323 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1324 | |
1325 | if (!dev_priv) { | |
3e684eae | 1326 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1327 | return -EINVAL; |
1da177e4 LT |
1328 | } |
1329 | ||
c153f45f | 1330 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1331 | } |
1332 | ||
b0b544cd CW |
1333 | static void i915_vblank_work_func(struct work_struct *work) |
1334 | { | |
1335 | drm_i915_private_t *dev_priv = | |
1336 | container_of(work, drm_i915_private_t, vblank_work); | |
1337 | ||
1338 | if (atomic_read(&dev_priv->vblank_enabled)) { | |
1339 | if (!dev_priv->vblank_pm_qos.pm_qos_class) | |
1340 | pm_qos_add_request(&dev_priv->vblank_pm_qos, | |
1341 | PM_QOS_CPU_DMA_LATENCY, | |
1342 | 15); //>=20 won't work | |
1343 | } else { | |
1344 | if (dev_priv->vblank_pm_qos.pm_qos_class) | |
1345 | pm_qos_remove_request(&dev_priv->vblank_pm_qos); | |
1346 | } | |
1347 | } | |
1348 | ||
42f52ef8 KP |
1349 | /* Called from drm generic code, passed 'crtc' which |
1350 | * we use as a pipe index | |
1351 | */ | |
1352 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1353 | { |
1354 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1355 | unsigned long irqflags; |
71e0ffa5 | 1356 | |
5eddb70b | 1357 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1358 | return -EINVAL; |
0a3e67a4 | 1359 | |
1ec14ad3 | 1360 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
bad720ff | 1361 | if (HAS_PCH_SPLIT(dev)) |
1ec14ad3 | 1362 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
c062df61 | 1363 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
a6c45cf0 | 1364 | else if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1365 | i915_enable_pipestat(dev_priv, pipe, |
1366 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1367 | else |
7c463586 KP |
1368 | i915_enable_pipestat(dev_priv, pipe, |
1369 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
1ec14ad3 | 1370 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
b0b544cd CW |
1371 | |
1372 | /* gen3 platforms have an issue with vsync interrupts not reaching | |
1373 | * cpu during deep c-state sleep (>C1), so we need to install a | |
1374 | * PM QoS handle to prevent C-state starvation of the GPU. | |
1375 | */ | |
1376 | if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) { | |
1377 | atomic_inc(&dev_priv->vblank_enabled); | |
1378 | queue_work(dev_priv->wq, &dev_priv->vblank_work); | |
1379 | } | |
1380 | ||
0a3e67a4 JB |
1381 | return 0; |
1382 | } | |
1383 | ||
42f52ef8 KP |
1384 | /* Called from drm generic code, passed 'crtc' which |
1385 | * we use as a pipe index | |
1386 | */ | |
1387 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1388 | { |
1389 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1390 | unsigned long irqflags; |
0a3e67a4 | 1391 | |
b0b544cd CW |
1392 | if (dev_priv->info->gen == 3 && !dev_priv->info->is_g33) { |
1393 | atomic_dec(&dev_priv->vblank_enabled); | |
1394 | queue_work(dev_priv->wq, &dev_priv->vblank_work); | |
1395 | } | |
1396 | ||
1ec14ad3 | 1397 | spin_lock_irqsave(&dev_priv->irq_lock, irqflags); |
bad720ff | 1398 | if (HAS_PCH_SPLIT(dev)) |
1ec14ad3 | 1399 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
c062df61 LP |
1400 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); |
1401 | else | |
1402 | i915_disable_pipestat(dev_priv, pipe, | |
1403 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1404 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
1ec14ad3 | 1405 | spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags); |
0a3e67a4 JB |
1406 | } |
1407 | ||
702880f2 DA |
1408 | /* Set the vblank monitor pipe |
1409 | */ | |
c153f45f EA |
1410 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1411 | struct drm_file *file_priv) | |
702880f2 | 1412 | { |
702880f2 | 1413 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1414 | |
1415 | if (!dev_priv) { | |
3e684eae | 1416 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1417 | return -EINVAL; |
702880f2 DA |
1418 | } |
1419 | ||
5b51694a | 1420 | return 0; |
702880f2 DA |
1421 | } |
1422 | ||
c153f45f EA |
1423 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1424 | struct drm_file *file_priv) | |
702880f2 | 1425 | { |
702880f2 | 1426 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1427 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1428 | |
1429 | if (!dev_priv) { | |
3e684eae | 1430 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1431 | return -EINVAL; |
702880f2 DA |
1432 | } |
1433 | ||
0a3e67a4 | 1434 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1435 | |
702880f2 DA |
1436 | return 0; |
1437 | } | |
1438 | ||
a6b54f3f MD |
1439 | /** |
1440 | * Schedule buffer swap at given vertical blank. | |
1441 | */ | |
c153f45f EA |
1442 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1443 | struct drm_file *file_priv) | |
a6b54f3f | 1444 | { |
bd95e0a4 EA |
1445 | /* The delayed swap mechanism was fundamentally racy, and has been |
1446 | * removed. The model was that the client requested a delayed flip/swap | |
1447 | * from the kernel, then waited for vblank before continuing to perform | |
1448 | * rendering. The problem was that the kernel might wake the client | |
1449 | * up before it dispatched the vblank swap (since the lock has to be | |
1450 | * held while touching the ringbuffer), in which case the client would | |
1451 | * clear and start the next frame before the swap occurred, and | |
1452 | * flicker would occur in addition to likely missing the vblank. | |
1453 | * | |
1454 | * In the absence of this ioctl, userland falls back to a correct path | |
1455 | * of waiting for a vblank, then dispatching the swap on its own. | |
1456 | * Context switching to userland and back is plenty fast enough for | |
1457 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1458 | */ |
bd95e0a4 | 1459 | return -EINVAL; |
a6b54f3f MD |
1460 | } |
1461 | ||
893eead0 CW |
1462 | static u32 |
1463 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1464 | { |
893eead0 CW |
1465 | return list_entry(ring->request_list.prev, |
1466 | struct drm_i915_gem_request, list)->seqno; | |
1467 | } | |
1468 | ||
1469 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1470 | { | |
1471 | if (list_empty(&ring->request_list) || | |
1472 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { | |
1473 | /* Issue a wake-up to catch stuck h/w. */ | |
b2223497 | 1474 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
893eead0 CW |
1475 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
1476 | ring->name, | |
b2223497 | 1477 | ring->waiting_seqno, |
893eead0 CW |
1478 | ring->get_seqno(ring)); |
1479 | wake_up_all(&ring->irq_queue); | |
1480 | *err = true; | |
1481 | } | |
1482 | return true; | |
1483 | } | |
1484 | return false; | |
f65d9421 BG |
1485 | } |
1486 | ||
1ec14ad3 CW |
1487 | static bool kick_ring(struct intel_ring_buffer *ring) |
1488 | { | |
1489 | struct drm_device *dev = ring->dev; | |
1490 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1491 | u32 tmp = I915_READ_CTL(ring); | |
1492 | if (tmp & RING_WAIT) { | |
1493 | DRM_ERROR("Kicking stuck wait on %s\n", | |
1494 | ring->name); | |
1495 | I915_WRITE_CTL(ring, tmp); | |
1496 | return true; | |
1497 | } | |
1498 | if (IS_GEN6(dev) && | |
1499 | (tmp & RING_WAIT_SEMAPHORE)) { | |
1500 | DRM_ERROR("Kicking stuck semaphore on %s\n", | |
1501 | ring->name); | |
1502 | I915_WRITE_CTL(ring, tmp); | |
1503 | return true; | |
1504 | } | |
1505 | return false; | |
1506 | } | |
1507 | ||
f65d9421 BG |
1508 | /** |
1509 | * This is called when the chip hasn't reported back with completed | |
1510 | * batchbuffers in a long time. The first time this is called we simply record | |
1511 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1512 | * again, we assume the chip is wedged and try to fix it. | |
1513 | */ | |
1514 | void i915_hangcheck_elapsed(unsigned long data) | |
1515 | { | |
1516 | struct drm_device *dev = (struct drm_device *)data; | |
1517 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1518 | uint32_t acthd, instdone, instdone1; |
893eead0 CW |
1519 | bool err = false; |
1520 | ||
1521 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
1ec14ad3 CW |
1522 | if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) && |
1523 | i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) && | |
1524 | i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) { | |
893eead0 CW |
1525 | dev_priv->hangcheck_count = 0; |
1526 | if (err) | |
1527 | goto repeat; | |
1528 | return; | |
1529 | } | |
b9201c14 | 1530 | |
a6c45cf0 | 1531 | if (INTEL_INFO(dev)->gen < 4) { |
f65d9421 | 1532 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1533 | instdone = I915_READ(INSTDONE); |
1534 | instdone1 = 0; | |
1535 | } else { | |
f65d9421 | 1536 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1537 | instdone = I915_READ(INSTDONE_I965); |
1538 | instdone1 = I915_READ(INSTDONE1); | |
1539 | } | |
f65d9421 | 1540 | |
cbb465e7 CW |
1541 | if (dev_priv->last_acthd == acthd && |
1542 | dev_priv->last_instdone == instdone && | |
1543 | dev_priv->last_instdone1 == instdone1) { | |
1544 | if (dev_priv->hangcheck_count++ > 1) { | |
1545 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
8c80b59b CW |
1546 | |
1547 | if (!IS_GEN2(dev)) { | |
1548 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1549 | * If so we can simply poke the RB_WAIT bit | |
1550 | * and break the hang. This should work on | |
1551 | * all but the second generation chipsets. | |
1552 | */ | |
1ec14ad3 CW |
1553 | |
1554 | if (kick_ring(&dev_priv->ring[RCS])) | |
1555 | goto repeat; | |
1556 | ||
1557 | if (HAS_BSD(dev) && | |
1558 | kick_ring(&dev_priv->ring[VCS])) | |
1559 | goto repeat; | |
1560 | ||
1561 | if (HAS_BLT(dev) && | |
1562 | kick_ring(&dev_priv->ring[BCS])) | |
893eead0 | 1563 | goto repeat; |
8c80b59b CW |
1564 | } |
1565 | ||
cbb465e7 CW |
1566 | i915_handle_error(dev, true); |
1567 | return; | |
1568 | } | |
1569 | } else { | |
1570 | dev_priv->hangcheck_count = 0; | |
1571 | ||
1572 | dev_priv->last_acthd = acthd; | |
1573 | dev_priv->last_instdone = instdone; | |
1574 | dev_priv->last_instdone1 = instdone1; | |
1575 | } | |
f65d9421 | 1576 | |
893eead0 | 1577 | repeat: |
f65d9421 | 1578 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1579 | mod_timer(&dev_priv->hangcheck_timer, |
1580 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1581 | } |
1582 | ||
1da177e4 LT |
1583 | /* drm_dma.h hooks |
1584 | */ | |
f2b115e6 | 1585 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1586 | { |
1587 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1588 | ||
1589 | I915_WRITE(HWSTAM, 0xeffe); | |
1590 | ||
1591 | /* XXX hotplug from PCH */ | |
1592 | ||
1593 | I915_WRITE(DEIMR, 0xffffffff); | |
1594 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1595 | POSTING_READ(DEIER); |
036a4a7d ZW |
1596 | |
1597 | /* and GT */ | |
1598 | I915_WRITE(GTIMR, 0xffffffff); | |
1599 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1600 | POSTING_READ(GTIER); |
c650156a ZW |
1601 | |
1602 | /* south display irq */ | |
1603 | I915_WRITE(SDEIMR, 0xffffffff); | |
1604 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1605 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1606 | } |
1607 | ||
f2b115e6 | 1608 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1609 | { |
1610 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1611 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1612 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1613 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
1ec14ad3 | 1614 | u32 render_irqs; |
2d7b8366 | 1615 | u32 hotplug_mask; |
9db4a9c7 | 1616 | int pipe; |
036a4a7d | 1617 | |
1ec14ad3 | 1618 | dev_priv->irq_mask = ~display_mask; |
036a4a7d ZW |
1619 | |
1620 | /* should always can generate irq */ | |
1621 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1ec14ad3 CW |
1622 | I915_WRITE(DEIMR, dev_priv->irq_mask); |
1623 | I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK); | |
3143a2bf | 1624 | POSTING_READ(DEIER); |
036a4a7d | 1625 | |
1ec14ad3 | 1626 | dev_priv->gt_irq_mask = ~0; |
036a4a7d ZW |
1627 | |
1628 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1ec14ad3 | 1629 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
881f47b6 | 1630 | |
1ec14ad3 CW |
1631 | if (IS_GEN6(dev)) |
1632 | render_irqs = | |
1633 | GT_USER_INTERRUPT | | |
1634 | GT_GEN6_BSD_USER_INTERRUPT | | |
1635 | GT_BLT_USER_INTERRUPT; | |
1636 | else | |
1637 | render_irqs = | |
88f23b8f | 1638 | GT_USER_INTERRUPT | |
c6df541c | 1639 | GT_PIPE_NOTIFY | |
1ec14ad3 CW |
1640 | GT_BSD_USER_INTERRUPT; |
1641 | I915_WRITE(GTIER, render_irqs); | |
3143a2bf | 1642 | POSTING_READ(GTIER); |
036a4a7d | 1643 | |
2d7b8366 YL |
1644 | if (HAS_PCH_CPT(dev)) { |
1645 | hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | | |
1646 | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; | |
1647 | } else { | |
1648 | hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | |
1649 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
776ad806 | 1650 | hotplug_mask |= SDE_AUX_MASK | SDE_FDI_MASK | SDE_TRANS_MASK; |
9db4a9c7 JB |
1651 | for_each_pipe(pipe) |
1652 | I915_WRITE(FDI_RX_IMR(pipe), 0); | |
2d7b8366 YL |
1653 | } |
1654 | ||
1ec14ad3 | 1655 | dev_priv->pch_irq_mask = ~hotplug_mask; |
c650156a ZW |
1656 | |
1657 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1ec14ad3 CW |
1658 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask); |
1659 | I915_WRITE(SDEIER, hotplug_mask); | |
3143a2bf | 1660 | POSTING_READ(SDEIER); |
c650156a | 1661 | |
f97108d1 JB |
1662 | if (IS_IRONLAKE_M(dev)) { |
1663 | /* Clear & enable PCU event interrupts */ | |
1664 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1665 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1666 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1667 | } | |
1668 | ||
036a4a7d ZW |
1669 | return 0; |
1670 | } | |
1671 | ||
84b1fd10 | 1672 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1673 | { |
1674 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1675 | int pipe; |
1da177e4 | 1676 | |
79e53945 | 1677 | atomic_set(&dev_priv->irq_received, 0); |
b0b544cd | 1678 | atomic_set(&dev_priv->vblank_enabled, 0); |
79e53945 | 1679 | |
036a4a7d | 1680 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1681 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
b0b544cd | 1682 | INIT_WORK(&dev_priv->vblank_work, i915_vblank_work_func); |
036a4a7d | 1683 | |
bad720ff | 1684 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1685 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1686 | return; |
1687 | } | |
1688 | ||
5ca58282 JB |
1689 | if (I915_HAS_HOTPLUG(dev)) { |
1690 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1691 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1692 | } | |
1693 | ||
0a3e67a4 | 1694 | I915_WRITE(HWSTAM, 0xeffe); |
9db4a9c7 JB |
1695 | for_each_pipe(pipe) |
1696 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 1697 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1698 | I915_WRITE(IER, 0x0); |
3143a2bf | 1699 | POSTING_READ(IER); |
1da177e4 LT |
1700 | } |
1701 | ||
b01f2c3a JB |
1702 | /* |
1703 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1704 | * enabled correctly. | |
1705 | */ | |
0a3e67a4 | 1706 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1707 | { |
1708 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1709 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1710 | u32 error_mask; |
0a3e67a4 | 1711 | |
1ec14ad3 | 1712 | DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue); |
d1b851fc | 1713 | if (HAS_BSD(dev)) |
1ec14ad3 | 1714 | DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue); |
549f7365 | 1715 | if (HAS_BLT(dev)) |
1ec14ad3 | 1716 | DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue); |
d1b851fc | 1717 | |
0a3e67a4 | 1718 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1719 | |
bad720ff | 1720 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1721 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1722 | |
7c463586 | 1723 | /* Unmask the interrupts that we always want on. */ |
1ec14ad3 | 1724 | dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX; |
7c463586 KP |
1725 | |
1726 | dev_priv->pipestat[0] = 0; | |
1727 | dev_priv->pipestat[1] = 0; | |
1728 | ||
5ca58282 | 1729 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1730 | /* Enable in IER... */ |
1731 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1732 | /* and unmask in IMR */ | |
1ec14ad3 | 1733 | dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1734 | } |
1735 | ||
63eeaf38 JB |
1736 | /* |
1737 | * Enable some error detection, note the instruction error mask | |
1738 | * bit is reserved, so we leave it masked. | |
1739 | */ | |
1740 | if (IS_G4X(dev)) { | |
1741 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1742 | GM45_ERROR_MEM_PRIV | | |
1743 | GM45_ERROR_CP_PRIV | | |
1744 | I915_ERROR_MEMORY_REFRESH); | |
1745 | } else { | |
1746 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1747 | I915_ERROR_MEMORY_REFRESH); | |
1748 | } | |
1749 | I915_WRITE(EMR, error_mask); | |
1750 | ||
1ec14ad3 | 1751 | I915_WRITE(IMR, dev_priv->irq_mask); |
c496fa1f | 1752 | I915_WRITE(IER, enable_mask); |
3143a2bf | 1753 | POSTING_READ(IER); |
ed4cb414 | 1754 | |
c496fa1f AJ |
1755 | if (I915_HAS_HOTPLUG(dev)) { |
1756 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1757 | ||
1758 | /* Note HDMI and DP share bits */ | |
1759 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1760 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1761 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1762 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1763 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1764 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1765 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1766 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1767 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1768 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1769 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1770 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1771 | |
1772 | /* Programming the CRT detection parameters tends | |
1773 | to generate a spurious hotplug event about three | |
1774 | seconds later. So just do it once. | |
1775 | */ | |
1776 | if (IS_G4X(dev)) | |
1777 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1778 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1779 | } | |
1780 | ||
c496fa1f AJ |
1781 | /* Ignore TV since it's buggy */ |
1782 | ||
1783 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1784 | } | |
1785 | ||
3b617967 | 1786 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
1787 | |
1788 | return 0; | |
1da177e4 LT |
1789 | } |
1790 | ||
f2b115e6 | 1791 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1792 | { |
1793 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1794 | I915_WRITE(HWSTAM, 0xffffffff); | |
1795 | ||
1796 | I915_WRITE(DEIMR, 0xffffffff); | |
1797 | I915_WRITE(DEIER, 0x0); | |
1798 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1799 | ||
1800 | I915_WRITE(GTIMR, 0xffffffff); | |
1801 | I915_WRITE(GTIER, 0x0); | |
1802 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1803 | } | |
1804 | ||
84b1fd10 | 1805 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1806 | { |
1807 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
9db4a9c7 | 1808 | int pipe; |
91e3738e | 1809 | |
1da177e4 LT |
1810 | if (!dev_priv) |
1811 | return; | |
1812 | ||
0a3e67a4 JB |
1813 | dev_priv->vblank_pipe = 0; |
1814 | ||
bad720ff | 1815 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1816 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1817 | return; |
1818 | } | |
1819 | ||
5ca58282 JB |
1820 | if (I915_HAS_HOTPLUG(dev)) { |
1821 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1822 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1823 | } | |
1824 | ||
0a3e67a4 | 1825 | I915_WRITE(HWSTAM, 0xffffffff); |
9db4a9c7 JB |
1826 | for_each_pipe(pipe) |
1827 | I915_WRITE(PIPESTAT(pipe), 0); | |
0a3e67a4 | 1828 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1829 | I915_WRITE(IER, 0x0); |
af6061af | 1830 | |
9db4a9c7 JB |
1831 | for_each_pipe(pipe) |
1832 | I915_WRITE(PIPESTAT(pipe), | |
1833 | I915_READ(PIPESTAT(pipe)) & 0x8000ffff); | |
7c463586 | 1834 | I915_WRITE(IIR, I915_READ(IIR)); |
1da177e4 | 1835 | } |