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drm/i915: add interface to simulate gpu hangs
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
036a4a7d 40/* For display hotplug interrupt */
995b6762 41static void
f2b115e6 42ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 43{
1ec14ad3
CW		 44 if ((dev_priv->irq_mask & mask) != 0) {
45 dev_priv->irq_mask &= ~mask;
46 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 47 POSTING_READ(DEIMR);
036a4a7d
ZW		 48 }
49}
50
51static inline void
f2b115e6 52ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 53{
1ec14ad3
CW		 54 if ((dev_priv->irq_mask & mask) != mask) {
55 dev_priv->irq_mask |= mask;
56 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 57 POSTING_READ(DEIMR);
036a4a7d
ZW		 58 }
59}
60
7c463586
KP		 61void
62i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
63{
64 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 65 u32 reg = PIPESTAT(pipe);
7c463586
KP		 66
67 dev_priv->pipestat[pipe] |= mask;
68 /* Enable the interrupt, clear any pending status */
69 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 70 POSTING_READ(reg);
7c463586
KP		 71 }
72}
73
74void
75i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
76{
77 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 78 u32 reg = PIPESTAT(pipe);
7c463586
KP		 79
80 dev_priv->pipestat[pipe] &= ~mask;
81 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 82 POSTING_READ(reg);
7c463586
KP		 83 }
84}
85
01c66889
ZY		 86/**
87 * intel_enable_asle - enable ASLE interrupt for OpRegion
88 */
1ec14ad3 89void intel_enable_asle(struct drm_device *dev)
01c66889 90{
1ec14ad3
CW		 91 drm_i915_private_t *dev_priv = dev->dev_private;
92 unsigned long irqflags;
93
7e231dbe
JB		 94 /* FIXME: opregion/asle for VLV */
95 if (IS_VALLEYVIEW(dev))
96 return;
97
1ec14ad3 98 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 99
c619eed4 100 if (HAS_PCH_SPLIT(dev))
f2b115e6 101 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 102 else {
01c66889 103 i915_enable_pipestat(dev_priv, 1,
d874bcff 104 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 105 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 106 i915_enable_pipestat(dev_priv, 0,
d874bcff 107 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 108 }
1ec14ad3
CW		 109
110 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 111}
112
0a3e67a4
JB		 113/**
114 * i915_pipe_enabled - check if a pipe is enabled
115 * @dev: DRM device
116 * @pipe: pipe to check
117 *
118 * Reading certain registers when the pipe is disabled can hang the chip.
119 * Use this routine to make sure the PLL is running and the pipe is active
120 * before reading such registers if unsure.
121 */
122static int
123i915_pipe_enabled(struct drm_device *dev, int pipe)
124{
125 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 126 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 127}
128
42f52ef8
KP		 129/* Called from drm generic code, passed a 'crtc', which
130 * we use as a pipe index
131 */
f71d4af4 132static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 133{
134 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
135 unsigned long high_frame;
136 unsigned long low_frame;
5eddb70b 137 u32 high1, high2, low;
0a3e67a4
JB		 138
139 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 140 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 141 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 142 return 0;
143 }
144
9db4a9c7
JB		 145 high_frame = PIPEFRAME(pipe);
146 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 147
0a3e67a4
JB		 148 /*
149 * High & low register fields aren't synchronized, so make sure
150 * we get a low value that's stable across two reads of the high
151 * register.
152 */
153 do {
5eddb70b
CW		 154 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
155 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
156 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 157 } while (high1 != high2);
158
5eddb70b
CW		 159 high1 >>= PIPE_FRAME_HIGH_SHIFT;
160 low >>= PIPE_FRAME_LOW_SHIFT;
161 return (high1 << 8) | low;
0a3e67a4
JB		 162}
163
f71d4af4 164static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 165{
166 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 167 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 168
169 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 170 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 171 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 172 return 0;
173 }
174
175 return I915_READ(reg);
176}
177
f71d4af4 178static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 179 int *vpos, int *hpos)
180{
181 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
182 u32 vbl = 0, position = 0;
183 int vbl_start, vbl_end, htotal, vtotal;
184 bool in_vbl = true;
185 int ret = 0;
186
187 if (!i915_pipe_enabled(dev, pipe)) {
188 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 189 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 190 return 0;
191 }
192
193 /* Get vtotal. */
194 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
195
196 if (INTEL_INFO(dev)->gen >= 4) {
197 /* No obvious pixelcount register. Only query vertical
198 * scanout position from Display scan line register.
199 */
200 position = I915_READ(PIPEDSL(pipe));
201
202 /* Decode into vertical scanout position. Don't have
203 * horizontal scanout position.
204 */
205 *vpos = position & 0x1fff;
206 *hpos = 0;
207 } else {
208 /* Have access to pixelcount since start of frame.
209 * We can split this into vertical and horizontal
210 * scanout position.
211 */
212 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
213
214 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
215 *vpos = position / htotal;
216 *hpos = position - (*vpos * htotal);
217 }
218
219 /* Query vblank area. */
220 vbl = I915_READ(VBLANK(pipe));
221
222 /* Test position against vblank region. */
223 vbl_start = vbl & 0x1fff;
224 vbl_end = (vbl >> 16) & 0x1fff;
225
226 if ((*vpos < vbl_start) || (*vpos > vbl_end))
227 in_vbl = false;
228
229 /* Inside "upper part" of vblank area? Apply corrective offset: */
230 if (in_vbl && (*vpos >= vbl_start))
231 *vpos = *vpos - vtotal;
232
233 /* Readouts valid? */
234 if (vbl > 0)
235 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
236
237 /* In vblank? */
238 if (in_vbl)
239 ret |= DRM_SCANOUTPOS_INVBL;
240
241 return ret;
242}
243
f71d4af4 244static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 245 int *max_error,
246 struct timeval *vblank_time,
247 unsigned flags)
248{
4041b853
CW		 249 struct drm_i915_private *dev_priv = dev->dev_private;
250 struct drm_crtc *crtc;
0af7e4df 251
4041b853
CW		 252 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
253 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 254 return -EINVAL;
255 }
256
257 /* Get drm_crtc to timestamp: */
4041b853
CW		 258 crtc = intel_get_crtc_for_pipe(dev, pipe);
259 if (crtc == NULL) {
260 DRM_ERROR("Invalid crtc %d\n", pipe);
261 return -EINVAL;
262 }
263
264 if (!crtc->enabled) {
265 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
266 return -EBUSY;
267 }
0af7e4df
MK		 268
269 /* Helper routine in DRM core does all the work: */
4041b853
CW		 270 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
271 vblank_time, flags,
272 crtc);
0af7e4df
MK		 273}
274
5ca58282
JB		 275/*
276 * Handle hotplug events outside the interrupt handler proper.
277 */
278static void i915_hotplug_work_func(struct work_struct *work)
279{
280 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
281 hotplug_work);
282 struct drm_device *dev = dev_priv->dev;
c31c4ba3 283 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 284 struct intel_encoder *encoder;
285
a65e34c7 286 mutex_lock(&mode_config->mutex);
e67189ab
JB		 287 DRM_DEBUG_KMS("running encoder hotplug functions\n");
288
4ef69c7a
CW		 289 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
290 if (encoder->hot_plug)
291 encoder->hot_plug(encoder);
292
40ee3381
KP		 293 mutex_unlock(&mode_config->mutex);
294
5ca58282 295 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 296 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 297}
298
f97108d1
JB		 299static void i915_handle_rps_change(struct drm_device *dev)
300{
301 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 302 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 303 u8 new_delay = dev_priv->cur_delay;
304
7648fa99 305 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 306 busy_up = I915_READ(RCPREVBSYTUPAVG);
307 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 308 max_avg = I915_READ(RCBMAXAVG);
309 min_avg = I915_READ(RCBMINAVG);
310
311 /* Handle RCS change request from hw */
b5b72e89 312 if (busy_up > max_avg) {
f97108d1
JB		 313 if (dev_priv->cur_delay != dev_priv->max_delay)
314 new_delay = dev_priv->cur_delay - 1;
315 if (new_delay < dev_priv->max_delay)
316 new_delay = dev_priv->max_delay;
b5b72e89 317 } else if (busy_down < min_avg) {
f97108d1
JB		 318 if (dev_priv->cur_delay != dev_priv->min_delay)
319 new_delay = dev_priv->cur_delay + 1;
320 if (new_delay > dev_priv->min_delay)
321 new_delay = dev_priv->min_delay;
322 }
323
7648fa99
JB		 324 if (ironlake_set_drps(dev, new_delay))
325 dev_priv->cur_delay = new_delay;
f97108d1
JB		 326
327 return;
328}
329
549f7365
CW		 330static void notify_ring(struct drm_device *dev,
331 struct intel_ring_buffer *ring)
332{
333 struct drm_i915_private *dev_priv = dev->dev_private;
9862e600 334
475553de
CW		 335 if (ring->obj == NULL)
336 return;
337
6d171cb4 338 trace_i915_gem_request_complete(ring, ring->get_seqno(ring));
9862e600 339
549f7365 340 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 341 if (i915_enable_hangcheck) {
342 dev_priv->hangcheck_count = 0;
343 mod_timer(&dev_priv->hangcheck_timer,
344 jiffies +
345 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
346 }
549f7365
CW		 347}
348
4912d041 349static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 350{
4912d041
BW		 351 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
352 rps_work);
3b8d8d91 353 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 354 u32 pm_iir, pm_imr;
355
356 spin_lock_irq(&dev_priv->rps_lock);
357 pm_iir = dev_priv->pm_iir;
358 dev_priv->pm_iir = 0;
359 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 360 I915_WRITE(GEN6_PMIMR, 0);
4912d041 361 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 362
3b8d8d91
JB		 363 if (!pm_iir)
364 return;
365
4912d041 366 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 367 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
368 if (dev_priv->cur_delay != dev_priv->max_delay)
369 new_delay = dev_priv->cur_delay + 1;
370 if (new_delay > dev_priv->max_delay)
371 new_delay = dev_priv->max_delay;
372 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 373 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 374 if (dev_priv->cur_delay != dev_priv->min_delay)
375 new_delay = dev_priv->cur_delay - 1;
376 if (new_delay < dev_priv->min_delay) {
377 new_delay = dev_priv->min_delay;
378 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
379 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
380 ((new_delay << 16) & 0x3f0000));
381 } else {
382 /* Make sure we continue to get down interrupts
383 * until we hit the minimum frequency */
384 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
385 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
386 }
4912d041 387 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 388 }
389
4912d041 390 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 391 dev_priv->cur_delay = new_delay;
392
4912d041
BW		 393 /*
394 * rps_lock not held here because clearing is non-destructive. There is
395 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
396 * by holding struct_mutex for the duration of the write.
397 */
4912d041 398 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399}
400
e7b4c6b1
DV		 401static void snb_gt_irq_handler(struct drm_device *dev,
402 struct drm_i915_private *dev_priv,
403 u32 gt_iir)
404{
405
406 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
407 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
408 notify_ring(dev, &dev_priv->ring[RCS]);
409 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
410 notify_ring(dev, &dev_priv->ring[VCS]);
411 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
412 notify_ring(dev, &dev_priv->ring[BCS]);
413
414 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
415 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
416 GT_RENDER_CS_ERROR_INTERRUPT)) {
417 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
418 i915_handle_error(dev, false);
419 }
420}
421
fc6826d1
CW		 422static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
423 u32 pm_iir)
424{
425 unsigned long flags;
426
427 /*
428 * IIR bits should never already be set because IMR should
429 * prevent an interrupt from being shown in IIR. The warning
430 * displays a case where we've unsafely cleared
431 * dev_priv->pm_iir. Although missing an interrupt of the same
432 * type is not a problem, it displays a problem in the logic.
433 *
434 * The mask bit in IMR is cleared by rps_work.
435 */
436
437 spin_lock_irqsave(&dev_priv->rps_lock, flags);
438 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
439 dev_priv->pm_iir |= pm_iir;
440 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
441 POSTING_READ(GEN6_PMIMR);
442 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
443
444 queue_work(dev_priv->wq, &dev_priv->rps_work);
445}
446
7e231dbe
JB		 447static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
448{
449 struct drm_device *dev = (struct drm_device *) arg;
450 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
451 u32 iir, gt_iir, pm_iir;
452 irqreturn_t ret = IRQ_NONE;
453 unsigned long irqflags;
454 int pipe;
455 u32 pipe_stats[I915_MAX_PIPES];
456 u32 vblank_status;
457 int vblank = 0;
458 bool blc_event;
459
460 atomic_inc(&dev_priv->irq_received);
461
462 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
463 PIPE_VBLANK_INTERRUPT_STATUS;
464
465 while (true) {
466 iir = I915_READ(VLV_IIR);
467 gt_iir = I915_READ(GTIIR);
468 pm_iir = I915_READ(GEN6_PMIIR);
469
470 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
471 goto out;
472
473 ret = IRQ_HANDLED;
474
e7b4c6b1 475 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 476
477 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
478 for_each_pipe(pipe) {
479 int reg = PIPESTAT(pipe);
480 pipe_stats[pipe] = I915_READ(reg);
481
482 /*
483 * Clear the PIPE*STAT regs before the IIR
484 */
485 if (pipe_stats[pipe] & 0x8000ffff) {
486 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
487 DRM_DEBUG_DRIVER("pipe %c underrun\n",
488 pipe_name(pipe));
489 I915_WRITE(reg, pipe_stats[pipe]);
490 }
491 }
492 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
493
494 /* Consume port. Then clear IIR or we'll miss events */
495 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
496 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
497
498 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
499 hotplug_status);
500 if (hotplug_status & dev_priv->hotplug_supported_mask)
501 queue_work(dev_priv->wq,
502 &dev_priv->hotplug_work);
503
504 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
505 I915_READ(PORT_HOTPLUG_STAT);
506 }
507
508
509 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
510 drm_handle_vblank(dev, 0);
511 vblank++;
e0f608d7 512 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 513 }
514
515 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
516 drm_handle_vblank(dev, 1);
517 vblank++;
e0f608d7 518 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 519 }
520
521 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
522 blc_event = true;
523
fc6826d1
CW		 524 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
525 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 526
527 I915_WRITE(GTIIR, gt_iir);
528 I915_WRITE(GEN6_PMIIR, pm_iir);
529 I915_WRITE(VLV_IIR, iir);
530 }
531
532out:
533 return ret;
534}
535
776ad806
JB		 536static void pch_irq_handler(struct drm_device *dev)
537{
538 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
539 u32 pch_iir;
9db4a9c7 540 int pipe;
776ad806
JB		 541
542 pch_iir = I915_READ(SDEIIR);
543
544 if (pch_iir & SDE_AUDIO_POWER_MASK)
545 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
546 (pch_iir & SDE_AUDIO_POWER_MASK) >>
547 SDE_AUDIO_POWER_SHIFT);
548
549 if (pch_iir & SDE_GMBUS)
550 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
551
552 if (pch_iir & SDE_AUDIO_HDCP_MASK)
553 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
554
555 if (pch_iir & SDE_AUDIO_TRANS_MASK)
556 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
557
558 if (pch_iir & SDE_POISON)
559 DRM_ERROR("PCH poison interrupt\n");
560
9db4a9c7
JB		 561 if (pch_iir & SDE_FDI_MASK)
562 for_each_pipe(pipe)
563 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
564 pipe_name(pipe),
565 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 566
567 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
568 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
569
570 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
571 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
572
573 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
574 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
575 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
576 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
577}
578
f71d4af4 579static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 580{
581 struct drm_device *dev = (struct drm_device *) arg;
582 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
583 int ret = IRQ_NONE;
584 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
b1f14ad0
JB		 585
586 atomic_inc(&dev_priv->irq_received);
587
588 /* disable master interrupt before clearing iir */
589 de_ier = I915_READ(DEIER);
590 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
591 POSTING_READ(DEIER);
592
593 de_iir = I915_READ(DEIIR);
594 gt_iir = I915_READ(GTIIR);
595 pch_iir = I915_READ(SDEIIR);
596 pm_iir = I915_READ(GEN6_PMIIR);
597
598 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
599 goto done;
600
601 ret = IRQ_HANDLED;
602
e7b4c6b1 603 snb_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 604
605 if (de_iir & DE_GSE_IVB)
606 intel_opregion_gse_intr(dev);
607
608 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
609 intel_prepare_page_flip(dev, 0);
610 intel_finish_page_flip_plane(dev, 0);
611 }
612
613 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
614 intel_prepare_page_flip(dev, 1);
615 intel_finish_page_flip_plane(dev, 1);
616 }
617
618 if (de_iir & DE_PIPEA_VBLANK_IVB)
619 drm_handle_vblank(dev, 0);
620
f6b07f45 621 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 622 drm_handle_vblank(dev, 1);
623
624 /* check event from PCH */
625 if (de_iir & DE_PCH_EVENT_IVB) {
626 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
627 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
628 pch_irq_handler(dev);
629 }
630
fc6826d1
CW		 631 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
632 gen6_queue_rps_work(dev_priv, pm_iir);
b1f14ad0
JB		 633
634 /* should clear PCH hotplug event before clear CPU irq */
635 I915_WRITE(SDEIIR, pch_iir);
636 I915_WRITE(GTIIR, gt_iir);
637 I915_WRITE(DEIIR, de_iir);
638 I915_WRITE(GEN6_PMIIR, pm_iir);
639
640done:
641 I915_WRITE(DEIER, de_ier);
642 POSTING_READ(DEIER);
643
644 return ret;
645}
646
e7b4c6b1
DV		 647static void ilk_gt_irq_handler(struct drm_device *dev,
648 struct drm_i915_private *dev_priv,
649 u32 gt_iir)
650{
651 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
652 notify_ring(dev, &dev_priv->ring[RCS]);
653 if (gt_iir & GT_BSD_USER_INTERRUPT)
654 notify_ring(dev, &dev_priv->ring[VCS]);
655}
656
f71d4af4 657static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 658{
4697995b 659 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 660 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
661 int ret = IRQ_NONE;
3b8d8d91 662 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 663 u32 hotplug_mask;
881f47b6 664
4697995b
JB		 665 atomic_inc(&dev_priv->irq_received);
666
2d109a84
ZN		 667 /* disable master interrupt before clearing iir */
668 de_ier = I915_READ(DEIER);
669 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 670 POSTING_READ(DEIER);
2d109a84 671
036a4a7d
ZW		 672 de_iir = I915_READ(DEIIR);
673 gt_iir = I915_READ(GTIIR);
c650156a 674 pch_iir = I915_READ(SDEIIR);
3b8d8d91 675 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 676
3b8d8d91
JB		 677 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
678 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 679 goto done;
036a4a7d 680
2d7b8366
YL		 681 if (HAS_PCH_CPT(dev))
682 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
683 else
684 hotplug_mask = SDE_HOTPLUG_MASK;
685
c7c85101 686 ret = IRQ_HANDLED;
036a4a7d 687
e7b4c6b1
DV		 688 if (IS_GEN5(dev))
689 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
690 else
691 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 692
c7c85101 693 if (de_iir & DE_GSE)
3b617967 694 intel_opregion_gse_intr(dev);
c650156a 695
f072d2e7 696 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 697 intel_prepare_page_flip(dev, 0);
2bbda389 698 intel_finish_page_flip_plane(dev, 0);
f072d2e7 699 }
013d5aa2 700
f072d2e7 701 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 702 intel_prepare_page_flip(dev, 1);
2bbda389 703 intel_finish_page_flip_plane(dev, 1);
f072d2e7 704 }
013d5aa2 705
f072d2e7 706 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 707 drm_handle_vblank(dev, 0);
708
f072d2e7 709 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 710 drm_handle_vblank(dev, 1);
711
c7c85101 712 /* check event from PCH */
776ad806
JB		 713 if (de_iir & DE_PCH_EVENT) {
714 if (pch_iir & hotplug_mask)
715 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
716 pch_irq_handler(dev);
717 }
036a4a7d 718
f97108d1 719 if (de_iir & DE_PCU_EVENT) {
7648fa99 720 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 721 i915_handle_rps_change(dev);
722 }
723
fc6826d1
CW		 724 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
725 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 726
c7c85101
ZN		 727 /* should clear PCH hotplug event before clear CPU irq */
728 I915_WRITE(SDEIIR, pch_iir);
729 I915_WRITE(GTIIR, gt_iir);
730 I915_WRITE(DEIIR, de_iir);
4912d041 731 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 732
733done:
2d109a84 734 I915_WRITE(DEIER, de_ier);
3143a2bf 735 POSTING_READ(DEIER);
2d109a84 736
036a4a7d
ZW		 737 return ret;
738}
739
8a905236
JB		 740/**
741 * i915_error_work_func - do process context error handling work
742 * @work: work struct
743 *
744 * Fire an error uevent so userspace can see that a hang or error
745 * was detected.
746 */
747static void i915_error_work_func(struct work_struct *work)
748{
749 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
750 error_work);
751 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 752 char *error_event[] = { "ERROR=1", NULL };
753 char *reset_event[] = { "RESET=1", NULL };
754 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 755
f316a42c
BG		 756 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
757
ba1234d1 758 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 759 DRM_DEBUG_DRIVER("resetting chip\n");
760 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
761 if (!i915_reset(dev, GRDOM_RENDER)) {
762 atomic_set(&dev_priv->mm.wedged, 0);
763 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 764 }
30dbf0c0 765 complete_all(&dev_priv->error_completion);
f316a42c 766 }
8a905236
JB		 767}
768
3bd3c932 769#ifdef CONFIG_DEBUG_FS
9df30794 770static struct drm_i915_error_object *
bcfb2e28 771i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 772 struct drm_i915_gem_object *src)
9df30794
CW		 773{
774 struct drm_i915_error_object *dst;
9df30794 775 int page, page_count;
e56660dd 776 u32 reloc_offset;
9df30794 777
05394f39 778 if (src == NULL || src->pages == NULL)
9df30794
CW		 779 return NULL;
780
05394f39 781 page_count = src->base.size / PAGE_SIZE;
9df30794 782
0206e353 783 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 784 if (dst == NULL)
785 return NULL;
786
05394f39 787 reloc_offset = src->gtt_offset;
9df30794 788 for (page = 0; page < page_count; page++) {
788885ae 789 unsigned long flags;
e56660dd 790 void *d;
788885ae 791
e56660dd 792 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 793 if (d == NULL)
794 goto unwind;
e56660dd 795
788885ae 796 local_irq_save(flags);
74898d7e
DV		 797 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
798 src->has_global_gtt_mapping) {
172975aa
CW		 799 void __iomem *s;
800
801 /* Simply ignore tiling or any overlapping fence.
802 * It's part of the error state, and this hopefully
803 * captures what the GPU read.
804 */
805
806 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
807 reloc_offset);
808 memcpy_fromio(d, s, PAGE_SIZE);
809 io_mapping_unmap_atomic(s);
810 } else {
811 void *s;
812
813 drm_clflush_pages(&src->pages[page], 1);
814
815 s = kmap_atomic(src->pages[page]);
816 memcpy(d, s, PAGE_SIZE);
817 kunmap_atomic(s);
818
819 drm_clflush_pages(&src->pages[page], 1);
820 }
788885ae 821 local_irq_restore(flags);
e56660dd 822
9df30794 823 dst->pages[page] = d;
e56660dd
CW		 824
825 reloc_offset += PAGE_SIZE;
9df30794
CW		 826 }
827 dst->page_count = page_count;
05394f39 828 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 829
830 return dst;
831
832unwind:
833 while (page--)
834 kfree(dst->pages[page]);
835 kfree(dst);
836 return NULL;
837}
838
839static void
840i915_error_object_free(struct drm_i915_error_object *obj)
841{
842 int page;
843
844 if (obj == NULL)
845 return;
846
847 for (page = 0; page < obj->page_count; page++)
848 kfree(obj->pages[page]);
849
850 kfree(obj);
851}
852
853static void
854i915_error_state_free(struct drm_device *dev,
855 struct drm_i915_error_state *error)
856{
e2f973d5
CW		 857 int i;
858
52d39a21
CW		 859 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
860 i915_error_object_free(error->ring[i].batchbuffer);
861 i915_error_object_free(error->ring[i].ringbuffer);
862 kfree(error->ring[i].requests);
863 }
e2f973d5 864
9df30794 865 kfree(error->active_bo);
6ef3d427 866 kfree(error->overlay);
9df30794
CW		 867 kfree(error);
868}
1b50247a
CW		 869static void capture_bo(struct drm_i915_error_buffer *err,
870 struct drm_i915_gem_object *obj)
871{
872 err->size = obj->base.size;
873 err->name = obj->base.name;
874 err->seqno = obj->last_rendering_seqno;
875 err->gtt_offset = obj->gtt_offset;
876 err->read_domains = obj->base.read_domains;
877 err->write_domain = obj->base.write_domain;
878 err->fence_reg = obj->fence_reg;
879 err->pinned = 0;
880 if (obj->pin_count > 0)
881 err->pinned = 1;
882 if (obj->user_pin_count > 0)
883 err->pinned = -1;
884 err->tiling = obj->tiling_mode;
885 err->dirty = obj->dirty;
886 err->purgeable = obj->madv != I915_MADV_WILLNEED;
887 err->ring = obj->ring ? obj->ring->id : -1;
888 err->cache_level = obj->cache_level;
889}
9df30794 890
1b50247a
CW		 891static u32 capture_active_bo(struct drm_i915_error_buffer *err,
892 int count, struct list_head *head)
c724e8a9
CW		 893{
894 struct drm_i915_gem_object *obj;
895 int i = 0;
896
897 list_for_each_entry(obj, head, mm_list) {
1b50247a 898 capture_bo(err++, obj);
c724e8a9
CW		 899 if (++i == count)
900 break;
1b50247a
CW		 901 }
902
903 return i;
904}
905
906static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
907 int count, struct list_head *head)
908{
909 struct drm_i915_gem_object *obj;
910 int i = 0;
911
912 list_for_each_entry(obj, head, gtt_list) {
913 if (obj->pin_count == 0)
914 continue;
c724e8a9 915
1b50247a
CW		 916 capture_bo(err++, obj);
917 if (++i == count)
918 break;
c724e8a9
CW		 919 }
920
921 return i;
922}
923
748ebc60
CW		 924static void i915_gem_record_fences(struct drm_device *dev,
925 struct drm_i915_error_state *error)
926{
927 struct drm_i915_private *dev_priv = dev->dev_private;
928 int i;
929
930 /* Fences */
931 switch (INTEL_INFO(dev)->gen) {
775d17b6 932 case 7:
748ebc60
CW		 933 case 6:
934 for (i = 0; i < 16; i++)
935 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
936 break;
937 case 5:
938 case 4:
939 for (i = 0; i < 16; i++)
940 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
941 break;
942 case 3:
943 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
944 for (i = 0; i < 8; i++)
945 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
946 case 2:
947 for (i = 0; i < 8; i++)
948 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
949 break;
950
951 }
952}
953
bcfb2e28
CW		 954static struct drm_i915_error_object *
955i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
956 struct intel_ring_buffer *ring)
957{
958 struct drm_i915_gem_object *obj;
959 u32 seqno;
960
961 if (!ring->get_seqno)
962 return NULL;
963
964 seqno = ring->get_seqno(ring);
965 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
966 if (obj->ring != ring)
967 continue;
968
c37d9a5d 969 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 970 continue;
971
972 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
973 continue;
974
975 /* We need to copy these to an anonymous buffer as the simplest
976 * method to avoid being overwritten by userspace.
977 */
978 return i915_error_object_create(dev_priv, obj);
979 }
980
981 return NULL;
982}
983
d27b1e0e
DV		 984static void i915_record_ring_state(struct drm_device *dev,
985 struct drm_i915_error_state *error,
986 struct intel_ring_buffer *ring)
987{
988 struct drm_i915_private *dev_priv = dev->dev_private;
989
33f3f518 990 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 991 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 992 error->semaphore_mboxes[ring->id][0]
993 = I915_READ(RING_SYNC_0(ring->mmio_base));
994 error->semaphore_mboxes[ring->id][1]
995 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 996 }
c1cd90ed 997
d27b1e0e 998 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 999 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1000 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1001 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1002 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1003 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1004 if (ring->id == RCS) {
d27b1e0e
DV		 1005 error->instdone1 = I915_READ(INSTDONE1);
1006 error->bbaddr = I915_READ64(BB_ADDR);
1007 }
1008 } else {
9d2f41fa 1009 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1010 error->ipeir[ring->id] = I915_READ(IPEIR);
1011 error->ipehr[ring->id] = I915_READ(IPEHR);
1012 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1013 }
1014
9574b3fe 1015 error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
c1cd90ed 1016 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1017 error->seqno[ring->id] = ring->get_seqno(ring);
1018 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1019 error->head[ring->id] = I915_READ_HEAD(ring);
1020 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1021
1022 error->cpu_ring_head[ring->id] = ring->head;
1023 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1024}
1025
52d39a21
CW		 1026static void i915_gem_record_rings(struct drm_device *dev,
1027 struct drm_i915_error_state *error)
1028{
1029 struct drm_i915_private *dev_priv = dev->dev_private;
1030 struct drm_i915_gem_request *request;
1031 int i, count;
1032
1033 for (i = 0; i < I915_NUM_RINGS; i++) {
1034 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1035
1036 if (ring->obj == NULL)
1037 continue;
1038
1039 i915_record_ring_state(dev, error, ring);
1040
1041 error->ring[i].batchbuffer =
1042 i915_error_first_batchbuffer(dev_priv, ring);
1043
1044 error->ring[i].ringbuffer =
1045 i915_error_object_create(dev_priv, ring->obj);
1046
1047 count = 0;
1048 list_for_each_entry(request, &ring->request_list, list)
1049 count++;
1050
1051 error->ring[i].num_requests = count;
1052 error->ring[i].requests =
1053 kmalloc(count*sizeof(struct drm_i915_error_request),
1054 GFP_ATOMIC);
1055 if (error->ring[i].requests == NULL) {
1056 error->ring[i].num_requests = 0;
1057 continue;
1058 }
1059
1060 count = 0;
1061 list_for_each_entry(request, &ring->request_list, list) {
1062 struct drm_i915_error_request *erq;
1063
1064 erq = &error->ring[i].requests[count++];
1065 erq->seqno = request->seqno;
1066 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1067 erq->tail = request->tail;
52d39a21
CW		 1068 }
1069 }
1070}
1071
8a905236
JB		 1072/**
1073 * i915_capture_error_state - capture an error record for later analysis
1074 * @dev: drm device
1075 *
1076 * Should be called when an error is detected (either a hang or an error
1077 * interrupt) to capture error state from the time of the error. Fills
1078 * out a structure which becomes available in debugfs for user level tools
1079 * to pick up.
1080 */
63eeaf38
JB		 1081static void i915_capture_error_state(struct drm_device *dev)
1082{
1083 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1084 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1085 struct drm_i915_error_state *error;
1086 unsigned long flags;
9db4a9c7 1087 int i, pipe;
63eeaf38
JB		 1088
1089 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1090 error = dev_priv->first_error;
1091 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1092 if (error)
1093 return;
63eeaf38 1094
9db4a9c7 1095 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1096 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1097 if (!error) {
9df30794
CW		 1098 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1099 return;
63eeaf38
JB		 1100 }
1101
b6f7833b
CW		 1102 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1103 dev->primary->index);
2fa772f3 1104
63eeaf38
JB		 1105 error->eir = I915_READ(EIR);
1106 error->pgtbl_er = I915_READ(PGTBL_ER);
be998e2e
BW		 1107
1108 if (HAS_PCH_SPLIT(dev))
1109 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1110 else if (IS_VALLEYVIEW(dev))
1111 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1112 else if (IS_GEN2(dev))
1113 error->ier = I915_READ16(IER);
1114 else
1115 error->ier = I915_READ(IER);
1116
9db4a9c7
JB		 1117 for_each_pipe(pipe)
1118 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1119
33f3f518 1120 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1121 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1122 error->done_reg = I915_READ(DONE_REG);
1123 }
d27b1e0e 1124
748ebc60 1125 i915_gem_record_fences(dev, error);
52d39a21 1126 i915_gem_record_rings(dev, error);
9df30794 1127
c724e8a9 1128 /* Record buffers on the active and pinned lists. */
9df30794 1129 error->active_bo = NULL;
c724e8a9 1130 error->pinned_bo = NULL;
9df30794 1131
bcfb2e28
CW		 1132 i = 0;
1133 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1134 i++;
1135 error->active_bo_count = i;
1b50247a
CW		 1136 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1137 if (obj->pin_count)
1138 i++;
bcfb2e28 1139 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1140
8e934dbf
CW		 1141 error->active_bo = NULL;
1142 error->pinned_bo = NULL;
bcfb2e28
CW		 1143 if (i) {
1144 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1145 GFP_ATOMIC);
c724e8a9
CW		 1146 if (error->active_bo)
1147 error->pinned_bo =
1148 error->active_bo + error->active_bo_count;
9df30794
CW		 1149 }
1150
c724e8a9
CW		 1151 if (error->active_bo)
1152 error->active_bo_count =
1b50247a
CW		 1153 capture_active_bo(error->active_bo,
1154 error->active_bo_count,
1155 &dev_priv->mm.active_list);
c724e8a9
CW		 1156
1157 if (error->pinned_bo)
1158 error->pinned_bo_count =
1b50247a
CW		 1159 capture_pinned_bo(error->pinned_bo,
1160 error->pinned_bo_count,
1161 &dev_priv->mm.gtt_list);
c724e8a9 1162
9df30794
CW		 1163 do_gettimeofday(&error->time);
1164
6ef3d427 1165 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1166 error->display = intel_display_capture_error_state(dev);
6ef3d427 1167
9df30794
CW		 1168 spin_lock_irqsave(&dev_priv->error_lock, flags);
1169 if (dev_priv->first_error == NULL) {
1170 dev_priv->first_error = error;
1171 error = NULL;
1172 }
63eeaf38 1173 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1174
1175 if (error)
1176 i915_error_state_free(dev, error);
1177}
1178
1179void i915_destroy_error_state(struct drm_device *dev)
1180{
1181 struct drm_i915_private *dev_priv = dev->dev_private;
1182 struct drm_i915_error_state *error;
6dc0e816 1183 unsigned long flags;
9df30794 1184
6dc0e816 1185 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1186 error = dev_priv->first_error;
1187 dev_priv->first_error = NULL;
6dc0e816 1188 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1189
1190 if (error)
1191 i915_error_state_free(dev, error);
63eeaf38 1192}
3bd3c932
CW		 1193#else
1194#define i915_capture_error_state(x)
1195#endif
63eeaf38 1196
35aed2e6 1197static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1198{
1199 struct drm_i915_private *dev_priv = dev->dev_private;
1200 u32 eir = I915_READ(EIR);
9db4a9c7 1201 int pipe;
8a905236 1202
35aed2e6
CW		 1203 if (!eir)
1204 return;
8a905236 1205
a70491cc 1206 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1207
1208 if (IS_G4X(dev)) {
1209 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1210 u32 ipeir = I915_READ(IPEIR_I965);
1211
a70491cc
JP		 1212 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1213 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1214 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1215 I915_READ(INSTDONE_I965));
a70491cc
JP		 1216 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1217 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1218 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1219 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1220 POSTING_READ(IPEIR_I965);
8a905236
JB		 1221 }
1222 if (eir & GM45_ERROR_PAGE_TABLE) {
1223 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1224 pr_err("page table error\n");
1225 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1226 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1227 POSTING_READ(PGTBL_ER);
8a905236
JB		 1228 }
1229 }
1230
a6c45cf0 1231 if (!IS_GEN2(dev)) {
8a905236
JB		 1232 if (eir & I915_ERROR_PAGE_TABLE) {
1233 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1234 pr_err("page table error\n");
1235 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1236 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1237 POSTING_READ(PGTBL_ER);
8a905236
JB		 1238 }
1239 }
1240
1241 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1242 pr_err("memory refresh error:\n");
9db4a9c7 1243 for_each_pipe(pipe)
a70491cc 1244 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1245 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1246 /* pipestat has already been acked */
1247 }
1248 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1249 pr_err("instruction error\n");
1250 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1251 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1252 u32 ipeir = I915_READ(IPEIR);
1253
a70491cc
JP		 1254 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1255 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1256 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1257 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1258 I915_WRITE(IPEIR, ipeir);
3143a2bf 1259 POSTING_READ(IPEIR);
8a905236
JB		 1260 } else {
1261 u32 ipeir = I915_READ(IPEIR_I965);
1262
a70491cc
JP		 1263 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1264 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1265 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1266 I915_READ(INSTDONE_I965));
a70491cc
JP		 1267 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1268 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1269 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1270 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1271 POSTING_READ(IPEIR_I965);
8a905236
JB		 1272 }
1273 }
1274
1275 I915_WRITE(EIR, eir);
3143a2bf 1276 POSTING_READ(EIR);
8a905236
JB		 1277 eir = I915_READ(EIR);
1278 if (eir) {
1279 /*
1280 * some errors might have become stuck,
1281 * mask them.
1282 */
1283 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1284 I915_WRITE(EMR, I915_READ(EMR) | eir);
1285 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1286 }
35aed2e6
CW		 1287}
1288
1289/**
1290 * i915_handle_error - handle an error interrupt
1291 * @dev: drm device
1292 *
1293 * Do some basic checking of regsiter state at error interrupt time and
1294 * dump it to the syslog. Also call i915_capture_error_state() to make
1295 * sure we get a record and make it available in debugfs. Fire a uevent
1296 * so userspace knows something bad happened (should trigger collection
1297 * of a ring dump etc.).
1298 */
527f9e90 1299void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1300{
1301 struct drm_i915_private *dev_priv = dev->dev_private;
1302
1303 i915_capture_error_state(dev);
1304 i915_report_and_clear_eir(dev);
8a905236 1305
ba1234d1 1306 if (wedged) {
30dbf0c0 1307 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1308 atomic_set(&dev_priv->mm.wedged, 1);
1309
11ed50ec
BG		 1310 /*
1311 * Wakeup waiting processes so they don't hang
1312 */
1ec14ad3 1313 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1314 if (HAS_BSD(dev))
1ec14ad3 1315 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1316 if (HAS_BLT(dev))
1ec14ad3 1317 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1318 }
1319
9c9fe1f8 1320 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1321}
1322
4e5359cd
SF		 1323static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1324{
1325 drm_i915_private_t *dev_priv = dev->dev_private;
1326 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1328 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1329 struct intel_unpin_work *work;
1330 unsigned long flags;
1331 bool stall_detected;
1332
1333 /* Ignore early vblank irqs */
1334 if (intel_crtc == NULL)
1335 return;
1336
1337 spin_lock_irqsave(&dev->event_lock, flags);
1338 work = intel_crtc->unpin_work;
1339
1340 if (work == NULL || work->pending || !work->enable_stall_check) {
1341 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1342 spin_unlock_irqrestore(&dev->event_lock, flags);
1343 return;
1344 }
1345
1346 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1347 obj = work->pending_flip_obj;
a6c45cf0 1348 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1349 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1350 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1351 obj->gtt_offset;
4e5359cd 1352 } else {
9db4a9c7 1353 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1354 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1355 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1356 crtc->x * crtc->fb->bits_per_pixel/8);
1357 }
1358
1359 spin_unlock_irqrestore(&dev->event_lock, flags);
1360
1361 if (stall_detected) {
1362 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1363 intel_prepare_page_flip(dev, intel_crtc->plane);
1364 }
1365}
1366
42f52ef8
KP		 1367/* Called from drm generic code, passed 'crtc' which
1368 * we use as a pipe index
1369 */
f71d4af4 1370static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1371{
1372 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1373 unsigned long irqflags;
71e0ffa5 1374
5eddb70b 1375 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1376 return -EINVAL;
0a3e67a4 1377
1ec14ad3 1378 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1379 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1380 i915_enable_pipestat(dev_priv, pipe,
1381 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1382 else
7c463586
KP		 1383 i915_enable_pipestat(dev_priv, pipe,
1384 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1385
1386 /* maintain vblank delivery even in deep C-states */
1387 if (dev_priv->info->gen == 3)
6b26c86d 1388 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1389 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1390
0a3e67a4
JB		 1391 return 0;
1392}
1393
f71d4af4 1394static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1395{
1396 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1397 unsigned long irqflags;
1398
1399 if (!i915_pipe_enabled(dev, pipe))
1400 return -EINVAL;
1401
1402 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1403 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1404 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1405 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1406
1407 return 0;
1408}
1409
f71d4af4 1410static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1411{
1412 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1413 unsigned long irqflags;
1414
1415 if (!i915_pipe_enabled(dev, pipe))
1416 return -EINVAL;
1417
1418 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1419 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1420 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1421 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1422
1423 return 0;
1424}
1425
7e231dbe
JB		 1426static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1427{
1428 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1429 unsigned long irqflags;
1430 u32 dpfl, imr;
1431
1432 if (!i915_pipe_enabled(dev, pipe))
1433 return -EINVAL;
1434
1435 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1436 dpfl = I915_READ(VLV_DPFLIPSTAT);
1437 imr = I915_READ(VLV_IMR);
1438 if (pipe == 0) {
1439 dpfl |= PIPEA_VBLANK_INT_EN;
1440 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1441 } else {
1442 dpfl |= PIPEA_VBLANK_INT_EN;
1443 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1444 }
1445 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1446 I915_WRITE(VLV_IMR, imr);
1447 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1448
1449 return 0;
1450}
1451
42f52ef8
KP		 1452/* Called from drm generic code, passed 'crtc' which
1453 * we use as a pipe index
1454 */
f71d4af4 1455static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1456{
1457 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1458 unsigned long irqflags;
0a3e67a4 1459
1ec14ad3 1460 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1461 if (dev_priv->info->gen == 3)
6b26c86d 1462 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1463
f796cf8f
JB		 1464 i915_disable_pipestat(dev_priv, pipe,
1465 PIPE_VBLANK_INTERRUPT_ENABLE |
1466 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1467 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1468}
1469
f71d4af4 1470static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1471{
1472 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1473 unsigned long irqflags;
1474
1475 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1476 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1477 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1478 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1479}
1480
f71d4af4 1481static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1482{
1483 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1484 unsigned long irqflags;
1485
1486 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1487 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1488 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1489 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1490}
1491
7e231dbe
JB		 1492static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1493{
1494 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1495 unsigned long irqflags;
1496 u32 dpfl, imr;
1497
1498 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1499 dpfl = I915_READ(VLV_DPFLIPSTAT);
1500 imr = I915_READ(VLV_IMR);
1501 if (pipe == 0) {
1502 dpfl &= ~PIPEA_VBLANK_INT_EN;
1503 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1504 } else {
1505 dpfl &= ~PIPEB_VBLANK_INT_EN;
1506 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1507 }
1508 I915_WRITE(VLV_IMR, imr);
1509 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1510 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1511}
1512
893eead0
CW		 1513static u32
1514ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1515{
893eead0
CW		 1516 return list_entry(ring->request_list.prev,
1517 struct drm_i915_gem_request, list)->seqno;
1518}
1519
1520static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1521{
9574b3fe
BW		 1522 /* We don't check whether the ring even exists before calling this
1523 * function. Hence check whether it's initialized. */
1524 if (ring->obj == NULL)
1525 return true;
1526
893eead0
CW		 1527 if (list_empty(&ring->request_list) ||
1528 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1529 /* Issue a wake-up to catch stuck h/w. */
9574b3fe
BW		 1530 if (waitqueue_active(&ring->irq_queue)) {
1531 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1532 ring->name);
893eead0
CW		 1533 wake_up_all(&ring->irq_queue);
1534 *err = true;
1535 }
1536 return true;
1537 }
1538 return false;
f65d9421
BG		 1539}
1540
1ec14ad3
CW		 1541static bool kick_ring(struct intel_ring_buffer *ring)
1542{
1543 struct drm_device *dev = ring->dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 u32 tmp = I915_READ_CTL(ring);
1546 if (tmp & RING_WAIT) {
1547 DRM_ERROR("Kicking stuck wait on %s\n",
1548 ring->name);
1549 I915_WRITE_CTL(ring, tmp);
1550 return true;
1551 }
1ec14ad3
CW		 1552 return false;
1553}
1554
d1e61e7f
CW		 1555static bool i915_hangcheck_hung(struct drm_device *dev)
1556{
1557 drm_i915_private_t *dev_priv = dev->dev_private;
1558
1559 if (dev_priv->hangcheck_count++ > 1) {
1560 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1561 i915_handle_error(dev, true);
1562
1563 if (!IS_GEN2(dev)) {
1564 /* Is the chip hanging on a WAIT_FOR_EVENT?
1565 * If so we can simply poke the RB_WAIT bit
1566 * and break the hang. This should work on
1567 * all but the second generation chipsets.
1568 */
1569 if (kick_ring(&dev_priv->ring[RCS]))
1570 return false;
1571
1572 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1573 return false;
1574
1575 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1576 return false;
1577 }
1578
1579 return true;
1580 }
1581
1582 return false;
1583}
1584
f65d9421
BG		 1585/**
1586 * This is called when the chip hasn't reported back with completed
1587 * batchbuffers in a long time. The first time this is called we simply record
1588 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1589 * again, we assume the chip is wedged and try to fix it.
1590 */
1591void i915_hangcheck_elapsed(unsigned long data)
1592{
1593 struct drm_device *dev = (struct drm_device *)data;
1594 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1595 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1596 bool err = false;
1597
3e0dc6b0
BW		 1598 if (!i915_enable_hangcheck)
1599 return;
1600
893eead0 1601 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1602 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1603 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1604 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1605 if (err) {
1606 if (i915_hangcheck_hung(dev))
1607 return;
1608
893eead0 1609 goto repeat;
d1e61e7f
CW		 1610 }
1611
1612 dev_priv->hangcheck_count = 0;
893eead0
CW		 1613 return;
1614 }
b9201c14 1615
a6c45cf0 1616 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1617 instdone = I915_READ(INSTDONE);
1618 instdone1 = 0;
1619 } else {
cbb465e7
CW		 1620 instdone = I915_READ(INSTDONE_I965);
1621 instdone1 = I915_READ(INSTDONE1);
1622 }
097354eb
DV		 1623 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1624 acthd_bsd = HAS_BSD(dev) ?
1625 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1626 acthd_blt = HAS_BLT(dev) ?
1627 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1628
cbb465e7 1629 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1630 dev_priv->last_acthd_bsd == acthd_bsd &&
1631 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1632 dev_priv->last_instdone == instdone &&
1633 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1634 if (i915_hangcheck_hung(dev))
cbb465e7 1635 return;
cbb465e7
CW		 1636 } else {
1637 dev_priv->hangcheck_count = 0;
1638
1639 dev_priv->last_acthd = acthd;
097354eb
DV		 1640 dev_priv->last_acthd_bsd = acthd_bsd;
1641 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1642 dev_priv->last_instdone = instdone;
1643 dev_priv->last_instdone1 = instdone1;
1644 }
f65d9421 1645
893eead0 1646repeat:
f65d9421 1647 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1648 mod_timer(&dev_priv->hangcheck_timer,
1649 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1650}
1651
1da177e4
LT		 1652/* drm_dma.h hooks
1653*/
f71d4af4 1654static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1655{
1656 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1657
4697995b
JB		 1658 atomic_set(&dev_priv->irq_received, 0);
1659
4697995b 1660
036a4a7d 1661 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1662
036a4a7d
ZW		 1663 /* XXX hotplug from PCH */
1664
1665 I915_WRITE(DEIMR, 0xffffffff);
1666 I915_WRITE(DEIER, 0x0);
3143a2bf 1667 POSTING_READ(DEIER);
036a4a7d
ZW		 1668
1669 /* and GT */
1670 I915_WRITE(GTIMR, 0xffffffff);
1671 I915_WRITE(GTIER, 0x0);
3143a2bf 1672 POSTING_READ(GTIER);
c650156a
ZW		 1673
1674 /* south display irq */
1675 I915_WRITE(SDEIMR, 0xffffffff);
1676 I915_WRITE(SDEIER, 0x0);
3143a2bf 1677 POSTING_READ(SDEIER);
036a4a7d
ZW		 1678}
1679
7e231dbe
JB		 1680static void valleyview_irq_preinstall(struct drm_device *dev)
1681{
1682 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1683 int pipe;
1684
1685 atomic_set(&dev_priv->irq_received, 0);
1686
7e231dbe
JB		 1687 /* VLV magic */
1688 I915_WRITE(VLV_IMR, 0);
1689 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1690 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1691 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1692
7e231dbe
JB		 1693 /* and GT */
1694 I915_WRITE(GTIIR, I915_READ(GTIIR));
1695 I915_WRITE(GTIIR, I915_READ(GTIIR));
1696 I915_WRITE(GTIMR, 0xffffffff);
1697 I915_WRITE(GTIER, 0x0);
1698 POSTING_READ(GTIER);
1699
1700 I915_WRITE(DPINVGTT, 0xff);
1701
1702 I915_WRITE(PORT_HOTPLUG_EN, 0);
1703 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1704 for_each_pipe(pipe)
1705 I915_WRITE(PIPESTAT(pipe), 0xffff);
1706 I915_WRITE(VLV_IIR, 0xffffffff);
1707 I915_WRITE(VLV_IMR, 0xffffffff);
1708 I915_WRITE(VLV_IER, 0x0);
1709 POSTING_READ(VLV_IER);
1710}
1711
7fe0b973
KP		 1712/*
1713 * Enable digital hotplug on the PCH, and configure the DP short pulse
1714 * duration to 2ms (which is the minimum in the Display Port spec)
1715 *
1716 * This register is the same on all known PCH chips.
1717 */
1718
1719static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1720{
1721 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1722 u32 hotplug;
1723
1724 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1725 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1726 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1727 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1728 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1729 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1730}
1731
f71d4af4 1732static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1733{
1734 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1735 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1736 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1737 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1738 u32 render_irqs;
2d7b8366 1739 u32 hotplug_mask;
036a4a7d 1740
1ec14ad3 1741 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1742
1743 /* should always can generate irq */
1744 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1745 I915_WRITE(DEIMR, dev_priv->irq_mask);
1746 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1747 POSTING_READ(DEIER);
036a4a7d 1748
1ec14ad3 1749 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1750
1751 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1752 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1753
1ec14ad3
CW		 1754 if (IS_GEN6(dev))
1755 render_irqs =
1756 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1757 GEN6_BSD_USER_INTERRUPT |
1758 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1759 else
1760 render_irqs =
88f23b8f 1761 GT_USER_INTERRUPT |
c6df541c 1762 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1763 GT_BSD_USER_INTERRUPT;
1764 I915_WRITE(GTIER, render_irqs);
3143a2bf 1765 POSTING_READ(GTIER);
036a4a7d 1766
2d7b8366 1767 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1768 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1769 SDE_PORTB_HOTPLUG_CPT |
1770 SDE_PORTC_HOTPLUG_CPT |
1771 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1772 } else {
9035a97a
CW		 1773 hotplug_mask = (SDE_CRT_HOTPLUG |
1774 SDE_PORTB_HOTPLUG |
1775 SDE_PORTC_HOTPLUG |
1776 SDE_PORTD_HOTPLUG |
1777 SDE_AUX_MASK);
2d7b8366
YL		 1778 }
1779
1ec14ad3 1780 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1781
1782 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1783 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1784 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1785 POSTING_READ(SDEIER);
c650156a 1786
7fe0b973
KP		 1787 ironlake_enable_pch_hotplug(dev);
1788
f97108d1
JB		 1789 if (IS_IRONLAKE_M(dev)) {
1790 /* Clear & enable PCU event interrupts */
1791 I915_WRITE(DEIIR, DE_PCU_EVENT);
1792 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1793 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
1794 }
1795
036a4a7d
ZW		 1796 return 0;
1797}
1798
f71d4af4 1799static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 1800{
1801 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1802 /* enable kind of interrupts always enabled */
1803 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
1804 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
1805 DE_PLANEB_FLIP_DONE_IVB;
1806 u32 render_irqs;
1807 u32 hotplug_mask;
1808
b1f14ad0
JB		 1809 dev_priv->irq_mask = ~display_mask;
1810
1811 /* should always can generate irq */
1812 I915_WRITE(DEIIR, I915_READ(DEIIR));
1813 I915_WRITE(DEIMR, dev_priv->irq_mask);
1814 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
1815 DE_PIPEB_VBLANK_IVB);
1816 POSTING_READ(DEIER);
1817
1818 dev_priv->gt_irq_mask = ~0;
1819
1820 I915_WRITE(GTIIR, I915_READ(GTIIR));
1821 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1822
e2a1e2f0
BW		 1823 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
1824 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 1825 I915_WRITE(GTIER, render_irqs);
1826 POSTING_READ(GTIER);
1827
1828 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1829 SDE_PORTB_HOTPLUG_CPT |
1830 SDE_PORTC_HOTPLUG_CPT |
1831 SDE_PORTD_HOTPLUG_CPT);
1832 dev_priv->pch_irq_mask = ~hotplug_mask;
1833
1834 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1835 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1836 I915_WRITE(SDEIER, hotplug_mask);
1837 POSTING_READ(SDEIER);
1838
7fe0b973
KP		 1839 ironlake_enable_pch_hotplug(dev);
1840
b1f14ad0
JB		 1841 return 0;
1842}
1843
7e231dbe
JB		 1844static int valleyview_irq_postinstall(struct drm_device *dev)
1845{
1846 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1847 u32 render_irqs;
1848 u32 enable_mask;
1849 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
1850 u16 msid;
1851
1852 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
1853 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
1854 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1855
1856 dev_priv->irq_mask = ~enable_mask;
1857
7e231dbe
JB		 1858 dev_priv->pipestat[0] = 0;
1859 dev_priv->pipestat[1] = 0;
1860
7e231dbe
JB		 1861 /* Hack for broken MSIs on VLV */
1862 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
1863 pci_read_config_word(dev->pdev, 0x98, &msid);
1864 msid &= 0xff; /* mask out delivery bits */
1865 msid |= (1<<14);
1866 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
1867
1868 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
1869 I915_WRITE(VLV_IER, enable_mask);
1870 I915_WRITE(VLV_IIR, 0xffffffff);
1871 I915_WRITE(PIPESTAT(0), 0xffff);
1872 I915_WRITE(PIPESTAT(1), 0xffff);
1873 POSTING_READ(VLV_IER);
1874
1875 I915_WRITE(VLV_IIR, 0xffffffff);
1876 I915_WRITE(VLV_IIR, 0xffffffff);
1877
1878 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
1879 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 1880 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 1881 GT_GEN6_BSD_USER_INTERRUPT |
1882 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
1883 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
1884 GT_PIPE_NOTIFY |
1885 GT_RENDER_CS_ERROR_INTERRUPT |
1886 GT_SYNC_STATUS |
1887 GT_USER_INTERRUPT;
1888
1889 dev_priv->gt_irq_mask = ~render_irqs;
1890
1891 I915_WRITE(GTIIR, I915_READ(GTIIR));
1892 I915_WRITE(GTIIR, I915_READ(GTIIR));
1893 I915_WRITE(GTIMR, 0);
1894 I915_WRITE(GTIER, render_irqs);
1895 POSTING_READ(GTIER);
1896
1897 /* ack & enable invalid PTE error interrupts */
1898#if 0 /* FIXME: add support to irq handler for checking these bits */
1899 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
1900 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
1901#endif
1902
1903 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
1904#if 0 /* FIXME: check register definitions; some have moved */
1905 /* Note HDMI and DP share bits */
1906 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
1907 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
1908 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
1909 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
1910 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
1911 hotplug_en |= HDMID_HOTPLUG_INT_EN;
1912 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
1913 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
1914 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
1915 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
1916 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
1917 hotplug_en |= CRT_HOTPLUG_INT_EN;
1918 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
1919 }
1920#endif
1921
1922 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
1923
1924 return 0;
1925}
1926
7e231dbe
JB		 1927static void valleyview_irq_uninstall(struct drm_device *dev)
1928{
1929 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1930 int pipe;
1931
1932 if (!dev_priv)
1933 return;
1934
7e231dbe
JB		 1935 for_each_pipe(pipe)
1936 I915_WRITE(PIPESTAT(pipe), 0xffff);
1937
1938 I915_WRITE(HWSTAM, 0xffffffff);
1939 I915_WRITE(PORT_HOTPLUG_EN, 0);
1940 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1941 for_each_pipe(pipe)
1942 I915_WRITE(PIPESTAT(pipe), 0xffff);
1943 I915_WRITE(VLV_IIR, 0xffffffff);
1944 I915_WRITE(VLV_IMR, 0xffffffff);
1945 I915_WRITE(VLV_IER, 0x0);
1946 POSTING_READ(VLV_IER);
1947}
1948
f71d4af4 1949static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 1950{
1951 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 1952
1953 if (!dev_priv)
1954 return;
1955
036a4a7d
ZW		 1956 I915_WRITE(HWSTAM, 0xffffffff);
1957
1958 I915_WRITE(DEIMR, 0xffffffff);
1959 I915_WRITE(DEIER, 0x0);
1960 I915_WRITE(DEIIR, I915_READ(DEIIR));
1961
1962 I915_WRITE(GTIMR, 0xffffffff);
1963 I915_WRITE(GTIER, 0x0);
1964 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 1965
1966 I915_WRITE(SDEIMR, 0xffffffff);
1967 I915_WRITE(SDEIER, 0x0);
1968 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 1969}
1970
a266c7d5 1971static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 1972{
1973 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 1974 int pipe;
91e3738e 1975
a266c7d5 1976 atomic_set(&dev_priv->irq_received, 0);
5ca58282 1977
9db4a9c7
JB		 1978 for_each_pipe(pipe)
1979 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 1980 I915_WRITE16(IMR, 0xffff);
1981 I915_WRITE16(IER, 0x0);
1982 POSTING_READ16(IER);
c2798b19
CW		 1983}
1984
1985static int i8xx_irq_postinstall(struct drm_device *dev)
1986{
1987 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1988
c2798b19
CW		 1989 dev_priv->pipestat[0] = 0;
1990 dev_priv->pipestat[1] = 0;
1991
1992 I915_WRITE16(EMR,
1993 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
1994
1995 /* Unmask the interrupts that we always want on. */
1996 dev_priv->irq_mask =
1997 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
1998 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
1999 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2000 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2001 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2002 I915_WRITE16(IMR, dev_priv->irq_mask);
2003
2004 I915_WRITE16(IER,
2005 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2006 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2007 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2008 I915_USER_INTERRUPT);
2009 POSTING_READ16(IER);
2010
2011 return 0;
2012}
2013
2014static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2015{
2016 struct drm_device *dev = (struct drm_device *) arg;
2017 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
c2798b19
CW		 2018 u16 iir, new_iir;
2019 u32 pipe_stats[2];
2020 unsigned long irqflags;
2021 int irq_received;
2022 int pipe;
2023 u16 flip_mask =
2024 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2025 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2026
2027 atomic_inc(&dev_priv->irq_received);
2028
2029 iir = I915_READ16(IIR);
2030 if (iir == 0)
2031 return IRQ_NONE;
2032
2033 while (iir & ~flip_mask) {
2034 /* Can't rely on pipestat interrupt bit in iir as it might
2035 * have been cleared after the pipestat interrupt was received.
2036 * It doesn't set the bit in iir again, but it still produces
2037 * interrupts (for non-MSI).
2038 */
2039 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2040 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2041 i915_handle_error(dev, false);
2042
2043 for_each_pipe(pipe) {
2044 int reg = PIPESTAT(pipe);
2045 pipe_stats[pipe] = I915_READ(reg);
2046
2047 /*
2048 * Clear the PIPE*STAT regs before the IIR
2049 */
2050 if (pipe_stats[pipe] & 0x8000ffff) {
2051 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2052 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2053 pipe_name(pipe));
2054 I915_WRITE(reg, pipe_stats[pipe]);
2055 irq_received = 1;
2056 }
2057 }
2058 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2059
2060 I915_WRITE16(IIR, iir & ~flip_mask);
2061 new_iir = I915_READ16(IIR); /* Flush posted writes */
2062
d05c617e 2063 i915_update_dri1_breadcrumb(dev);
c2798b19
CW		 2064
2065 if (iir & I915_USER_INTERRUPT)
2066 notify_ring(dev, &dev_priv->ring[RCS]);
2067
2068 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2069 drm_handle_vblank(dev, 0)) {
2070 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2071 intel_prepare_page_flip(dev, 0);
2072 intel_finish_page_flip(dev, 0);
2073 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2074 }
2075 }
2076
2077 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2078 drm_handle_vblank(dev, 1)) {
2079 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2080 intel_prepare_page_flip(dev, 1);
2081 intel_finish_page_flip(dev, 1);
2082 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2083 }
2084 }
2085
2086 iir = new_iir;
2087 }
2088
2089 return IRQ_HANDLED;
2090}
2091
2092static void i8xx_irq_uninstall(struct drm_device * dev)
2093{
2094 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2095 int pipe;
2096
c2798b19
CW		 2097 for_each_pipe(pipe) {
2098 /* Clear enable bits; then clear status bits */
2099 I915_WRITE(PIPESTAT(pipe), 0);
2100 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2101 }
2102 I915_WRITE16(IMR, 0xffff);
2103 I915_WRITE16(IER, 0x0);
2104 I915_WRITE16(IIR, I915_READ16(IIR));
2105}
2106
a266c7d5
CW		 2107static void i915_irq_preinstall(struct drm_device * dev)
2108{
2109 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2110 int pipe;
2111
2112 atomic_set(&dev_priv->irq_received, 0);
2113
2114 if (I915_HAS_HOTPLUG(dev)) {
2115 I915_WRITE(PORT_HOTPLUG_EN, 0);
2116 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2117 }
2118
00d98ebd 2119 I915_WRITE16(HWSTAM, 0xeffe);
a266c7d5
CW		 2120 for_each_pipe(pipe)
2121 I915_WRITE(PIPESTAT(pipe), 0);
2122 I915_WRITE(IMR, 0xffffffff);
2123 I915_WRITE(IER, 0x0);
2124 POSTING_READ(IER);
2125}
2126
2127static int i915_irq_postinstall(struct drm_device *dev)
2128{
2129 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
38bde180 2130 u32 enable_mask;
a266c7d5 2131
a266c7d5
CW		 2132 dev_priv->pipestat[0] = 0;
2133 dev_priv->pipestat[1] = 0;
2134
38bde180
CW		 2135 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2136
2137 /* Unmask the interrupts that we always want on. */
2138 dev_priv->irq_mask =
2139 ~(I915_ASLE_INTERRUPT |
2140 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2141 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2142 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2143 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2144 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2145
2146 enable_mask =
2147 I915_ASLE_INTERRUPT |
2148 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2149 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2150 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2151 I915_USER_INTERRUPT;
2152
a266c7d5
CW		 2153 if (I915_HAS_HOTPLUG(dev)) {
2154 /* Enable in IER... */
2155 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2156 /* and unmask in IMR */
2157 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2158 }
2159
a266c7d5
CW		 2160 I915_WRITE(IMR, dev_priv->irq_mask);
2161 I915_WRITE(IER, enable_mask);
2162 POSTING_READ(IER);
2163
2164 if (I915_HAS_HOTPLUG(dev)) {
2165 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2166
a266c7d5
CW		 2167 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2168 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2169 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2170 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2171 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2172 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2173 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2174 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2175 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2176 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2177 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2178 hotplug_en |= CRT_HOTPLUG_INT_EN;
a266c7d5
CW		 2179 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2180 }
2181
2182 /* Ignore TV since it's buggy */
2183
2184 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2185 }
2186
2187 intel_opregion_enable_asle(dev);
2188
2189 return 0;
2190}
2191
2192static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2193{
2194 struct drm_device *dev = (struct drm_device *) arg;
2195 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
8291ee90 2196 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
a266c7d5 2197 unsigned long irqflags;
38bde180
CW		 2198 u32 flip_mask =
2199 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2200 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2201 u32 flip[2] = {
2202 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT,
2203 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
2204 };
2205 int pipe, ret = IRQ_NONE;
a266c7d5
CW		 2206
2207 atomic_inc(&dev_priv->irq_received);
2208
2209 iir = I915_READ(IIR);
38bde180
CW		 2210 do {
2211 bool irq_received = (iir & ~flip_mask) != 0;
8291ee90 2212 bool blc_event = false;
a266c7d5
CW		 2213
2214 /* Can't rely on pipestat interrupt bit in iir as it might
2215 * have been cleared after the pipestat interrupt was received.
2216 * It doesn't set the bit in iir again, but it still produces
2217 * interrupts (for non-MSI).
2218 */
2219 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2220 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2221 i915_handle_error(dev, false);
2222
2223 for_each_pipe(pipe) {
2224 int reg = PIPESTAT(pipe);
2225 pipe_stats[pipe] = I915_READ(reg);
2226
38bde180 2227 /* Clear the PIPE*STAT regs before the IIR */
a266c7d5
CW		 2228 if (pipe_stats[pipe] & 0x8000ffff) {
2229 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2230 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2231 pipe_name(pipe));
2232 I915_WRITE(reg, pipe_stats[pipe]);
38bde180 2233 irq_received = true;
a266c7d5
CW		 2234 }
2235 }
2236 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2237
2238 if (!irq_received)
2239 break;
2240
a266c7d5
CW		 2241 /* Consume port. Then clear IIR or we'll miss events */
2242 if ((I915_HAS_HOTPLUG(dev)) &&
2243 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2244 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2245
2246 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2247 hotplug_status);
2248 if (hotplug_status & dev_priv->hotplug_supported_mask)
2249 queue_work(dev_priv->wq,
2250 &dev_priv->hotplug_work);
2251
2252 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
38bde180 2253 POSTING_READ(PORT_HOTPLUG_STAT);
a266c7d5
CW		 2254 }
2255
38bde180 2256 I915_WRITE(IIR, iir & ~flip_mask);
a266c7d5
CW		 2257 new_iir = I915_READ(IIR); /* Flush posted writes */
2258
a266c7d5
CW		 2259 if (iir & I915_USER_INTERRUPT)
2260 notify_ring(dev, &dev_priv->ring[RCS]);
a266c7d5 2261
a266c7d5 2262 for_each_pipe(pipe) {
38bde180
CW		 2263 int plane = pipe;
2264 if (IS_MOBILE(dev))
2265 plane = !plane;
8291ee90 2266 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2267 drm_handle_vblank(dev, pipe)) {
38bde180
CW		 2268 if (iir & flip[plane]) {
2269 intel_prepare_page_flip(dev, plane);
2270 intel_finish_page_flip(dev, pipe);
2271 flip_mask &= ~flip[plane];
2272 }
a266c7d5
CW		 2273 }
2274
2275 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2276 blc_event = true;
2277 }
2278
a266c7d5
CW		 2279 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2280 intel_opregion_asle_intr(dev);
2281
2282 /* With MSI, interrupts are only generated when iir
2283 * transitions from zero to nonzero. If another bit got
2284 * set while we were handling the existing iir bits, then
2285 * we would never get another interrupt.
2286 *
2287 * This is fine on non-MSI as well, as if we hit this path
2288 * we avoid exiting the interrupt handler only to generate
2289 * another one.
2290 *
2291 * Note that for MSI this could cause a stray interrupt report
2292 * if an interrupt landed in the time between writing IIR and
2293 * the posting read. This should be rare enough to never
2294 * trigger the 99% of 100,000 interrupts test for disabling
2295 * stray interrupts.
2296 */
38bde180 2297 ret = IRQ_HANDLED;
a266c7d5 2298 iir = new_iir;
38bde180 2299 } while (iir & ~flip_mask);
a266c7d5 2300
d05c617e 2301 i915_update_dri1_breadcrumb(dev);
8291ee90 2302
a266c7d5
CW		 2303 return ret;
2304}
2305
2306static void i915_irq_uninstall(struct drm_device * dev)
2307{
2308 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2309 int pipe;
2310
a266c7d5
CW		 2311 if (I915_HAS_HOTPLUG(dev)) {
2312 I915_WRITE(PORT_HOTPLUG_EN, 0);
2313 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2314 }
2315
00d98ebd 2316 I915_WRITE16(HWSTAM, 0xffff);
55b39755
CW		 2317 for_each_pipe(pipe) {
2318 /* Clear enable bits; then clear status bits */
a266c7d5 2319 I915_WRITE(PIPESTAT(pipe), 0);
55b39755
CW		 2320 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2321 }
a266c7d5
CW		 2322 I915_WRITE(IMR, 0xffffffff);
2323 I915_WRITE(IER, 0x0);
2324
a266c7d5
CW		 2325 I915_WRITE(IIR, I915_READ(IIR));
2326}
2327
2328static void i965_irq_preinstall(struct drm_device * dev)
2329{
2330 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2331 int pipe;
2332
2333 atomic_set(&dev_priv->irq_received, 0);
2334
2335 if (I915_HAS_HOTPLUG(dev)) {
2336 I915_WRITE(PORT_HOTPLUG_EN, 0);
2337 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2338 }
2339
2340 I915_WRITE(HWSTAM, 0xeffe);
2341 for_each_pipe(pipe)
2342 I915_WRITE(PIPESTAT(pipe), 0);
2343 I915_WRITE(IMR, 0xffffffff);
2344 I915_WRITE(IER, 0x0);
2345 POSTING_READ(IER);
2346}
2347
2348static int i965_irq_postinstall(struct drm_device *dev)
2349{
2350 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
bbba0a97 2351 u32 enable_mask;
a266c7d5
CW		 2352 u32 error_mask;
2353
a266c7d5 2354 /* Unmask the interrupts that we always want on. */
bbba0a97
CW		 2355 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2356 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2357 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2358 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2359 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2360 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2361
2362 enable_mask = ~dev_priv->irq_mask;
2363 enable_mask |= I915_USER_INTERRUPT;
2364
2365 if (IS_G4X(dev))
2366 enable_mask |= I915_BSD_USER_INTERRUPT;
a266c7d5
CW		 2367
2368 dev_priv->pipestat[0] = 0;
2369 dev_priv->pipestat[1] = 0;
2370
2371 if (I915_HAS_HOTPLUG(dev)) {
2372 /* Enable in IER... */
2373 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2374 /* and unmask in IMR */
2375 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2376 }
2377
2378 /*
2379 * Enable some error detection, note the instruction error mask
2380 * bit is reserved, so we leave it masked.
2381 */
2382 if (IS_G4X(dev)) {
2383 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2384 GM45_ERROR_MEM_PRIV |
2385 GM45_ERROR_CP_PRIV |
2386 I915_ERROR_MEMORY_REFRESH);
2387 } else {
2388 error_mask = ~(I915_ERROR_PAGE_TABLE |
2389 I915_ERROR_MEMORY_REFRESH);
2390 }
2391 I915_WRITE(EMR, error_mask);
2392
2393 I915_WRITE(IMR, dev_priv->irq_mask);
2394 I915_WRITE(IER, enable_mask);
2395 POSTING_READ(IER);
2396
2397 if (I915_HAS_HOTPLUG(dev)) {
2398 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2399
2400 /* Note HDMI and DP share bits */
2401 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2402 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2403 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2404 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2405 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2406 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2407 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2408 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2409 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2410 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2411 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2412 hotplug_en |= CRT_HOTPLUG_INT_EN;
2413
2414 /* Programming the CRT detection parameters tends
2415 to generate a spurious hotplug event about three
2416 seconds later. So just do it once.
2417 */
2418 if (IS_G4X(dev))
2419 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2420 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2421 }
2422
2423 /* Ignore TV since it's buggy */
2424
2425 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2426 }
2427
2428 intel_opregion_enable_asle(dev);
2429
2430 return 0;
2431}
2432
2433static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2434{
2435 struct drm_device *dev = (struct drm_device *) arg;
2436 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
a266c7d5
CW		 2437 u32 iir, new_iir;
2438 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2439 unsigned long irqflags;
2440 int irq_received;
2441 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2442
2443 atomic_inc(&dev_priv->irq_received);
2444
2445 iir = I915_READ(IIR);
2446
a266c7d5 2447 for (;;) {
2c8ba29f
CW		 2448 bool blc_event = false;
2449
a266c7d5
CW		 2450 irq_received = iir != 0;
2451
2452 /* Can't rely on pipestat interrupt bit in iir as it might
2453 * have been cleared after the pipestat interrupt was received.
2454 * It doesn't set the bit in iir again, but it still produces
2455 * interrupts (for non-MSI).
2456 */
2457 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2458 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2459 i915_handle_error(dev, false);
2460
2461 for_each_pipe(pipe) {
2462 int reg = PIPESTAT(pipe);
2463 pipe_stats[pipe] = I915_READ(reg);
2464
2465 /*
2466 * Clear the PIPE*STAT regs before the IIR
2467 */
2468 if (pipe_stats[pipe] & 0x8000ffff) {
2469 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2470 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2471 pipe_name(pipe));
2472 I915_WRITE(reg, pipe_stats[pipe]);
2473 irq_received = 1;
2474 }
2475 }
2476 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2477
2478 if (!irq_received)
2479 break;
2480
2481 ret = IRQ_HANDLED;
2482
2483 /* Consume port. Then clear IIR or we'll miss events */
2484 if ((I915_HAS_HOTPLUG(dev)) &&
2485 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2486 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2487
2488 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2489 hotplug_status);
2490 if (hotplug_status & dev_priv->hotplug_supported_mask)
2491 queue_work(dev_priv->wq,
2492 &dev_priv->hotplug_work);
2493
2494 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2495 I915_READ(PORT_HOTPLUG_STAT);
2496 }
2497
2498 I915_WRITE(IIR, iir);
2499 new_iir = I915_READ(IIR); /* Flush posted writes */
2500
a266c7d5
CW		 2501 if (iir & I915_USER_INTERRUPT)
2502 notify_ring(dev, &dev_priv->ring[RCS]);
2503 if (iir & I915_BSD_USER_INTERRUPT)
2504 notify_ring(dev, &dev_priv->ring[VCS]);
2505
4f7d1e79 2506 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2507 intel_prepare_page_flip(dev, 0);
a266c7d5 2508
4f7d1e79 2509 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2510 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2511
2512 for_each_pipe(pipe) {
2c8ba29f 2513 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2514 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2515 i915_pageflip_stall_check(dev, pipe);
2516 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2517 }
2518
2519 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2520 blc_event = true;
2521 }
2522
2523
2524 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2525 intel_opregion_asle_intr(dev);
2526
2527 /* With MSI, interrupts are only generated when iir
2528 * transitions from zero to nonzero. If another bit got
2529 * set while we were handling the existing iir bits, then
2530 * we would never get another interrupt.
2531 *
2532 * This is fine on non-MSI as well, as if we hit this path
2533 * we avoid exiting the interrupt handler only to generate
2534 * another one.
2535 *
2536 * Note that for MSI this could cause a stray interrupt report
2537 * if an interrupt landed in the time between writing IIR and
2538 * the posting read. This should be rare enough to never
2539 * trigger the 99% of 100,000 interrupts test for disabling
2540 * stray interrupts.
2541 */
2542 iir = new_iir;
2543 }
2544
d05c617e 2545 i915_update_dri1_breadcrumb(dev);
2c8ba29f 2546
a266c7d5
CW		 2547 return ret;
2548}
2549
2550static void i965_irq_uninstall(struct drm_device * dev)
2551{
2552 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2553 int pipe;
2554
2555 if (!dev_priv)
2556 return;
2557
a266c7d5
CW		 2558 if (I915_HAS_HOTPLUG(dev)) {
2559 I915_WRITE(PORT_HOTPLUG_EN, 0);
2560 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2561 }
2562
2563 I915_WRITE(HWSTAM, 0xffffffff);
2564 for_each_pipe(pipe)
2565 I915_WRITE(PIPESTAT(pipe), 0);
2566 I915_WRITE(IMR, 0xffffffff);
2567 I915_WRITE(IER, 0x0);
2568
2569 for_each_pipe(pipe)
2570 I915_WRITE(PIPESTAT(pipe),
2571 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2572 I915_WRITE(IIR, I915_READ(IIR));
2573}
2574
f71d4af4
JB		 2575void intel_irq_init(struct drm_device *dev)
2576{
8b2e326d
CW		 2577 struct drm_i915_private *dev_priv = dev->dev_private;
2578
2579 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2580 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2581 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2582
f71d4af4
JB		 2583 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2584 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2585 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2586 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2587 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2588 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2589 }
2590
c3613de9
KP		 2591 if (drm_core_check_feature(dev, DRIVER_MODESET))
2592 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2593 else
2594 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2595 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2596
7e231dbe
JB		 2597 if (IS_VALLEYVIEW(dev)) {
2598 dev->driver->irq_handler = valleyview_irq_handler;
2599 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2600 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2601 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2602 dev->driver->enable_vblank = valleyview_enable_vblank;
2603 dev->driver->disable_vblank = valleyview_disable_vblank;
2604 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2605 /* Share pre & uninstall handlers with ILK/SNB */
2606 dev->driver->irq_handler = ivybridge_irq_handler;
2607 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2608 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2609 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2610 dev->driver->enable_vblank = ivybridge_enable_vblank;
2611 dev->driver->disable_vblank = ivybridge_disable_vblank;
2612 } else if (HAS_PCH_SPLIT(dev)) {
2613 dev->driver->irq_handler = ironlake_irq_handler;
2614 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2615 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2616 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2617 dev->driver->enable_vblank = ironlake_enable_vblank;
2618 dev->driver->disable_vblank = ironlake_disable_vblank;
2619 } else {
c2798b19
CW		 2620 if (INTEL_INFO(dev)->gen == 2) {
2621 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2622 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2623 dev->driver->irq_handler = i8xx_irq_handler;
2624 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2625 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2626 /* IIR "flip pending" means done if this bit is set */
2627 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2628
a266c7d5
CW		 2629 dev->driver->irq_preinstall = i915_irq_preinstall;
2630 dev->driver->irq_postinstall = i915_irq_postinstall;
2631 dev->driver->irq_uninstall = i915_irq_uninstall;
2632 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2633 } else {
a266c7d5
CW		 2634 dev->driver->irq_preinstall = i965_irq_preinstall;
2635 dev->driver->irq_postinstall = i965_irq_postinstall;
2636 dev->driver->irq_uninstall = i965_irq_uninstall;
2637 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2638 }
f71d4af4
JB		 2639 dev->driver->enable_vblank = i915_enable_vblank;
2640 dev->driver->disable_vblank = i915_disable_vblank;
2641 }
2642}
kernel source for telekom puls (alcatel/mediatek)