Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | void |
f2b115e6 | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
69 | { |
70 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
71 | dev_priv->gt_irq_mask_reg &= ~mask; | |
72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
3143a2bf | 73 | POSTING_READ(GTIMR); |
036a4a7d ZW |
74 | } |
75 | } | |
76 | ||
62fdfeaf | 77 | void |
f2b115e6 | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
79 | { |
80 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
81 | dev_priv->gt_irq_mask_reg |= mask; | |
82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
3143a2bf | 83 | POSTING_READ(GTIMR); |
036a4a7d ZW |
84 | } |
85 | } | |
86 | ||
87 | /* For display hotplug interrupt */ | |
995b6762 | 88 | static void |
f2b115e6 | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
90 | { |
91 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
92 | dev_priv->irq_mask_reg &= ~mask; | |
93 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
3143a2bf | 94 | POSTING_READ(DEIMR); |
036a4a7d ZW |
95 | } |
96 | } | |
97 | ||
98 | static inline void | |
f2b115e6 | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
100 | { |
101 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
102 | dev_priv->irq_mask_reg |= mask; | |
103 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
3143a2bf | 104 | POSTING_READ(DEIMR); |
036a4a7d ZW |
105 | } |
106 | } | |
107 | ||
8ee1c3db | 108 | void |
ed4cb414 EA |
109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
110 | { | |
111 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
112 | dev_priv->irq_mask_reg &= ~mask; | |
113 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
3143a2bf | 114 | POSTING_READ(IMR); |
ed4cb414 EA |
115 | } |
116 | } | |
117 | ||
62fdfeaf | 118 | void |
ed4cb414 EA |
119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
120 | { | |
121 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
122 | dev_priv->irq_mask_reg |= mask; | |
123 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
3143a2bf | 124 | POSTING_READ(IMR); |
ed4cb414 EA |
125 | } |
126 | } | |
127 | ||
7c463586 KP |
128 | static inline u32 |
129 | i915_pipestat(int pipe) | |
130 | { | |
131 | if (pipe == 0) | |
132 | return PIPEASTAT; | |
133 | if (pipe == 1) | |
134 | return PIPEBSTAT; | |
9c84ba4e | 135 | BUG(); |
7c463586 KP |
136 | } |
137 | ||
138 | void | |
139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
140 | { | |
141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
142 | u32 reg = i915_pipestat(pipe); | |
143 | ||
144 | dev_priv->pipestat[pipe] |= mask; | |
145 | /* Enable the interrupt, clear any pending status */ | |
146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
3143a2bf | 147 | POSTING_READ(reg); |
7c463586 KP |
148 | } |
149 | } | |
150 | ||
151 | void | |
152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
153 | { | |
154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
155 | u32 reg = i915_pipestat(pipe); | |
156 | ||
157 | dev_priv->pipestat[pipe] &= ~mask; | |
158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
3143a2bf | 159 | POSTING_READ(reg); |
7c463586 KP |
160 | } |
161 | } | |
162 | ||
01c66889 ZY |
163 | /** |
164 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
165 | */ | |
166 | void intel_enable_asle (struct drm_device *dev) | |
167 | { | |
168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
169 | ||
c619eed4 | 170 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 172 | else { |
01c66889 | 173 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 174 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 175 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 176 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 178 | } |
01c66889 ZY |
179 | } |
180 | ||
0a3e67a4 JB |
181 | /** |
182 | * i915_pipe_enabled - check if a pipe is enabled | |
183 | * @dev: DRM device | |
184 | * @pipe: pipe to check | |
185 | * | |
186 | * Reading certain registers when the pipe is disabled can hang the chip. | |
187 | * Use this routine to make sure the PLL is running and the pipe is active | |
188 | * before reading such registers if unsure. | |
189 | */ | |
190 | static int | |
191 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
192 | { | |
193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 194 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
195 | } |
196 | ||
42f52ef8 KP |
197 | /* Called from drm generic code, passed a 'crtc', which |
198 | * we use as a pipe index | |
199 | */ | |
200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
201 | { |
202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
203 | unsigned long high_frame; | |
204 | unsigned long low_frame; | |
5eddb70b | 205 | u32 high1, high2, low; |
0a3e67a4 JB |
206 | |
207 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
208 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
209 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
210 | return 0; |
211 | } | |
212 | ||
5eddb70b CW |
213 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
214 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
215 | ||
0a3e67a4 JB |
216 | /* |
217 | * High & low register fields aren't synchronized, so make sure | |
218 | * we get a low value that's stable across two reads of the high | |
219 | * register. | |
220 | */ | |
221 | do { | |
5eddb70b CW |
222 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
223 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
224 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
225 | } while (high1 != high2); |
226 | ||
5eddb70b CW |
227 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
228 | low >>= PIPE_FRAME_LOW_SHIFT; | |
229 | return (high1 << 8) | low; | |
0a3e67a4 JB |
230 | } |
231 | ||
9880b7a5 JB |
232 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
233 | { | |
234 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
235 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
236 | ||
237 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
238 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
239 | "pipe %d\n", pipe); | |
9880b7a5 JB |
240 | return 0; |
241 | } | |
242 | ||
243 | return I915_READ(reg); | |
244 | } | |
245 | ||
5ca58282 JB |
246 | /* |
247 | * Handle hotplug events outside the interrupt handler proper. | |
248 | */ | |
249 | static void i915_hotplug_work_func(struct work_struct *work) | |
250 | { | |
251 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
252 | hotplug_work); | |
253 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 254 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
255 | struct intel_encoder *encoder; |
256 | ||
257 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
258 | if (encoder->hot_plug) | |
259 | encoder->hot_plug(encoder); | |
260 | ||
5ca58282 | 261 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 262 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
263 | } |
264 | ||
f97108d1 JB |
265 | static void i915_handle_rps_change(struct drm_device *dev) |
266 | { | |
267 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 268 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
269 | u8 new_delay = dev_priv->cur_delay; |
270 | ||
7648fa99 | 271 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
272 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
273 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
274 | max_avg = I915_READ(RCBMAXAVG); |
275 | min_avg = I915_READ(RCBMINAVG); | |
276 | ||
277 | /* Handle RCS change request from hw */ | |
b5b72e89 | 278 | if (busy_up > max_avg) { |
f97108d1 JB |
279 | if (dev_priv->cur_delay != dev_priv->max_delay) |
280 | new_delay = dev_priv->cur_delay - 1; | |
281 | if (new_delay < dev_priv->max_delay) | |
282 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 283 | } else if (busy_down < min_avg) { |
f97108d1 JB |
284 | if (dev_priv->cur_delay != dev_priv->min_delay) |
285 | new_delay = dev_priv->cur_delay + 1; | |
286 | if (new_delay > dev_priv->min_delay) | |
287 | new_delay = dev_priv->min_delay; | |
288 | } | |
289 | ||
7648fa99 JB |
290 | if (ironlake_set_drps(dev, new_delay)) |
291 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
292 | |
293 | return; | |
294 | } | |
295 | ||
549f7365 CW |
296 | static void notify_ring(struct drm_device *dev, |
297 | struct intel_ring_buffer *ring) | |
298 | { | |
299 | struct drm_i915_private *dev_priv = dev->dev_private; | |
78501eac | 300 | u32 seqno = ring->get_seqno(ring); |
b2223497 | 301 | ring->irq_seqno = seqno; |
549f7365 CW |
302 | trace_i915_gem_request_complete(dev, seqno); |
303 | wake_up_all(&ring->irq_queue); | |
304 | dev_priv->hangcheck_count = 0; | |
305 | mod_timer(&dev_priv->hangcheck_timer, | |
306 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
307 | } | |
308 | ||
995b6762 | 309 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
310 | { |
311 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
312 | int ret = IRQ_NONE; | |
3ff99164 | 313 | u32 de_iir, gt_iir, de_ier, pch_iir; |
2d7b8366 | 314 | u32 hotplug_mask; |
036a4a7d | 315 | struct drm_i915_master_private *master_priv; |
881f47b6 XH |
316 | u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT; |
317 | ||
318 | if (IS_GEN6(dev)) | |
319 | bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT; | |
036a4a7d | 320 | |
2d109a84 ZN |
321 | /* disable master interrupt before clearing iir */ |
322 | de_ier = I915_READ(DEIER); | |
323 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
3143a2bf | 324 | POSTING_READ(DEIER); |
2d109a84 | 325 | |
036a4a7d ZW |
326 | de_iir = I915_READ(DEIIR); |
327 | gt_iir = I915_READ(GTIIR); | |
c650156a | 328 | pch_iir = I915_READ(SDEIIR); |
036a4a7d | 329 | |
c7c85101 ZN |
330 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
331 | goto done; | |
036a4a7d | 332 | |
2d7b8366 YL |
333 | if (HAS_PCH_CPT(dev)) |
334 | hotplug_mask = SDE_HOTPLUG_MASK_CPT; | |
335 | else | |
336 | hotplug_mask = SDE_HOTPLUG_MASK; | |
337 | ||
c7c85101 | 338 | ret = IRQ_HANDLED; |
036a4a7d | 339 | |
c7c85101 ZN |
340 | if (dev->primary->master) { |
341 | master_priv = dev->primary->master->driver_priv; | |
342 | if (master_priv->sarea_priv) | |
343 | master_priv->sarea_priv->last_dispatch = | |
344 | READ_BREADCRUMB(dev_priv); | |
345 | } | |
036a4a7d | 346 | |
549f7365 CW |
347 | if (gt_iir & GT_PIPE_NOTIFY) |
348 | notify_ring(dev, &dev_priv->render_ring); | |
881f47b6 | 349 | if (gt_iir & bsd_usr_interrupt) |
549f7365 CW |
350 | notify_ring(dev, &dev_priv->bsd_ring); |
351 | if (HAS_BLT(dev) && gt_iir & GT_BLT_USER_INTERRUPT) | |
352 | notify_ring(dev, &dev_priv->blt_ring); | |
01c66889 | 353 | |
c7c85101 | 354 | if (de_iir & DE_GSE) |
3b617967 | 355 | intel_opregion_gse_intr(dev); |
c650156a | 356 | |
f072d2e7 | 357 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 358 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 359 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 360 | } |
013d5aa2 | 361 | |
f072d2e7 | 362 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 363 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 364 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 365 | } |
013d5aa2 | 366 | |
f072d2e7 | 367 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
368 | drm_handle_vblank(dev, 0); |
369 | ||
f072d2e7 | 370 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
371 | drm_handle_vblank(dev, 1); |
372 | ||
c7c85101 | 373 | /* check event from PCH */ |
2d7b8366 | 374 | if ((de_iir & DE_PCH_EVENT) && (pch_iir & hotplug_mask)) |
c7c85101 | 375 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); |
036a4a7d | 376 | |
f97108d1 | 377 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 378 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
379 | i915_handle_rps_change(dev); |
380 | } | |
381 | ||
c7c85101 ZN |
382 | /* should clear PCH hotplug event before clear CPU irq */ |
383 | I915_WRITE(SDEIIR, pch_iir); | |
384 | I915_WRITE(GTIIR, gt_iir); | |
385 | I915_WRITE(DEIIR, de_iir); | |
386 | ||
387 | done: | |
2d109a84 | 388 | I915_WRITE(DEIER, de_ier); |
3143a2bf | 389 | POSTING_READ(DEIER); |
2d109a84 | 390 | |
036a4a7d ZW |
391 | return ret; |
392 | } | |
393 | ||
8a905236 JB |
394 | /** |
395 | * i915_error_work_func - do process context error handling work | |
396 | * @work: work struct | |
397 | * | |
398 | * Fire an error uevent so userspace can see that a hang or error | |
399 | * was detected. | |
400 | */ | |
401 | static void i915_error_work_func(struct work_struct *work) | |
402 | { | |
403 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
404 | error_work); | |
405 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
406 | char *error_event[] = { "ERROR=1", NULL }; |
407 | char *reset_event[] = { "RESET=1", NULL }; | |
408 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 409 | |
f316a42c BG |
410 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
411 | ||
ba1234d1 | 412 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
413 | DRM_DEBUG_DRIVER("resetting chip\n"); |
414 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
415 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
416 | atomic_set(&dev_priv->mm.wedged, 0); | |
417 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c | 418 | } |
30dbf0c0 | 419 | complete_all(&dev_priv->error_completion); |
f316a42c | 420 | } |
8a905236 JB |
421 | } |
422 | ||
3bd3c932 | 423 | #ifdef CONFIG_DEBUG_FS |
9df30794 CW |
424 | static struct drm_i915_error_object * |
425 | i915_error_object_create(struct drm_device *dev, | |
426 | struct drm_gem_object *src) | |
427 | { | |
e56660dd | 428 | drm_i915_private_t *dev_priv = dev->dev_private; |
9df30794 CW |
429 | struct drm_i915_error_object *dst; |
430 | struct drm_i915_gem_object *src_priv; | |
431 | int page, page_count; | |
e56660dd | 432 | u32 reloc_offset; |
9df30794 CW |
433 | |
434 | if (src == NULL) | |
435 | return NULL; | |
436 | ||
23010e43 | 437 | src_priv = to_intel_bo(src); |
9df30794 CW |
438 | if (src_priv->pages == NULL) |
439 | return NULL; | |
440 | ||
441 | page_count = src->size / PAGE_SIZE; | |
442 | ||
443 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
444 | if (dst == NULL) | |
445 | return NULL; | |
446 | ||
e56660dd | 447 | reloc_offset = src_priv->gtt_offset; |
9df30794 | 448 | for (page = 0; page < page_count; page++) { |
788885ae | 449 | unsigned long flags; |
e56660dd CW |
450 | void __iomem *s; |
451 | void *d; | |
788885ae | 452 | |
e56660dd | 453 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
454 | if (d == NULL) |
455 | goto unwind; | |
e56660dd | 456 | |
788885ae | 457 | local_irq_save(flags); |
e56660dd | 458 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3e4d3af5 | 459 | reloc_offset); |
e56660dd | 460 | memcpy_fromio(d, s, PAGE_SIZE); |
3e4d3af5 | 461 | io_mapping_unmap_atomic(s); |
788885ae | 462 | local_irq_restore(flags); |
e56660dd | 463 | |
9df30794 | 464 | dst->pages[page] = d; |
e56660dd CW |
465 | |
466 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
467 | } |
468 | dst->page_count = page_count; | |
469 | dst->gtt_offset = src_priv->gtt_offset; | |
470 | ||
471 | return dst; | |
472 | ||
473 | unwind: | |
474 | while (page--) | |
475 | kfree(dst->pages[page]); | |
476 | kfree(dst); | |
477 | return NULL; | |
478 | } | |
479 | ||
480 | static void | |
481 | i915_error_object_free(struct drm_i915_error_object *obj) | |
482 | { | |
483 | int page; | |
484 | ||
485 | if (obj == NULL) | |
486 | return; | |
487 | ||
488 | for (page = 0; page < obj->page_count; page++) | |
489 | kfree(obj->pages[page]); | |
490 | ||
491 | kfree(obj); | |
492 | } | |
493 | ||
494 | static void | |
495 | i915_error_state_free(struct drm_device *dev, | |
496 | struct drm_i915_error_state *error) | |
497 | { | |
498 | i915_error_object_free(error->batchbuffer[0]); | |
499 | i915_error_object_free(error->batchbuffer[1]); | |
500 | i915_error_object_free(error->ringbuffer); | |
501 | kfree(error->active_bo); | |
6ef3d427 | 502 | kfree(error->overlay); |
9df30794 CW |
503 | kfree(error); |
504 | } | |
505 | ||
506 | static u32 | |
507 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) | |
508 | { | |
509 | u32 cmd; | |
510 | ||
511 | if (IS_I830(dev) || IS_845G(dev)) | |
512 | cmd = MI_BATCH_BUFFER; | |
a6c45cf0 | 513 | else if (INTEL_INFO(dev)->gen >= 4) |
9df30794 CW |
514 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | |
515 | MI_BATCH_NON_SECURE_I965); | |
516 | else | |
517 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); | |
518 | ||
519 | return ring[0] == cmd ? ring[1] : 0; | |
520 | } | |
521 | ||
522 | static u32 | |
8168bd48 CW |
523 | i915_ringbuffer_last_batch(struct drm_device *dev, |
524 | struct intel_ring_buffer *ring) | |
9df30794 CW |
525 | { |
526 | struct drm_i915_private *dev_priv = dev->dev_private; | |
527 | u32 head, bbaddr; | |
8168bd48 | 528 | u32 *val; |
9df30794 CW |
529 | |
530 | /* Locate the current position in the ringbuffer and walk back | |
531 | * to find the most recently dispatched batch buffer. | |
532 | */ | |
533 | bbaddr = 0; | |
8168bd48 CW |
534 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
535 | val = (u32 *)(ring->virtual_start + head); | |
9df30794 | 536 | |
8168bd48 CW |
537 | while (--val >= (u32 *)ring->virtual_start) { |
538 | bbaddr = i915_get_bbaddr(dev, val); | |
9df30794 CW |
539 | if (bbaddr) |
540 | break; | |
541 | } | |
542 | ||
543 | if (bbaddr == 0) { | |
8168bd48 CW |
544 | val = (u32 *)(ring->virtual_start + ring->size); |
545 | while (--val >= (u32 *)ring->virtual_start) { | |
546 | bbaddr = i915_get_bbaddr(dev, val); | |
9df30794 CW |
547 | if (bbaddr) |
548 | break; | |
549 | } | |
550 | } | |
551 | ||
552 | return bbaddr; | |
553 | } | |
554 | ||
c724e8a9 CW |
555 | static u32 capture_bo_list(struct drm_i915_error_buffer *err, |
556 | int count, | |
557 | struct list_head *head) | |
558 | { | |
559 | struct drm_i915_gem_object *obj; | |
560 | int i = 0; | |
561 | ||
562 | list_for_each_entry(obj, head, mm_list) { | |
563 | err->size = obj->base.size; | |
564 | err->name = obj->base.name; | |
565 | err->seqno = obj->last_rendering_seqno; | |
566 | err->gtt_offset = obj->gtt_offset; | |
567 | err->read_domains = obj->base.read_domains; | |
568 | err->write_domain = obj->base.write_domain; | |
569 | err->fence_reg = obj->fence_reg; | |
570 | err->pinned = 0; | |
571 | if (obj->pin_count > 0) | |
572 | err->pinned = 1; | |
573 | if (obj->user_pin_count > 0) | |
574 | err->pinned = -1; | |
575 | err->tiling = obj->tiling_mode; | |
576 | err->dirty = obj->dirty; | |
577 | err->purgeable = obj->madv != I915_MADV_WILLNEED; | |
578 | err->ring = obj->ring->id; | |
579 | ||
580 | if (++i == count) | |
581 | break; | |
582 | ||
583 | err++; | |
584 | } | |
585 | ||
586 | return i; | |
587 | } | |
588 | ||
8a905236 JB |
589 | /** |
590 | * i915_capture_error_state - capture an error record for later analysis | |
591 | * @dev: drm device | |
592 | * | |
593 | * Should be called when an error is detected (either a hang or an error | |
594 | * interrupt) to capture error state from the time of the error. Fills | |
595 | * out a structure which becomes available in debugfs for user level tools | |
596 | * to pick up. | |
597 | */ | |
63eeaf38 JB |
598 | static void i915_capture_error_state(struct drm_device *dev) |
599 | { | |
600 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9df30794 | 601 | struct drm_i915_gem_object *obj_priv; |
63eeaf38 | 602 | struct drm_i915_error_state *error; |
9df30794 | 603 | struct drm_gem_object *batchbuffer[2]; |
63eeaf38 | 604 | unsigned long flags; |
9df30794 CW |
605 | u32 bbaddr; |
606 | int count; | |
63eeaf38 JB |
607 | |
608 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
609 | error = dev_priv->first_error; |
610 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
611 | if (error) | |
612 | return; | |
63eeaf38 JB |
613 | |
614 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
615 | if (!error) { | |
9df30794 CW |
616 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
617 | return; | |
63eeaf38 JB |
618 | } |
619 | ||
2fa772f3 CW |
620 | DRM_DEBUG_DRIVER("generating error event\n"); |
621 | ||
f787a5f5 | 622 | error->seqno = |
78501eac | 623 | dev_priv->render_ring.get_seqno(&dev_priv->render_ring); |
63eeaf38 JB |
624 | error->eir = I915_READ(EIR); |
625 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
626 | error->pipeastat = I915_READ(PIPEASTAT); | |
627 | error->pipebstat = I915_READ(PIPEBSTAT); | |
628 | error->instpm = I915_READ(INSTPM); | |
f406839f CW |
629 | error->error = 0; |
630 | if (INTEL_INFO(dev)->gen >= 6) { | |
631 | error->error = I915_READ(ERROR_GEN6); | |
add354dd | 632 | |
1d8f38f4 CW |
633 | error->bcs_acthd = I915_READ(BCS_ACTHD); |
634 | error->bcs_ipehr = I915_READ(BCS_IPEHR); | |
635 | error->bcs_ipeir = I915_READ(BCS_IPEIR); | |
636 | error->bcs_instdone = I915_READ(BCS_INSTDONE); | |
637 | error->bcs_seqno = 0; | |
638 | if (dev_priv->blt_ring.get_seqno) | |
639 | error->bcs_seqno = dev_priv->blt_ring.get_seqno(&dev_priv->blt_ring); | |
add354dd CW |
640 | |
641 | error->vcs_acthd = I915_READ(VCS_ACTHD); | |
642 | error->vcs_ipehr = I915_READ(VCS_IPEHR); | |
643 | error->vcs_ipeir = I915_READ(VCS_IPEIR); | |
644 | error->vcs_instdone = I915_READ(VCS_INSTDONE); | |
645 | error->vcs_seqno = 0; | |
646 | if (dev_priv->bsd_ring.get_seqno) | |
647 | error->vcs_seqno = dev_priv->bsd_ring.get_seqno(&dev_priv->bsd_ring); | |
f406839f CW |
648 | } |
649 | if (INTEL_INFO(dev)->gen >= 4) { | |
63eeaf38 JB |
650 | error->ipeir = I915_READ(IPEIR_I965); |
651 | error->ipehr = I915_READ(IPEHR_I965); | |
652 | error->instdone = I915_READ(INSTDONE_I965); | |
653 | error->instps = I915_READ(INSTPS); | |
654 | error->instdone1 = I915_READ(INSTDONE1); | |
655 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 656 | error->bbaddr = I915_READ64(BB_ADDR); |
f406839f CW |
657 | } else { |
658 | error->ipeir = I915_READ(IPEIR); | |
659 | error->ipehr = I915_READ(IPEHR); | |
660 | error->instdone = I915_READ(INSTDONE); | |
661 | error->acthd = I915_READ(ACTHD); | |
662 | error->bbaddr = 0; | |
63eeaf38 JB |
663 | } |
664 | ||
8168bd48 | 665 | bbaddr = i915_ringbuffer_last_batch(dev, &dev_priv->render_ring); |
8a905236 | 666 | |
9df30794 CW |
667 | /* Grab the current batchbuffer, most likely to have crashed. */ |
668 | batchbuffer[0] = NULL; | |
669 | batchbuffer[1] = NULL; | |
670 | count = 0; | |
69dc4987 | 671 | list_for_each_entry(obj_priv, &dev_priv->mm.active_list, mm_list) { |
a8089e84 | 672 | struct drm_gem_object *obj = &obj_priv->base; |
63eeaf38 | 673 | |
9df30794 CW |
674 | if (batchbuffer[0] == NULL && |
675 | bbaddr >= obj_priv->gtt_offset && | |
676 | bbaddr < obj_priv->gtt_offset + obj->size) | |
677 | batchbuffer[0] = obj; | |
678 | ||
679 | if (batchbuffer[1] == NULL && | |
680 | error->acthd >= obj_priv->gtt_offset && | |
e56660dd | 681 | error->acthd < obj_priv->gtt_offset + obj->size) |
9df30794 CW |
682 | batchbuffer[1] = obj; |
683 | ||
684 | count++; | |
685 | } | |
e56660dd CW |
686 | /* Scan the other lists for completeness for those bizarre errors. */ |
687 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
69dc4987 | 688 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, mm_list) { |
e56660dd CW |
689 | struct drm_gem_object *obj = &obj_priv->base; |
690 | ||
691 | if (batchbuffer[0] == NULL && | |
692 | bbaddr >= obj_priv->gtt_offset && | |
693 | bbaddr < obj_priv->gtt_offset + obj->size) | |
694 | batchbuffer[0] = obj; | |
695 | ||
696 | if (batchbuffer[1] == NULL && | |
697 | error->acthd >= obj_priv->gtt_offset && | |
698 | error->acthd < obj_priv->gtt_offset + obj->size) | |
699 | batchbuffer[1] = obj; | |
700 | ||
701 | if (batchbuffer[0] && batchbuffer[1]) | |
702 | break; | |
703 | } | |
704 | } | |
705 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
69dc4987 | 706 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, mm_list) { |
e56660dd CW |
707 | struct drm_gem_object *obj = &obj_priv->base; |
708 | ||
709 | if (batchbuffer[0] == NULL && | |
710 | bbaddr >= obj_priv->gtt_offset && | |
711 | bbaddr < obj_priv->gtt_offset + obj->size) | |
712 | batchbuffer[0] = obj; | |
713 | ||
714 | if (batchbuffer[1] == NULL && | |
715 | error->acthd >= obj_priv->gtt_offset && | |
716 | error->acthd < obj_priv->gtt_offset + obj->size) | |
717 | batchbuffer[1] = obj; | |
718 | ||
719 | if (batchbuffer[0] && batchbuffer[1]) | |
720 | break; | |
721 | } | |
722 | } | |
9df30794 CW |
723 | |
724 | /* We need to copy these to an anonymous buffer as the simplest | |
139d363b | 725 | * method to avoid being overwritten by userspace. |
9df30794 CW |
726 | */ |
727 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); | |
e56660dd CW |
728 | if (batchbuffer[1] != batchbuffer[0]) |
729 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); | |
730 | else | |
731 | error->batchbuffer[1] = NULL; | |
9df30794 CW |
732 | |
733 | /* Record the ringbuffer */ | |
8187a2b7 ZN |
734 | error->ringbuffer = i915_error_object_create(dev, |
735 | dev_priv->render_ring.gem_object); | |
9df30794 | 736 | |
c724e8a9 | 737 | /* Record buffers on the active and pinned lists. */ |
9df30794 | 738 | error->active_bo = NULL; |
c724e8a9 | 739 | error->pinned_bo = NULL; |
9df30794 | 740 | |
c724e8a9 CW |
741 | error->active_bo_count = count; |
742 | list_for_each_entry(obj_priv, &dev_priv->mm.pinned_list, mm_list) | |
743 | count++; | |
744 | error->pinned_bo_count = count - error->active_bo_count; | |
745 | ||
746 | if (count) { | |
9df30794 CW |
747 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, |
748 | GFP_ATOMIC); | |
c724e8a9 CW |
749 | if (error->active_bo) |
750 | error->pinned_bo = | |
751 | error->active_bo + error->active_bo_count; | |
9df30794 CW |
752 | } |
753 | ||
c724e8a9 CW |
754 | if (error->active_bo) |
755 | error->active_bo_count = | |
756 | capture_bo_list(error->active_bo, | |
757 | error->active_bo_count, | |
758 | &dev_priv->mm.active_list); | |
759 | ||
760 | if (error->pinned_bo) | |
761 | error->pinned_bo_count = | |
762 | capture_bo_list(error->pinned_bo, | |
763 | error->pinned_bo_count, | |
764 | &dev_priv->mm.pinned_list); | |
765 | ||
9df30794 CW |
766 | do_gettimeofday(&error->time); |
767 | ||
6ef3d427 CW |
768 | error->overlay = intel_overlay_capture_error_state(dev); |
769 | ||
9df30794 CW |
770 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
771 | if (dev_priv->first_error == NULL) { | |
772 | dev_priv->first_error = error; | |
773 | error = NULL; | |
774 | } | |
63eeaf38 | 775 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
776 | |
777 | if (error) | |
778 | i915_error_state_free(dev, error); | |
779 | } | |
780 | ||
781 | void i915_destroy_error_state(struct drm_device *dev) | |
782 | { | |
783 | struct drm_i915_private *dev_priv = dev->dev_private; | |
784 | struct drm_i915_error_state *error; | |
785 | ||
786 | spin_lock(&dev_priv->error_lock); | |
787 | error = dev_priv->first_error; | |
788 | dev_priv->first_error = NULL; | |
789 | spin_unlock(&dev_priv->error_lock); | |
790 | ||
791 | if (error) | |
792 | i915_error_state_free(dev, error); | |
63eeaf38 | 793 | } |
3bd3c932 CW |
794 | #else |
795 | #define i915_capture_error_state(x) | |
796 | #endif | |
63eeaf38 | 797 | |
35aed2e6 | 798 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
799 | { |
800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
801 | u32 eir = I915_READ(EIR); | |
8a905236 | 802 | |
35aed2e6 CW |
803 | if (!eir) |
804 | return; | |
8a905236 JB |
805 | |
806 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
807 | eir); | |
808 | ||
809 | if (IS_G4X(dev)) { | |
810 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
811 | u32 ipeir = I915_READ(IPEIR_I965); | |
812 | ||
813 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
814 | I915_READ(IPEIR_I965)); | |
815 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
816 | I915_READ(IPEHR_I965)); | |
817 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
818 | I915_READ(INSTDONE_I965)); | |
819 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
820 | I915_READ(INSTPS)); | |
821 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
822 | I915_READ(INSTDONE1)); | |
823 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
824 | I915_READ(ACTHD_I965)); | |
825 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 826 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
827 | } |
828 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
829 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
830 | printk(KERN_ERR "page table error\n"); | |
831 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
832 | pgtbl_err); | |
833 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 834 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
835 | } |
836 | } | |
837 | ||
a6c45cf0 | 838 | if (!IS_GEN2(dev)) { |
8a905236 JB |
839 | if (eir & I915_ERROR_PAGE_TABLE) { |
840 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
841 | printk(KERN_ERR "page table error\n"); | |
842 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
843 | pgtbl_err); | |
844 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
3143a2bf | 845 | POSTING_READ(PGTBL_ER); |
8a905236 JB |
846 | } |
847 | } | |
848 | ||
849 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
35aed2e6 CW |
850 | u32 pipea_stats = I915_READ(PIPEASTAT); |
851 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
852 | ||
8a905236 JB |
853 | printk(KERN_ERR "memory refresh error\n"); |
854 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
855 | pipea_stats); | |
856 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
857 | pipeb_stats); | |
858 | /* pipestat has already been acked */ | |
859 | } | |
860 | if (eir & I915_ERROR_INSTRUCTION) { | |
861 | printk(KERN_ERR "instruction error\n"); | |
862 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
863 | I915_READ(INSTPM)); | |
a6c45cf0 | 864 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
865 | u32 ipeir = I915_READ(IPEIR); |
866 | ||
867 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
868 | I915_READ(IPEIR)); | |
869 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
870 | I915_READ(IPEHR)); | |
871 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
872 | I915_READ(INSTDONE)); | |
873 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
874 | I915_READ(ACTHD)); | |
875 | I915_WRITE(IPEIR, ipeir); | |
3143a2bf | 876 | POSTING_READ(IPEIR); |
8a905236 JB |
877 | } else { |
878 | u32 ipeir = I915_READ(IPEIR_I965); | |
879 | ||
880 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
881 | I915_READ(IPEIR_I965)); | |
882 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
883 | I915_READ(IPEHR_I965)); | |
884 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
885 | I915_READ(INSTDONE_I965)); | |
886 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
887 | I915_READ(INSTPS)); | |
888 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
889 | I915_READ(INSTDONE1)); | |
890 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
891 | I915_READ(ACTHD_I965)); | |
892 | I915_WRITE(IPEIR_I965, ipeir); | |
3143a2bf | 893 | POSTING_READ(IPEIR_I965); |
8a905236 JB |
894 | } |
895 | } | |
896 | ||
897 | I915_WRITE(EIR, eir); | |
3143a2bf | 898 | POSTING_READ(EIR); |
8a905236 JB |
899 | eir = I915_READ(EIR); |
900 | if (eir) { | |
901 | /* | |
902 | * some errors might have become stuck, | |
903 | * mask them. | |
904 | */ | |
905 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
906 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
907 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
908 | } | |
35aed2e6 CW |
909 | } |
910 | ||
911 | /** | |
912 | * i915_handle_error - handle an error interrupt | |
913 | * @dev: drm device | |
914 | * | |
915 | * Do some basic checking of regsiter state at error interrupt time and | |
916 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
917 | * sure we get a record and make it available in debugfs. Fire a uevent | |
918 | * so userspace knows something bad happened (should trigger collection | |
919 | * of a ring dump etc.). | |
920 | */ | |
527f9e90 | 921 | void i915_handle_error(struct drm_device *dev, bool wedged) |
35aed2e6 CW |
922 | { |
923 | struct drm_i915_private *dev_priv = dev->dev_private; | |
924 | ||
925 | i915_capture_error_state(dev); | |
926 | i915_report_and_clear_eir(dev); | |
8a905236 | 927 | |
ba1234d1 | 928 | if (wedged) { |
30dbf0c0 | 929 | INIT_COMPLETION(dev_priv->error_completion); |
ba1234d1 BG |
930 | atomic_set(&dev_priv->mm.wedged, 1); |
931 | ||
11ed50ec BG |
932 | /* |
933 | * Wakeup waiting processes so they don't hang | |
934 | */ | |
f787a5f5 CW |
935 | wake_up_all(&dev_priv->render_ring.irq_queue); |
936 | if (HAS_BSD(dev)) | |
937 | wake_up_all(&dev_priv->bsd_ring.irq_queue); | |
549f7365 CW |
938 | if (HAS_BLT(dev)) |
939 | wake_up_all(&dev_priv->blt_ring.irq_queue); | |
11ed50ec BG |
940 | } |
941 | ||
9c9fe1f8 | 942 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
943 | } |
944 | ||
4e5359cd SF |
945 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
946 | { | |
947 | drm_i915_private_t *dev_priv = dev->dev_private; | |
948 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
949 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
950 | struct drm_i915_gem_object *obj_priv; | |
951 | struct intel_unpin_work *work; | |
952 | unsigned long flags; | |
953 | bool stall_detected; | |
954 | ||
955 | /* Ignore early vblank irqs */ | |
956 | if (intel_crtc == NULL) | |
957 | return; | |
958 | ||
959 | spin_lock_irqsave(&dev->event_lock, flags); | |
960 | work = intel_crtc->unpin_work; | |
961 | ||
962 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
963 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
964 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
965 | return; | |
966 | } | |
967 | ||
968 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
969 | obj_priv = to_intel_bo(work->pending_flip_obj); | |
a6c45cf0 | 970 | if (INTEL_INFO(dev)->gen >= 4) { |
4e5359cd SF |
971 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; |
972 | stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset; | |
973 | } else { | |
974 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; | |
975 | stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset + | |
976 | crtc->y * crtc->fb->pitch + | |
977 | crtc->x * crtc->fb->bits_per_pixel/8); | |
978 | } | |
979 | ||
980 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
981 | ||
982 | if (stall_detected) { | |
983 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
984 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
985 | } | |
986 | } | |
987 | ||
1da177e4 LT |
988 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
989 | { | |
84b1fd10 | 990 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 991 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 992 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
993 | u32 iir, new_iir; |
994 | u32 pipea_stats, pipeb_stats; | |
05eff845 | 995 | u32 vblank_status; |
0a3e67a4 | 996 | int vblank = 0; |
7c463586 | 997 | unsigned long irqflags; |
05eff845 KP |
998 | int irq_received; |
999 | int ret = IRQ_NONE; | |
6e5fca53 | 1000 | |
630681d9 EA |
1001 | atomic_inc(&dev_priv->irq_received); |
1002 | ||
bad720ff | 1003 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1004 | return ironlake_irq_handler(dev); |
036a4a7d | 1005 | |
ed4cb414 | 1006 | iir = I915_READ(IIR); |
a6b54f3f | 1007 | |
a6c45cf0 | 1008 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 1009 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 1010 | else |
d874bcff | 1011 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 1012 | |
05eff845 KP |
1013 | for (;;) { |
1014 | irq_received = iir != 0; | |
1015 | ||
1016 | /* Can't rely on pipestat interrupt bit in iir as it might | |
1017 | * have been cleared after the pipestat interrupt was received. | |
1018 | * It doesn't set the bit in iir again, but it still produces | |
1019 | * interrupts (for non-MSI). | |
1020 | */ | |
1021 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
1022 | pipea_stats = I915_READ(PIPEASTAT); | |
1023 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 1024 | |
8a905236 | 1025 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 1026 | i915_handle_error(dev, false); |
8a905236 | 1027 | |
cdfbc41f EA |
1028 | /* |
1029 | * Clear the PIPE(A|B)STAT regs before the IIR | |
1030 | */ | |
05eff845 | 1031 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 1032 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 1033 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 1034 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 1035 | irq_received = 1; |
cdfbc41f | 1036 | } |
1da177e4 | 1037 | |
05eff845 | 1038 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 1039 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 1040 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 1041 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 1042 | irq_received = 1; |
cdfbc41f | 1043 | } |
05eff845 KP |
1044 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
1045 | ||
1046 | if (!irq_received) | |
1047 | break; | |
1048 | ||
1049 | ret = IRQ_HANDLED; | |
8ee1c3db | 1050 | |
5ca58282 JB |
1051 | /* Consume port. Then clear IIR or we'll miss events */ |
1052 | if ((I915_HAS_HOTPLUG(dev)) && | |
1053 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
1054 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
1055 | ||
44d98a61 | 1056 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
1057 | hotplug_status); |
1058 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
1059 | queue_work(dev_priv->wq, |
1060 | &dev_priv->hotplug_work); | |
5ca58282 JB |
1061 | |
1062 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
1063 | I915_READ(PORT_HOTPLUG_STAT); | |
1064 | } | |
1065 | ||
cdfbc41f EA |
1066 | I915_WRITE(IIR, iir); |
1067 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1068 | |
7c1c2871 DA |
1069 | if (dev->primary->master) { |
1070 | master_priv = dev->primary->master->driver_priv; | |
1071 | if (master_priv->sarea_priv) | |
1072 | master_priv->sarea_priv->last_dispatch = | |
1073 | READ_BREADCRUMB(dev_priv); | |
1074 | } | |
0a3e67a4 | 1075 | |
549f7365 CW |
1076 | if (iir & I915_USER_INTERRUPT) |
1077 | notify_ring(dev, &dev_priv->render_ring); | |
d1b851fc | 1078 | if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT)) |
549f7365 | 1079 | notify_ring(dev, &dev_priv->bsd_ring); |
d1b851fc | 1080 | |
1afe3e9d | 1081 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1082 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1083 | if (dev_priv->flip_pending_is_done) |
1084 | intel_finish_page_flip_plane(dev, 0); | |
1085 | } | |
6b95a207 | 1086 | |
1afe3e9d | 1087 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1088 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1089 | if (dev_priv->flip_pending_is_done) |
1090 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1091 | } |
6b95a207 | 1092 | |
05eff845 | 1093 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
1094 | vblank++; |
1095 | drm_handle_vblank(dev, 0); | |
4e5359cd SF |
1096 | if (!dev_priv->flip_pending_is_done) { |
1097 | i915_pageflip_stall_check(dev, 0); | |
1afe3e9d | 1098 | intel_finish_page_flip(dev, 0); |
4e5359cd | 1099 | } |
cdfbc41f | 1100 | } |
7c463586 | 1101 | |
05eff845 | 1102 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
1103 | vblank++; |
1104 | drm_handle_vblank(dev, 1); | |
4e5359cd SF |
1105 | if (!dev_priv->flip_pending_is_done) { |
1106 | i915_pageflip_stall_check(dev, 1); | |
1afe3e9d | 1107 | intel_finish_page_flip(dev, 1); |
4e5359cd | 1108 | } |
cdfbc41f | 1109 | } |
7c463586 | 1110 | |
d874bcff JB |
1111 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
1112 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || | |
cdfbc41f | 1113 | (iir & I915_ASLE_INTERRUPT)) |
3b617967 | 1114 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1115 | |
1116 | /* With MSI, interrupts are only generated when iir | |
1117 | * transitions from zero to nonzero. If another bit got | |
1118 | * set while we were handling the existing iir bits, then | |
1119 | * we would never get another interrupt. | |
1120 | * | |
1121 | * This is fine on non-MSI as well, as if we hit this path | |
1122 | * we avoid exiting the interrupt handler only to generate | |
1123 | * another one. | |
1124 | * | |
1125 | * Note that for MSI this could cause a stray interrupt report | |
1126 | * if an interrupt landed in the time between writing IIR and | |
1127 | * the posting read. This should be rare enough to never | |
1128 | * trigger the 99% of 100,000 interrupts test for disabling | |
1129 | * stray interrupts. | |
1130 | */ | |
1131 | iir = new_iir; | |
05eff845 | 1132 | } |
0a3e67a4 | 1133 | |
05eff845 | 1134 | return ret; |
1da177e4 LT |
1135 | } |
1136 | ||
af6061af | 1137 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1138 | { |
1139 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1140 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1141 | |
1142 | i915_kernel_lost_context(dev); | |
1143 | ||
44d98a61 | 1144 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1145 | |
c99b058f | 1146 | dev_priv->counter++; |
c29b669c | 1147 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1148 | dev_priv->counter = 1; |
7c1c2871 DA |
1149 | if (master_priv->sarea_priv) |
1150 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1151 | |
e1f99ce6 CW |
1152 | if (BEGIN_LP_RING(4) == 0) { |
1153 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1154 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1155 | OUT_RING(dev_priv->counter); | |
1156 | OUT_RING(MI_USER_INTERRUPT); | |
1157 | ADVANCE_LP_RING(); | |
1158 | } | |
bc5f4523 | 1159 | |
c29b669c | 1160 | return dev_priv->counter; |
1da177e4 LT |
1161 | } |
1162 | ||
9d34e5db CW |
1163 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
1164 | { | |
1165 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8187a2b7 | 1166 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
9d34e5db CW |
1167 | |
1168 | if (dev_priv->trace_irq_seqno == 0) | |
78501eac | 1169 | render_ring->user_irq_get(render_ring); |
9d34e5db CW |
1170 | |
1171 | dev_priv->trace_irq_seqno = seqno; | |
1172 | } | |
1173 | ||
84b1fd10 | 1174 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1175 | { |
1176 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1177 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1178 | int ret = 0; |
8187a2b7 | 1179 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
1da177e4 | 1180 | |
44d98a61 | 1181 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1182 | READ_BREADCRUMB(dev_priv)); |
1183 | ||
ed4cb414 | 1184 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1185 | if (master_priv->sarea_priv) |
1186 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1187 | return 0; |
ed4cb414 | 1188 | } |
1da177e4 | 1189 | |
7c1c2871 DA |
1190 | if (master_priv->sarea_priv) |
1191 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1192 | |
78501eac | 1193 | render_ring->user_irq_get(render_ring); |
852835f3 | 1194 | DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ, |
1da177e4 | 1195 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
78501eac | 1196 | render_ring->user_irq_put(render_ring); |
1da177e4 | 1197 | |
20caafa6 | 1198 | if (ret == -EBUSY) { |
3e684eae | 1199 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1200 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1201 | } | |
1202 | ||
af6061af DA |
1203 | return ret; |
1204 | } | |
1205 | ||
1da177e4 LT |
1206 | /* Needs the lock as it touches the ring. |
1207 | */ | |
c153f45f EA |
1208 | int i915_irq_emit(struct drm_device *dev, void *data, |
1209 | struct drm_file *file_priv) | |
1da177e4 | 1210 | { |
1da177e4 | 1211 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1212 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1213 | int result; |
1214 | ||
d3301d86 | 1215 | if (!dev_priv || !dev_priv->render_ring.virtual_start) { |
3e684eae | 1216 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1217 | return -EINVAL; |
1da177e4 | 1218 | } |
299eb93c EA |
1219 | |
1220 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1221 | ||
546b0974 | 1222 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1223 | result = i915_emit_irq(dev); |
546b0974 | 1224 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1225 | |
c153f45f | 1226 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1227 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1228 | return -EFAULT; |
1da177e4 LT |
1229 | } |
1230 | ||
1231 | return 0; | |
1232 | } | |
1233 | ||
1234 | /* Doesn't need the hardware lock. | |
1235 | */ | |
c153f45f EA |
1236 | int i915_irq_wait(struct drm_device *dev, void *data, |
1237 | struct drm_file *file_priv) | |
1da177e4 | 1238 | { |
1da177e4 | 1239 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1240 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1241 | |
1242 | if (!dev_priv) { | |
3e684eae | 1243 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1244 | return -EINVAL; |
1da177e4 LT |
1245 | } |
1246 | ||
c153f45f | 1247 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1248 | } |
1249 | ||
42f52ef8 KP |
1250 | /* Called from drm generic code, passed 'crtc' which |
1251 | * we use as a pipe index | |
1252 | */ | |
1253 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1254 | { |
1255 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1256 | unsigned long irqflags; |
71e0ffa5 | 1257 | |
5eddb70b | 1258 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1259 | return -EINVAL; |
0a3e67a4 | 1260 | |
e9d21d7f | 1261 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1262 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1263 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
1264 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
a6c45cf0 | 1265 | else if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1266 | i915_enable_pipestat(dev_priv, pipe, |
1267 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1268 | else |
7c463586 KP |
1269 | i915_enable_pipestat(dev_priv, pipe, |
1270 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1271 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1272 | return 0; |
1273 | } | |
1274 | ||
42f52ef8 KP |
1275 | /* Called from drm generic code, passed 'crtc' which |
1276 | * we use as a pipe index | |
1277 | */ | |
1278 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1279 | { |
1280 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1281 | unsigned long irqflags; |
0a3e67a4 | 1282 | |
e9d21d7f | 1283 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1284 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1285 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
1286 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1287 | else | |
1288 | i915_disable_pipestat(dev_priv, pipe, | |
1289 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1290 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1291 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1292 | } |
1293 | ||
79e53945 JB |
1294 | void i915_enable_interrupt (struct drm_device *dev) |
1295 | { | |
1296 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 | 1297 | |
bad720ff | 1298 | if (!HAS_PCH_SPLIT(dev)) |
3b617967 | 1299 | intel_opregion_enable_asle(dev); |
79e53945 JB |
1300 | dev_priv->irq_enabled = 1; |
1301 | } | |
1302 | ||
1303 | ||
702880f2 DA |
1304 | /* Set the vblank monitor pipe |
1305 | */ | |
c153f45f EA |
1306 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1307 | struct drm_file *file_priv) | |
702880f2 | 1308 | { |
702880f2 | 1309 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1310 | |
1311 | if (!dev_priv) { | |
3e684eae | 1312 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1313 | return -EINVAL; |
702880f2 DA |
1314 | } |
1315 | ||
5b51694a | 1316 | return 0; |
702880f2 DA |
1317 | } |
1318 | ||
c153f45f EA |
1319 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1320 | struct drm_file *file_priv) | |
702880f2 | 1321 | { |
702880f2 | 1322 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1323 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1324 | |
1325 | if (!dev_priv) { | |
3e684eae | 1326 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1327 | return -EINVAL; |
702880f2 DA |
1328 | } |
1329 | ||
0a3e67a4 | 1330 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1331 | |
702880f2 DA |
1332 | return 0; |
1333 | } | |
1334 | ||
a6b54f3f MD |
1335 | /** |
1336 | * Schedule buffer swap at given vertical blank. | |
1337 | */ | |
c153f45f EA |
1338 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1339 | struct drm_file *file_priv) | |
a6b54f3f | 1340 | { |
bd95e0a4 EA |
1341 | /* The delayed swap mechanism was fundamentally racy, and has been |
1342 | * removed. The model was that the client requested a delayed flip/swap | |
1343 | * from the kernel, then waited for vblank before continuing to perform | |
1344 | * rendering. The problem was that the kernel might wake the client | |
1345 | * up before it dispatched the vblank swap (since the lock has to be | |
1346 | * held while touching the ringbuffer), in which case the client would | |
1347 | * clear and start the next frame before the swap occurred, and | |
1348 | * flicker would occur in addition to likely missing the vblank. | |
1349 | * | |
1350 | * In the absence of this ioctl, userland falls back to a correct path | |
1351 | * of waiting for a vblank, then dispatching the swap on its own. | |
1352 | * Context switching to userland and back is plenty fast enough for | |
1353 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1354 | */ |
bd95e0a4 | 1355 | return -EINVAL; |
a6b54f3f MD |
1356 | } |
1357 | ||
893eead0 CW |
1358 | static u32 |
1359 | ring_last_seqno(struct intel_ring_buffer *ring) | |
852835f3 | 1360 | { |
893eead0 CW |
1361 | return list_entry(ring->request_list.prev, |
1362 | struct drm_i915_gem_request, list)->seqno; | |
1363 | } | |
1364 | ||
1365 | static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err) | |
1366 | { | |
1367 | if (list_empty(&ring->request_list) || | |
1368 | i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) { | |
1369 | /* Issue a wake-up to catch stuck h/w. */ | |
b2223497 | 1370 | if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) { |
893eead0 CW |
1371 | DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n", |
1372 | ring->name, | |
b2223497 | 1373 | ring->waiting_seqno, |
893eead0 CW |
1374 | ring->get_seqno(ring)); |
1375 | wake_up_all(&ring->irq_queue); | |
1376 | *err = true; | |
1377 | } | |
1378 | return true; | |
1379 | } | |
1380 | return false; | |
f65d9421 BG |
1381 | } |
1382 | ||
1383 | /** | |
1384 | * This is called when the chip hasn't reported back with completed | |
1385 | * batchbuffers in a long time. The first time this is called we simply record | |
1386 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1387 | * again, we assume the chip is wedged and try to fix it. | |
1388 | */ | |
1389 | void i915_hangcheck_elapsed(unsigned long data) | |
1390 | { | |
1391 | struct drm_device *dev = (struct drm_device *)data; | |
1392 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1393 | uint32_t acthd, instdone, instdone1; |
893eead0 CW |
1394 | bool err = false; |
1395 | ||
1396 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
1397 | if (i915_hangcheck_ring_idle(&dev_priv->render_ring, &err) && | |
1398 | i915_hangcheck_ring_idle(&dev_priv->bsd_ring, &err) && | |
1399 | i915_hangcheck_ring_idle(&dev_priv->blt_ring, &err)) { | |
1400 | dev_priv->hangcheck_count = 0; | |
1401 | if (err) | |
1402 | goto repeat; | |
1403 | return; | |
1404 | } | |
b9201c14 | 1405 | |
a6c45cf0 | 1406 | if (INTEL_INFO(dev)->gen < 4) { |
f65d9421 | 1407 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1408 | instdone = I915_READ(INSTDONE); |
1409 | instdone1 = 0; | |
1410 | } else { | |
f65d9421 | 1411 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1412 | instdone = I915_READ(INSTDONE_I965); |
1413 | instdone1 = I915_READ(INSTDONE1); | |
1414 | } | |
f65d9421 | 1415 | |
cbb465e7 CW |
1416 | if (dev_priv->last_acthd == acthd && |
1417 | dev_priv->last_instdone == instdone && | |
1418 | dev_priv->last_instdone1 == instdone1) { | |
1419 | if (dev_priv->hangcheck_count++ > 1) { | |
1420 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
8c80b59b CW |
1421 | |
1422 | if (!IS_GEN2(dev)) { | |
1423 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1424 | * If so we can simply poke the RB_WAIT bit | |
1425 | * and break the hang. This should work on | |
1426 | * all but the second generation chipsets. | |
1427 | */ | |
8168bd48 CW |
1428 | struct intel_ring_buffer *ring = &dev_priv->render_ring; |
1429 | u32 tmp = I915_READ_CTL(ring); | |
8c80b59b | 1430 | if (tmp & RING_WAIT) { |
8168bd48 | 1431 | I915_WRITE_CTL(ring, tmp); |
893eead0 | 1432 | goto repeat; |
8c80b59b CW |
1433 | } |
1434 | } | |
1435 | ||
cbb465e7 CW |
1436 | i915_handle_error(dev, true); |
1437 | return; | |
1438 | } | |
1439 | } else { | |
1440 | dev_priv->hangcheck_count = 0; | |
1441 | ||
1442 | dev_priv->last_acthd = acthd; | |
1443 | dev_priv->last_instdone = instdone; | |
1444 | dev_priv->last_instdone1 = instdone1; | |
1445 | } | |
f65d9421 | 1446 | |
893eead0 | 1447 | repeat: |
f65d9421 | 1448 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1449 | mod_timer(&dev_priv->hangcheck_timer, |
1450 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1451 | } |
1452 | ||
1da177e4 LT |
1453 | /* drm_dma.h hooks |
1454 | */ | |
f2b115e6 | 1455 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1456 | { |
1457 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1458 | ||
1459 | I915_WRITE(HWSTAM, 0xeffe); | |
1460 | ||
1461 | /* XXX hotplug from PCH */ | |
1462 | ||
1463 | I915_WRITE(DEIMR, 0xffffffff); | |
1464 | I915_WRITE(DEIER, 0x0); | |
3143a2bf | 1465 | POSTING_READ(DEIER); |
036a4a7d ZW |
1466 | |
1467 | /* and GT */ | |
1468 | I915_WRITE(GTIMR, 0xffffffff); | |
1469 | I915_WRITE(GTIER, 0x0); | |
3143a2bf | 1470 | POSTING_READ(GTIER); |
c650156a ZW |
1471 | |
1472 | /* south display irq */ | |
1473 | I915_WRITE(SDEIMR, 0xffffffff); | |
1474 | I915_WRITE(SDEIER, 0x0); | |
3143a2bf | 1475 | POSTING_READ(SDEIER); |
036a4a7d ZW |
1476 | } |
1477 | ||
f2b115e6 | 1478 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1479 | { |
1480 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1481 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1482 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1483 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
d1b851fc | 1484 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; |
2d7b8366 | 1485 | u32 hotplug_mask; |
036a4a7d ZW |
1486 | |
1487 | dev_priv->irq_mask_reg = ~display_mask; | |
643ced9b | 1488 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
036a4a7d ZW |
1489 | |
1490 | /* should always can generate irq */ | |
1491 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1492 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1493 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
3143a2bf | 1494 | POSTING_READ(DEIER); |
036a4a7d | 1495 | |
549f7365 CW |
1496 | if (IS_GEN6(dev)) { |
1497 | render_mask = | |
1498 | GT_PIPE_NOTIFY | | |
1499 | GT_GEN6_BSD_USER_INTERRUPT | | |
1500 | GT_BLT_USER_INTERRUPT; | |
1501 | } | |
3fdef020 | 1502 | |
852835f3 | 1503 | dev_priv->gt_irq_mask_reg = ~render_mask; |
036a4a7d ZW |
1504 | dev_priv->gt_irq_enable_reg = render_mask; |
1505 | ||
1506 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1507 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
881f47b6 | 1508 | if (IS_GEN6(dev)) { |
3fdef020 | 1509 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); |
881f47b6 | 1510 | I915_WRITE(GEN6_BSD_IMR, ~GEN6_BSD_IMR_USER_INTERRUPT); |
549f7365 | 1511 | I915_WRITE(GEN6_BLITTER_IMR, ~GEN6_BLITTER_USER_INTERRUPT); |
881f47b6 XH |
1512 | } |
1513 | ||
036a4a7d | 1514 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
3143a2bf | 1515 | POSTING_READ(GTIER); |
036a4a7d | 1516 | |
2d7b8366 YL |
1517 | if (HAS_PCH_CPT(dev)) { |
1518 | hotplug_mask = SDE_CRT_HOTPLUG_CPT | SDE_PORTB_HOTPLUG_CPT | | |
1519 | SDE_PORTC_HOTPLUG_CPT | SDE_PORTD_HOTPLUG_CPT ; | |
1520 | } else { | |
1521 | hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | | |
1522 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
1523 | } | |
1524 | ||
c650156a ZW |
1525 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1526 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1527 | ||
1528 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1529 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1530 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
3143a2bf | 1531 | POSTING_READ(SDEIER); |
c650156a | 1532 | |
f97108d1 JB |
1533 | if (IS_IRONLAKE_M(dev)) { |
1534 | /* Clear & enable PCU event interrupts */ | |
1535 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1536 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1537 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1538 | } | |
1539 | ||
036a4a7d ZW |
1540 | return 0; |
1541 | } | |
1542 | ||
84b1fd10 | 1543 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1544 | { |
1545 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1546 | ||
79e53945 JB |
1547 | atomic_set(&dev_priv->irq_received, 0); |
1548 | ||
036a4a7d | 1549 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1550 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1551 | |
bad720ff | 1552 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1553 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1554 | return; |
1555 | } | |
1556 | ||
5ca58282 JB |
1557 | if (I915_HAS_HOTPLUG(dev)) { |
1558 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1559 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1560 | } | |
1561 | ||
0a3e67a4 | 1562 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1563 | I915_WRITE(PIPEASTAT, 0); |
1564 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1565 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1566 | I915_WRITE(IER, 0x0); |
3143a2bf | 1567 | POSTING_READ(IER); |
1da177e4 LT |
1568 | } |
1569 | ||
b01f2c3a JB |
1570 | /* |
1571 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1572 | * enabled correctly. | |
1573 | */ | |
0a3e67a4 | 1574 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1575 | { |
1576 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1577 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1578 | u32 error_mask; |
0a3e67a4 | 1579 | |
852835f3 | 1580 | DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue); |
d1b851fc ZN |
1581 | if (HAS_BSD(dev)) |
1582 | DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue); | |
549f7365 CW |
1583 | if (HAS_BLT(dev)) |
1584 | DRM_INIT_WAITQUEUE(&dev_priv->blt_ring.irq_queue); | |
d1b851fc | 1585 | |
0a3e67a4 | 1586 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1587 | |
bad720ff | 1588 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1589 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1590 | |
7c463586 KP |
1591 | /* Unmask the interrupts that we always want on. */ |
1592 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1593 | ||
1594 | dev_priv->pipestat[0] = 0; | |
1595 | dev_priv->pipestat[1] = 0; | |
1596 | ||
5ca58282 | 1597 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1598 | /* Enable in IER... */ |
1599 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1600 | /* and unmask in IMR */ | |
c496fa1f | 1601 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1602 | } |
1603 | ||
63eeaf38 JB |
1604 | /* |
1605 | * Enable some error detection, note the instruction error mask | |
1606 | * bit is reserved, so we leave it masked. | |
1607 | */ | |
1608 | if (IS_G4X(dev)) { | |
1609 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1610 | GM45_ERROR_MEM_PRIV | | |
1611 | GM45_ERROR_CP_PRIV | | |
1612 | I915_ERROR_MEMORY_REFRESH); | |
1613 | } else { | |
1614 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1615 | I915_ERROR_MEMORY_REFRESH); | |
1616 | } | |
1617 | I915_WRITE(EMR, error_mask); | |
1618 | ||
7c463586 | 1619 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
c496fa1f | 1620 | I915_WRITE(IER, enable_mask); |
3143a2bf | 1621 | POSTING_READ(IER); |
ed4cb414 | 1622 | |
c496fa1f AJ |
1623 | if (I915_HAS_HOTPLUG(dev)) { |
1624 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1625 | ||
1626 | /* Note HDMI and DP share bits */ | |
1627 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1628 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1629 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1630 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1631 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1632 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1633 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1634 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1635 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1636 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1637 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1638 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1639 | |
1640 | /* Programming the CRT detection parameters tends | |
1641 | to generate a spurious hotplug event about three | |
1642 | seconds later. So just do it once. | |
1643 | */ | |
1644 | if (IS_G4X(dev)) | |
1645 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1646 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1647 | } | |
1648 | ||
c496fa1f AJ |
1649 | /* Ignore TV since it's buggy */ |
1650 | ||
1651 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1652 | } | |
1653 | ||
3b617967 | 1654 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
1655 | |
1656 | return 0; | |
1da177e4 LT |
1657 | } |
1658 | ||
f2b115e6 | 1659 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1660 | { |
1661 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1662 | I915_WRITE(HWSTAM, 0xffffffff); | |
1663 | ||
1664 | I915_WRITE(DEIMR, 0xffffffff); | |
1665 | I915_WRITE(DEIER, 0x0); | |
1666 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1667 | ||
1668 | I915_WRITE(GTIMR, 0xffffffff); | |
1669 | I915_WRITE(GTIER, 0x0); | |
1670 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1671 | } | |
1672 | ||
84b1fd10 | 1673 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1674 | { |
1675 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1676 | |
1da177e4 LT |
1677 | if (!dev_priv) |
1678 | return; | |
1679 | ||
0a3e67a4 JB |
1680 | dev_priv->vblank_pipe = 0; |
1681 | ||
bad720ff | 1682 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1683 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1684 | return; |
1685 | } | |
1686 | ||
5ca58282 JB |
1687 | if (I915_HAS_HOTPLUG(dev)) { |
1688 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1689 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1690 | } | |
1691 | ||
0a3e67a4 | 1692 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1693 | I915_WRITE(PIPEASTAT, 0); |
1694 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1695 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1696 | I915_WRITE(IER, 0x0); |
af6061af | 1697 | |
7c463586 KP |
1698 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1699 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1700 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1701 | } |