Commit | Line | Data |
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0d6aa60b | 1 | /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*- |
1da177e4 | 2 | */ |
0d6aa60b | 3 | /* |
1da177e4 LT |
4 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
5 | * All Rights Reserved. | |
bc54fd1a DA |
6 | * |
7 | * Permission is hereby granted, free of charge, to any person obtaining a | |
8 | * copy of this software and associated documentation files (the | |
9 | * "Software"), to deal in the Software without restriction, including | |
10 | * without limitation the rights to use, copy, modify, merge, publish, | |
11 | * distribute, sub license, and/or sell copies of the Software, and to | |
12 | * permit persons to whom the Software is furnished to do so, subject to | |
13 | * the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice (including the | |
16 | * next paragraph) shall be included in all copies or substantial portions | |
17 | * of the Software. | |
18 | * | |
19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
22 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
23 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
24 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
25 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
26 | * | |
0d6aa60b | 27 | */ |
1da177e4 | 28 | |
63eeaf38 | 29 | #include <linux/sysrq.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
1c5d22f7 | 35 | #include "i915_trace.h" |
79e53945 | 36 | #include "intel_drv.h" |
1da177e4 | 37 | |
1da177e4 | 38 | #define MAX_NOPID ((u32)~0) |
1da177e4 | 39 | |
7c463586 KP |
40 | /** |
41 | * Interrupts that are always left unmasked. | |
42 | * | |
43 | * Since pipe events are edge-triggered from the PIPESTAT register to IIR, | |
44 | * we leave them always unmasked in IMR and then control enabling them through | |
45 | * PIPESTAT alone. | |
46 | */ | |
6b95a207 KH |
47 | #define I915_INTERRUPT_ENABLE_FIX \ |
48 | (I915_ASLE_INTERRUPT | \ | |
49 | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \ | |
50 | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \ | |
51 | I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \ | |
52 | I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \ | |
53 | I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) | |
7c463586 KP |
54 | |
55 | /** Interrupts that we mask and unmask at runtime. */ | |
d1b851fc | 56 | #define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT) |
7c463586 | 57 | |
79e53945 JB |
58 | #define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\ |
59 | PIPE_VBLANK_INTERRUPT_STATUS) | |
60 | ||
61 | #define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\ | |
62 | PIPE_VBLANK_INTERRUPT_ENABLE) | |
63 | ||
64 | #define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \ | |
65 | DRM_I915_VBLANK_PIPE_B) | |
66 | ||
036a4a7d | 67 | void |
f2b115e6 | 68 | ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
69 | { |
70 | if ((dev_priv->gt_irq_mask_reg & mask) != 0) { | |
71 | dev_priv->gt_irq_mask_reg &= ~mask; | |
72 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
73 | (void) I915_READ(GTIMR); | |
74 | } | |
75 | } | |
76 | ||
62fdfeaf | 77 | void |
f2b115e6 | 78 | ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
79 | { |
80 | if ((dev_priv->gt_irq_mask_reg & mask) != mask) { | |
81 | dev_priv->gt_irq_mask_reg |= mask; | |
82 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
83 | (void) I915_READ(GTIMR); | |
84 | } | |
85 | } | |
86 | ||
87 | /* For display hotplug interrupt */ | |
995b6762 | 88 | static void |
f2b115e6 | 89 | ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
90 | { |
91 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
92 | dev_priv->irq_mask_reg &= ~mask; | |
93 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
94 | (void) I915_READ(DEIMR); | |
95 | } | |
96 | } | |
97 | ||
98 | static inline void | |
f2b115e6 | 99 | ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask) |
036a4a7d ZW |
100 | { |
101 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
102 | dev_priv->irq_mask_reg |= mask; | |
103 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
104 | (void) I915_READ(DEIMR); | |
105 | } | |
106 | } | |
107 | ||
8ee1c3db | 108 | void |
ed4cb414 EA |
109 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
110 | { | |
111 | if ((dev_priv->irq_mask_reg & mask) != 0) { | |
112 | dev_priv->irq_mask_reg &= ~mask; | |
113 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
114 | (void) I915_READ(IMR); | |
115 | } | |
116 | } | |
117 | ||
62fdfeaf | 118 | void |
ed4cb414 EA |
119 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
120 | { | |
121 | if ((dev_priv->irq_mask_reg & mask) != mask) { | |
122 | dev_priv->irq_mask_reg |= mask; | |
123 | I915_WRITE(IMR, dev_priv->irq_mask_reg); | |
124 | (void) I915_READ(IMR); | |
125 | } | |
126 | } | |
127 | ||
7c463586 KP |
128 | static inline u32 |
129 | i915_pipestat(int pipe) | |
130 | { | |
131 | if (pipe == 0) | |
132 | return PIPEASTAT; | |
133 | if (pipe == 1) | |
134 | return PIPEBSTAT; | |
9c84ba4e | 135 | BUG(); |
7c463586 KP |
136 | } |
137 | ||
138 | void | |
139 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
140 | { | |
141 | if ((dev_priv->pipestat[pipe] & mask) != mask) { | |
142 | u32 reg = i915_pipestat(pipe); | |
143 | ||
144 | dev_priv->pipestat[pipe] |= mask; | |
145 | /* Enable the interrupt, clear any pending status */ | |
146 | I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); | |
147 | (void) I915_READ(reg); | |
148 | } | |
149 | } | |
150 | ||
151 | void | |
152 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask) | |
153 | { | |
154 | if ((dev_priv->pipestat[pipe] & mask) != 0) { | |
155 | u32 reg = i915_pipestat(pipe); | |
156 | ||
157 | dev_priv->pipestat[pipe] &= ~mask; | |
158 | I915_WRITE(reg, dev_priv->pipestat[pipe]); | |
159 | (void) I915_READ(reg); | |
160 | } | |
161 | } | |
162 | ||
01c66889 ZY |
163 | /** |
164 | * intel_enable_asle - enable ASLE interrupt for OpRegion | |
165 | */ | |
166 | void intel_enable_asle (struct drm_device *dev) | |
167 | { | |
168 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
169 | ||
c619eed4 | 170 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 171 | ironlake_enable_display_irq(dev_priv, DE_GSE); |
edcb49ca | 172 | else { |
01c66889 | 173 | i915_enable_pipestat(dev_priv, 1, |
d874bcff | 174 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
a6c45cf0 | 175 | if (INTEL_INFO(dev)->gen >= 4) |
edcb49ca | 176 | i915_enable_pipestat(dev_priv, 0, |
d874bcff | 177 | PIPE_LEGACY_BLC_EVENT_ENABLE); |
edcb49ca | 178 | } |
01c66889 ZY |
179 | } |
180 | ||
0a3e67a4 JB |
181 | /** |
182 | * i915_pipe_enabled - check if a pipe is enabled | |
183 | * @dev: DRM device | |
184 | * @pipe: pipe to check | |
185 | * | |
186 | * Reading certain registers when the pipe is disabled can hang the chip. | |
187 | * Use this routine to make sure the PLL is running and the pipe is active | |
188 | * before reading such registers if unsure. | |
189 | */ | |
190 | static int | |
191 | i915_pipe_enabled(struct drm_device *dev, int pipe) | |
192 | { | |
193 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5eddb70b | 194 | return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; |
0a3e67a4 JB |
195 | } |
196 | ||
42f52ef8 KP |
197 | /* Called from drm generic code, passed a 'crtc', which |
198 | * we use as a pipe index | |
199 | */ | |
200 | u32 i915_get_vblank_counter(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
201 | { |
202 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
203 | unsigned long high_frame; | |
204 | unsigned long low_frame; | |
5eddb70b | 205 | u32 high1, high2, low; |
0a3e67a4 JB |
206 | |
207 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
208 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
209 | "pipe %d\n", pipe); | |
0a3e67a4 JB |
210 | return 0; |
211 | } | |
212 | ||
5eddb70b CW |
213 | high_frame = pipe ? PIPEBFRAMEHIGH : PIPEAFRAMEHIGH; |
214 | low_frame = pipe ? PIPEBFRAMEPIXEL : PIPEAFRAMEPIXEL; | |
215 | ||
0a3e67a4 JB |
216 | /* |
217 | * High & low register fields aren't synchronized, so make sure | |
218 | * we get a low value that's stable across two reads of the high | |
219 | * register. | |
220 | */ | |
221 | do { | |
5eddb70b CW |
222 | high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; |
223 | low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK; | |
224 | high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK; | |
0a3e67a4 JB |
225 | } while (high1 != high2); |
226 | ||
5eddb70b CW |
227 | high1 >>= PIPE_FRAME_HIGH_SHIFT; |
228 | low >>= PIPE_FRAME_LOW_SHIFT; | |
229 | return (high1 << 8) | low; | |
0a3e67a4 JB |
230 | } |
231 | ||
9880b7a5 JB |
232 | u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) |
233 | { | |
234 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
235 | int reg = pipe ? PIPEB_FRMCOUNT_GM45 : PIPEA_FRMCOUNT_GM45; | |
236 | ||
237 | if (!i915_pipe_enabled(dev, pipe)) { | |
44d98a61 ZY |
238 | DRM_DEBUG_DRIVER("trying to get vblank count for disabled " |
239 | "pipe %d\n", pipe); | |
9880b7a5 JB |
240 | return 0; |
241 | } | |
242 | ||
243 | return I915_READ(reg); | |
244 | } | |
245 | ||
5ca58282 JB |
246 | /* |
247 | * Handle hotplug events outside the interrupt handler proper. | |
248 | */ | |
249 | static void i915_hotplug_work_func(struct work_struct *work) | |
250 | { | |
251 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
252 | hotplug_work); | |
253 | struct drm_device *dev = dev_priv->dev; | |
c31c4ba3 | 254 | struct drm_mode_config *mode_config = &dev->mode_config; |
4ef69c7a CW |
255 | struct intel_encoder *encoder; |
256 | ||
257 | list_for_each_entry(encoder, &mode_config->encoder_list, base.head) | |
258 | if (encoder->hot_plug) | |
259 | encoder->hot_plug(encoder); | |
260 | ||
5ca58282 | 261 | /* Just fire off a uevent and let userspace tell us what to do */ |
eb1f8e4f | 262 | drm_helper_hpd_irq_event(dev); |
5ca58282 JB |
263 | } |
264 | ||
f97108d1 JB |
265 | static void i915_handle_rps_change(struct drm_device *dev) |
266 | { | |
267 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b5b72e89 | 268 | u32 busy_up, busy_down, max_avg, min_avg; |
f97108d1 JB |
269 | u8 new_delay = dev_priv->cur_delay; |
270 | ||
7648fa99 | 271 | I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG); |
b5b72e89 MG |
272 | busy_up = I915_READ(RCPREVBSYTUPAVG); |
273 | busy_down = I915_READ(RCPREVBSYTDNAVG); | |
f97108d1 JB |
274 | max_avg = I915_READ(RCBMAXAVG); |
275 | min_avg = I915_READ(RCBMINAVG); | |
276 | ||
277 | /* Handle RCS change request from hw */ | |
b5b72e89 | 278 | if (busy_up > max_avg) { |
f97108d1 JB |
279 | if (dev_priv->cur_delay != dev_priv->max_delay) |
280 | new_delay = dev_priv->cur_delay - 1; | |
281 | if (new_delay < dev_priv->max_delay) | |
282 | new_delay = dev_priv->max_delay; | |
b5b72e89 | 283 | } else if (busy_down < min_avg) { |
f97108d1 JB |
284 | if (dev_priv->cur_delay != dev_priv->min_delay) |
285 | new_delay = dev_priv->cur_delay + 1; | |
286 | if (new_delay > dev_priv->min_delay) | |
287 | new_delay = dev_priv->min_delay; | |
288 | } | |
289 | ||
7648fa99 JB |
290 | if (ironlake_set_drps(dev, new_delay)) |
291 | dev_priv->cur_delay = new_delay; | |
f97108d1 JB |
292 | |
293 | return; | |
294 | } | |
295 | ||
995b6762 | 296 | static irqreturn_t ironlake_irq_handler(struct drm_device *dev) |
036a4a7d ZW |
297 | { |
298 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
299 | int ret = IRQ_NONE; | |
3ff99164 | 300 | u32 de_iir, gt_iir, de_ier, pch_iir; |
036a4a7d | 301 | struct drm_i915_master_private *master_priv; |
852835f3 | 302 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
036a4a7d | 303 | |
2d109a84 ZN |
304 | /* disable master interrupt before clearing iir */ |
305 | de_ier = I915_READ(DEIER); | |
306 | I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL); | |
307 | (void)I915_READ(DEIER); | |
308 | ||
036a4a7d ZW |
309 | de_iir = I915_READ(DEIIR); |
310 | gt_iir = I915_READ(GTIIR); | |
c650156a | 311 | pch_iir = I915_READ(SDEIIR); |
036a4a7d | 312 | |
c7c85101 ZN |
313 | if (de_iir == 0 && gt_iir == 0 && pch_iir == 0) |
314 | goto done; | |
036a4a7d | 315 | |
c7c85101 | 316 | ret = IRQ_HANDLED; |
036a4a7d | 317 | |
c7c85101 ZN |
318 | if (dev->primary->master) { |
319 | master_priv = dev->primary->master->driver_priv; | |
320 | if (master_priv->sarea_priv) | |
321 | master_priv->sarea_priv->last_dispatch = | |
322 | READ_BREADCRUMB(dev_priv); | |
323 | } | |
036a4a7d | 324 | |
e552eb70 | 325 | if (gt_iir & GT_PIPE_NOTIFY) { |
852835f3 ZN |
326 | u32 seqno = render_ring->get_gem_seqno(dev, render_ring); |
327 | render_ring->irq_gem_seqno = seqno; | |
c7c85101 | 328 | trace_i915_gem_request_complete(dev, seqno); |
852835f3 | 329 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); |
c7c85101 | 330 | dev_priv->hangcheck_count = 0; |
b3b079db CW |
331 | mod_timer(&dev_priv->hangcheck_timer, |
332 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
c7c85101 | 333 | } |
d1b851fc ZN |
334 | if (gt_iir & GT_BSD_USER_INTERRUPT) |
335 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); | |
336 | ||
01c66889 | 337 | |
c7c85101 | 338 | if (de_iir & DE_GSE) |
3b617967 | 339 | intel_opregion_gse_intr(dev); |
c650156a | 340 | |
f072d2e7 | 341 | if (de_iir & DE_PLANEA_FLIP_DONE) { |
013d5aa2 | 342 | intel_prepare_page_flip(dev, 0); |
2bbda389 | 343 | intel_finish_page_flip_plane(dev, 0); |
f072d2e7 | 344 | } |
013d5aa2 | 345 | |
f072d2e7 | 346 | if (de_iir & DE_PLANEB_FLIP_DONE) { |
013d5aa2 | 347 | intel_prepare_page_flip(dev, 1); |
2bbda389 | 348 | intel_finish_page_flip_plane(dev, 1); |
f072d2e7 | 349 | } |
013d5aa2 | 350 | |
f072d2e7 | 351 | if (de_iir & DE_PIPEA_VBLANK) |
c062df61 LP |
352 | drm_handle_vblank(dev, 0); |
353 | ||
f072d2e7 | 354 | if (de_iir & DE_PIPEB_VBLANK) |
c062df61 LP |
355 | drm_handle_vblank(dev, 1); |
356 | ||
c7c85101 ZN |
357 | /* check event from PCH */ |
358 | if ((de_iir & DE_PCH_EVENT) && | |
359 | (pch_iir & SDE_HOTPLUG_MASK)) { | |
360 | queue_work(dev_priv->wq, &dev_priv->hotplug_work); | |
036a4a7d ZW |
361 | } |
362 | ||
f97108d1 | 363 | if (de_iir & DE_PCU_EVENT) { |
7648fa99 | 364 | I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); |
f97108d1 JB |
365 | i915_handle_rps_change(dev); |
366 | } | |
367 | ||
c7c85101 ZN |
368 | /* should clear PCH hotplug event before clear CPU irq */ |
369 | I915_WRITE(SDEIIR, pch_iir); | |
370 | I915_WRITE(GTIIR, gt_iir); | |
371 | I915_WRITE(DEIIR, de_iir); | |
372 | ||
373 | done: | |
2d109a84 ZN |
374 | I915_WRITE(DEIER, de_ier); |
375 | (void)I915_READ(DEIER); | |
376 | ||
036a4a7d ZW |
377 | return ret; |
378 | } | |
379 | ||
8a905236 JB |
380 | /** |
381 | * i915_error_work_func - do process context error handling work | |
382 | * @work: work struct | |
383 | * | |
384 | * Fire an error uevent so userspace can see that a hang or error | |
385 | * was detected. | |
386 | */ | |
387 | static void i915_error_work_func(struct work_struct *work) | |
388 | { | |
389 | drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, | |
390 | error_work); | |
391 | struct drm_device *dev = dev_priv->dev; | |
f316a42c BG |
392 | char *error_event[] = { "ERROR=1", NULL }; |
393 | char *reset_event[] = { "RESET=1", NULL }; | |
394 | char *reset_done_event[] = { "ERROR=0", NULL }; | |
8a905236 | 395 | |
44d98a61 | 396 | DRM_DEBUG_DRIVER("generating error event\n"); |
f316a42c BG |
397 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event); |
398 | ||
ba1234d1 | 399 | if (atomic_read(&dev_priv->mm.wedged)) { |
f803aa55 CW |
400 | DRM_DEBUG_DRIVER("resetting chip\n"); |
401 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event); | |
402 | if (!i915_reset(dev, GRDOM_RENDER)) { | |
403 | atomic_set(&dev_priv->mm.wedged, 0); | |
404 | kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event); | |
f316a42c BG |
405 | } |
406 | } | |
8a905236 JB |
407 | } |
408 | ||
3bd3c932 | 409 | #ifdef CONFIG_DEBUG_FS |
9df30794 CW |
410 | static struct drm_i915_error_object * |
411 | i915_error_object_create(struct drm_device *dev, | |
412 | struct drm_gem_object *src) | |
413 | { | |
e56660dd | 414 | drm_i915_private_t *dev_priv = dev->dev_private; |
9df30794 CW |
415 | struct drm_i915_error_object *dst; |
416 | struct drm_i915_gem_object *src_priv; | |
417 | int page, page_count; | |
e56660dd | 418 | u32 reloc_offset; |
9df30794 CW |
419 | |
420 | if (src == NULL) | |
421 | return NULL; | |
422 | ||
23010e43 | 423 | src_priv = to_intel_bo(src); |
9df30794 CW |
424 | if (src_priv->pages == NULL) |
425 | return NULL; | |
426 | ||
427 | page_count = src->size / PAGE_SIZE; | |
428 | ||
429 | dst = kmalloc(sizeof(*dst) + page_count * sizeof (u32 *), GFP_ATOMIC); | |
430 | if (dst == NULL) | |
431 | return NULL; | |
432 | ||
e56660dd | 433 | reloc_offset = src_priv->gtt_offset; |
9df30794 | 434 | for (page = 0; page < page_count; page++) { |
788885ae | 435 | unsigned long flags; |
e56660dd CW |
436 | void __iomem *s; |
437 | void *d; | |
788885ae | 438 | |
e56660dd | 439 | d = kmalloc(PAGE_SIZE, GFP_ATOMIC); |
9df30794 CW |
440 | if (d == NULL) |
441 | goto unwind; | |
e56660dd | 442 | |
788885ae | 443 | local_irq_save(flags); |
e56660dd CW |
444 | s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
445 | reloc_offset, | |
446 | KM_IRQ0); | |
447 | memcpy_fromio(d, s, PAGE_SIZE); | |
448 | io_mapping_unmap_atomic(s, KM_IRQ0); | |
788885ae | 449 | local_irq_restore(flags); |
e56660dd | 450 | |
9df30794 | 451 | dst->pages[page] = d; |
e56660dd CW |
452 | |
453 | reloc_offset += PAGE_SIZE; | |
9df30794 CW |
454 | } |
455 | dst->page_count = page_count; | |
456 | dst->gtt_offset = src_priv->gtt_offset; | |
457 | ||
458 | return dst; | |
459 | ||
460 | unwind: | |
461 | while (page--) | |
462 | kfree(dst->pages[page]); | |
463 | kfree(dst); | |
464 | return NULL; | |
465 | } | |
466 | ||
467 | static void | |
468 | i915_error_object_free(struct drm_i915_error_object *obj) | |
469 | { | |
470 | int page; | |
471 | ||
472 | if (obj == NULL) | |
473 | return; | |
474 | ||
475 | for (page = 0; page < obj->page_count; page++) | |
476 | kfree(obj->pages[page]); | |
477 | ||
478 | kfree(obj); | |
479 | } | |
480 | ||
481 | static void | |
482 | i915_error_state_free(struct drm_device *dev, | |
483 | struct drm_i915_error_state *error) | |
484 | { | |
485 | i915_error_object_free(error->batchbuffer[0]); | |
486 | i915_error_object_free(error->batchbuffer[1]); | |
487 | i915_error_object_free(error->ringbuffer); | |
488 | kfree(error->active_bo); | |
6ef3d427 | 489 | kfree(error->overlay); |
9df30794 CW |
490 | kfree(error); |
491 | } | |
492 | ||
493 | static u32 | |
494 | i915_get_bbaddr(struct drm_device *dev, u32 *ring) | |
495 | { | |
496 | u32 cmd; | |
497 | ||
498 | if (IS_I830(dev) || IS_845G(dev)) | |
499 | cmd = MI_BATCH_BUFFER; | |
a6c45cf0 | 500 | else if (INTEL_INFO(dev)->gen >= 4) |
9df30794 CW |
501 | cmd = (MI_BATCH_BUFFER_START | (2 << 6) | |
502 | MI_BATCH_NON_SECURE_I965); | |
503 | else | |
504 | cmd = (MI_BATCH_BUFFER_START | (2 << 6)); | |
505 | ||
506 | return ring[0] == cmd ? ring[1] : 0; | |
507 | } | |
508 | ||
509 | static u32 | |
510 | i915_ringbuffer_last_batch(struct drm_device *dev) | |
511 | { | |
512 | struct drm_i915_private *dev_priv = dev->dev_private; | |
513 | u32 head, bbaddr; | |
514 | u32 *ring; | |
515 | ||
516 | /* Locate the current position in the ringbuffer and walk back | |
517 | * to find the most recently dispatched batch buffer. | |
518 | */ | |
519 | bbaddr = 0; | |
520 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
d3301d86 | 521 | ring = (u32 *)(dev_priv->render_ring.virtual_start + head); |
9df30794 | 522 | |
d3301d86 | 523 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
9df30794 CW |
524 | bbaddr = i915_get_bbaddr(dev, ring); |
525 | if (bbaddr) | |
526 | break; | |
527 | } | |
528 | ||
529 | if (bbaddr == 0) { | |
8187a2b7 ZN |
530 | ring = (u32 *)(dev_priv->render_ring.virtual_start |
531 | + dev_priv->render_ring.size); | |
d3301d86 | 532 | while (--ring >= (u32 *)dev_priv->render_ring.virtual_start) { |
9df30794 CW |
533 | bbaddr = i915_get_bbaddr(dev, ring); |
534 | if (bbaddr) | |
535 | break; | |
536 | } | |
537 | } | |
538 | ||
539 | return bbaddr; | |
540 | } | |
541 | ||
8a905236 JB |
542 | /** |
543 | * i915_capture_error_state - capture an error record for later analysis | |
544 | * @dev: drm device | |
545 | * | |
546 | * Should be called when an error is detected (either a hang or an error | |
547 | * interrupt) to capture error state from the time of the error. Fills | |
548 | * out a structure which becomes available in debugfs for user level tools | |
549 | * to pick up. | |
550 | */ | |
63eeaf38 JB |
551 | static void i915_capture_error_state(struct drm_device *dev) |
552 | { | |
553 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9df30794 | 554 | struct drm_i915_gem_object *obj_priv; |
63eeaf38 | 555 | struct drm_i915_error_state *error; |
9df30794 | 556 | struct drm_gem_object *batchbuffer[2]; |
63eeaf38 | 557 | unsigned long flags; |
9df30794 CW |
558 | u32 bbaddr; |
559 | int count; | |
63eeaf38 JB |
560 | |
561 | spin_lock_irqsave(&dev_priv->error_lock, flags); | |
9df30794 CW |
562 | error = dev_priv->first_error; |
563 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); | |
564 | if (error) | |
565 | return; | |
63eeaf38 JB |
566 | |
567 | error = kmalloc(sizeof(*error), GFP_ATOMIC); | |
568 | if (!error) { | |
9df30794 CW |
569 | DRM_DEBUG_DRIVER("out of memory, not capturing error state\n"); |
570 | return; | |
63eeaf38 JB |
571 | } |
572 | ||
852835f3 | 573 | error->seqno = i915_get_gem_seqno(dev, &dev_priv->render_ring); |
63eeaf38 JB |
574 | error->eir = I915_READ(EIR); |
575 | error->pgtbl_er = I915_READ(PGTBL_ER); | |
576 | error->pipeastat = I915_READ(PIPEASTAT); | |
577 | error->pipebstat = I915_READ(PIPEBSTAT); | |
578 | error->instpm = I915_READ(INSTPM); | |
a6c45cf0 | 579 | if (INTEL_INFO(dev)->gen < 4) { |
63eeaf38 JB |
580 | error->ipeir = I915_READ(IPEIR); |
581 | error->ipehr = I915_READ(IPEHR); | |
582 | error->instdone = I915_READ(INSTDONE); | |
583 | error->acthd = I915_READ(ACTHD); | |
9df30794 | 584 | error->bbaddr = 0; |
63eeaf38 JB |
585 | } else { |
586 | error->ipeir = I915_READ(IPEIR_I965); | |
587 | error->ipehr = I915_READ(IPEHR_I965); | |
588 | error->instdone = I915_READ(INSTDONE_I965); | |
589 | error->instps = I915_READ(INSTPS); | |
590 | error->instdone1 = I915_READ(INSTDONE1); | |
591 | error->acthd = I915_READ(ACTHD_I965); | |
9df30794 | 592 | error->bbaddr = I915_READ64(BB_ADDR); |
63eeaf38 JB |
593 | } |
594 | ||
9df30794 | 595 | bbaddr = i915_ringbuffer_last_batch(dev); |
8a905236 | 596 | |
9df30794 CW |
597 | /* Grab the current batchbuffer, most likely to have crashed. */ |
598 | batchbuffer[0] = NULL; | |
599 | batchbuffer[1] = NULL; | |
600 | count = 0; | |
852835f3 ZN |
601 | list_for_each_entry(obj_priv, |
602 | &dev_priv->render_ring.active_list, list) { | |
603 | ||
a8089e84 | 604 | struct drm_gem_object *obj = &obj_priv->base; |
63eeaf38 | 605 | |
9df30794 CW |
606 | if (batchbuffer[0] == NULL && |
607 | bbaddr >= obj_priv->gtt_offset && | |
608 | bbaddr < obj_priv->gtt_offset + obj->size) | |
609 | batchbuffer[0] = obj; | |
610 | ||
611 | if (batchbuffer[1] == NULL && | |
612 | error->acthd >= obj_priv->gtt_offset && | |
e56660dd | 613 | error->acthd < obj_priv->gtt_offset + obj->size) |
9df30794 CW |
614 | batchbuffer[1] = obj; |
615 | ||
616 | count++; | |
617 | } | |
e56660dd CW |
618 | /* Scan the other lists for completeness for those bizarre errors. */ |
619 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
620 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { | |
621 | struct drm_gem_object *obj = &obj_priv->base; | |
622 | ||
623 | if (batchbuffer[0] == NULL && | |
624 | bbaddr >= obj_priv->gtt_offset && | |
625 | bbaddr < obj_priv->gtt_offset + obj->size) | |
626 | batchbuffer[0] = obj; | |
627 | ||
628 | if (batchbuffer[1] == NULL && | |
629 | error->acthd >= obj_priv->gtt_offset && | |
630 | error->acthd < obj_priv->gtt_offset + obj->size) | |
631 | batchbuffer[1] = obj; | |
632 | ||
633 | if (batchbuffer[0] && batchbuffer[1]) | |
634 | break; | |
635 | } | |
636 | } | |
637 | if (batchbuffer[0] == NULL || batchbuffer[1] == NULL) { | |
638 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { | |
639 | struct drm_gem_object *obj = &obj_priv->base; | |
640 | ||
641 | if (batchbuffer[0] == NULL && | |
642 | bbaddr >= obj_priv->gtt_offset && | |
643 | bbaddr < obj_priv->gtt_offset + obj->size) | |
644 | batchbuffer[0] = obj; | |
645 | ||
646 | if (batchbuffer[1] == NULL && | |
647 | error->acthd >= obj_priv->gtt_offset && | |
648 | error->acthd < obj_priv->gtt_offset + obj->size) | |
649 | batchbuffer[1] = obj; | |
650 | ||
651 | if (batchbuffer[0] && batchbuffer[1]) | |
652 | break; | |
653 | } | |
654 | } | |
9df30794 CW |
655 | |
656 | /* We need to copy these to an anonymous buffer as the simplest | |
657 | * method to avoid being overwritten by userpace. | |
658 | */ | |
659 | error->batchbuffer[0] = i915_error_object_create(dev, batchbuffer[0]); | |
e56660dd CW |
660 | if (batchbuffer[1] != batchbuffer[0]) |
661 | error->batchbuffer[1] = i915_error_object_create(dev, batchbuffer[1]); | |
662 | else | |
663 | error->batchbuffer[1] = NULL; | |
9df30794 CW |
664 | |
665 | /* Record the ringbuffer */ | |
8187a2b7 ZN |
666 | error->ringbuffer = i915_error_object_create(dev, |
667 | dev_priv->render_ring.gem_object); | |
9df30794 CW |
668 | |
669 | /* Record buffers on the active list. */ | |
670 | error->active_bo = NULL; | |
671 | error->active_bo_count = 0; | |
672 | ||
673 | if (count) | |
674 | error->active_bo = kmalloc(sizeof(*error->active_bo)*count, | |
675 | GFP_ATOMIC); | |
676 | ||
677 | if (error->active_bo) { | |
678 | int i = 0; | |
852835f3 ZN |
679 | list_for_each_entry(obj_priv, |
680 | &dev_priv->render_ring.active_list, list) { | |
a8089e84 | 681 | struct drm_gem_object *obj = &obj_priv->base; |
9df30794 CW |
682 | |
683 | error->active_bo[i].size = obj->size; | |
684 | error->active_bo[i].name = obj->name; | |
685 | error->active_bo[i].seqno = obj_priv->last_rendering_seqno; | |
686 | error->active_bo[i].gtt_offset = obj_priv->gtt_offset; | |
687 | error->active_bo[i].read_domains = obj->read_domains; | |
688 | error->active_bo[i].write_domain = obj->write_domain; | |
689 | error->active_bo[i].fence_reg = obj_priv->fence_reg; | |
690 | error->active_bo[i].pinned = 0; | |
691 | if (obj_priv->pin_count > 0) | |
692 | error->active_bo[i].pinned = 1; | |
693 | if (obj_priv->user_pin_count > 0) | |
694 | error->active_bo[i].pinned = -1; | |
695 | error->active_bo[i].tiling = obj_priv->tiling_mode; | |
696 | error->active_bo[i].dirty = obj_priv->dirty; | |
697 | error->active_bo[i].purgeable = obj_priv->madv != I915_MADV_WILLNEED; | |
698 | ||
699 | if (++i == count) | |
700 | break; | |
701 | } | |
702 | error->active_bo_count = i; | |
703 | } | |
704 | ||
705 | do_gettimeofday(&error->time); | |
706 | ||
6ef3d427 CW |
707 | error->overlay = intel_overlay_capture_error_state(dev); |
708 | ||
9df30794 CW |
709 | spin_lock_irqsave(&dev_priv->error_lock, flags); |
710 | if (dev_priv->first_error == NULL) { | |
711 | dev_priv->first_error = error; | |
712 | error = NULL; | |
713 | } | |
63eeaf38 | 714 | spin_unlock_irqrestore(&dev_priv->error_lock, flags); |
9df30794 CW |
715 | |
716 | if (error) | |
717 | i915_error_state_free(dev, error); | |
718 | } | |
719 | ||
720 | void i915_destroy_error_state(struct drm_device *dev) | |
721 | { | |
722 | struct drm_i915_private *dev_priv = dev->dev_private; | |
723 | struct drm_i915_error_state *error; | |
724 | ||
725 | spin_lock(&dev_priv->error_lock); | |
726 | error = dev_priv->first_error; | |
727 | dev_priv->first_error = NULL; | |
728 | spin_unlock(&dev_priv->error_lock); | |
729 | ||
730 | if (error) | |
731 | i915_error_state_free(dev, error); | |
63eeaf38 | 732 | } |
3bd3c932 CW |
733 | #else |
734 | #define i915_capture_error_state(x) | |
735 | #endif | |
63eeaf38 | 736 | |
35aed2e6 | 737 | static void i915_report_and_clear_eir(struct drm_device *dev) |
8a905236 JB |
738 | { |
739 | struct drm_i915_private *dev_priv = dev->dev_private; | |
740 | u32 eir = I915_READ(EIR); | |
8a905236 | 741 | |
35aed2e6 CW |
742 | if (!eir) |
743 | return; | |
8a905236 JB |
744 | |
745 | printk(KERN_ERR "render error detected, EIR: 0x%08x\n", | |
746 | eir); | |
747 | ||
748 | if (IS_G4X(dev)) { | |
749 | if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) { | |
750 | u32 ipeir = I915_READ(IPEIR_I965); | |
751 | ||
752 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
753 | I915_READ(IPEIR_I965)); | |
754 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
755 | I915_READ(IPEHR_I965)); | |
756 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
757 | I915_READ(INSTDONE_I965)); | |
758 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
759 | I915_READ(INSTPS)); | |
760 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
761 | I915_READ(INSTDONE1)); | |
762 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
763 | I915_READ(ACTHD_I965)); | |
764 | I915_WRITE(IPEIR_I965, ipeir); | |
765 | (void)I915_READ(IPEIR_I965); | |
766 | } | |
767 | if (eir & GM45_ERROR_PAGE_TABLE) { | |
768 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
769 | printk(KERN_ERR "page table error\n"); | |
770 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
771 | pgtbl_err); | |
772 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
773 | (void)I915_READ(PGTBL_ER); | |
774 | } | |
775 | } | |
776 | ||
a6c45cf0 | 777 | if (!IS_GEN2(dev)) { |
8a905236 JB |
778 | if (eir & I915_ERROR_PAGE_TABLE) { |
779 | u32 pgtbl_err = I915_READ(PGTBL_ER); | |
780 | printk(KERN_ERR "page table error\n"); | |
781 | printk(KERN_ERR " PGTBL_ER: 0x%08x\n", | |
782 | pgtbl_err); | |
783 | I915_WRITE(PGTBL_ER, pgtbl_err); | |
784 | (void)I915_READ(PGTBL_ER); | |
785 | } | |
786 | } | |
787 | ||
788 | if (eir & I915_ERROR_MEMORY_REFRESH) { | |
35aed2e6 CW |
789 | u32 pipea_stats = I915_READ(PIPEASTAT); |
790 | u32 pipeb_stats = I915_READ(PIPEBSTAT); | |
791 | ||
8a905236 JB |
792 | printk(KERN_ERR "memory refresh error\n"); |
793 | printk(KERN_ERR "PIPEASTAT: 0x%08x\n", | |
794 | pipea_stats); | |
795 | printk(KERN_ERR "PIPEBSTAT: 0x%08x\n", | |
796 | pipeb_stats); | |
797 | /* pipestat has already been acked */ | |
798 | } | |
799 | if (eir & I915_ERROR_INSTRUCTION) { | |
800 | printk(KERN_ERR "instruction error\n"); | |
801 | printk(KERN_ERR " INSTPM: 0x%08x\n", | |
802 | I915_READ(INSTPM)); | |
a6c45cf0 | 803 | if (INTEL_INFO(dev)->gen < 4) { |
8a905236 JB |
804 | u32 ipeir = I915_READ(IPEIR); |
805 | ||
806 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
807 | I915_READ(IPEIR)); | |
808 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
809 | I915_READ(IPEHR)); | |
810 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
811 | I915_READ(INSTDONE)); | |
812 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
813 | I915_READ(ACTHD)); | |
814 | I915_WRITE(IPEIR, ipeir); | |
815 | (void)I915_READ(IPEIR); | |
816 | } else { | |
817 | u32 ipeir = I915_READ(IPEIR_I965); | |
818 | ||
819 | printk(KERN_ERR " IPEIR: 0x%08x\n", | |
820 | I915_READ(IPEIR_I965)); | |
821 | printk(KERN_ERR " IPEHR: 0x%08x\n", | |
822 | I915_READ(IPEHR_I965)); | |
823 | printk(KERN_ERR " INSTDONE: 0x%08x\n", | |
824 | I915_READ(INSTDONE_I965)); | |
825 | printk(KERN_ERR " INSTPS: 0x%08x\n", | |
826 | I915_READ(INSTPS)); | |
827 | printk(KERN_ERR " INSTDONE1: 0x%08x\n", | |
828 | I915_READ(INSTDONE1)); | |
829 | printk(KERN_ERR " ACTHD: 0x%08x\n", | |
830 | I915_READ(ACTHD_I965)); | |
831 | I915_WRITE(IPEIR_I965, ipeir); | |
832 | (void)I915_READ(IPEIR_I965); | |
833 | } | |
834 | } | |
835 | ||
836 | I915_WRITE(EIR, eir); | |
837 | (void)I915_READ(EIR); | |
838 | eir = I915_READ(EIR); | |
839 | if (eir) { | |
840 | /* | |
841 | * some errors might have become stuck, | |
842 | * mask them. | |
843 | */ | |
844 | DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir); | |
845 | I915_WRITE(EMR, I915_READ(EMR) | eir); | |
846 | I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); | |
847 | } | |
35aed2e6 CW |
848 | } |
849 | ||
850 | /** | |
851 | * i915_handle_error - handle an error interrupt | |
852 | * @dev: drm device | |
853 | * | |
854 | * Do some basic checking of regsiter state at error interrupt time and | |
855 | * dump it to the syslog. Also call i915_capture_error_state() to make | |
856 | * sure we get a record and make it available in debugfs. Fire a uevent | |
857 | * so userspace knows something bad happened (should trigger collection | |
858 | * of a ring dump etc.). | |
859 | */ | |
860 | static void i915_handle_error(struct drm_device *dev, bool wedged) | |
861 | { | |
862 | struct drm_i915_private *dev_priv = dev->dev_private; | |
863 | ||
864 | i915_capture_error_state(dev); | |
865 | i915_report_and_clear_eir(dev); | |
8a905236 | 866 | |
ba1234d1 BG |
867 | if (wedged) { |
868 | atomic_set(&dev_priv->mm.wedged, 1); | |
869 | ||
11ed50ec BG |
870 | /* |
871 | * Wakeup waiting processes so they don't hang | |
872 | */ | |
852835f3 | 873 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); |
11ed50ec BG |
874 | } |
875 | ||
9c9fe1f8 | 876 | queue_work(dev_priv->wq, &dev_priv->error_work); |
8a905236 JB |
877 | } |
878 | ||
4e5359cd SF |
879 | static void i915_pageflip_stall_check(struct drm_device *dev, int pipe) |
880 | { | |
881 | drm_i915_private_t *dev_priv = dev->dev_private; | |
882 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
883 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
884 | struct drm_i915_gem_object *obj_priv; | |
885 | struct intel_unpin_work *work; | |
886 | unsigned long flags; | |
887 | bool stall_detected; | |
888 | ||
889 | /* Ignore early vblank irqs */ | |
890 | if (intel_crtc == NULL) | |
891 | return; | |
892 | ||
893 | spin_lock_irqsave(&dev->event_lock, flags); | |
894 | work = intel_crtc->unpin_work; | |
895 | ||
896 | if (work == NULL || work->pending || !work->enable_stall_check) { | |
897 | /* Either the pending flip IRQ arrived, or we're too early. Don't check */ | |
898 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
899 | return; | |
900 | } | |
901 | ||
902 | /* Potential stall - if we see that the flip has happened, assume a missed interrupt */ | |
903 | obj_priv = to_intel_bo(work->pending_flip_obj); | |
a6c45cf0 | 904 | if (INTEL_INFO(dev)->gen >= 4) { |
4e5359cd SF |
905 | int dspsurf = intel_crtc->plane == 0 ? DSPASURF : DSPBSURF; |
906 | stall_detected = I915_READ(dspsurf) == obj_priv->gtt_offset; | |
907 | } else { | |
908 | int dspaddr = intel_crtc->plane == 0 ? DSPAADDR : DSPBADDR; | |
909 | stall_detected = I915_READ(dspaddr) == (obj_priv->gtt_offset + | |
910 | crtc->y * crtc->fb->pitch + | |
911 | crtc->x * crtc->fb->bits_per_pixel/8); | |
912 | } | |
913 | ||
914 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
915 | ||
916 | if (stall_detected) { | |
917 | DRM_DEBUG_DRIVER("Pageflip stall detected\n"); | |
918 | intel_prepare_page_flip(dev, intel_crtc->plane); | |
919 | } | |
920 | } | |
921 | ||
1da177e4 LT |
922 | irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS) |
923 | { | |
84b1fd10 | 924 | struct drm_device *dev = (struct drm_device *) arg; |
1da177e4 | 925 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; |
7c1c2871 | 926 | struct drm_i915_master_private *master_priv; |
cdfbc41f EA |
927 | u32 iir, new_iir; |
928 | u32 pipea_stats, pipeb_stats; | |
05eff845 | 929 | u32 vblank_status; |
0a3e67a4 | 930 | int vblank = 0; |
7c463586 | 931 | unsigned long irqflags; |
05eff845 KP |
932 | int irq_received; |
933 | int ret = IRQ_NONE; | |
852835f3 | 934 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
6e5fca53 | 935 | |
630681d9 EA |
936 | atomic_inc(&dev_priv->irq_received); |
937 | ||
bad720ff | 938 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 939 | return ironlake_irq_handler(dev); |
036a4a7d | 940 | |
ed4cb414 | 941 | iir = I915_READ(IIR); |
a6b54f3f | 942 | |
a6c45cf0 | 943 | if (INTEL_INFO(dev)->gen >= 4) |
d874bcff | 944 | vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS; |
e25e6601 | 945 | else |
d874bcff | 946 | vblank_status = PIPE_VBLANK_INTERRUPT_STATUS; |
af6061af | 947 | |
05eff845 KP |
948 | for (;;) { |
949 | irq_received = iir != 0; | |
950 | ||
951 | /* Can't rely on pipestat interrupt bit in iir as it might | |
952 | * have been cleared after the pipestat interrupt was received. | |
953 | * It doesn't set the bit in iir again, but it still produces | |
954 | * interrupts (for non-MSI). | |
955 | */ | |
956 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); | |
957 | pipea_stats = I915_READ(PIPEASTAT); | |
958 | pipeb_stats = I915_READ(PIPEBSTAT); | |
79e53945 | 959 | |
8a905236 | 960 | if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) |
ba1234d1 | 961 | i915_handle_error(dev, false); |
8a905236 | 962 | |
cdfbc41f EA |
963 | /* |
964 | * Clear the PIPE(A|B)STAT regs before the IIR | |
965 | */ | |
05eff845 | 966 | if (pipea_stats & 0x8000ffff) { |
7662c8bd | 967 | if (pipea_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 968 | DRM_DEBUG_DRIVER("pipe a underrun\n"); |
cdfbc41f | 969 | I915_WRITE(PIPEASTAT, pipea_stats); |
05eff845 | 970 | irq_received = 1; |
cdfbc41f | 971 | } |
1da177e4 | 972 | |
05eff845 | 973 | if (pipeb_stats & 0x8000ffff) { |
7662c8bd | 974 | if (pipeb_stats & PIPE_FIFO_UNDERRUN_STATUS) |
44d98a61 | 975 | DRM_DEBUG_DRIVER("pipe b underrun\n"); |
cdfbc41f | 976 | I915_WRITE(PIPEBSTAT, pipeb_stats); |
05eff845 | 977 | irq_received = 1; |
cdfbc41f | 978 | } |
05eff845 KP |
979 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
980 | ||
981 | if (!irq_received) | |
982 | break; | |
983 | ||
984 | ret = IRQ_HANDLED; | |
8ee1c3db | 985 | |
5ca58282 JB |
986 | /* Consume port. Then clear IIR or we'll miss events */ |
987 | if ((I915_HAS_HOTPLUG(dev)) && | |
988 | (iir & I915_DISPLAY_PORT_INTERRUPT)) { | |
989 | u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); | |
990 | ||
44d98a61 | 991 | DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n", |
5ca58282 JB |
992 | hotplug_status); |
993 | if (hotplug_status & dev_priv->hotplug_supported_mask) | |
9c9fe1f8 EA |
994 | queue_work(dev_priv->wq, |
995 | &dev_priv->hotplug_work); | |
5ca58282 JB |
996 | |
997 | I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); | |
998 | I915_READ(PORT_HOTPLUG_STAT); | |
999 | } | |
1000 | ||
cdfbc41f EA |
1001 | I915_WRITE(IIR, iir); |
1002 | new_iir = I915_READ(IIR); /* Flush posted writes */ | |
7c463586 | 1003 | |
7c1c2871 DA |
1004 | if (dev->primary->master) { |
1005 | master_priv = dev->primary->master->driver_priv; | |
1006 | if (master_priv->sarea_priv) | |
1007 | master_priv->sarea_priv->last_dispatch = | |
1008 | READ_BREADCRUMB(dev_priv); | |
1009 | } | |
0a3e67a4 | 1010 | |
cdfbc41f | 1011 | if (iir & I915_USER_INTERRUPT) { |
852835f3 ZN |
1012 | u32 seqno = |
1013 | render_ring->get_gem_seqno(dev, render_ring); | |
1014 | render_ring->irq_gem_seqno = seqno; | |
1c5d22f7 | 1015 | trace_i915_gem_request_complete(dev, seqno); |
852835f3 | 1016 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); |
f65d9421 | 1017 | dev_priv->hangcheck_count = 0; |
b3b079db CW |
1018 | mod_timer(&dev_priv->hangcheck_timer, |
1019 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
cdfbc41f | 1020 | } |
673a394b | 1021 | |
d1b851fc ZN |
1022 | if (HAS_BSD(dev) && (iir & I915_BSD_USER_INTERRUPT)) |
1023 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); | |
1024 | ||
1afe3e9d | 1025 | if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) { |
6b95a207 | 1026 | intel_prepare_page_flip(dev, 0); |
1afe3e9d JB |
1027 | if (dev_priv->flip_pending_is_done) |
1028 | intel_finish_page_flip_plane(dev, 0); | |
1029 | } | |
6b95a207 | 1030 | |
1afe3e9d | 1031 | if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) { |
70565d00 | 1032 | intel_prepare_page_flip(dev, 1); |
1afe3e9d JB |
1033 | if (dev_priv->flip_pending_is_done) |
1034 | intel_finish_page_flip_plane(dev, 1); | |
1afe3e9d | 1035 | } |
6b95a207 | 1036 | |
05eff845 | 1037 | if (pipea_stats & vblank_status) { |
cdfbc41f EA |
1038 | vblank++; |
1039 | drm_handle_vblank(dev, 0); | |
4e5359cd SF |
1040 | if (!dev_priv->flip_pending_is_done) { |
1041 | i915_pageflip_stall_check(dev, 0); | |
1afe3e9d | 1042 | intel_finish_page_flip(dev, 0); |
4e5359cd | 1043 | } |
cdfbc41f | 1044 | } |
7c463586 | 1045 | |
05eff845 | 1046 | if (pipeb_stats & vblank_status) { |
cdfbc41f EA |
1047 | vblank++; |
1048 | drm_handle_vblank(dev, 1); | |
4e5359cd SF |
1049 | if (!dev_priv->flip_pending_is_done) { |
1050 | i915_pageflip_stall_check(dev, 1); | |
1afe3e9d | 1051 | intel_finish_page_flip(dev, 1); |
4e5359cd | 1052 | } |
cdfbc41f | 1053 | } |
7c463586 | 1054 | |
d874bcff JB |
1055 | if ((pipea_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || |
1056 | (pipeb_stats & PIPE_LEGACY_BLC_EVENT_STATUS) || | |
cdfbc41f | 1057 | (iir & I915_ASLE_INTERRUPT)) |
3b617967 | 1058 | intel_opregion_asle_intr(dev); |
cdfbc41f EA |
1059 | |
1060 | /* With MSI, interrupts are only generated when iir | |
1061 | * transitions from zero to nonzero. If another bit got | |
1062 | * set while we were handling the existing iir bits, then | |
1063 | * we would never get another interrupt. | |
1064 | * | |
1065 | * This is fine on non-MSI as well, as if we hit this path | |
1066 | * we avoid exiting the interrupt handler only to generate | |
1067 | * another one. | |
1068 | * | |
1069 | * Note that for MSI this could cause a stray interrupt report | |
1070 | * if an interrupt landed in the time between writing IIR and | |
1071 | * the posting read. This should be rare enough to never | |
1072 | * trigger the 99% of 100,000 interrupts test for disabling | |
1073 | * stray interrupts. | |
1074 | */ | |
1075 | iir = new_iir; | |
05eff845 | 1076 | } |
0a3e67a4 | 1077 | |
05eff845 | 1078 | return ret; |
1da177e4 LT |
1079 | } |
1080 | ||
af6061af | 1081 | static int i915_emit_irq(struct drm_device * dev) |
1da177e4 LT |
1082 | { |
1083 | drm_i915_private_t *dev_priv = dev->dev_private; | |
7c1c2871 | 1084 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 LT |
1085 | |
1086 | i915_kernel_lost_context(dev); | |
1087 | ||
44d98a61 | 1088 | DRM_DEBUG_DRIVER("\n"); |
1da177e4 | 1089 | |
c99b058f | 1090 | dev_priv->counter++; |
c29b669c | 1091 | if (dev_priv->counter > 0x7FFFFFFFUL) |
c99b058f | 1092 | dev_priv->counter = 1; |
7c1c2871 DA |
1093 | if (master_priv->sarea_priv) |
1094 | master_priv->sarea_priv->last_enqueue = dev_priv->counter; | |
c29b669c | 1095 | |
0baf823a | 1096 | BEGIN_LP_RING(4); |
585fb111 | 1097 | OUT_RING(MI_STORE_DWORD_INDEX); |
0baf823a | 1098 | OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
c29b669c | 1099 | OUT_RING(dev_priv->counter); |
585fb111 | 1100 | OUT_RING(MI_USER_INTERRUPT); |
1da177e4 | 1101 | ADVANCE_LP_RING(); |
bc5f4523 | 1102 | |
c29b669c | 1103 | return dev_priv->counter; |
1da177e4 LT |
1104 | } |
1105 | ||
9d34e5db CW |
1106 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno) |
1107 | { | |
1108 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
8187a2b7 | 1109 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
9d34e5db CW |
1110 | |
1111 | if (dev_priv->trace_irq_seqno == 0) | |
8187a2b7 | 1112 | render_ring->user_irq_get(dev, render_ring); |
9d34e5db CW |
1113 | |
1114 | dev_priv->trace_irq_seqno = seqno; | |
1115 | } | |
1116 | ||
84b1fd10 | 1117 | static int i915_wait_irq(struct drm_device * dev, int irq_nr) |
1da177e4 LT |
1118 | { |
1119 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
7c1c2871 | 1120 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
1da177e4 | 1121 | int ret = 0; |
8187a2b7 | 1122 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
1da177e4 | 1123 | |
44d98a61 | 1124 | DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr, |
1da177e4 LT |
1125 | READ_BREADCRUMB(dev_priv)); |
1126 | ||
ed4cb414 | 1127 | if (READ_BREADCRUMB(dev_priv) >= irq_nr) { |
7c1c2871 DA |
1128 | if (master_priv->sarea_priv) |
1129 | master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv); | |
1da177e4 | 1130 | return 0; |
ed4cb414 | 1131 | } |
1da177e4 | 1132 | |
7c1c2871 DA |
1133 | if (master_priv->sarea_priv) |
1134 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; | |
1da177e4 | 1135 | |
8187a2b7 | 1136 | render_ring->user_irq_get(dev, render_ring); |
852835f3 | 1137 | DRM_WAIT_ON(ret, dev_priv->render_ring.irq_queue, 3 * DRM_HZ, |
1da177e4 | 1138 | READ_BREADCRUMB(dev_priv) >= irq_nr); |
8187a2b7 | 1139 | render_ring->user_irq_put(dev, render_ring); |
1da177e4 | 1140 | |
20caafa6 | 1141 | if (ret == -EBUSY) { |
3e684eae | 1142 | DRM_ERROR("EBUSY -- rec: %d emitted: %d\n", |
1da177e4 LT |
1143 | READ_BREADCRUMB(dev_priv), (int)dev_priv->counter); |
1144 | } | |
1145 | ||
af6061af DA |
1146 | return ret; |
1147 | } | |
1148 | ||
1da177e4 LT |
1149 | /* Needs the lock as it touches the ring. |
1150 | */ | |
c153f45f EA |
1151 | int i915_irq_emit(struct drm_device *dev, void *data, |
1152 | struct drm_file *file_priv) | |
1da177e4 | 1153 | { |
1da177e4 | 1154 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1155 | drm_i915_irq_emit_t *emit = data; |
1da177e4 LT |
1156 | int result; |
1157 | ||
d3301d86 | 1158 | if (!dev_priv || !dev_priv->render_ring.virtual_start) { |
3e684eae | 1159 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1160 | return -EINVAL; |
1da177e4 | 1161 | } |
299eb93c EA |
1162 | |
1163 | RING_LOCK_TEST_WITH_RETURN(dev, file_priv); | |
1164 | ||
546b0974 | 1165 | mutex_lock(&dev->struct_mutex); |
1da177e4 | 1166 | result = i915_emit_irq(dev); |
546b0974 | 1167 | mutex_unlock(&dev->struct_mutex); |
1da177e4 | 1168 | |
c153f45f | 1169 | if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) { |
1da177e4 | 1170 | DRM_ERROR("copy_to_user\n"); |
20caafa6 | 1171 | return -EFAULT; |
1da177e4 LT |
1172 | } |
1173 | ||
1174 | return 0; | |
1175 | } | |
1176 | ||
1177 | /* Doesn't need the hardware lock. | |
1178 | */ | |
c153f45f EA |
1179 | int i915_irq_wait(struct drm_device *dev, void *data, |
1180 | struct drm_file *file_priv) | |
1da177e4 | 1181 | { |
1da177e4 | 1182 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1183 | drm_i915_irq_wait_t *irqwait = data; |
1da177e4 LT |
1184 | |
1185 | if (!dev_priv) { | |
3e684eae | 1186 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1187 | return -EINVAL; |
1da177e4 LT |
1188 | } |
1189 | ||
c153f45f | 1190 | return i915_wait_irq(dev, irqwait->irq_seq); |
1da177e4 LT |
1191 | } |
1192 | ||
42f52ef8 KP |
1193 | /* Called from drm generic code, passed 'crtc' which |
1194 | * we use as a pipe index | |
1195 | */ | |
1196 | int i915_enable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1197 | { |
1198 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1199 | unsigned long irqflags; |
71e0ffa5 | 1200 | |
5eddb70b | 1201 | if (!i915_pipe_enabled(dev, pipe)) |
71e0ffa5 | 1202 | return -EINVAL; |
0a3e67a4 | 1203 | |
e9d21d7f | 1204 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1205 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1206 | ironlake_enable_display_irq(dev_priv, (pipe == 0) ? |
1207 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
a6c45cf0 | 1208 | else if (INTEL_INFO(dev)->gen >= 4) |
7c463586 KP |
1209 | i915_enable_pipestat(dev_priv, pipe, |
1210 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1211 | else |
7c463586 KP |
1212 | i915_enable_pipestat(dev_priv, pipe, |
1213 | PIPE_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1214 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1215 | return 0; |
1216 | } | |
1217 | ||
42f52ef8 KP |
1218 | /* Called from drm generic code, passed 'crtc' which |
1219 | * we use as a pipe index | |
1220 | */ | |
1221 | void i915_disable_vblank(struct drm_device *dev, int pipe) | |
0a3e67a4 JB |
1222 | { |
1223 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
e9d21d7f | 1224 | unsigned long irqflags; |
0a3e67a4 | 1225 | |
e9d21d7f | 1226 | spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags); |
bad720ff | 1227 | if (HAS_PCH_SPLIT(dev)) |
c062df61 LP |
1228 | ironlake_disable_display_irq(dev_priv, (pipe == 0) ? |
1229 | DE_PIPEA_VBLANK: DE_PIPEB_VBLANK); | |
1230 | else | |
1231 | i915_disable_pipestat(dev_priv, pipe, | |
1232 | PIPE_VBLANK_INTERRUPT_ENABLE | | |
1233 | PIPE_START_VBLANK_INTERRUPT_ENABLE); | |
e9d21d7f | 1234 | spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags); |
0a3e67a4 JB |
1235 | } |
1236 | ||
79e53945 JB |
1237 | void i915_enable_interrupt (struct drm_device *dev) |
1238 | { | |
1239 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e170b030 | 1240 | |
bad720ff | 1241 | if (!HAS_PCH_SPLIT(dev)) |
3b617967 | 1242 | intel_opregion_enable_asle(dev); |
79e53945 JB |
1243 | dev_priv->irq_enabled = 1; |
1244 | } | |
1245 | ||
1246 | ||
702880f2 DA |
1247 | /* Set the vblank monitor pipe |
1248 | */ | |
c153f45f EA |
1249 | int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1250 | struct drm_file *file_priv) | |
702880f2 | 1251 | { |
702880f2 | 1252 | drm_i915_private_t *dev_priv = dev->dev_private; |
702880f2 DA |
1253 | |
1254 | if (!dev_priv) { | |
3e684eae | 1255 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1256 | return -EINVAL; |
702880f2 DA |
1257 | } |
1258 | ||
5b51694a | 1259 | return 0; |
702880f2 DA |
1260 | } |
1261 | ||
c153f45f EA |
1262 | int i915_vblank_pipe_get(struct drm_device *dev, void *data, |
1263 | struct drm_file *file_priv) | |
702880f2 | 1264 | { |
702880f2 | 1265 | drm_i915_private_t *dev_priv = dev->dev_private; |
c153f45f | 1266 | drm_i915_vblank_pipe_t *pipe = data; |
702880f2 DA |
1267 | |
1268 | if (!dev_priv) { | |
3e684eae | 1269 | DRM_ERROR("called with no initialization\n"); |
20caafa6 | 1270 | return -EINVAL; |
702880f2 DA |
1271 | } |
1272 | ||
0a3e67a4 | 1273 | pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
c153f45f | 1274 | |
702880f2 DA |
1275 | return 0; |
1276 | } | |
1277 | ||
a6b54f3f MD |
1278 | /** |
1279 | * Schedule buffer swap at given vertical blank. | |
1280 | */ | |
c153f45f EA |
1281 | int i915_vblank_swap(struct drm_device *dev, void *data, |
1282 | struct drm_file *file_priv) | |
a6b54f3f | 1283 | { |
bd95e0a4 EA |
1284 | /* The delayed swap mechanism was fundamentally racy, and has been |
1285 | * removed. The model was that the client requested a delayed flip/swap | |
1286 | * from the kernel, then waited for vblank before continuing to perform | |
1287 | * rendering. The problem was that the kernel might wake the client | |
1288 | * up before it dispatched the vblank swap (since the lock has to be | |
1289 | * held while touching the ringbuffer), in which case the client would | |
1290 | * clear and start the next frame before the swap occurred, and | |
1291 | * flicker would occur in addition to likely missing the vblank. | |
1292 | * | |
1293 | * In the absence of this ioctl, userland falls back to a correct path | |
1294 | * of waiting for a vblank, then dispatching the swap on its own. | |
1295 | * Context switching to userland and back is plenty fast enough for | |
1296 | * meeting the requirements of vblank swapping. | |
0a3e67a4 | 1297 | */ |
bd95e0a4 | 1298 | return -EINVAL; |
a6b54f3f MD |
1299 | } |
1300 | ||
995b6762 | 1301 | static struct drm_i915_gem_request * |
852835f3 ZN |
1302 | i915_get_tail_request(struct drm_device *dev) |
1303 | { | |
f65d9421 | 1304 | drm_i915_private_t *dev_priv = dev->dev_private; |
852835f3 ZN |
1305 | return list_entry(dev_priv->render_ring.request_list.prev, |
1306 | struct drm_i915_gem_request, list); | |
f65d9421 BG |
1307 | } |
1308 | ||
1309 | /** | |
1310 | * This is called when the chip hasn't reported back with completed | |
1311 | * batchbuffers in a long time. The first time this is called we simply record | |
1312 | * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses | |
1313 | * again, we assume the chip is wedged and try to fix it. | |
1314 | */ | |
1315 | void i915_hangcheck_elapsed(unsigned long data) | |
1316 | { | |
1317 | struct drm_device *dev = (struct drm_device *)data; | |
1318 | drm_i915_private_t *dev_priv = dev->dev_private; | |
cbb465e7 | 1319 | uint32_t acthd, instdone, instdone1; |
b9201c14 | 1320 | |
a6c45cf0 | 1321 | if (INTEL_INFO(dev)->gen < 4) { |
f65d9421 | 1322 | acthd = I915_READ(ACTHD); |
cbb465e7 CW |
1323 | instdone = I915_READ(INSTDONE); |
1324 | instdone1 = 0; | |
1325 | } else { | |
f65d9421 | 1326 | acthd = I915_READ(ACTHD_I965); |
cbb465e7 CW |
1327 | instdone = I915_READ(INSTDONE_I965); |
1328 | instdone1 = I915_READ(INSTDONE1); | |
1329 | } | |
f65d9421 BG |
1330 | |
1331 | /* If all work is done then ACTHD clearly hasn't advanced. */ | |
852835f3 ZN |
1332 | if (list_empty(&dev_priv->render_ring.request_list) || |
1333 | i915_seqno_passed(i915_get_gem_seqno(dev, | |
1334 | &dev_priv->render_ring), | |
1335 | i915_get_tail_request(dev)->seqno)) { | |
7839d956 CW |
1336 | bool missed_wakeup = false; |
1337 | ||
f65d9421 | 1338 | dev_priv->hangcheck_count = 0; |
e78d73b1 CW |
1339 | |
1340 | /* Issue a wake-up to catch stuck h/w. */ | |
7839d956 CW |
1341 | if (dev_priv->render_ring.waiting_gem_seqno && |
1342 | waitqueue_active(&dev_priv->render_ring.irq_queue)) { | |
1343 | DRM_WAKEUP(&dev_priv->render_ring.irq_queue); | |
1344 | missed_wakeup = true; | |
1345 | } | |
1346 | ||
1347 | if (dev_priv->bsd_ring.waiting_gem_seqno && | |
1348 | waitqueue_active(&dev_priv->bsd_ring.irq_queue)) { | |
1349 | DRM_WAKEUP(&dev_priv->bsd_ring.irq_queue); | |
1350 | missed_wakeup = true; | |
e78d73b1 | 1351 | } |
7839d956 CW |
1352 | |
1353 | if (missed_wakeup) | |
1354 | DRM_ERROR("Hangcheck timer elapsed... GPU idle, missed IRQ.\n"); | |
f65d9421 BG |
1355 | return; |
1356 | } | |
1357 | ||
cbb465e7 CW |
1358 | if (dev_priv->last_acthd == acthd && |
1359 | dev_priv->last_instdone == instdone && | |
1360 | dev_priv->last_instdone1 == instdone1) { | |
1361 | if (dev_priv->hangcheck_count++ > 1) { | |
1362 | DRM_ERROR("Hangcheck timer elapsed... GPU hung\n"); | |
8c80b59b CW |
1363 | |
1364 | if (!IS_GEN2(dev)) { | |
1365 | /* Is the chip hanging on a WAIT_FOR_EVENT? | |
1366 | * If so we can simply poke the RB_WAIT bit | |
1367 | * and break the hang. This should work on | |
1368 | * all but the second generation chipsets. | |
1369 | */ | |
1370 | u32 tmp = I915_READ(PRB0_CTL); | |
1371 | if (tmp & RING_WAIT) { | |
1372 | I915_WRITE(PRB0_CTL, tmp); | |
1373 | POSTING_READ(PRB0_CTL); | |
1374 | goto out; | |
1375 | } | |
1376 | } | |
1377 | ||
cbb465e7 CW |
1378 | i915_handle_error(dev, true); |
1379 | return; | |
1380 | } | |
1381 | } else { | |
1382 | dev_priv->hangcheck_count = 0; | |
1383 | ||
1384 | dev_priv->last_acthd = acthd; | |
1385 | dev_priv->last_instdone = instdone; | |
1386 | dev_priv->last_instdone1 = instdone1; | |
1387 | } | |
f65d9421 | 1388 | |
8c80b59b | 1389 | out: |
f65d9421 | 1390 | /* Reset timer case chip hangs without another request being added */ |
b3b079db CW |
1391 | mod_timer(&dev_priv->hangcheck_timer, |
1392 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 BG |
1393 | } |
1394 | ||
1da177e4 LT |
1395 | /* drm_dma.h hooks |
1396 | */ | |
f2b115e6 | 1397 | static void ironlake_irq_preinstall(struct drm_device *dev) |
036a4a7d ZW |
1398 | { |
1399 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1400 | ||
1401 | I915_WRITE(HWSTAM, 0xeffe); | |
1402 | ||
1403 | /* XXX hotplug from PCH */ | |
1404 | ||
1405 | I915_WRITE(DEIMR, 0xffffffff); | |
1406 | I915_WRITE(DEIER, 0x0); | |
1407 | (void) I915_READ(DEIER); | |
1408 | ||
1409 | /* and GT */ | |
1410 | I915_WRITE(GTIMR, 0xffffffff); | |
1411 | I915_WRITE(GTIER, 0x0); | |
1412 | (void) I915_READ(GTIER); | |
c650156a ZW |
1413 | |
1414 | /* south display irq */ | |
1415 | I915_WRITE(SDEIMR, 0xffffffff); | |
1416 | I915_WRITE(SDEIER, 0x0); | |
1417 | (void) I915_READ(SDEIER); | |
036a4a7d ZW |
1418 | } |
1419 | ||
f2b115e6 | 1420 | static int ironlake_irq_postinstall(struct drm_device *dev) |
036a4a7d ZW |
1421 | { |
1422 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1423 | /* enable kind of interrupts always enabled */ | |
013d5aa2 JB |
1424 | u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT | |
1425 | DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE; | |
d1b851fc | 1426 | u32 render_mask = GT_PIPE_NOTIFY | GT_BSD_USER_INTERRUPT; |
c650156a ZW |
1427 | u32 hotplug_mask = SDE_CRT_HOTPLUG | SDE_PORTB_HOTPLUG | |
1428 | SDE_PORTC_HOTPLUG | SDE_PORTD_HOTPLUG; | |
036a4a7d ZW |
1429 | |
1430 | dev_priv->irq_mask_reg = ~display_mask; | |
643ced9b | 1431 | dev_priv->de_irq_enable_reg = display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK; |
036a4a7d ZW |
1432 | |
1433 | /* should always can generate irq */ | |
1434 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1435 | I915_WRITE(DEIMR, dev_priv->irq_mask_reg); | |
1436 | I915_WRITE(DEIER, dev_priv->de_irq_enable_reg); | |
1437 | (void) I915_READ(DEIER); | |
1438 | ||
3fdef020 ZW |
1439 | /* Gen6 only needs render pipe_control now */ |
1440 | if (IS_GEN6(dev)) | |
1441 | render_mask = GT_PIPE_NOTIFY; | |
1442 | ||
852835f3 | 1443 | dev_priv->gt_irq_mask_reg = ~render_mask; |
036a4a7d ZW |
1444 | dev_priv->gt_irq_enable_reg = render_mask; |
1445 | ||
1446 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1447 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask_reg); | |
3fdef020 ZW |
1448 | if (IS_GEN6(dev)) |
1449 | I915_WRITE(GEN6_RENDER_IMR, ~GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT); | |
036a4a7d ZW |
1450 | I915_WRITE(GTIER, dev_priv->gt_irq_enable_reg); |
1451 | (void) I915_READ(GTIER); | |
1452 | ||
c650156a ZW |
1453 | dev_priv->pch_irq_mask_reg = ~hotplug_mask; |
1454 | dev_priv->pch_irq_enable_reg = hotplug_mask; | |
1455 | ||
1456 | I915_WRITE(SDEIIR, I915_READ(SDEIIR)); | |
1457 | I915_WRITE(SDEIMR, dev_priv->pch_irq_mask_reg); | |
1458 | I915_WRITE(SDEIER, dev_priv->pch_irq_enable_reg); | |
1459 | (void) I915_READ(SDEIER); | |
1460 | ||
f97108d1 JB |
1461 | if (IS_IRONLAKE_M(dev)) { |
1462 | /* Clear & enable PCU event interrupts */ | |
1463 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
1464 | I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT); | |
1465 | ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT); | |
1466 | } | |
1467 | ||
036a4a7d ZW |
1468 | return 0; |
1469 | } | |
1470 | ||
84b1fd10 | 1471 | void i915_driver_irq_preinstall(struct drm_device * dev) |
1da177e4 LT |
1472 | { |
1473 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1474 | ||
79e53945 JB |
1475 | atomic_set(&dev_priv->irq_received, 0); |
1476 | ||
036a4a7d | 1477 | INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func); |
8a905236 | 1478 | INIT_WORK(&dev_priv->error_work, i915_error_work_func); |
036a4a7d | 1479 | |
bad720ff | 1480 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1481 | ironlake_irq_preinstall(dev); |
036a4a7d ZW |
1482 | return; |
1483 | } | |
1484 | ||
5ca58282 JB |
1485 | if (I915_HAS_HOTPLUG(dev)) { |
1486 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1487 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1488 | } | |
1489 | ||
0a3e67a4 | 1490 | I915_WRITE(HWSTAM, 0xeffe); |
7c463586 KP |
1491 | I915_WRITE(PIPEASTAT, 0); |
1492 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1493 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1494 | I915_WRITE(IER, 0x0); |
7c463586 | 1495 | (void) I915_READ(IER); |
1da177e4 LT |
1496 | } |
1497 | ||
b01f2c3a JB |
1498 | /* |
1499 | * Must be called after intel_modeset_init or hotplug interrupts won't be | |
1500 | * enabled correctly. | |
1501 | */ | |
0a3e67a4 | 1502 | int i915_driver_irq_postinstall(struct drm_device *dev) |
1da177e4 LT |
1503 | { |
1504 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
5ca58282 | 1505 | u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR; |
63eeaf38 | 1506 | u32 error_mask; |
0a3e67a4 | 1507 | |
852835f3 | 1508 | DRM_INIT_WAITQUEUE(&dev_priv->render_ring.irq_queue); |
036a4a7d | 1509 | |
d1b851fc ZN |
1510 | if (HAS_BSD(dev)) |
1511 | DRM_INIT_WAITQUEUE(&dev_priv->bsd_ring.irq_queue); | |
1512 | ||
0a3e67a4 | 1513 | dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B; |
0a3e67a4 | 1514 | |
bad720ff | 1515 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 1516 | return ironlake_irq_postinstall(dev); |
036a4a7d | 1517 | |
7c463586 KP |
1518 | /* Unmask the interrupts that we always want on. */ |
1519 | dev_priv->irq_mask_reg = ~I915_INTERRUPT_ENABLE_FIX; | |
1520 | ||
1521 | dev_priv->pipestat[0] = 0; | |
1522 | dev_priv->pipestat[1] = 0; | |
1523 | ||
5ca58282 | 1524 | if (I915_HAS_HOTPLUG(dev)) { |
5ca58282 JB |
1525 | /* Enable in IER... */ |
1526 | enable_mask |= I915_DISPLAY_PORT_INTERRUPT; | |
1527 | /* and unmask in IMR */ | |
c496fa1f | 1528 | dev_priv->irq_mask_reg &= ~I915_DISPLAY_PORT_INTERRUPT; |
5ca58282 JB |
1529 | } |
1530 | ||
63eeaf38 JB |
1531 | /* |
1532 | * Enable some error detection, note the instruction error mask | |
1533 | * bit is reserved, so we leave it masked. | |
1534 | */ | |
1535 | if (IS_G4X(dev)) { | |
1536 | error_mask = ~(GM45_ERROR_PAGE_TABLE | | |
1537 | GM45_ERROR_MEM_PRIV | | |
1538 | GM45_ERROR_CP_PRIV | | |
1539 | I915_ERROR_MEMORY_REFRESH); | |
1540 | } else { | |
1541 | error_mask = ~(I915_ERROR_PAGE_TABLE | | |
1542 | I915_ERROR_MEMORY_REFRESH); | |
1543 | } | |
1544 | I915_WRITE(EMR, error_mask); | |
1545 | ||
7c463586 | 1546 | I915_WRITE(IMR, dev_priv->irq_mask_reg); |
c496fa1f | 1547 | I915_WRITE(IER, enable_mask); |
ed4cb414 EA |
1548 | (void) I915_READ(IER); |
1549 | ||
c496fa1f AJ |
1550 | if (I915_HAS_HOTPLUG(dev)) { |
1551 | u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN); | |
1552 | ||
1553 | /* Note HDMI and DP share bits */ | |
1554 | if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS) | |
1555 | hotplug_en |= HDMIB_HOTPLUG_INT_EN; | |
1556 | if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS) | |
1557 | hotplug_en |= HDMIC_HOTPLUG_INT_EN; | |
1558 | if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS) | |
1559 | hotplug_en |= HDMID_HOTPLUG_INT_EN; | |
1560 | if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS) | |
1561 | hotplug_en |= SDVOC_HOTPLUG_INT_EN; | |
1562 | if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS) | |
1563 | hotplug_en |= SDVOB_HOTPLUG_INT_EN; | |
2d1c9752 | 1564 | if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) { |
c496fa1f | 1565 | hotplug_en |= CRT_HOTPLUG_INT_EN; |
2d1c9752 AL |
1566 | |
1567 | /* Programming the CRT detection parameters tends | |
1568 | to generate a spurious hotplug event about three | |
1569 | seconds later. So just do it once. | |
1570 | */ | |
1571 | if (IS_G4X(dev)) | |
1572 | hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64; | |
1573 | hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50; | |
1574 | } | |
1575 | ||
c496fa1f AJ |
1576 | /* Ignore TV since it's buggy */ |
1577 | ||
1578 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
1579 | } | |
1580 | ||
3b617967 | 1581 | intel_opregion_enable_asle(dev); |
0a3e67a4 JB |
1582 | |
1583 | return 0; | |
1da177e4 LT |
1584 | } |
1585 | ||
f2b115e6 | 1586 | static void ironlake_irq_uninstall(struct drm_device *dev) |
036a4a7d ZW |
1587 | { |
1588 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
1589 | I915_WRITE(HWSTAM, 0xffffffff); | |
1590 | ||
1591 | I915_WRITE(DEIMR, 0xffffffff); | |
1592 | I915_WRITE(DEIER, 0x0); | |
1593 | I915_WRITE(DEIIR, I915_READ(DEIIR)); | |
1594 | ||
1595 | I915_WRITE(GTIMR, 0xffffffff); | |
1596 | I915_WRITE(GTIER, 0x0); | |
1597 | I915_WRITE(GTIIR, I915_READ(GTIIR)); | |
1598 | } | |
1599 | ||
84b1fd10 | 1600 | void i915_driver_irq_uninstall(struct drm_device * dev) |
1da177e4 LT |
1601 | { |
1602 | drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; | |
91e3738e | 1603 | |
1da177e4 LT |
1604 | if (!dev_priv) |
1605 | return; | |
1606 | ||
0a3e67a4 JB |
1607 | dev_priv->vblank_pipe = 0; |
1608 | ||
bad720ff | 1609 | if (HAS_PCH_SPLIT(dev)) { |
f2b115e6 | 1610 | ironlake_irq_uninstall(dev); |
036a4a7d ZW |
1611 | return; |
1612 | } | |
1613 | ||
5ca58282 JB |
1614 | if (I915_HAS_HOTPLUG(dev)) { |
1615 | I915_WRITE(PORT_HOTPLUG_EN, 0); | |
1616 | I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT)); | |
1617 | } | |
1618 | ||
0a3e67a4 | 1619 | I915_WRITE(HWSTAM, 0xffffffff); |
7c463586 KP |
1620 | I915_WRITE(PIPEASTAT, 0); |
1621 | I915_WRITE(PIPEBSTAT, 0); | |
0a3e67a4 | 1622 | I915_WRITE(IMR, 0xffffffff); |
ed4cb414 | 1623 | I915_WRITE(IER, 0x0); |
af6061af | 1624 | |
7c463586 KP |
1625 | I915_WRITE(PIPEASTAT, I915_READ(PIPEASTAT) & 0x8000ffff); |
1626 | I915_WRITE(PIPEBSTAT, I915_READ(PIPEBSTAT) & 0x8000ffff); | |
1627 | I915_WRITE(IIR, I915_READ(IIR)); | |
1da177e4 | 1628 | } |