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drm/i915: Remove gen3 irq code from gen4 irq routine
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / i915 / i915_irq.c
CommitLineData
0d6aa60b 1/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
1da177e4 2 */
0d6aa60b 3/*
1da177e4
LT		 4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
bc54fd1a
DA		 6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
0d6aa60b 27 */
1da177e4 28
a70491cc
JP		 29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
63eeaf38 31#include <linux/sysrq.h>
5a0e3ad6 32#include <linux/slab.h>
1da177e4
LT		 33#include "drmP.h"
34#include "drm.h"
35#include "i915_drm.h"
36#include "i915_drv.h"
1c5d22f7 37#include "i915_trace.h"
79e53945 38#include "intel_drv.h"
1da177e4 39
1da177e4 40#define MAX_NOPID ((u32)~0)
1da177e4 41
7c463586
KP		 42/**
43 * Interrupts that are always left unmasked.
44 *
45 * Since pipe events are edge-triggered from the PIPESTAT register to IIR,
46 * we leave them always unmasked in IMR and then control enabling them through
47 * PIPESTAT alone.
48 */
6b95a207
KH		 49#define I915_INTERRUPT_ENABLE_FIX \
50 (I915_ASLE_INTERRUPT | \
51 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | \
52 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | \
53 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | \
54 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT | \
55 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
7c463586
KP		 56
57/** Interrupts that we mask and unmask at runtime. */
d1b851fc 58#define I915_INTERRUPT_ENABLE_VAR (I915_USER_INTERRUPT | I915_BSD_USER_INTERRUPT)
7c463586 59
79e53945
JB		 60#define I915_PIPE_VBLANK_STATUS (PIPE_START_VBLANK_INTERRUPT_STATUS |\
61 PIPE_VBLANK_INTERRUPT_STATUS)
62
63#define I915_PIPE_VBLANK_ENABLE (PIPE_START_VBLANK_INTERRUPT_ENABLE |\
64 PIPE_VBLANK_INTERRUPT_ENABLE)
65
66#define DRM_I915_VBLANK_PIPE_ALL (DRM_I915_VBLANK_PIPE_A | \
67 DRM_I915_VBLANK_PIPE_B)
68
036a4a7d 69/* For display hotplug interrupt */
995b6762 70static void
f2b115e6 71ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 72{
1ec14ad3
CW		 73 if ((dev_priv->irq_mask & mask) != 0) {
74 dev_priv->irq_mask &= ~mask;
75 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 76 POSTING_READ(DEIMR);
036a4a7d
ZW		 77 }
78}
79
80static inline void
f2b115e6 81ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
036a4a7d 82{
1ec14ad3
CW		 83 if ((dev_priv->irq_mask & mask) != mask) {
84 dev_priv->irq_mask |= mask;
85 I915_WRITE(DEIMR, dev_priv->irq_mask);
3143a2bf 86 POSTING_READ(DEIMR);
036a4a7d
ZW		 87 }
88}
89
7c463586
KP		 90void
91i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
92{
93 if ((dev_priv->pipestat[pipe] & mask) != mask) {
9db4a9c7 94 u32 reg = PIPESTAT(pipe);
7c463586
KP		 95
96 dev_priv->pipestat[pipe] |= mask;
97 /* Enable the interrupt, clear any pending status */
98 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16));
3143a2bf 99 POSTING_READ(reg);
7c463586
KP		 100 }
101}
102
103void
104i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
105{
106 if ((dev_priv->pipestat[pipe] & mask) != 0) {
9db4a9c7 107 u32 reg = PIPESTAT(pipe);
7c463586
KP		 108
109 dev_priv->pipestat[pipe] &= ~mask;
110 I915_WRITE(reg, dev_priv->pipestat[pipe]);
3143a2bf 111 POSTING_READ(reg);
7c463586
KP		 112 }
113}
114
01c66889
ZY		 115/**
116 * intel_enable_asle - enable ASLE interrupt for OpRegion
117 */
1ec14ad3 118void intel_enable_asle(struct drm_device *dev)
01c66889 119{
1ec14ad3
CW		 120 drm_i915_private_t *dev_priv = dev->dev_private;
121 unsigned long irqflags;
122
7e231dbe
JB		 123 /* FIXME: opregion/asle for VLV */
124 if (IS_VALLEYVIEW(dev))
125 return;
126
1ec14ad3 127 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
01c66889 128
c619eed4 129 if (HAS_PCH_SPLIT(dev))
f2b115e6 130 ironlake_enable_display_irq(dev_priv, DE_GSE);
edcb49ca 131 else {
01c66889 132 i915_enable_pipestat(dev_priv, 1,
d874bcff 133 PIPE_LEGACY_BLC_EVENT_ENABLE);
a6c45cf0 134 if (INTEL_INFO(dev)->gen >= 4)
edcb49ca 135 i915_enable_pipestat(dev_priv, 0,
d874bcff 136 PIPE_LEGACY_BLC_EVENT_ENABLE);
edcb49ca 137 }
1ec14ad3
CW		 138
139 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
01c66889
ZY		 140}
141
0a3e67a4
JB		 142/**
143 * i915_pipe_enabled - check if a pipe is enabled
144 * @dev: DRM device
145 * @pipe: pipe to check
146 *
147 * Reading certain registers when the pipe is disabled can hang the chip.
148 * Use this routine to make sure the PLL is running and the pipe is active
149 * before reading such registers if unsure.
150 */
151static int
152i915_pipe_enabled(struct drm_device *dev, int pipe)
153{
154 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
5eddb70b 155 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE;
0a3e67a4
JB		 156}
157
42f52ef8
KP		 158/* Called from drm generic code, passed a 'crtc', which
159 * we use as a pipe index
160 */
f71d4af4 161static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
0a3e67a4
JB		 162{
163 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
164 unsigned long high_frame;
165 unsigned long low_frame;
5eddb70b 166 u32 high1, high2, low;
0a3e67a4
JB		 167
168 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 169 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 170 "pipe %c\n", pipe_name(pipe));
0a3e67a4
JB		 171 return 0;
172 }
173
9db4a9c7
JB		 174 high_frame = PIPEFRAME(pipe);
175 low_frame = PIPEFRAMEPIXEL(pipe);
5eddb70b 176
0a3e67a4
JB		 177 /*
178 * High & low register fields aren't synchronized, so make sure
179 * we get a low value that's stable across two reads of the high
180 * register.
181 */
182 do {
5eddb70b
CW		 183 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
184 low = I915_READ(low_frame) & PIPE_FRAME_LOW_MASK;
185 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
0a3e67a4
JB		 186 } while (high1 != high2);
187
5eddb70b
CW		 188 high1 >>= PIPE_FRAME_HIGH_SHIFT;
189 low >>= PIPE_FRAME_LOW_SHIFT;
190 return (high1 << 8) | low;
0a3e67a4
JB		 191}
192
f71d4af4 193static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
9880b7a5
JB		 194{
195 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 196 int reg = PIPE_FRMCOUNT_GM45(pipe);
9880b7a5
JB		 197
198 if (!i915_pipe_enabled(dev, pipe)) {
44d98a61 199 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
9db4a9c7 200 "pipe %c\n", pipe_name(pipe));
9880b7a5
JB		 201 return 0;
202 }
203
204 return I915_READ(reg);
205}
206
f71d4af4 207static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
0af7e4df
MK		 208 int *vpos, int *hpos)
209{
210 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
211 u32 vbl = 0, position = 0;
212 int vbl_start, vbl_end, htotal, vtotal;
213 bool in_vbl = true;
214 int ret = 0;
215
216 if (!i915_pipe_enabled(dev, pipe)) {
217 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
9db4a9c7 218 "pipe %c\n", pipe_name(pipe));
0af7e4df
MK		 219 return 0;
220 }
221
222 /* Get vtotal. */
223 vtotal = 1 + ((I915_READ(VTOTAL(pipe)) >> 16) & 0x1fff);
224
225 if (INTEL_INFO(dev)->gen >= 4) {
226 /* No obvious pixelcount register. Only query vertical
227 * scanout position from Display scan line register.
228 */
229 position = I915_READ(PIPEDSL(pipe));
230
231 /* Decode into vertical scanout position. Don't have
232 * horizontal scanout position.
233 */
234 *vpos = position & 0x1fff;
235 *hpos = 0;
236 } else {
237 /* Have access to pixelcount since start of frame.
238 * We can split this into vertical and horizontal
239 * scanout position.
240 */
241 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
242
243 htotal = 1 + ((I915_READ(HTOTAL(pipe)) >> 16) & 0x1fff);
244 *vpos = position / htotal;
245 *hpos = position - (*vpos * htotal);
246 }
247
248 /* Query vblank area. */
249 vbl = I915_READ(VBLANK(pipe));
250
251 /* Test position against vblank region. */
252 vbl_start = vbl & 0x1fff;
253 vbl_end = (vbl >> 16) & 0x1fff;
254
255 if ((*vpos < vbl_start) || (*vpos > vbl_end))
256 in_vbl = false;
257
258 /* Inside "upper part" of vblank area? Apply corrective offset: */
259 if (in_vbl && (*vpos >= vbl_start))
260 *vpos = *vpos - vtotal;
261
262 /* Readouts valid? */
263 if (vbl > 0)
264 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
265
266 /* In vblank? */
267 if (in_vbl)
268 ret |= DRM_SCANOUTPOS_INVBL;
269
270 return ret;
271}
272
f71d4af4 273static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
0af7e4df
MK		 274 int *max_error,
275 struct timeval *vblank_time,
276 unsigned flags)
277{
4041b853
CW		 278 struct drm_i915_private *dev_priv = dev->dev_private;
279 struct drm_crtc *crtc;
0af7e4df 280
4041b853
CW		 281 if (pipe < 0 || pipe >= dev_priv->num_pipe) {
282 DRM_ERROR("Invalid crtc %d\n", pipe);
0af7e4df
MK		 283 return -EINVAL;
284 }
285
286 /* Get drm_crtc to timestamp: */
4041b853
CW		 287 crtc = intel_get_crtc_for_pipe(dev, pipe);
288 if (crtc == NULL) {
289 DRM_ERROR("Invalid crtc %d\n", pipe);
290 return -EINVAL;
291 }
292
293 if (!crtc->enabled) {
294 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
295 return -EBUSY;
296 }
0af7e4df
MK		 297
298 /* Helper routine in DRM core does all the work: */
4041b853
CW		 299 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
300 vblank_time, flags,
301 crtc);
0af7e4df
MK		 302}
303
5ca58282
JB		 304/*
305 * Handle hotplug events outside the interrupt handler proper.
306 */
307static void i915_hotplug_work_func(struct work_struct *work)
308{
309 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
310 hotplug_work);
311 struct drm_device *dev = dev_priv->dev;
c31c4ba3 312 struct drm_mode_config *mode_config = &dev->mode_config;
4ef69c7a
CW		 313 struct intel_encoder *encoder;
314
a65e34c7 315 mutex_lock(&mode_config->mutex);
e67189ab
JB		 316 DRM_DEBUG_KMS("running encoder hotplug functions\n");
317
4ef69c7a
CW		 318 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
319 if (encoder->hot_plug)
320 encoder->hot_plug(encoder);
321
40ee3381
KP		 322 mutex_unlock(&mode_config->mutex);
323
5ca58282 324 /* Just fire off a uevent and let userspace tell us what to do */
eb1f8e4f 325 drm_helper_hpd_irq_event(dev);
5ca58282
JB		 326}
327
f97108d1
JB		 328static void i915_handle_rps_change(struct drm_device *dev)
329{
330 drm_i915_private_t *dev_priv = dev->dev_private;
b5b72e89 331 u32 busy_up, busy_down, max_avg, min_avg;
f97108d1
JB		 332 u8 new_delay = dev_priv->cur_delay;
333
7648fa99 334 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
b5b72e89
MG		 335 busy_up = I915_READ(RCPREVBSYTUPAVG);
336 busy_down = I915_READ(RCPREVBSYTDNAVG);
f97108d1
JB		 337 max_avg = I915_READ(RCBMAXAVG);
338 min_avg = I915_READ(RCBMINAVG);
339
340 /* Handle RCS change request from hw */
b5b72e89 341 if (busy_up > max_avg) {
f97108d1
JB		 342 if (dev_priv->cur_delay != dev_priv->max_delay)
343 new_delay = dev_priv->cur_delay - 1;
344 if (new_delay < dev_priv->max_delay)
345 new_delay = dev_priv->max_delay;
b5b72e89 346 } else if (busy_down < min_avg) {
f97108d1
JB		 347 if (dev_priv->cur_delay != dev_priv->min_delay)
348 new_delay = dev_priv->cur_delay + 1;
349 if (new_delay > dev_priv->min_delay)
350 new_delay = dev_priv->min_delay;
351 }
352
7648fa99
JB		 353 if (ironlake_set_drps(dev, new_delay))
354 dev_priv->cur_delay = new_delay;
f97108d1
JB		 355
356 return;
357}
358
549f7365
CW		 359static void notify_ring(struct drm_device *dev,
360 struct intel_ring_buffer *ring)
361{
362 struct drm_i915_private *dev_priv = dev->dev_private;
475553de 363 u32 seqno;
9862e600 364
475553de
CW		 365 if (ring->obj == NULL)
366 return;
367
368 seqno = ring->get_seqno(ring);
db53a302 369 trace_i915_gem_request_complete(ring, seqno);
9862e600
CW		 370
371 ring->irq_seqno = seqno;
549f7365 372 wake_up_all(&ring->irq_queue);
3e0dc6b0
BW		 373 if (i915_enable_hangcheck) {
374 dev_priv->hangcheck_count = 0;
375 mod_timer(&dev_priv->hangcheck_timer,
376 jiffies +
377 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
378 }
549f7365
CW		 379}
380
4912d041 381static void gen6_pm_rps_work(struct work_struct *work)
3b8d8d91 382{
4912d041
BW		 383 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
384 rps_work);
3b8d8d91 385 u8 new_delay = dev_priv->cur_delay;
4912d041
BW		 386 u32 pm_iir, pm_imr;
387
388 spin_lock_irq(&dev_priv->rps_lock);
389 pm_iir = dev_priv->pm_iir;
390 dev_priv->pm_iir = 0;
391 pm_imr = I915_READ(GEN6_PMIMR);
a9e2641d 392 I915_WRITE(GEN6_PMIMR, 0);
4912d041 393 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91 394
3b8d8d91
JB		 395 if (!pm_iir)
396 return;
397
4912d041 398 mutex_lock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 399 if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
400 if (dev_priv->cur_delay != dev_priv->max_delay)
401 new_delay = dev_priv->cur_delay + 1;
402 if (new_delay > dev_priv->max_delay)
403 new_delay = dev_priv->max_delay;
404 } else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
4912d041 405 gen6_gt_force_wake_get(dev_priv);
3b8d8d91
JB		 406 if (dev_priv->cur_delay != dev_priv->min_delay)
407 new_delay = dev_priv->cur_delay - 1;
408 if (new_delay < dev_priv->min_delay) {
409 new_delay = dev_priv->min_delay;
410 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
411 I915_READ(GEN6_RP_INTERRUPT_LIMITS) |
412 ((new_delay << 16) & 0x3f0000));
413 } else {
414 /* Make sure we continue to get down interrupts
415 * until we hit the minimum frequency */
416 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
417 I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
418 }
4912d041 419 gen6_gt_force_wake_put(dev_priv);
3b8d8d91
JB		 420 }
421
4912d041 422 gen6_set_rps(dev_priv->dev, new_delay);
3b8d8d91
JB		 423 dev_priv->cur_delay = new_delay;
424
4912d041
BW		 425 /*
426 * rps_lock not held here because clearing is non-destructive. There is
427 * an *extremely* unlikely race with gen6_rps_enable() that is prevented
428 * by holding struct_mutex for the duration of the write.
429 */
4912d041 430 mutex_unlock(&dev_priv->dev->struct_mutex);
3b8d8d91
JB		 431}
432
e7b4c6b1
DV		 433static void snb_gt_irq_handler(struct drm_device *dev,
434 struct drm_i915_private *dev_priv,
435 u32 gt_iir)
436{
437
438 if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
439 GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
440 notify_ring(dev, &dev_priv->ring[RCS]);
441 if (gt_iir & GEN6_BSD_USER_INTERRUPT)
442 notify_ring(dev, &dev_priv->ring[VCS]);
443 if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
444 notify_ring(dev, &dev_priv->ring[BCS]);
445
446 if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
447 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
448 GT_RENDER_CS_ERROR_INTERRUPT)) {
449 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
450 i915_handle_error(dev, false);
451 }
452}
453
fc6826d1
CW		 454static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
455 u32 pm_iir)
456{
457 unsigned long flags;
458
459 /*
460 * IIR bits should never already be set because IMR should
461 * prevent an interrupt from being shown in IIR. The warning
462 * displays a case where we've unsafely cleared
463 * dev_priv->pm_iir. Although missing an interrupt of the same
464 * type is not a problem, it displays a problem in the logic.
465 *
466 * The mask bit in IMR is cleared by rps_work.
467 */
468
469 spin_lock_irqsave(&dev_priv->rps_lock, flags);
470 WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
471 dev_priv->pm_iir |= pm_iir;
472 I915_WRITE(GEN6_PMIMR, dev_priv->pm_iir);
473 POSTING_READ(GEN6_PMIMR);
474 spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
475
476 queue_work(dev_priv->wq, &dev_priv->rps_work);
477}
478
7e231dbe
JB		 479static irqreturn_t valleyview_irq_handler(DRM_IRQ_ARGS)
480{
481 struct drm_device *dev = (struct drm_device *) arg;
482 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
483 u32 iir, gt_iir, pm_iir;
484 irqreturn_t ret = IRQ_NONE;
485 unsigned long irqflags;
486 int pipe;
487 u32 pipe_stats[I915_MAX_PIPES];
488 u32 vblank_status;
489 int vblank = 0;
490 bool blc_event;
491
492 atomic_inc(&dev_priv->irq_received);
493
494 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS |
495 PIPE_VBLANK_INTERRUPT_STATUS;
496
497 while (true) {
498 iir = I915_READ(VLV_IIR);
499 gt_iir = I915_READ(GTIIR);
500 pm_iir = I915_READ(GEN6_PMIIR);
501
502 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
503 goto out;
504
505 ret = IRQ_HANDLED;
506
e7b4c6b1 507 snb_gt_irq_handler(dev, dev_priv, gt_iir);
7e231dbe
JB		 508
509 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
510 for_each_pipe(pipe) {
511 int reg = PIPESTAT(pipe);
512 pipe_stats[pipe] = I915_READ(reg);
513
514 /*
515 * Clear the PIPE*STAT regs before the IIR
516 */
517 if (pipe_stats[pipe] & 0x8000ffff) {
518 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
519 DRM_DEBUG_DRIVER("pipe %c underrun\n",
520 pipe_name(pipe));
521 I915_WRITE(reg, pipe_stats[pipe]);
522 }
523 }
524 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
525
526 /* Consume port. Then clear IIR or we'll miss events */
527 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
528 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
529
530 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
531 hotplug_status);
532 if (hotplug_status & dev_priv->hotplug_supported_mask)
533 queue_work(dev_priv->wq,
534 &dev_priv->hotplug_work);
535
536 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
537 I915_READ(PORT_HOTPLUG_STAT);
538 }
539
540
541 if (iir & I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT) {
542 drm_handle_vblank(dev, 0);
543 vblank++;
e0f608d7 544 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 545 }
546
547 if (iir & I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT) {
548 drm_handle_vblank(dev, 1);
549 vblank++;
e0f608d7 550 intel_finish_page_flip(dev, 0);
7e231dbe
JB		 551 }
552
553 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
554 blc_event = true;
555
fc6826d1
CW		 556 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
557 gen6_queue_rps_work(dev_priv, pm_iir);
7e231dbe
JB		 558
559 I915_WRITE(GTIIR, gt_iir);
560 I915_WRITE(GEN6_PMIIR, pm_iir);
561 I915_WRITE(VLV_IIR, iir);
562 }
563
564out:
565 return ret;
566}
567
776ad806
JB		 568static void pch_irq_handler(struct drm_device *dev)
569{
570 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
571 u32 pch_iir;
9db4a9c7 572 int pipe;
776ad806
JB		 573
574 pch_iir = I915_READ(SDEIIR);
575
576 if (pch_iir & SDE_AUDIO_POWER_MASK)
577 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
578 (pch_iir & SDE_AUDIO_POWER_MASK) >>
579 SDE_AUDIO_POWER_SHIFT);
580
581 if (pch_iir & SDE_GMBUS)
582 DRM_DEBUG_DRIVER("PCH GMBUS interrupt\n");
583
584 if (pch_iir & SDE_AUDIO_HDCP_MASK)
585 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
586
587 if (pch_iir & SDE_AUDIO_TRANS_MASK)
588 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
589
590 if (pch_iir & SDE_POISON)
591 DRM_ERROR("PCH poison interrupt\n");
592
9db4a9c7
JB		 593 if (pch_iir & SDE_FDI_MASK)
594 for_each_pipe(pipe)
595 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
596 pipe_name(pipe),
597 I915_READ(FDI_RX_IIR(pipe)));
776ad806
JB		 598
599 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
600 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
601
602 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
603 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
604
605 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
606 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
607 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
608 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
609}
610
f71d4af4 611static irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
b1f14ad0
JB		 612{
613 struct drm_device *dev = (struct drm_device *) arg;
614 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
615 int ret = IRQ_NONE;
616 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
617 struct drm_i915_master_private *master_priv;
618
619 atomic_inc(&dev_priv->irq_received);
620
621 /* disable master interrupt before clearing iir */
622 de_ier = I915_READ(DEIER);
623 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
624 POSTING_READ(DEIER);
625
626 de_iir = I915_READ(DEIIR);
627 gt_iir = I915_READ(GTIIR);
628 pch_iir = I915_READ(SDEIIR);
629 pm_iir = I915_READ(GEN6_PMIIR);
630
631 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
632 goto done;
633
634 ret = IRQ_HANDLED;
635
636 if (dev->primary->master) {
637 master_priv = dev->primary->master->driver_priv;
638 if (master_priv->sarea_priv)
639 master_priv->sarea_priv->last_dispatch =
640 READ_BREADCRUMB(dev_priv);
641 }
642
e7b4c6b1 643 snb_gt_irq_handler(dev, dev_priv, gt_iir);
b1f14ad0
JB		 644
645 if (de_iir & DE_GSE_IVB)
646 intel_opregion_gse_intr(dev);
647
648 if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
649 intel_prepare_page_flip(dev, 0);
650 intel_finish_page_flip_plane(dev, 0);
651 }
652
653 if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
654 intel_prepare_page_flip(dev, 1);
655 intel_finish_page_flip_plane(dev, 1);
656 }
657
658 if (de_iir & DE_PIPEA_VBLANK_IVB)
659 drm_handle_vblank(dev, 0);
660
f6b07f45 661 if (de_iir & DE_PIPEB_VBLANK_IVB)
b1f14ad0
JB		 662 drm_handle_vblank(dev, 1);
663
664 /* check event from PCH */
665 if (de_iir & DE_PCH_EVENT_IVB) {
666 if (pch_iir & SDE_HOTPLUG_MASK_CPT)
667 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
668 pch_irq_handler(dev);
669 }
670
fc6826d1
CW		 671 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
672 gen6_queue_rps_work(dev_priv, pm_iir);
b1f14ad0
JB		 673
674 /* should clear PCH hotplug event before clear CPU irq */
675 I915_WRITE(SDEIIR, pch_iir);
676 I915_WRITE(GTIIR, gt_iir);
677 I915_WRITE(DEIIR, de_iir);
678 I915_WRITE(GEN6_PMIIR, pm_iir);
679
680done:
681 I915_WRITE(DEIER, de_ier);
682 POSTING_READ(DEIER);
683
684 return ret;
685}
686
e7b4c6b1
DV		 687static void ilk_gt_irq_handler(struct drm_device *dev,
688 struct drm_i915_private *dev_priv,
689 u32 gt_iir)
690{
691 if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
692 notify_ring(dev, &dev_priv->ring[RCS]);
693 if (gt_iir & GT_BSD_USER_INTERRUPT)
694 notify_ring(dev, &dev_priv->ring[VCS]);
695}
696
f71d4af4 697static irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
036a4a7d 698{
4697995b 699 struct drm_device *dev = (struct drm_device *) arg;
036a4a7d
ZW		 700 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
701 int ret = IRQ_NONE;
3b8d8d91 702 u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
2d7b8366 703 u32 hotplug_mask;
036a4a7d 704 struct drm_i915_master_private *master_priv;
881f47b6 705
4697995b
JB		 706 atomic_inc(&dev_priv->irq_received);
707
2d109a84
ZN		 708 /* disable master interrupt before clearing iir */
709 de_ier = I915_READ(DEIER);
710 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
3143a2bf 711 POSTING_READ(DEIER);
2d109a84 712
036a4a7d
ZW		 713 de_iir = I915_READ(DEIIR);
714 gt_iir = I915_READ(GTIIR);
c650156a 715 pch_iir = I915_READ(SDEIIR);
3b8d8d91 716 pm_iir = I915_READ(GEN6_PMIIR);
036a4a7d 717
3b8d8d91
JB		 718 if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 &&
719 (!IS_GEN6(dev) || pm_iir == 0))
c7c85101 720 goto done;
036a4a7d 721
2d7b8366
YL		 722 if (HAS_PCH_CPT(dev))
723 hotplug_mask = SDE_HOTPLUG_MASK_CPT;
724 else
725 hotplug_mask = SDE_HOTPLUG_MASK;
726
c7c85101 727 ret = IRQ_HANDLED;
036a4a7d 728
c7c85101
ZN		 729 if (dev->primary->master) {
730 master_priv = dev->primary->master->driver_priv;
731 if (master_priv->sarea_priv)
732 master_priv->sarea_priv->last_dispatch =
733 READ_BREADCRUMB(dev_priv);
734 }
036a4a7d 735
e7b4c6b1
DV		 736 if (IS_GEN5(dev))
737 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
738 else
739 snb_gt_irq_handler(dev, dev_priv, gt_iir);
01c66889 740
c7c85101 741 if (de_iir & DE_GSE)
3b617967 742 intel_opregion_gse_intr(dev);
c650156a 743
f072d2e7 744 if (de_iir & DE_PLANEA_FLIP_DONE) {
013d5aa2 745 intel_prepare_page_flip(dev, 0);
2bbda389 746 intel_finish_page_flip_plane(dev, 0);
f072d2e7 747 }
013d5aa2 748
f072d2e7 749 if (de_iir & DE_PLANEB_FLIP_DONE) {
013d5aa2 750 intel_prepare_page_flip(dev, 1);
2bbda389 751 intel_finish_page_flip_plane(dev, 1);
f072d2e7 752 }
013d5aa2 753
f072d2e7 754 if (de_iir & DE_PIPEA_VBLANK)
c062df61
LP		 755 drm_handle_vblank(dev, 0);
756
f072d2e7 757 if (de_iir & DE_PIPEB_VBLANK)
c062df61
LP		 758 drm_handle_vblank(dev, 1);
759
c7c85101 760 /* check event from PCH */
776ad806
JB		 761 if (de_iir & DE_PCH_EVENT) {
762 if (pch_iir & hotplug_mask)
763 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
764 pch_irq_handler(dev);
765 }
036a4a7d 766
f97108d1 767 if (de_iir & DE_PCU_EVENT) {
7648fa99 768 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
f97108d1
JB		 769 i915_handle_rps_change(dev);
770 }
771
fc6826d1
CW		 772 if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
773 gen6_queue_rps_work(dev_priv, pm_iir);
3b8d8d91 774
c7c85101
ZN		 775 /* should clear PCH hotplug event before clear CPU irq */
776 I915_WRITE(SDEIIR, pch_iir);
777 I915_WRITE(GTIIR, gt_iir);
778 I915_WRITE(DEIIR, de_iir);
4912d041 779 I915_WRITE(GEN6_PMIIR, pm_iir);
c7c85101
ZN		 780
781done:
2d109a84 782 I915_WRITE(DEIER, de_ier);
3143a2bf 783 POSTING_READ(DEIER);
2d109a84 784
036a4a7d
ZW		 785 return ret;
786}
787
8a905236
JB		 788/**
789 * i915_error_work_func - do process context error handling work
790 * @work: work struct
791 *
792 * Fire an error uevent so userspace can see that a hang or error
793 * was detected.
794 */
795static void i915_error_work_func(struct work_struct *work)
796{
797 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
798 error_work);
799 struct drm_device *dev = dev_priv->dev;
f316a42c
BG		 800 char *error_event[] = { "ERROR=1", NULL };
801 char *reset_event[] = { "RESET=1", NULL };
802 char *reset_done_event[] = { "ERROR=0", NULL };
8a905236 803
f316a42c
BG		 804 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
805
ba1234d1 806 if (atomic_read(&dev_priv->mm.wedged)) {
f803aa55
CW		 807 DRM_DEBUG_DRIVER("resetting chip\n");
808 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_event);
809 if (!i915_reset(dev, GRDOM_RENDER)) {
810 atomic_set(&dev_priv->mm.wedged, 0);
811 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, reset_done_event);
f316a42c 812 }
30dbf0c0 813 complete_all(&dev_priv->error_completion);
f316a42c 814 }
8a905236
JB		 815}
816
3bd3c932 817#ifdef CONFIG_DEBUG_FS
9df30794 818static struct drm_i915_error_object *
bcfb2e28 819i915_error_object_create(struct drm_i915_private *dev_priv,
05394f39 820 struct drm_i915_gem_object *src)
9df30794
CW		 821{
822 struct drm_i915_error_object *dst;
9df30794 823 int page, page_count;
e56660dd 824 u32 reloc_offset;
9df30794 825
05394f39 826 if (src == NULL || src->pages == NULL)
9df30794
CW		 827 return NULL;
828
05394f39 829 page_count = src->base.size / PAGE_SIZE;
9df30794 830
0206e353 831 dst = kmalloc(sizeof(*dst) + page_count * sizeof(u32 *), GFP_ATOMIC);
9df30794
CW		 832 if (dst == NULL)
833 return NULL;
834
05394f39 835 reloc_offset = src->gtt_offset;
9df30794 836 for (page = 0; page < page_count; page++) {
788885ae 837 unsigned long flags;
e56660dd 838 void *d;
788885ae 839
e56660dd 840 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
9df30794
CW		 841 if (d == NULL)
842 goto unwind;
e56660dd 843
788885ae 844 local_irq_save(flags);
74898d7e
DV		 845 if (reloc_offset < dev_priv->mm.gtt_mappable_end &&
846 src->has_global_gtt_mapping) {
172975aa
CW		 847 void __iomem *s;
848
849 /* Simply ignore tiling or any overlapping fence.
850 * It's part of the error state, and this hopefully
851 * captures what the GPU read.
852 */
853
854 s = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
855 reloc_offset);
856 memcpy_fromio(d, s, PAGE_SIZE);
857 io_mapping_unmap_atomic(s);
858 } else {
859 void *s;
860
861 drm_clflush_pages(&src->pages[page], 1);
862
863 s = kmap_atomic(src->pages[page]);
864 memcpy(d, s, PAGE_SIZE);
865 kunmap_atomic(s);
866
867 drm_clflush_pages(&src->pages[page], 1);
868 }
788885ae 869 local_irq_restore(flags);
e56660dd 870
9df30794 871 dst->pages[page] = d;
e56660dd
CW		 872
873 reloc_offset += PAGE_SIZE;
9df30794
CW		 874 }
875 dst->page_count = page_count;
05394f39 876 dst->gtt_offset = src->gtt_offset;
9df30794
CW		 877
878 return dst;
879
880unwind:
881 while (page--)
882 kfree(dst->pages[page]);
883 kfree(dst);
884 return NULL;
885}
886
887static void
888i915_error_object_free(struct drm_i915_error_object *obj)
889{
890 int page;
891
892 if (obj == NULL)
893 return;
894
895 for (page = 0; page < obj->page_count; page++)
896 kfree(obj->pages[page]);
897
898 kfree(obj);
899}
900
901static void
902i915_error_state_free(struct drm_device *dev,
903 struct drm_i915_error_state *error)
904{
e2f973d5
CW		 905 int i;
906
52d39a21
CW		 907 for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
908 i915_error_object_free(error->ring[i].batchbuffer);
909 i915_error_object_free(error->ring[i].ringbuffer);
910 kfree(error->ring[i].requests);
911 }
e2f973d5 912
9df30794 913 kfree(error->active_bo);
6ef3d427 914 kfree(error->overlay);
9df30794
CW		 915 kfree(error);
916}
1b50247a
CW		 917static void capture_bo(struct drm_i915_error_buffer *err,
918 struct drm_i915_gem_object *obj)
919{
920 err->size = obj->base.size;
921 err->name = obj->base.name;
922 err->seqno = obj->last_rendering_seqno;
923 err->gtt_offset = obj->gtt_offset;
924 err->read_domains = obj->base.read_domains;
925 err->write_domain = obj->base.write_domain;
926 err->fence_reg = obj->fence_reg;
927 err->pinned = 0;
928 if (obj->pin_count > 0)
929 err->pinned = 1;
930 if (obj->user_pin_count > 0)
931 err->pinned = -1;
932 err->tiling = obj->tiling_mode;
933 err->dirty = obj->dirty;
934 err->purgeable = obj->madv != I915_MADV_WILLNEED;
935 err->ring = obj->ring ? obj->ring->id : -1;
936 err->cache_level = obj->cache_level;
937}
9df30794 938
1b50247a
CW		 939static u32 capture_active_bo(struct drm_i915_error_buffer *err,
940 int count, struct list_head *head)
c724e8a9
CW		 941{
942 struct drm_i915_gem_object *obj;
943 int i = 0;
944
945 list_for_each_entry(obj, head, mm_list) {
1b50247a 946 capture_bo(err++, obj);
c724e8a9
CW		 947 if (++i == count)
948 break;
1b50247a
CW		 949 }
950
951 return i;
952}
953
954static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
955 int count, struct list_head *head)
956{
957 struct drm_i915_gem_object *obj;
958 int i = 0;
959
960 list_for_each_entry(obj, head, gtt_list) {
961 if (obj->pin_count == 0)
962 continue;
c724e8a9 963
1b50247a
CW		 964 capture_bo(err++, obj);
965 if (++i == count)
966 break;
c724e8a9
CW		 967 }
968
969 return i;
970}
971
748ebc60
CW		 972static void i915_gem_record_fences(struct drm_device *dev,
973 struct drm_i915_error_state *error)
974{
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 int i;
977
978 /* Fences */
979 switch (INTEL_INFO(dev)->gen) {
775d17b6 980 case 7:
748ebc60
CW		 981 case 6:
982 for (i = 0; i < 16; i++)
983 error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
984 break;
985 case 5:
986 case 4:
987 for (i = 0; i < 16; i++)
988 error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
989 break;
990 case 3:
991 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
992 for (i = 0; i < 8; i++)
993 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
994 case 2:
995 for (i = 0; i < 8; i++)
996 error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
997 break;
998
999 }
1000}
1001
bcfb2e28
CW		 1002static struct drm_i915_error_object *
1003i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1004 struct intel_ring_buffer *ring)
1005{
1006 struct drm_i915_gem_object *obj;
1007 u32 seqno;
1008
1009 if (!ring->get_seqno)
1010 return NULL;
1011
1012 seqno = ring->get_seqno(ring);
1013 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1014 if (obj->ring != ring)
1015 continue;
1016
c37d9a5d 1017 if (i915_seqno_passed(seqno, obj->last_rendering_seqno))
bcfb2e28
CW		 1018 continue;
1019
1020 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1021 continue;
1022
1023 /* We need to copy these to an anonymous buffer as the simplest
1024 * method to avoid being overwritten by userspace.
1025 */
1026 return i915_error_object_create(dev_priv, obj);
1027 }
1028
1029 return NULL;
1030}
1031
d27b1e0e
DV		 1032static void i915_record_ring_state(struct drm_device *dev,
1033 struct drm_i915_error_state *error,
1034 struct intel_ring_buffer *ring)
1035{
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037
33f3f518 1038 if (INTEL_INFO(dev)->gen >= 6) {
33f3f518 1039 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
7e3b8737
DV		 1040 error->semaphore_mboxes[ring->id][0]
1041 = I915_READ(RING_SYNC_0(ring->mmio_base));
1042 error->semaphore_mboxes[ring->id][1]
1043 = I915_READ(RING_SYNC_1(ring->mmio_base));
33f3f518 1044 }
c1cd90ed 1045
d27b1e0e 1046 if (INTEL_INFO(dev)->gen >= 4) {
9d2f41fa 1047 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
d27b1e0e
DV		 1048 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1049 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1050 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
c1cd90ed 1051 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
d27b1e0e 1052 if (ring->id == RCS) {
d27b1e0e
DV		 1053 error->instdone1 = I915_READ(INSTDONE1);
1054 error->bbaddr = I915_READ64(BB_ADDR);
1055 }
1056 } else {
9d2f41fa 1057 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
d27b1e0e
DV		 1058 error->ipeir[ring->id] = I915_READ(IPEIR);
1059 error->ipehr[ring->id] = I915_READ(IPEHR);
1060 error->instdone[ring->id] = I915_READ(INSTDONE);
d27b1e0e
DV		 1061 }
1062
c1cd90ed 1063 error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
d27b1e0e
DV		 1064 error->seqno[ring->id] = ring->get_seqno(ring);
1065 error->acthd[ring->id] = intel_ring_get_active_head(ring);
c1cd90ed
DV		 1066 error->head[ring->id] = I915_READ_HEAD(ring);
1067 error->tail[ring->id] = I915_READ_TAIL(ring);
7e3b8737
DV		 1068
1069 error->cpu_ring_head[ring->id] = ring->head;
1070 error->cpu_ring_tail[ring->id] = ring->tail;
d27b1e0e
DV		 1071}
1072
52d39a21
CW		 1073static void i915_gem_record_rings(struct drm_device *dev,
1074 struct drm_i915_error_state *error)
1075{
1076 struct drm_i915_private *dev_priv = dev->dev_private;
1077 struct drm_i915_gem_request *request;
1078 int i, count;
1079
1080 for (i = 0; i < I915_NUM_RINGS; i++) {
1081 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1082
1083 if (ring->obj == NULL)
1084 continue;
1085
1086 i915_record_ring_state(dev, error, ring);
1087
1088 error->ring[i].batchbuffer =
1089 i915_error_first_batchbuffer(dev_priv, ring);
1090
1091 error->ring[i].ringbuffer =
1092 i915_error_object_create(dev_priv, ring->obj);
1093
1094 count = 0;
1095 list_for_each_entry(request, &ring->request_list, list)
1096 count++;
1097
1098 error->ring[i].num_requests = count;
1099 error->ring[i].requests =
1100 kmalloc(count*sizeof(struct drm_i915_error_request),
1101 GFP_ATOMIC);
1102 if (error->ring[i].requests == NULL) {
1103 error->ring[i].num_requests = 0;
1104 continue;
1105 }
1106
1107 count = 0;
1108 list_for_each_entry(request, &ring->request_list, list) {
1109 struct drm_i915_error_request *erq;
1110
1111 erq = &error->ring[i].requests[count++];
1112 erq->seqno = request->seqno;
1113 erq->jiffies = request->emitted_jiffies;
ee4f42b1 1114 erq->tail = request->tail;
52d39a21
CW		 1115 }
1116 }
1117}
1118
8a905236
JB		 1119/**
1120 * i915_capture_error_state - capture an error record for later analysis
1121 * @dev: drm device
1122 *
1123 * Should be called when an error is detected (either a hang or an error
1124 * interrupt) to capture error state from the time of the error. Fills
1125 * out a structure which becomes available in debugfs for user level tools
1126 * to pick up.
1127 */
63eeaf38
JB		 1128static void i915_capture_error_state(struct drm_device *dev)
1129{
1130 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1131 struct drm_i915_gem_object *obj;
63eeaf38
JB		 1132 struct drm_i915_error_state *error;
1133 unsigned long flags;
9db4a9c7 1134 int i, pipe;
63eeaf38
JB		 1135
1136 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1137 error = dev_priv->first_error;
1138 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
1139 if (error)
1140 return;
63eeaf38 1141
9db4a9c7 1142 /* Account for pipe specific data like PIPE*STAT */
33f3f518 1143 error = kzalloc(sizeof(*error), GFP_ATOMIC);
63eeaf38 1144 if (!error) {
9df30794
CW		 1145 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1146 return;
63eeaf38
JB		 1147 }
1148
b6f7833b
CW		 1149 DRM_INFO("capturing error event; look for more information in /debug/dri/%d/i915_error_state\n",
1150 dev->primary->index);
2fa772f3 1151
63eeaf38
JB		 1152 error->eir = I915_READ(EIR);
1153 error->pgtbl_er = I915_READ(PGTBL_ER);
9db4a9c7
JB		 1154 for_each_pipe(pipe)
1155 error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
d27b1e0e 1156
33f3f518 1157 if (INTEL_INFO(dev)->gen >= 6) {
f406839f 1158 error->error = I915_READ(ERROR_GEN6);
33f3f518
DV		 1159 error->done_reg = I915_READ(DONE_REG);
1160 }
d27b1e0e 1161
748ebc60 1162 i915_gem_record_fences(dev, error);
52d39a21 1163 i915_gem_record_rings(dev, error);
9df30794 1164
c724e8a9 1165 /* Record buffers on the active and pinned lists. */
9df30794 1166 error->active_bo = NULL;
c724e8a9 1167 error->pinned_bo = NULL;
9df30794 1168
bcfb2e28
CW		 1169 i = 0;
1170 list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1171 i++;
1172 error->active_bo_count = i;
1b50247a
CW		 1173 list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list)
1174 if (obj->pin_count)
1175 i++;
bcfb2e28 1176 error->pinned_bo_count = i - error->active_bo_count;
c724e8a9 1177
8e934dbf
CW		 1178 error->active_bo = NULL;
1179 error->pinned_bo = NULL;
bcfb2e28
CW		 1180 if (i) {
1181 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
9df30794 1182 GFP_ATOMIC);
c724e8a9
CW		 1183 if (error->active_bo)
1184 error->pinned_bo =
1185 error->active_bo + error->active_bo_count;
9df30794
CW		 1186 }
1187
c724e8a9
CW		 1188 if (error->active_bo)
1189 error->active_bo_count =
1b50247a
CW		 1190 capture_active_bo(error->active_bo,
1191 error->active_bo_count,
1192 &dev_priv->mm.active_list);
c724e8a9
CW		 1193
1194 if (error->pinned_bo)
1195 error->pinned_bo_count =
1b50247a
CW		 1196 capture_pinned_bo(error->pinned_bo,
1197 error->pinned_bo_count,
1198 &dev_priv->mm.gtt_list);
c724e8a9 1199
9df30794
CW		 1200 do_gettimeofday(&error->time);
1201
6ef3d427 1202 error->overlay = intel_overlay_capture_error_state(dev);
c4a1d9e4 1203 error->display = intel_display_capture_error_state(dev);
6ef3d427 1204
9df30794
CW		 1205 spin_lock_irqsave(&dev_priv->error_lock, flags);
1206 if (dev_priv->first_error == NULL) {
1207 dev_priv->first_error = error;
1208 error = NULL;
1209 }
63eeaf38 1210 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1211
1212 if (error)
1213 i915_error_state_free(dev, error);
1214}
1215
1216void i915_destroy_error_state(struct drm_device *dev)
1217{
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 struct drm_i915_error_state *error;
6dc0e816 1220 unsigned long flags;
9df30794 1221
6dc0e816 1222 spin_lock_irqsave(&dev_priv->error_lock, flags);
9df30794
CW		 1223 error = dev_priv->first_error;
1224 dev_priv->first_error = NULL;
6dc0e816 1225 spin_unlock_irqrestore(&dev_priv->error_lock, flags);
9df30794
CW		 1226
1227 if (error)
1228 i915_error_state_free(dev, error);
63eeaf38 1229}
3bd3c932
CW		 1230#else
1231#define i915_capture_error_state(x)
1232#endif
63eeaf38 1233
35aed2e6 1234static void i915_report_and_clear_eir(struct drm_device *dev)
8a905236
JB		 1235{
1236 struct drm_i915_private *dev_priv = dev->dev_private;
1237 u32 eir = I915_READ(EIR);
9db4a9c7 1238 int pipe;
8a905236 1239
35aed2e6
CW		 1240 if (!eir)
1241 return;
8a905236 1242
a70491cc 1243 pr_err("render error detected, EIR: 0x%08x\n", eir);
8a905236
JB		 1244
1245 if (IS_G4X(dev)) {
1246 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1247 u32 ipeir = I915_READ(IPEIR_I965);
1248
a70491cc
JP		 1249 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1250 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1251 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1252 I915_READ(INSTDONE_I965));
a70491cc
JP		 1253 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1254 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1255 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1256 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1257 POSTING_READ(IPEIR_I965);
8a905236
JB		 1258 }
1259 if (eir & GM45_ERROR_PAGE_TABLE) {
1260 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1261 pr_err("page table error\n");
1262 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1263 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1264 POSTING_READ(PGTBL_ER);
8a905236
JB		 1265 }
1266 }
1267
a6c45cf0 1268 if (!IS_GEN2(dev)) {
8a905236
JB		 1269 if (eir & I915_ERROR_PAGE_TABLE) {
1270 u32 pgtbl_err = I915_READ(PGTBL_ER);
a70491cc
JP		 1271 pr_err("page table error\n");
1272 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
8a905236 1273 I915_WRITE(PGTBL_ER, pgtbl_err);
3143a2bf 1274 POSTING_READ(PGTBL_ER);
8a905236
JB		 1275 }
1276 }
1277
1278 if (eir & I915_ERROR_MEMORY_REFRESH) {
a70491cc 1279 pr_err("memory refresh error:\n");
9db4a9c7 1280 for_each_pipe(pipe)
a70491cc 1281 pr_err("pipe %c stat: 0x%08x\n",
9db4a9c7 1282 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
8a905236
JB		 1283 /* pipestat has already been acked */
1284 }
1285 if (eir & I915_ERROR_INSTRUCTION) {
a70491cc
JP		 1286 pr_err("instruction error\n");
1287 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
a6c45cf0 1288 if (INTEL_INFO(dev)->gen < 4) {
8a905236
JB		 1289 u32 ipeir = I915_READ(IPEIR);
1290
a70491cc
JP		 1291 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
1292 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
1293 pr_err(" INSTDONE: 0x%08x\n", I915_READ(INSTDONE));
1294 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
8a905236 1295 I915_WRITE(IPEIR, ipeir);
3143a2bf 1296 POSTING_READ(IPEIR);
8a905236
JB		 1297 } else {
1298 u32 ipeir = I915_READ(IPEIR_I965);
1299
a70491cc
JP		 1300 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1301 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1302 pr_err(" INSTDONE: 0x%08x\n",
8a905236 1303 I915_READ(INSTDONE_I965));
a70491cc
JP		 1304 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
1305 pr_err(" INSTDONE1: 0x%08x\n", I915_READ(INSTDONE1));
1306 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
8a905236 1307 I915_WRITE(IPEIR_I965, ipeir);
3143a2bf 1308 POSTING_READ(IPEIR_I965);
8a905236
JB		 1309 }
1310 }
1311
1312 I915_WRITE(EIR, eir);
3143a2bf 1313 POSTING_READ(EIR);
8a905236
JB		 1314 eir = I915_READ(EIR);
1315 if (eir) {
1316 /*
1317 * some errors might have become stuck,
1318 * mask them.
1319 */
1320 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1321 I915_WRITE(EMR, I915_READ(EMR) | eir);
1322 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1323 }
35aed2e6
CW		 1324}
1325
1326/**
1327 * i915_handle_error - handle an error interrupt
1328 * @dev: drm device
1329 *
1330 * Do some basic checking of regsiter state at error interrupt time and
1331 * dump it to the syslog. Also call i915_capture_error_state() to make
1332 * sure we get a record and make it available in debugfs. Fire a uevent
1333 * so userspace knows something bad happened (should trigger collection
1334 * of a ring dump etc.).
1335 */
527f9e90 1336void i915_handle_error(struct drm_device *dev, bool wedged)
35aed2e6
CW		 1337{
1338 struct drm_i915_private *dev_priv = dev->dev_private;
1339
1340 i915_capture_error_state(dev);
1341 i915_report_and_clear_eir(dev);
8a905236 1342
ba1234d1 1343 if (wedged) {
30dbf0c0 1344 INIT_COMPLETION(dev_priv->error_completion);
ba1234d1
BG		 1345 atomic_set(&dev_priv->mm.wedged, 1);
1346
11ed50ec
BG		 1347 /*
1348 * Wakeup waiting processes so they don't hang
1349 */
1ec14ad3 1350 wake_up_all(&dev_priv->ring[RCS].irq_queue);
f787a5f5 1351 if (HAS_BSD(dev))
1ec14ad3 1352 wake_up_all(&dev_priv->ring[VCS].irq_queue);
549f7365 1353 if (HAS_BLT(dev))
1ec14ad3 1354 wake_up_all(&dev_priv->ring[BCS].irq_queue);
11ed50ec
BG		 1355 }
1356
9c9fe1f8 1357 queue_work(dev_priv->wq, &dev_priv->error_work);
8a905236
JB		 1358}
1359
4e5359cd
SF		 1360static void i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1361{
1362 drm_i915_private_t *dev_priv = dev->dev_private;
1363 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 1365 struct drm_i915_gem_object *obj;
4e5359cd
SF		 1366 struct intel_unpin_work *work;
1367 unsigned long flags;
1368 bool stall_detected;
1369
1370 /* Ignore early vblank irqs */
1371 if (intel_crtc == NULL)
1372 return;
1373
1374 spin_lock_irqsave(&dev->event_lock, flags);
1375 work = intel_crtc->unpin_work;
1376
1377 if (work == NULL || work->pending || !work->enable_stall_check) {
1378 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1379 spin_unlock_irqrestore(&dev->event_lock, flags);
1380 return;
1381 }
1382
1383 /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
05394f39 1384 obj = work->pending_flip_obj;
a6c45cf0 1385 if (INTEL_INFO(dev)->gen >= 4) {
9db4a9c7 1386 int dspsurf = DSPSURF(intel_crtc->plane);
446f2545
AR		 1387 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1388 obj->gtt_offset;
4e5359cd 1389 } else {
9db4a9c7 1390 int dspaddr = DSPADDR(intel_crtc->plane);
05394f39 1391 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
01f2c773 1392 crtc->y * crtc->fb->pitches[0] +
4e5359cd
SF		 1393 crtc->x * crtc->fb->bits_per_pixel/8);
1394 }
1395
1396 spin_unlock_irqrestore(&dev->event_lock, flags);
1397
1398 if (stall_detected) {
1399 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1400 intel_prepare_page_flip(dev, intel_crtc->plane);
1401 }
1402}
1403
af6061af 1404static int i915_emit_irq(struct drm_device * dev)
1da177e4
LT		 1405{
1406 drm_i915_private_t *dev_priv = dev->dev_private;
7c1c2871 1407 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4
LT		 1408
1409 i915_kernel_lost_context(dev);
1410
44d98a61 1411 DRM_DEBUG_DRIVER("\n");
1da177e4 1412
c99b058f 1413 dev_priv->counter++;
c29b669c 1414 if (dev_priv->counter > 0x7FFFFFFFUL)
c99b058f 1415 dev_priv->counter = 1;
7c1c2871
DA		 1416 if (master_priv->sarea_priv)
1417 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
c29b669c 1418
e1f99ce6
CW		 1419 if (BEGIN_LP_RING(4) == 0) {
1420 OUT_RING(MI_STORE_DWORD_INDEX);
1421 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1422 OUT_RING(dev_priv->counter);
1423 OUT_RING(MI_USER_INTERRUPT);
1424 ADVANCE_LP_RING();
1425 }
bc5f4523 1426
c29b669c 1427 return dev_priv->counter;
1da177e4
LT		 1428}
1429
84b1fd10 1430static int i915_wait_irq(struct drm_device * dev, int irq_nr)
1da177e4
LT		 1431{
1432 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
7c1c2871 1433 struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1da177e4 1434 int ret = 0;
1ec14ad3 1435 struct intel_ring_buffer *ring = LP_RING(dev_priv);
1da177e4 1436
44d98a61 1437 DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
1da177e4
LT		 1438 READ_BREADCRUMB(dev_priv));
1439
ed4cb414 1440 if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
7c1c2871
DA		 1441 if (master_priv->sarea_priv)
1442 master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
1da177e4 1443 return 0;
ed4cb414 1444 }
1da177e4 1445
7c1c2871
DA		 1446 if (master_priv->sarea_priv)
1447 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1da177e4 1448
b13c2b96
CW		 1449 if (ring->irq_get(ring)) {
1450 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
1451 READ_BREADCRUMB(dev_priv) >= irq_nr);
1452 ring->irq_put(ring);
5a9a8d1a
CW		 1453 } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
1454 ret = -EBUSY;
1da177e4 1455
20caafa6 1456 if (ret == -EBUSY) {
3e684eae 1457 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
1da177e4
LT		 1458 READ_BREADCRUMB(dev_priv), (int)dev_priv->counter);
1459 }
1460
af6061af
DA		 1461 return ret;
1462}
1463
1da177e4
LT		 1464/* Needs the lock as it touches the ring.
1465 */
c153f45f
EA		 1466int i915_irq_emit(struct drm_device *dev, void *data,
1467 struct drm_file *file_priv)
1da177e4 1468{
1da177e4 1469 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1470 drm_i915_irq_emit_t *emit = data;
1da177e4
LT		 1471 int result;
1472
cd9d4e9f
DV		 1473 if (drm_core_check_feature(dev, DRIVER_MODESET))
1474 return -ENODEV;
1475
1ec14ad3 1476 if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
3e684eae 1477 DRM_ERROR("called with no initialization\n");
20caafa6 1478 return -EINVAL;
1da177e4 1479 }
299eb93c
EA		 1480
1481 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
1482
546b0974 1483 mutex_lock(&dev->struct_mutex);
1da177e4 1484 result = i915_emit_irq(dev);
546b0974 1485 mutex_unlock(&dev->struct_mutex);
1da177e4 1486
c153f45f 1487 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
1da177e4 1488 DRM_ERROR("copy_to_user\n");
20caafa6 1489 return -EFAULT;
1da177e4
LT		 1490 }
1491
1492 return 0;
1493}
1494
1495/* Doesn't need the hardware lock.
1496 */
c153f45f
EA		 1497int i915_irq_wait(struct drm_device *dev, void *data,
1498 struct drm_file *file_priv)
1da177e4 1499{
1da177e4 1500 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1501 drm_i915_irq_wait_t *irqwait = data;
1da177e4 1502
cd9d4e9f
DV		 1503 if (drm_core_check_feature(dev, DRIVER_MODESET))
1504 return -ENODEV;
1505
1da177e4 1506 if (!dev_priv) {
3e684eae 1507 DRM_ERROR("called with no initialization\n");
20caafa6 1508 return -EINVAL;
1da177e4
LT		 1509 }
1510
c153f45f 1511 return i915_wait_irq(dev, irqwait->irq_seq);
1da177e4
LT		 1512}
1513
42f52ef8
KP		 1514/* Called from drm generic code, passed 'crtc' which
1515 * we use as a pipe index
1516 */
f71d4af4 1517static int i915_enable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1518{
1519 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1520 unsigned long irqflags;
71e0ffa5 1521
5eddb70b 1522 if (!i915_pipe_enabled(dev, pipe))
71e0ffa5 1523 return -EINVAL;
0a3e67a4 1524
1ec14ad3 1525 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
f796cf8f 1526 if (INTEL_INFO(dev)->gen >= 4)
7c463586
KP		 1527 i915_enable_pipestat(dev_priv, pipe,
1528 PIPE_START_VBLANK_INTERRUPT_ENABLE);
e9d21d7f 1529 else
7c463586
KP		 1530 i915_enable_pipestat(dev_priv, pipe,
1531 PIPE_VBLANK_INTERRUPT_ENABLE);
8692d00e
CW		 1532
1533 /* maintain vblank delivery even in deep C-states */
1534 if (dev_priv->info->gen == 3)
6b26c86d 1535 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1ec14ad3 1536 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
8692d00e 1537
0a3e67a4
JB		 1538 return 0;
1539}
1540
f71d4af4 1541static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1542{
1543 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1544 unsigned long irqflags;
1545
1546 if (!i915_pipe_enabled(dev, pipe))
1547 return -EINVAL;
1548
1549 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1550 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1551 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
f796cf8f
JB		 1552 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1553
1554 return 0;
1555}
1556
f71d4af4 1557static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1558{
1559 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1560 unsigned long irqflags;
1561
1562 if (!i915_pipe_enabled(dev, pipe))
1563 return -EINVAL;
1564
1565 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1566 ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1567 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1568 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1569
1570 return 0;
1571}
1572
7e231dbe
JB		 1573static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1574{
1575 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1576 unsigned long irqflags;
1577 u32 dpfl, imr;
1578
1579 if (!i915_pipe_enabled(dev, pipe))
1580 return -EINVAL;
1581
1582 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1583 dpfl = I915_READ(VLV_DPFLIPSTAT);
1584 imr = I915_READ(VLV_IMR);
1585 if (pipe == 0) {
1586 dpfl |= PIPEA_VBLANK_INT_EN;
1587 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1588 } else {
1589 dpfl |= PIPEA_VBLANK_INT_EN;
1590 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1591 }
1592 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1593 I915_WRITE(VLV_IMR, imr);
1594 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1595
1596 return 0;
1597}
1598
42f52ef8
KP		 1599/* Called from drm generic code, passed 'crtc' which
1600 * we use as a pipe index
1601 */
f71d4af4 1602static void i915_disable_vblank(struct drm_device *dev, int pipe)
0a3e67a4
JB		 1603{
1604 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
e9d21d7f 1605 unsigned long irqflags;
0a3e67a4 1606
1ec14ad3 1607 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
8692d00e 1608 if (dev_priv->info->gen == 3)
6b26c86d 1609 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
8692d00e 1610
f796cf8f
JB		 1611 i915_disable_pipestat(dev_priv, pipe,
1612 PIPE_VBLANK_INTERRUPT_ENABLE |
1613 PIPE_START_VBLANK_INTERRUPT_ENABLE);
1614 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1615}
1616
f71d4af4 1617static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
f796cf8f
JB		 1618{
1619 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1620 unsigned long irqflags;
1621
1622 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1623 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
0206e353 1624 DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1ec14ad3 1625 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
0a3e67a4
JB		 1626}
1627
f71d4af4 1628static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
b1f14ad0
JB		 1629{
1630 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1631 unsigned long irqflags;
1632
1633 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1634 ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1635 DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
1636 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1637}
1638
7e231dbe
JB		 1639static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1640{
1641 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1642 unsigned long irqflags;
1643 u32 dpfl, imr;
1644
1645 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1646 dpfl = I915_READ(VLV_DPFLIPSTAT);
1647 imr = I915_READ(VLV_IMR);
1648 if (pipe == 0) {
1649 dpfl &= ~PIPEA_VBLANK_INT_EN;
1650 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1651 } else {
1652 dpfl &= ~PIPEB_VBLANK_INT_EN;
1653 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1654 }
1655 I915_WRITE(VLV_IMR, imr);
1656 I915_WRITE(VLV_DPFLIPSTAT, dpfl);
1657 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1658}
1659
1660
702880f2
DA		 1661/* Set the vblank monitor pipe
1662 */
c153f45f
EA		 1663int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1664 struct drm_file *file_priv)
702880f2 1665{
702880f2 1666 drm_i915_private_t *dev_priv = dev->dev_private;
702880f2 1667
cd9d4e9f
DV		 1668 if (drm_core_check_feature(dev, DRIVER_MODESET))
1669 return -ENODEV;
1670
702880f2 1671 if (!dev_priv) {
3e684eae 1672 DRM_ERROR("called with no initialization\n");
20caafa6 1673 return -EINVAL;
702880f2
DA		 1674 }
1675
5b51694a 1676 return 0;
702880f2
DA		 1677}
1678
c153f45f
EA		 1679int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1680 struct drm_file *file_priv)
702880f2 1681{
702880f2 1682 drm_i915_private_t *dev_priv = dev->dev_private;
c153f45f 1683 drm_i915_vblank_pipe_t *pipe = data;
702880f2 1684
cd9d4e9f
DV		 1685 if (drm_core_check_feature(dev, DRIVER_MODESET))
1686 return -ENODEV;
1687
702880f2 1688 if (!dev_priv) {
3e684eae 1689 DRM_ERROR("called with no initialization\n");
20caafa6 1690 return -EINVAL;
702880f2
DA		 1691 }
1692
0a3e67a4 1693 pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
c153f45f 1694
702880f2
DA		 1695 return 0;
1696}
1697
a6b54f3f
MD		 1698/**
1699 * Schedule buffer swap at given vertical blank.
1700 */
c153f45f
EA		 1701int i915_vblank_swap(struct drm_device *dev, void *data,
1702 struct drm_file *file_priv)
a6b54f3f 1703{
bd95e0a4
EA		 1704 /* The delayed swap mechanism was fundamentally racy, and has been
1705 * removed. The model was that the client requested a delayed flip/swap
1706 * from the kernel, then waited for vblank before continuing to perform
1707 * rendering. The problem was that the kernel might wake the client
1708 * up before it dispatched the vblank swap (since the lock has to be
1709 * held while touching the ringbuffer), in which case the client would
1710 * clear and start the next frame before the swap occurred, and
1711 * flicker would occur in addition to likely missing the vblank.
1712 *
1713 * In the absence of this ioctl, userland falls back to a correct path
1714 * of waiting for a vblank, then dispatching the swap on its own.
1715 * Context switching to userland and back is plenty fast enough for
1716 * meeting the requirements of vblank swapping.
0a3e67a4 1717 */
bd95e0a4 1718 return -EINVAL;
a6b54f3f
MD		 1719}
1720
893eead0
CW		 1721static u32
1722ring_last_seqno(struct intel_ring_buffer *ring)
852835f3 1723{
893eead0
CW		 1724 return list_entry(ring->request_list.prev,
1725 struct drm_i915_gem_request, list)->seqno;
1726}
1727
1728static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1729{
1730 if (list_empty(&ring->request_list) ||
1731 i915_seqno_passed(ring->get_seqno(ring), ring_last_seqno(ring))) {
1732 /* Issue a wake-up to catch stuck h/w. */
b2223497 1733 if (ring->waiting_seqno && waitqueue_active(&ring->irq_queue)) {
893eead0
CW		 1734 DRM_ERROR("Hangcheck timer elapsed... %s idle [waiting on %d, at %d], missed IRQ?\n",
1735 ring->name,
b2223497 1736 ring->waiting_seqno,
893eead0
CW		 1737 ring->get_seqno(ring));
1738 wake_up_all(&ring->irq_queue);
1739 *err = true;
1740 }
1741 return true;
1742 }
1743 return false;
f65d9421
BG		 1744}
1745
1ec14ad3
CW		 1746static bool kick_ring(struct intel_ring_buffer *ring)
1747{
1748 struct drm_device *dev = ring->dev;
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 u32 tmp = I915_READ_CTL(ring);
1751 if (tmp & RING_WAIT) {
1752 DRM_ERROR("Kicking stuck wait on %s\n",
1753 ring->name);
1754 I915_WRITE_CTL(ring, tmp);
1755 return true;
1756 }
1ec14ad3
CW		 1757 return false;
1758}
1759
d1e61e7f
CW		 1760static bool i915_hangcheck_hung(struct drm_device *dev)
1761{
1762 drm_i915_private_t *dev_priv = dev->dev_private;
1763
1764 if (dev_priv->hangcheck_count++ > 1) {
1765 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
1766 i915_handle_error(dev, true);
1767
1768 if (!IS_GEN2(dev)) {
1769 /* Is the chip hanging on a WAIT_FOR_EVENT?
1770 * If so we can simply poke the RB_WAIT bit
1771 * and break the hang. This should work on
1772 * all but the second generation chipsets.
1773 */
1774 if (kick_ring(&dev_priv->ring[RCS]))
1775 return false;
1776
1777 if (HAS_BSD(dev) && kick_ring(&dev_priv->ring[VCS]))
1778 return false;
1779
1780 if (HAS_BLT(dev) && kick_ring(&dev_priv->ring[BCS]))
1781 return false;
1782 }
1783
1784 return true;
1785 }
1786
1787 return false;
1788}
1789
f65d9421
BG		 1790/**
1791 * This is called when the chip hasn't reported back with completed
1792 * batchbuffers in a long time. The first time this is called we simply record
1793 * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
1794 * again, we assume the chip is wedged and try to fix it.
1795 */
1796void i915_hangcheck_elapsed(unsigned long data)
1797{
1798 struct drm_device *dev = (struct drm_device *)data;
1799 drm_i915_private_t *dev_priv = dev->dev_private;
097354eb 1800 uint32_t acthd, instdone, instdone1, acthd_bsd, acthd_blt;
893eead0
CW		 1801 bool err = false;
1802
3e0dc6b0
BW		 1803 if (!i915_enable_hangcheck)
1804 return;
1805
893eead0 1806 /* If all work is done then ACTHD clearly hasn't advanced. */
1ec14ad3
CW		 1807 if (i915_hangcheck_ring_idle(&dev_priv->ring[RCS], &err) &&
1808 i915_hangcheck_ring_idle(&dev_priv->ring[VCS], &err) &&
1809 i915_hangcheck_ring_idle(&dev_priv->ring[BCS], &err)) {
d1e61e7f
CW		 1810 if (err) {
1811 if (i915_hangcheck_hung(dev))
1812 return;
1813
893eead0 1814 goto repeat;
d1e61e7f
CW		 1815 }
1816
1817 dev_priv->hangcheck_count = 0;
893eead0
CW		 1818 return;
1819 }
b9201c14 1820
a6c45cf0 1821 if (INTEL_INFO(dev)->gen < 4) {
cbb465e7
CW		 1822 instdone = I915_READ(INSTDONE);
1823 instdone1 = 0;
1824 } else {
cbb465e7
CW		 1825 instdone = I915_READ(INSTDONE_I965);
1826 instdone1 = I915_READ(INSTDONE1);
1827 }
097354eb
DV		 1828 acthd = intel_ring_get_active_head(&dev_priv->ring[RCS]);
1829 acthd_bsd = HAS_BSD(dev) ?
1830 intel_ring_get_active_head(&dev_priv->ring[VCS]) : 0;
1831 acthd_blt = HAS_BLT(dev) ?
1832 intel_ring_get_active_head(&dev_priv->ring[BCS]) : 0;
f65d9421 1833
cbb465e7 1834 if (dev_priv->last_acthd == acthd &&
097354eb
DV		 1835 dev_priv->last_acthd_bsd == acthd_bsd &&
1836 dev_priv->last_acthd_blt == acthd_blt &&
cbb465e7
CW		 1837 dev_priv->last_instdone == instdone &&
1838 dev_priv->last_instdone1 == instdone1) {
d1e61e7f 1839 if (i915_hangcheck_hung(dev))
cbb465e7 1840 return;
cbb465e7
CW		 1841 } else {
1842 dev_priv->hangcheck_count = 0;
1843
1844 dev_priv->last_acthd = acthd;
097354eb
DV		 1845 dev_priv->last_acthd_bsd = acthd_bsd;
1846 dev_priv->last_acthd_blt = acthd_blt;
cbb465e7
CW		 1847 dev_priv->last_instdone = instdone;
1848 dev_priv->last_instdone1 = instdone1;
1849 }
f65d9421 1850
893eead0 1851repeat:
f65d9421 1852 /* Reset timer case chip hangs without another request being added */
b3b079db
CW		 1853 mod_timer(&dev_priv->hangcheck_timer,
1854 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421
BG		 1855}
1856
1da177e4
LT		 1857/* drm_dma.h hooks
1858*/
f71d4af4 1859static void ironlake_irq_preinstall(struct drm_device *dev)
036a4a7d
ZW		 1860{
1861 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1862
4697995b
JB		 1863 atomic_set(&dev_priv->irq_received, 0);
1864
4697995b 1865
036a4a7d 1866 I915_WRITE(HWSTAM, 0xeffe);
bdfcdb63 1867
036a4a7d
ZW		 1868 /* XXX hotplug from PCH */
1869
1870 I915_WRITE(DEIMR, 0xffffffff);
1871 I915_WRITE(DEIER, 0x0);
3143a2bf 1872 POSTING_READ(DEIER);
036a4a7d
ZW		 1873
1874 /* and GT */
1875 I915_WRITE(GTIMR, 0xffffffff);
1876 I915_WRITE(GTIER, 0x0);
3143a2bf 1877 POSTING_READ(GTIER);
c650156a
ZW		 1878
1879 /* south display irq */
1880 I915_WRITE(SDEIMR, 0xffffffff);
1881 I915_WRITE(SDEIER, 0x0);
3143a2bf 1882 POSTING_READ(SDEIER);
036a4a7d
ZW		 1883}
1884
7e231dbe
JB		 1885static void valleyview_irq_preinstall(struct drm_device *dev)
1886{
1887 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1888 int pipe;
1889
1890 atomic_set(&dev_priv->irq_received, 0);
1891
7e231dbe
JB		 1892 /* VLV magic */
1893 I915_WRITE(VLV_IMR, 0);
1894 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
1895 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
1896 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
1897
7e231dbe
JB		 1898 /* and GT */
1899 I915_WRITE(GTIIR, I915_READ(GTIIR));
1900 I915_WRITE(GTIIR, I915_READ(GTIIR));
1901 I915_WRITE(GTIMR, 0xffffffff);
1902 I915_WRITE(GTIER, 0x0);
1903 POSTING_READ(GTIER);
1904
1905 I915_WRITE(DPINVGTT, 0xff);
1906
1907 I915_WRITE(PORT_HOTPLUG_EN, 0);
1908 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
1909 for_each_pipe(pipe)
1910 I915_WRITE(PIPESTAT(pipe), 0xffff);
1911 I915_WRITE(VLV_IIR, 0xffffffff);
1912 I915_WRITE(VLV_IMR, 0xffffffff);
1913 I915_WRITE(VLV_IER, 0x0);
1914 POSTING_READ(VLV_IER);
1915}
1916
7fe0b973
KP		 1917/*
1918 * Enable digital hotplug on the PCH, and configure the DP short pulse
1919 * duration to 2ms (which is the minimum in the Display Port spec)
1920 *
1921 * This register is the same on all known PCH chips.
1922 */
1923
1924static void ironlake_enable_pch_hotplug(struct drm_device *dev)
1925{
1926 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1927 u32 hotplug;
1928
1929 hotplug = I915_READ(PCH_PORT_HOTPLUG);
1930 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
1931 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
1932 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
1933 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
1934 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
1935}
1936
f71d4af4 1937static int ironlake_irq_postinstall(struct drm_device *dev)
036a4a7d
ZW		 1938{
1939 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1940 /* enable kind of interrupts always enabled */
013d5aa2
JB		 1941 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
1942 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE;
1ec14ad3 1943 u32 render_irqs;
2d7b8366 1944 u32 hotplug_mask;
036a4a7d 1945
4697995b 1946 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
1ec14ad3 1947 dev_priv->irq_mask = ~display_mask;
036a4a7d
ZW		 1948
1949 /* should always can generate irq */
1950 I915_WRITE(DEIIR, I915_READ(DEIIR));
1ec14ad3
CW		 1951 I915_WRITE(DEIMR, dev_priv->irq_mask);
1952 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
3143a2bf 1953 POSTING_READ(DEIER);
036a4a7d 1954
1ec14ad3 1955 dev_priv->gt_irq_mask = ~0;
036a4a7d
ZW		 1956
1957 I915_WRITE(GTIIR, I915_READ(GTIIR));
1ec14ad3 1958 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
881f47b6 1959
1ec14ad3
CW		 1960 if (IS_GEN6(dev))
1961 render_irqs =
1962 GT_USER_INTERRUPT |
e2a1e2f0
BW		 1963 GEN6_BSD_USER_INTERRUPT |
1964 GEN6_BLITTER_USER_INTERRUPT;
1ec14ad3
CW		 1965 else
1966 render_irqs =
88f23b8f 1967 GT_USER_INTERRUPT |
c6df541c 1968 GT_PIPE_NOTIFY |
1ec14ad3
CW		 1969 GT_BSD_USER_INTERRUPT;
1970 I915_WRITE(GTIER, render_irqs);
3143a2bf 1971 POSTING_READ(GTIER);
036a4a7d 1972
2d7b8366 1973 if (HAS_PCH_CPT(dev)) {
9035a97a
CW		 1974 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
1975 SDE_PORTB_HOTPLUG_CPT |
1976 SDE_PORTC_HOTPLUG_CPT |
1977 SDE_PORTD_HOTPLUG_CPT);
2d7b8366 1978 } else {
9035a97a
CW		 1979 hotplug_mask = (SDE_CRT_HOTPLUG |
1980 SDE_PORTB_HOTPLUG |
1981 SDE_PORTC_HOTPLUG |
1982 SDE_PORTD_HOTPLUG |
1983 SDE_AUX_MASK);
2d7b8366
YL		 1984 }
1985
1ec14ad3 1986 dev_priv->pch_irq_mask = ~hotplug_mask;
c650156a
ZW		 1987
1988 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
1ec14ad3
CW		 1989 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
1990 I915_WRITE(SDEIER, hotplug_mask);
3143a2bf 1991 POSTING_READ(SDEIER);
c650156a 1992
7fe0b973
KP		 1993 ironlake_enable_pch_hotplug(dev);
1994
f97108d1
JB		 1995 if (IS_IRONLAKE_M(dev)) {
1996 /* Clear & enable PCU event interrupts */
1997 I915_WRITE(DEIIR, DE_PCU_EVENT);
1998 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
1999 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2000 }
2001
036a4a7d
ZW		 2002 return 0;
2003}
2004
f71d4af4 2005static int ivybridge_irq_postinstall(struct drm_device *dev)
b1f14ad0
JB		 2006{
2007 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2008 /* enable kind of interrupts always enabled */
2009 u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
2010 DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
2011 DE_PLANEB_FLIP_DONE_IVB;
2012 u32 render_irqs;
2013 u32 hotplug_mask;
2014
b1f14ad0
JB		 2015 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2016 dev_priv->irq_mask = ~display_mask;
2017
2018 /* should always can generate irq */
2019 I915_WRITE(DEIIR, I915_READ(DEIIR));
2020 I915_WRITE(DEIMR, dev_priv->irq_mask);
2021 I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
2022 DE_PIPEB_VBLANK_IVB);
2023 POSTING_READ(DEIER);
2024
2025 dev_priv->gt_irq_mask = ~0;
2026
2027 I915_WRITE(GTIIR, I915_READ(GTIIR));
2028 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2029
e2a1e2f0
BW		 2030 render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2031 GEN6_BLITTER_USER_INTERRUPT;
b1f14ad0
JB		 2032 I915_WRITE(GTIER, render_irqs);
2033 POSTING_READ(GTIER);
2034
2035 hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
2036 SDE_PORTB_HOTPLUG_CPT |
2037 SDE_PORTC_HOTPLUG_CPT |
2038 SDE_PORTD_HOTPLUG_CPT);
2039 dev_priv->pch_irq_mask = ~hotplug_mask;
2040
2041 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2042 I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
2043 I915_WRITE(SDEIER, hotplug_mask);
2044 POSTING_READ(SDEIER);
2045
7fe0b973
KP		 2046 ironlake_enable_pch_hotplug(dev);
2047
b1f14ad0
JB		 2048 return 0;
2049}
2050
7e231dbe
JB		 2051static int valleyview_irq_postinstall(struct drm_device *dev)
2052{
2053 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2054 u32 render_irqs;
2055 u32 enable_mask;
2056 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2057 u16 msid;
2058
2059 enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2060 enable_mask |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2061 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2062
2063 dev_priv->irq_mask = ~enable_mask;
2064
7e231dbe
JB		 2065 dev_priv->pipestat[0] = 0;
2066 dev_priv->pipestat[1] = 0;
2067
2068 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2069
2070 /* Hack for broken MSIs on VLV */
2071 pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2072 pci_read_config_word(dev->pdev, 0x98, &msid);
2073 msid &= 0xff; /* mask out delivery bits */
2074 msid |= (1<<14);
2075 pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2076
2077 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2078 I915_WRITE(VLV_IER, enable_mask);
2079 I915_WRITE(VLV_IIR, 0xffffffff);
2080 I915_WRITE(PIPESTAT(0), 0xffff);
2081 I915_WRITE(PIPESTAT(1), 0xffff);
2082 POSTING_READ(VLV_IER);
2083
2084 I915_WRITE(VLV_IIR, 0xffffffff);
2085 I915_WRITE(VLV_IIR, 0xffffffff);
2086
2087 render_irqs = GT_GEN6_BLT_FLUSHDW_NOTIFY_INTERRUPT |
2088 GT_GEN6_BLT_CS_ERROR_INTERRUPT |
e2a1e2f0 2089 GT_GEN6_BLT_USER_INTERRUPT |
7e231dbe
JB		 2090 GT_GEN6_BSD_USER_INTERRUPT |
2091 GT_GEN6_BSD_CS_ERROR_INTERRUPT |
2092 GT_GEN7_L3_PARITY_ERROR_INTERRUPT |
2093 GT_PIPE_NOTIFY |
2094 GT_RENDER_CS_ERROR_INTERRUPT |
2095 GT_SYNC_STATUS |
2096 GT_USER_INTERRUPT;
2097
2098 dev_priv->gt_irq_mask = ~render_irqs;
2099
2100 I915_WRITE(GTIIR, I915_READ(GTIIR));
2101 I915_WRITE(GTIIR, I915_READ(GTIIR));
2102 I915_WRITE(GTIMR, 0);
2103 I915_WRITE(GTIER, render_irqs);
2104 POSTING_READ(GTIER);
2105
2106 /* ack & enable invalid PTE error interrupts */
2107#if 0 /* FIXME: add support to irq handler for checking these bits */
2108 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2109 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2110#endif
2111
2112 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2113#if 0 /* FIXME: check register definitions; some have moved */
2114 /* Note HDMI and DP share bits */
2115 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2116 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2117 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2118 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2119 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2120 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2121 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2122 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2123 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2124 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2125 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2126 hotplug_en |= CRT_HOTPLUG_INT_EN;
2127 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2128 }
2129#endif
2130
2131 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2132
2133 return 0;
2134}
2135
7e231dbe
JB		 2136static void valleyview_irq_uninstall(struct drm_device *dev)
2137{
2138 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2139 int pipe;
2140
2141 if (!dev_priv)
2142 return;
2143
2144 dev_priv->vblank_pipe = 0;
2145
2146 for_each_pipe(pipe)
2147 I915_WRITE(PIPESTAT(pipe), 0xffff);
2148
2149 I915_WRITE(HWSTAM, 0xffffffff);
2150 I915_WRITE(PORT_HOTPLUG_EN, 0);
2151 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2152 for_each_pipe(pipe)
2153 I915_WRITE(PIPESTAT(pipe), 0xffff);
2154 I915_WRITE(VLV_IIR, 0xffffffff);
2155 I915_WRITE(VLV_IMR, 0xffffffff);
2156 I915_WRITE(VLV_IER, 0x0);
2157 POSTING_READ(VLV_IER);
2158}
2159
f71d4af4 2160static void ironlake_irq_uninstall(struct drm_device *dev)
036a4a7d
ZW		 2161{
2162 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
4697995b
JB		 2163
2164 if (!dev_priv)
2165 return;
2166
2167 dev_priv->vblank_pipe = 0;
2168
036a4a7d
ZW		 2169 I915_WRITE(HWSTAM, 0xffffffff);
2170
2171 I915_WRITE(DEIMR, 0xffffffff);
2172 I915_WRITE(DEIER, 0x0);
2173 I915_WRITE(DEIIR, I915_READ(DEIIR));
2174
2175 I915_WRITE(GTIMR, 0xffffffff);
2176 I915_WRITE(GTIER, 0x0);
2177 I915_WRITE(GTIIR, I915_READ(GTIIR));
192aac1f
KP		 2178
2179 I915_WRITE(SDEIMR, 0xffffffff);
2180 I915_WRITE(SDEIER, 0x0);
2181 I915_WRITE(SDEIIR, I915_READ(SDEIIR));
036a4a7d
ZW		 2182}
2183
a266c7d5 2184static void i8xx_irq_preinstall(struct drm_device * dev)
1da177e4
LT		 2185{
2186 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
9db4a9c7 2187 int pipe;
91e3738e 2188
a266c7d5 2189 atomic_set(&dev_priv->irq_received, 0);
5ca58282 2190
9db4a9c7
JB		 2191 for_each_pipe(pipe)
2192 I915_WRITE(PIPESTAT(pipe), 0);
a266c7d5
CW		 2193 I915_WRITE16(IMR, 0xffff);
2194 I915_WRITE16(IER, 0x0);
2195 POSTING_READ16(IER);
c2798b19
CW		 2196}
2197
2198static int i8xx_irq_postinstall(struct drm_device *dev)
2199{
2200 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2201
2202 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2203
2204 dev_priv->pipestat[0] = 0;
2205 dev_priv->pipestat[1] = 0;
2206
2207 I915_WRITE16(EMR,
2208 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2209
2210 /* Unmask the interrupts that we always want on. */
2211 dev_priv->irq_mask =
2212 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2213 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2214 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2215 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2216 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2217 I915_WRITE16(IMR, dev_priv->irq_mask);
2218
2219 I915_WRITE16(IER,
2220 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2221 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2222 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2223 I915_USER_INTERRUPT);
2224 POSTING_READ16(IER);
2225
2226 return 0;
2227}
2228
2229static irqreturn_t i8xx_irq_handler(DRM_IRQ_ARGS)
2230{
2231 struct drm_device *dev = (struct drm_device *) arg;
2232 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2233 struct drm_i915_master_private *master_priv;
2234 u16 iir, new_iir;
2235 u32 pipe_stats[2];
2236 unsigned long irqflags;
2237 int irq_received;
2238 int pipe;
2239 u16 flip_mask =
2240 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2241 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2242
2243 atomic_inc(&dev_priv->irq_received);
2244
2245 iir = I915_READ16(IIR);
2246 if (iir == 0)
2247 return IRQ_NONE;
2248
2249 while (iir & ~flip_mask) {
2250 /* Can't rely on pipestat interrupt bit in iir as it might
2251 * have been cleared after the pipestat interrupt was received.
2252 * It doesn't set the bit in iir again, but it still produces
2253 * interrupts (for non-MSI).
2254 */
2255 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2256 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2257 i915_handle_error(dev, false);
2258
2259 for_each_pipe(pipe) {
2260 int reg = PIPESTAT(pipe);
2261 pipe_stats[pipe] = I915_READ(reg);
2262
2263 /*
2264 * Clear the PIPE*STAT regs before the IIR
2265 */
2266 if (pipe_stats[pipe] & 0x8000ffff) {
2267 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2268 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2269 pipe_name(pipe));
2270 I915_WRITE(reg, pipe_stats[pipe]);
2271 irq_received = 1;
2272 }
2273 }
2274 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2275
2276 I915_WRITE16(IIR, iir & ~flip_mask);
2277 new_iir = I915_READ16(IIR); /* Flush posted writes */
2278
2279 if (dev->primary->master) {
2280 master_priv = dev->primary->master->driver_priv;
2281 if (master_priv->sarea_priv)
2282 master_priv->sarea_priv->last_dispatch =
2283 READ_BREADCRUMB(dev_priv);
2284 }
2285
2286 if (iir & I915_USER_INTERRUPT)
2287 notify_ring(dev, &dev_priv->ring[RCS]);
2288
2289 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2290 drm_handle_vblank(dev, 0)) {
2291 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT) {
2292 intel_prepare_page_flip(dev, 0);
2293 intel_finish_page_flip(dev, 0);
2294 flip_mask &= ~I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT;
2295 }
2296 }
2297
2298 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2299 drm_handle_vblank(dev, 1)) {
2300 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT) {
2301 intel_prepare_page_flip(dev, 1);
2302 intel_finish_page_flip(dev, 1);
2303 flip_mask &= ~I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2304 }
2305 }
2306
2307 iir = new_iir;
2308 }
2309
2310 return IRQ_HANDLED;
2311}
2312
2313static void i8xx_irq_uninstall(struct drm_device * dev)
2314{
2315 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2316 int pipe;
2317
2318 dev_priv->vblank_pipe = 0;
2319
2320 for_each_pipe(pipe) {
2321 /* Clear enable bits; then clear status bits */
2322 I915_WRITE(PIPESTAT(pipe), 0);
2323 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2324 }
2325 I915_WRITE16(IMR, 0xffff);
2326 I915_WRITE16(IER, 0x0);
2327 I915_WRITE16(IIR, I915_READ16(IIR));
2328}
2329
a266c7d5
CW		 2330static void i915_irq_preinstall(struct drm_device * dev)
2331{
2332 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2333 int pipe;
2334
2335 atomic_set(&dev_priv->irq_received, 0);
2336
2337 if (I915_HAS_HOTPLUG(dev)) {
2338 I915_WRITE(PORT_HOTPLUG_EN, 0);
2339 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2340 }
2341
2342 I915_WRITE(HWSTAM, 0xeffe);
2343 for_each_pipe(pipe)
2344 I915_WRITE(PIPESTAT(pipe), 0);
2345 I915_WRITE(IMR, 0xffffffff);
2346 I915_WRITE(IER, 0x0);
2347 POSTING_READ(IER);
2348}
2349
2350static int i915_irq_postinstall(struct drm_device *dev)
2351{
2352 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2353 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
2354 u32 error_mask;
2355
2356 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2357
2358 /* Unmask the interrupts that we always want on. */
2359 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
2360
2361 dev_priv->pipestat[0] = 0;
2362 dev_priv->pipestat[1] = 0;
2363
2364 if (I915_HAS_HOTPLUG(dev)) {
2365 /* Enable in IER... */
2366 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2367 /* and unmask in IMR */
2368 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2369 }
2370
2371 /*
2372 * Enable some error detection, note the instruction error mask
2373 * bit is reserved, so we leave it masked.
2374 */
2375 if (IS_G4X(dev)) {
2376 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2377 GM45_ERROR_MEM_PRIV |
2378 GM45_ERROR_CP_PRIV |
2379 I915_ERROR_MEMORY_REFRESH);
2380 } else {
2381 error_mask = ~(I915_ERROR_PAGE_TABLE |
2382 I915_ERROR_MEMORY_REFRESH);
2383 }
2384 I915_WRITE(EMR, error_mask);
2385
2386 I915_WRITE(IMR, dev_priv->irq_mask);
2387 I915_WRITE(IER, enable_mask);
2388 POSTING_READ(IER);
2389
2390 if (I915_HAS_HOTPLUG(dev)) {
2391 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2392
2393 /* Note HDMI and DP share bits */
2394 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2395 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2396 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2397 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2398 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2399 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2400 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2401 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2402 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2403 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2404 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2405 hotplug_en |= CRT_HOTPLUG_INT_EN;
2406
2407 /* Programming the CRT detection parameters tends
2408 to generate a spurious hotplug event about three
2409 seconds later. So just do it once.
2410 */
2411 if (IS_G4X(dev))
2412 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2413 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2414 }
2415
2416 /* Ignore TV since it's buggy */
2417
2418 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2419 }
2420
2421 intel_opregion_enable_asle(dev);
2422
2423 return 0;
2424}
2425
2426static irqreturn_t i915_irq_handler(DRM_IRQ_ARGS)
2427{
2428 struct drm_device *dev = (struct drm_device *) arg;
2429 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2430 struct drm_i915_master_private *master_priv;
2431 u32 iir, new_iir;
2432 u32 pipe_stats[I915_MAX_PIPES];
2433 u32 vblank_status;
2434 int vblank = 0;
2435 unsigned long irqflags;
2436 int irq_received;
2437 int ret = IRQ_NONE, pipe;
2438 bool blc_event = false;
2439
2440 atomic_inc(&dev_priv->irq_received);
2441
2442 iir = I915_READ(IIR);
2443
2444 if (INTEL_INFO(dev)->gen >= 4)
2445 vblank_status = PIPE_START_VBLANK_INTERRUPT_STATUS;
2446 else
2447 vblank_status = PIPE_VBLANK_INTERRUPT_STATUS;
2448
2449 for (;;) {
2450 irq_received = iir != 0;
2451
2452 /* Can't rely on pipestat interrupt bit in iir as it might
2453 * have been cleared after the pipestat interrupt was received.
2454 * It doesn't set the bit in iir again, but it still produces
2455 * interrupts (for non-MSI).
2456 */
2457 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2458 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2459 i915_handle_error(dev, false);
2460
2461 for_each_pipe(pipe) {
2462 int reg = PIPESTAT(pipe);
2463 pipe_stats[pipe] = I915_READ(reg);
2464
2465 /*
2466 * Clear the PIPE*STAT regs before the IIR
2467 */
2468 if (pipe_stats[pipe] & 0x8000ffff) {
2469 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2470 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2471 pipe_name(pipe));
2472 I915_WRITE(reg, pipe_stats[pipe]);
2473 irq_received = 1;
2474 }
2475 }
2476 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2477
2478 if (!irq_received)
2479 break;
2480
2481 ret = IRQ_HANDLED;
2482
2483 /* Consume port. Then clear IIR or we'll miss events */
2484 if ((I915_HAS_HOTPLUG(dev)) &&
2485 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2486 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2487
2488 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2489 hotplug_status);
2490 if (hotplug_status & dev_priv->hotplug_supported_mask)
2491 queue_work(dev_priv->wq,
2492 &dev_priv->hotplug_work);
2493
2494 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2495 I915_READ(PORT_HOTPLUG_STAT);
2496 }
2497
2498 I915_WRITE(IIR, iir);
2499 new_iir = I915_READ(IIR); /* Flush posted writes */
2500
2501 if (dev->primary->master) {
2502 master_priv = dev->primary->master->driver_priv;
2503 if (master_priv->sarea_priv)
2504 master_priv->sarea_priv->last_dispatch =
2505 READ_BREADCRUMB(dev_priv);
2506 }
2507
2508 if (iir & I915_USER_INTERRUPT)
2509 notify_ring(dev, &dev_priv->ring[RCS]);
2510 if (iir & I915_BSD_USER_INTERRUPT)
2511 notify_ring(dev, &dev_priv->ring[VCS]);
2512
4f7d1e79 2513 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2514 intel_prepare_page_flip(dev, 0);
a266c7d5 2515
4f7d1e79 2516 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2517 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2518
2519 for_each_pipe(pipe) {
2520 if (pipe_stats[pipe] & vblank_status &&
2521 drm_handle_vblank(dev, pipe)) {
2522 vblank++;
4f7d1e79
CW		 2523 i915_pageflip_stall_check(dev, pipe);
2524 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2525 }
2526
2527 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2528 blc_event = true;
2529 }
2530
2531
2532 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2533 intel_opregion_asle_intr(dev);
2534
2535 /* With MSI, interrupts are only generated when iir
2536 * transitions from zero to nonzero. If another bit got
2537 * set while we were handling the existing iir bits, then
2538 * we would never get another interrupt.
2539 *
2540 * This is fine on non-MSI as well, as if we hit this path
2541 * we avoid exiting the interrupt handler only to generate
2542 * another one.
2543 *
2544 * Note that for MSI this could cause a stray interrupt report
2545 * if an interrupt landed in the time between writing IIR and
2546 * the posting read. This should be rare enough to never
2547 * trigger the 99% of 100,000 interrupts test for disabling
2548 * stray interrupts.
2549 */
2550 iir = new_iir;
2551 }
2552
2553 return ret;
2554}
2555
2556static void i915_irq_uninstall(struct drm_device * dev)
2557{
2558 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2559 int pipe;
2560
2561 if (!dev_priv)
2562 return;
2563
2564 dev_priv->vblank_pipe = 0;
2565
2566 if (I915_HAS_HOTPLUG(dev)) {
2567 I915_WRITE(PORT_HOTPLUG_EN, 0);
2568 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2569 }
2570
2571 I915_WRITE(HWSTAM, 0xffffffff);
2572 for_each_pipe(pipe)
2573 I915_WRITE(PIPESTAT(pipe), 0);
2574 I915_WRITE(IMR, 0xffffffff);
2575 I915_WRITE(IER, 0x0);
2576
2577 for_each_pipe(pipe)
2578 I915_WRITE(PIPESTAT(pipe),
2579 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2580 I915_WRITE(IIR, I915_READ(IIR));
2581}
2582
2583static void i965_irq_preinstall(struct drm_device * dev)
2584{
2585 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2586 int pipe;
2587
2588 atomic_set(&dev_priv->irq_received, 0);
2589
2590 if (I915_HAS_HOTPLUG(dev)) {
2591 I915_WRITE(PORT_HOTPLUG_EN, 0);
2592 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2593 }
2594
2595 I915_WRITE(HWSTAM, 0xeffe);
2596 for_each_pipe(pipe)
2597 I915_WRITE(PIPESTAT(pipe), 0);
2598 I915_WRITE(IMR, 0xffffffff);
2599 I915_WRITE(IER, 0x0);
2600 POSTING_READ(IER);
2601}
2602
2603static int i965_irq_postinstall(struct drm_device *dev)
2604{
2605 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2606 u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
2607 u32 error_mask;
2608
2609 dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
2610
2611 /* Unmask the interrupts that we always want on. */
2612 dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
2613
2614 dev_priv->pipestat[0] = 0;
2615 dev_priv->pipestat[1] = 0;
2616
2617 if (I915_HAS_HOTPLUG(dev)) {
2618 /* Enable in IER... */
2619 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2620 /* and unmask in IMR */
2621 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2622 }
2623
2624 /*
2625 * Enable some error detection, note the instruction error mask
2626 * bit is reserved, so we leave it masked.
2627 */
2628 if (IS_G4X(dev)) {
2629 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2630 GM45_ERROR_MEM_PRIV |
2631 GM45_ERROR_CP_PRIV |
2632 I915_ERROR_MEMORY_REFRESH);
2633 } else {
2634 error_mask = ~(I915_ERROR_PAGE_TABLE |
2635 I915_ERROR_MEMORY_REFRESH);
2636 }
2637 I915_WRITE(EMR, error_mask);
2638
2639 I915_WRITE(IMR, dev_priv->irq_mask);
2640 I915_WRITE(IER, enable_mask);
2641 POSTING_READ(IER);
2642
2643 if (I915_HAS_HOTPLUG(dev)) {
2644 u32 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2645
2646 /* Note HDMI and DP share bits */
2647 if (dev_priv->hotplug_supported_mask & HDMIB_HOTPLUG_INT_STATUS)
2648 hotplug_en |= HDMIB_HOTPLUG_INT_EN;
2649 if (dev_priv->hotplug_supported_mask & HDMIC_HOTPLUG_INT_STATUS)
2650 hotplug_en |= HDMIC_HOTPLUG_INT_EN;
2651 if (dev_priv->hotplug_supported_mask & HDMID_HOTPLUG_INT_STATUS)
2652 hotplug_en |= HDMID_HOTPLUG_INT_EN;
2653 if (dev_priv->hotplug_supported_mask & SDVOC_HOTPLUG_INT_STATUS)
2654 hotplug_en |= SDVOC_HOTPLUG_INT_EN;
2655 if (dev_priv->hotplug_supported_mask & SDVOB_HOTPLUG_INT_STATUS)
2656 hotplug_en |= SDVOB_HOTPLUG_INT_EN;
2657 if (dev_priv->hotplug_supported_mask & CRT_HOTPLUG_INT_STATUS) {
2658 hotplug_en |= CRT_HOTPLUG_INT_EN;
2659
2660 /* Programming the CRT detection parameters tends
2661 to generate a spurious hotplug event about three
2662 seconds later. So just do it once.
2663 */
2664 if (IS_G4X(dev))
2665 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2666 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2667 }
2668
2669 /* Ignore TV since it's buggy */
2670
2671 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2672 }
2673
2674 intel_opregion_enable_asle(dev);
2675
2676 return 0;
2677}
2678
2679static irqreturn_t i965_irq_handler(DRM_IRQ_ARGS)
2680{
2681 struct drm_device *dev = (struct drm_device *) arg;
2682 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2683 struct drm_i915_master_private *master_priv;
2684 u32 iir, new_iir;
2685 u32 pipe_stats[I915_MAX_PIPES];
a266c7d5
CW		 2686 unsigned long irqflags;
2687 int irq_received;
2688 int ret = IRQ_NONE, pipe;
a266c7d5
CW		 2689
2690 atomic_inc(&dev_priv->irq_received);
2691
2692 iir = I915_READ(IIR);
2693
a266c7d5 2694 for (;;) {
2c8ba29f
CW		 2695 bool blc_event = false;
2696
a266c7d5
CW		 2697 irq_received = iir != 0;
2698
2699 /* Can't rely on pipestat interrupt bit in iir as it might
2700 * have been cleared after the pipestat interrupt was received.
2701 * It doesn't set the bit in iir again, but it still produces
2702 * interrupts (for non-MSI).
2703 */
2704 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2705 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2706 i915_handle_error(dev, false);
2707
2708 for_each_pipe(pipe) {
2709 int reg = PIPESTAT(pipe);
2710 pipe_stats[pipe] = I915_READ(reg);
2711
2712 /*
2713 * Clear the PIPE*STAT regs before the IIR
2714 */
2715 if (pipe_stats[pipe] & 0x8000ffff) {
2716 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2717 DRM_DEBUG_DRIVER("pipe %c underrun\n",
2718 pipe_name(pipe));
2719 I915_WRITE(reg, pipe_stats[pipe]);
2720 irq_received = 1;
2721 }
2722 }
2723 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2724
2725 if (!irq_received)
2726 break;
2727
2728 ret = IRQ_HANDLED;
2729
2730 /* Consume port. Then clear IIR or we'll miss events */
2731 if ((I915_HAS_HOTPLUG(dev)) &&
2732 (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2733 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2734
2735 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2736 hotplug_status);
2737 if (hotplug_status & dev_priv->hotplug_supported_mask)
2738 queue_work(dev_priv->wq,
2739 &dev_priv->hotplug_work);
2740
2741 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2742 I915_READ(PORT_HOTPLUG_STAT);
2743 }
2744
2745 I915_WRITE(IIR, iir);
2746 new_iir = I915_READ(IIR); /* Flush posted writes */
2747
a266c7d5
CW		 2748 if (iir & I915_USER_INTERRUPT)
2749 notify_ring(dev, &dev_priv->ring[RCS]);
2750 if (iir & I915_BSD_USER_INTERRUPT)
2751 notify_ring(dev, &dev_priv->ring[VCS]);
2752
4f7d1e79 2753 if (iir & I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT)
a266c7d5 2754 intel_prepare_page_flip(dev, 0);
a266c7d5 2755
4f7d1e79 2756 if (iir & I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT)
a266c7d5 2757 intel_prepare_page_flip(dev, 1);
a266c7d5
CW		 2758
2759 for_each_pipe(pipe) {
2c8ba29f 2760 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
a266c7d5 2761 drm_handle_vblank(dev, pipe)) {
4f7d1e79
CW		 2762 i915_pageflip_stall_check(dev, pipe);
2763 intel_finish_page_flip(dev, pipe);
a266c7d5
CW		 2764 }
2765
2766 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2767 blc_event = true;
2768 }
2769
2770
2771 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2772 intel_opregion_asle_intr(dev);
2773
2774 /* With MSI, interrupts are only generated when iir
2775 * transitions from zero to nonzero. If another bit got
2776 * set while we were handling the existing iir bits, then
2777 * we would never get another interrupt.
2778 *
2779 * This is fine on non-MSI as well, as if we hit this path
2780 * we avoid exiting the interrupt handler only to generate
2781 * another one.
2782 *
2783 * Note that for MSI this could cause a stray interrupt report
2784 * if an interrupt landed in the time between writing IIR and
2785 * the posting read. This should be rare enough to never
2786 * trigger the 99% of 100,000 interrupts test for disabling
2787 * stray interrupts.
2788 */
2789 iir = new_iir;
2790 }
2791
2c8ba29f
CW		 2792 if (dev->primary->master) {
2793 master_priv = dev->primary->master->driver_priv;
2794 if (master_priv->sarea_priv)
2795 master_priv->sarea_priv->last_dispatch =
2796 READ_BREADCRUMB(dev_priv);
2797 }
2798
a266c7d5
CW		 2799 return ret;
2800}
2801
2802static void i965_irq_uninstall(struct drm_device * dev)
2803{
2804 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2805 int pipe;
2806
2807 if (!dev_priv)
2808 return;
2809
2810 dev_priv->vblank_pipe = 0;
2811
2812 if (I915_HAS_HOTPLUG(dev)) {
2813 I915_WRITE(PORT_HOTPLUG_EN, 0);
2814 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2815 }
2816
2817 I915_WRITE(HWSTAM, 0xffffffff);
2818 for_each_pipe(pipe)
2819 I915_WRITE(PIPESTAT(pipe), 0);
2820 I915_WRITE(IMR, 0xffffffff);
2821 I915_WRITE(IER, 0x0);
2822
2823 for_each_pipe(pipe)
2824 I915_WRITE(PIPESTAT(pipe),
2825 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
2826 I915_WRITE(IIR, I915_READ(IIR));
2827}
2828
f71d4af4
JB		 2829void intel_irq_init(struct drm_device *dev)
2830{
8b2e326d
CW		 2831 struct drm_i915_private *dev_priv = dev->dev_private;
2832
2833 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
2834 INIT_WORK(&dev_priv->error_work, i915_error_work_func);
2835 INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
2836
f71d4af4
JB		 2837 dev->driver->get_vblank_counter = i915_get_vblank_counter;
2838 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
7e231dbe
JB		 2839 if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev) ||
2840 IS_VALLEYVIEW(dev)) {
f71d4af4
JB		 2841 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2842 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2843 }
2844
c3613de9
KP		 2845 if (drm_core_check_feature(dev, DRIVER_MODESET))
2846 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
2847 else
2848 dev->driver->get_vblank_timestamp = NULL;
f71d4af4
JB		 2849 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
2850
7e231dbe
JB		 2851 if (IS_VALLEYVIEW(dev)) {
2852 dev->driver->irq_handler = valleyview_irq_handler;
2853 dev->driver->irq_preinstall = valleyview_irq_preinstall;
2854 dev->driver->irq_postinstall = valleyview_irq_postinstall;
2855 dev->driver->irq_uninstall = valleyview_irq_uninstall;
2856 dev->driver->enable_vblank = valleyview_enable_vblank;
2857 dev->driver->disable_vblank = valleyview_disable_vblank;
2858 } else if (IS_IVYBRIDGE(dev)) {
f71d4af4
JB		 2859 /* Share pre & uninstall handlers with ILK/SNB */
2860 dev->driver->irq_handler = ivybridge_irq_handler;
2861 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2862 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
2863 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2864 dev->driver->enable_vblank = ivybridge_enable_vblank;
2865 dev->driver->disable_vblank = ivybridge_disable_vblank;
2866 } else if (HAS_PCH_SPLIT(dev)) {
2867 dev->driver->irq_handler = ironlake_irq_handler;
2868 dev->driver->irq_preinstall = ironlake_irq_preinstall;
2869 dev->driver->irq_postinstall = ironlake_irq_postinstall;
2870 dev->driver->irq_uninstall = ironlake_irq_uninstall;
2871 dev->driver->enable_vblank = ironlake_enable_vblank;
2872 dev->driver->disable_vblank = ironlake_disable_vblank;
2873 } else {
c2798b19
CW		 2874 if (INTEL_INFO(dev)->gen == 2) {
2875 dev->driver->irq_preinstall = i8xx_irq_preinstall;
2876 dev->driver->irq_postinstall = i8xx_irq_postinstall;
2877 dev->driver->irq_handler = i8xx_irq_handler;
2878 dev->driver->irq_uninstall = i8xx_irq_uninstall;
a266c7d5 2879 } else if (INTEL_INFO(dev)->gen == 3) {
4f7d1e79
CW		 2880 /* IIR "flip pending" means done if this bit is set */
2881 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
2882
a266c7d5
CW		 2883 dev->driver->irq_preinstall = i915_irq_preinstall;
2884 dev->driver->irq_postinstall = i915_irq_postinstall;
2885 dev->driver->irq_uninstall = i915_irq_uninstall;
2886 dev->driver->irq_handler = i915_irq_handler;
c2798b19 2887 } else {
a266c7d5
CW		 2888 dev->driver->irq_preinstall = i965_irq_preinstall;
2889 dev->driver->irq_postinstall = i965_irq_postinstall;
2890 dev->driver->irq_uninstall = i965_irq_uninstall;
2891 dev->driver->irq_handler = i965_irq_handler;
c2798b19 2892 }
f71d4af4
JB		 2893 dev->driver->enable_vblank = i915_enable_vblank;
2894 dev->driver->disable_vblank = i915_disable_vblank;
2895 }
2896}
kernel source for telekom puls (alcatel/mediatek)