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drm/i915: Sanity check pread/pwrite
[GitHub/LineageOS/android_kernel_motorola_exynos9610.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
f8f235e5 37#include <linux/intel-gtt.h>
673a394b 38
0108a3ed 39static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
2dafb1e0 40static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 43static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 int write);
45static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 uint64_t offset,
47 uint64_t size);
48static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 49static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 50static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 unsigned alignment);
de151cf6 52static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
71acb5eb
DA		 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
be72615b 56static void i915_gem_free_object_tail(struct drm_gem_object *obj);
673a394b 57
31169714
CW		 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
7d1c4804
CW		 61static inline bool
62i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
63{
64 return obj_priv->gtt_space &&
65 !obj_priv->active &&
66 obj_priv->pin_count == 0;
67}
68
79e53945
JB		 69int i915_gem_do_init(struct drm_device *dev, unsigned long start,
70 unsigned long end)
673a394b
EA		 71{
72 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 73
79e53945
JB		 74 if (start >= end ||
75 (start & (PAGE_SIZE - 1)) != 0 ||
76 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 77 return -EINVAL;
78 }
79
79e53945
JB		 80 drm_mm_init(&dev_priv->mm.gtt_space, start,
81 end - start);
673a394b 82
79e53945
JB		 83 dev->gtt_total = (uint32_t) (end - start);
84
85 return 0;
86}
673a394b 87
79e53945
JB		 88int
89i915_gem_init_ioctl(struct drm_device *dev, void *data,
90 struct drm_file *file_priv)
91{
92 struct drm_i915_gem_init *args = data;
93 int ret;
94
95 mutex_lock(&dev->struct_mutex);
96 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 97 mutex_unlock(&dev->struct_mutex);
98
79e53945 99 return ret;
673a394b
EA		 100}
101
5a125c3c
EA		 102int
103i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
104 struct drm_file *file_priv)
105{
5a125c3c 106 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 107
108 if (!(dev->driver->driver_features & DRIVER_GEM))
109 return -ENODEV;
110
111 args->aper_size = dev->gtt_total;
2678d9d6
KP		 112 args->aper_available_size = (args->aper_size -
113 atomic_read(&dev->pin_memory));
5a125c3c
EA		 114
115 return 0;
116}
117
673a394b
EA		 118
119/**
120 * Creates a new mm object and returns a handle to it.
121 */
122int
123i915_gem_create_ioctl(struct drm_device *dev, void *data,
124 struct drm_file *file_priv)
125{
126 struct drm_i915_gem_create *args = data;
127 struct drm_gem_object *obj;
a1a2d1d3
PP		 128 int ret;
129 u32 handle;
673a394b
EA		 130
131 args->size = roundup(args->size, PAGE_SIZE);
132
133 /* Allocate the new object */
ac52bc56 134 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 135 if (obj == NULL)
136 return -ENOMEM;
137
138 ret = drm_gem_handle_create(file_priv, obj, &handle);
1dfd9754
CW		 139 if (ret) {
140 drm_gem_object_unreference_unlocked(obj);
673a394b 141 return ret;
1dfd9754 142 }
673a394b 143
1dfd9754
CW		 144 /* Sink the floating reference from kref_init(handlecount) */
145 drm_gem_object_handle_unreference_unlocked(obj);
673a394b 146
1dfd9754 147 args->handle = handle;
673a394b
EA		 148 return 0;
149}
150
eb01459f
EA		 151static inline int
152fast_shmem_read(struct page **pages,
153 loff_t page_base, int page_offset,
154 char __user *data,
155 int length)
156{
157 char __iomem *vaddr;
2bc43b5c 158 int unwritten;
eb01459f
EA		 159
160 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
161 if (vaddr == NULL)
162 return -ENOMEM;
2bc43b5c 163 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 164 kunmap_atomic(vaddr, KM_USER0);
165
2bc43b5c
FM		 166 if (unwritten)
167 return -EFAULT;
168
169 return 0;
eb01459f
EA		 170}
171
280b713b
EA		 172static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
173{
174 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 175 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 176
177 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
178 obj_priv->tiling_mode != I915_TILING_NONE;
179}
180
99a03df5 181static inline void
40123c1f
EA		 182slow_shmem_copy(struct page *dst_page,
183 int dst_offset,
184 struct page *src_page,
185 int src_offset,
186 int length)
187{
188 char *dst_vaddr, *src_vaddr;
189
99a03df5
CW		 190 dst_vaddr = kmap(dst_page);
191 src_vaddr = kmap(src_page);
40123c1f
EA		 192
193 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
194
99a03df5
CW		 195 kunmap(src_page);
196 kunmap(dst_page);
40123c1f
EA		 197}
198
99a03df5 199static inline void
280b713b
EA		 200slow_shmem_bit17_copy(struct page *gpu_page,
201 int gpu_offset,
202 struct page *cpu_page,
203 int cpu_offset,
204 int length,
205 int is_read)
206{
207 char *gpu_vaddr, *cpu_vaddr;
208
209 /* Use the unswizzled path if this page isn't affected. */
210 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
211 if (is_read)
212 return slow_shmem_copy(cpu_page, cpu_offset,
213 gpu_page, gpu_offset, length);
214 else
215 return slow_shmem_copy(gpu_page, gpu_offset,
216 cpu_page, cpu_offset, length);
217 }
218
99a03df5
CW		 219 gpu_vaddr = kmap(gpu_page);
220 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 221
222 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
223 * XORing with the other bits (A9 for Y, A9 and A10 for X)
224 */
225 while (length > 0) {
226 int cacheline_end = ALIGN(gpu_offset + 1, 64);
227 int this_length = min(cacheline_end - gpu_offset, length);
228 int swizzled_gpu_offset = gpu_offset ^ 64;
229
230 if (is_read) {
231 memcpy(cpu_vaddr + cpu_offset,
232 gpu_vaddr + swizzled_gpu_offset,
233 this_length);
234 } else {
235 memcpy(gpu_vaddr + swizzled_gpu_offset,
236 cpu_vaddr + cpu_offset,
237 this_length);
238 }
239 cpu_offset += this_length;
240 gpu_offset += this_length;
241 length -= this_length;
242 }
243
99a03df5
CW		 244 kunmap(cpu_page);
245 kunmap(gpu_page);
280b713b
EA		 246}
247
eb01459f
EA		 248/**
249 * This is the fast shmem pread path, which attempts to copy_from_user directly
250 * from the backing pages of the object to the user's address space. On a
251 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
252 */
253static int
254i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
255 struct drm_i915_gem_pread *args,
256 struct drm_file *file_priv)
257{
23010e43 258 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 259 ssize_t remain;
260 loff_t offset, page_base;
261 char __user *user_data;
262 int page_offset, page_length;
263 int ret;
264
265 user_data = (char __user *) (uintptr_t) args->data_ptr;
266 remain = args->size;
267
268 mutex_lock(&dev->struct_mutex);
269
4bdadb97 270 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 271 if (ret != 0)
272 goto fail_unlock;
273
274 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
275 args->size);
276 if (ret != 0)
277 goto fail_put_pages;
278
23010e43 279 obj_priv = to_intel_bo(obj);
eb01459f
EA		 280 offset = args->offset;
281
282 while (remain > 0) {
283 /* Operation in this page
284 *
285 * page_base = page offset within aperture
286 * page_offset = offset within page
287 * page_length = bytes to copy for this page
288 */
289 page_base = (offset & ~(PAGE_SIZE-1));
290 page_offset = offset & (PAGE_SIZE-1);
291 page_length = remain;
292 if ((page_offset + remain) > PAGE_SIZE)
293 page_length = PAGE_SIZE - page_offset;
294
295 ret = fast_shmem_read(obj_priv->pages,
296 page_base, page_offset,
297 user_data, page_length);
298 if (ret)
299 goto fail_put_pages;
300
301 remain -= page_length;
302 user_data += page_length;
303 offset += page_length;
304 }
305
306fail_put_pages:
307 i915_gem_object_put_pages(obj);
308fail_unlock:
309 mutex_unlock(&dev->struct_mutex);
310
311 return ret;
312}
313
07f73f69
CW		 314static int
315i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
316{
317 int ret;
318
4bdadb97 319 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 320
321 /* If we've insufficient memory to map in the pages, attempt
322 * to make some space by throwing out some old buffers.
323 */
324 if (ret == -ENOMEM) {
325 struct drm_device *dev = obj->dev;
07f73f69 326
0108a3ed
DV		 327 ret = i915_gem_evict_something(dev, obj->size,
328 i915_gem_get_gtt_alignment(obj));
07f73f69
CW		 329 if (ret)
330 return ret;
331
4bdadb97 332 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 333 }
334
335 return ret;
336}
337
eb01459f
EA		 338/**
339 * This is the fallback shmem pread path, which allocates temporary storage
340 * in kernel space to copy_to_user into outside of the struct_mutex, so we
341 * can copy out of the object's backing pages while holding the struct mutex
342 * and not take page faults.
343 */
344static int
345i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
346 struct drm_i915_gem_pread *args,
347 struct drm_file *file_priv)
348{
23010e43 349 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 350 struct mm_struct *mm = current->mm;
351 struct page **user_pages;
352 ssize_t remain;
353 loff_t offset, pinned_pages, i;
354 loff_t first_data_page, last_data_page, num_pages;
355 int shmem_page_index, shmem_page_offset;
356 int data_page_index, data_page_offset;
357 int page_length;
358 int ret;
359 uint64_t data_ptr = args->data_ptr;
280b713b 360 int do_bit17_swizzling;
eb01459f
EA		 361
362 remain = args->size;
363
364 /* Pin the user pages containing the data. We can't fault while
365 * holding the struct mutex, yet we want to hold it while
366 * dereferencing the user data.
367 */
368 first_data_page = data_ptr / PAGE_SIZE;
369 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
370 num_pages = last_data_page - first_data_page + 1;
371
8e7d2b2c 372 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 373 if (user_pages == NULL)
374 return -ENOMEM;
375
376 down_read(&mm->mmap_sem);
377 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 378 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 379 up_read(&mm->mmap_sem);
380 if (pinned_pages < num_pages) {
381 ret = -EFAULT;
382 goto fail_put_user_pages;
383 }
384
280b713b
EA		 385 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
386
eb01459f
EA		 387 mutex_lock(&dev->struct_mutex);
388
07f73f69
CW		 389 ret = i915_gem_object_get_pages_or_evict(obj);
390 if (ret)
eb01459f
EA		 391 goto fail_unlock;
392
393 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
394 args->size);
395 if (ret != 0)
396 goto fail_put_pages;
397
23010e43 398 obj_priv = to_intel_bo(obj);
eb01459f
EA		 399 offset = args->offset;
400
401 while (remain > 0) {
402 /* Operation in this page
403 *
404 * shmem_page_index = page number within shmem file
405 * shmem_page_offset = offset within page in shmem file
406 * data_page_index = page number in get_user_pages return
407 * data_page_offset = offset with data_page_index page.
408 * page_length = bytes to copy for this page
409 */
410 shmem_page_index = offset / PAGE_SIZE;
411 shmem_page_offset = offset & ~PAGE_MASK;
412 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
413 data_page_offset = data_ptr & ~PAGE_MASK;
414
415 page_length = remain;
416 if ((shmem_page_offset + page_length) > PAGE_SIZE)
417 page_length = PAGE_SIZE - shmem_page_offset;
418 if ((data_page_offset + page_length) > PAGE_SIZE)
419 page_length = PAGE_SIZE - data_page_offset;
420
280b713b 421 if (do_bit17_swizzling) {
99a03df5 422 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b 423 shmem_page_offset,
99a03df5
CW		 424 user_pages[data_page_index],
425 data_page_offset,
426 page_length,
427 1);
428 } else {
429 slow_shmem_copy(user_pages[data_page_index],
430 data_page_offset,
431 obj_priv->pages[shmem_page_index],
432 shmem_page_offset,
433 page_length);
280b713b 434 }
eb01459f
EA		 435
436 remain -= page_length;
437 data_ptr += page_length;
438 offset += page_length;
439 }
440
441fail_put_pages:
442 i915_gem_object_put_pages(obj);
443fail_unlock:
444 mutex_unlock(&dev->struct_mutex);
445fail_put_user_pages:
446 for (i = 0; i < pinned_pages; i++) {
447 SetPageDirty(user_pages[i]);
448 page_cache_release(user_pages[i]);
449 }
8e7d2b2c 450 drm_free_large(user_pages);
eb01459f
EA		 451
452 return ret;
453}
454
673a394b
EA		 455/**
456 * Reads data from the object referenced by handle.
457 *
458 * On error, the contents of *data are undefined.
459 */
460int
461i915_gem_pread_ioctl(struct drm_device *dev, void *data,
462 struct drm_file *file_priv)
463{
464 struct drm_i915_gem_pread *args = data;
465 struct drm_gem_object *obj;
466 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 467 int ret;
468
469 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
470 if (obj == NULL)
bf79cb91 471 return -ENOENT;
23010e43 472 obj_priv = to_intel_bo(obj);
673a394b
EA		 473
474 /* Bounds check source.
475 *
476 * XXX: This could use review for overflow issues...
477 */
478 if (args->offset > obj->size || args->size > obj->size ||
479 args->offset + args->size > obj->size) {
ce9d419d
CW		 480 ret = -EINVAL;
481 goto err;
482 }
483
484 if (!access_ok(VERIFY_WRITE,
485 (char __user *)(uintptr_t)args->data_ptr,
486 args->size)) {
487 ret = -EFAULT;
488 goto err;
673a394b
EA		 489 }
490
280b713b 491 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 492 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 493 } else {
494 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
495 if (ret != 0)
496 ret = i915_gem_shmem_pread_slow(dev, obj, args,
497 file_priv);
498 }
673a394b 499
ce9d419d 500err:
bc9025bd 501 drm_gem_object_unreference_unlocked(obj);
eb01459f 502 return ret;
673a394b
EA		 503}
504
0839ccb8
KP		 505/* This is the fast write path which cannot handle
506 * page faults in the source data
9b7530cc 507 */
0839ccb8
KP		 508
509static inline int
510fast_user_write(struct io_mapping *mapping,
511 loff_t page_base, int page_offset,
512 char __user *user_data,
513 int length)
9b7530cc 514{
9b7530cc 515 char *vaddr_atomic;
0839ccb8 516 unsigned long unwritten;
9b7530cc 517
fca3ec01 518 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
0839ccb8
KP		 519 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
520 user_data, length);
fca3ec01 521 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
0839ccb8
KP		 522 if (unwritten)
523 return -EFAULT;
524 return 0;
525}
526
527/* Here's the write path which can sleep for
528 * page faults
529 */
530
ab34c226 531static inline void
3de09aa3
EA		 532slow_kernel_write(struct io_mapping *mapping,
533 loff_t gtt_base, int gtt_offset,
534 struct page *user_page, int user_offset,
535 int length)
0839ccb8 536{
ab34c226
CW		 537 char __iomem *dst_vaddr;
538 char *src_vaddr;
0839ccb8 539
ab34c226
CW		 540 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
541 src_vaddr = kmap(user_page);
542
543 memcpy_toio(dst_vaddr + gtt_offset,
544 src_vaddr + user_offset,
545 length);
546
547 kunmap(user_page);
548 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 549}
550
40123c1f
EA		 551static inline int
552fast_shmem_write(struct page **pages,
553 loff_t page_base, int page_offset,
554 char __user *data,
555 int length)
556{
557 char __iomem *vaddr;
d0088775 558 unsigned long unwritten;
40123c1f
EA		 559
560 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
561 if (vaddr == NULL)
562 return -ENOMEM;
d0088775 563 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 564 kunmap_atomic(vaddr, KM_USER0);
565
d0088775
DA		 566 if (unwritten)
567 return -EFAULT;
40123c1f
EA		 568 return 0;
569}
570
3de09aa3
EA		 571/**
572 * This is the fast pwrite path, where we copy the data directly from the
573 * user into the GTT, uncached.
574 */
673a394b 575static int
3de09aa3
EA		 576i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
577 struct drm_i915_gem_pwrite *args,
578 struct drm_file *file_priv)
673a394b 579{
23010e43 580 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 581 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 582 ssize_t remain;
0839ccb8 583 loff_t offset, page_base;
673a394b 584 char __user *user_data;
0839ccb8
KP		 585 int page_offset, page_length;
586 int ret;
673a394b
EA		 587
588 user_data = (char __user *) (uintptr_t) args->data_ptr;
589 remain = args->size;
673a394b
EA		 590
591
592 mutex_lock(&dev->struct_mutex);
593 ret = i915_gem_object_pin(obj, 0);
594 if (ret) {
595 mutex_unlock(&dev->struct_mutex);
596 return ret;
597 }
2ef7eeaa 598 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 599 if (ret)
600 goto fail;
601
23010e43 602 obj_priv = to_intel_bo(obj);
673a394b 603 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 604
605 while (remain > 0) {
606 /* Operation in this page
607 *
0839ccb8
KP		 608 * page_base = page offset within aperture
609 * page_offset = offset within page
610 * page_length = bytes to copy for this page
673a394b 611 */
0839ccb8
KP		 612 page_base = (offset & ~(PAGE_SIZE-1));
613 page_offset = offset & (PAGE_SIZE-1);
614 page_length = remain;
615 if ((page_offset + remain) > PAGE_SIZE)
616 page_length = PAGE_SIZE - page_offset;
617
618 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
619 page_offset, user_data, page_length);
620
621 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 622 * source page isn't available. Return the error and we'll
623 * retry in the slow path.
0839ccb8 624 */
3de09aa3
EA		 625 if (ret)
626 goto fail;
673a394b 627
0839ccb8
KP		 628 remain -= page_length;
629 user_data += page_length;
630 offset += page_length;
673a394b 631 }
673a394b
EA		 632
633fail:
634 i915_gem_object_unpin(obj);
635 mutex_unlock(&dev->struct_mutex);
636
637 return ret;
638}
639
3de09aa3
EA		 640/**
641 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
642 * the memory and maps it using kmap_atomic for copying.
643 *
644 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
645 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
646 */
3043c60c 647static int
3de09aa3
EA		 648i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
649 struct drm_i915_gem_pwrite *args,
650 struct drm_file *file_priv)
673a394b 651{
23010e43 652 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 653 drm_i915_private_t *dev_priv = dev->dev_private;
654 ssize_t remain;
655 loff_t gtt_page_base, offset;
656 loff_t first_data_page, last_data_page, num_pages;
657 loff_t pinned_pages, i;
658 struct page **user_pages;
659 struct mm_struct *mm = current->mm;
660 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 661 int ret;
3de09aa3
EA		 662 uint64_t data_ptr = args->data_ptr;
663
664 remain = args->size;
665
666 /* Pin the user pages containing the data. We can't fault while
667 * holding the struct mutex, and all of the pwrite implementations
668 * want to hold it while dereferencing the user data.
669 */
670 first_data_page = data_ptr / PAGE_SIZE;
671 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
672 num_pages = last_data_page - first_data_page + 1;
673
8e7d2b2c 674 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 675 if (user_pages == NULL)
676 return -ENOMEM;
677
678 down_read(&mm->mmap_sem);
679 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
680 num_pages, 0, 0, user_pages, NULL);
681 up_read(&mm->mmap_sem);
682 if (pinned_pages < num_pages) {
683 ret = -EFAULT;
684 goto out_unpin_pages;
685 }
673a394b
EA		 686
687 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 688 ret = i915_gem_object_pin(obj, 0);
689 if (ret)
690 goto out_unlock;
691
692 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
693 if (ret)
694 goto out_unpin_object;
695
23010e43 696 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 697 offset = obj_priv->gtt_offset + args->offset;
698
699 while (remain > 0) {
700 /* Operation in this page
701 *
702 * gtt_page_base = page offset within aperture
703 * gtt_page_offset = offset within page in aperture
704 * data_page_index = page number in get_user_pages return
705 * data_page_offset = offset with data_page_index page.
706 * page_length = bytes to copy for this page
707 */
708 gtt_page_base = offset & PAGE_MASK;
709 gtt_page_offset = offset & ~PAGE_MASK;
710 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
711 data_page_offset = data_ptr & ~PAGE_MASK;
712
713 page_length = remain;
714 if ((gtt_page_offset + page_length) > PAGE_SIZE)
715 page_length = PAGE_SIZE - gtt_page_offset;
716 if ((data_page_offset + page_length) > PAGE_SIZE)
717 page_length = PAGE_SIZE - data_page_offset;
718
ab34c226
CW		 719 slow_kernel_write(dev_priv->mm.gtt_mapping,
720 gtt_page_base, gtt_page_offset,
721 user_pages[data_page_index],
722 data_page_offset,
723 page_length);
3de09aa3
EA		 724
725 remain -= page_length;
726 offset += page_length;
727 data_ptr += page_length;
728 }
729
730out_unpin_object:
731 i915_gem_object_unpin(obj);
732out_unlock:
733 mutex_unlock(&dev->struct_mutex);
734out_unpin_pages:
735 for (i = 0; i < pinned_pages; i++)
736 page_cache_release(user_pages[i]);
8e7d2b2c 737 drm_free_large(user_pages);
3de09aa3
EA		 738
739 return ret;
740}
741
40123c1f
EA		 742/**
743 * This is the fast shmem pwrite path, which attempts to directly
744 * copy_from_user into the kmapped pages backing the object.
745 */
3043c60c 746static int
40123c1f
EA		 747i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
748 struct drm_i915_gem_pwrite *args,
749 struct drm_file *file_priv)
673a394b 750{
23010e43 751 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 752 ssize_t remain;
753 loff_t offset, page_base;
754 char __user *user_data;
755 int page_offset, page_length;
673a394b 756 int ret;
40123c1f
EA		 757
758 user_data = (char __user *) (uintptr_t) args->data_ptr;
759 remain = args->size;
673a394b
EA		 760
761 mutex_lock(&dev->struct_mutex);
762
4bdadb97 763 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 764 if (ret != 0)
765 goto fail_unlock;
673a394b 766
e47c68e9 767 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 768 if (ret != 0)
769 goto fail_put_pages;
770
23010e43 771 obj_priv = to_intel_bo(obj);
40123c1f
EA		 772 offset = args->offset;
773 obj_priv->dirty = 1;
774
775 while (remain > 0) {
776 /* Operation in this page
777 *
778 * page_base = page offset within aperture
779 * page_offset = offset within page
780 * page_length = bytes to copy for this page
781 */
782 page_base = (offset & ~(PAGE_SIZE-1));
783 page_offset = offset & (PAGE_SIZE-1);
784 page_length = remain;
785 if ((page_offset + remain) > PAGE_SIZE)
786 page_length = PAGE_SIZE - page_offset;
787
788 ret = fast_shmem_write(obj_priv->pages,
789 page_base, page_offset,
790 user_data, page_length);
791 if (ret)
792 goto fail_put_pages;
793
794 remain -= page_length;
795 user_data += page_length;
796 offset += page_length;
797 }
798
799fail_put_pages:
800 i915_gem_object_put_pages(obj);
801fail_unlock:
802 mutex_unlock(&dev->struct_mutex);
803
804 return ret;
805}
806
807/**
808 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
809 * the memory and maps it using kmap_atomic for copying.
810 *
811 * This avoids taking mmap_sem for faulting on the user's address while the
812 * struct_mutex is held.
813 */
814static int
815i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
816 struct drm_i915_gem_pwrite *args,
817 struct drm_file *file_priv)
818{
23010e43 819 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 820 struct mm_struct *mm = current->mm;
821 struct page **user_pages;
822 ssize_t remain;
823 loff_t offset, pinned_pages, i;
824 loff_t first_data_page, last_data_page, num_pages;
825 int shmem_page_index, shmem_page_offset;
826 int data_page_index, data_page_offset;
827 int page_length;
828 int ret;
829 uint64_t data_ptr = args->data_ptr;
280b713b 830 int do_bit17_swizzling;
40123c1f
EA		 831
832 remain = args->size;
833
834 /* Pin the user pages containing the data. We can't fault while
835 * holding the struct mutex, and all of the pwrite implementations
836 * want to hold it while dereferencing the user data.
837 */
838 first_data_page = data_ptr / PAGE_SIZE;
839 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
840 num_pages = last_data_page - first_data_page + 1;
841
8e7d2b2c 842 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 843 if (user_pages == NULL)
844 return -ENOMEM;
845
846 down_read(&mm->mmap_sem);
847 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
848 num_pages, 0, 0, user_pages, NULL);
849 up_read(&mm->mmap_sem);
850 if (pinned_pages < num_pages) {
851 ret = -EFAULT;
852 goto fail_put_user_pages;
673a394b
EA		 853 }
854
280b713b
EA		 855 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
856
40123c1f
EA		 857 mutex_lock(&dev->struct_mutex);
858
07f73f69
CW		 859 ret = i915_gem_object_get_pages_or_evict(obj);
860 if (ret)
40123c1f
EA		 861 goto fail_unlock;
862
863 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
864 if (ret != 0)
865 goto fail_put_pages;
866
23010e43 867 obj_priv = to_intel_bo(obj);
673a394b 868 offset = args->offset;
40123c1f 869 obj_priv->dirty = 1;
673a394b 870
40123c1f
EA		 871 while (remain > 0) {
872 /* Operation in this page
873 *
874 * shmem_page_index = page number within shmem file
875 * shmem_page_offset = offset within page in shmem file
876 * data_page_index = page number in get_user_pages return
877 * data_page_offset = offset with data_page_index page.
878 * page_length = bytes to copy for this page
879 */
880 shmem_page_index = offset / PAGE_SIZE;
881 shmem_page_offset = offset & ~PAGE_MASK;
882 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
883 data_page_offset = data_ptr & ~PAGE_MASK;
884
885 page_length = remain;
886 if ((shmem_page_offset + page_length) > PAGE_SIZE)
887 page_length = PAGE_SIZE - shmem_page_offset;
888 if ((data_page_offset + page_length) > PAGE_SIZE)
889 page_length = PAGE_SIZE - data_page_offset;
890
280b713b 891 if (do_bit17_swizzling) {
99a03df5 892 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b
EA		 893 shmem_page_offset,
894 user_pages[data_page_index],
895 data_page_offset,
99a03df5
CW		 896 page_length,
897 0);
898 } else {
899 slow_shmem_copy(obj_priv->pages[shmem_page_index],
900 shmem_page_offset,
901 user_pages[data_page_index],
902 data_page_offset,
903 page_length);
280b713b 904 }
40123c1f
EA		 905
906 remain -= page_length;
907 data_ptr += page_length;
908 offset += page_length;
673a394b
EA		 909 }
910
40123c1f
EA		 911fail_put_pages:
912 i915_gem_object_put_pages(obj);
913fail_unlock:
673a394b 914 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 915fail_put_user_pages:
916 for (i = 0; i < pinned_pages; i++)
917 page_cache_release(user_pages[i]);
8e7d2b2c 918 drm_free_large(user_pages);
673a394b 919
40123c1f 920 return ret;
673a394b
EA		 921}
922
923/**
924 * Writes data to the object referenced by handle.
925 *
926 * On error, the contents of the buffer that were to be modified are undefined.
927 */
928int
929i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
930 struct drm_file *file_priv)
931{
932 struct drm_i915_gem_pwrite *args = data;
933 struct drm_gem_object *obj;
934 struct drm_i915_gem_object *obj_priv;
935 int ret = 0;
936
937 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
938 if (obj == NULL)
bf79cb91 939 return -ENOENT;
23010e43 940 obj_priv = to_intel_bo(obj);
673a394b
EA		 941
942 /* Bounds check destination.
943 *
944 * XXX: This could use review for overflow issues...
945 */
946 if (args->offset > obj->size || args->size > obj->size ||
947 args->offset + args->size > obj->size) {
ce9d419d
CW		 948 ret = -EINVAL;
949 goto err;
950 }
951
952 if (!access_ok(VERIFY_READ,
953 (char __user *)(uintptr_t)args->data_ptr,
954 args->size)) {
955 ret = -EFAULT;
956 goto err;
673a394b
EA		 957 }
958
959 /* We can only do the GTT pwrite on untiled buffers, as otherwise
960 * it would end up going through the fenced access, and we'll get
961 * different detiling behavior between reading and writing.
962 * pread/pwrite currently are reading and writing from the CPU
963 * perspective, requiring manual detiling by the client.
964 */
71acb5eb
DA		 965 if (obj_priv->phys_obj)
966 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
967 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
9b8c4a0b
CW		 968 dev->gtt_total != 0 &&
969 obj->write_domain != I915_GEM_DOMAIN_CPU) {
3de09aa3
EA		 970 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
971 if (ret == -EFAULT) {
972 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
973 file_priv);
974 }
280b713b
EA		 975 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
976 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 977 } else {
978 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
979 if (ret == -EFAULT) {
980 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
981 file_priv);
982 }
983 }
673a394b
EA		 984
985#if WATCH_PWRITE
986 if (ret)
987 DRM_INFO("pwrite failed %d\n", ret);
988#endif
989
ce9d419d 990err:
bc9025bd 991 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 992 return ret;
993}
994
995/**
2ef7eeaa
EA		 996 * Called when user space prepares to use an object with the CPU, either
997 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 998 */
999int
1000i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1001 struct drm_file *file_priv)
1002{
a09ba7fa 1003 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1004 struct drm_i915_gem_set_domain *args = data;
1005 struct drm_gem_object *obj;
652c393a 1006 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1007 uint32_t read_domains = args->read_domains;
1008 uint32_t write_domain = args->write_domain;
673a394b
EA		 1009 int ret;
1010
1011 if (!(dev->driver->driver_features & DRIVER_GEM))
1012 return -ENODEV;
1013
2ef7eeaa 1014 /* Only handle setting domains to types used by the CPU. */
21d509e3 1015 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1016 return -EINVAL;
1017
21d509e3 1018 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1019 return -EINVAL;
1020
1021 /* Having something in the write domain implies it's in the read
1022 * domain, and only that read domain. Enforce that in the request.
1023 */
1024 if (write_domain != 0 && read_domains != write_domain)
1025 return -EINVAL;
1026
673a394b
EA		 1027 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1028 if (obj == NULL)
bf79cb91 1029 return -ENOENT;
23010e43 1030 obj_priv = to_intel_bo(obj);
673a394b
EA		 1031
1032 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1033
1034 intel_mark_busy(dev, obj);
1035
673a394b 1036#if WATCH_BUF
cfd43c02 1037 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1038 obj, obj->size, read_domains, write_domain);
673a394b 1039#endif
2ef7eeaa
EA		 1040 if (read_domains & I915_GEM_DOMAIN_GTT) {
1041 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1042
a09ba7fa
EA		 1043 /* Update the LRU on the fence for the CPU access that's
1044 * about to occur.
1045 */
1046 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1047 struct drm_i915_fence_reg *reg =
1048 &dev_priv->fence_regs[obj_priv->fence_reg];
1049 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1050 &dev_priv->mm.fence_list);
1051 }
1052
02354392
EA		 1053 /* Silently promote "you're not bound, there was nothing to do"
1054 * to success, since the client was just asking us to
1055 * make sure everything was done.
1056 */
1057 if (ret == -EINVAL)
1058 ret = 0;
2ef7eeaa 1059 } else {
e47c68e9 1060 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1061 }
1062
7d1c4804
CW		 1063
1064 /* Maintain LRU order of "inactive" objects */
1065 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1066 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1067
673a394b
EA		 1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1070 return ret;
1071}
1072
1073/**
1074 * Called when user space has done writes to this buffer
1075 */
1076int
1077i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1079{
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1083 int ret = 0;
1084
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1086 return -ENODEV;
1087
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 if (obj == NULL) {
1091 mutex_unlock(&dev->struct_mutex);
bf79cb91 1092 return -ENOENT;
673a394b
EA		 1093 }
1094
1095#if WATCH_BUF
cfd43c02 1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1097 __func__, args->handle, obj, obj->size);
1098#endif
23010e43 1099 obj_priv = to_intel_bo(obj);
673a394b
EA		 1100
1101 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1104
673a394b
EA		 1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1107 return ret;
1108}
1109
1110/**
1111 * Maps the contents of an object, returning the address it is mapped
1112 * into.
1113 *
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1116 */
1117int
1118i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1120{
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1123 loff_t offset;
1124 unsigned long addr;
1125
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1127 return -ENODEV;
1128
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1130 if (obj == NULL)
bf79cb91 1131 return -ENOENT;
673a394b
EA		 1132
1133 offset = args->offset;
1134
1135 down_write(&current->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1138 args->offset);
1139 up_write(&current->mm->mmap_sem);
bc9025bd 1140 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1141 if (IS_ERR((void *)addr))
1142 return addr;
1143
1144 args->addr_ptr = (uint64_t) addr;
1145
1146 return 0;
1147}
1148
de151cf6
JB		 1149/**
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1152 * vmf: fault info
1153 *
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1159 *
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1163 * left.
1164 */
1165int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1166{
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
7d1c4804 1169 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1171 pgoff_t page_offset;
1172 unsigned long pfn;
1173 int ret = 0;
0f973f27 1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1175
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1178 PAGE_SHIFT;
1179
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
e67b8ce1 1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1184 if (ret)
1185 goto unlock;
07f4f3e8 1186
07f4f3e8 1187 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1188 if (ret)
1189 goto unlock;
de151cf6
JB		 1190 }
1191
1192 /* Need a new fence register? */
a09ba7fa 1193 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1194 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1195 if (ret)
1196 goto unlock;
d9ddcb96 1197 }
de151cf6 1198
7d1c4804
CW		 1199 if (i915_gem_object_is_inactive(obj_priv))
1200 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1201
de151cf6
JB		 1202 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1203 page_offset;
1204
1205 /* Finally, remap it using the new GTT offset */
1206 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1207unlock:
de151cf6
JB		 1208 mutex_unlock(&dev->struct_mutex);
1209
1210 switch (ret) {
c715089f
CW		 1211 case 0:
1212 case -ERESTARTSYS:
1213 return VM_FAULT_NOPAGE;
de151cf6
JB		 1214 case -ENOMEM:
1215 case -EAGAIN:
1216 return VM_FAULT_OOM;
de151cf6 1217 default:
c715089f 1218 return VM_FAULT_SIGBUS;
de151cf6
JB		 1219 }
1220}
1221
1222/**
1223 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1224 * @obj: obj in question
1225 *
1226 * GEM memory mapping works by handing back to userspace a fake mmap offset
1227 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1228 * up the object based on the offset and sets up the various memory mapping
1229 * structures.
1230 *
1231 * This routine allocates and attaches a fake offset for @obj.
1232 */
1233static int
1234i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1235{
1236 struct drm_device *dev = obj->dev;
1237 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1238 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1239 struct drm_map_list *list;
f77d390c 1240 struct drm_local_map *map;
de151cf6
JB		 1241 int ret = 0;
1242
1243 /* Set the object up for mmap'ing */
1244 list = &obj->map_list;
9a298b2a 1245 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1246 if (!list->map)
1247 return -ENOMEM;
1248
1249 map = list->map;
1250 map->type = _DRM_GEM;
1251 map->size = obj->size;
1252 map->handle = obj;
1253
1254 /* Get a DRM GEM mmap offset allocated... */
1255 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1256 obj->size / PAGE_SIZE, 0, 0);
1257 if (!list->file_offset_node) {
1258 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1259 ret = -ENOMEM;
1260 goto out_free_list;
1261 }
1262
1263 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1264 obj->size / PAGE_SIZE, 0);
1265 if (!list->file_offset_node) {
1266 ret = -ENOMEM;
1267 goto out_free_list;
1268 }
1269
1270 list->hash.key = list->file_offset_node->start;
1271 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1272 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1273 ret = -ENOMEM;
de151cf6
JB		 1274 goto out_free_mm;
1275 }
1276
1277 /* By now we should be all set, any drm_mmap request on the offset
1278 * below will get to our mmap & fault handler */
1279 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1280
1281 return 0;
1282
1283out_free_mm:
1284 drm_mm_put_block(list->file_offset_node);
1285out_free_list:
9a298b2a 1286 kfree(list->map);
de151cf6
JB		 1287
1288 return ret;
1289}
1290
901782b2
CW		 1291/**
1292 * i915_gem_release_mmap - remove physical page mappings
1293 * @obj: obj in question
1294 *
af901ca1 1295 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1296 * relinquish ownership of the pages back to the system.
1297 *
1298 * It is vital that we remove the page mapping if we have mapped a tiled
1299 * object through the GTT and then lose the fence register due to
1300 * resource pressure. Similarly if the object has been moved out of the
1301 * aperture, than pages mapped into userspace must be revoked. Removing the
1302 * mapping will then trigger a page fault on the next user access, allowing
1303 * fixup by i915_gem_fault().
1304 */
d05ca301 1305void
901782b2
CW		 1306i915_gem_release_mmap(struct drm_gem_object *obj)
1307{
1308 struct drm_device *dev = obj->dev;
23010e43 1309 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1310
1311 if (dev->dev_mapping)
1312 unmap_mapping_range(dev->dev_mapping,
1313 obj_priv->mmap_offset, obj->size, 1);
1314}
1315
ab00b3e5
JB		 1316static void
1317i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1318{
1319 struct drm_device *dev = obj->dev;
23010e43 1320 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1321 struct drm_gem_mm *mm = dev->mm_private;
1322 struct drm_map_list *list;
1323
1324 list = &obj->map_list;
1325 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1326
1327 if (list->file_offset_node) {
1328 drm_mm_put_block(list->file_offset_node);
1329 list->file_offset_node = NULL;
1330 }
1331
1332 if (list->map) {
9a298b2a 1333 kfree(list->map);
ab00b3e5
JB		 1334 list->map = NULL;
1335 }
1336
1337 obj_priv->mmap_offset = 0;
1338}
1339
de151cf6
JB		 1340/**
1341 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1342 * @obj: object to check
1343 *
1344 * Return the required GTT alignment for an object, taking into account
1345 * potential fence register mapping if needed.
1346 */
1347static uint32_t
1348i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1349{
1350 struct drm_device *dev = obj->dev;
23010e43 1351 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1352 int start, i;
1353
1354 /*
1355 * Minimum alignment is 4k (GTT page size), but might be greater
1356 * if a fence register is needed for the object.
1357 */
1358 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1359 return 4096;
1360
1361 /*
1362 * Previous chips need to be aligned to the size of the smallest
1363 * fence register that can contain the object.
1364 */
1365 if (IS_I9XX(dev))
1366 start = 1024*1024;
1367 else
1368 start = 512*1024;
1369
1370 for (i = start; i < obj->size; i <<= 1)
1371 ;
1372
1373 return i;
1374}
1375
1376/**
1377 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1378 * @dev: DRM device
1379 * @data: GTT mapping ioctl data
1380 * @file_priv: GEM object info
1381 *
1382 * Simply returns the fake offset to userspace so it can mmap it.
1383 * The mmap call will end up in drm_gem_mmap(), which will set things
1384 * up so we can get faults in the handler above.
1385 *
1386 * The fault handler will take care of binding the object into the GTT
1387 * (since it may have been evicted to make room for something), allocating
1388 * a fence register, and mapping the appropriate aperture address into
1389 * userspace.
1390 */
1391int
1392i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1393 struct drm_file *file_priv)
1394{
1395 struct drm_i915_gem_mmap_gtt *args = data;
de151cf6
JB		 1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1398 int ret;
1399
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1401 return -ENODEV;
1402
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1404 if (obj == NULL)
bf79cb91 1405 return -ENOENT;
de151cf6
JB		 1406
1407 mutex_lock(&dev->struct_mutex);
1408
23010e43 1409 obj_priv = to_intel_bo(obj);
de151cf6 1410
ab18282d
CW		 1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1415 return -EINVAL;
1416 }
1417
1418
de151cf6
JB		 1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1421 if (ret) {
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
de151cf6 1424 return ret;
13af1062 1425 }
de151cf6
JB		 1426 }
1427
1428 args->offset = obj_priv->mmap_offset;
1429
de151cf6
JB		 1430 /*
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1433 */
1434 if (!obj_priv->agp_mem) {
e67b8ce1 1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1439 return ret;
1440 }
de151cf6
JB		 1441 }
1442
1443 drm_gem_object_unreference(obj);
1444 mutex_unlock(&dev->struct_mutex);
1445
1446 return 0;
1447}
1448
6911a9b8 1449void
856fa198 1450i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1451{
23010e43 1452 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1453 int page_count = obj->size / PAGE_SIZE;
1454 int i;
1455
856fa198 1456 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1457 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1458
856fa198
EA		 1459 if (--obj_priv->pages_refcount != 0)
1460 return;
673a394b 1461
280b713b
EA		 1462 if (obj_priv->tiling_mode != I915_TILING_NONE)
1463 i915_gem_object_save_bit_17_swizzle(obj);
1464
3ef94daa 1465 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1466 obj_priv->dirty = 0;
3ef94daa
CW		 1467
1468 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1469 if (obj_priv->dirty)
1470 set_page_dirty(obj_priv->pages[i]);
1471
1472 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1473 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1474
1475 page_cache_release(obj_priv->pages[i]);
1476 }
673a394b
EA		 1477 obj_priv->dirty = 0;
1478
8e7d2b2c 1479 drm_free_large(obj_priv->pages);
856fa198 1480 obj_priv->pages = NULL;
673a394b
EA		 1481}
1482
1483static void
852835f3
ZN		 1484i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1485 struct intel_ring_buffer *ring)
673a394b
EA		 1486{
1487 struct drm_device *dev = obj->dev;
1488 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1489 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
852835f3
ZN		 1490 BUG_ON(ring == NULL);
1491 obj_priv->ring = ring;
673a394b
EA		 1492
1493 /* Add a reference if we're newly entering the active list. */
1494 if (!obj_priv->active) {
1495 drm_gem_object_reference(obj);
1496 obj_priv->active = 1;
1497 }
1498 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1499 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1500 list_move_tail(&obj_priv->list, &ring->active_list);
5e118f41 1501 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1502 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1503}
1504
ce44b0ea
EA		 1505static void
1506i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1507{
1508 struct drm_device *dev = obj->dev;
1509 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1510 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1511
1512 BUG_ON(!obj_priv->active);
1513 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1514 obj_priv->last_rendering_seqno = 0;
1515}
673a394b 1516
963b4836
CW		 1517/* Immediately discard the backing storage */
1518static void
1519i915_gem_object_truncate(struct drm_gem_object *obj)
1520{
23010e43 1521 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1522 struct inode *inode;
963b4836 1523
ae9fed6b
CW		 1524 /* Our goal here is to return as much of the memory as
1525 * is possible back to the system as we are called from OOM.
1526 * To do this we must instruct the shmfs to drop all of its
1527 * backing pages, *now*. Here we mirror the actions taken
1528 * when by shmem_delete_inode() to release the backing store.
1529 */
bb6baf76 1530 inode = obj->filp->f_path.dentry->d_inode;
ae9fed6b
CW		 1531 truncate_inode_pages(inode->i_mapping, 0);
1532 if (inode->i_op->truncate_range)
1533 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
bb6baf76
CW		 1534
1535 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1536}
1537
1538static inline int
1539i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1540{
1541 return obj_priv->madv == I915_MADV_DONTNEED;
1542}
1543
673a394b
EA		 1544static void
1545i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1546{
1547 struct drm_device *dev = obj->dev;
1548 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1549 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1550
1551 i915_verify_inactive(dev, __FILE__, __LINE__);
1552 if (obj_priv->pin_count != 0)
1553 list_del_init(&obj_priv->list);
1554 else
1555 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1556
99fcb766
DV		 1557 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1558
ce44b0ea 1559 obj_priv->last_rendering_seqno = 0;
852835f3 1560 obj_priv->ring = NULL;
673a394b
EA		 1561 if (obj_priv->active) {
1562 obj_priv->active = 0;
1563 drm_gem_object_unreference(obj);
1564 }
1565 i915_verify_inactive(dev, __FILE__, __LINE__);
1566}
1567
63560396
DV		 1568static void
1569i915_gem_process_flushing_list(struct drm_device *dev,
852835f3
ZN		 1570 uint32_t flush_domains, uint32_t seqno,
1571 struct intel_ring_buffer *ring)
63560396
DV		 1572{
1573 drm_i915_private_t *dev_priv = dev->dev_private;
1574 struct drm_i915_gem_object *obj_priv, *next;
1575
1576 list_for_each_entry_safe(obj_priv, next,
1577 &dev_priv->mm.gpu_write_list,
1578 gpu_write_list) {
a8089e84 1579 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1580
1581 if ((obj->write_domain & flush_domains) ==
852835f3
ZN		 1582 obj->write_domain &&
1583 obj_priv->ring->ring_flag == ring->ring_flag) {
63560396
DV		 1584 uint32_t old_write_domain = obj->write_domain;
1585
1586 obj->write_domain = 0;
1587 list_del_init(&obj_priv->gpu_write_list);
852835f3 1588 i915_gem_object_move_to_active(obj, seqno, ring);
63560396
DV		 1589
1590 /* update the fence lru list */
007cc8ac
DV		 1591 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1592 struct drm_i915_fence_reg *reg =
1593 &dev_priv->fence_regs[obj_priv->fence_reg];
1594 list_move_tail(&reg->lru_list,
63560396 1595 &dev_priv->mm.fence_list);
007cc8ac 1596 }
63560396
DV		 1597
1598 trace_i915_gem_object_change_domain(obj,
1599 obj->read_domains,
1600 old_write_domain);
1601 }
1602 }
1603}
8187a2b7 1604
5a5a0c64 1605uint32_t
b962442e 1606i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
852835f3 1607 uint32_t flush_domains, struct intel_ring_buffer *ring)
673a394b
EA		 1608{
1609 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1610 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1611 struct drm_i915_gem_request *request;
1612 uint32_t seqno;
1613 int was_empty;
673a394b 1614
b962442e
EA		 1615 if (file_priv != NULL)
1616 i915_file_priv = file_priv->driver_priv;
1617
9a298b2a 1618 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1619 if (request == NULL)
1620 return 0;
1621
852835f3 1622 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
673a394b
EA		 1623
1624 request->seqno = seqno;
852835f3 1625 request->ring = ring;
673a394b 1626 request->emitted_jiffies = jiffies;
852835f3
ZN		 1627 was_empty = list_empty(&ring->request_list);
1628 list_add_tail(&request->list, &ring->request_list);
1629
b962442e
EA		 1630 if (i915_file_priv) {
1631 list_add_tail(&request->client_list,
1632 &i915_file_priv->mm.request_list);
1633 } else {
1634 INIT_LIST_HEAD(&request->client_list);
1635 }
673a394b 1636
ce44b0ea
EA		 1637 /* Associate any objects on the flushing list matching the write
1638 * domain we're flushing with our flush.
1639 */
63560396 1640 if (flush_domains != 0)
852835f3 1641 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
ce44b0ea 1642
f65d9421
BG		 1643 if (!dev_priv->mm.suspended) {
1644 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1645 if (was_empty)
1646 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1647 }
673a394b
EA		 1648 return seqno;
1649}
1650
1651/**
1652 * Command execution barrier
1653 *
1654 * Ensures that all commands in the ring are finished
1655 * before signalling the CPU
1656 */
3043c60c 1657static uint32_t
852835f3 1658i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1659{
673a394b 1660 uint32_t flush_domains = 0;
673a394b
EA		 1661
1662 /* The sampler always gets flushed on i965 (sigh) */
1663 if (IS_I965G(dev))
1664 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1665
1666 ring->flush(dev, ring,
1667 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1668 return flush_domains;
1669}
1670
1671/**
1672 * Moves buffers associated only with the given active seqno from the active
1673 * to inactive list, potentially freeing them.
1674 */
1675static void
1676i915_gem_retire_request(struct drm_device *dev,
1677 struct drm_i915_gem_request *request)
1678{
1679 drm_i915_private_t *dev_priv = dev->dev_private;
1680
1c5d22f7
CW		 1681 trace_i915_gem_request_retire(dev, request->seqno);
1682
673a394b
EA		 1683 /* Move any buffers on the active list that are no longer referenced
1684 * by the ringbuffer to the flushing/inactive lists as appropriate.
1685 */
5e118f41 1686 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1687 while (!list_empty(&request->ring->active_list)) {
673a394b
EA		 1688 struct drm_gem_object *obj;
1689 struct drm_i915_gem_object *obj_priv;
1690
852835f3 1691 obj_priv = list_first_entry(&request->ring->active_list,
673a394b
EA		 1692 struct drm_i915_gem_object,
1693 list);
a8089e84 1694 obj = &obj_priv->base;
673a394b
EA		 1695
1696 /* If the seqno being retired doesn't match the oldest in the
1697 * list, then the oldest in the list must still be newer than
1698 * this seqno.
1699 */
1700 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1701 goto out;
de151cf6 1702
673a394b
EA		 1703#if WATCH_LRU
1704 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1705 __func__, request->seqno, obj);
1706#endif
1707
ce44b0ea
EA		 1708 if (obj->write_domain != 0)
1709 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1710 else {
1711 /* Take a reference on the object so it won't be
1712 * freed while the spinlock is held. The list
1713 * protection for this spinlock is safe when breaking
1714 * the lock like this since the next thing we do
1715 * is just get the head of the list again.
1716 */
1717 drm_gem_object_reference(obj);
673a394b 1718 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1719 spin_unlock(&dev_priv->mm.active_list_lock);
1720 drm_gem_object_unreference(obj);
1721 spin_lock(&dev_priv->mm.active_list_lock);
1722 }
673a394b 1723 }
5e118f41
CW		 1724out:
1725 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1726}
1727
1728/**
1729 * Returns true if seq1 is later than seq2.
1730 */
22be1724 1731bool
673a394b
EA		 1732i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1733{
1734 return (int32_t)(seq1 - seq2) >= 0;
1735}
1736
1737uint32_t
852835f3 1738i915_get_gem_seqno(struct drm_device *dev,
d1b851fc 1739 struct intel_ring_buffer *ring)
673a394b 1740{
852835f3 1741 return ring->get_gem_seqno(dev, ring);
673a394b
EA		 1742}
1743
1744/**
1745 * This function clears the request list as sequence numbers are passed.
1746 */
b09a1fec
CW		 1747static void
1748i915_gem_retire_requests_ring(struct drm_device *dev,
1749 struct intel_ring_buffer *ring)
673a394b
EA		 1750{
1751 drm_i915_private_t *dev_priv = dev->dev_private;
1752 uint32_t seqno;
1753
8187a2b7 1754 if (!ring->status_page.page_addr
852835f3 1755 || list_empty(&ring->request_list))
6c0594a3
KW		 1756 return;
1757
852835f3 1758 seqno = i915_get_gem_seqno(dev, ring);
673a394b 1759
852835f3 1760 while (!list_empty(&ring->request_list)) {
673a394b
EA		 1761 struct drm_i915_gem_request *request;
1762 uint32_t retiring_seqno;
1763
852835f3 1764 request = list_first_entry(&ring->request_list,
673a394b
EA		 1765 struct drm_i915_gem_request,
1766 list);
1767 retiring_seqno = request->seqno;
1768
1769 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1770 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1771 i915_gem_retire_request(dev, request);
1772
1773 list_del(&request->list);
b962442e 1774 list_del(&request->client_list);
9a298b2a 1775 kfree(request);
673a394b
EA		 1776 } else
1777 break;
1778 }
9d34e5db
CW		 1779
1780 if (unlikely (dev_priv->trace_irq_seqno &&
1781 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1782
1783 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1784 dev_priv->trace_irq_seqno = 0;
1785 }
673a394b
EA		 1786}
1787
b09a1fec
CW		 1788void
1789i915_gem_retire_requests(struct drm_device *dev)
1790{
1791 drm_i915_private_t *dev_priv = dev->dev_private;
1792
be72615b
CW		 1793 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1794 struct drm_i915_gem_object *obj_priv, *tmp;
1795
1796 /* We must be careful that during unbind() we do not
1797 * accidentally infinitely recurse into retire requests.
1798 * Currently:
1799 * retire -> free -> unbind -> wait -> retire_ring
1800 */
1801 list_for_each_entry_safe(obj_priv, tmp,
1802 &dev_priv->mm.deferred_free_list,
1803 list)
1804 i915_gem_free_object_tail(&obj_priv->base);
1805 }
1806
b09a1fec
CW		 1807 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1808 if (HAS_BSD(dev))
1809 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1810}
1811
673a394b
EA		 1812void
1813i915_gem_retire_work_handler(struct work_struct *work)
1814{
1815 drm_i915_private_t *dev_priv;
1816 struct drm_device *dev;
1817
1818 dev_priv = container_of(work, drm_i915_private_t,
1819 mm.retire_work.work);
1820 dev = dev_priv->dev;
1821
1822 mutex_lock(&dev->struct_mutex);
b09a1fec 1823 i915_gem_retire_requests(dev);
d1b851fc 1824
6dbe2772 1825 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1826 (!list_empty(&dev_priv->render_ring.request_list) ||
1827 (HAS_BSD(dev) &&
1828 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1829 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1830 mutex_unlock(&dev->struct_mutex);
1831}
1832
5a5a0c64 1833int
852835f3
ZN		 1834i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1835 int interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1836{
1837 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1838 u32 ier;
673a394b
EA		 1839 int ret = 0;
1840
1841 BUG_ON(seqno == 0);
1842
ba1234d1 1843 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1844 return -EIO;
1845
852835f3 1846 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
bad720ff 1847 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1848 ier = I915_READ(DEIER) | I915_READ(GTIER);
1849 else
1850 ier = I915_READ(IER);
802c7eb6
JB		 1851 if (!ier) {
1852 DRM_ERROR("something (likely vbetool) disabled "
1853 "interrupts, re-enabling\n");
1854 i915_driver_irq_preinstall(dev);
1855 i915_driver_irq_postinstall(dev);
1856 }
1857
1c5d22f7
CW		 1858 trace_i915_gem_request_wait_begin(dev, seqno);
1859
852835f3 1860 ring->waiting_gem_seqno = seqno;
8187a2b7 1861 ring->user_irq_get(dev, ring);
48764bf4 1862 if (interruptible)
852835f3
ZN		 1863 ret = wait_event_interruptible(ring->irq_queue,
1864 i915_seqno_passed(
1865 ring->get_gem_seqno(dev, ring), seqno)
1866 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1867 else
852835f3
ZN		 1868 wait_event(ring->irq_queue,
1869 i915_seqno_passed(
1870 ring->get_gem_seqno(dev, ring), seqno)
1871 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1872
8187a2b7 1873 ring->user_irq_put(dev, ring);
852835f3 1874 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 1875
1876 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1877 }
ba1234d1 1878 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1879 ret = -EIO;
1880
1881 if (ret && ret != -ERESTARTSYS)
1882 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
852835f3 1883 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
673a394b
EA		 1884
1885 /* Directly dispatch request retiring. While we have the work queue
1886 * to handle this, the waiter on a request often wants an associated
1887 * buffer to have made it to the inactive list, and we would need
1888 * a separate wait queue to handle that.
1889 */
1890 if (ret == 0)
b09a1fec 1891 i915_gem_retire_requests_ring(dev, ring);
673a394b
EA		 1892
1893 return ret;
1894}
1895
48764bf4
DV		 1896/**
1897 * Waits for a sequence number to be signaled, and cleans up the
1898 * request and object lists appropriately for that event.
1899 */
1900static int
852835f3
ZN		 1901i915_wait_request(struct drm_device *dev, uint32_t seqno,
1902 struct intel_ring_buffer *ring)
48764bf4 1903{
852835f3 1904 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 1905}
1906
8187a2b7
ZN		 1907static void
1908i915_gem_flush(struct drm_device *dev,
1909 uint32_t invalidate_domains,
1910 uint32_t flush_domains)
1911{
1912 drm_i915_private_t *dev_priv = dev->dev_private;
1913 if (flush_domains & I915_GEM_DOMAIN_CPU)
1914 drm_agp_chipset_flush(dev);
1915 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1916 invalidate_domains,
1917 flush_domains);
d1b851fc
ZN		 1918
1919 if (HAS_BSD(dev))
1920 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1921 invalidate_domains,
1922 flush_domains);
8187a2b7
ZN		 1923}
1924
673a394b
EA		 1925/**
1926 * Ensures that all rendering to the object has completed and the object is
1927 * safe to unbind from the GTT or access from the CPU.
1928 */
1929static int
1930i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1931{
1932 struct drm_device *dev = obj->dev;
23010e43 1933 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1934 int ret;
1935
e47c68e9
EA		 1936 /* This function only exists to support waiting for existing rendering,
1937 * not for emitting required flushes.
673a394b 1938 */
e47c68e9 1939 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1940
1941 /* If there is rendering queued on the buffer being evicted, wait for
1942 * it.
1943 */
1944 if (obj_priv->active) {
1945#if WATCH_BUF
1946 DRM_INFO("%s: object %p wait for seqno %08x\n",
1947 __func__, obj, obj_priv->last_rendering_seqno);
1948#endif
852835f3
ZN		 1949 ret = i915_wait_request(dev,
1950 obj_priv->last_rendering_seqno, obj_priv->ring);
673a394b
EA		 1951 if (ret != 0)
1952 return ret;
1953 }
1954
1955 return 0;
1956}
1957
1958/**
1959 * Unbinds an object from the GTT aperture.
1960 */
0f973f27 1961int
673a394b
EA		 1962i915_gem_object_unbind(struct drm_gem_object *obj)
1963{
1964 struct drm_device *dev = obj->dev;
4a87b8ca 1965 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1966 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1967 int ret = 0;
1968
1969#if WATCH_BUF
1970 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1971 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1972#endif
1973 if (obj_priv->gtt_space == NULL)
1974 return 0;
1975
1976 if (obj_priv->pin_count != 0) {
1977 DRM_ERROR("Attempting to unbind pinned buffer\n");
1978 return -EINVAL;
1979 }
1980
5323fd04
EA		 1981 /* blow away mappings if mapped through GTT */
1982 i915_gem_release_mmap(obj);
1983
673a394b
EA		 1984 /* Move the object to the CPU domain to ensure that
1985 * any possible CPU writes while it's not in the GTT
1986 * are flushed when we go to remap it. This will
1987 * also ensure that all pending GPU writes are finished
1988 * before we unbind.
1989 */
e47c68e9 1990 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
8dc1775d 1991 if (ret == -ERESTARTSYS)
673a394b 1992 return ret;
8dc1775d
CW		 1993 /* Continue on if we fail due to EIO, the GPU is hung so we
1994 * should be safe and we need to cleanup or else we might
1995 * cause memory corruption through use-after-free.
1996 */
673a394b 1997
96b47b65
DV		 1998 /* release the fence reg _after_ flushing */
1999 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2000 i915_gem_clear_fence_reg(obj);
2001
673a394b
EA		 2002 if (obj_priv->agp_mem != NULL) {
2003 drm_unbind_agp(obj_priv->agp_mem);
2004 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2005 obj_priv->agp_mem = NULL;
2006 }
2007
856fa198 2008 i915_gem_object_put_pages(obj);
a32808c0 2009 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 2010
2011 if (obj_priv->gtt_space) {
2012 atomic_dec(&dev->gtt_count);
2013 atomic_sub(obj->size, &dev->gtt_memory);
2014
2015 drm_mm_put_block(obj_priv->gtt_space);
2016 obj_priv->gtt_space = NULL;
2017 }
2018
2019 /* Remove ourselves from the LRU list if present. */
4a87b8ca 2020 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 2021 if (!list_empty(&obj_priv->list))
2022 list_del_init(&obj_priv->list);
4a87b8ca 2023 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 2024
963b4836
CW		 2025 if (i915_gem_object_is_purgeable(obj_priv))
2026 i915_gem_object_truncate(obj);
2027
1c5d22f7
CW		 2028 trace_i915_gem_object_unbind(obj);
2029
8dc1775d 2030 return ret;
673a394b
EA		 2031}
2032
b47eb4a2 2033int
4df2faf4
DV		 2034i915_gpu_idle(struct drm_device *dev)
2035{
2036 drm_i915_private_t *dev_priv = dev->dev_private;
2037 bool lists_empty;
d1b851fc 2038 uint32_t seqno1, seqno2;
852835f3 2039 int ret;
4df2faf4
DV		 2040
2041 spin_lock(&dev_priv->mm.active_list_lock);
d1b851fc
ZN		 2042 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2043 list_empty(&dev_priv->render_ring.active_list) &&
2044 (!HAS_BSD(dev) ||
2045 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2046 spin_unlock(&dev_priv->mm.active_list_lock);
2047
2048 if (lists_empty)
2049 return 0;
2050
2051 /* Flush everything onto the inactive list. */
2052 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
d1b851fc 2053 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
852835f3 2054 &dev_priv->render_ring);
d1b851fc 2055 if (seqno1 == 0)
4df2faf4 2056 return -ENOMEM;
d1b851fc
ZN		 2057 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2058
2059 if (HAS_BSD(dev)) {
2060 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2061 &dev_priv->bsd_ring);
2062 if (seqno2 == 0)
2063 return -ENOMEM;
2064
2065 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2066 if (ret)
2067 return ret;
2068 }
2069
4df2faf4 2070
852835f3 2071 return ret;
4df2faf4
DV		 2072}
2073
6911a9b8 2074int
4bdadb97
CW		 2075i915_gem_object_get_pages(struct drm_gem_object *obj,
2076 gfp_t gfpmask)
673a394b 2077{
23010e43 2078 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2079 int page_count, i;
2080 struct address_space *mapping;
2081 struct inode *inode;
2082 struct page *page;
673a394b 2083
778c3544
DV		 2084 BUG_ON(obj_priv->pages_refcount
2085 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2086
856fa198 2087 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2088 return 0;
2089
2090 /* Get the list of pages out of our struct file. They'll be pinned
2091 * at this point until we release them.
2092 */
2093 page_count = obj->size / PAGE_SIZE;
856fa198 2094 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2095 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2096 if (obj_priv->pages == NULL) {
856fa198 2097 obj_priv->pages_refcount--;
673a394b
EA		 2098 return -ENOMEM;
2099 }
2100
2101 inode = obj->filp->f_path.dentry->d_inode;
2102 mapping = inode->i_mapping;
2103 for (i = 0; i < page_count; i++) {
4bdadb97 2104 page = read_cache_page_gfp(mapping, i,
985b823b 2105 GFP_HIGHUSER |
4bdadb97 2106 __GFP_COLD |
cd9f040d 2107 __GFP_RECLAIMABLE |
4bdadb97 2108 gfpmask);
1f2b1013
CW		 2109 if (IS_ERR(page))
2110 goto err_pages;
2111
856fa198 2112 obj_priv->pages[i] = page;
673a394b 2113 }
280b713b
EA		 2114
2115 if (obj_priv->tiling_mode != I915_TILING_NONE)
2116 i915_gem_object_do_bit_17_swizzle(obj);
2117
673a394b 2118 return 0;
1f2b1013
CW		 2119
2120err_pages:
2121 while (i--)
2122 page_cache_release(obj_priv->pages[i]);
2123
2124 drm_free_large(obj_priv->pages);
2125 obj_priv->pages = NULL;
2126 obj_priv->pages_refcount--;
2127 return PTR_ERR(page);
673a394b
EA		 2128}
2129
4e901fdc
EA		 2130static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2131{
2132 struct drm_gem_object *obj = reg->obj;
2133 struct drm_device *dev = obj->dev;
2134 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2135 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2136 int regnum = obj_priv->fence_reg;
2137 uint64_t val;
2138
2139 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2140 0xfffff000) << 32;
2141 val |= obj_priv->gtt_offset & 0xfffff000;
2142 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2143 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2144
2145 if (obj_priv->tiling_mode == I915_TILING_Y)
2146 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2147 val |= I965_FENCE_REG_VALID;
2148
2149 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2150}
2151
de151cf6
JB		 2152static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2153{
2154 struct drm_gem_object *obj = reg->obj;
2155 struct drm_device *dev = obj->dev;
2156 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2157 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2158 int regnum = obj_priv->fence_reg;
2159 uint64_t val;
2160
2161 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2162 0xfffff000) << 32;
2163 val |= obj_priv->gtt_offset & 0xfffff000;
2164 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2165 if (obj_priv->tiling_mode == I915_TILING_Y)
2166 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2167 val |= I965_FENCE_REG_VALID;
2168
2169 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2170}
2171
2172static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2173{
2174 struct drm_gem_object *obj = reg->obj;
2175 struct drm_device *dev = obj->dev;
2176 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2177 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2178 int regnum = obj_priv->fence_reg;
0f973f27 2179 int tile_width;
dc529a4f 2180 uint32_t fence_reg, val;
de151cf6
JB		 2181 uint32_t pitch_val;
2182
2183 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2184 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2185 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2186 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2187 return;
2188 }
2189
0f973f27
JB		 2190 if (obj_priv->tiling_mode == I915_TILING_Y &&
2191 HAS_128_BYTE_Y_TILING(dev))
2192 tile_width = 128;
de151cf6 2193 else
0f973f27
JB		 2194 tile_width = 512;
2195
2196 /* Note: pitch better be a power of two tile widths */
2197 pitch_val = obj_priv->stride / tile_width;
2198 pitch_val = ffs(pitch_val) - 1;
de151cf6 2199
c36a2a6d
DV		 2200 if (obj_priv->tiling_mode == I915_TILING_Y &&
2201 HAS_128_BYTE_Y_TILING(dev))
2202 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2203 else
2204 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2205
de151cf6
JB		 2206 val = obj_priv->gtt_offset;
2207 if (obj_priv->tiling_mode == I915_TILING_Y)
2208 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2209 val |= I915_FENCE_SIZE_BITS(obj->size);
2210 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2211 val |= I830_FENCE_REG_VALID;
2212
dc529a4f
EA		 2213 if (regnum < 8)
2214 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2215 else
2216 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2217 I915_WRITE(fence_reg, val);
de151cf6
JB		 2218}
2219
2220static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2221{
2222 struct drm_gem_object *obj = reg->obj;
2223 struct drm_device *dev = obj->dev;
2224 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2225 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2226 int regnum = obj_priv->fence_reg;
2227 uint32_t val;
2228 uint32_t pitch_val;
8d7773a3 2229 uint32_t fence_size_bits;
de151cf6 2230
8d7773a3 2231 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2232 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2233 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2234 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2235 return;
2236 }
2237
e76a16de
EA		 2238 pitch_val = obj_priv->stride / 128;
2239 pitch_val = ffs(pitch_val) - 1;
2240 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2241
de151cf6
JB		 2242 val = obj_priv->gtt_offset;
2243 if (obj_priv->tiling_mode == I915_TILING_Y)
2244 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2245 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2246 WARN_ON(fence_size_bits & ~0x00000f00);
2247 val |= fence_size_bits;
de151cf6
JB		 2248 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2249 val |= I830_FENCE_REG_VALID;
2250
2251 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2252}
2253
ae3db24a
DV		 2254static int i915_find_fence_reg(struct drm_device *dev)
2255{
2256 struct drm_i915_fence_reg *reg = NULL;
2257 struct drm_i915_gem_object *obj_priv = NULL;
2258 struct drm_i915_private *dev_priv = dev->dev_private;
2259 struct drm_gem_object *obj = NULL;
2260 int i, avail, ret;
2261
2262 /* First try to find a free reg */
2263 avail = 0;
2264 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2265 reg = &dev_priv->fence_regs[i];
2266 if (!reg->obj)
2267 return i;
2268
23010e43 2269 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2270 if (!obj_priv->pin_count)
2271 avail++;
2272 }
2273
2274 if (avail == 0)
2275 return -ENOSPC;
2276
2277 /* None available, try to steal one or wait for a user to finish */
2278 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2279 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2280 lru_list) {
2281 obj = reg->obj;
2282 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2283
2284 if (obj_priv->pin_count)
2285 continue;
2286
2287 /* found one! */
2288 i = obj_priv->fence_reg;
2289 break;
2290 }
2291
2292 BUG_ON(i == I915_FENCE_REG_NONE);
2293
2294 /* We only have a reference on obj from the active list. put_fence_reg
2295 * might drop that one, causing a use-after-free in it. So hold a
2296 * private reference to obj like the other callers of put_fence_reg
2297 * (set_tiling ioctl) do. */
2298 drm_gem_object_reference(obj);
2299 ret = i915_gem_object_put_fence_reg(obj);
2300 drm_gem_object_unreference(obj);
2301 if (ret != 0)
2302 return ret;
2303
2304 return i;
2305}
2306
de151cf6
JB		 2307/**
2308 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2309 * @obj: object to map through a fence reg
2310 *
2311 * When mapping objects through the GTT, userspace wants to be able to write
2312 * to them without having to worry about swizzling if the object is tiled.
2313 *
2314 * This function walks the fence regs looking for a free one for @obj,
2315 * stealing one if it can't find any.
2316 *
2317 * It then sets up the reg based on the object's properties: address, pitch
2318 * and tiling format.
2319 */
8c4b8c3f
CW		 2320int
2321i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2322{
2323 struct drm_device *dev = obj->dev;
79e53945 2324 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2325 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2326 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2327 int ret;
de151cf6 2328
a09ba7fa
EA		 2329 /* Just update our place in the LRU if our fence is getting used. */
2330 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2331 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2332 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2333 return 0;
2334 }
2335
de151cf6
JB		 2336 switch (obj_priv->tiling_mode) {
2337 case I915_TILING_NONE:
2338 WARN(1, "allocating a fence for non-tiled object?\n");
2339 break;
2340 case I915_TILING_X:
0f973f27
JB		 2341 if (!obj_priv->stride)
2342 return -EINVAL;
2343 WARN((obj_priv->stride & (512 - 1)),
2344 "object 0x%08x is X tiled but has non-512B pitch\n",
2345 obj_priv->gtt_offset);
de151cf6
JB		 2346 break;
2347 case I915_TILING_Y:
0f973f27
JB		 2348 if (!obj_priv->stride)
2349 return -EINVAL;
2350 WARN((obj_priv->stride & (128 - 1)),
2351 "object 0x%08x is Y tiled but has non-128B pitch\n",
2352 obj_priv->gtt_offset);
de151cf6
JB		 2353 break;
2354 }
2355
ae3db24a
DV		 2356 ret = i915_find_fence_reg(dev);
2357 if (ret < 0)
2358 return ret;
de151cf6 2359
ae3db24a
DV		 2360 obj_priv->fence_reg = ret;
2361 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2362 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2363
de151cf6
JB		 2364 reg->obj = obj;
2365
e259befd
CW		 2366 switch (INTEL_INFO(dev)->gen) {
2367 case 6:
4e901fdc 2368 sandybridge_write_fence_reg(reg);
e259befd
CW		 2369 break;
2370 case 5:
2371 case 4:
de151cf6 2372 i965_write_fence_reg(reg);
e259befd
CW		 2373 break;
2374 case 3:
de151cf6 2375 i915_write_fence_reg(reg);
e259befd
CW		 2376 break;
2377 case 2:
de151cf6 2378 i830_write_fence_reg(reg);
e259befd
CW		 2379 break;
2380 }
d9ddcb96 2381
ae3db24a
DV		 2382 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2383 obj_priv->tiling_mode);
1c5d22f7 2384
d9ddcb96 2385 return 0;
de151cf6
JB		 2386}
2387
2388/**
2389 * i915_gem_clear_fence_reg - clear out fence register info
2390 * @obj: object to clear
2391 *
2392 * Zeroes out the fence register itself and clears out the associated
2393 * data structures in dev_priv and obj_priv.
2394 */
2395static void
2396i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2397{
2398 struct drm_device *dev = obj->dev;
79e53945 2399 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2400 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2401 struct drm_i915_fence_reg *reg =
2402 &dev_priv->fence_regs[obj_priv->fence_reg];
e259befd 2403 uint32_t fence_reg;
de151cf6 2404
e259befd
CW		 2405 switch (INTEL_INFO(dev)->gen) {
2406 case 6:
4e901fdc
EA		 2407 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2408 (obj_priv->fence_reg * 8), 0);
e259befd
CW		 2409 break;
2410 case 5:
2411 case 4:
de151cf6 2412 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
e259befd
CW		 2413 break;
2414 case 3:
9b74f734 2415 if (obj_priv->fence_reg >= 8)
e259befd 2416 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
dc529a4f 2417 else
e259befd
CW		 2418 case 2:
2419 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
dc529a4f
EA		 2420
2421 I915_WRITE(fence_reg, 0);
e259befd 2422 break;
dc529a4f 2423 }
de151cf6 2424
007cc8ac 2425 reg->obj = NULL;
de151cf6 2426 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2427 list_del_init(&reg->lru_list);
de151cf6
JB		 2428}
2429
52dc7d32
CW		 2430/**
2431 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2432 * to the buffer to finish, and then resets the fence register.
2433 * @obj: tiled object holding a fence register.
2434 *
2435 * Zeroes out the fence register itself and clears out the associated
2436 * data structures in dev_priv and obj_priv.
2437 */
2438int
2439i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2440{
2441 struct drm_device *dev = obj->dev;
23010e43 2442 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2443
2444 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2445 return 0;
2446
10ae9bd2
DV		 2447 /* If we've changed tiling, GTT-mappings of the object
2448 * need to re-fault to ensure that the correct fence register
2449 * setup is in place.
2450 */
2451 i915_gem_release_mmap(obj);
2452
52dc7d32
CW		 2453 /* On the i915, GPU access to tiled buffers is via a fence,
2454 * therefore we must wait for any outstanding access to complete
2455 * before clearing the fence.
2456 */
2457 if (!IS_I965G(dev)) {
2458 int ret;
2459
2dafb1e0
CW		 2460 ret = i915_gem_object_flush_gpu_write_domain(obj);
2461 if (ret != 0)
2462 return ret;
2463
52dc7d32
CW		 2464 ret = i915_gem_object_wait_rendering(obj);
2465 if (ret != 0)
2466 return ret;
2467 }
2468
4a726612 2469 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2470 i915_gem_clear_fence_reg (obj);
2471
2472 return 0;
2473}
2474
673a394b
EA		 2475/**
2476 * Finds free space in the GTT aperture and binds the object there.
2477 */
2478static int
2479i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2480{
2481 struct drm_device *dev = obj->dev;
2482 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2483 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2484 struct drm_mm_node *free_space;
4bdadb97 2485 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2486 int ret;
673a394b 2487
bb6baf76 2488 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2489 DRM_ERROR("Attempting to bind a purgeable object\n");
2490 return -EINVAL;
2491 }
2492
673a394b 2493 if (alignment == 0)
0f973f27 2494 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2495 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2496 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2497 return -EINVAL;
2498 }
2499
654fc607
CW		 2500 /* If the object is bigger than the entire aperture, reject it early
2501 * before evicting everything in a vain attempt to find space.
2502 */
2503 if (obj->size > dev->gtt_total) {
2504 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2505 return -E2BIG;
2506 }
2507
673a394b
EA		 2508 search_free:
2509 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2510 obj->size, alignment, 0);
2511 if (free_space != NULL) {
2512 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2513 alignment);
db3307a9 2514 if (obj_priv->gtt_space != NULL)
673a394b 2515 obj_priv->gtt_offset = obj_priv->gtt_space->start;
673a394b
EA		 2516 }
2517 if (obj_priv->gtt_space == NULL) {
2518 /* If the gtt is empty and we're still having trouble
2519 * fitting our object in, we're out of memory.
2520 */
2521#if WATCH_LRU
2522 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2523#endif
0108a3ed 2524 ret = i915_gem_evict_something(dev, obj->size, alignment);
9731129c 2525 if (ret)
673a394b 2526 return ret;
9731129c 2527
673a394b
EA		 2528 goto search_free;
2529 }
2530
2531#if WATCH_BUF
cfd43c02 2532 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2533 obj->size, obj_priv->gtt_offset);
2534#endif
4bdadb97 2535 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2536 if (ret) {
2537 drm_mm_put_block(obj_priv->gtt_space);
2538 obj_priv->gtt_space = NULL;
07f73f69
CW		 2539
2540 if (ret == -ENOMEM) {
2541 /* first try to clear up some space from the GTT */
0108a3ed
DV		 2542 ret = i915_gem_evict_something(dev, obj->size,
2543 alignment);
07f73f69 2544 if (ret) {
07f73f69 2545 /* now try to shrink everyone else */
4bdadb97
CW		 2546 if (gfpmask) {
2547 gfpmask = 0;
2548 goto search_free;
07f73f69
CW		 2549 }
2550
2551 return ret;
2552 }
2553
2554 goto search_free;
2555 }
2556
673a394b
EA		 2557 return ret;
2558 }
2559
673a394b
EA		 2560 /* Create an AGP memory structure pointing at our pages, and bind it
2561 * into the GTT.
2562 */
2563 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2564 obj_priv->pages,
07f73f69 2565 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2566 obj_priv->gtt_offset,
2567 obj_priv->agp_type);
673a394b 2568 if (obj_priv->agp_mem == NULL) {
856fa198 2569 i915_gem_object_put_pages(obj);
673a394b
EA		 2570 drm_mm_put_block(obj_priv->gtt_space);
2571 obj_priv->gtt_space = NULL;
07f73f69 2572
0108a3ed 2573 ret = i915_gem_evict_something(dev, obj->size, alignment);
9731129c 2574 if (ret)
07f73f69 2575 return ret;
07f73f69
CW		 2576
2577 goto search_free;
673a394b
EA		 2578 }
2579 atomic_inc(&dev->gtt_count);
2580 atomic_add(obj->size, &dev->gtt_memory);
2581
bf1a1092
CW		 2582 /* keep track of bounds object by adding it to the inactive list */
2583 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2584
673a394b
EA		 2585 /* Assert that the object is not currently in any GPU domain. As it
2586 * wasn't in the GTT, there shouldn't be any way it could have been in
2587 * a GPU cache
2588 */
21d509e3
CW		 2589 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2590 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2591
1c5d22f7
CW		 2592 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2593
673a394b
EA		 2594 return 0;
2595}
2596
2597void
2598i915_gem_clflush_object(struct drm_gem_object *obj)
2599{
23010e43 2600 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2601
2602 /* If we don't have a page list set up, then we're not pinned
2603 * to GPU, and we can ignore the cache flush because it'll happen
2604 * again at bind time.
2605 */
856fa198 2606 if (obj_priv->pages == NULL)
673a394b
EA		 2607 return;
2608
1c5d22f7 2609 trace_i915_gem_object_clflush(obj);
cfa16a0d 2610
856fa198 2611 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2612}
2613
e47c68e9 2614/** Flushes any GPU write domain for the object if it's dirty. */
2dafb1e0 2615static int
e47c68e9
EA		 2616i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2617{
2618 struct drm_device *dev = obj->dev;
1c5d22f7 2619 uint32_t old_write_domain;
852835f3 2620 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
e47c68e9
EA		 2621
2622 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2dafb1e0 2623 return 0;
e47c68e9
EA		 2624
2625 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2626 old_write_domain = obj->write_domain;
e47c68e9 2627 i915_gem_flush(dev, 0, obj->write_domain);
2dafb1e0
CW		 2628 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2629 return -ENOMEM;
1c5d22f7
CW		 2630
2631 trace_i915_gem_object_change_domain(obj,
2632 obj->read_domains,
2633 old_write_domain);
2dafb1e0 2634 return 0;
e47c68e9
EA		 2635}
2636
2637/** Flushes the GTT write domain for the object if it's dirty. */
2638static void
2639i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2640{
1c5d22f7
CW		 2641 uint32_t old_write_domain;
2642
e47c68e9
EA		 2643 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2644 return;
2645
2646 /* No actual flushing is required for the GTT write domain. Writes
2647 * to it immediately go to main memory as far as we know, so there's
2648 * no chipset flush. It also doesn't land in render cache.
2649 */
1c5d22f7 2650 old_write_domain = obj->write_domain;
e47c68e9 2651 obj->write_domain = 0;
1c5d22f7
CW		 2652
2653 trace_i915_gem_object_change_domain(obj,
2654 obj->read_domains,
2655 old_write_domain);
e47c68e9
EA		 2656}
2657
2658/** Flushes the CPU write domain for the object if it's dirty. */
2659static void
2660i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2661{
2662 struct drm_device *dev = obj->dev;
1c5d22f7 2663 uint32_t old_write_domain;
e47c68e9
EA		 2664
2665 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2666 return;
2667
2668 i915_gem_clflush_object(obj);
2669 drm_agp_chipset_flush(dev);
1c5d22f7 2670 old_write_domain = obj->write_domain;
e47c68e9 2671 obj->write_domain = 0;
1c5d22f7
CW		 2672
2673 trace_i915_gem_object_change_domain(obj,
2674 obj->read_domains,
2675 old_write_domain);
e47c68e9
EA		 2676}
2677
2dafb1e0 2678int
6b95a207
KH		 2679i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2680{
2dafb1e0
CW		 2681 int ret = 0;
2682
6b95a207
KH		 2683 switch (obj->write_domain) {
2684 case I915_GEM_DOMAIN_GTT:
2685 i915_gem_object_flush_gtt_write_domain(obj);
2686 break;
2687 case I915_GEM_DOMAIN_CPU:
2688 i915_gem_object_flush_cpu_write_domain(obj);
2689 break;
2690 default:
2dafb1e0 2691 ret = i915_gem_object_flush_gpu_write_domain(obj);
6b95a207
KH		 2692 break;
2693 }
2dafb1e0
CW		 2694
2695 return ret;
6b95a207
KH		 2696}
2697
2ef7eeaa
EA		 2698/**
2699 * Moves a single object to the GTT read, and possibly write domain.
2700 *
2701 * This function returns when the move is complete, including waiting on
2702 * flushes to occur.
2703 */
79e53945 2704int
2ef7eeaa
EA		 2705i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2706{
23010e43 2707 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2708 uint32_t old_write_domain, old_read_domains;
e47c68e9 2709 int ret;
2ef7eeaa 2710
02354392
EA		 2711 /* Not valid to be called on unbound objects. */
2712 if (obj_priv->gtt_space == NULL)
2713 return -EINVAL;
2714
2dafb1e0
CW		 2715 ret = i915_gem_object_flush_gpu_write_domain(obj);
2716 if (ret != 0)
2717 return ret;
2718
e47c68e9
EA		 2719 /* Wait on any GPU rendering and flushing to occur. */
2720 ret = i915_gem_object_wait_rendering(obj);
2721 if (ret != 0)
2722 return ret;
2723
1c5d22f7
CW		 2724 old_write_domain = obj->write_domain;
2725 old_read_domains = obj->read_domains;
2726
e47c68e9
EA		 2727 /* If we're writing through the GTT domain, then CPU and GPU caches
2728 * will need to be invalidated at next use.
2ef7eeaa 2729 */
e47c68e9
EA		 2730 if (write)
2731 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2732
e47c68e9 2733 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2734
e47c68e9
EA		 2735 /* It should now be out of any other write domains, and we can update
2736 * the domain values for our changes.
2737 */
2738 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2739 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2740 if (write) {
2741 obj->write_domain = I915_GEM_DOMAIN_GTT;
2742 obj_priv->dirty = 1;
2ef7eeaa
EA		 2743 }
2744
1c5d22f7
CW		 2745 trace_i915_gem_object_change_domain(obj,
2746 old_read_domains,
2747 old_write_domain);
2748
e47c68e9
EA		 2749 return 0;
2750}
2751
b9241ea3
ZW		 2752/*
2753 * Prepare buffer for display plane. Use uninterruptible for possible flush
2754 * wait, as in modesetting process we're not supposed to be interrupted.
2755 */
2756int
2757i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2758{
2759 struct drm_device *dev = obj->dev;
23010e43 2760 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2761 uint32_t old_write_domain, old_read_domains;
2762 int ret;
2763
2764 /* Not valid to be called on unbound objects. */
2765 if (obj_priv->gtt_space == NULL)
2766 return -EINVAL;
2767
2dafb1e0
CW		 2768 ret = i915_gem_object_flush_gpu_write_domain(obj);
2769 if (ret)
2770 return ret;
b9241ea3
ZW		 2771
2772 /* Wait on any GPU rendering and flushing to occur. */
2773 if (obj_priv->active) {
2774#if WATCH_BUF
2775 DRM_INFO("%s: object %p wait for seqno %08x\n",
2776 __func__, obj, obj_priv->last_rendering_seqno);
2777#endif
852835f3
ZN		 2778 ret = i915_do_wait_request(dev,
2779 obj_priv->last_rendering_seqno,
2780 0,
2781 obj_priv->ring);
b9241ea3
ZW		 2782 if (ret != 0)
2783 return ret;
2784 }
2785
b118c1e3
CW		 2786 i915_gem_object_flush_cpu_write_domain(obj);
2787
b9241ea3
ZW		 2788 old_write_domain = obj->write_domain;
2789 old_read_domains = obj->read_domains;
2790
b9241ea3
ZW		 2791 /* It should now be out of any other write domains, and we can update
2792 * the domain values for our changes.
2793 */
2794 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
b118c1e3 2795 obj->read_domains = I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 2796 obj->write_domain = I915_GEM_DOMAIN_GTT;
2797 obj_priv->dirty = 1;
2798
2799 trace_i915_gem_object_change_domain(obj,
2800 old_read_domains,
2801 old_write_domain);
2802
2803 return 0;
2804}
2805
e47c68e9
EA		 2806/**
2807 * Moves a single object to the CPU read, and possibly write domain.
2808 *
2809 * This function returns when the move is complete, including waiting on
2810 * flushes to occur.
2811 */
2812static int
2813i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2814{
1c5d22f7 2815 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2816 int ret;
2817
2dafb1e0
CW		 2818 ret = i915_gem_object_flush_gpu_write_domain(obj);
2819 if (ret)
2820 return ret;
2821
2ef7eeaa 2822 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2823 ret = i915_gem_object_wait_rendering(obj);
2824 if (ret != 0)
2825 return ret;
2ef7eeaa 2826
e47c68e9 2827 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2828
e47c68e9
EA		 2829 /* If we have a partially-valid cache of the object in the CPU,
2830 * finish invalidating it and free the per-page flags.
2ef7eeaa 2831 */
e47c68e9 2832 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2833
1c5d22f7
CW		 2834 old_write_domain = obj->write_domain;
2835 old_read_domains = obj->read_domains;
2836
e47c68e9
EA		 2837 /* Flush the CPU cache if it's still invalid. */
2838 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2839 i915_gem_clflush_object(obj);
2ef7eeaa 2840
e47c68e9 2841 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2842 }
2843
2844 /* It should now be out of any other write domains, and we can update
2845 * the domain values for our changes.
2846 */
e47c68e9
EA		 2847 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2848
2849 /* If we're writing through the CPU, then the GPU read domains will
2850 * need to be invalidated at next use.
2851 */
2852 if (write) {
2853 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2854 obj->write_domain = I915_GEM_DOMAIN_CPU;
2855 }
2ef7eeaa 2856
1c5d22f7
CW		 2857 trace_i915_gem_object_change_domain(obj,
2858 old_read_domains,
2859 old_write_domain);
2860
2ef7eeaa
EA		 2861 return 0;
2862}
2863
673a394b
EA		 2864/*
2865 * Set the next domain for the specified object. This
2866 * may not actually perform the necessary flushing/invaliding though,
2867 * as that may want to be batched with other set_domain operations
2868 *
2869 * This is (we hope) the only really tricky part of gem. The goal
2870 * is fairly simple -- track which caches hold bits of the object
2871 * and make sure they remain coherent. A few concrete examples may
2872 * help to explain how it works. For shorthand, we use the notation
2873 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2874 * a pair of read and write domain masks.
2875 *
2876 * Case 1: the batch buffer
2877 *
2878 * 1. Allocated
2879 * 2. Written by CPU
2880 * 3. Mapped to GTT
2881 * 4. Read by GPU
2882 * 5. Unmapped from GTT
2883 * 6. Freed
2884 *
2885 * Let's take these a step at a time
2886 *
2887 * 1. Allocated
2888 * Pages allocated from the kernel may still have
2889 * cache contents, so we set them to (CPU, CPU) always.
2890 * 2. Written by CPU (using pwrite)
2891 * The pwrite function calls set_domain (CPU, CPU) and
2892 * this function does nothing (as nothing changes)
2893 * 3. Mapped by GTT
2894 * This function asserts that the object is not
2895 * currently in any GPU-based read or write domains
2896 * 4. Read by GPU
2897 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2898 * As write_domain is zero, this function adds in the
2899 * current read domains (CPU+COMMAND, 0).
2900 * flush_domains is set to CPU.
2901 * invalidate_domains is set to COMMAND
2902 * clflush is run to get data out of the CPU caches
2903 * then i915_dev_set_domain calls i915_gem_flush to
2904 * emit an MI_FLUSH and drm_agp_chipset_flush
2905 * 5. Unmapped from GTT
2906 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2907 * flush_domains and invalidate_domains end up both zero
2908 * so no flushing/invalidating happens
2909 * 6. Freed
2910 * yay, done
2911 *
2912 * Case 2: The shared render buffer
2913 *
2914 * 1. Allocated
2915 * 2. Mapped to GTT
2916 * 3. Read/written by GPU
2917 * 4. set_domain to (CPU,CPU)
2918 * 5. Read/written by CPU
2919 * 6. Read/written by GPU
2920 *
2921 * 1. Allocated
2922 * Same as last example, (CPU, CPU)
2923 * 2. Mapped to GTT
2924 * Nothing changes (assertions find that it is not in the GPU)
2925 * 3. Read/written by GPU
2926 * execbuffer calls set_domain (RENDER, RENDER)
2927 * flush_domains gets CPU
2928 * invalidate_domains gets GPU
2929 * clflush (obj)
2930 * MI_FLUSH and drm_agp_chipset_flush
2931 * 4. set_domain (CPU, CPU)
2932 * flush_domains gets GPU
2933 * invalidate_domains gets CPU
2934 * wait_rendering (obj) to make sure all drawing is complete.
2935 * This will include an MI_FLUSH to get the data from GPU
2936 * to memory
2937 * clflush (obj) to invalidate the CPU cache
2938 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2939 * 5. Read/written by CPU
2940 * cache lines are loaded and dirtied
2941 * 6. Read written by GPU
2942 * Same as last GPU access
2943 *
2944 * Case 3: The constant buffer
2945 *
2946 * 1. Allocated
2947 * 2. Written by CPU
2948 * 3. Read by GPU
2949 * 4. Updated (written) by CPU again
2950 * 5. Read by GPU
2951 *
2952 * 1. Allocated
2953 * (CPU, CPU)
2954 * 2. Written by CPU
2955 * (CPU, CPU)
2956 * 3. Read by GPU
2957 * (CPU+RENDER, 0)
2958 * flush_domains = CPU
2959 * invalidate_domains = RENDER
2960 * clflush (obj)
2961 * MI_FLUSH
2962 * drm_agp_chipset_flush
2963 * 4. Updated (written) by CPU again
2964 * (CPU, CPU)
2965 * flush_domains = 0 (no previous write domain)
2966 * invalidate_domains = 0 (no new read domains)
2967 * 5. Read by GPU
2968 * (CPU+RENDER, 0)
2969 * flush_domains = CPU
2970 * invalidate_domains = RENDER
2971 * clflush (obj)
2972 * MI_FLUSH
2973 * drm_agp_chipset_flush
2974 */
c0d90829 2975static void
8b0e378a 2976i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 2977{
2978 struct drm_device *dev = obj->dev;
88f356b7 2979 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2980 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2981 uint32_t invalidate_domains = 0;
2982 uint32_t flush_domains = 0;
1c5d22f7 2983 uint32_t old_read_domains;
e47c68e9 2984
8b0e378a
EA		 2985 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2986 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 2987
652c393a
JB		 2988 intel_mark_busy(dev, obj);
2989
673a394b
EA		 2990#if WATCH_BUF
2991 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2992 __func__, obj,
8b0e378a
EA		 2993 obj->read_domains, obj->pending_read_domains,
2994 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 2995#endif
2996 /*
2997 * If the object isn't moving to a new write domain,
2998 * let the object stay in multiple read domains
2999 */
8b0e378a
EA		 3000 if (obj->pending_write_domain == 0)
3001 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3002 else
3003 obj_priv->dirty = 1;
3004
3005 /*
3006 * Flush the current write domain if
3007 * the new read domains don't match. Invalidate
3008 * any read domains which differ from the old
3009 * write domain
3010 */
8b0e378a
EA		 3011 if (obj->write_domain &&
3012 obj->write_domain != obj->pending_read_domains) {
673a394b 3013 flush_domains |= obj->write_domain;
8b0e378a
EA		 3014 invalidate_domains |=
3015 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3016 }
3017 /*
3018 * Invalidate any read caches which may have
3019 * stale data. That is, any new read domains.
3020 */
8b0e378a 3021 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3022 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3023#if WATCH_BUF
3024 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3025 __func__, flush_domains, invalidate_domains);
3026#endif
673a394b
EA		 3027 i915_gem_clflush_object(obj);
3028 }
3029
1c5d22f7
CW		 3030 old_read_domains = obj->read_domains;
3031
efbeed96
EA		 3032 /* The actual obj->write_domain will be updated with
3033 * pending_write_domain after we emit the accumulated flush for all
3034 * of our domain changes in execbuffers (which clears objects'
3035 * write_domains). So if we have a current write domain that we
3036 * aren't changing, set pending_write_domain to that.
3037 */
3038 if (flush_domains == 0 && obj->pending_write_domain == 0)
3039 obj->pending_write_domain = obj->write_domain;
8b0e378a 3040 obj->read_domains = obj->pending_read_domains;
673a394b 3041
88f356b7
CW		 3042 if (flush_domains & I915_GEM_GPU_DOMAINS) {
3043 if (obj_priv->ring == &dev_priv->render_ring)
3044 dev_priv->flush_rings |= FLUSH_RENDER_RING;
3045 else if (obj_priv->ring == &dev_priv->bsd_ring)
3046 dev_priv->flush_rings |= FLUSH_BSD_RING;
3047 }
3048
673a394b
EA		 3049 dev->invalidate_domains |= invalidate_domains;
3050 dev->flush_domains |= flush_domains;
3051#if WATCH_BUF
3052 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3053 __func__,
3054 obj->read_domains, obj->write_domain,
3055 dev->invalidate_domains, dev->flush_domains);
3056#endif
1c5d22f7
CW		 3057
3058 trace_i915_gem_object_change_domain(obj,
3059 old_read_domains,
3060 obj->write_domain);
673a394b
EA		 3061}
3062
3063/**
e47c68e9 3064 * Moves the object from a partially CPU read to a full one.
673a394b 3065 *
e47c68e9
EA		 3066 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3067 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3068 */
e47c68e9
EA		 3069static void
3070i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3071{
23010e43 3072 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3073
e47c68e9
EA		 3074 if (!obj_priv->page_cpu_valid)
3075 return;
3076
3077 /* If we're partially in the CPU read domain, finish moving it in.
3078 */
3079 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3080 int i;
3081
3082 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3083 if (obj_priv->page_cpu_valid[i])
3084 continue;
856fa198 3085 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3086 }
e47c68e9
EA		 3087 }
3088
3089 /* Free the page_cpu_valid mappings which are now stale, whether
3090 * or not we've got I915_GEM_DOMAIN_CPU.
3091 */
9a298b2a 3092 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3093 obj_priv->page_cpu_valid = NULL;
3094}
3095
3096/**
3097 * Set the CPU read domain on a range of the object.
3098 *
3099 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3100 * not entirely valid. The page_cpu_valid member of the object flags which
3101 * pages have been flushed, and will be respected by
3102 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3103 * of the whole object.
3104 *
3105 * This function returns when the move is complete, including waiting on
3106 * flushes to occur.
3107 */
3108static int
3109i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3110 uint64_t offset, uint64_t size)
3111{
23010e43 3112 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3113 uint32_t old_read_domains;
e47c68e9 3114 int i, ret;
673a394b 3115
e47c68e9
EA		 3116 if (offset == 0 && size == obj->size)
3117 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3118
2dafb1e0
CW		 3119 ret = i915_gem_object_flush_gpu_write_domain(obj);
3120 if (ret)
3121 return ret;
3122
e47c68e9 3123 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3124 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3125 if (ret != 0)
6a47baa6 3126 return ret;
e47c68e9
EA		 3127 i915_gem_object_flush_gtt_write_domain(obj);
3128
3129 /* If we're already fully in the CPU read domain, we're done. */
3130 if (obj_priv->page_cpu_valid == NULL &&
3131 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3132 return 0;
673a394b 3133
e47c68e9
EA		 3134 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3135 * newly adding I915_GEM_DOMAIN_CPU
3136 */
673a394b 3137 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3138 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3139 GFP_KERNEL);
e47c68e9
EA		 3140 if (obj_priv->page_cpu_valid == NULL)
3141 return -ENOMEM;
3142 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3143 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3144
3145 /* Flush the cache on any pages that are still invalid from the CPU's
3146 * perspective.
3147 */
e47c68e9
EA		 3148 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3149 i++) {
673a394b
EA		 3150 if (obj_priv->page_cpu_valid[i])
3151 continue;
3152
856fa198 3153 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3154
3155 obj_priv->page_cpu_valid[i] = 1;
3156 }
3157
e47c68e9
EA		 3158 /* It should now be out of any other write domains, and we can update
3159 * the domain values for our changes.
3160 */
3161 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3162
1c5d22f7 3163 old_read_domains = obj->read_domains;
e47c68e9
EA		 3164 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3165
1c5d22f7
CW		 3166 trace_i915_gem_object_change_domain(obj,
3167 old_read_domains,
3168 obj->write_domain);
3169
673a394b
EA		 3170 return 0;
3171}
3172
673a394b
EA		 3173/**
3174 * Pin an object to the GTT and evaluate the relocations landing in it.
3175 */
3176static int
3177i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3178 struct drm_file *file_priv,
76446cac 3179 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3180 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3181{
3182 struct drm_device *dev = obj->dev;
0839ccb8 3183 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3184 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3185 int i, ret;
0839ccb8 3186 void __iomem *reloc_page;
76446cac
JB		 3187 bool need_fence;
3188
3189 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3190 obj_priv->tiling_mode != I915_TILING_NONE;
3191
3192 /* Check fence reg constraints and rebind if necessary */
808b24d6
CW		 3193 if (need_fence &&
3194 !i915_gem_object_fence_offset_ok(obj,
3195 obj_priv->tiling_mode)) {
3196 ret = i915_gem_object_unbind(obj);
3197 if (ret)
3198 return ret;
3199 }
673a394b
EA		 3200
3201 /* Choose the GTT offset for our buffer and put it there. */
3202 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3203 if (ret)
3204 return ret;
3205
76446cac
JB		 3206 /*
3207 * Pre-965 chips need a fence register set up in order to
3208 * properly handle blits to/from tiled surfaces.
3209 */
3210 if (need_fence) {
3211 ret = i915_gem_object_get_fence_reg(obj);
3212 if (ret != 0) {
76446cac
JB		 3213 i915_gem_object_unpin(obj);
3214 return ret;
3215 }
3216 }
3217
673a394b
EA		 3218 entry->offset = obj_priv->gtt_offset;
3219
673a394b
EA		 3220 /* Apply the relocations, using the GTT aperture to avoid cache
3221 * flushing requirements.
3222 */
3223 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3224 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3225 struct drm_gem_object *target_obj;
3226 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3227 uint32_t reloc_val, reloc_offset;
3228 uint32_t __iomem *reloc_entry;
673a394b 3229
673a394b 3230 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3231 reloc->target_handle);
673a394b
EA		 3232 if (target_obj == NULL) {
3233 i915_gem_object_unpin(obj);
bf79cb91 3234 return -ENOENT;
673a394b 3235 }
23010e43 3236 target_obj_priv = to_intel_bo(target_obj);
673a394b 3237
8542a0bb
CW		 3238#if WATCH_RELOC
3239 DRM_INFO("%s: obj %p offset %08x target %d "
3240 "read %08x write %08x gtt %08x "
3241 "presumed %08x delta %08x\n",
3242 __func__,
3243 obj,
3244 (int) reloc->offset,
3245 (int) reloc->target_handle,
3246 (int) reloc->read_domains,
3247 (int) reloc->write_domain,
3248 (int) target_obj_priv->gtt_offset,
3249 (int) reloc->presumed_offset,
3250 reloc->delta);
3251#endif
3252
673a394b
EA		 3253 /* The target buffer should have appeared before us in the
3254 * exec_object list, so it should have a GTT space bound by now.
3255 */
3256 if (target_obj_priv->gtt_space == NULL) {
3257 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3258 reloc->target_handle);
673a394b
EA		 3259 drm_gem_object_unreference(target_obj);
3260 i915_gem_object_unpin(obj);
3261 return -EINVAL;
3262 }
3263
8542a0bb 3264 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3265 if (reloc->write_domain & (reloc->write_domain - 1)) {
3266 DRM_ERROR("reloc with multiple write domains: "
3267 "obj %p target %d offset %d "
3268 "read %08x write %08x",
3269 obj, reloc->target_handle,
3270 (int) reloc->offset,
3271 reloc->read_domains,
3272 reloc->write_domain);
929f49bf
JL		 3273 drm_gem_object_unreference(target_obj);
3274 i915_gem_object_unpin(obj);
16edd550
DV		 3275 return -EINVAL;
3276 }
40a5f0de
EA		 3277 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3278 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3279 DRM_ERROR("reloc with read/write CPU domains: "
3280 "obj %p target %d offset %d "
3281 "read %08x write %08x",
40a5f0de
EA		 3282 obj, reloc->target_handle,
3283 (int) reloc->offset,
3284 reloc->read_domains,
3285 reloc->write_domain);
491152b8
CW		 3286 drm_gem_object_unreference(target_obj);
3287 i915_gem_object_unpin(obj);
e47c68e9
EA		 3288 return -EINVAL;
3289 }
40a5f0de
EA		 3290 if (reloc->write_domain && target_obj->pending_write_domain &&
3291 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3292 DRM_ERROR("Write domain conflict: "
3293 "obj %p target %d offset %d "
3294 "new %08x old %08x\n",
40a5f0de
EA		 3295 obj, reloc->target_handle,
3296 (int) reloc->offset,
3297 reloc->write_domain,
673a394b
EA		 3298 target_obj->pending_write_domain);
3299 drm_gem_object_unreference(target_obj);
3300 i915_gem_object_unpin(obj);
3301 return -EINVAL;
3302 }
3303
40a5f0de
EA		 3304 target_obj->pending_read_domains |= reloc->read_domains;
3305 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3306
3307 /* If the relocation already has the right value in it, no
3308 * more work needs to be done.
3309 */
40a5f0de 3310 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3311 drm_gem_object_unreference(target_obj);
3312 continue;
3313 }
3314
8542a0bb
CW		 3315 /* Check that the relocation address is valid... */
3316 if (reloc->offset > obj->size - 4) {
3317 DRM_ERROR("Relocation beyond object bounds: "
3318 "obj %p target %d offset %d size %d.\n",
3319 obj, reloc->target_handle,
3320 (int) reloc->offset, (int) obj->size);
3321 drm_gem_object_unreference(target_obj);
3322 i915_gem_object_unpin(obj);
3323 return -EINVAL;
3324 }
3325 if (reloc->offset & 3) {
3326 DRM_ERROR("Relocation not 4-byte aligned: "
3327 "obj %p target %d offset %d.\n",
3328 obj, reloc->target_handle,
3329 (int) reloc->offset);
3330 drm_gem_object_unreference(target_obj);
3331 i915_gem_object_unpin(obj);
3332 return -EINVAL;
3333 }
3334
3335 /* and points to somewhere within the target object. */
3336 if (reloc->delta >= target_obj->size) {
3337 DRM_ERROR("Relocation beyond target object bounds: "
3338 "obj %p target %d delta %d size %d.\n",
3339 obj, reloc->target_handle,
3340 (int) reloc->delta, (int) target_obj->size);
3341 drm_gem_object_unreference(target_obj);
3342 i915_gem_object_unpin(obj);
3343 return -EINVAL;
3344 }
3345
2ef7eeaa
EA		 3346 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3347 if (ret != 0) {
3348 drm_gem_object_unreference(target_obj);
3349 i915_gem_object_unpin(obj);
3350 return -EINVAL;
673a394b
EA		 3351 }
3352
3353 /* Map the page containing the relocation we're going to
3354 * perform.
3355 */
40a5f0de 3356 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3357 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3358 (reloc_offset &
fca3ec01
CW		 3359 ~(PAGE_SIZE - 1)),
3360 KM_USER0);
3043c60c 3361 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3362 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3363 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3364
3365#if WATCH_BUF
3366 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3367 obj, (unsigned int) reloc->offset,
673a394b
EA		 3368 readl(reloc_entry), reloc_val);
3369#endif
3370 writel(reloc_val, reloc_entry);
fca3ec01 3371 io_mapping_unmap_atomic(reloc_page, KM_USER0);
673a394b 3372
40a5f0de
EA		 3373 /* The updated presumed offset for this entry will be
3374 * copied back out to the user.
673a394b 3375 */
40a5f0de 3376 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3377
3378 drm_gem_object_unreference(target_obj);
3379 }
3380
673a394b
EA		 3381#if WATCH_BUF
3382 if (0)
3383 i915_gem_dump_object(obj, 128, __func__, ~0);
3384#endif
3385 return 0;
3386}
3387
673a394b
EA		 3388/* Throttle our rendering by waiting until the ring has completed our requests
3389 * emitted over 20 msec ago.
3390 *
b962442e
EA		 3391 * Note that if we were to use the current jiffies each time around the loop,
3392 * we wouldn't escape the function with any frames outstanding if the time to
3393 * render a frame was over 20ms.
3394 *
673a394b
EA		 3395 * This should get us reasonable parallelism between CPU and GPU but also
3396 * relatively low latency when blocking on a particular request to finish.
3397 */
3398static int
3399i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3400{
3401 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3402 int ret = 0;
b962442e 3403 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3404
3405 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3406 while (!list_empty(&i915_file_priv->mm.request_list)) {
3407 struct drm_i915_gem_request *request;
3408
3409 request = list_first_entry(&i915_file_priv->mm.request_list,
3410 struct drm_i915_gem_request,
3411 client_list);
3412
3413 if (time_after_eq(request->emitted_jiffies, recent_enough))
3414 break;
3415
852835f3 3416 ret = i915_wait_request(dev, request->seqno, request->ring);
b962442e
EA		 3417 if (ret != 0)
3418 break;
3419 }
673a394b 3420 mutex_unlock(&dev->struct_mutex);
b962442e 3421
673a394b
EA		 3422 return ret;
3423}
3424
40a5f0de 3425static int
76446cac 3426i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3427 uint32_t buffer_count,
3428 struct drm_i915_gem_relocation_entry **relocs)
3429{
3430 uint32_t reloc_count = 0, reloc_index = 0, i;
3431 int ret;
3432
3433 *relocs = NULL;
3434 for (i = 0; i < buffer_count; i++) {
3435 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3436 return -EINVAL;
3437 reloc_count += exec_list[i].relocation_count;
3438 }
3439
8e7d2b2c 3440 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3441 if (*relocs == NULL) {
3442 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3443 return -ENOMEM;
76446cac 3444 }
40a5f0de
EA		 3445
3446 for (i = 0; i < buffer_count; i++) {
3447 struct drm_i915_gem_relocation_entry __user *user_relocs;
3448
3449 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3450
3451 ret = copy_from_user(&(*relocs)[reloc_index],
3452 user_relocs,
3453 exec_list[i].relocation_count *
3454 sizeof(**relocs));
3455 if (ret != 0) {
8e7d2b2c 3456 drm_free_large(*relocs);
40a5f0de 3457 *relocs = NULL;
2bc43b5c 3458 return -EFAULT;
40a5f0de
EA		 3459 }
3460
3461 reloc_index += exec_list[i].relocation_count;
3462 }
3463
2bc43b5c 3464 return 0;
40a5f0de
EA		 3465}
3466
3467static int
76446cac 3468i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3469 uint32_t buffer_count,
3470 struct drm_i915_gem_relocation_entry *relocs)
3471{
3472 uint32_t reloc_count = 0, i;
2bc43b5c 3473 int ret = 0;
40a5f0de 3474
93533c29
CW		 3475 if (relocs == NULL)
3476 return 0;
3477
40a5f0de
EA		 3478 for (i = 0; i < buffer_count; i++) {
3479 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3480 int unwritten;
40a5f0de
EA		 3481
3482 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3483
2bc43b5c
FM		 3484 unwritten = copy_to_user(user_relocs,
3485 &relocs[reloc_count],
3486 exec_list[i].relocation_count *
3487 sizeof(*relocs));
3488
3489 if (unwritten) {
3490 ret = -EFAULT;
3491 goto err;
40a5f0de
EA		 3492 }
3493
3494 reloc_count += exec_list[i].relocation_count;
3495 }
3496
2bc43b5c 3497err:
8e7d2b2c 3498 drm_free_large(relocs);
40a5f0de
EA		 3499
3500 return ret;
3501}
3502
83d60795 3503static int
76446cac 3504i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3505 uint64_t exec_offset)
3506{
3507 uint32_t exec_start, exec_len;
3508
3509 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3510 exec_len = (uint32_t) exec->batch_len;
3511
3512 if ((exec_start | exec_len) & 0x7)
3513 return -EINVAL;
3514
3515 if (!exec_start)
3516 return -EINVAL;
3517
3518 return 0;
3519}
3520
6b95a207
KH		 3521static int
3522i915_gem_wait_for_pending_flip(struct drm_device *dev,
3523 struct drm_gem_object **object_list,
3524 int count)
3525{
3526 drm_i915_private_t *dev_priv = dev->dev_private;
3527 struct drm_i915_gem_object *obj_priv;
3528 DEFINE_WAIT(wait);
3529 int i, ret = 0;
3530
3531 for (;;) {
3532 prepare_to_wait(&dev_priv->pending_flip_queue,
3533 &wait, TASK_INTERRUPTIBLE);
3534 for (i = 0; i < count; i++) {
23010e43 3535 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3536 if (atomic_read(&obj_priv->pending_flip) > 0)
3537 break;
3538 }
3539 if (i == count)
3540 break;
3541
3542 if (!signal_pending(current)) {
3543 mutex_unlock(&dev->struct_mutex);
3544 schedule();
3545 mutex_lock(&dev->struct_mutex);
3546 continue;
3547 }
3548 ret = -ERESTARTSYS;
3549 break;
3550 }
3551 finish_wait(&dev_priv->pending_flip_queue, &wait);
3552
3553 return ret;
3554}
3555
43b27f40 3556
673a394b 3557int
76446cac
JB		 3558i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3559 struct drm_file *file_priv,
3560 struct drm_i915_gem_execbuffer2 *args,
3561 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3562{
3563 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3564 struct drm_gem_object **object_list = NULL;
3565 struct drm_gem_object *batch_obj;
b70d11da 3566 struct drm_i915_gem_object *obj_priv;
201361a5 3567 struct drm_clip_rect *cliprects = NULL;
93533c29 3568 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3569 int ret = 0, ret2, i, pinned = 0;
673a394b 3570 uint64_t exec_offset;
40a5f0de 3571 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3572 int pin_tries, flips;
673a394b 3573
852835f3
ZN		 3574 struct intel_ring_buffer *ring = NULL;
3575
673a394b
EA		 3576#if WATCH_EXEC
3577 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3578 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3579#endif
d1b851fc
ZN		 3580 if (args->flags & I915_EXEC_BSD) {
3581 if (!HAS_BSD(dev)) {
3582 DRM_ERROR("execbuf with wrong flag\n");
3583 return -EINVAL;
3584 }
3585 ring = &dev_priv->bsd_ring;
3586 } else {
3587 ring = &dev_priv->render_ring;
3588 }
3589
4f481ed2
EA		 3590 if (args->buffer_count < 1) {
3591 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3592 return -EINVAL;
3593 }
c8e0f93a 3594 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3595 if (object_list == NULL) {
3596 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3597 args->buffer_count);
3598 ret = -ENOMEM;
3599 goto pre_mutex_err;
3600 }
673a394b 3601
201361a5 3602 if (args->num_cliprects != 0) {
9a298b2a
EA		 3603 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3604 GFP_KERNEL);
a40e8d31
OA		 3605 if (cliprects == NULL) {
3606 ret = -ENOMEM;
201361a5 3607 goto pre_mutex_err;
a40e8d31 3608 }
201361a5
EA		 3609
3610 ret = copy_from_user(cliprects,
3611 (struct drm_clip_rect __user *)
3612 (uintptr_t) args->cliprects_ptr,
3613 sizeof(*cliprects) * args->num_cliprects);
3614 if (ret != 0) {
3615 DRM_ERROR("copy %d cliprects failed: %d\n",
3616 args->num_cliprects, ret);
c877cdce 3617 ret = -EFAULT;
201361a5
EA		 3618 goto pre_mutex_err;
3619 }
3620 }
3621
40a5f0de
EA		 3622 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3623 &relocs);
3624 if (ret != 0)
3625 goto pre_mutex_err;
3626
673a394b
EA		 3627 mutex_lock(&dev->struct_mutex);
3628
3629 i915_verify_inactive(dev, __FILE__, __LINE__);
3630
ba1234d1 3631 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3632 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3633 ret = -EIO;
3634 goto pre_mutex_err;
673a394b
EA		 3635 }
3636
3637 if (dev_priv->mm.suspended) {
673a394b 3638 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3639 ret = -EBUSY;
3640 goto pre_mutex_err;
673a394b
EA		 3641 }
3642
ac94a962 3643 /* Look up object handles */
6b95a207 3644 flips = 0;
673a394b
EA		 3645 for (i = 0; i < args->buffer_count; i++) {
3646 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3647 exec_list[i].handle);
3648 if (object_list[i] == NULL) {
3649 DRM_ERROR("Invalid object handle %d at index %d\n",
3650 exec_list[i].handle, i);
0ce907f8
CW		 3651 /* prevent error path from reading uninitialized data */
3652 args->buffer_count = i + 1;
bf79cb91 3653 ret = -ENOENT;
673a394b
EA		 3654 goto err;
3655 }
b70d11da 3656
23010e43 3657 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3658 if (obj_priv->in_execbuffer) {
3659 DRM_ERROR("Object %p appears more than once in object list\n",
3660 object_list[i]);
0ce907f8
CW		 3661 /* prevent error path from reading uninitialized data */
3662 args->buffer_count = i + 1;
bf79cb91 3663 ret = -EINVAL;
b70d11da
KH		 3664 goto err;
3665 }
3666 obj_priv->in_execbuffer = true;
6b95a207
KH		 3667 flips += atomic_read(&obj_priv->pending_flip);
3668 }
3669
3670 if (flips > 0) {
3671 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3672 args->buffer_count);
3673 if (ret)
3674 goto err;
ac94a962 3675 }
673a394b 3676
ac94a962
KP		 3677 /* Pin and relocate */
3678 for (pin_tries = 0; ; pin_tries++) {
3679 ret = 0;
40a5f0de
EA		 3680 reloc_index = 0;
3681
ac94a962
KP		 3682 for (i = 0; i < args->buffer_count; i++) {
3683 object_list[i]->pending_read_domains = 0;
3684 object_list[i]->pending_write_domain = 0;
3685 ret = i915_gem_object_pin_and_relocate(object_list[i],
3686 file_priv,
40a5f0de
EA		 3687 &exec_list[i],
3688 &relocs[reloc_index]);
ac94a962
KP		 3689 if (ret)
3690 break;
3691 pinned = i + 1;
40a5f0de 3692 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3693 }
3694 /* success */
3695 if (ret == 0)
3696 break;
3697
3698 /* error other than GTT full, or we've already tried again */
2939e1f5 3699 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3700 if (ret != -ERESTARTSYS) {
3701 unsigned long long total_size = 0;
3d1cc470
CW		 3702 int num_fences = 0;
3703 for (i = 0; i < args->buffer_count; i++) {
43b27f40 3704 obj_priv = to_intel_bo(object_list[i]);
3d1cc470 3705
07f73f69 3706 total_size += object_list[i]->size;
3d1cc470
CW		 3707 num_fences +=
3708 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3709 obj_priv->tiling_mode != I915_TILING_NONE;
3710 }
3711 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
07f73f69 3712 pinned+1, args->buffer_count,
3d1cc470
CW		 3713 total_size, num_fences,
3714 ret);
07f73f69
CW		 3715 DRM_ERROR("%d objects [%d pinned], "
3716 "%d object bytes [%d pinned], "
3717 "%d/%d gtt bytes\n",
3718 atomic_read(&dev->object_count),
3719 atomic_read(&dev->pin_count),
3720 atomic_read(&dev->object_memory),
3721 atomic_read(&dev->pin_memory),
3722 atomic_read(&dev->gtt_memory),
3723 dev->gtt_total);
3724 }
673a394b
EA		 3725 goto err;
3726 }
ac94a962
KP		 3727
3728 /* unpin all of our buffers */
3729 for (i = 0; i < pinned; i++)
3730 i915_gem_object_unpin(object_list[i]);
b1177636 3731 pinned = 0;
ac94a962
KP		 3732
3733 /* evict everyone we can from the aperture */
3734 ret = i915_gem_evict_everything(dev);
07f73f69 3735 if (ret && ret != -ENOSPC)
ac94a962 3736 goto err;
673a394b
EA		 3737 }
3738
3739 /* Set the pending read domains for the batch buffer to COMMAND */
3740 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3741 if (batch_obj->pending_write_domain) {
3742 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3743 ret = -EINVAL;
3744 goto err;
3745 }
3746 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3747
83d60795
CW		 3748 /* Sanity check the batch buffer, prior to moving objects */
3749 exec_offset = exec_list[args->buffer_count - 1].offset;
3750 ret = i915_gem_check_execbuffer (args, exec_offset);
3751 if (ret != 0) {
3752 DRM_ERROR("execbuf with invalid offset/length\n");
3753 goto err;
3754 }
3755
673a394b
EA		 3756 i915_verify_inactive(dev, __FILE__, __LINE__);
3757
646f0f6e
KP		 3758 /* Zero the global flush/invalidate flags. These
3759 * will be modified as new domains are computed
3760 * for each object
3761 */
3762 dev->invalidate_domains = 0;
3763 dev->flush_domains = 0;
88f356b7 3764 dev_priv->flush_rings = 0;
646f0f6e 3765
673a394b
EA		 3766 for (i = 0; i < args->buffer_count; i++) {
3767 struct drm_gem_object *obj = object_list[i];
673a394b 3768
646f0f6e 3769 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3770 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3771 }
3772
3773 i915_verify_inactive(dev, __FILE__, __LINE__);
3774
646f0f6e
KP		 3775 if (dev->invalidate_domains | dev->flush_domains) {
3776#if WATCH_EXEC
3777 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3778 __func__,
3779 dev->invalidate_domains,
3780 dev->flush_domains);
3781#endif
3782 i915_gem_flush(dev,
3783 dev->invalidate_domains,
3784 dev->flush_domains);
88f356b7 3785 if (dev_priv->flush_rings & FLUSH_RENDER_RING)
b962442e 3786 (void)i915_add_request(dev, file_priv,
88f356b7
CW		 3787 dev->flush_domains,
3788 &dev_priv->render_ring);
3789 if (dev_priv->flush_rings & FLUSH_BSD_RING)
3790 (void)i915_add_request(dev, file_priv,
3791 dev->flush_domains,
3792 &dev_priv->bsd_ring);
646f0f6e 3793 }
673a394b 3794
efbeed96
EA		 3795 for (i = 0; i < args->buffer_count; i++) {
3796 struct drm_gem_object *obj = object_list[i];
23010e43 3797 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3798 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3799
3800 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3801 if (obj->write_domain)
3802 list_move_tail(&obj_priv->gpu_write_list,
3803 &dev_priv->mm.gpu_write_list);
3804 else
3805 list_del_init(&obj_priv->gpu_write_list);
3806
1c5d22f7
CW		 3807 trace_i915_gem_object_change_domain(obj,
3808 obj->read_domains,
3809 old_write_domain);
efbeed96
EA		 3810 }
3811
673a394b
EA		 3812 i915_verify_inactive(dev, __FILE__, __LINE__);
3813
3814#if WATCH_COHERENCY
3815 for (i = 0; i < args->buffer_count; i++) {
3816 i915_gem_object_check_coherency(object_list[i],
3817 exec_list[i].handle);
3818 }
3819#endif
3820
673a394b 3821#if WATCH_EXEC
6911a9b8 3822 i915_gem_dump_object(batch_obj,
673a394b
EA		 3823 args->batch_len,
3824 __func__,
3825 ~0);
3826#endif
3827
673a394b 3828 /* Exec the batchbuffer */
852835f3
ZN		 3829 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3830 cliprects, exec_offset);
673a394b
EA		 3831 if (ret) {
3832 DRM_ERROR("dispatch failed %d\n", ret);
3833 goto err;
3834 }
3835
3836 /*
3837 * Ensure that the commands in the batch buffer are
3838 * finished before the interrupt fires
3839 */
852835f3 3840 flush_domains = i915_retire_commands(dev, ring);
673a394b
EA		 3841
3842 i915_verify_inactive(dev, __FILE__, __LINE__);
3843
3844 /*
3845 * Get a seqno representing the execution of the current buffer,
3846 * which we can wait on. We would like to mitigate these interrupts,
3847 * likely by only creating seqnos occasionally (so that we have
3848 * *some* interrupts representing completion of buffers that we can
3849 * wait on when trying to clear up gtt space).
3850 */
852835f3 3851 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
673a394b 3852 BUG_ON(seqno == 0);
673a394b
EA		 3853 for (i = 0; i < args->buffer_count; i++) {
3854 struct drm_gem_object *obj = object_list[i];
852835f3 3855 obj_priv = to_intel_bo(obj);
673a394b 3856
852835f3 3857 i915_gem_object_move_to_active(obj, seqno, ring);
673a394b
EA		 3858#if WATCH_LRU
3859 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3860#endif
3861 }
3862#if WATCH_LRU
3863 i915_dump_lru(dev, __func__);
3864#endif
3865
3866 i915_verify_inactive(dev, __FILE__, __LINE__);
3867
673a394b 3868err:
aad87dff
JL		 3869 for (i = 0; i < pinned; i++)
3870 i915_gem_object_unpin(object_list[i]);
3871
b70d11da
KH		 3872 for (i = 0; i < args->buffer_count; i++) {
3873 if (object_list[i]) {
23010e43 3874 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3875 obj_priv->in_execbuffer = false;
3876 }
aad87dff 3877 drm_gem_object_unreference(object_list[i]);
b70d11da 3878 }
673a394b 3879
673a394b
EA		 3880 mutex_unlock(&dev->struct_mutex);
3881
93533c29 3882pre_mutex_err:
40a5f0de
EA		 3883 /* Copy the updated relocations out regardless of current error
3884 * state. Failure to update the relocs would mean that the next
3885 * time userland calls execbuf, it would do so with presumed offset
3886 * state that didn't match the actual object state.
3887 */
3888 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3889 relocs);
3890 if (ret2 != 0) {
3891 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3892
3893 if (ret == 0)
3894 ret = ret2;
3895 }
3896
8e7d2b2c 3897 drm_free_large(object_list);
9a298b2a 3898 kfree(cliprects);
673a394b
EA		 3899
3900 return ret;
3901}
3902
76446cac
JB		 3903/*
3904 * Legacy execbuffer just creates an exec2 list from the original exec object
3905 * list array and passes it to the real function.
3906 */
3907int
3908i915_gem_execbuffer(struct drm_device *dev, void *data,
3909 struct drm_file *file_priv)
3910{
3911 struct drm_i915_gem_execbuffer *args = data;
3912 struct drm_i915_gem_execbuffer2 exec2;
3913 struct drm_i915_gem_exec_object *exec_list = NULL;
3914 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3915 int ret, i;
3916
3917#if WATCH_EXEC
3918 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3919 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3920#endif
3921
3922 if (args->buffer_count < 1) {
3923 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3924 return -EINVAL;
3925 }
3926
3927 /* Copy in the exec list from userland */
3928 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3929 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3930 if (exec_list == NULL || exec2_list == NULL) {
3931 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3932 args->buffer_count);
3933 drm_free_large(exec_list);
3934 drm_free_large(exec2_list);
3935 return -ENOMEM;
3936 }
3937 ret = copy_from_user(exec_list,
3938 (struct drm_i915_relocation_entry __user *)
3939 (uintptr_t) args->buffers_ptr,
3940 sizeof(*exec_list) * args->buffer_count);
3941 if (ret != 0) {
3942 DRM_ERROR("copy %d exec entries failed %d\n",
3943 args->buffer_count, ret);
3944 drm_free_large(exec_list);
3945 drm_free_large(exec2_list);
3946 return -EFAULT;
3947 }
3948
3949 for (i = 0; i < args->buffer_count; i++) {
3950 exec2_list[i].handle = exec_list[i].handle;
3951 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3952 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3953 exec2_list[i].alignment = exec_list[i].alignment;
3954 exec2_list[i].offset = exec_list[i].offset;
3955 if (!IS_I965G(dev))
3956 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3957 else
3958 exec2_list[i].flags = 0;
3959 }
3960
3961 exec2.buffers_ptr = args->buffers_ptr;
3962 exec2.buffer_count = args->buffer_count;
3963 exec2.batch_start_offset = args->batch_start_offset;
3964 exec2.batch_len = args->batch_len;
3965 exec2.DR1 = args->DR1;
3966 exec2.DR4 = args->DR4;
3967 exec2.num_cliprects = args->num_cliprects;
3968 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 3969 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 3970
3971 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3972 if (!ret) {
3973 /* Copy the new buffer offsets back to the user's exec list. */
3974 for (i = 0; i < args->buffer_count; i++)
3975 exec_list[i].offset = exec2_list[i].offset;
3976 /* ... and back out to userspace */
3977 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3978 (uintptr_t) args->buffers_ptr,
3979 exec_list,
3980 sizeof(*exec_list) * args->buffer_count);
3981 if (ret) {
3982 ret = -EFAULT;
3983 DRM_ERROR("failed to copy %d exec entries "
3984 "back to user (%d)\n",
3985 args->buffer_count, ret);
3986 }
76446cac
JB		 3987 }
3988
3989 drm_free_large(exec_list);
3990 drm_free_large(exec2_list);
3991 return ret;
3992}
3993
3994int
3995i915_gem_execbuffer2(struct drm_device *dev, void *data,
3996 struct drm_file *file_priv)
3997{
3998 struct drm_i915_gem_execbuffer2 *args = data;
3999 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4000 int ret;
4001
4002#if WATCH_EXEC
4003 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4004 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4005#endif
4006
4007 if (args->buffer_count < 1) {
4008 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4009 return -EINVAL;
4010 }
4011
4012 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4013 if (exec2_list == NULL) {
4014 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4015 args->buffer_count);
4016 return -ENOMEM;
4017 }
4018 ret = copy_from_user(exec2_list,
4019 (struct drm_i915_relocation_entry __user *)
4020 (uintptr_t) args->buffers_ptr,
4021 sizeof(*exec2_list) * args->buffer_count);
4022 if (ret != 0) {
4023 DRM_ERROR("copy %d exec entries failed %d\n",
4024 args->buffer_count, ret);
4025 drm_free_large(exec2_list);
4026 return -EFAULT;
4027 }
4028
4029 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4030 if (!ret) {
4031 /* Copy the new buffer offsets back to the user's exec list. */
4032 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4033 (uintptr_t) args->buffers_ptr,
4034 exec2_list,
4035 sizeof(*exec2_list) * args->buffer_count);
4036 if (ret) {
4037 ret = -EFAULT;
4038 DRM_ERROR("failed to copy %d exec entries "
4039 "back to user (%d)\n",
4040 args->buffer_count, ret);
4041 }
4042 }
4043
4044 drm_free_large(exec2_list);
4045 return ret;
4046}
4047
673a394b
EA		 4048int
4049i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4050{
4051 struct drm_device *dev = obj->dev;
23010e43 4052 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4053 int ret;
4054
778c3544
DV		 4055 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4056
673a394b 4057 i915_verify_inactive(dev, __FILE__, __LINE__);
ac0c6b5a
CW		 4058
4059 if (obj_priv->gtt_space != NULL) {
4060 if (alignment == 0)
4061 alignment = i915_gem_get_gtt_alignment(obj);
4062 if (obj_priv->gtt_offset & (alignment - 1)) {
ae7d49d8
CW		 4063 WARN(obj_priv->pin_count,
4064 "bo is already pinned with incorrect alignment:"
4065 " offset=%x, req.alignment=%x\n",
4066 obj_priv->gtt_offset, alignment);
ac0c6b5a
CW		 4067 ret = i915_gem_object_unbind(obj);
4068 if (ret)
4069 return ret;
4070 }
4071 }
4072
673a394b
EA		 4073 if (obj_priv->gtt_space == NULL) {
4074 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4075 if (ret)
673a394b 4076 return ret;
22c344e9 4077 }
76446cac 4078
673a394b
EA		 4079 obj_priv->pin_count++;
4080
4081 /* If the object is not active and not pending a flush,
4082 * remove it from the inactive list
4083 */
4084 if (obj_priv->pin_count == 1) {
4085 atomic_inc(&dev->pin_count);
4086 atomic_add(obj->size, &dev->pin_memory);
4087 if (!obj_priv->active &&
bf1a1092 4088 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4089 list_del_init(&obj_priv->list);
4090 }
4091 i915_verify_inactive(dev, __FILE__, __LINE__);
4092
4093 return 0;
4094}
4095
4096void
4097i915_gem_object_unpin(struct drm_gem_object *obj)
4098{
4099 struct drm_device *dev = obj->dev;
4100 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4101 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4102
4103 i915_verify_inactive(dev, __FILE__, __LINE__);
4104 obj_priv->pin_count--;
4105 BUG_ON(obj_priv->pin_count < 0);
4106 BUG_ON(obj_priv->gtt_space == NULL);
4107
4108 /* If the object is no longer pinned, and is
4109 * neither active nor being flushed, then stick it on
4110 * the inactive list
4111 */
4112 if (obj_priv->pin_count == 0) {
4113 if (!obj_priv->active &&
21d509e3 4114 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4115 list_move_tail(&obj_priv->list,
4116 &dev_priv->mm.inactive_list);
4117 atomic_dec(&dev->pin_count);
4118 atomic_sub(obj->size, &dev->pin_memory);
4119 }
4120 i915_verify_inactive(dev, __FILE__, __LINE__);
4121}
4122
4123int
4124i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4125 struct drm_file *file_priv)
4126{
4127 struct drm_i915_gem_pin *args = data;
4128 struct drm_gem_object *obj;
4129 struct drm_i915_gem_object *obj_priv;
4130 int ret;
4131
4132 mutex_lock(&dev->struct_mutex);
4133
4134 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4135 if (obj == NULL) {
4136 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4137 args->handle);
4138 mutex_unlock(&dev->struct_mutex);
bf79cb91 4139 return -ENOENT;
673a394b 4140 }
23010e43 4141 obj_priv = to_intel_bo(obj);
673a394b 4142
bb6baf76
CW		 4143 if (obj_priv->madv != I915_MADV_WILLNEED) {
4144 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4145 drm_gem_object_unreference(obj);
4146 mutex_unlock(&dev->struct_mutex);
4147 return -EINVAL;
4148 }
4149
79e53945
JB		 4150 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4151 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4152 args->handle);
96dec61d 4153 drm_gem_object_unreference(obj);
673a394b 4154 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4155 return -EINVAL;
4156 }
4157
4158 obj_priv->user_pin_count++;
4159 obj_priv->pin_filp = file_priv;
4160 if (obj_priv->user_pin_count == 1) {
4161 ret = i915_gem_object_pin(obj, args->alignment);
4162 if (ret != 0) {
4163 drm_gem_object_unreference(obj);
4164 mutex_unlock(&dev->struct_mutex);
4165 return ret;
4166 }
673a394b
EA		 4167 }
4168
4169 /* XXX - flush the CPU caches for pinned objects
4170 * as the X server doesn't manage domains yet
4171 */
e47c68e9 4172 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4173 args->offset = obj_priv->gtt_offset;
4174 drm_gem_object_unreference(obj);
4175 mutex_unlock(&dev->struct_mutex);
4176
4177 return 0;
4178}
4179
4180int
4181i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4182 struct drm_file *file_priv)
4183{
4184 struct drm_i915_gem_pin *args = data;
4185 struct drm_gem_object *obj;
79e53945 4186 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4187
4188 mutex_lock(&dev->struct_mutex);
4189
4190 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4191 if (obj == NULL) {
4192 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4193 args->handle);
4194 mutex_unlock(&dev->struct_mutex);
bf79cb91 4195 return -ENOENT;
673a394b
EA		 4196 }
4197
23010e43 4198 obj_priv = to_intel_bo(obj);
79e53945
JB		 4199 if (obj_priv->pin_filp != file_priv) {
4200 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4201 args->handle);
4202 drm_gem_object_unreference(obj);
4203 mutex_unlock(&dev->struct_mutex);
4204 return -EINVAL;
4205 }
4206 obj_priv->user_pin_count--;
4207 if (obj_priv->user_pin_count == 0) {
4208 obj_priv->pin_filp = NULL;
4209 i915_gem_object_unpin(obj);
4210 }
673a394b
EA		 4211
4212 drm_gem_object_unreference(obj);
4213 mutex_unlock(&dev->struct_mutex);
4214 return 0;
4215}
4216
4217int
4218i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4219 struct drm_file *file_priv)
4220{
4221 struct drm_i915_gem_busy *args = data;
4222 struct drm_gem_object *obj;
4223 struct drm_i915_gem_object *obj_priv;
4224
673a394b
EA		 4225 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4226 if (obj == NULL) {
4227 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4228 args->handle);
bf79cb91 4229 return -ENOENT;
673a394b
EA		 4230 }
4231
b1ce786c 4232 mutex_lock(&dev->struct_mutex);
d1b851fc 4233
0be555b6
CW		 4234 /* Count all active objects as busy, even if they are currently not used
4235 * by the gpu. Users of this interface expect objects to eventually
4236 * become non-busy without any further actions, therefore emit any
4237 * necessary flushes here.
c4de0a5d 4238 */
0be555b6
CW		 4239 obj_priv = to_intel_bo(obj);
4240 args->busy = obj_priv->active;
4241 if (args->busy) {
4242 /* Unconditionally flush objects, even when the gpu still uses this
4243 * object. Userspace calling this function indicates that it wants to
4244 * use this buffer rather sooner than later, so issuing the required
4245 * flush earlier is beneficial.
4246 */
4247 if (obj->write_domain) {
4248 i915_gem_flush(dev, 0, obj->write_domain);
4249 (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring);
4250 }
4251
4252 /* Update the active list for the hardware's current position.
4253 * Otherwise this only updates on a delayed timer or when irqs
4254 * are actually unmasked, and our working set ends up being
4255 * larger than required.
4256 */
4257 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4258
4259 args->busy = obj_priv->active;
4260 }
673a394b
EA		 4261
4262 drm_gem_object_unreference(obj);
4263 mutex_unlock(&dev->struct_mutex);
4264 return 0;
4265}
4266
4267int
4268i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4269 struct drm_file *file_priv)
4270{
4271 return i915_gem_ring_throttle(dev, file_priv);
4272}
4273
3ef94daa
CW		 4274int
4275i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4276 struct drm_file *file_priv)
4277{
4278 struct drm_i915_gem_madvise *args = data;
4279 struct drm_gem_object *obj;
4280 struct drm_i915_gem_object *obj_priv;
4281
4282 switch (args->madv) {
4283 case I915_MADV_DONTNEED:
4284 case I915_MADV_WILLNEED:
4285 break;
4286 default:
4287 return -EINVAL;
4288 }
4289
4290 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4291 if (obj == NULL) {
4292 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4293 args->handle);
bf79cb91 4294 return -ENOENT;
3ef94daa
CW		 4295 }
4296
4297 mutex_lock(&dev->struct_mutex);
23010e43 4298 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4299
4300 if (obj_priv->pin_count) {
4301 drm_gem_object_unreference(obj);
4302 mutex_unlock(&dev->struct_mutex);
4303
4304 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4305 return -EINVAL;
4306 }
4307
bb6baf76
CW		 4308 if (obj_priv->madv != __I915_MADV_PURGED)
4309 obj_priv->madv = args->madv;
3ef94daa 4310
2d7ef395
CW		 4311 /* if the object is no longer bound, discard its backing storage */
4312 if (i915_gem_object_is_purgeable(obj_priv) &&
4313 obj_priv->gtt_space == NULL)
4314 i915_gem_object_truncate(obj);
4315
bb6baf76
CW		 4316 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4317
3ef94daa
CW		 4318 drm_gem_object_unreference(obj);
4319 mutex_unlock(&dev->struct_mutex);
4320
4321 return 0;
4322}
4323
ac52bc56
DV		 4324struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4325 size_t size)
4326{
c397b908 4327 struct drm_i915_gem_object *obj;
ac52bc56 4328
c397b908
DV		 4329 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4330 if (obj == NULL)
4331 return NULL;
673a394b 4332
c397b908
DV		 4333 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4334 kfree(obj);
4335 return NULL;
4336 }
673a394b 4337
c397b908
DV		 4338 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4339 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4340
c397b908 4341 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4342 obj->base.driver_private = NULL;
c397b908
DV		 4343 obj->fence_reg = I915_FENCE_REG_NONE;
4344 INIT_LIST_HEAD(&obj->list);
4345 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4346 obj->madv = I915_MADV_WILLNEED;
de151cf6 4347
c397b908
DV		 4348 trace_i915_gem_object_create(&obj->base);
4349
4350 return &obj->base;
4351}
4352
4353int i915_gem_init_object(struct drm_gem_object *obj)
4354{
4355 BUG();
de151cf6 4356
673a394b
EA		 4357 return 0;
4358}
4359
be72615b 4360static void i915_gem_free_object_tail(struct drm_gem_object *obj)
673a394b 4361{
de151cf6 4362 struct drm_device *dev = obj->dev;
be72615b 4363 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4364 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
be72615b 4365 int ret;
673a394b 4366
be72615b
CW		 4367 ret = i915_gem_object_unbind(obj);
4368 if (ret == -ERESTARTSYS) {
4369 list_move(&obj_priv->list,
4370 &dev_priv->mm.deferred_free_list);
4371 return;
4372 }
673a394b 4373
7e616158
CW		 4374 if (obj_priv->mmap_offset)
4375 i915_gem_free_mmap_offset(obj);
de151cf6 4376
c397b908
DV		 4377 drm_gem_object_release(obj);
4378
9a298b2a 4379 kfree(obj_priv->page_cpu_valid);
280b713b 4380 kfree(obj_priv->bit_17);
c397b908 4381 kfree(obj_priv);
673a394b
EA		 4382}
4383
be72615b
CW		 4384void i915_gem_free_object(struct drm_gem_object *obj)
4385{
4386 struct drm_device *dev = obj->dev;
4387 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4388
4389 trace_i915_gem_object_destroy(obj);
4390
4391 while (obj_priv->pin_count > 0)
4392 i915_gem_object_unpin(obj);
4393
4394 if (obj_priv->phys_obj)
4395 i915_gem_detach_phys_object(dev, obj);
4396
4397 i915_gem_free_object_tail(obj);
4398}
4399
29105ccc
CW		 4400int
4401i915_gem_idle(struct drm_device *dev)
4402{
4403 drm_i915_private_t *dev_priv = dev->dev_private;
4404 int ret;
28dfe52a 4405
29105ccc 4406 mutex_lock(&dev->struct_mutex);
1c5d22f7 4407
8187a2b7 4408 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4409 (dev_priv->render_ring.gem_object == NULL) ||
4410 (HAS_BSD(dev) &&
4411 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4412 mutex_unlock(&dev->struct_mutex);
4413 return 0;
28dfe52a
EA		 4414 }
4415
29105ccc 4416 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4417 if (ret) {
4418 mutex_unlock(&dev->struct_mutex);
673a394b 4419 return ret;
6dbe2772 4420 }
673a394b 4421
29105ccc
CW		 4422 /* Under UMS, be paranoid and evict. */
4423 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
b47eb4a2 4424 ret = i915_gem_evict_inactive(dev);
29105ccc
CW		 4425 if (ret) {
4426 mutex_unlock(&dev->struct_mutex);
4427 return ret;
4428 }
4429 }
4430
4431 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4432 * We need to replace this with a semaphore, or something.
4433 * And not confound mm.suspended!
4434 */
4435 dev_priv->mm.suspended = 1;
4436 del_timer(&dev_priv->hangcheck_timer);
4437
4438 i915_kernel_lost_context(dev);
6dbe2772 4439 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4440
6dbe2772
KP		 4441 mutex_unlock(&dev->struct_mutex);
4442
29105ccc
CW		 4443 /* Cancel the retire work handler, which should be idle now. */
4444 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4445
673a394b
EA		 4446 return 0;
4447}
4448
e552eb70
JB		 4449/*
4450 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4451 * over cache flushing.
4452 */
8187a2b7 4453static int
e552eb70
JB		 4454i915_gem_init_pipe_control(struct drm_device *dev)
4455{
4456 drm_i915_private_t *dev_priv = dev->dev_private;
4457 struct drm_gem_object *obj;
4458 struct drm_i915_gem_object *obj_priv;
4459 int ret;
4460
34dc4d44 4461 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4462 if (obj == NULL) {
4463 DRM_ERROR("Failed to allocate seqno page\n");
4464 ret = -ENOMEM;
4465 goto err;
4466 }
4467 obj_priv = to_intel_bo(obj);
4468 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4469
4470 ret = i915_gem_object_pin(obj, 4096);
4471 if (ret)
4472 goto err_unref;
4473
4474 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4475 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4476 if (dev_priv->seqno_page == NULL)
4477 goto err_unpin;
4478
4479 dev_priv->seqno_obj = obj;
4480 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4481
4482 return 0;
4483
4484err_unpin:
4485 i915_gem_object_unpin(obj);
4486err_unref:
4487 drm_gem_object_unreference(obj);
4488err:
4489 return ret;
4490}
4491
8187a2b7
ZN		 4492
4493static void
e552eb70
JB		 4494i915_gem_cleanup_pipe_control(struct drm_device *dev)
4495{
4496 drm_i915_private_t *dev_priv = dev->dev_private;
4497 struct drm_gem_object *obj;
4498 struct drm_i915_gem_object *obj_priv;
4499
4500 obj = dev_priv->seqno_obj;
4501 obj_priv = to_intel_bo(obj);
4502 kunmap(obj_priv->pages[0]);
4503 i915_gem_object_unpin(obj);
4504 drm_gem_object_unreference(obj);
4505 dev_priv->seqno_obj = NULL;
4506
4507 dev_priv->seqno_page = NULL;
673a394b
EA		 4508}
4509
8187a2b7
ZN		 4510int
4511i915_gem_init_ringbuffer(struct drm_device *dev)
4512{
4513 drm_i915_private_t *dev_priv = dev->dev_private;
4514 int ret;
68f95ba9 4515
8187a2b7 4516 dev_priv->render_ring = render_ring;
68f95ba9 4517
8187a2b7
ZN		 4518 if (!I915_NEED_GFX_HWS(dev)) {
4519 dev_priv->render_ring.status_page.page_addr
4520 = dev_priv->status_page_dmah->vaddr;
4521 memset(dev_priv->render_ring.status_page.page_addr,
4522 0, PAGE_SIZE);
4523 }
68f95ba9 4524
8187a2b7
ZN		 4525 if (HAS_PIPE_CONTROL(dev)) {
4526 ret = i915_gem_init_pipe_control(dev);
4527 if (ret)
4528 return ret;
4529 }
68f95ba9 4530
8187a2b7 4531 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
68f95ba9
CW		 4532 if (ret)
4533 goto cleanup_pipe_control;
4534
4535 if (HAS_BSD(dev)) {
d1b851fc
ZN		 4536 dev_priv->bsd_ring = bsd_ring;
4537 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
68f95ba9
CW		 4538 if (ret)
4539 goto cleanup_render_ring;
d1b851fc 4540 }
68f95ba9 4541
6f392d54
CW		 4542 dev_priv->next_seqno = 1;
4543
68f95ba9
CW		 4544 return 0;
4545
4546cleanup_render_ring:
4547 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4548cleanup_pipe_control:
4549 if (HAS_PIPE_CONTROL(dev))
4550 i915_gem_cleanup_pipe_control(dev);
8187a2b7
ZN		 4551 return ret;
4552}
4553
4554void
4555i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4556{
4557 drm_i915_private_t *dev_priv = dev->dev_private;
4558
4559 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4560 if (HAS_BSD(dev))
4561 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4562 if (HAS_PIPE_CONTROL(dev))
4563 i915_gem_cleanup_pipe_control(dev);
4564}
4565
673a394b
EA		 4566int
4567i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4568 struct drm_file *file_priv)
4569{
4570 drm_i915_private_t *dev_priv = dev->dev_private;
4571 int ret;
4572
79e53945
JB		 4573 if (drm_core_check_feature(dev, DRIVER_MODESET))
4574 return 0;
4575
ba1234d1 4576 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4577 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4578 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4579 }
4580
673a394b 4581 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4582 dev_priv->mm.suspended = 0;
4583
4584 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4585 if (ret != 0) {
4586 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4587 return ret;
d816f6ac 4588 }
9bb2d6f9 4589
5e118f41 4590 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 4591 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4592 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
5e118f41
CW		 4593 spin_unlock(&dev_priv->mm.active_list_lock);
4594
673a394b
EA		 4595 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4596 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4597 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4598 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4599 mutex_unlock(&dev->struct_mutex);
dbb19d30 4600
5f35308b
CW		 4601 ret = drm_irq_install(dev);
4602 if (ret)
4603 goto cleanup_ringbuffer;
dbb19d30 4604
673a394b 4605 return 0;
5f35308b
CW		 4606
4607cleanup_ringbuffer:
4608 mutex_lock(&dev->struct_mutex);
4609 i915_gem_cleanup_ringbuffer(dev);
4610 dev_priv->mm.suspended = 1;
4611 mutex_unlock(&dev->struct_mutex);
4612
4613 return ret;
673a394b
EA		 4614}
4615
4616int
4617i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4618 struct drm_file *file_priv)
4619{
79e53945
JB		 4620 if (drm_core_check_feature(dev, DRIVER_MODESET))
4621 return 0;
4622
dbb19d30 4623 drm_irq_uninstall(dev);
e6890f6f 4624 return i915_gem_idle(dev);
673a394b
EA		 4625}
4626
4627void
4628i915_gem_lastclose(struct drm_device *dev)
4629{
4630 int ret;
673a394b 4631
e806b495
EA		 4632 if (drm_core_check_feature(dev, DRIVER_MODESET))
4633 return;
4634
6dbe2772
KP		 4635 ret = i915_gem_idle(dev);
4636 if (ret)
4637 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4638}
4639
4640void
4641i915_gem_load(struct drm_device *dev)
4642{
b5aa8a0f 4643 int i;
673a394b
EA		 4644 drm_i915_private_t *dev_priv = dev->dev_private;
4645
5e118f41 4646 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b 4647 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4648 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4649 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 4650 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
be72615b 4651 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
852835f3
ZN		 4652 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4653 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4654 if (HAS_BSD(dev)) {
4655 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4656 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4657 }
007cc8ac
DV		 4658 for (i = 0; i < 16; i++)
4659 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4660 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4661 i915_gem_retire_work_handler);
31169714
CW		 4662 spin_lock(&shrink_list_lock);
4663 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4664 spin_unlock(&shrink_list_lock);
4665
94400120
DA		 4666 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4667 if (IS_GEN3(dev)) {
4668 u32 tmp = I915_READ(MI_ARB_STATE);
4669 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4670 /* arb state is a masked write, so set bit + bit in mask */
4671 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4672 I915_WRITE(MI_ARB_STATE, tmp);
4673 }
4674 }
4675
de151cf6 4676 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4677 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4678 dev_priv->fence_reg_start = 3;
de151cf6 4679
0f973f27 4680 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4681 dev_priv->num_fence_regs = 16;
4682 else
4683 dev_priv->num_fence_regs = 8;
4684
b5aa8a0f
GH		 4685 /* Initialize fence registers to zero */
4686 if (IS_I965G(dev)) {
4687 for (i = 0; i < 16; i++)
4688 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4689 } else {
4690 for (i = 0; i < 8; i++)
4691 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4692 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4693 for (i = 0; i < 8; i++)
4694 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4695 }
673a394b 4696 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4697 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4698}
71acb5eb
DA		 4699
4700/*
4701 * Create a physically contiguous memory object for this object
4702 * e.g. for cursor + overlay regs
4703 */
4704int i915_gem_init_phys_object(struct drm_device *dev,
6eeefaf3 4705 int id, int size, int align)
71acb5eb
DA		 4706{
4707 drm_i915_private_t *dev_priv = dev->dev_private;
4708 struct drm_i915_gem_phys_object *phys_obj;
4709 int ret;
4710
4711 if (dev_priv->mm.phys_objs[id - 1] || !size)
4712 return 0;
4713
9a298b2a 4714 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4715 if (!phys_obj)
4716 return -ENOMEM;
4717
4718 phys_obj->id = id;
4719
6eeefaf3 4720 phys_obj->handle = drm_pci_alloc(dev, size, align);
71acb5eb
DA		 4721 if (!phys_obj->handle) {
4722 ret = -ENOMEM;
4723 goto kfree_obj;
4724 }
4725#ifdef CONFIG_X86
4726 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4727#endif
4728
4729 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4730
4731 return 0;
4732kfree_obj:
9a298b2a 4733 kfree(phys_obj);
71acb5eb
DA		 4734 return ret;
4735}
4736
4737void i915_gem_free_phys_object(struct drm_device *dev, int id)
4738{
4739 drm_i915_private_t *dev_priv = dev->dev_private;
4740 struct drm_i915_gem_phys_object *phys_obj;
4741
4742 if (!dev_priv->mm.phys_objs[id - 1])
4743 return;
4744
4745 phys_obj = dev_priv->mm.phys_objs[id - 1];
4746 if (phys_obj->cur_obj) {
4747 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4748 }
4749
4750#ifdef CONFIG_X86
4751 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4752#endif
4753 drm_pci_free(dev, phys_obj->handle);
4754 kfree(phys_obj);
4755 dev_priv->mm.phys_objs[id - 1] = NULL;
4756}
4757
4758void i915_gem_free_all_phys_object(struct drm_device *dev)
4759{
4760 int i;
4761
260883c8 4762 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4763 i915_gem_free_phys_object(dev, i);
4764}
4765
4766void i915_gem_detach_phys_object(struct drm_device *dev,
4767 struct drm_gem_object *obj)
4768{
4769 struct drm_i915_gem_object *obj_priv;
4770 int i;
4771 int ret;
4772 int page_count;
4773
23010e43 4774 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4775 if (!obj_priv->phys_obj)
4776 return;
4777
4bdadb97 4778 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4779 if (ret)
4780 goto out;
4781
4782 page_count = obj->size / PAGE_SIZE;
4783
4784 for (i = 0; i < page_count; i++) {
856fa198 4785 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4786 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4787
4788 memcpy(dst, src, PAGE_SIZE);
4789 kunmap_atomic(dst, KM_USER0);
4790 }
856fa198 4791 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4792 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4793
4794 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4795out:
4796 obj_priv->phys_obj->cur_obj = NULL;
4797 obj_priv->phys_obj = NULL;
4798}
4799
4800int
4801i915_gem_attach_phys_object(struct drm_device *dev,
6eeefaf3
CW		 4802 struct drm_gem_object *obj,
4803 int id,
4804 int align)
71acb5eb
DA		 4805{
4806 drm_i915_private_t *dev_priv = dev->dev_private;
4807 struct drm_i915_gem_object *obj_priv;
4808 int ret = 0;
4809 int page_count;
4810 int i;
4811
4812 if (id > I915_MAX_PHYS_OBJECT)
4813 return -EINVAL;
4814
23010e43 4815 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4816
4817 if (obj_priv->phys_obj) {
4818 if (obj_priv->phys_obj->id == id)
4819 return 0;
4820 i915_gem_detach_phys_object(dev, obj);
4821 }
4822
71acb5eb
DA		 4823 /* create a new object */
4824 if (!dev_priv->mm.phys_objs[id - 1]) {
4825 ret = i915_gem_init_phys_object(dev, id,
6eeefaf3 4826 obj->size, align);
71acb5eb 4827 if (ret) {
aeb565df 4828 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4829 goto out;
4830 }
4831 }
4832
4833 /* bind to the object */
4834 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4835 obj_priv->phys_obj->cur_obj = obj;
4836
4bdadb97 4837 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4838 if (ret) {
4839 DRM_ERROR("failed to get page list\n");
4840 goto out;
4841 }
4842
4843 page_count = obj->size / PAGE_SIZE;
4844
4845 for (i = 0; i < page_count; i++) {
856fa198 4846 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4847 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4848
4849 memcpy(dst, src, PAGE_SIZE);
4850 kunmap_atomic(src, KM_USER0);
4851 }
4852
d78b47b9
CW		 4853 i915_gem_object_put_pages(obj);
4854
71acb5eb
DA		 4855 return 0;
4856out:
4857 return ret;
4858}
4859
4860static int
4861i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4862 struct drm_i915_gem_pwrite *args,
4863 struct drm_file *file_priv)
4864{
23010e43 4865 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4866 void *obj_addr;
4867 int ret;
4868 char __user *user_data;
4869
4870 user_data = (char __user *) (uintptr_t) args->data_ptr;
4871 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4872
44d98a61 4873 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4874 ret = copy_from_user(obj_addr, user_data, args->size);
4875 if (ret)
4876 return -EFAULT;
4877
4878 drm_agp_chipset_flush(dev);
4879 return 0;
4880}
b962442e
EA		 4881
4882void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4883{
4884 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4885
4886 /* Clean up our request list when the client is going away, so that
4887 * later retire_requests won't dereference our soon-to-be-gone
4888 * file_priv.
4889 */
4890 mutex_lock(&dev->struct_mutex);
4891 while (!list_empty(&i915_file_priv->mm.request_list))
4892 list_del_init(i915_file_priv->mm.request_list.next);
4893 mutex_unlock(&dev->struct_mutex);
4894}
31169714 4895
1637ef41
CW		 4896static int
4897i915_gpu_is_active(struct drm_device *dev)
4898{
4899 drm_i915_private_t *dev_priv = dev->dev_private;
4900 int lists_empty;
4901
4902 spin_lock(&dev_priv->mm.active_list_lock);
4903 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 4904 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 4905 if (HAS_BSD(dev))
4906 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 4907 spin_unlock(&dev_priv->mm.active_list_lock);
4908
4909 return !lists_empty;
4910}
4911
31169714 4912static int
7f8275d0 4913i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
31169714
CW		 4914{
4915 drm_i915_private_t *dev_priv, *next_dev;
4916 struct drm_i915_gem_object *obj_priv, *next_obj;
4917 int cnt = 0;
4918 int would_deadlock = 1;
4919
4920 /* "fast-path" to count number of available objects */
4921 if (nr_to_scan == 0) {
4922 spin_lock(&shrink_list_lock);
4923 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4924 struct drm_device *dev = dev_priv->dev;
4925
4926 if (mutex_trylock(&dev->struct_mutex)) {
4927 list_for_each_entry(obj_priv,
4928 &dev_priv->mm.inactive_list,
4929 list)
4930 cnt++;
4931 mutex_unlock(&dev->struct_mutex);
4932 }
4933 }
4934 spin_unlock(&shrink_list_lock);
4935
4936 return (cnt / 100) * sysctl_vfs_cache_pressure;
4937 }
4938
4939 spin_lock(&shrink_list_lock);
4940
1637ef41 4941rescan:
31169714
CW		 4942 /* first scan for clean buffers */
4943 list_for_each_entry_safe(dev_priv, next_dev,
4944 &shrink_list, mm.shrink_list) {
4945 struct drm_device *dev = dev_priv->dev;
4946
4947 if (! mutex_trylock(&dev->struct_mutex))
4948 continue;
4949
4950 spin_unlock(&shrink_list_lock);
b09a1fec 4951 i915_gem_retire_requests(dev);
31169714
CW		 4952
4953 list_for_each_entry_safe(obj_priv, next_obj,
4954 &dev_priv->mm.inactive_list,
4955 list) {
4956 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 4957 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 4958 if (--nr_to_scan <= 0)
4959 break;
4960 }
4961 }
4962
4963 spin_lock(&shrink_list_lock);
4964 mutex_unlock(&dev->struct_mutex);
4965
963b4836
CW		 4966 would_deadlock = 0;
4967
31169714
CW		 4968 if (nr_to_scan <= 0)
4969 break;
4970 }
4971
4972 /* second pass, evict/count anything still on the inactive list */
4973 list_for_each_entry_safe(dev_priv, next_dev,
4974 &shrink_list, mm.shrink_list) {
4975 struct drm_device *dev = dev_priv->dev;
4976
4977 if (! mutex_trylock(&dev->struct_mutex))
4978 continue;
4979
4980 spin_unlock(&shrink_list_lock);
4981
4982 list_for_each_entry_safe(obj_priv, next_obj,
4983 &dev_priv->mm.inactive_list,
4984 list) {
4985 if (nr_to_scan > 0) {
a8089e84 4986 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 4987 nr_to_scan--;
4988 } else
4989 cnt++;
4990 }
4991
4992 spin_lock(&shrink_list_lock);
4993 mutex_unlock(&dev->struct_mutex);
4994
4995 would_deadlock = 0;
4996 }
4997
1637ef41
CW		 4998 if (nr_to_scan) {
4999 int active = 0;
5000
5001 /*
5002 * We are desperate for pages, so as a last resort, wait
5003 * for the GPU to finish and discard whatever we can.
5004 * This has a dramatic impact to reduce the number of
5005 * OOM-killer events whilst running the GPU aggressively.
5006 */
5007 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5008 struct drm_device *dev = dev_priv->dev;
5009
5010 if (!mutex_trylock(&dev->struct_mutex))
5011 continue;
5012
5013 spin_unlock(&shrink_list_lock);
5014
5015 if (i915_gpu_is_active(dev)) {
5016 i915_gpu_idle(dev);
5017 active++;
5018 }
5019
5020 spin_lock(&shrink_list_lock);
5021 mutex_unlock(&dev->struct_mutex);
5022 }
5023
5024 if (active)
5025 goto rescan;
5026 }
5027
31169714
CW		 5028 spin_unlock(&shrink_list_lock);
5029
5030 if (would_deadlock)
5031 return -1;
5032 else if (cnt > 0)
5033 return (cnt / 100) * sysctl_vfs_cache_pressure;
5034 else
5035 return 0;
5036}
5037
5038static struct shrinker shrinker = {
5039 .shrink = i915_gem_shrink,
5040 .seeks = DEFAULT_SEEKS,
5041};
5042
5043__init void
5044i915_gem_shrinker_init(void)
5045{
5046 register_shrinker(&shrinker);
5047}
5048
5049__exit void
5050i915_gem_shrinker_exit(void)
5051{
5052 unregister_shrinker(&shrinker);
5053}