Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0f8c6d7c CW |
39 | struct change_domains { |
40 | uint32_t invalidate_domains; | |
41 | uint32_t flush_domains; | |
42 | uint32_t flush_rings; | |
43 | }; | |
44 | ||
a00b10c3 CW |
45 | static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv); |
46 | static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv); | |
ba3d8d74 DV |
47 | |
48 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
49 | bool pipelined); | |
e47c68e9 EA |
50 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
51 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
52 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
53 | int write); | |
54 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
55 | uint64_t offset, | |
56 | uint64_t size); | |
57 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
58 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
59 | bool interruptible); | |
de151cf6 | 60 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
a00b10c3 | 61 | unsigned alignment, |
75e9e915 | 62 | bool map_and_fenceable); |
de151cf6 | 63 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
64 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
65 | struct drm_i915_gem_pwrite *args, | |
66 | struct drm_file *file_priv); | |
be72615b | 67 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 68 | |
17250b71 CW |
69 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
70 | int nr_to_scan, | |
71 | gfp_t gfp_mask); | |
72 | ||
31169714 | 73 | |
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
89 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 90 | struct drm_i915_gem_object *obj) |
73aa808f CW |
91 | { |
92 | dev_priv->mm.gtt_count++; | |
a00b10c3 CW |
93 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
94 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 95 | dev_priv->mm.mappable_gtt_used += |
a00b10c3 CW |
96 | min_t(size_t, obj->gtt_space->size, |
97 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 98 | } |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 102 | struct drm_i915_gem_object *obj) |
73aa808f CW |
103 | { |
104 | dev_priv->mm.gtt_count--; | |
a00b10c3 CW |
105 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
106 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 107 | dev_priv->mm.mappable_gtt_used -= |
a00b10c3 CW |
108 | min_t(size_t, obj->gtt_space->size, |
109 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a DV |
110 | } |
111 | } | |
112 | ||
113 | /** | |
114 | * Update the mappable working set counters. Call _only_ when there is a change | |
115 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
116 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
117 | */ | |
118 | static void | |
119 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
a00b10c3 | 120 | struct drm_i915_gem_object *obj, |
fb7d516a DV |
121 | bool mappable) |
122 | { | |
fb7d516a | 123 | if (mappable) { |
a00b10c3 | 124 | if (obj->pin_mappable && obj->fault_mappable) |
fb7d516a DV |
125 | /* Combined state was already mappable. */ |
126 | return; | |
127 | dev_priv->mm.gtt_mappable_count++; | |
a00b10c3 | 128 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
fb7d516a | 129 | } else { |
a00b10c3 | 130 | if (obj->pin_mappable || obj->fault_mappable) |
fb7d516a DV |
131 | /* Combined state still mappable. */ |
132 | return; | |
133 | dev_priv->mm.gtt_mappable_count--; | |
a00b10c3 | 134 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
fb7d516a | 135 | } |
73aa808f CW |
136 | } |
137 | ||
138 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 139 | struct drm_i915_gem_object *obj, |
fb7d516a | 140 | bool mappable) |
73aa808f CW |
141 | { |
142 | dev_priv->mm.pin_count++; | |
a00b10c3 | 143 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
fb7d516a | 144 | if (mappable) { |
a00b10c3 | 145 | obj->pin_mappable = true; |
fb7d516a DV |
146 | i915_gem_info_update_mappable(dev_priv, obj, true); |
147 | } | |
73aa808f CW |
148 | } |
149 | ||
150 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 151 | struct drm_i915_gem_object *obj) |
73aa808f CW |
152 | { |
153 | dev_priv->mm.pin_count--; | |
a00b10c3 CW |
154 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
155 | if (obj->pin_mappable) { | |
156 | obj->pin_mappable = false; | |
fb7d516a DV |
157 | i915_gem_info_update_mappable(dev_priv, obj, false); |
158 | } | |
73aa808f CW |
159 | } |
160 | ||
30dbf0c0 CW |
161 | int |
162 | i915_gem_check_is_wedged(struct drm_device *dev) | |
163 | { | |
164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
165 | struct completion *x = &dev_priv->error_completion; | |
166 | unsigned long flags; | |
167 | int ret; | |
168 | ||
169 | if (!atomic_read(&dev_priv->mm.wedged)) | |
170 | return 0; | |
171 | ||
172 | ret = wait_for_completion_interruptible(x); | |
173 | if (ret) | |
174 | return ret; | |
175 | ||
176 | /* Success, we reset the GPU! */ | |
177 | if (!atomic_read(&dev_priv->mm.wedged)) | |
178 | return 0; | |
179 | ||
180 | /* GPU is hung, bump the completion count to account for | |
181 | * the token we just consumed so that we never hit zero and | |
182 | * end up waiting upon a subsequent completion event that | |
183 | * will never happen. | |
184 | */ | |
185 | spin_lock_irqsave(&x->wait.lock, flags); | |
186 | x->done++; | |
187 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
188 | return -EIO; | |
189 | } | |
190 | ||
76c1dec1 CW |
191 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
192 | { | |
193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
194 | int ret; | |
195 | ||
196 | ret = i915_gem_check_is_wedged(dev); | |
197 | if (ret) | |
198 | return ret; | |
199 | ||
200 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
201 | if (ret) | |
202 | return ret; | |
203 | ||
204 | if (atomic_read(&dev_priv->mm.wedged)) { | |
205 | mutex_unlock(&dev->struct_mutex); | |
206 | return -EAGAIN; | |
207 | } | |
208 | ||
23bc5982 | 209 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
210 | return 0; |
211 | } | |
30dbf0c0 | 212 | |
7d1c4804 CW |
213 | static inline bool |
214 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
215 | { | |
216 | return obj_priv->gtt_space && | |
217 | !obj_priv->active && | |
218 | obj_priv->pin_count == 0; | |
219 | } | |
220 | ||
73aa808f CW |
221 | int i915_gem_do_init(struct drm_device *dev, |
222 | unsigned long start, | |
53984635 | 223 | unsigned long mappable_end, |
79e53945 | 224 | unsigned long end) |
673a394b EA |
225 | { |
226 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 227 | |
79e53945 JB |
228 | if (start >= end || |
229 | (start & (PAGE_SIZE - 1)) != 0 || | |
230 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
231 | return -EINVAL; |
232 | } | |
233 | ||
79e53945 JB |
234 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
235 | end - start); | |
673a394b | 236 | |
73aa808f | 237 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 238 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 239 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
240 | |
241 | return 0; | |
242 | } | |
673a394b | 243 | |
79e53945 JB |
244 | int |
245 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
246 | struct drm_file *file_priv) | |
247 | { | |
248 | struct drm_i915_gem_init *args = data; | |
249 | int ret; | |
250 | ||
251 | mutex_lock(&dev->struct_mutex); | |
53984635 | 252 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
253 | mutex_unlock(&dev->struct_mutex); |
254 | ||
79e53945 | 255 | return ret; |
673a394b EA |
256 | } |
257 | ||
5a125c3c EA |
258 | int |
259 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
260 | struct drm_file *file_priv) | |
261 | { | |
73aa808f | 262 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 263 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
264 | |
265 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
266 | return -ENODEV; | |
267 | ||
73aa808f CW |
268 | mutex_lock(&dev->struct_mutex); |
269 | args->aper_size = dev_priv->mm.gtt_total; | |
270 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
271 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
673a394b EA |
276 | |
277 | /** | |
278 | * Creates a new mm object and returns a handle to it. | |
279 | */ | |
280 | int | |
281 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
282 | struct drm_file *file_priv) | |
283 | { | |
284 | struct drm_i915_gem_create *args = data; | |
285 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
286 | int ret; |
287 | u32 handle; | |
673a394b EA |
288 | |
289 | args->size = roundup(args->size, PAGE_SIZE); | |
290 | ||
291 | /* Allocate the new object */ | |
ac52bc56 | 292 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
293 | if (obj == NULL) |
294 | return -ENOMEM; | |
295 | ||
296 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 297 | if (ret) { |
202f2fef CW |
298 | drm_gem_object_release(obj); |
299 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
300 | kfree(obj); | |
673a394b | 301 | return ret; |
1dfd9754 | 302 | } |
673a394b | 303 | |
202f2fef CW |
304 | /* drop reference from allocate - handle holds it now */ |
305 | drm_gem_object_unreference(obj); | |
306 | trace_i915_gem_object_create(obj); | |
307 | ||
1dfd9754 | 308 | args->handle = handle; |
673a394b EA |
309 | return 0; |
310 | } | |
311 | ||
280b713b EA |
312 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
313 | { | |
314 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 315 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
316 | |
317 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
318 | obj_priv->tiling_mode != I915_TILING_NONE; | |
319 | } | |
320 | ||
99a03df5 | 321 | static inline void |
40123c1f EA |
322 | slow_shmem_copy(struct page *dst_page, |
323 | int dst_offset, | |
324 | struct page *src_page, | |
325 | int src_offset, | |
326 | int length) | |
327 | { | |
328 | char *dst_vaddr, *src_vaddr; | |
329 | ||
99a03df5 CW |
330 | dst_vaddr = kmap(dst_page); |
331 | src_vaddr = kmap(src_page); | |
40123c1f EA |
332 | |
333 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
334 | ||
99a03df5 CW |
335 | kunmap(src_page); |
336 | kunmap(dst_page); | |
40123c1f EA |
337 | } |
338 | ||
99a03df5 | 339 | static inline void |
280b713b EA |
340 | slow_shmem_bit17_copy(struct page *gpu_page, |
341 | int gpu_offset, | |
342 | struct page *cpu_page, | |
343 | int cpu_offset, | |
344 | int length, | |
345 | int is_read) | |
346 | { | |
347 | char *gpu_vaddr, *cpu_vaddr; | |
348 | ||
349 | /* Use the unswizzled path if this page isn't affected. */ | |
350 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
351 | if (is_read) | |
352 | return slow_shmem_copy(cpu_page, cpu_offset, | |
353 | gpu_page, gpu_offset, length); | |
354 | else | |
355 | return slow_shmem_copy(gpu_page, gpu_offset, | |
356 | cpu_page, cpu_offset, length); | |
357 | } | |
358 | ||
99a03df5 CW |
359 | gpu_vaddr = kmap(gpu_page); |
360 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
361 | |
362 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
363 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
364 | */ | |
365 | while (length > 0) { | |
366 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
367 | int this_length = min(cacheline_end - gpu_offset, length); | |
368 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
369 | ||
370 | if (is_read) { | |
371 | memcpy(cpu_vaddr + cpu_offset, | |
372 | gpu_vaddr + swizzled_gpu_offset, | |
373 | this_length); | |
374 | } else { | |
375 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
376 | cpu_vaddr + cpu_offset, | |
377 | this_length); | |
378 | } | |
379 | cpu_offset += this_length; | |
380 | gpu_offset += this_length; | |
381 | length -= this_length; | |
382 | } | |
383 | ||
99a03df5 CW |
384 | kunmap(cpu_page); |
385 | kunmap(gpu_page); | |
280b713b EA |
386 | } |
387 | ||
eb01459f EA |
388 | /** |
389 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
390 | * from the backing pages of the object to the user's address space. On a | |
391 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
392 | */ | |
393 | static int | |
394 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
395 | struct drm_i915_gem_pread *args, | |
396 | struct drm_file *file_priv) | |
397 | { | |
23010e43 | 398 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
e5281ccd | 399 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 400 | ssize_t remain; |
e5281ccd | 401 | loff_t offset; |
eb01459f EA |
402 | char __user *user_data; |
403 | int page_offset, page_length; | |
eb01459f EA |
404 | |
405 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
406 | remain = args->size; | |
407 | ||
23010e43 | 408 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
409 | offset = args->offset; |
410 | ||
411 | while (remain > 0) { | |
e5281ccd CW |
412 | struct page *page; |
413 | char *vaddr; | |
414 | int ret; | |
415 | ||
eb01459f EA |
416 | /* Operation in this page |
417 | * | |
eb01459f EA |
418 | * page_offset = offset within page |
419 | * page_length = bytes to copy for this page | |
420 | */ | |
eb01459f EA |
421 | page_offset = offset & (PAGE_SIZE-1); |
422 | page_length = remain; | |
423 | if ((page_offset + remain) > PAGE_SIZE) | |
424 | page_length = PAGE_SIZE - page_offset; | |
425 | ||
e5281ccd CW |
426 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
427 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
428 | if (IS_ERR(page)) | |
429 | return PTR_ERR(page); | |
430 | ||
431 | vaddr = kmap_atomic(page); | |
432 | ret = __copy_to_user_inatomic(user_data, | |
433 | vaddr + page_offset, | |
434 | page_length); | |
435 | kunmap_atomic(vaddr); | |
436 | ||
437 | mark_page_accessed(page); | |
438 | page_cache_release(page); | |
439 | if (ret) | |
4f27b75d | 440 | return -EFAULT; |
eb01459f EA |
441 | |
442 | remain -= page_length; | |
443 | user_data += page_length; | |
444 | offset += page_length; | |
445 | } | |
446 | ||
4f27b75d | 447 | return 0; |
eb01459f EA |
448 | } |
449 | ||
450 | /** | |
451 | * This is the fallback shmem pread path, which allocates temporary storage | |
452 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
453 | * can copy out of the object's backing pages while holding the struct mutex | |
454 | * and not take page faults. | |
455 | */ | |
456 | static int | |
457 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
458 | struct drm_i915_gem_pread *args, | |
459 | struct drm_file *file_priv) | |
460 | { | |
e5281ccd | 461 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 462 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
463 | struct mm_struct *mm = current->mm; |
464 | struct page **user_pages; | |
465 | ssize_t remain; | |
466 | loff_t offset, pinned_pages, i; | |
467 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
468 | int shmem_page_offset; |
469 | int data_page_index, data_page_offset; | |
eb01459f EA |
470 | int page_length; |
471 | int ret; | |
472 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 473 | int do_bit17_swizzling; |
eb01459f EA |
474 | |
475 | remain = args->size; | |
476 | ||
477 | /* Pin the user pages containing the data. We can't fault while | |
478 | * holding the struct mutex, yet we want to hold it while | |
479 | * dereferencing the user data. | |
480 | */ | |
481 | first_data_page = data_ptr / PAGE_SIZE; | |
482 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
483 | num_pages = last_data_page - first_data_page + 1; | |
484 | ||
4f27b75d | 485 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
486 | if (user_pages == NULL) |
487 | return -ENOMEM; | |
488 | ||
4f27b75d | 489 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
490 | down_read(&mm->mmap_sem); |
491 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 492 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 493 | up_read(&mm->mmap_sem); |
4f27b75d | 494 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
495 | if (pinned_pages < num_pages) { |
496 | ret = -EFAULT; | |
4f27b75d | 497 | goto out; |
eb01459f EA |
498 | } |
499 | ||
4f27b75d CW |
500 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
501 | args->offset, | |
502 | args->size); | |
07f73f69 | 503 | if (ret) |
4f27b75d | 504 | goto out; |
eb01459f | 505 | |
4f27b75d | 506 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 507 | |
23010e43 | 508 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
509 | offset = args->offset; |
510 | ||
511 | while (remain > 0) { | |
e5281ccd CW |
512 | struct page *page; |
513 | ||
eb01459f EA |
514 | /* Operation in this page |
515 | * | |
eb01459f EA |
516 | * shmem_page_offset = offset within page in shmem file |
517 | * data_page_index = page number in get_user_pages return | |
518 | * data_page_offset = offset with data_page_index page. | |
519 | * page_length = bytes to copy for this page | |
520 | */ | |
eb01459f EA |
521 | shmem_page_offset = offset & ~PAGE_MASK; |
522 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
523 | data_page_offset = data_ptr & ~PAGE_MASK; | |
524 | ||
525 | page_length = remain; | |
526 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
527 | page_length = PAGE_SIZE - shmem_page_offset; | |
528 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
529 | page_length = PAGE_SIZE - data_page_offset; | |
530 | ||
e5281ccd CW |
531 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
532 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
533 | if (IS_ERR(page)) | |
534 | return PTR_ERR(page); | |
535 | ||
280b713b | 536 | if (do_bit17_swizzling) { |
e5281ccd | 537 | slow_shmem_bit17_copy(page, |
280b713b | 538 | shmem_page_offset, |
99a03df5 CW |
539 | user_pages[data_page_index], |
540 | data_page_offset, | |
541 | page_length, | |
542 | 1); | |
543 | } else { | |
544 | slow_shmem_copy(user_pages[data_page_index], | |
545 | data_page_offset, | |
e5281ccd | 546 | page, |
99a03df5 CW |
547 | shmem_page_offset, |
548 | page_length); | |
280b713b | 549 | } |
eb01459f | 550 | |
e5281ccd CW |
551 | mark_page_accessed(page); |
552 | page_cache_release(page); | |
553 | ||
eb01459f EA |
554 | remain -= page_length; |
555 | data_ptr += page_length; | |
556 | offset += page_length; | |
557 | } | |
558 | ||
4f27b75d | 559 | out: |
eb01459f EA |
560 | for (i = 0; i < pinned_pages; i++) { |
561 | SetPageDirty(user_pages[i]); | |
e5281ccd | 562 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
563 | page_cache_release(user_pages[i]); |
564 | } | |
8e7d2b2c | 565 | drm_free_large(user_pages); |
eb01459f EA |
566 | |
567 | return ret; | |
568 | } | |
569 | ||
673a394b EA |
570 | /** |
571 | * Reads data from the object referenced by handle. | |
572 | * | |
573 | * On error, the contents of *data are undefined. | |
574 | */ | |
575 | int | |
576 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
577 | struct drm_file *file_priv) | |
578 | { | |
579 | struct drm_i915_gem_pread *args = data; | |
580 | struct drm_gem_object *obj; | |
581 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 582 | int ret = 0; |
673a394b | 583 | |
4f27b75d | 584 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 585 | if (ret) |
4f27b75d | 586 | return ret; |
673a394b EA |
587 | |
588 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
589 | if (obj == NULL) { |
590 | ret = -ENOENT; | |
591 | goto unlock; | |
4f27b75d | 592 | } |
23010e43 | 593 | obj_priv = to_intel_bo(obj); |
673a394b | 594 | |
7dcd2499 CW |
595 | /* Bounds check source. */ |
596 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 597 | ret = -EINVAL; |
35b62a89 | 598 | goto out; |
ce9d419d CW |
599 | } |
600 | ||
35b62a89 CW |
601 | if (args->size == 0) |
602 | goto out; | |
603 | ||
ce9d419d CW |
604 | if (!access_ok(VERIFY_WRITE, |
605 | (char __user *)(uintptr_t)args->data_ptr, | |
606 | args->size)) { | |
607 | ret = -EFAULT; | |
35b62a89 | 608 | goto out; |
673a394b EA |
609 | } |
610 | ||
b5e4feb6 CW |
611 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
612 | args->size); | |
613 | if (ret) { | |
614 | ret = -EFAULT; | |
615 | goto out; | |
280b713b | 616 | } |
673a394b | 617 | |
4f27b75d CW |
618 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
619 | args->offset, | |
620 | args->size); | |
621 | if (ret) | |
e5281ccd | 622 | goto out; |
4f27b75d CW |
623 | |
624 | ret = -EFAULT; | |
625 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 626 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
627 | if (ret == -EFAULT) |
628 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 629 | |
35b62a89 | 630 | out: |
4f27b75d | 631 | drm_gem_object_unreference(obj); |
1d7cfea1 | 632 | unlock: |
4f27b75d | 633 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 634 | return ret; |
673a394b EA |
635 | } |
636 | ||
0839ccb8 KP |
637 | /* This is the fast write path which cannot handle |
638 | * page faults in the source data | |
9b7530cc | 639 | */ |
0839ccb8 KP |
640 | |
641 | static inline int | |
642 | fast_user_write(struct io_mapping *mapping, | |
643 | loff_t page_base, int page_offset, | |
644 | char __user *user_data, | |
645 | int length) | |
9b7530cc | 646 | { |
9b7530cc | 647 | char *vaddr_atomic; |
0839ccb8 | 648 | unsigned long unwritten; |
9b7530cc | 649 | |
3e4d3af5 | 650 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
651 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
652 | user_data, length); | |
3e4d3af5 | 653 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 654 | return unwritten; |
0839ccb8 KP |
655 | } |
656 | ||
657 | /* Here's the write path which can sleep for | |
658 | * page faults | |
659 | */ | |
660 | ||
ab34c226 | 661 | static inline void |
3de09aa3 EA |
662 | slow_kernel_write(struct io_mapping *mapping, |
663 | loff_t gtt_base, int gtt_offset, | |
664 | struct page *user_page, int user_offset, | |
665 | int length) | |
0839ccb8 | 666 | { |
ab34c226 CW |
667 | char __iomem *dst_vaddr; |
668 | char *src_vaddr; | |
0839ccb8 | 669 | |
ab34c226 CW |
670 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
671 | src_vaddr = kmap(user_page); | |
672 | ||
673 | memcpy_toio(dst_vaddr + gtt_offset, | |
674 | src_vaddr + user_offset, | |
675 | length); | |
676 | ||
677 | kunmap(user_page); | |
678 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
679 | } |
680 | ||
3de09aa3 EA |
681 | /** |
682 | * This is the fast pwrite path, where we copy the data directly from the | |
683 | * user into the GTT, uncached. | |
684 | */ | |
673a394b | 685 | static int |
3de09aa3 EA |
686 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
687 | struct drm_i915_gem_pwrite *args, | |
688 | struct drm_file *file_priv) | |
673a394b | 689 | { |
23010e43 | 690 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 691 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 692 | ssize_t remain; |
0839ccb8 | 693 | loff_t offset, page_base; |
673a394b | 694 | char __user *user_data; |
0839ccb8 | 695 | int page_offset, page_length; |
673a394b EA |
696 | |
697 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
698 | remain = args->size; | |
673a394b | 699 | |
23010e43 | 700 | obj_priv = to_intel_bo(obj); |
673a394b | 701 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
702 | |
703 | while (remain > 0) { | |
704 | /* Operation in this page | |
705 | * | |
0839ccb8 KP |
706 | * page_base = page offset within aperture |
707 | * page_offset = offset within page | |
708 | * page_length = bytes to copy for this page | |
673a394b | 709 | */ |
0839ccb8 KP |
710 | page_base = (offset & ~(PAGE_SIZE-1)); |
711 | page_offset = offset & (PAGE_SIZE-1); | |
712 | page_length = remain; | |
713 | if ((page_offset + remain) > PAGE_SIZE) | |
714 | page_length = PAGE_SIZE - page_offset; | |
715 | ||
0839ccb8 | 716 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
717 | * source page isn't available. Return the error and we'll |
718 | * retry in the slow path. | |
0839ccb8 | 719 | */ |
fbd5a26d CW |
720 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
721 | page_offset, user_data, page_length)) | |
722 | ||
723 | return -EFAULT; | |
673a394b | 724 | |
0839ccb8 KP |
725 | remain -= page_length; |
726 | user_data += page_length; | |
727 | offset += page_length; | |
673a394b | 728 | } |
673a394b | 729 | |
fbd5a26d | 730 | return 0; |
673a394b EA |
731 | } |
732 | ||
3de09aa3 EA |
733 | /** |
734 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
735 | * the memory and maps it using kmap_atomic for copying. | |
736 | * | |
737 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
738 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
739 | */ | |
3043c60c | 740 | static int |
3de09aa3 EA |
741 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
742 | struct drm_i915_gem_pwrite *args, | |
743 | struct drm_file *file_priv) | |
673a394b | 744 | { |
23010e43 | 745 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
746 | drm_i915_private_t *dev_priv = dev->dev_private; |
747 | ssize_t remain; | |
748 | loff_t gtt_page_base, offset; | |
749 | loff_t first_data_page, last_data_page, num_pages; | |
750 | loff_t pinned_pages, i; | |
751 | struct page **user_pages; | |
752 | struct mm_struct *mm = current->mm; | |
753 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 754 | int ret; |
3de09aa3 EA |
755 | uint64_t data_ptr = args->data_ptr; |
756 | ||
757 | remain = args->size; | |
758 | ||
759 | /* Pin the user pages containing the data. We can't fault while | |
760 | * holding the struct mutex, and all of the pwrite implementations | |
761 | * want to hold it while dereferencing the user data. | |
762 | */ | |
763 | first_data_page = data_ptr / PAGE_SIZE; | |
764 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
765 | num_pages = last_data_page - first_data_page + 1; | |
766 | ||
fbd5a26d | 767 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
768 | if (user_pages == NULL) |
769 | return -ENOMEM; | |
770 | ||
fbd5a26d | 771 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
772 | down_read(&mm->mmap_sem); |
773 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
774 | num_pages, 0, 0, user_pages, NULL); | |
775 | up_read(&mm->mmap_sem); | |
fbd5a26d | 776 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
777 | if (pinned_pages < num_pages) { |
778 | ret = -EFAULT; | |
779 | goto out_unpin_pages; | |
780 | } | |
673a394b | 781 | |
3de09aa3 EA |
782 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
783 | if (ret) | |
fbd5a26d | 784 | goto out_unpin_pages; |
3de09aa3 | 785 | |
23010e43 | 786 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
787 | offset = obj_priv->gtt_offset + args->offset; |
788 | ||
789 | while (remain > 0) { | |
790 | /* Operation in this page | |
791 | * | |
792 | * gtt_page_base = page offset within aperture | |
793 | * gtt_page_offset = offset within page in aperture | |
794 | * data_page_index = page number in get_user_pages return | |
795 | * data_page_offset = offset with data_page_index page. | |
796 | * page_length = bytes to copy for this page | |
797 | */ | |
798 | gtt_page_base = offset & PAGE_MASK; | |
799 | gtt_page_offset = offset & ~PAGE_MASK; | |
800 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
801 | data_page_offset = data_ptr & ~PAGE_MASK; | |
802 | ||
803 | page_length = remain; | |
804 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
805 | page_length = PAGE_SIZE - gtt_page_offset; | |
806 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
807 | page_length = PAGE_SIZE - data_page_offset; | |
808 | ||
ab34c226 CW |
809 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
810 | gtt_page_base, gtt_page_offset, | |
811 | user_pages[data_page_index], | |
812 | data_page_offset, | |
813 | page_length); | |
3de09aa3 EA |
814 | |
815 | remain -= page_length; | |
816 | offset += page_length; | |
817 | data_ptr += page_length; | |
818 | } | |
819 | ||
3de09aa3 EA |
820 | out_unpin_pages: |
821 | for (i = 0; i < pinned_pages; i++) | |
822 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 823 | drm_free_large(user_pages); |
3de09aa3 EA |
824 | |
825 | return ret; | |
826 | } | |
827 | ||
40123c1f EA |
828 | /** |
829 | * This is the fast shmem pwrite path, which attempts to directly | |
830 | * copy_from_user into the kmapped pages backing the object. | |
831 | */ | |
3043c60c | 832 | static int |
40123c1f EA |
833 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
834 | struct drm_i915_gem_pwrite *args, | |
835 | struct drm_file *file_priv) | |
673a394b | 836 | { |
e5281ccd | 837 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 838 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f | 839 | ssize_t remain; |
e5281ccd | 840 | loff_t offset; |
40123c1f EA |
841 | char __user *user_data; |
842 | int page_offset, page_length; | |
40123c1f EA |
843 | |
844 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
845 | remain = args->size; | |
673a394b | 846 | |
23010e43 | 847 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
848 | offset = args->offset; |
849 | obj_priv->dirty = 1; | |
850 | ||
851 | while (remain > 0) { | |
e5281ccd CW |
852 | struct page *page; |
853 | char *vaddr; | |
854 | int ret; | |
855 | ||
40123c1f EA |
856 | /* Operation in this page |
857 | * | |
40123c1f EA |
858 | * page_offset = offset within page |
859 | * page_length = bytes to copy for this page | |
860 | */ | |
40123c1f EA |
861 | page_offset = offset & (PAGE_SIZE-1); |
862 | page_length = remain; | |
863 | if ((page_offset + remain) > PAGE_SIZE) | |
864 | page_length = PAGE_SIZE - page_offset; | |
865 | ||
e5281ccd CW |
866 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
867 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
868 | if (IS_ERR(page)) | |
869 | return PTR_ERR(page); | |
870 | ||
871 | vaddr = kmap_atomic(page, KM_USER0); | |
872 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
873 | user_data, | |
874 | page_length); | |
875 | kunmap_atomic(vaddr, KM_USER0); | |
876 | ||
877 | set_page_dirty(page); | |
878 | mark_page_accessed(page); | |
879 | page_cache_release(page); | |
880 | ||
881 | /* If we get a fault while copying data, then (presumably) our | |
882 | * source page isn't available. Return the error and we'll | |
883 | * retry in the slow path. | |
884 | */ | |
885 | if (ret) | |
fbd5a26d | 886 | return -EFAULT; |
40123c1f EA |
887 | |
888 | remain -= page_length; | |
889 | user_data += page_length; | |
890 | offset += page_length; | |
891 | } | |
892 | ||
fbd5a26d | 893 | return 0; |
40123c1f EA |
894 | } |
895 | ||
896 | /** | |
897 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
898 | * the memory and maps it using kmap_atomic for copying. | |
899 | * | |
900 | * This avoids taking mmap_sem for faulting on the user's address while the | |
901 | * struct_mutex is held. | |
902 | */ | |
903 | static int | |
904 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
905 | struct drm_i915_gem_pwrite *args, | |
906 | struct drm_file *file_priv) | |
907 | { | |
e5281ccd | 908 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 909 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
910 | struct mm_struct *mm = current->mm; |
911 | struct page **user_pages; | |
912 | ssize_t remain; | |
913 | loff_t offset, pinned_pages, i; | |
914 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 915 | int shmem_page_offset; |
40123c1f EA |
916 | int data_page_index, data_page_offset; |
917 | int page_length; | |
918 | int ret; | |
919 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 920 | int do_bit17_swizzling; |
40123c1f EA |
921 | |
922 | remain = args->size; | |
923 | ||
924 | /* Pin the user pages containing the data. We can't fault while | |
925 | * holding the struct mutex, and all of the pwrite implementations | |
926 | * want to hold it while dereferencing the user data. | |
927 | */ | |
928 | first_data_page = data_ptr / PAGE_SIZE; | |
929 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
930 | num_pages = last_data_page - first_data_page + 1; | |
931 | ||
4f27b75d | 932 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
933 | if (user_pages == NULL) |
934 | return -ENOMEM; | |
935 | ||
fbd5a26d | 936 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
937 | down_read(&mm->mmap_sem); |
938 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
939 | num_pages, 0, 0, user_pages, NULL); | |
940 | up_read(&mm->mmap_sem); | |
fbd5a26d | 941 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
942 | if (pinned_pages < num_pages) { |
943 | ret = -EFAULT; | |
fbd5a26d | 944 | goto out; |
673a394b EA |
945 | } |
946 | ||
fbd5a26d | 947 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 948 | if (ret) |
fbd5a26d | 949 | goto out; |
40123c1f | 950 | |
fbd5a26d | 951 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 952 | |
23010e43 | 953 | obj_priv = to_intel_bo(obj); |
673a394b | 954 | offset = args->offset; |
40123c1f | 955 | obj_priv->dirty = 1; |
673a394b | 956 | |
40123c1f | 957 | while (remain > 0) { |
e5281ccd CW |
958 | struct page *page; |
959 | ||
40123c1f EA |
960 | /* Operation in this page |
961 | * | |
40123c1f EA |
962 | * shmem_page_offset = offset within page in shmem file |
963 | * data_page_index = page number in get_user_pages return | |
964 | * data_page_offset = offset with data_page_index page. | |
965 | * page_length = bytes to copy for this page | |
966 | */ | |
40123c1f EA |
967 | shmem_page_offset = offset & ~PAGE_MASK; |
968 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
969 | data_page_offset = data_ptr & ~PAGE_MASK; | |
970 | ||
971 | page_length = remain; | |
972 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
973 | page_length = PAGE_SIZE - shmem_page_offset; | |
974 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
975 | page_length = PAGE_SIZE - data_page_offset; | |
976 | ||
e5281ccd CW |
977 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
978 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
979 | if (IS_ERR(page)) { | |
980 | ret = PTR_ERR(page); | |
981 | goto out; | |
982 | } | |
983 | ||
280b713b | 984 | if (do_bit17_swizzling) { |
e5281ccd | 985 | slow_shmem_bit17_copy(page, |
280b713b EA |
986 | shmem_page_offset, |
987 | user_pages[data_page_index], | |
988 | data_page_offset, | |
99a03df5 CW |
989 | page_length, |
990 | 0); | |
991 | } else { | |
e5281ccd | 992 | slow_shmem_copy(page, |
99a03df5 CW |
993 | shmem_page_offset, |
994 | user_pages[data_page_index], | |
995 | data_page_offset, | |
996 | page_length); | |
280b713b | 997 | } |
40123c1f | 998 | |
e5281ccd CW |
999 | set_page_dirty(page); |
1000 | mark_page_accessed(page); | |
1001 | page_cache_release(page); | |
1002 | ||
40123c1f EA |
1003 | remain -= page_length; |
1004 | data_ptr += page_length; | |
1005 | offset += page_length; | |
673a394b EA |
1006 | } |
1007 | ||
fbd5a26d | 1008 | out: |
40123c1f EA |
1009 | for (i = 0; i < pinned_pages; i++) |
1010 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1011 | drm_free_large(user_pages); |
673a394b | 1012 | |
40123c1f | 1013 | return ret; |
673a394b EA |
1014 | } |
1015 | ||
1016 | /** | |
1017 | * Writes data to the object referenced by handle. | |
1018 | * | |
1019 | * On error, the contents of the buffer that were to be modified are undefined. | |
1020 | */ | |
1021 | int | |
1022 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1023 | struct drm_file *file) |
673a394b EA |
1024 | { |
1025 | struct drm_i915_gem_pwrite *args = data; | |
1026 | struct drm_gem_object *obj; | |
1027 | struct drm_i915_gem_object *obj_priv; | |
1028 | int ret = 0; | |
1029 | ||
fbd5a26d | 1030 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1031 | if (ret) |
fbd5a26d | 1032 | return ret; |
1d7cfea1 CW |
1033 | |
1034 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1035 | if (obj == NULL) { | |
1036 | ret = -ENOENT; | |
1037 | goto unlock; | |
fbd5a26d | 1038 | } |
23010e43 | 1039 | obj_priv = to_intel_bo(obj); |
673a394b | 1040 | |
fbd5a26d | 1041 | |
7dcd2499 CW |
1042 | /* Bounds check destination. */ |
1043 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1044 | ret = -EINVAL; |
35b62a89 | 1045 | goto out; |
ce9d419d CW |
1046 | } |
1047 | ||
35b62a89 CW |
1048 | if (args->size == 0) |
1049 | goto out; | |
1050 | ||
ce9d419d CW |
1051 | if (!access_ok(VERIFY_READ, |
1052 | (char __user *)(uintptr_t)args->data_ptr, | |
1053 | args->size)) { | |
1054 | ret = -EFAULT; | |
35b62a89 | 1055 | goto out; |
673a394b EA |
1056 | } |
1057 | ||
b5e4feb6 CW |
1058 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1059 | args->size); | |
1060 | if (ret) { | |
1061 | ret = -EFAULT; | |
1062 | goto out; | |
673a394b EA |
1063 | } |
1064 | ||
1065 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1066 | * it would end up going through the fenced access, and we'll get | |
1067 | * different detiling behavior between reading and writing. | |
1068 | * pread/pwrite currently are reading and writing from the CPU | |
1069 | * perspective, requiring manual detiling by the client. | |
1070 | */ | |
71acb5eb | 1071 | if (obj_priv->phys_obj) |
fbd5a26d | 1072 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1073 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1074 | obj_priv->gtt_space && |
9b8c4a0b | 1075 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 1076 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1077 | if (ret) |
1078 | goto out; | |
1079 | ||
1080 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1081 | if (ret) | |
1082 | goto out_unpin; | |
1083 | ||
1084 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1085 | if (ret == -EFAULT) | |
1086 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1087 | ||
1088 | out_unpin: | |
1089 | i915_gem_object_unpin(obj); | |
40123c1f | 1090 | } else { |
fbd5a26d CW |
1091 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1092 | if (ret) | |
e5281ccd | 1093 | goto out; |
673a394b | 1094 | |
fbd5a26d CW |
1095 | ret = -EFAULT; |
1096 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1097 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1098 | if (ret == -EFAULT) | |
1099 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1100 | } |
673a394b | 1101 | |
35b62a89 | 1102 | out: |
fbd5a26d | 1103 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1104 | unlock: |
fbd5a26d | 1105 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1106 | return ret; |
1107 | } | |
1108 | ||
1109 | /** | |
2ef7eeaa EA |
1110 | * Called when user space prepares to use an object with the CPU, either |
1111 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1112 | */ |
1113 | int | |
1114 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1115 | struct drm_file *file_priv) | |
1116 | { | |
a09ba7fa | 1117 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1118 | struct drm_i915_gem_set_domain *args = data; |
1119 | struct drm_gem_object *obj; | |
652c393a | 1120 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1121 | uint32_t read_domains = args->read_domains; |
1122 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1123 | int ret; |
1124 | ||
1125 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1126 | return -ENODEV; | |
1127 | ||
2ef7eeaa | 1128 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1129 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1130 | return -EINVAL; |
1131 | ||
21d509e3 | 1132 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1133 | return -EINVAL; |
1134 | ||
1135 | /* Having something in the write domain implies it's in the read | |
1136 | * domain, and only that read domain. Enforce that in the request. | |
1137 | */ | |
1138 | if (write_domain != 0 && read_domains != write_domain) | |
1139 | return -EINVAL; | |
1140 | ||
76c1dec1 | 1141 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1142 | if (ret) |
76c1dec1 | 1143 | return ret; |
1d7cfea1 | 1144 | |
673a394b | 1145 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1146 | if (obj == NULL) { |
1147 | ret = -ENOENT; | |
1148 | goto unlock; | |
76c1dec1 | 1149 | } |
23010e43 | 1150 | obj_priv = to_intel_bo(obj); |
673a394b | 1151 | |
652c393a JB |
1152 | intel_mark_busy(dev, obj); |
1153 | ||
2ef7eeaa EA |
1154 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1155 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1156 | |
a09ba7fa EA |
1157 | /* Update the LRU on the fence for the CPU access that's |
1158 | * about to occur. | |
1159 | */ | |
1160 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1161 | struct drm_i915_fence_reg *reg = |
1162 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1163 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1164 | &dev_priv->mm.fence_list); |
1165 | } | |
1166 | ||
02354392 EA |
1167 | /* Silently promote "you're not bound, there was nothing to do" |
1168 | * to success, since the client was just asking us to | |
1169 | * make sure everything was done. | |
1170 | */ | |
1171 | if (ret == -EINVAL) | |
1172 | ret = 0; | |
2ef7eeaa | 1173 | } else { |
e47c68e9 | 1174 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1175 | } |
1176 | ||
7d1c4804 CW |
1177 | /* Maintain LRU order of "inactive" objects */ |
1178 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1179 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1180 | |
673a394b | 1181 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1182 | unlock: |
673a394b EA |
1183 | mutex_unlock(&dev->struct_mutex); |
1184 | return ret; | |
1185 | } | |
1186 | ||
1187 | /** | |
1188 | * Called when user space has done writes to this buffer | |
1189 | */ | |
1190 | int | |
1191 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1192 | struct drm_file *file_priv) | |
1193 | { | |
1194 | struct drm_i915_gem_sw_finish *args = data; | |
1195 | struct drm_gem_object *obj; | |
673a394b EA |
1196 | int ret = 0; |
1197 | ||
1198 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1199 | return -ENODEV; | |
1200 | ||
76c1dec1 | 1201 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1202 | if (ret) |
76c1dec1 | 1203 | return ret; |
1d7cfea1 | 1204 | |
673a394b EA |
1205 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1206 | if (obj == NULL) { | |
1d7cfea1 CW |
1207 | ret = -ENOENT; |
1208 | goto unlock; | |
673a394b EA |
1209 | } |
1210 | ||
673a394b | 1211 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1212 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1213 | i915_gem_object_flush_cpu_write_domain(obj); |
1214 | ||
673a394b | 1215 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1216 | unlock: |
673a394b EA |
1217 | mutex_unlock(&dev->struct_mutex); |
1218 | return ret; | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * Maps the contents of an object, returning the address it is mapped | |
1223 | * into. | |
1224 | * | |
1225 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1226 | * imply a ref on the object itself. | |
1227 | */ | |
1228 | int | |
1229 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1230 | struct drm_file *file_priv) | |
1231 | { | |
da761a6e | 1232 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1233 | struct drm_i915_gem_mmap *args = data; |
1234 | struct drm_gem_object *obj; | |
1235 | loff_t offset; | |
1236 | unsigned long addr; | |
1237 | ||
1238 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1239 | return -ENODEV; | |
1240 | ||
1241 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1242 | if (obj == NULL) | |
bf79cb91 | 1243 | return -ENOENT; |
673a394b | 1244 | |
da761a6e CW |
1245 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1246 | drm_gem_object_unreference_unlocked(obj); | |
1247 | return -E2BIG; | |
1248 | } | |
1249 | ||
673a394b EA |
1250 | offset = args->offset; |
1251 | ||
1252 | down_write(¤t->mm->mmap_sem); | |
1253 | addr = do_mmap(obj->filp, 0, args->size, | |
1254 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1255 | args->offset); | |
1256 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1257 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1258 | if (IS_ERR((void *)addr)) |
1259 | return addr; | |
1260 | ||
1261 | args->addr_ptr = (uint64_t) addr; | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
de151cf6 JB |
1266 | /** |
1267 | * i915_gem_fault - fault a page into the GTT | |
1268 | * vma: VMA in question | |
1269 | * vmf: fault info | |
1270 | * | |
1271 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1272 | * from userspace. The fault handler takes care of binding the object to | |
1273 | * the GTT (if needed), allocating and programming a fence register (again, | |
1274 | * only if needed based on whether the old reg is still valid or the object | |
1275 | * is tiled) and inserting a new PTE into the faulting process. | |
1276 | * | |
1277 | * Note that the faulting process may involve evicting existing objects | |
1278 | * from the GTT and/or fence registers to make room. So performance may | |
1279 | * suffer if the GTT working set is large or there are few fence registers | |
1280 | * left. | |
1281 | */ | |
1282 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1283 | { | |
1284 | struct drm_gem_object *obj = vma->vm_private_data; | |
1285 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1286 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1287 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1288 | pgoff_t page_offset; |
1289 | unsigned long pfn; | |
1290 | int ret = 0; | |
0f973f27 | 1291 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1292 | |
1293 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1294 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1295 | PAGE_SHIFT; | |
1296 | ||
1297 | /* Now bind it into the GTT if needed */ | |
1298 | mutex_lock(&dev->struct_mutex); | |
fb7d516a | 1299 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
a00b10c3 CW |
1300 | |
1301 | if (obj_priv->gtt_space) { | |
75e9e915 | 1302 | if (!obj_priv->map_and_fenceable) { |
a00b10c3 CW |
1303 | ret = i915_gem_object_unbind(obj); |
1304 | if (ret) | |
1305 | goto unlock; | |
1306 | } | |
1307 | } | |
16e809ac | 1308 | |
de151cf6 | 1309 | if (!obj_priv->gtt_space) { |
75e9e915 | 1310 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1311 | if (ret) |
1312 | goto unlock; | |
de151cf6 JB |
1313 | } |
1314 | ||
4a684a41 CW |
1315 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1316 | if (ret) | |
1317 | goto unlock; | |
1318 | ||
fb7d516a DV |
1319 | if (!obj_priv->fault_mappable) { |
1320 | obj_priv->fault_mappable = true; | |
a00b10c3 | 1321 | i915_gem_info_update_mappable(dev_priv, obj_priv, true); |
fb7d516a DV |
1322 | } |
1323 | ||
de151cf6 | 1324 | /* Need a new fence register? */ |
a09ba7fa | 1325 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1326 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1327 | if (ret) |
1328 | goto unlock; | |
d9ddcb96 | 1329 | } |
de151cf6 | 1330 | |
7d1c4804 | 1331 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1332 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1333 | |
de151cf6 JB |
1334 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1335 | page_offset; | |
1336 | ||
1337 | /* Finally, remap it using the new GTT offset */ | |
1338 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1339 | unlock: |
de151cf6 JB |
1340 | mutex_unlock(&dev->struct_mutex); |
1341 | ||
1342 | switch (ret) { | |
045e769a CW |
1343 | case -EAGAIN: |
1344 | set_need_resched(); | |
c715089f CW |
1345 | case 0: |
1346 | case -ERESTARTSYS: | |
1347 | return VM_FAULT_NOPAGE; | |
de151cf6 | 1348 | case -ENOMEM: |
de151cf6 | 1349 | return VM_FAULT_OOM; |
de151cf6 | 1350 | default: |
c715089f | 1351 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1352 | } |
1353 | } | |
1354 | ||
1355 | /** | |
1356 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1357 | * @obj: obj in question | |
1358 | * | |
1359 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1360 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1361 | * up the object based on the offset and sets up the various memory mapping | |
1362 | * structures. | |
1363 | * | |
1364 | * This routine allocates and attaches a fake offset for @obj. | |
1365 | */ | |
1366 | static int | |
1367 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1368 | { | |
1369 | struct drm_device *dev = obj->dev; | |
1370 | struct drm_gem_mm *mm = dev->mm_private; | |
de151cf6 | 1371 | struct drm_map_list *list; |
f77d390c | 1372 | struct drm_local_map *map; |
de151cf6 JB |
1373 | int ret = 0; |
1374 | ||
1375 | /* Set the object up for mmap'ing */ | |
1376 | list = &obj->map_list; | |
9a298b2a | 1377 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1378 | if (!list->map) |
1379 | return -ENOMEM; | |
1380 | ||
1381 | map = list->map; | |
1382 | map->type = _DRM_GEM; | |
1383 | map->size = obj->size; | |
1384 | map->handle = obj; | |
1385 | ||
1386 | /* Get a DRM GEM mmap offset allocated... */ | |
1387 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1388 | obj->size / PAGE_SIZE, 0, 0); | |
1389 | if (!list->file_offset_node) { | |
1390 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1391 | ret = -ENOSPC; |
de151cf6 JB |
1392 | goto out_free_list; |
1393 | } | |
1394 | ||
1395 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1396 | obj->size / PAGE_SIZE, 0); | |
1397 | if (!list->file_offset_node) { | |
1398 | ret = -ENOMEM; | |
1399 | goto out_free_list; | |
1400 | } | |
1401 | ||
1402 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1403 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1404 | if (ret) { | |
de151cf6 JB |
1405 | DRM_ERROR("failed to add to map hash\n"); |
1406 | goto out_free_mm; | |
1407 | } | |
1408 | ||
de151cf6 JB |
1409 | return 0; |
1410 | ||
1411 | out_free_mm: | |
1412 | drm_mm_put_block(list->file_offset_node); | |
1413 | out_free_list: | |
9a298b2a | 1414 | kfree(list->map); |
39a01d1f | 1415 | list->map = NULL; |
de151cf6 JB |
1416 | |
1417 | return ret; | |
1418 | } | |
1419 | ||
901782b2 CW |
1420 | /** |
1421 | * i915_gem_release_mmap - remove physical page mappings | |
1422 | * @obj: obj in question | |
1423 | * | |
af901ca1 | 1424 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1425 | * relinquish ownership of the pages back to the system. |
1426 | * | |
1427 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1428 | * object through the GTT and then lose the fence register due to | |
1429 | * resource pressure. Similarly if the object has been moved out of the | |
1430 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1431 | * mapping will then trigger a page fault on the next user access, allowing | |
1432 | * fixup by i915_gem_fault(). | |
1433 | */ | |
d05ca301 | 1434 | void |
901782b2 CW |
1435 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1436 | { | |
1437 | struct drm_device *dev = obj->dev; | |
fb7d516a | 1438 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1439 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 | 1440 | |
39a01d1f | 1441 | if (unlikely(obj->map_list.map && dev->dev_mapping)) |
901782b2 | 1442 | unmap_mapping_range(dev->dev_mapping, |
39a01d1f CW |
1443 | (loff_t)obj->map_list.hash.key<<PAGE_SHIFT, |
1444 | obj->size, 1); | |
fb7d516a DV |
1445 | |
1446 | if (obj_priv->fault_mappable) { | |
1447 | obj_priv->fault_mappable = false; | |
a00b10c3 | 1448 | i915_gem_info_update_mappable(dev_priv, obj_priv, false); |
fb7d516a | 1449 | } |
901782b2 CW |
1450 | } |
1451 | ||
ab00b3e5 JB |
1452 | static void |
1453 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1454 | { | |
1455 | struct drm_device *dev = obj->dev; | |
ab00b3e5 | 1456 | struct drm_gem_mm *mm = dev->mm_private; |
39a01d1f | 1457 | struct drm_map_list *list = &obj->map_list; |
ab00b3e5 | 1458 | |
ab00b3e5 | 1459 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1460 | drm_mm_put_block(list->file_offset_node); |
1461 | kfree(list->map); | |
1462 | list->map = NULL; | |
ab00b3e5 JB |
1463 | } |
1464 | ||
de151cf6 JB |
1465 | /** |
1466 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1467 | * @obj: object to check | |
1468 | * | |
1469 | * Return the required GTT alignment for an object, taking into account | |
1470 | * potential fence register mapping if needed. | |
1471 | */ | |
1472 | static uint32_t | |
a00b10c3 | 1473 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv) |
de151cf6 | 1474 | { |
a00b10c3 | 1475 | struct drm_device *dev = obj_priv->base.dev; |
de151cf6 JB |
1476 | |
1477 | /* | |
1478 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1479 | * if a fence register is needed for the object. | |
1480 | */ | |
a00b10c3 CW |
1481 | if (INTEL_INFO(dev)->gen >= 4 || |
1482 | obj_priv->tiling_mode == I915_TILING_NONE) | |
de151cf6 JB |
1483 | return 4096; |
1484 | ||
a00b10c3 CW |
1485 | /* |
1486 | * Previous chips need to be aligned to the size of the smallest | |
1487 | * fence register that can contain the object. | |
1488 | */ | |
1489 | return i915_gem_get_gtt_size(obj_priv); | |
1490 | } | |
1491 | ||
1492 | static uint32_t | |
1493 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv) | |
1494 | { | |
1495 | struct drm_device *dev = obj_priv->base.dev; | |
1496 | uint32_t size; | |
1497 | ||
1498 | /* | |
1499 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1500 | * if a fence register is needed for the object. | |
1501 | */ | |
1502 | if (INTEL_INFO(dev)->gen >= 4) | |
1503 | return obj_priv->base.size; | |
1504 | ||
de151cf6 JB |
1505 | /* |
1506 | * Previous chips need to be aligned to the size of the smallest | |
1507 | * fence register that can contain the object. | |
1508 | */ | |
a6c45cf0 | 1509 | if (INTEL_INFO(dev)->gen == 3) |
a00b10c3 | 1510 | size = 1024*1024; |
de151cf6 | 1511 | else |
a00b10c3 | 1512 | size = 512*1024; |
de151cf6 | 1513 | |
a00b10c3 CW |
1514 | while (size < obj_priv->base.size) |
1515 | size <<= 1; | |
de151cf6 | 1516 | |
a00b10c3 | 1517 | return size; |
de151cf6 JB |
1518 | } |
1519 | ||
1520 | /** | |
1521 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1522 | * @dev: DRM device | |
1523 | * @data: GTT mapping ioctl data | |
1524 | * @file_priv: GEM object info | |
1525 | * | |
1526 | * Simply returns the fake offset to userspace so it can mmap it. | |
1527 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1528 | * up so we can get faults in the handler above. | |
1529 | * | |
1530 | * The fault handler will take care of binding the object into the GTT | |
1531 | * (since it may have been evicted to make room for something), allocating | |
1532 | * a fence register, and mapping the appropriate aperture address into | |
1533 | * userspace. | |
1534 | */ | |
1535 | int | |
1536 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1537 | struct drm_file *file_priv) | |
1538 | { | |
da761a6e | 1539 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1540 | struct drm_i915_gem_mmap_gtt *args = data; |
de151cf6 JB |
1541 | struct drm_gem_object *obj; |
1542 | struct drm_i915_gem_object *obj_priv; | |
1543 | int ret; | |
1544 | ||
1545 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1546 | return -ENODEV; | |
1547 | ||
76c1dec1 | 1548 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1549 | if (ret) |
76c1dec1 | 1550 | return ret; |
de151cf6 | 1551 | |
1d7cfea1 CW |
1552 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1553 | if (obj == NULL) { | |
1554 | ret = -ENOENT; | |
1555 | goto unlock; | |
1556 | } | |
23010e43 | 1557 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1558 | |
da761a6e CW |
1559 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1560 | ret = -E2BIG; | |
1561 | goto unlock; | |
1562 | } | |
1563 | ||
ab18282d CW |
1564 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1565 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1566 | ret = -EINVAL; |
1567 | goto out; | |
ab18282d CW |
1568 | } |
1569 | ||
39a01d1f | 1570 | if (!obj->map_list.map) { |
de151cf6 | 1571 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1572 | if (ret) |
1573 | goto out; | |
de151cf6 JB |
1574 | } |
1575 | ||
39a01d1f | 1576 | args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1577 | |
1d7cfea1 | 1578 | out: |
de151cf6 | 1579 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1580 | unlock: |
de151cf6 | 1581 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1582 | return ret; |
de151cf6 JB |
1583 | } |
1584 | ||
e5281ccd CW |
1585 | static int |
1586 | i915_gem_object_get_pages_gtt(struct drm_gem_object *obj, | |
1587 | gfp_t gfpmask) | |
1588 | { | |
1589 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
1590 | int page_count, i; | |
1591 | struct address_space *mapping; | |
1592 | struct inode *inode; | |
1593 | struct page *page; | |
1594 | ||
1595 | /* Get the list of pages out of our struct file. They'll be pinned | |
1596 | * at this point until we release them. | |
1597 | */ | |
1598 | page_count = obj->size / PAGE_SIZE; | |
1599 | BUG_ON(obj_priv->pages != NULL); | |
1600 | obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1601 | if (obj_priv->pages == NULL) | |
1602 | return -ENOMEM; | |
1603 | ||
1604 | inode = obj->filp->f_path.dentry->d_inode; | |
1605 | mapping = inode->i_mapping; | |
1606 | for (i = 0; i < page_count; i++) { | |
1607 | page = read_cache_page_gfp(mapping, i, | |
1608 | GFP_HIGHUSER | | |
1609 | __GFP_COLD | | |
1610 | __GFP_RECLAIMABLE | | |
1611 | gfpmask); | |
1612 | if (IS_ERR(page)) | |
1613 | goto err_pages; | |
1614 | ||
1615 | obj_priv->pages[i] = page; | |
1616 | } | |
1617 | ||
1618 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1619 | i915_gem_object_do_bit_17_swizzle(obj); | |
1620 | ||
1621 | return 0; | |
1622 | ||
1623 | err_pages: | |
1624 | while (i--) | |
1625 | page_cache_release(obj_priv->pages[i]); | |
1626 | ||
1627 | drm_free_large(obj_priv->pages); | |
1628 | obj_priv->pages = NULL; | |
1629 | return PTR_ERR(page); | |
1630 | } | |
1631 | ||
5cdf5881 | 1632 | static void |
e5281ccd | 1633 | i915_gem_object_put_pages_gtt(struct drm_gem_object *obj) |
673a394b | 1634 | { |
23010e43 | 1635 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1636 | int page_count = obj->size / PAGE_SIZE; |
1637 | int i; | |
1638 | ||
bb6baf76 | 1639 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1640 | |
280b713b EA |
1641 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1642 | i915_gem_object_save_bit_17_swizzle(obj); | |
1643 | ||
3ef94daa | 1644 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1645 | obj_priv->dirty = 0; |
3ef94daa CW |
1646 | |
1647 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1648 | if (obj_priv->dirty) |
1649 | set_page_dirty(obj_priv->pages[i]); | |
1650 | ||
1651 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1652 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1653 | |
1654 | page_cache_release(obj_priv->pages[i]); | |
1655 | } | |
673a394b EA |
1656 | obj_priv->dirty = 0; |
1657 | ||
8e7d2b2c | 1658 | drm_free_large(obj_priv->pages); |
856fa198 | 1659 | obj_priv->pages = NULL; |
673a394b EA |
1660 | } |
1661 | ||
a56ba56c CW |
1662 | static uint32_t |
1663 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1664 | struct intel_ring_buffer *ring) | |
1665 | { | |
1666 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5d97eb69 | 1667 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
a56ba56c CW |
1668 | } |
1669 | ||
673a394b | 1670 | static void |
617dbe27 | 1671 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1672 | struct intel_ring_buffer *ring) |
673a394b EA |
1673 | { |
1674 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1675 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1676 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1677 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1678 | |
852835f3 ZN |
1679 | BUG_ON(ring == NULL); |
1680 | obj_priv->ring = ring; | |
673a394b EA |
1681 | |
1682 | /* Add a reference if we're newly entering the active list. */ | |
1683 | if (!obj_priv->active) { | |
1684 | drm_gem_object_reference(obj); | |
1685 | obj_priv->active = 1; | |
1686 | } | |
e35a41de | 1687 | |
673a394b | 1688 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1689 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1690 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1691 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1692 | } |
1693 | ||
ce44b0ea EA |
1694 | static void |
1695 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1696 | { | |
1697 | struct drm_device *dev = obj->dev; | |
1698 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1699 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1700 | |
1701 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1702 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1703 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1704 | obj_priv->last_rendering_seqno = 0; |
1705 | } | |
673a394b | 1706 | |
963b4836 CW |
1707 | /* Immediately discard the backing storage */ |
1708 | static void | |
1709 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1710 | { | |
23010e43 | 1711 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1712 | struct inode *inode; |
963b4836 | 1713 | |
ae9fed6b CW |
1714 | /* Our goal here is to return as much of the memory as |
1715 | * is possible back to the system as we are called from OOM. | |
1716 | * To do this we must instruct the shmfs to drop all of its | |
1717 | * backing pages, *now*. Here we mirror the actions taken | |
1718 | * when by shmem_delete_inode() to release the backing store. | |
1719 | */ | |
bb6baf76 | 1720 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1721 | truncate_inode_pages(inode->i_mapping, 0); |
1722 | if (inode->i_op->truncate_range) | |
1723 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1724 | |
1725 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1726 | } |
1727 | ||
1728 | static inline int | |
1729 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1730 | { | |
1731 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1732 | } | |
1733 | ||
673a394b EA |
1734 | static void |
1735 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1736 | { | |
1737 | struct drm_device *dev = obj->dev; | |
1738 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1739 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1740 | |
673a394b | 1741 | if (obj_priv->pin_count != 0) |
69dc4987 | 1742 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1743 | else |
69dc4987 CW |
1744 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1745 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1746 | |
99fcb766 DV |
1747 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1748 | ||
ce44b0ea | 1749 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1750 | obj_priv->ring = NULL; |
673a394b EA |
1751 | if (obj_priv->active) { |
1752 | obj_priv->active = 0; | |
1753 | drm_gem_object_unreference(obj); | |
1754 | } | |
23bc5982 | 1755 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1756 | } |
1757 | ||
63560396 DV |
1758 | static void |
1759 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1760 | uint32_t flush_domains, |
852835f3 | 1761 | struct intel_ring_buffer *ring) |
63560396 DV |
1762 | { |
1763 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1764 | struct drm_i915_gem_object *obj_priv, *next; | |
1765 | ||
1766 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1767 | &ring->gpu_write_list, |
63560396 | 1768 | gpu_write_list) { |
a8089e84 | 1769 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1770 | |
64193406 | 1771 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1772 | uint32_t old_write_domain = obj->write_domain; |
1773 | ||
1774 | obj->write_domain = 0; | |
1775 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1776 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1777 | |
1778 | /* update the fence lru list */ | |
007cc8ac DV |
1779 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1780 | struct drm_i915_fence_reg *reg = | |
1781 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1782 | list_move_tail(®->lru_list, | |
63560396 | 1783 | &dev_priv->mm.fence_list); |
007cc8ac | 1784 | } |
63560396 DV |
1785 | |
1786 | trace_i915_gem_object_change_domain(obj, | |
1787 | obj->read_domains, | |
1788 | old_write_domain); | |
1789 | } | |
1790 | } | |
1791 | } | |
8187a2b7 | 1792 | |
3cce469c | 1793 | int |
8a1a49f9 | 1794 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1795 | struct drm_file *file, |
8dc5d147 | 1796 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1797 | struct intel_ring_buffer *ring) |
673a394b EA |
1798 | { |
1799 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1800 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1801 | uint32_t seqno; |
1802 | int was_empty; | |
3cce469c CW |
1803 | int ret; |
1804 | ||
1805 | BUG_ON(request == NULL); | |
673a394b | 1806 | |
f787a5f5 CW |
1807 | if (file != NULL) |
1808 | file_priv = file->driver_priv; | |
b962442e | 1809 | |
3cce469c CW |
1810 | ret = ring->add_request(ring, &seqno); |
1811 | if (ret) | |
1812 | return ret; | |
673a394b | 1813 | |
a56ba56c | 1814 | ring->outstanding_lazy_request = false; |
673a394b EA |
1815 | |
1816 | request->seqno = seqno; | |
852835f3 | 1817 | request->ring = ring; |
673a394b | 1818 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1819 | was_empty = list_empty(&ring->request_list); |
1820 | list_add_tail(&request->list, &ring->request_list); | |
1821 | ||
f787a5f5 | 1822 | if (file_priv) { |
1c25595f | 1823 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1824 | request->file_priv = file_priv; |
b962442e | 1825 | list_add_tail(&request->client_list, |
f787a5f5 | 1826 | &file_priv->mm.request_list); |
1c25595f | 1827 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1828 | } |
673a394b | 1829 | |
f65d9421 | 1830 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1831 | mod_timer(&dev_priv->hangcheck_timer, |
1832 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1833 | if (was_empty) |
b3b079db CW |
1834 | queue_delayed_work(dev_priv->wq, |
1835 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1836 | } |
3cce469c | 1837 | return 0; |
673a394b EA |
1838 | } |
1839 | ||
1840 | /** | |
1841 | * Command execution barrier | |
1842 | * | |
1843 | * Ensures that all commands in the ring are finished | |
1844 | * before signalling the CPU | |
1845 | */ | |
8a1a49f9 | 1846 | static void |
852835f3 | 1847 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1848 | { |
673a394b | 1849 | uint32_t flush_domains = 0; |
673a394b EA |
1850 | |
1851 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1852 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1853 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1854 | |
78501eac | 1855 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1856 | } |
1857 | ||
f787a5f5 CW |
1858 | static inline void |
1859 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1860 | { |
1c25595f | 1861 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1862 | |
1c25595f CW |
1863 | if (!file_priv) |
1864 | return; | |
1c5d22f7 | 1865 | |
1c25595f CW |
1866 | spin_lock(&file_priv->mm.lock); |
1867 | list_del(&request->client_list); | |
1868 | request->file_priv = NULL; | |
1869 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1870 | } |
673a394b | 1871 | |
dfaae392 CW |
1872 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1873 | struct intel_ring_buffer *ring) | |
9375e446 | 1874 | { |
dfaae392 CW |
1875 | while (!list_empty(&ring->request_list)) { |
1876 | struct drm_i915_gem_request *request; | |
673a394b | 1877 | |
dfaae392 CW |
1878 | request = list_first_entry(&ring->request_list, |
1879 | struct drm_i915_gem_request, | |
1880 | list); | |
de151cf6 | 1881 | |
dfaae392 | 1882 | list_del(&request->list); |
f787a5f5 | 1883 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1884 | kfree(request); |
1885 | } | |
673a394b | 1886 | |
dfaae392 | 1887 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1888 | struct drm_i915_gem_object *obj_priv; |
1889 | ||
dfaae392 | 1890 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1891 | struct drm_i915_gem_object, |
69dc4987 | 1892 | ring_list); |
9375e446 CW |
1893 | |
1894 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1895 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1896 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1897 | } |
1898 | } | |
1899 | ||
069efc1d | 1900 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1901 | { |
77f01230 CW |
1902 | struct drm_i915_private *dev_priv = dev->dev_private; |
1903 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1904 | int i; |
673a394b | 1905 | |
dfaae392 | 1906 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1907 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1908 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1909 | |
1910 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1911 | * to be lost on reset along with the data, so simply move the | |
1912 | * lost bo to the inactive list. | |
1913 | */ | |
1914 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1915 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1916 | struct drm_i915_gem_object, | |
69dc4987 | 1917 | mm_list); |
dfaae392 CW |
1918 | |
1919 | obj_priv->base.write_domain = 0; | |
1920 | list_del_init(&obj_priv->gpu_write_list); | |
1921 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1922 | } | |
1923 | ||
1924 | /* Move everything out of the GPU domains to ensure we do any | |
1925 | * necessary invalidation upon reuse. | |
1926 | */ | |
77f01230 CW |
1927 | list_for_each_entry(obj_priv, |
1928 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1929 | mm_list) |
77f01230 CW |
1930 | { |
1931 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1932 | } | |
069efc1d CW |
1933 | |
1934 | /* The fence registers are invalidated so clear them out */ | |
1935 | for (i = 0; i < 16; i++) { | |
1936 | struct drm_i915_fence_reg *reg; | |
1937 | ||
1938 | reg = &dev_priv->fence_regs[i]; | |
1939 | if (!reg->obj) | |
1940 | continue; | |
1941 | ||
1942 | i915_gem_clear_fence_reg(reg->obj); | |
1943 | } | |
673a394b EA |
1944 | } |
1945 | ||
1946 | /** | |
1947 | * This function clears the request list as sequence numbers are passed. | |
1948 | */ | |
b09a1fec CW |
1949 | static void |
1950 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1951 | struct intel_ring_buffer *ring) | |
673a394b EA |
1952 | { |
1953 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1954 | uint32_t seqno; | |
1955 | ||
b84d5f0c CW |
1956 | if (!ring->status_page.page_addr || |
1957 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1958 | return; |
1959 | ||
23bc5982 | 1960 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1961 | |
78501eac | 1962 | seqno = ring->get_seqno(ring); |
852835f3 | 1963 | while (!list_empty(&ring->request_list)) { |
673a394b | 1964 | struct drm_i915_gem_request *request; |
673a394b | 1965 | |
852835f3 | 1966 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1967 | struct drm_i915_gem_request, |
1968 | list); | |
673a394b | 1969 | |
dfaae392 | 1970 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1971 | break; |
1972 | ||
1973 | trace_i915_gem_request_retire(dev, request->seqno); | |
1974 | ||
1975 | list_del(&request->list); | |
f787a5f5 | 1976 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1977 | kfree(request); |
1978 | } | |
673a394b | 1979 | |
b84d5f0c CW |
1980 | /* Move any buffers on the active list that are no longer referenced |
1981 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1982 | */ | |
1983 | while (!list_empty(&ring->active_list)) { | |
1984 | struct drm_gem_object *obj; | |
1985 | struct drm_i915_gem_object *obj_priv; | |
1986 | ||
1987 | obj_priv = list_first_entry(&ring->active_list, | |
1988 | struct drm_i915_gem_object, | |
69dc4987 | 1989 | ring_list); |
673a394b | 1990 | |
dfaae392 | 1991 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1992 | break; |
b84d5f0c CW |
1993 | |
1994 | obj = &obj_priv->base; | |
b84d5f0c CW |
1995 | if (obj->write_domain != 0) |
1996 | i915_gem_object_move_to_flushing(obj); | |
1997 | else | |
1998 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1999 | } |
9d34e5db CW |
2000 | |
2001 | if (unlikely (dev_priv->trace_irq_seqno && | |
2002 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 2003 | ring->user_irq_put(ring); |
9d34e5db CW |
2004 | dev_priv->trace_irq_seqno = 0; |
2005 | } | |
23bc5982 CW |
2006 | |
2007 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2008 | } |
2009 | ||
b09a1fec CW |
2010 | void |
2011 | i915_gem_retire_requests(struct drm_device *dev) | |
2012 | { | |
2013 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2014 | ||
be72615b CW |
2015 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
2016 | struct drm_i915_gem_object *obj_priv, *tmp; | |
2017 | ||
2018 | /* We must be careful that during unbind() we do not | |
2019 | * accidentally infinitely recurse into retire requests. | |
2020 | * Currently: | |
2021 | * retire -> free -> unbind -> wait -> retire_ring | |
2022 | */ | |
2023 | list_for_each_entry_safe(obj_priv, tmp, | |
2024 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 2025 | mm_list) |
be72615b CW |
2026 | i915_gem_free_object_tail(&obj_priv->base); |
2027 | } | |
2028 | ||
b09a1fec | 2029 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2030 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2031 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2032 | } |
2033 | ||
75ef9da2 | 2034 | static void |
673a394b EA |
2035 | i915_gem_retire_work_handler(struct work_struct *work) |
2036 | { | |
2037 | drm_i915_private_t *dev_priv; | |
2038 | struct drm_device *dev; | |
2039 | ||
2040 | dev_priv = container_of(work, drm_i915_private_t, | |
2041 | mm.retire_work.work); | |
2042 | dev = dev_priv->dev; | |
2043 | ||
891b48cf CW |
2044 | /* Come back later if the device is busy... */ |
2045 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2046 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2047 | return; | |
2048 | } | |
2049 | ||
b09a1fec | 2050 | i915_gem_retire_requests(dev); |
d1b851fc | 2051 | |
6dbe2772 | 2052 | if (!dev_priv->mm.suspended && |
d1b851fc | 2053 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2054 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2055 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2056 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2057 | mutex_unlock(&dev->struct_mutex); |
2058 | } | |
2059 | ||
5a5a0c64 | 2060 | int |
852835f3 | 2061 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2062 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2063 | { |
2064 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2065 | u32 ier; |
673a394b EA |
2066 | int ret = 0; |
2067 | ||
2068 | BUG_ON(seqno == 0); | |
2069 | ||
ba1234d1 | 2070 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2071 | return -EAGAIN; |
2072 | ||
5d97eb69 | 2073 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
2074 | struct drm_i915_gem_request *request; |
2075 | ||
2076 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2077 | if (request == NULL) | |
e35a41de | 2078 | return -ENOMEM; |
3cce469c CW |
2079 | |
2080 | ret = i915_add_request(dev, NULL, request, ring); | |
2081 | if (ret) { | |
2082 | kfree(request); | |
2083 | return ret; | |
2084 | } | |
2085 | ||
2086 | seqno = request->seqno; | |
e35a41de | 2087 | } |
ffed1d09 | 2088 | |
78501eac | 2089 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2090 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2091 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2092 | else | |
2093 | ier = I915_READ(IER); | |
802c7eb6 JB |
2094 | if (!ier) { |
2095 | DRM_ERROR("something (likely vbetool) disabled " | |
2096 | "interrupts, re-enabling\n"); | |
2097 | i915_driver_irq_preinstall(dev); | |
2098 | i915_driver_irq_postinstall(dev); | |
2099 | } | |
2100 | ||
1c5d22f7 CW |
2101 | trace_i915_gem_request_wait_begin(dev, seqno); |
2102 | ||
b2223497 | 2103 | ring->waiting_seqno = seqno; |
78501eac | 2104 | ring->user_irq_get(ring); |
48764bf4 | 2105 | if (interruptible) |
852835f3 | 2106 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2107 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2108 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2109 | else |
852835f3 | 2110 | wait_event(ring->irq_queue, |
78501eac | 2111 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2112 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2113 | |
78501eac | 2114 | ring->user_irq_put(ring); |
b2223497 | 2115 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2116 | |
2117 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2118 | } |
ba1234d1 | 2119 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2120 | ret = -EAGAIN; |
673a394b EA |
2121 | |
2122 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2123 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2124 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2125 | dev_priv->next_seqno); |
673a394b EA |
2126 | |
2127 | /* Directly dispatch request retiring. While we have the work queue | |
2128 | * to handle this, the waiter on a request often wants an associated | |
2129 | * buffer to have made it to the inactive list, and we would need | |
2130 | * a separate wait queue to handle that. | |
2131 | */ | |
2132 | if (ret == 0) | |
b09a1fec | 2133 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2134 | |
2135 | return ret; | |
2136 | } | |
2137 | ||
48764bf4 DV |
2138 | /** |
2139 | * Waits for a sequence number to be signaled, and cleans up the | |
2140 | * request and object lists appropriately for that event. | |
2141 | */ | |
2142 | static int | |
852835f3 | 2143 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2144 | struct intel_ring_buffer *ring) |
48764bf4 | 2145 | { |
852835f3 | 2146 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2147 | } |
2148 | ||
20f0cd55 | 2149 | static void |
9220434a | 2150 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2151 | struct drm_file *file_priv, |
9220434a CW |
2152 | struct intel_ring_buffer *ring, |
2153 | uint32_t invalidate_domains, | |
2154 | uint32_t flush_domains) | |
2155 | { | |
78501eac | 2156 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2157 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2158 | } | |
2159 | ||
8187a2b7 ZN |
2160 | static void |
2161 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2162 | struct drm_file *file_priv, |
8187a2b7 | 2163 | uint32_t invalidate_domains, |
9220434a CW |
2164 | uint32_t flush_domains, |
2165 | uint32_t flush_rings) | |
8187a2b7 ZN |
2166 | { |
2167 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2168 | |
8187a2b7 ZN |
2169 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2170 | drm_agp_chipset_flush(dev); | |
8bff917c | 2171 | |
9220434a CW |
2172 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2173 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2174 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2175 | &dev_priv->render_ring, |
2176 | invalidate_domains, flush_domains); | |
2177 | if (flush_rings & RING_BSD) | |
c78ec30b | 2178 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2179 | &dev_priv->bsd_ring, |
2180 | invalidate_domains, flush_domains); | |
549f7365 CW |
2181 | if (flush_rings & RING_BLT) |
2182 | i915_gem_flush_ring(dev, file_priv, | |
2183 | &dev_priv->blt_ring, | |
2184 | invalidate_domains, flush_domains); | |
9220434a | 2185 | } |
8187a2b7 ZN |
2186 | } |
2187 | ||
673a394b EA |
2188 | /** |
2189 | * Ensures that all rendering to the object has completed and the object is | |
2190 | * safe to unbind from the GTT or access from the CPU. | |
2191 | */ | |
2192 | static int | |
2cf34d7b CW |
2193 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2194 | bool interruptible) | |
673a394b EA |
2195 | { |
2196 | struct drm_device *dev = obj->dev; | |
23010e43 | 2197 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2198 | int ret; |
2199 | ||
e47c68e9 EA |
2200 | /* This function only exists to support waiting for existing rendering, |
2201 | * not for emitting required flushes. | |
673a394b | 2202 | */ |
e47c68e9 | 2203 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2204 | |
2205 | /* If there is rendering queued on the buffer being evicted, wait for | |
2206 | * it. | |
2207 | */ | |
2208 | if (obj_priv->active) { | |
2cf34d7b CW |
2209 | ret = i915_do_wait_request(dev, |
2210 | obj_priv->last_rendering_seqno, | |
2211 | interruptible, | |
2212 | obj_priv->ring); | |
2213 | if (ret) | |
673a394b EA |
2214 | return ret; |
2215 | } | |
2216 | ||
2217 | return 0; | |
2218 | } | |
2219 | ||
2220 | /** | |
2221 | * Unbinds an object from the GTT aperture. | |
2222 | */ | |
0f973f27 | 2223 | int |
673a394b EA |
2224 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2225 | { | |
2226 | struct drm_device *dev = obj->dev; | |
73aa808f | 2227 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2228 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2229 | int ret = 0; |
2230 | ||
673a394b EA |
2231 | if (obj_priv->gtt_space == NULL) |
2232 | return 0; | |
2233 | ||
2234 | if (obj_priv->pin_count != 0) { | |
2235 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2236 | return -EINVAL; | |
2237 | } | |
2238 | ||
5323fd04 EA |
2239 | /* blow away mappings if mapped through GTT */ |
2240 | i915_gem_release_mmap(obj); | |
2241 | ||
673a394b EA |
2242 | /* Move the object to the CPU domain to ensure that |
2243 | * any possible CPU writes while it's not in the GTT | |
2244 | * are flushed when we go to remap it. This will | |
2245 | * also ensure that all pending GPU writes are finished | |
2246 | * before we unbind. | |
2247 | */ | |
e47c68e9 | 2248 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2249 | if (ret == -ERESTARTSYS) |
673a394b | 2250 | return ret; |
8dc1775d CW |
2251 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2252 | * should be safe and we need to cleanup or else we might | |
2253 | * cause memory corruption through use-after-free. | |
2254 | */ | |
812ed492 CW |
2255 | if (ret) { |
2256 | i915_gem_clflush_object(obj); | |
2257 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2258 | } | |
673a394b | 2259 | |
96b47b65 DV |
2260 | /* release the fence reg _after_ flushing */ |
2261 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2262 | i915_gem_clear_fence_reg(obj); | |
2263 | ||
73aa808f CW |
2264 | drm_unbind_agp(obj_priv->agp_mem); |
2265 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2266 | |
e5281ccd | 2267 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2268 | |
a00b10c3 | 2269 | i915_gem_info_remove_gtt(dev_priv, obj_priv); |
69dc4987 | 2270 | list_del_init(&obj_priv->mm_list); |
75e9e915 DV |
2271 | /* Avoid an unnecessary call to unbind on rebind. */ |
2272 | obj_priv->map_and_fenceable = true; | |
673a394b | 2273 | |
73aa808f CW |
2274 | drm_mm_put_block(obj_priv->gtt_space); |
2275 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2276 | obj_priv->gtt_offset = 0; |
673a394b | 2277 | |
963b4836 CW |
2278 | if (i915_gem_object_is_purgeable(obj_priv)) |
2279 | i915_gem_object_truncate(obj); | |
2280 | ||
1c5d22f7 CW |
2281 | trace_i915_gem_object_unbind(obj); |
2282 | ||
8dc1775d | 2283 | return ret; |
673a394b EA |
2284 | } |
2285 | ||
a56ba56c CW |
2286 | static int i915_ring_idle(struct drm_device *dev, |
2287 | struct intel_ring_buffer *ring) | |
2288 | { | |
395b70be | 2289 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2290 | return 0; |
2291 | ||
a56ba56c CW |
2292 | i915_gem_flush_ring(dev, NULL, ring, |
2293 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2294 | return i915_wait_request(dev, | |
2295 | i915_gem_next_request_seqno(dev, ring), | |
2296 | ring); | |
2297 | } | |
2298 | ||
b47eb4a2 | 2299 | int |
4df2faf4 DV |
2300 | i915_gpu_idle(struct drm_device *dev) |
2301 | { | |
2302 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2303 | bool lists_empty; | |
852835f3 | 2304 | int ret; |
4df2faf4 | 2305 | |
d1b851fc | 2306 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2307 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2308 | if (lists_empty) |
2309 | return 0; | |
2310 | ||
2311 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2312 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2313 | if (ret) |
2314 | return ret; | |
d1b851fc | 2315 | |
87acb0a5 CW |
2316 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2317 | if (ret) | |
2318 | return ret; | |
d1b851fc | 2319 | |
549f7365 CW |
2320 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2321 | if (ret) | |
2322 | return ret; | |
4df2faf4 | 2323 | |
8a1a49f9 | 2324 | return 0; |
4df2faf4 DV |
2325 | } |
2326 | ||
a00b10c3 | 2327 | static void sandybridge_write_fence_reg(struct drm_gem_object *obj) |
4e901fdc | 2328 | { |
4e901fdc EA |
2329 | struct drm_device *dev = obj->dev; |
2330 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2331 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2332 | u32 size = i915_gem_get_gtt_size(obj_priv); |
4e901fdc EA |
2333 | int regnum = obj_priv->fence_reg; |
2334 | uint64_t val; | |
2335 | ||
a00b10c3 | 2336 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
4e901fdc EA |
2337 | 0xfffff000) << 32; |
2338 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2339 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2340 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2341 | ||
2342 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2343 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2344 | val |= I965_FENCE_REG_VALID; | |
2345 | ||
2346 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2347 | } | |
2348 | ||
a00b10c3 | 2349 | static void i965_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2350 | { |
de151cf6 JB |
2351 | struct drm_device *dev = obj->dev; |
2352 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2353 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2354 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2355 | int regnum = obj_priv->fence_reg; |
2356 | uint64_t val; | |
2357 | ||
a00b10c3 | 2358 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
de151cf6 JB |
2359 | 0xfffff000) << 32; |
2360 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2361 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2362 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2363 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2364 | val |= I965_FENCE_REG_VALID; | |
2365 | ||
2366 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2367 | } | |
2368 | ||
a00b10c3 | 2369 | static void i915_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2370 | { |
de151cf6 JB |
2371 | struct drm_device *dev = obj->dev; |
2372 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2373 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 CW |
2374 | u32 size = i915_gem_get_gtt_size(obj_priv); |
2375 | uint32_t fence_reg, val, pitch_val; | |
0f973f27 | 2376 | int tile_width; |
de151cf6 JB |
2377 | |
2378 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
a00b10c3 CW |
2379 | (obj_priv->gtt_offset & (size - 1))) { |
2380 | WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n", | |
75e9e915 | 2381 | __func__, obj_priv->gtt_offset, obj_priv->map_and_fenceable, size, |
a00b10c3 | 2382 | obj_priv->gtt_space->start, obj_priv->gtt_space->size); |
de151cf6 JB |
2383 | return; |
2384 | } | |
2385 | ||
0f973f27 JB |
2386 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2387 | HAS_128_BYTE_Y_TILING(dev)) | |
2388 | tile_width = 128; | |
de151cf6 | 2389 | else |
0f973f27 JB |
2390 | tile_width = 512; |
2391 | ||
2392 | /* Note: pitch better be a power of two tile widths */ | |
2393 | pitch_val = obj_priv->stride / tile_width; | |
2394 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2395 | |
c36a2a6d DV |
2396 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2397 | HAS_128_BYTE_Y_TILING(dev)) | |
2398 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2399 | else | |
2400 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2401 | ||
de151cf6 JB |
2402 | val = obj_priv->gtt_offset; |
2403 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2404 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2405 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2406 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2407 | val |= I830_FENCE_REG_VALID; | |
2408 | ||
a00b10c3 CW |
2409 | fence_reg = obj_priv->fence_reg; |
2410 | if (fence_reg < 8) | |
2411 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2412 | else |
a00b10c3 | 2413 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
dc529a4f | 2414 | I915_WRITE(fence_reg, val); |
de151cf6 JB |
2415 | } |
2416 | ||
a00b10c3 | 2417 | static void i830_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2418 | { |
de151cf6 JB |
2419 | struct drm_device *dev = obj->dev; |
2420 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2421 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2422 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2423 | int regnum = obj_priv->fence_reg; |
2424 | uint32_t val; | |
2425 | uint32_t pitch_val; | |
8d7773a3 | 2426 | uint32_t fence_size_bits; |
de151cf6 | 2427 | |
8d7773a3 | 2428 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2429 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2430 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2431 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2432 | return; |
2433 | } | |
2434 | ||
e76a16de EA |
2435 | pitch_val = obj_priv->stride / 128; |
2436 | pitch_val = ffs(pitch_val) - 1; | |
2437 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2438 | ||
de151cf6 JB |
2439 | val = obj_priv->gtt_offset; |
2440 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2441 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2442 | fence_size_bits = I830_FENCE_SIZE_BITS(size); |
8d7773a3 DV |
2443 | WARN_ON(fence_size_bits & ~0x00000f00); |
2444 | val |= fence_size_bits; | |
de151cf6 JB |
2445 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2446 | val |= I830_FENCE_REG_VALID; | |
2447 | ||
2448 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2449 | } |
2450 | ||
2cf34d7b CW |
2451 | static int i915_find_fence_reg(struct drm_device *dev, |
2452 | bool interruptible) | |
ae3db24a | 2453 | { |
ae3db24a | 2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
a00b10c3 CW |
2455 | struct drm_i915_fence_reg *reg; |
2456 | struct drm_i915_gem_object *obj_priv = NULL; | |
ae3db24a DV |
2457 | int i, avail, ret; |
2458 | ||
2459 | /* First try to find a free reg */ | |
2460 | avail = 0; | |
2461 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2462 | reg = &dev_priv->fence_regs[i]; | |
2463 | if (!reg->obj) | |
2464 | return i; | |
2465 | ||
23010e43 | 2466 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2467 | if (!obj_priv->pin_count) |
2468 | avail++; | |
2469 | } | |
2470 | ||
2471 | if (avail == 0) | |
2472 | return -ENOSPC; | |
2473 | ||
2474 | /* None available, try to steal one or wait for a user to finish */ | |
a00b10c3 | 2475 | avail = I915_FENCE_REG_NONE; |
007cc8ac DV |
2476 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2477 | lru_list) { | |
a00b10c3 | 2478 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2479 | if (obj_priv->pin_count) |
2480 | continue; | |
2481 | ||
2482 | /* found one! */ | |
a00b10c3 | 2483 | avail = obj_priv->fence_reg; |
ae3db24a DV |
2484 | break; |
2485 | } | |
2486 | ||
a00b10c3 | 2487 | BUG_ON(avail == I915_FENCE_REG_NONE); |
ae3db24a DV |
2488 | |
2489 | /* We only have a reference on obj from the active list. put_fence_reg | |
2490 | * might drop that one, causing a use-after-free in it. So hold a | |
2491 | * private reference to obj like the other callers of put_fence_reg | |
2492 | * (set_tiling ioctl) do. */ | |
a00b10c3 CW |
2493 | drm_gem_object_reference(&obj_priv->base); |
2494 | ret = i915_gem_object_put_fence_reg(&obj_priv->base, interruptible); | |
2495 | drm_gem_object_unreference(&obj_priv->base); | |
ae3db24a DV |
2496 | if (ret != 0) |
2497 | return ret; | |
2498 | ||
a00b10c3 | 2499 | return avail; |
ae3db24a DV |
2500 | } |
2501 | ||
de151cf6 JB |
2502 | /** |
2503 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2504 | * @obj: object to map through a fence reg | |
2505 | * | |
2506 | * When mapping objects through the GTT, userspace wants to be able to write | |
2507 | * to them without having to worry about swizzling if the object is tiled. | |
2508 | * | |
2509 | * This function walks the fence regs looking for a free one for @obj, | |
2510 | * stealing one if it can't find any. | |
2511 | * | |
2512 | * It then sets up the reg based on the object's properties: address, pitch | |
2513 | * and tiling format. | |
2514 | */ | |
8c4b8c3f | 2515 | int |
2cf34d7b CW |
2516 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2517 | bool interruptible) | |
de151cf6 JB |
2518 | { |
2519 | struct drm_device *dev = obj->dev; | |
79e53945 | 2520 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2521 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2522 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2523 | int ret; |
de151cf6 | 2524 | |
a09ba7fa EA |
2525 | /* Just update our place in the LRU if our fence is getting used. */ |
2526 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2527 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2528 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2529 | return 0; |
2530 | } | |
2531 | ||
de151cf6 JB |
2532 | switch (obj_priv->tiling_mode) { |
2533 | case I915_TILING_NONE: | |
2534 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2535 | break; | |
2536 | case I915_TILING_X: | |
0f973f27 JB |
2537 | if (!obj_priv->stride) |
2538 | return -EINVAL; | |
2539 | WARN((obj_priv->stride & (512 - 1)), | |
2540 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2541 | obj_priv->gtt_offset); | |
de151cf6 JB |
2542 | break; |
2543 | case I915_TILING_Y: | |
0f973f27 JB |
2544 | if (!obj_priv->stride) |
2545 | return -EINVAL; | |
2546 | WARN((obj_priv->stride & (128 - 1)), | |
2547 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2548 | obj_priv->gtt_offset); | |
de151cf6 JB |
2549 | break; |
2550 | } | |
2551 | ||
2cf34d7b | 2552 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2553 | if (ret < 0) |
2554 | return ret; | |
de151cf6 | 2555 | |
ae3db24a DV |
2556 | obj_priv->fence_reg = ret; |
2557 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2558 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2559 | |
de151cf6 JB |
2560 | reg->obj = obj; |
2561 | ||
e259befd CW |
2562 | switch (INTEL_INFO(dev)->gen) { |
2563 | case 6: | |
a00b10c3 | 2564 | sandybridge_write_fence_reg(obj); |
e259befd CW |
2565 | break; |
2566 | case 5: | |
2567 | case 4: | |
a00b10c3 | 2568 | i965_write_fence_reg(obj); |
e259befd CW |
2569 | break; |
2570 | case 3: | |
a00b10c3 | 2571 | i915_write_fence_reg(obj); |
e259befd CW |
2572 | break; |
2573 | case 2: | |
a00b10c3 | 2574 | i830_write_fence_reg(obj); |
e259befd CW |
2575 | break; |
2576 | } | |
d9ddcb96 | 2577 | |
a00b10c3 CW |
2578 | trace_i915_gem_object_get_fence(obj, |
2579 | obj_priv->fence_reg, | |
2580 | obj_priv->tiling_mode); | |
1c5d22f7 | 2581 | |
d9ddcb96 | 2582 | return 0; |
de151cf6 JB |
2583 | } |
2584 | ||
2585 | /** | |
2586 | * i915_gem_clear_fence_reg - clear out fence register info | |
2587 | * @obj: object to clear | |
2588 | * | |
2589 | * Zeroes out the fence register itself and clears out the associated | |
2590 | * data structures in dev_priv and obj_priv. | |
2591 | */ | |
2592 | static void | |
2593 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2594 | { | |
2595 | struct drm_device *dev = obj->dev; | |
79e53945 | 2596 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2597 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2598 | struct drm_i915_fence_reg *reg = |
2599 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2600 | uint32_t fence_reg; |
de151cf6 | 2601 | |
e259befd CW |
2602 | switch (INTEL_INFO(dev)->gen) { |
2603 | case 6: | |
4e901fdc EA |
2604 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2605 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2606 | break; |
2607 | case 5: | |
2608 | case 4: | |
de151cf6 | 2609 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2610 | break; |
2611 | case 3: | |
9b74f734 | 2612 | if (obj_priv->fence_reg >= 8) |
e259befd | 2613 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2614 | else |
e259befd CW |
2615 | case 2: |
2616 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2617 | |
2618 | I915_WRITE(fence_reg, 0); | |
e259befd | 2619 | break; |
dc529a4f | 2620 | } |
de151cf6 | 2621 | |
007cc8ac | 2622 | reg->obj = NULL; |
de151cf6 | 2623 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2624 | list_del_init(®->lru_list); |
de151cf6 JB |
2625 | } |
2626 | ||
52dc7d32 CW |
2627 | /** |
2628 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2629 | * to the buffer to finish, and then resets the fence register. | |
2630 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2631 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2632 | * |
2633 | * Zeroes out the fence register itself and clears out the associated | |
2634 | * data structures in dev_priv and obj_priv. | |
2635 | */ | |
2636 | int | |
2cf34d7b CW |
2637 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2638 | bool interruptible) | |
52dc7d32 CW |
2639 | { |
2640 | struct drm_device *dev = obj->dev; | |
53640e1d | 2641 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2642 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2643 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2644 | |
2645 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2646 | return 0; | |
2647 | ||
10ae9bd2 DV |
2648 | /* If we've changed tiling, GTT-mappings of the object |
2649 | * need to re-fault to ensure that the correct fence register | |
2650 | * setup is in place. | |
2651 | */ | |
2652 | i915_gem_release_mmap(obj); | |
2653 | ||
52dc7d32 CW |
2654 | /* On the i915, GPU access to tiled buffers is via a fence, |
2655 | * therefore we must wait for any outstanding access to complete | |
2656 | * before clearing the fence. | |
2657 | */ | |
53640e1d CW |
2658 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2659 | if (reg->gpu) { | |
52dc7d32 CW |
2660 | int ret; |
2661 | ||
2cf34d7b | 2662 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2663 | if (ret) |
2dafb1e0 CW |
2664 | return ret; |
2665 | ||
2cf34d7b | 2666 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2667 | if (ret) |
52dc7d32 | 2668 | return ret; |
53640e1d CW |
2669 | |
2670 | reg->gpu = false; | |
52dc7d32 CW |
2671 | } |
2672 | ||
4a726612 | 2673 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2674 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2675 | |
2676 | return 0; | |
2677 | } | |
2678 | ||
673a394b EA |
2679 | /** |
2680 | * Finds free space in the GTT aperture and binds the object there. | |
2681 | */ | |
2682 | static int | |
920afa77 DV |
2683 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2684 | unsigned alignment, | |
75e9e915 | 2685 | bool map_and_fenceable) |
673a394b EA |
2686 | { |
2687 | struct drm_device *dev = obj->dev; | |
2688 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2689 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2690 | struct drm_mm_node *free_space; |
a00b10c3 CW |
2691 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
2692 | u32 size, fence_size, fence_alignment; | |
75e9e915 | 2693 | bool mappable, fenceable; |
07f73f69 | 2694 | int ret; |
673a394b | 2695 | |
bb6baf76 | 2696 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2697 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2698 | return -EINVAL; | |
2699 | } | |
2700 | ||
a00b10c3 CW |
2701 | fence_size = i915_gem_get_gtt_size(obj_priv); |
2702 | fence_alignment = i915_gem_get_gtt_alignment(obj_priv); | |
2703 | ||
673a394b | 2704 | if (alignment == 0) |
75e9e915 DV |
2705 | alignment = map_and_fenceable ? fence_alignment : 4096; |
2706 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { | |
673a394b EA |
2707 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2708 | return -EINVAL; | |
2709 | } | |
2710 | ||
75e9e915 | 2711 | size = map_and_fenceable ? fence_size : obj->size; |
a00b10c3 | 2712 | |
654fc607 CW |
2713 | /* If the object is bigger than the entire aperture, reject it early |
2714 | * before evicting everything in a vain attempt to find space. | |
2715 | */ | |
920afa77 | 2716 | if (obj->size > |
75e9e915 | 2717 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2718 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2719 | return -E2BIG; | |
2720 | } | |
2721 | ||
673a394b | 2722 | search_free: |
75e9e915 | 2723 | if (map_and_fenceable) |
920afa77 DV |
2724 | free_space = |
2725 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2726 | size, alignment, 0, |
920afa77 DV |
2727 | dev_priv->mm.gtt_mappable_end, |
2728 | 0); | |
2729 | else | |
2730 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2731 | size, alignment, 0); |
920afa77 DV |
2732 | |
2733 | if (free_space != NULL) { | |
75e9e915 | 2734 | if (map_and_fenceable) |
920afa77 DV |
2735 | obj_priv->gtt_space = |
2736 | drm_mm_get_block_range_generic(free_space, | |
a00b10c3 | 2737 | size, alignment, 0, |
920afa77 DV |
2738 | dev_priv->mm.gtt_mappable_end, |
2739 | 0); | |
2740 | else | |
2741 | obj_priv->gtt_space = | |
a00b10c3 | 2742 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2743 | } |
673a394b EA |
2744 | if (obj_priv->gtt_space == NULL) { |
2745 | /* If the gtt is empty and we're still having trouble | |
2746 | * fitting our object in, we're out of memory. | |
2747 | */ | |
75e9e915 DV |
2748 | ret = i915_gem_evict_something(dev, size, alignment, |
2749 | map_and_fenceable); | |
9731129c | 2750 | if (ret) |
673a394b | 2751 | return ret; |
9731129c | 2752 | |
673a394b EA |
2753 | goto search_free; |
2754 | } | |
2755 | ||
e5281ccd | 2756 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b EA |
2757 | if (ret) { |
2758 | drm_mm_put_block(obj_priv->gtt_space); | |
2759 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2760 | |
2761 | if (ret == -ENOMEM) { | |
2762 | /* first try to clear up some space from the GTT */ | |
a00b10c3 | 2763 | ret = i915_gem_evict_something(dev, size, |
75e9e915 DV |
2764 | alignment, |
2765 | map_and_fenceable); | |
07f73f69 | 2766 | if (ret) { |
07f73f69 | 2767 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2768 | if (gfpmask) { |
2769 | gfpmask = 0; | |
2770 | goto search_free; | |
07f73f69 CW |
2771 | } |
2772 | ||
2773 | return ret; | |
2774 | } | |
2775 | ||
2776 | goto search_free; | |
2777 | } | |
2778 | ||
673a394b EA |
2779 | return ret; |
2780 | } | |
2781 | ||
673a394b EA |
2782 | /* Create an AGP memory structure pointing at our pages, and bind it |
2783 | * into the GTT. | |
2784 | */ | |
2785 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2786 | obj_priv->pages, |
07f73f69 | 2787 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2788 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2789 | obj_priv->agp_type); |
673a394b | 2790 | if (obj_priv->agp_mem == NULL) { |
e5281ccd | 2791 | i915_gem_object_put_pages_gtt(obj); |
673a394b EA |
2792 | drm_mm_put_block(obj_priv->gtt_space); |
2793 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2794 | |
a00b10c3 | 2795 | ret = i915_gem_evict_something(dev, size, |
75e9e915 | 2796 | alignment, map_and_fenceable); |
9731129c | 2797 | if (ret) |
07f73f69 | 2798 | return ret; |
07f73f69 CW |
2799 | |
2800 | goto search_free; | |
673a394b | 2801 | } |
673a394b | 2802 | |
fb7d516a DV |
2803 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
2804 | ||
bf1a1092 | 2805 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2806 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
a00b10c3 | 2807 | i915_gem_info_add_gtt(dev_priv, obj_priv); |
bf1a1092 | 2808 | |
673a394b EA |
2809 | /* Assert that the object is not currently in any GPU domain. As it |
2810 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2811 | * a GPU cache | |
2812 | */ | |
21d509e3 CW |
2813 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2814 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2815 | |
75e9e915 | 2816 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, map_and_fenceable); |
1c5d22f7 | 2817 | |
75e9e915 | 2818 | fenceable = |
a00b10c3 CW |
2819 | obj_priv->gtt_space->size == fence_size && |
2820 | (obj_priv->gtt_space->start & (fence_alignment -1)) == 0; | |
2821 | ||
75e9e915 | 2822 | mappable = |
a00b10c3 CW |
2823 | obj_priv->gtt_offset + obj->size <= dev_priv->mm.gtt_mappable_end; |
2824 | ||
75e9e915 DV |
2825 | obj_priv->map_and_fenceable = mappable && fenceable; |
2826 | ||
673a394b EA |
2827 | return 0; |
2828 | } | |
2829 | ||
2830 | void | |
2831 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2832 | { | |
23010e43 | 2833 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2834 | |
2835 | /* If we don't have a page list set up, then we're not pinned | |
2836 | * to GPU, and we can ignore the cache flush because it'll happen | |
2837 | * again at bind time. | |
2838 | */ | |
856fa198 | 2839 | if (obj_priv->pages == NULL) |
673a394b EA |
2840 | return; |
2841 | ||
1c5d22f7 | 2842 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2843 | |
856fa198 | 2844 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2845 | } |
2846 | ||
e47c68e9 | 2847 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2848 | static int |
ba3d8d74 DV |
2849 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2850 | bool pipelined) | |
e47c68e9 EA |
2851 | { |
2852 | struct drm_device *dev = obj->dev; | |
e47c68e9 EA |
2853 | |
2854 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2855 | return 0; |
e47c68e9 EA |
2856 | |
2857 | /* Queue the GPU write cache flushing we need. */ | |
c78ec30b | 2858 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2859 | to_intel_bo(obj)->ring, |
2860 | 0, obj->write_domain); | |
48b956c5 | 2861 | BUG_ON(obj->write_domain); |
1c5d22f7 | 2862 | |
ba3d8d74 DV |
2863 | if (pipelined) |
2864 | return 0; | |
2865 | ||
2cf34d7b | 2866 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2867 | } |
2868 | ||
2869 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2870 | static void | |
2871 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2872 | { | |
1c5d22f7 CW |
2873 | uint32_t old_write_domain; |
2874 | ||
e47c68e9 EA |
2875 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2876 | return; | |
2877 | ||
2878 | /* No actual flushing is required for the GTT write domain. Writes | |
2879 | * to it immediately go to main memory as far as we know, so there's | |
2880 | * no chipset flush. It also doesn't land in render cache. | |
2881 | */ | |
4a684a41 CW |
2882 | i915_gem_release_mmap(obj); |
2883 | ||
1c5d22f7 | 2884 | old_write_domain = obj->write_domain; |
e47c68e9 | 2885 | obj->write_domain = 0; |
1c5d22f7 CW |
2886 | |
2887 | trace_i915_gem_object_change_domain(obj, | |
2888 | obj->read_domains, | |
2889 | old_write_domain); | |
e47c68e9 EA |
2890 | } |
2891 | ||
2892 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2893 | static void | |
2894 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2895 | { | |
2896 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2897 | uint32_t old_write_domain; |
e47c68e9 EA |
2898 | |
2899 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2900 | return; | |
2901 | ||
2902 | i915_gem_clflush_object(obj); | |
2903 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2904 | old_write_domain = obj->write_domain; |
e47c68e9 | 2905 | obj->write_domain = 0; |
1c5d22f7 CW |
2906 | |
2907 | trace_i915_gem_object_change_domain(obj, | |
2908 | obj->read_domains, | |
2909 | old_write_domain); | |
e47c68e9 EA |
2910 | } |
2911 | ||
2ef7eeaa EA |
2912 | /** |
2913 | * Moves a single object to the GTT read, and possibly write domain. | |
2914 | * | |
2915 | * This function returns when the move is complete, including waiting on | |
2916 | * flushes to occur. | |
2917 | */ | |
79e53945 | 2918 | int |
2ef7eeaa EA |
2919 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2920 | { | |
23010e43 | 2921 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2922 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2923 | int ret; |
2ef7eeaa | 2924 | |
02354392 EA |
2925 | /* Not valid to be called on unbound objects. */ |
2926 | if (obj_priv->gtt_space == NULL) | |
2927 | return -EINVAL; | |
2928 | ||
ba3d8d74 | 2929 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2930 | if (ret != 0) |
2931 | return ret; | |
2932 | ||
7213342d | 2933 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2934 | |
ba3d8d74 | 2935 | if (write) { |
2cf34d7b | 2936 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2937 | if (ret) |
2938 | return ret; | |
ba3d8d74 | 2939 | } |
e47c68e9 | 2940 | |
1c5d22f7 CW |
2941 | old_write_domain = obj->write_domain; |
2942 | old_read_domains = obj->read_domains; | |
2943 | ||
e47c68e9 EA |
2944 | /* It should now be out of any other write domains, and we can update |
2945 | * the domain values for our changes. | |
2946 | */ | |
2947 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2948 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2949 | if (write) { | |
7213342d | 2950 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2951 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2952 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2953 | } |
2954 | ||
1c5d22f7 CW |
2955 | trace_i915_gem_object_change_domain(obj, |
2956 | old_read_domains, | |
2957 | old_write_domain); | |
2958 | ||
e47c68e9 EA |
2959 | return 0; |
2960 | } | |
2961 | ||
b9241ea3 ZW |
2962 | /* |
2963 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2964 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2965 | */ | |
2966 | int | |
48b956c5 CW |
2967 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2968 | bool pipelined) | |
b9241ea3 | 2969 | { |
23010e43 | 2970 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2971 | uint32_t old_read_domains; |
b9241ea3 ZW |
2972 | int ret; |
2973 | ||
2974 | /* Not valid to be called on unbound objects. */ | |
2975 | if (obj_priv->gtt_space == NULL) | |
2976 | return -EINVAL; | |
2977 | ||
ced270fa | 2978 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
2979 | if (ret) |
2980 | return ret; | |
b9241ea3 | 2981 | |
ced270fa CW |
2982 | /* Currently, we are always called from an non-interruptible context. */ |
2983 | if (!pipelined) { | |
2984 | ret = i915_gem_object_wait_rendering(obj, false); | |
2985 | if (ret) | |
b9241ea3 ZW |
2986 | return ret; |
2987 | } | |
2988 | ||
b118c1e3 CW |
2989 | i915_gem_object_flush_cpu_write_domain(obj); |
2990 | ||
b9241ea3 | 2991 | old_read_domains = obj->read_domains; |
c78ec30b | 2992 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2993 | |
2994 | trace_i915_gem_object_change_domain(obj, | |
2995 | old_read_domains, | |
ba3d8d74 | 2996 | obj->write_domain); |
b9241ea3 ZW |
2997 | |
2998 | return 0; | |
2999 | } | |
3000 | ||
e47c68e9 EA |
3001 | /** |
3002 | * Moves a single object to the CPU read, and possibly write domain. | |
3003 | * | |
3004 | * This function returns when the move is complete, including waiting on | |
3005 | * flushes to occur. | |
3006 | */ | |
3007 | static int | |
3008 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
3009 | { | |
1c5d22f7 | 3010 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3011 | int ret; |
3012 | ||
ba3d8d74 | 3013 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3014 | if (ret != 0) |
3015 | return ret; | |
2ef7eeaa | 3016 | |
e47c68e9 | 3017 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3018 | |
e47c68e9 EA |
3019 | /* If we have a partially-valid cache of the object in the CPU, |
3020 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3021 | */ |
e47c68e9 | 3022 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3023 | |
7213342d | 3024 | if (write) { |
2cf34d7b | 3025 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3026 | if (ret) |
3027 | return ret; | |
3028 | } | |
3029 | ||
1c5d22f7 CW |
3030 | old_write_domain = obj->write_domain; |
3031 | old_read_domains = obj->read_domains; | |
3032 | ||
e47c68e9 EA |
3033 | /* Flush the CPU cache if it's still invalid. */ |
3034 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 3035 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3036 | |
e47c68e9 | 3037 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3038 | } |
3039 | ||
3040 | /* It should now be out of any other write domains, and we can update | |
3041 | * the domain values for our changes. | |
3042 | */ | |
e47c68e9 EA |
3043 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3044 | ||
3045 | /* If we're writing through the CPU, then the GPU read domains will | |
3046 | * need to be invalidated at next use. | |
3047 | */ | |
3048 | if (write) { | |
c78ec30b | 3049 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3050 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3051 | } | |
2ef7eeaa | 3052 | |
1c5d22f7 CW |
3053 | trace_i915_gem_object_change_domain(obj, |
3054 | old_read_domains, | |
3055 | old_write_domain); | |
3056 | ||
2ef7eeaa EA |
3057 | return 0; |
3058 | } | |
3059 | ||
673a394b EA |
3060 | /* |
3061 | * Set the next domain for the specified object. This | |
3062 | * may not actually perform the necessary flushing/invaliding though, | |
3063 | * as that may want to be batched with other set_domain operations | |
3064 | * | |
3065 | * This is (we hope) the only really tricky part of gem. The goal | |
3066 | * is fairly simple -- track which caches hold bits of the object | |
3067 | * and make sure they remain coherent. A few concrete examples may | |
3068 | * help to explain how it works. For shorthand, we use the notation | |
3069 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3070 | * a pair of read and write domain masks. | |
3071 | * | |
3072 | * Case 1: the batch buffer | |
3073 | * | |
3074 | * 1. Allocated | |
3075 | * 2. Written by CPU | |
3076 | * 3. Mapped to GTT | |
3077 | * 4. Read by GPU | |
3078 | * 5. Unmapped from GTT | |
3079 | * 6. Freed | |
3080 | * | |
3081 | * Let's take these a step at a time | |
3082 | * | |
3083 | * 1. Allocated | |
3084 | * Pages allocated from the kernel may still have | |
3085 | * cache contents, so we set them to (CPU, CPU) always. | |
3086 | * 2. Written by CPU (using pwrite) | |
3087 | * The pwrite function calls set_domain (CPU, CPU) and | |
3088 | * this function does nothing (as nothing changes) | |
3089 | * 3. Mapped by GTT | |
3090 | * This function asserts that the object is not | |
3091 | * currently in any GPU-based read or write domains | |
3092 | * 4. Read by GPU | |
3093 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3094 | * As write_domain is zero, this function adds in the | |
3095 | * current read domains (CPU+COMMAND, 0). | |
3096 | * flush_domains is set to CPU. | |
3097 | * invalidate_domains is set to COMMAND | |
3098 | * clflush is run to get data out of the CPU caches | |
3099 | * then i915_dev_set_domain calls i915_gem_flush to | |
3100 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3101 | * 5. Unmapped from GTT | |
3102 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3103 | * flush_domains and invalidate_domains end up both zero | |
3104 | * so no flushing/invalidating happens | |
3105 | * 6. Freed | |
3106 | * yay, done | |
3107 | * | |
3108 | * Case 2: The shared render buffer | |
3109 | * | |
3110 | * 1. Allocated | |
3111 | * 2. Mapped to GTT | |
3112 | * 3. Read/written by GPU | |
3113 | * 4. set_domain to (CPU,CPU) | |
3114 | * 5. Read/written by CPU | |
3115 | * 6. Read/written by GPU | |
3116 | * | |
3117 | * 1. Allocated | |
3118 | * Same as last example, (CPU, CPU) | |
3119 | * 2. Mapped to GTT | |
3120 | * Nothing changes (assertions find that it is not in the GPU) | |
3121 | * 3. Read/written by GPU | |
3122 | * execbuffer calls set_domain (RENDER, RENDER) | |
3123 | * flush_domains gets CPU | |
3124 | * invalidate_domains gets GPU | |
3125 | * clflush (obj) | |
3126 | * MI_FLUSH and drm_agp_chipset_flush | |
3127 | * 4. set_domain (CPU, CPU) | |
3128 | * flush_domains gets GPU | |
3129 | * invalidate_domains gets CPU | |
3130 | * wait_rendering (obj) to make sure all drawing is complete. | |
3131 | * This will include an MI_FLUSH to get the data from GPU | |
3132 | * to memory | |
3133 | * clflush (obj) to invalidate the CPU cache | |
3134 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3135 | * 5. Read/written by CPU | |
3136 | * cache lines are loaded and dirtied | |
3137 | * 6. Read written by GPU | |
3138 | * Same as last GPU access | |
3139 | * | |
3140 | * Case 3: The constant buffer | |
3141 | * | |
3142 | * 1. Allocated | |
3143 | * 2. Written by CPU | |
3144 | * 3. Read by GPU | |
3145 | * 4. Updated (written) by CPU again | |
3146 | * 5. Read by GPU | |
3147 | * | |
3148 | * 1. Allocated | |
3149 | * (CPU, CPU) | |
3150 | * 2. Written by CPU | |
3151 | * (CPU, CPU) | |
3152 | * 3. Read by GPU | |
3153 | * (CPU+RENDER, 0) | |
3154 | * flush_domains = CPU | |
3155 | * invalidate_domains = RENDER | |
3156 | * clflush (obj) | |
3157 | * MI_FLUSH | |
3158 | * drm_agp_chipset_flush | |
3159 | * 4. Updated (written) by CPU again | |
3160 | * (CPU, CPU) | |
3161 | * flush_domains = 0 (no previous write domain) | |
3162 | * invalidate_domains = 0 (no new read domains) | |
3163 | * 5. Read by GPU | |
3164 | * (CPU+RENDER, 0) | |
3165 | * flush_domains = CPU | |
3166 | * invalidate_domains = RENDER | |
3167 | * clflush (obj) | |
3168 | * MI_FLUSH | |
3169 | * drm_agp_chipset_flush | |
3170 | */ | |
c0d90829 | 3171 | static void |
b6651458 | 3172 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
0f8c6d7c CW |
3173 | struct intel_ring_buffer *ring, |
3174 | struct change_domains *cd) | |
673a394b | 3175 | { |
23010e43 | 3176 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3177 | uint32_t invalidate_domains = 0; |
3178 | uint32_t flush_domains = 0; | |
652c393a | 3179 | |
673a394b EA |
3180 | /* |
3181 | * If the object isn't moving to a new write domain, | |
3182 | * let the object stay in multiple read domains | |
3183 | */ | |
8b0e378a EA |
3184 | if (obj->pending_write_domain == 0) |
3185 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3186 | |
3187 | /* | |
3188 | * Flush the current write domain if | |
3189 | * the new read domains don't match. Invalidate | |
3190 | * any read domains which differ from the old | |
3191 | * write domain | |
3192 | */ | |
8b0e378a | 3193 | if (obj->write_domain && |
13b29289 CW |
3194 | (obj->write_domain != obj->pending_read_domains || |
3195 | obj_priv->ring != ring)) { | |
673a394b | 3196 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3197 | invalidate_domains |= |
3198 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3199 | } |
3200 | /* | |
3201 | * Invalidate any read caches which may have | |
3202 | * stale data. That is, any new read domains. | |
3203 | */ | |
8b0e378a | 3204 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3205 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3206 | i915_gem_clflush_object(obj); |
673a394b | 3207 | |
4a684a41 CW |
3208 | /* blow away mappings if mapped through GTT */ |
3209 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) | |
3210 | i915_gem_release_mmap(obj); | |
3211 | ||
efbeed96 EA |
3212 | /* The actual obj->write_domain will be updated with |
3213 | * pending_write_domain after we emit the accumulated flush for all | |
3214 | * of our domain changes in execbuffers (which clears objects' | |
3215 | * write_domains). So if we have a current write domain that we | |
3216 | * aren't changing, set pending_write_domain to that. | |
3217 | */ | |
3218 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3219 | obj->pending_write_domain = obj->write_domain; | |
673a394b | 3220 | |
0f8c6d7c CW |
3221 | cd->invalidate_domains |= invalidate_domains; |
3222 | cd->flush_domains |= flush_domains; | |
b6651458 | 3223 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3224 | cd->flush_rings |= obj_priv->ring->id; |
b6651458 | 3225 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3226 | cd->flush_rings |= ring->id; |
673a394b EA |
3227 | } |
3228 | ||
3229 | /** | |
e47c68e9 | 3230 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3231 | * |
e47c68e9 EA |
3232 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3233 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3234 | */ |
e47c68e9 EA |
3235 | static void |
3236 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3237 | { |
23010e43 | 3238 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3239 | |
e47c68e9 EA |
3240 | if (!obj_priv->page_cpu_valid) |
3241 | return; | |
3242 | ||
3243 | /* If we're partially in the CPU read domain, finish moving it in. | |
3244 | */ | |
3245 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3246 | int i; | |
3247 | ||
3248 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3249 | if (obj_priv->page_cpu_valid[i]) | |
3250 | continue; | |
856fa198 | 3251 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3252 | } |
e47c68e9 EA |
3253 | } |
3254 | ||
3255 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3256 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3257 | */ | |
9a298b2a | 3258 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3259 | obj_priv->page_cpu_valid = NULL; |
3260 | } | |
3261 | ||
3262 | /** | |
3263 | * Set the CPU read domain on a range of the object. | |
3264 | * | |
3265 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3266 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3267 | * pages have been flushed, and will be respected by | |
3268 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3269 | * of the whole object. | |
3270 | * | |
3271 | * This function returns when the move is complete, including waiting on | |
3272 | * flushes to occur. | |
3273 | */ | |
3274 | static int | |
3275 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3276 | uint64_t offset, uint64_t size) | |
3277 | { | |
23010e43 | 3278 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3279 | uint32_t old_read_domains; |
e47c68e9 | 3280 | int i, ret; |
673a394b | 3281 | |
e47c68e9 EA |
3282 | if (offset == 0 && size == obj->size) |
3283 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3284 | |
ba3d8d74 | 3285 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3286 | if (ret != 0) |
6a47baa6 | 3287 | return ret; |
e47c68e9 EA |
3288 | i915_gem_object_flush_gtt_write_domain(obj); |
3289 | ||
3290 | /* If we're already fully in the CPU read domain, we're done. */ | |
3291 | if (obj_priv->page_cpu_valid == NULL && | |
3292 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3293 | return 0; | |
673a394b | 3294 | |
e47c68e9 EA |
3295 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3296 | * newly adding I915_GEM_DOMAIN_CPU | |
3297 | */ | |
673a394b | 3298 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3299 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3300 | GFP_KERNEL); | |
e47c68e9 EA |
3301 | if (obj_priv->page_cpu_valid == NULL) |
3302 | return -ENOMEM; | |
3303 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3304 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3305 | |
3306 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3307 | * perspective. | |
3308 | */ | |
e47c68e9 EA |
3309 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3310 | i++) { | |
673a394b EA |
3311 | if (obj_priv->page_cpu_valid[i]) |
3312 | continue; | |
3313 | ||
856fa198 | 3314 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3315 | |
3316 | obj_priv->page_cpu_valid[i] = 1; | |
3317 | } | |
3318 | ||
e47c68e9 EA |
3319 | /* It should now be out of any other write domains, and we can update |
3320 | * the domain values for our changes. | |
3321 | */ | |
3322 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3323 | ||
1c5d22f7 | 3324 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3325 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3326 | ||
1c5d22f7 CW |
3327 | trace_i915_gem_object_change_domain(obj, |
3328 | old_read_domains, | |
3329 | obj->write_domain); | |
3330 | ||
673a394b EA |
3331 | return 0; |
3332 | } | |
3333 | ||
673a394b EA |
3334 | /** |
3335 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3336 | */ | |
3337 | static int | |
9af90d19 CW |
3338 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3339 | struct drm_file *file_priv, | |
3340 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3341 | { |
9af90d19 | 3342 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3343 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3344 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3345 | struct drm_gem_object *target_obj = NULL; |
3346 | uint32_t target_handle = 0; | |
3347 | int i, ret = 0; | |
673a394b | 3348 | |
2549d6c2 | 3349 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3350 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3351 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3352 | uint32_t target_offset; |
673a394b | 3353 | |
9af90d19 CW |
3354 | if (__copy_from_user_inatomic(&reloc, |
3355 | user_relocs+i, | |
3356 | sizeof(reloc))) { | |
3357 | ret = -EFAULT; | |
3358 | break; | |
76446cac | 3359 | } |
76446cac | 3360 | |
9af90d19 CW |
3361 | if (reloc.target_handle != target_handle) { |
3362 | drm_gem_object_unreference(target_obj); | |
673a394b | 3363 | |
9af90d19 CW |
3364 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3365 | reloc.target_handle); | |
3366 | if (target_obj == NULL) { | |
3367 | ret = -ENOENT; | |
3368 | break; | |
3369 | } | |
3370 | ||
3371 | target_handle = reloc.target_handle; | |
673a394b | 3372 | } |
9af90d19 | 3373 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3374 | |
8542a0bb CW |
3375 | #if WATCH_RELOC |
3376 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3377 | "read %08x write %08x gtt %08x " | |
3378 | "presumed %08x delta %08x\n", | |
3379 | __func__, | |
3380 | obj, | |
2549d6c2 CW |
3381 | (int) reloc.offset, |
3382 | (int) reloc.target_handle, | |
3383 | (int) reloc.read_domains, | |
3384 | (int) reloc.write_domain, | |
9af90d19 | 3385 | (int) target_offset, |
2549d6c2 CW |
3386 | (int) reloc.presumed_offset, |
3387 | reloc.delta); | |
8542a0bb CW |
3388 | #endif |
3389 | ||
673a394b EA |
3390 | /* The target buffer should have appeared before us in the |
3391 | * exec_object list, so it should have a GTT space bound by now. | |
3392 | */ | |
9af90d19 | 3393 | if (target_offset == 0) { |
673a394b | 3394 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3395 | reloc.target_handle); |
9af90d19 CW |
3396 | ret = -EINVAL; |
3397 | break; | |
673a394b EA |
3398 | } |
3399 | ||
8542a0bb | 3400 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3401 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3402 | DRM_ERROR("reloc with multiple write domains: " |
3403 | "obj %p target %d offset %d " | |
3404 | "read %08x write %08x", | |
2549d6c2 CW |
3405 | obj, reloc.target_handle, |
3406 | (int) reloc.offset, | |
3407 | reloc.read_domains, | |
3408 | reloc.write_domain); | |
9af90d19 CW |
3409 | ret = -EINVAL; |
3410 | break; | |
16edd550 | 3411 | } |
2549d6c2 CW |
3412 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3413 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3414 | DRM_ERROR("reloc with read/write CPU domains: " |
3415 | "obj %p target %d offset %d " | |
3416 | "read %08x write %08x", | |
2549d6c2 CW |
3417 | obj, reloc.target_handle, |
3418 | (int) reloc.offset, | |
3419 | reloc.read_domains, | |
3420 | reloc.write_domain); | |
9af90d19 CW |
3421 | ret = -EINVAL; |
3422 | break; | |
e47c68e9 | 3423 | } |
2549d6c2 CW |
3424 | if (reloc.write_domain && target_obj->pending_write_domain && |
3425 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3426 | DRM_ERROR("Write domain conflict: " |
3427 | "obj %p target %d offset %d " | |
3428 | "new %08x old %08x\n", | |
2549d6c2 CW |
3429 | obj, reloc.target_handle, |
3430 | (int) reloc.offset, | |
3431 | reloc.write_domain, | |
673a394b | 3432 | target_obj->pending_write_domain); |
9af90d19 CW |
3433 | ret = -EINVAL; |
3434 | break; | |
673a394b EA |
3435 | } |
3436 | ||
2549d6c2 | 3437 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3438 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3439 | |
3440 | /* If the relocation already has the right value in it, no | |
3441 | * more work needs to be done. | |
3442 | */ | |
9af90d19 | 3443 | if (target_offset == reloc.presumed_offset) |
673a394b | 3444 | continue; |
673a394b | 3445 | |
8542a0bb | 3446 | /* Check that the relocation address is valid... */ |
9af90d19 | 3447 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3448 | DRM_ERROR("Relocation beyond object bounds: " |
3449 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3450 | obj, reloc.target_handle, |
9af90d19 CW |
3451 | (int) reloc.offset, (int) obj->base.size); |
3452 | ret = -EINVAL; | |
3453 | break; | |
8542a0bb | 3454 | } |
2549d6c2 | 3455 | if (reloc.offset & 3) { |
8542a0bb CW |
3456 | DRM_ERROR("Relocation not 4-byte aligned: " |
3457 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3458 | obj, reloc.target_handle, |
3459 | (int) reloc.offset); | |
9af90d19 CW |
3460 | ret = -EINVAL; |
3461 | break; | |
8542a0bb CW |
3462 | } |
3463 | ||
3464 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3465 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3466 | DRM_ERROR("Relocation beyond target object bounds: " |
3467 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3468 | obj, reloc.target_handle, |
3469 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3470 | ret = -EINVAL; |
3471 | break; | |
673a394b EA |
3472 | } |
3473 | ||
9af90d19 CW |
3474 | reloc.delta += target_offset; |
3475 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3476 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3477 | char *vaddr; | |
673a394b | 3478 | |
c48c43e4 | 3479 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3480 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3481 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3482 | } else { |
3483 | uint32_t __iomem *reloc_entry; | |
3484 | void __iomem *reloc_page; | |
b962442e | 3485 | |
9af90d19 CW |
3486 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3487 | if (ret) | |
3488 | break; | |
b962442e | 3489 | |
f0c43d9b | 3490 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3491 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3492 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3493 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3494 | reloc_entry = (uint32_t __iomem *) |
3495 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3496 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3497 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3498 | } |
b962442e | 3499 | |
b5dc608c CW |
3500 | /* and update the user's relocation entry */ |
3501 | reloc.presumed_offset = target_offset; | |
3502 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3503 | &reloc.presumed_offset, | |
3504 | sizeof(reloc.presumed_offset))) { | |
3505 | ret = -EFAULT; | |
3506 | break; | |
3507 | } | |
b962442e | 3508 | } |
b962442e | 3509 | |
9af90d19 | 3510 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3511 | return ret; |
3512 | } | |
3513 | ||
40a5f0de | 3514 | static int |
9af90d19 CW |
3515 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3516 | struct drm_file *file, | |
3517 | struct drm_gem_object **object_list, | |
3518 | struct drm_i915_gem_exec_object2 *exec_list, | |
3519 | int count) | |
40a5f0de | 3520 | { |
9af90d19 CW |
3521 | struct drm_i915_private *dev_priv = dev->dev_private; |
3522 | int ret, i, retry; | |
40a5f0de | 3523 | |
9af90d19 | 3524 | /* attempt to pin all of the buffers into the GTT */ |
5eac3ab4 CW |
3525 | retry = 0; |
3526 | do { | |
9af90d19 CW |
3527 | ret = 0; |
3528 | for (i = 0; i < count; i++) { | |
3529 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3530 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3531 | bool need_fence = |
3532 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3533 | obj->tiling_mode != I915_TILING_NONE; | |
3534 | ||
16e809ac DV |
3535 | /* g33/pnv can't fence buffers in the unmappable part */ |
3536 | bool need_mappable = | |
3537 | entry->relocation_count ? true : need_fence; | |
3538 | ||
9af90d19 | 3539 | /* Check fence reg constraints and rebind if necessary */ |
75e9e915 | 3540 | if (need_mappable && !obj->map_and_fenceable) { |
9af90d19 CW |
3541 | ret = i915_gem_object_unbind(&obj->base); |
3542 | if (ret) | |
3543 | break; | |
3544 | } | |
40a5f0de | 3545 | |
920afa77 | 3546 | ret = i915_gem_object_pin(&obj->base, |
16e809ac | 3547 | entry->alignment, |
75e9e915 | 3548 | need_mappable); |
9af90d19 CW |
3549 | if (ret) |
3550 | break; | |
40a5f0de | 3551 | |
9af90d19 CW |
3552 | /* |
3553 | * Pre-965 chips need a fence register set up in order | |
3554 | * to properly handle blits to/from tiled surfaces. | |
3555 | */ | |
3556 | if (need_fence) { | |
3557 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3558 | if (ret) { | |
3559 | i915_gem_object_unpin(&obj->base); | |
3560 | break; | |
3561 | } | |
40a5f0de | 3562 | |
9af90d19 CW |
3563 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3564 | } | |
40a5f0de | 3565 | |
9af90d19 | 3566 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3567 | } |
3568 | ||
9af90d19 CW |
3569 | while (i--) |
3570 | i915_gem_object_unpin(object_list[i]); | |
3571 | ||
5eac3ab4 | 3572 | if (ret != -ENOSPC || retry > 1) |
9af90d19 CW |
3573 | return ret; |
3574 | ||
5eac3ab4 CW |
3575 | /* First attempt, just clear anything that is purgeable. |
3576 | * Second attempt, clear the entire GTT. | |
3577 | */ | |
3578 | ret = i915_gem_evict_everything(dev, retry == 0); | |
9af90d19 CW |
3579 | if (ret) |
3580 | return ret; | |
40a5f0de | 3581 | |
5eac3ab4 CW |
3582 | retry++; |
3583 | } while (1); | |
40a5f0de EA |
3584 | } |
3585 | ||
13b29289 CW |
3586 | static int |
3587 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, | |
3588 | struct drm_file *file, | |
3589 | struct intel_ring_buffer *ring, | |
3590 | struct drm_gem_object **objects, | |
3591 | int count) | |
3592 | { | |
0f8c6d7c | 3593 | struct change_domains cd; |
13b29289 CW |
3594 | int ret, i; |
3595 | ||
0f8c6d7c CW |
3596 | cd.invalidate_domains = 0; |
3597 | cd.flush_domains = 0; | |
3598 | cd.flush_rings = 0; | |
13b29289 | 3599 | for (i = 0; i < count; i++) |
0f8c6d7c | 3600 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
13b29289 | 3601 | |
0f8c6d7c | 3602 | if (cd.invalidate_domains | cd.flush_domains) { |
13b29289 CW |
3603 | #if WATCH_EXEC |
3604 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3605 | __func__, | |
0f8c6d7c CW |
3606 | cd.invalidate_domains, |
3607 | cd.flush_domains); | |
13b29289 CW |
3608 | #endif |
3609 | i915_gem_flush(dev, file, | |
0f8c6d7c CW |
3610 | cd.invalidate_domains, |
3611 | cd.flush_domains, | |
3612 | cd.flush_rings); | |
13b29289 CW |
3613 | } |
3614 | ||
3615 | for (i = 0; i < count; i++) { | |
3616 | struct drm_i915_gem_object *obj = to_intel_bo(objects[i]); | |
3617 | /* XXX replace with semaphores */ | |
3618 | if (obj->ring && ring != obj->ring) { | |
3619 | ret = i915_gem_object_wait_rendering(&obj->base, true); | |
3620 | if (ret) | |
3621 | return ret; | |
3622 | } | |
3623 | } | |
3624 | ||
3625 | return 0; | |
3626 | } | |
3627 | ||
673a394b EA |
3628 | /* Throttle our rendering by waiting until the ring has completed our requests |
3629 | * emitted over 20 msec ago. | |
3630 | * | |
b962442e EA |
3631 | * Note that if we were to use the current jiffies each time around the loop, |
3632 | * we wouldn't escape the function with any frames outstanding if the time to | |
3633 | * render a frame was over 20ms. | |
3634 | * | |
673a394b EA |
3635 | * This should get us reasonable parallelism between CPU and GPU but also |
3636 | * relatively low latency when blocking on a particular request to finish. | |
3637 | */ | |
40a5f0de | 3638 | static int |
f787a5f5 | 3639 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3640 | { |
f787a5f5 CW |
3641 | struct drm_i915_private *dev_priv = dev->dev_private; |
3642 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3643 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3644 | struct drm_i915_gem_request *request; |
3645 | struct intel_ring_buffer *ring = NULL; | |
3646 | u32 seqno = 0; | |
3647 | int ret; | |
93533c29 | 3648 | |
1c25595f | 3649 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3650 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3651 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3652 | break; | |
40a5f0de | 3653 | |
f787a5f5 CW |
3654 | ring = request->ring; |
3655 | seqno = request->seqno; | |
b962442e | 3656 | } |
1c25595f | 3657 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3658 | |
f787a5f5 CW |
3659 | if (seqno == 0) |
3660 | return 0; | |
2bc43b5c | 3661 | |
f787a5f5 | 3662 | ret = 0; |
78501eac | 3663 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3664 | /* And wait for the seqno passing without holding any locks and |
3665 | * causing extra latency for others. This is safe as the irq | |
3666 | * generation is designed to be run atomically and so is | |
3667 | * lockless. | |
3668 | */ | |
78501eac | 3669 | ring->user_irq_get(ring); |
f787a5f5 | 3670 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3671 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3672 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3673 | ring->user_irq_put(ring); |
40a5f0de | 3674 | |
f787a5f5 CW |
3675 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3676 | ret = -EIO; | |
40a5f0de EA |
3677 | } |
3678 | ||
f787a5f5 CW |
3679 | if (ret == 0) |
3680 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3681 | |
3682 | return ret; | |
3683 | } | |
3684 | ||
83d60795 | 3685 | static int |
2549d6c2 CW |
3686 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3687 | uint64_t exec_offset) | |
83d60795 CW |
3688 | { |
3689 | uint32_t exec_start, exec_len; | |
3690 | ||
3691 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3692 | exec_len = (uint32_t) exec->batch_len; | |
3693 | ||
3694 | if ((exec_start | exec_len) & 0x7) | |
3695 | return -EINVAL; | |
3696 | ||
3697 | if (!exec_start) | |
3698 | return -EINVAL; | |
3699 | ||
3700 | return 0; | |
3701 | } | |
3702 | ||
6b95a207 | 3703 | static int |
2549d6c2 CW |
3704 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3705 | int count) | |
6b95a207 | 3706 | { |
2549d6c2 | 3707 | int i; |
6b95a207 | 3708 | |
2549d6c2 CW |
3709 | for (i = 0; i < count; i++) { |
3710 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3711 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3712 | |
2549d6c2 CW |
3713 | if (!access_ok(VERIFY_READ, ptr, length)) |
3714 | return -EFAULT; | |
40a5f0de | 3715 | |
b5dc608c CW |
3716 | /* we may also need to update the presumed offsets */ |
3717 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3718 | return -EFAULT; | |
3719 | ||
2549d6c2 CW |
3720 | if (fault_in_pages_readable(ptr, length)) |
3721 | return -EFAULT; | |
6b95a207 | 3722 | } |
6b95a207 | 3723 | |
83d60795 | 3724 | return 0; |
6b95a207 KH |
3725 | } |
3726 | ||
8dc5d147 | 3727 | static int |
76446cac | 3728 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3729 | struct drm_file *file, |
76446cac JB |
3730 | struct drm_i915_gem_execbuffer2 *args, |
3731 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3732 | { |
3733 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3734 | struct drm_gem_object **object_list = NULL; |
3735 | struct drm_gem_object *batch_obj; | |
201361a5 | 3736 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3737 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3738 | int ret, i, flips; |
673a394b | 3739 | uint64_t exec_offset; |
673a394b | 3740 | |
852835f3 ZN |
3741 | struct intel_ring_buffer *ring = NULL; |
3742 | ||
30dbf0c0 CW |
3743 | ret = i915_gem_check_is_wedged(dev); |
3744 | if (ret) | |
3745 | return ret; | |
3746 | ||
2549d6c2 CW |
3747 | ret = validate_exec_list(exec_list, args->buffer_count); |
3748 | if (ret) | |
3749 | return ret; | |
3750 | ||
673a394b EA |
3751 | #if WATCH_EXEC |
3752 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3753 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3754 | #endif | |
549f7365 CW |
3755 | switch (args->flags & I915_EXEC_RING_MASK) { |
3756 | case I915_EXEC_DEFAULT: | |
3757 | case I915_EXEC_RENDER: | |
3758 | ring = &dev_priv->render_ring; | |
3759 | break; | |
3760 | case I915_EXEC_BSD: | |
d1b851fc | 3761 | if (!HAS_BSD(dev)) { |
549f7365 | 3762 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3763 | return -EINVAL; |
3764 | } | |
3765 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3766 | break; |
3767 | case I915_EXEC_BLT: | |
3768 | if (!HAS_BLT(dev)) { | |
3769 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3770 | return -EINVAL; | |
3771 | } | |
3772 | ring = &dev_priv->blt_ring; | |
3773 | break; | |
3774 | default: | |
3775 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3776 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3777 | return -EINVAL; | |
d1b851fc ZN |
3778 | } |
3779 | ||
4f481ed2 EA |
3780 | if (args->buffer_count < 1) { |
3781 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3782 | return -EINVAL; | |
3783 | } | |
c8e0f93a | 3784 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3785 | if (object_list == NULL) { |
3786 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3787 | args->buffer_count); |
3788 | ret = -ENOMEM; | |
3789 | goto pre_mutex_err; | |
3790 | } | |
673a394b | 3791 | |
201361a5 | 3792 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3793 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3794 | GFP_KERNEL); | |
a40e8d31 OA |
3795 | if (cliprects == NULL) { |
3796 | ret = -ENOMEM; | |
201361a5 | 3797 | goto pre_mutex_err; |
a40e8d31 | 3798 | } |
201361a5 EA |
3799 | |
3800 | ret = copy_from_user(cliprects, | |
3801 | (struct drm_clip_rect __user *) | |
3802 | (uintptr_t) args->cliprects_ptr, | |
3803 | sizeof(*cliprects) * args->num_cliprects); | |
3804 | if (ret != 0) { | |
3805 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3806 | args->num_cliprects, ret); | |
c877cdce | 3807 | ret = -EFAULT; |
201361a5 EA |
3808 | goto pre_mutex_err; |
3809 | } | |
3810 | } | |
3811 | ||
8dc5d147 CW |
3812 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3813 | if (request == NULL) { | |
3814 | ret = -ENOMEM; | |
40a5f0de | 3815 | goto pre_mutex_err; |
8dc5d147 | 3816 | } |
40a5f0de | 3817 | |
76c1dec1 CW |
3818 | ret = i915_mutex_lock_interruptible(dev); |
3819 | if (ret) | |
a198bc80 | 3820 | goto pre_mutex_err; |
673a394b EA |
3821 | |
3822 | if (dev_priv->mm.suspended) { | |
673a394b | 3823 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3824 | ret = -EBUSY; |
3825 | goto pre_mutex_err; | |
673a394b EA |
3826 | } |
3827 | ||
ac94a962 | 3828 | /* Look up object handles */ |
673a394b | 3829 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3830 | struct drm_i915_gem_object *obj_priv; |
3831 | ||
9af90d19 | 3832 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3833 | exec_list[i].handle); |
3834 | if (object_list[i] == NULL) { | |
3835 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3836 | exec_list[i].handle, i); | |
0ce907f8 CW |
3837 | /* prevent error path from reading uninitialized data */ |
3838 | args->buffer_count = i + 1; | |
bf79cb91 | 3839 | ret = -ENOENT; |
673a394b EA |
3840 | goto err; |
3841 | } | |
b70d11da | 3842 | |
23010e43 | 3843 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3844 | if (obj_priv->in_execbuffer) { |
3845 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3846 | object_list[i]); | |
0ce907f8 CW |
3847 | /* prevent error path from reading uninitialized data */ |
3848 | args->buffer_count = i + 1; | |
bf79cb91 | 3849 | ret = -EINVAL; |
b70d11da KH |
3850 | goto err; |
3851 | } | |
3852 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3853 | } |
673a394b | 3854 | |
9af90d19 CW |
3855 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3856 | ret = i915_gem_execbuffer_pin(dev, file, | |
3857 | object_list, exec_list, | |
3858 | args->buffer_count); | |
3859 | if (ret) | |
3860 | goto err; | |
ac94a962 | 3861 | |
9af90d19 CW |
3862 | /* The objects are in their final locations, apply the relocations. */ |
3863 | for (i = 0; i < args->buffer_count; i++) { | |
3864 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3865 | obj->base.pending_read_domains = 0; | |
3866 | obj->base.pending_write_domain = 0; | |
3867 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3868 | if (ret) | |
ac94a962 | 3869 | goto err; |
673a394b EA |
3870 | } |
3871 | ||
3872 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3873 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3874 | if (batch_obj->pending_write_domain) { |
3875 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3876 | ret = -EINVAL; | |
3877 | goto err; | |
3878 | } | |
3879 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3880 | |
9af90d19 CW |
3881 | /* Sanity check the batch buffer */ |
3882 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3883 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3884 | if (ret != 0) { |
3885 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3886 | goto err; | |
3887 | } | |
3888 | ||
13b29289 CW |
3889 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
3890 | object_list, args->buffer_count); | |
3891 | if (ret) | |
3892 | goto err; | |
673a394b | 3893 | |
673a394b EA |
3894 | #if WATCH_COHERENCY |
3895 | for (i = 0; i < args->buffer_count; i++) { | |
3896 | i915_gem_object_check_coherency(object_list[i], | |
3897 | exec_list[i].handle); | |
3898 | } | |
3899 | #endif | |
3900 | ||
673a394b | 3901 | #if WATCH_EXEC |
6911a9b8 | 3902 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3903 | args->batch_len, |
3904 | __func__, | |
3905 | ~0); | |
3906 | #endif | |
3907 | ||
e59f2bac CW |
3908 | /* Check for any pending flips. As we only maintain a flip queue depth |
3909 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3910 | * to executing the batch and avoid stalling the CPU. | |
3911 | */ | |
3912 | flips = 0; | |
3913 | for (i = 0; i < args->buffer_count; i++) { | |
3914 | if (object_list[i]->write_domain) | |
3915 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3916 | } | |
3917 | if (flips) { | |
3918 | int plane, flip_mask; | |
3919 | ||
3920 | for (plane = 0; flips >> plane; plane++) { | |
3921 | if (((flips >> plane) & 1) == 0) | |
3922 | continue; | |
3923 | ||
3924 | if (plane) | |
3925 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3926 | else | |
3927 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3928 | ||
e1f99ce6 CW |
3929 | ret = intel_ring_begin(ring, 2); |
3930 | if (ret) | |
3931 | goto err; | |
3932 | ||
78501eac CW |
3933 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
3934 | intel_ring_emit(ring, MI_NOOP); | |
3935 | intel_ring_advance(ring); | |
e59f2bac CW |
3936 | } |
3937 | } | |
3938 | ||
673a394b | 3939 | /* Exec the batchbuffer */ |
78501eac | 3940 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
3941 | if (ret) { |
3942 | DRM_ERROR("dispatch failed %d\n", ret); | |
3943 | goto err; | |
3944 | } | |
3945 | ||
673a394b EA |
3946 | for (i = 0; i < args->buffer_count; i++) { |
3947 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3948 | |
7e318e18 CW |
3949 | obj->read_domains = obj->pending_read_domains; |
3950 | obj->write_domain = obj->pending_write_domain; | |
3951 | ||
617dbe27 | 3952 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
3953 | if (obj->write_domain) { |
3954 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
3955 | obj_priv->dirty = 1; | |
3956 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 3957 | &ring->gpu_write_list); |
7e318e18 CW |
3958 | intel_mark_busy(dev, obj); |
3959 | } | |
3960 | ||
3961 | trace_i915_gem_object_change_domain(obj, | |
3962 | obj->read_domains, | |
3963 | obj->write_domain); | |
673a394b | 3964 | } |
673a394b | 3965 | |
7e318e18 CW |
3966 | /* |
3967 | * Ensure that the commands in the batch buffer are | |
3968 | * finished before the interrupt fires | |
3969 | */ | |
3970 | i915_retire_commands(dev, ring); | |
3971 | ||
3cce469c | 3972 | if (i915_add_request(dev, file, request, ring)) |
5d97eb69 | 3973 | i915_gem_next_request_seqno(dev, ring); |
3cce469c CW |
3974 | else |
3975 | request = NULL; | |
673a394b | 3976 | |
673a394b | 3977 | err: |
b70d11da | 3978 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3979 | if (object_list[i] == NULL) |
3980 | break; | |
3981 | ||
3982 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 3983 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3984 | } |
673a394b | 3985 | |
673a394b EA |
3986 | mutex_unlock(&dev->struct_mutex); |
3987 | ||
93533c29 | 3988 | pre_mutex_err: |
8e7d2b2c | 3989 | drm_free_large(object_list); |
9a298b2a | 3990 | kfree(cliprects); |
8dc5d147 | 3991 | kfree(request); |
673a394b EA |
3992 | |
3993 | return ret; | |
3994 | } | |
3995 | ||
76446cac JB |
3996 | /* |
3997 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3998 | * list array and passes it to the real function. | |
3999 | */ | |
4000 | int | |
4001 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
4002 | struct drm_file *file_priv) | |
4003 | { | |
4004 | struct drm_i915_gem_execbuffer *args = data; | |
4005 | struct drm_i915_gem_execbuffer2 exec2; | |
4006 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4007 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4008 | int ret, i; | |
4009 | ||
4010 | #if WATCH_EXEC | |
4011 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4012 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4013 | #endif | |
4014 | ||
4015 | if (args->buffer_count < 1) { | |
4016 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4017 | return -EINVAL; | |
4018 | } | |
4019 | ||
4020 | /* Copy in the exec list from userland */ | |
4021 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4022 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4023 | if (exec_list == NULL || exec2_list == NULL) { | |
4024 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4025 | args->buffer_count); | |
4026 | drm_free_large(exec_list); | |
4027 | drm_free_large(exec2_list); | |
4028 | return -ENOMEM; | |
4029 | } | |
4030 | ret = copy_from_user(exec_list, | |
4031 | (struct drm_i915_relocation_entry __user *) | |
4032 | (uintptr_t) args->buffers_ptr, | |
4033 | sizeof(*exec_list) * args->buffer_count); | |
4034 | if (ret != 0) { | |
4035 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4036 | args->buffer_count, ret); | |
4037 | drm_free_large(exec_list); | |
4038 | drm_free_large(exec2_list); | |
4039 | return -EFAULT; | |
4040 | } | |
4041 | ||
4042 | for (i = 0; i < args->buffer_count; i++) { | |
4043 | exec2_list[i].handle = exec_list[i].handle; | |
4044 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4045 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4046 | exec2_list[i].alignment = exec_list[i].alignment; | |
4047 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4048 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4049 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4050 | else | |
4051 | exec2_list[i].flags = 0; | |
4052 | } | |
4053 | ||
4054 | exec2.buffers_ptr = args->buffers_ptr; | |
4055 | exec2.buffer_count = args->buffer_count; | |
4056 | exec2.batch_start_offset = args->batch_start_offset; | |
4057 | exec2.batch_len = args->batch_len; | |
4058 | exec2.DR1 = args->DR1; | |
4059 | exec2.DR4 = args->DR4; | |
4060 | exec2.num_cliprects = args->num_cliprects; | |
4061 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4062 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4063 | |
4064 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4065 | if (!ret) { | |
4066 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4067 | for (i = 0; i < args->buffer_count; i++) | |
4068 | exec_list[i].offset = exec2_list[i].offset; | |
4069 | /* ... and back out to userspace */ | |
4070 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4071 | (uintptr_t) args->buffers_ptr, | |
4072 | exec_list, | |
4073 | sizeof(*exec_list) * args->buffer_count); | |
4074 | if (ret) { | |
4075 | ret = -EFAULT; | |
4076 | DRM_ERROR("failed to copy %d exec entries " | |
4077 | "back to user (%d)\n", | |
4078 | args->buffer_count, ret); | |
4079 | } | |
76446cac JB |
4080 | } |
4081 | ||
4082 | drm_free_large(exec_list); | |
4083 | drm_free_large(exec2_list); | |
4084 | return ret; | |
4085 | } | |
4086 | ||
4087 | int | |
4088 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4089 | struct drm_file *file_priv) | |
4090 | { | |
4091 | struct drm_i915_gem_execbuffer2 *args = data; | |
4092 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4093 | int ret; | |
4094 | ||
4095 | #if WATCH_EXEC | |
4096 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4097 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4098 | #endif | |
4099 | ||
4100 | if (args->buffer_count < 1) { | |
4101 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4102 | return -EINVAL; | |
4103 | } | |
4104 | ||
4105 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4106 | if (exec2_list == NULL) { | |
4107 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4108 | args->buffer_count); | |
4109 | return -ENOMEM; | |
4110 | } | |
4111 | ret = copy_from_user(exec2_list, | |
4112 | (struct drm_i915_relocation_entry __user *) | |
4113 | (uintptr_t) args->buffers_ptr, | |
4114 | sizeof(*exec2_list) * args->buffer_count); | |
4115 | if (ret != 0) { | |
4116 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4117 | args->buffer_count, ret); | |
4118 | drm_free_large(exec2_list); | |
4119 | return -EFAULT; | |
4120 | } | |
4121 | ||
4122 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4123 | if (!ret) { | |
4124 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4125 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4126 | (uintptr_t) args->buffers_ptr, | |
4127 | exec2_list, | |
4128 | sizeof(*exec2_list) * args->buffer_count); | |
4129 | if (ret) { | |
4130 | ret = -EFAULT; | |
4131 | DRM_ERROR("failed to copy %d exec entries " | |
4132 | "back to user (%d)\n", | |
4133 | args->buffer_count, ret); | |
4134 | } | |
4135 | } | |
4136 | ||
4137 | drm_free_large(exec2_list); | |
4138 | return ret; | |
4139 | } | |
4140 | ||
673a394b | 4141 | int |
920afa77 | 4142 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
75e9e915 | 4143 | bool map_and_fenceable) |
673a394b EA |
4144 | { |
4145 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4146 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4147 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4148 | int ret; |
4149 | ||
778c3544 | 4150 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
75e9e915 | 4151 | BUG_ON(map_and_fenceable && !map_and_fenceable); |
23bc5982 | 4152 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4153 | |
4154 | if (obj_priv->gtt_space != NULL) { | |
a00b10c3 | 4155 | if ((alignment && obj_priv->gtt_offset & (alignment - 1)) || |
75e9e915 | 4156 | (map_and_fenceable && !obj_priv->map_and_fenceable)) { |
ae7d49d8 CW |
4157 | WARN(obj_priv->pin_count, |
4158 | "bo is already pinned with incorrect alignment:" | |
75e9e915 DV |
4159 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
4160 | " obj->map_and_fenceable=%d\n", | |
a00b10c3 | 4161 | obj_priv->gtt_offset, alignment, |
75e9e915 DV |
4162 | map_and_fenceable, |
4163 | obj_priv->map_and_fenceable); | |
ac0c6b5a CW |
4164 | ret = i915_gem_object_unbind(obj); |
4165 | if (ret) | |
4166 | return ret; | |
4167 | } | |
4168 | } | |
4169 | ||
673a394b | 4170 | if (obj_priv->gtt_space == NULL) { |
a00b10c3 | 4171 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 4172 | map_and_fenceable); |
9731129c | 4173 | if (ret) |
673a394b | 4174 | return ret; |
22c344e9 | 4175 | } |
76446cac | 4176 | |
7465378f | 4177 | if (obj_priv->pin_count++ == 0) { |
75e9e915 | 4178 | i915_gem_info_add_pin(dev_priv, obj_priv, map_and_fenceable); |
f13d3f73 | 4179 | if (!obj_priv->active) |
69dc4987 | 4180 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4181 | &dev_priv->mm.pinned_list); |
673a394b | 4182 | } |
75e9e915 | 4183 | BUG_ON(!obj_priv->pin_mappable && map_and_fenceable); |
673a394b | 4184 | |
23bc5982 | 4185 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4186 | return 0; |
4187 | } | |
4188 | ||
4189 | void | |
4190 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4191 | { | |
4192 | struct drm_device *dev = obj->dev; | |
4193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4194 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4195 | |
23bc5982 | 4196 | WARN_ON(i915_verify_lists(dev)); |
7465378f | 4197 | BUG_ON(obj_priv->pin_count == 0); |
673a394b EA |
4198 | BUG_ON(obj_priv->gtt_space == NULL); |
4199 | ||
7465378f | 4200 | if (--obj_priv->pin_count == 0) { |
f13d3f73 | 4201 | if (!obj_priv->active) |
69dc4987 | 4202 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4203 | &dev_priv->mm.inactive_list); |
a00b10c3 | 4204 | i915_gem_info_remove_pin(dev_priv, obj_priv); |
673a394b | 4205 | } |
23bc5982 | 4206 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4207 | } |
4208 | ||
4209 | int | |
4210 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4211 | struct drm_file *file_priv) | |
4212 | { | |
4213 | struct drm_i915_gem_pin *args = data; | |
4214 | struct drm_gem_object *obj; | |
4215 | struct drm_i915_gem_object *obj_priv; | |
4216 | int ret; | |
4217 | ||
1d7cfea1 CW |
4218 | ret = i915_mutex_lock_interruptible(dev); |
4219 | if (ret) | |
4220 | return ret; | |
673a394b EA |
4221 | |
4222 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4223 | if (obj == NULL) { | |
1d7cfea1 CW |
4224 | ret = -ENOENT; |
4225 | goto unlock; | |
673a394b | 4226 | } |
23010e43 | 4227 | obj_priv = to_intel_bo(obj); |
673a394b | 4228 | |
bb6baf76 CW |
4229 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4230 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4231 | ret = -EINVAL; |
4232 | goto out; | |
3ef94daa CW |
4233 | } |
4234 | ||
79e53945 JB |
4235 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4236 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4237 | args->handle); | |
1d7cfea1 CW |
4238 | ret = -EINVAL; |
4239 | goto out; | |
79e53945 JB |
4240 | } |
4241 | ||
4242 | obj_priv->user_pin_count++; | |
4243 | obj_priv->pin_filp = file_priv; | |
4244 | if (obj_priv->user_pin_count == 1) { | |
75e9e915 | 4245 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4246 | if (ret) |
4247 | goto out; | |
673a394b EA |
4248 | } |
4249 | ||
4250 | /* XXX - flush the CPU caches for pinned objects | |
4251 | * as the X server doesn't manage domains yet | |
4252 | */ | |
e47c68e9 | 4253 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4254 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4255 | out: |
673a394b | 4256 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4257 | unlock: |
673a394b | 4258 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4259 | return ret; |
673a394b EA |
4260 | } |
4261 | ||
4262 | int | |
4263 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4264 | struct drm_file *file_priv) | |
4265 | { | |
4266 | struct drm_i915_gem_pin *args = data; | |
4267 | struct drm_gem_object *obj; | |
79e53945 | 4268 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4269 | int ret; |
673a394b | 4270 | |
1d7cfea1 CW |
4271 | ret = i915_mutex_lock_interruptible(dev); |
4272 | if (ret) | |
4273 | return ret; | |
673a394b EA |
4274 | |
4275 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4276 | if (obj == NULL) { | |
1d7cfea1 CW |
4277 | ret = -ENOENT; |
4278 | goto unlock; | |
673a394b | 4279 | } |
23010e43 | 4280 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4281 | |
79e53945 JB |
4282 | if (obj_priv->pin_filp != file_priv) { |
4283 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4284 | args->handle); | |
1d7cfea1 CW |
4285 | ret = -EINVAL; |
4286 | goto out; | |
79e53945 JB |
4287 | } |
4288 | obj_priv->user_pin_count--; | |
4289 | if (obj_priv->user_pin_count == 0) { | |
4290 | obj_priv->pin_filp = NULL; | |
4291 | i915_gem_object_unpin(obj); | |
4292 | } | |
673a394b | 4293 | |
1d7cfea1 | 4294 | out: |
673a394b | 4295 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4296 | unlock: |
673a394b | 4297 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4298 | return ret; |
673a394b EA |
4299 | } |
4300 | ||
4301 | int | |
4302 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4303 | struct drm_file *file_priv) | |
4304 | { | |
4305 | struct drm_i915_gem_busy *args = data; | |
4306 | struct drm_gem_object *obj; | |
4307 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4308 | int ret; |
4309 | ||
76c1dec1 | 4310 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4311 | if (ret) |
76c1dec1 | 4312 | return ret; |
673a394b | 4313 | |
673a394b EA |
4314 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4315 | if (obj == NULL) { | |
1d7cfea1 CW |
4316 | ret = -ENOENT; |
4317 | goto unlock; | |
673a394b | 4318 | } |
1d7cfea1 | 4319 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4320 | |
0be555b6 CW |
4321 | /* Count all active objects as busy, even if they are currently not used |
4322 | * by the gpu. Users of this interface expect objects to eventually | |
4323 | * become non-busy without any further actions, therefore emit any | |
4324 | * necessary flushes here. | |
c4de0a5d | 4325 | */ |
0be555b6 CW |
4326 | args->busy = obj_priv->active; |
4327 | if (args->busy) { | |
4328 | /* Unconditionally flush objects, even when the gpu still uses this | |
4329 | * object. Userspace calling this function indicates that it wants to | |
4330 | * use this buffer rather sooner than later, so issuing the required | |
4331 | * flush earlier is beneficial. | |
4332 | */ | |
c78ec30b CW |
4333 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4334 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4335 | obj_priv->ring, |
4336 | 0, obj->write_domain); | |
0be555b6 CW |
4337 | |
4338 | /* Update the active list for the hardware's current position. | |
4339 | * Otherwise this only updates on a delayed timer or when irqs | |
4340 | * are actually unmasked, and our working set ends up being | |
4341 | * larger than required. | |
4342 | */ | |
4343 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4344 | ||
4345 | args->busy = obj_priv->active; | |
4346 | } | |
673a394b EA |
4347 | |
4348 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4349 | unlock: |
673a394b | 4350 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4351 | return ret; |
673a394b EA |
4352 | } |
4353 | ||
4354 | int | |
4355 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4356 | struct drm_file *file_priv) | |
4357 | { | |
4358 | return i915_gem_ring_throttle(dev, file_priv); | |
4359 | } | |
4360 | ||
3ef94daa CW |
4361 | int |
4362 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4363 | struct drm_file *file_priv) | |
4364 | { | |
4365 | struct drm_i915_gem_madvise *args = data; | |
4366 | struct drm_gem_object *obj; | |
4367 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4368 | int ret; |
3ef94daa CW |
4369 | |
4370 | switch (args->madv) { | |
4371 | case I915_MADV_DONTNEED: | |
4372 | case I915_MADV_WILLNEED: | |
4373 | break; | |
4374 | default: | |
4375 | return -EINVAL; | |
4376 | } | |
4377 | ||
1d7cfea1 CW |
4378 | ret = i915_mutex_lock_interruptible(dev); |
4379 | if (ret) | |
4380 | return ret; | |
4381 | ||
3ef94daa CW |
4382 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4383 | if (obj == NULL) { | |
1d7cfea1 CW |
4384 | ret = -ENOENT; |
4385 | goto unlock; | |
3ef94daa | 4386 | } |
23010e43 | 4387 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4388 | |
4389 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4390 | ret = -EINVAL; |
4391 | goto out; | |
3ef94daa CW |
4392 | } |
4393 | ||
bb6baf76 CW |
4394 | if (obj_priv->madv != __I915_MADV_PURGED) |
4395 | obj_priv->madv = args->madv; | |
3ef94daa | 4396 | |
2d7ef395 CW |
4397 | /* if the object is no longer bound, discard its backing storage */ |
4398 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4399 | obj_priv->gtt_space == NULL) | |
4400 | i915_gem_object_truncate(obj); | |
4401 | ||
bb6baf76 CW |
4402 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4403 | ||
1d7cfea1 | 4404 | out: |
3ef94daa | 4405 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4406 | unlock: |
3ef94daa | 4407 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4408 | return ret; |
3ef94daa CW |
4409 | } |
4410 | ||
ac52bc56 DV |
4411 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4412 | size_t size) | |
4413 | { | |
73aa808f | 4414 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4415 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4416 | |
c397b908 DV |
4417 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4418 | if (obj == NULL) | |
4419 | return NULL; | |
673a394b | 4420 | |
c397b908 DV |
4421 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4422 | kfree(obj); | |
4423 | return NULL; | |
4424 | } | |
673a394b | 4425 | |
73aa808f CW |
4426 | i915_gem_info_add_obj(dev_priv, size); |
4427 | ||
c397b908 DV |
4428 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4429 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4430 | |
c397b908 | 4431 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4432 | obj->base.driver_private = NULL; |
c397b908 | 4433 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4434 | INIT_LIST_HEAD(&obj->mm_list); |
4435 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4436 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4437 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
4438 | /* Avoid an unnecessary call to unbind on the first bind. */ |
4439 | obj->map_and_fenceable = true; | |
de151cf6 | 4440 | |
c397b908 DV |
4441 | return &obj->base; |
4442 | } | |
4443 | ||
4444 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4445 | { | |
4446 | BUG(); | |
de151cf6 | 4447 | |
673a394b EA |
4448 | return 0; |
4449 | } | |
4450 | ||
be72615b | 4451 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4452 | { |
de151cf6 | 4453 | struct drm_device *dev = obj->dev; |
be72615b | 4454 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4455 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4456 | int ret; |
673a394b | 4457 | |
be72615b CW |
4458 | ret = i915_gem_object_unbind(obj); |
4459 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4460 | list_move(&obj_priv->mm_list, |
be72615b CW |
4461 | &dev_priv->mm.deferred_free_list); |
4462 | return; | |
4463 | } | |
673a394b | 4464 | |
39a01d1f | 4465 | if (obj->map_list.map) |
7e616158 | 4466 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4467 | |
c397b908 | 4468 | drm_gem_object_release(obj); |
73aa808f | 4469 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4470 | |
9a298b2a | 4471 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4472 | kfree(obj_priv->bit_17); |
c397b908 | 4473 | kfree(obj_priv); |
673a394b EA |
4474 | } |
4475 | ||
be72615b CW |
4476 | void i915_gem_free_object(struct drm_gem_object *obj) |
4477 | { | |
4478 | struct drm_device *dev = obj->dev; | |
4479 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4480 | ||
4481 | trace_i915_gem_object_destroy(obj); | |
4482 | ||
4483 | while (obj_priv->pin_count > 0) | |
4484 | i915_gem_object_unpin(obj); | |
4485 | ||
4486 | if (obj_priv->phys_obj) | |
4487 | i915_gem_detach_phys_object(dev, obj); | |
4488 | ||
4489 | i915_gem_free_object_tail(obj); | |
4490 | } | |
4491 | ||
29105ccc CW |
4492 | int |
4493 | i915_gem_idle(struct drm_device *dev) | |
4494 | { | |
4495 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4496 | int ret; | |
28dfe52a | 4497 | |
29105ccc | 4498 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4499 | |
87acb0a5 | 4500 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4501 | mutex_unlock(&dev->struct_mutex); |
4502 | return 0; | |
28dfe52a EA |
4503 | } |
4504 | ||
29105ccc | 4505 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4506 | if (ret) { |
4507 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4508 | return ret; |
6dbe2772 | 4509 | } |
673a394b | 4510 | |
29105ccc CW |
4511 | /* Under UMS, be paranoid and evict. */ |
4512 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 4513 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
4514 | if (ret) { |
4515 | mutex_unlock(&dev->struct_mutex); | |
4516 | return ret; | |
4517 | } | |
4518 | } | |
4519 | ||
4520 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4521 | * We need to replace this with a semaphore, or something. | |
4522 | * And not confound mm.suspended! | |
4523 | */ | |
4524 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4525 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4526 | |
4527 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4528 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4529 | |
6dbe2772 KP |
4530 | mutex_unlock(&dev->struct_mutex); |
4531 | ||
29105ccc CW |
4532 | /* Cancel the retire work handler, which should be idle now. */ |
4533 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4534 | ||
673a394b EA |
4535 | return 0; |
4536 | } | |
4537 | ||
e552eb70 JB |
4538 | /* |
4539 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4540 | * over cache flushing. | |
4541 | */ | |
8187a2b7 | 4542 | static int |
e552eb70 JB |
4543 | i915_gem_init_pipe_control(struct drm_device *dev) |
4544 | { | |
4545 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4546 | struct drm_gem_object *obj; | |
4547 | struct drm_i915_gem_object *obj_priv; | |
4548 | int ret; | |
4549 | ||
34dc4d44 | 4550 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4551 | if (obj == NULL) { |
4552 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4553 | ret = -ENOMEM; | |
4554 | goto err; | |
4555 | } | |
4556 | obj_priv = to_intel_bo(obj); | |
4557 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4558 | ||
75e9e915 | 4559 | ret = i915_gem_object_pin(obj, 4096, true); |
e552eb70 JB |
4560 | if (ret) |
4561 | goto err_unref; | |
4562 | ||
4563 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4564 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4565 | if (dev_priv->seqno_page == NULL) | |
4566 | goto err_unpin; | |
4567 | ||
4568 | dev_priv->seqno_obj = obj; | |
4569 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4570 | ||
4571 | return 0; | |
4572 | ||
4573 | err_unpin: | |
4574 | i915_gem_object_unpin(obj); | |
4575 | err_unref: | |
4576 | drm_gem_object_unreference(obj); | |
4577 | err: | |
4578 | return ret; | |
4579 | } | |
4580 | ||
8187a2b7 ZN |
4581 | |
4582 | static void | |
e552eb70 JB |
4583 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4584 | { | |
4585 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4586 | struct drm_gem_object *obj; | |
4587 | struct drm_i915_gem_object *obj_priv; | |
4588 | ||
4589 | obj = dev_priv->seqno_obj; | |
4590 | obj_priv = to_intel_bo(obj); | |
4591 | kunmap(obj_priv->pages[0]); | |
4592 | i915_gem_object_unpin(obj); | |
4593 | drm_gem_object_unreference(obj); | |
4594 | dev_priv->seqno_obj = NULL; | |
4595 | ||
4596 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4597 | } |
4598 | ||
8187a2b7 ZN |
4599 | int |
4600 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4601 | { | |
4602 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4603 | int ret; | |
68f95ba9 | 4604 | |
8187a2b7 ZN |
4605 | if (HAS_PIPE_CONTROL(dev)) { |
4606 | ret = i915_gem_init_pipe_control(dev); | |
4607 | if (ret) | |
4608 | return ret; | |
4609 | } | |
68f95ba9 | 4610 | |
5c1143bb | 4611 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4612 | if (ret) |
4613 | goto cleanup_pipe_control; | |
4614 | ||
4615 | if (HAS_BSD(dev)) { | |
5c1143bb | 4616 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4617 | if (ret) |
4618 | goto cleanup_render_ring; | |
d1b851fc | 4619 | } |
68f95ba9 | 4620 | |
549f7365 CW |
4621 | if (HAS_BLT(dev)) { |
4622 | ret = intel_init_blt_ring_buffer(dev); | |
4623 | if (ret) | |
4624 | goto cleanup_bsd_ring; | |
4625 | } | |
4626 | ||
6f392d54 CW |
4627 | dev_priv->next_seqno = 1; |
4628 | ||
68f95ba9 CW |
4629 | return 0; |
4630 | ||
549f7365 | 4631 | cleanup_bsd_ring: |
78501eac | 4632 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4633 | cleanup_render_ring: |
78501eac | 4634 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4635 | cleanup_pipe_control: |
4636 | if (HAS_PIPE_CONTROL(dev)) | |
4637 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4638 | return ret; |
4639 | } | |
4640 | ||
4641 | void | |
4642 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4643 | { | |
4644 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4645 | ||
78501eac CW |
4646 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4647 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4648 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4649 | if (HAS_PIPE_CONTROL(dev)) |
4650 | i915_gem_cleanup_pipe_control(dev); | |
4651 | } | |
4652 | ||
673a394b EA |
4653 | int |
4654 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4655 | struct drm_file *file_priv) | |
4656 | { | |
4657 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4658 | int ret; | |
4659 | ||
79e53945 JB |
4660 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4661 | return 0; | |
4662 | ||
ba1234d1 | 4663 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4664 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4665 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4666 | } |
4667 | ||
673a394b | 4668 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4669 | dev_priv->mm.suspended = 0; |
4670 | ||
4671 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4672 | if (ret != 0) { |
4673 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4674 | return ret; |
d816f6ac | 4675 | } |
9bb2d6f9 | 4676 | |
69dc4987 | 4677 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4678 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4679 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4680 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4681 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4682 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4683 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4684 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4685 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4686 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4687 | |
5f35308b CW |
4688 | ret = drm_irq_install(dev); |
4689 | if (ret) | |
4690 | goto cleanup_ringbuffer; | |
dbb19d30 | 4691 | |
673a394b | 4692 | return 0; |
5f35308b CW |
4693 | |
4694 | cleanup_ringbuffer: | |
4695 | mutex_lock(&dev->struct_mutex); | |
4696 | i915_gem_cleanup_ringbuffer(dev); | |
4697 | dev_priv->mm.suspended = 1; | |
4698 | mutex_unlock(&dev->struct_mutex); | |
4699 | ||
4700 | return ret; | |
673a394b EA |
4701 | } |
4702 | ||
4703 | int | |
4704 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4705 | struct drm_file *file_priv) | |
4706 | { | |
79e53945 JB |
4707 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4708 | return 0; | |
4709 | ||
dbb19d30 | 4710 | drm_irq_uninstall(dev); |
e6890f6f | 4711 | return i915_gem_idle(dev); |
673a394b EA |
4712 | } |
4713 | ||
4714 | void | |
4715 | i915_gem_lastclose(struct drm_device *dev) | |
4716 | { | |
4717 | int ret; | |
673a394b | 4718 | |
e806b495 EA |
4719 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4720 | return; | |
4721 | ||
6dbe2772 KP |
4722 | ret = i915_gem_idle(dev); |
4723 | if (ret) | |
4724 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4725 | } |
4726 | ||
64193406 CW |
4727 | static void |
4728 | init_ring_lists(struct intel_ring_buffer *ring) | |
4729 | { | |
4730 | INIT_LIST_HEAD(&ring->active_list); | |
4731 | INIT_LIST_HEAD(&ring->request_list); | |
4732 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4733 | } | |
4734 | ||
673a394b EA |
4735 | void |
4736 | i915_gem_load(struct drm_device *dev) | |
4737 | { | |
b5aa8a0f | 4738 | int i; |
673a394b EA |
4739 | drm_i915_private_t *dev_priv = dev->dev_private; |
4740 | ||
69dc4987 | 4741 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4742 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4743 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4744 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4745 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4746 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4747 | init_ring_lists(&dev_priv->render_ring); |
4748 | init_ring_lists(&dev_priv->bsd_ring); | |
4749 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4750 | for (i = 0; i < 16; i++) |
4751 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4752 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4753 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4754 | init_completion(&dev_priv->error_completion); |
31169714 | 4755 | |
94400120 DA |
4756 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4757 | if (IS_GEN3(dev)) { | |
4758 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4759 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4760 | /* arb state is a masked write, so set bit + bit in mask */ | |
4761 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4762 | I915_WRITE(MI_ARB_STATE, tmp); | |
4763 | } | |
4764 | } | |
4765 | ||
de151cf6 | 4766 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4767 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4768 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4769 | |
a6c45cf0 | 4770 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4771 | dev_priv->num_fence_regs = 16; |
4772 | else | |
4773 | dev_priv->num_fence_regs = 8; | |
4774 | ||
b5aa8a0f | 4775 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4776 | switch (INTEL_INFO(dev)->gen) { |
4777 | case 6: | |
4778 | for (i = 0; i < 16; i++) | |
4779 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4780 | break; | |
4781 | case 5: | |
4782 | case 4: | |
b5aa8a0f GH |
4783 | for (i = 0; i < 16; i++) |
4784 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4785 | break; |
4786 | case 3: | |
b5aa8a0f GH |
4787 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4788 | for (i = 0; i < 8; i++) | |
4789 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4790 | case 2: |
4791 | for (i = 0; i < 8; i++) | |
4792 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4793 | break; | |
b5aa8a0f | 4794 | } |
673a394b | 4795 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4796 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4797 | |
4798 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4799 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4800 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4801 | } |
71acb5eb DA |
4802 | |
4803 | /* | |
4804 | * Create a physically contiguous memory object for this object | |
4805 | * e.g. for cursor + overlay regs | |
4806 | */ | |
995b6762 CW |
4807 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4808 | int id, int size, int align) | |
71acb5eb DA |
4809 | { |
4810 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4811 | struct drm_i915_gem_phys_object *phys_obj; | |
4812 | int ret; | |
4813 | ||
4814 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4815 | return 0; | |
4816 | ||
9a298b2a | 4817 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4818 | if (!phys_obj) |
4819 | return -ENOMEM; | |
4820 | ||
4821 | phys_obj->id = id; | |
4822 | ||
6eeefaf3 | 4823 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4824 | if (!phys_obj->handle) { |
4825 | ret = -ENOMEM; | |
4826 | goto kfree_obj; | |
4827 | } | |
4828 | #ifdef CONFIG_X86 | |
4829 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4830 | #endif | |
4831 | ||
4832 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4833 | ||
4834 | return 0; | |
4835 | kfree_obj: | |
9a298b2a | 4836 | kfree(phys_obj); |
71acb5eb DA |
4837 | return ret; |
4838 | } | |
4839 | ||
995b6762 | 4840 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4841 | { |
4842 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4843 | struct drm_i915_gem_phys_object *phys_obj; | |
4844 | ||
4845 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4846 | return; | |
4847 | ||
4848 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4849 | if (phys_obj->cur_obj) { | |
4850 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4851 | } | |
4852 | ||
4853 | #ifdef CONFIG_X86 | |
4854 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4855 | #endif | |
4856 | drm_pci_free(dev, phys_obj->handle); | |
4857 | kfree(phys_obj); | |
4858 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4859 | } | |
4860 | ||
4861 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4862 | { | |
4863 | int i; | |
4864 | ||
260883c8 | 4865 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4866 | i915_gem_free_phys_object(dev, i); |
4867 | } | |
4868 | ||
4869 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4870 | struct drm_gem_object *obj) | |
4871 | { | |
e5281ccd CW |
4872 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
4873 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4874 | char *vaddr; | |
71acb5eb | 4875 | int i; |
71acb5eb DA |
4876 | int page_count; |
4877 | ||
71acb5eb DA |
4878 | if (!obj_priv->phys_obj) |
4879 | return; | |
e5281ccd | 4880 | vaddr = obj_priv->phys_obj->handle->vaddr; |
71acb5eb DA |
4881 | |
4882 | page_count = obj->size / PAGE_SIZE; | |
4883 | ||
4884 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4885 | struct page *page = read_cache_page_gfp(mapping, i, |
4886 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4887 | if (!IS_ERR(page)) { | |
4888 | char *dst = kmap_atomic(page); | |
4889 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4890 | kunmap_atomic(dst); | |
4891 | ||
4892 | drm_clflush_pages(&page, 1); | |
4893 | ||
4894 | set_page_dirty(page); | |
4895 | mark_page_accessed(page); | |
4896 | page_cache_release(page); | |
4897 | } | |
71acb5eb | 4898 | } |
71acb5eb | 4899 | drm_agp_chipset_flush(dev); |
d78b47b9 | 4900 | |
71acb5eb DA |
4901 | obj_priv->phys_obj->cur_obj = NULL; |
4902 | obj_priv->phys_obj = NULL; | |
4903 | } | |
4904 | ||
4905 | int | |
4906 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4907 | struct drm_gem_object *obj, |
4908 | int id, | |
4909 | int align) | |
71acb5eb | 4910 | { |
e5281ccd | 4911 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb DA |
4912 | drm_i915_private_t *dev_priv = dev->dev_private; |
4913 | struct drm_i915_gem_object *obj_priv; | |
4914 | int ret = 0; | |
4915 | int page_count; | |
4916 | int i; | |
4917 | ||
4918 | if (id > I915_MAX_PHYS_OBJECT) | |
4919 | return -EINVAL; | |
4920 | ||
23010e43 | 4921 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4922 | |
4923 | if (obj_priv->phys_obj) { | |
4924 | if (obj_priv->phys_obj->id == id) | |
4925 | return 0; | |
4926 | i915_gem_detach_phys_object(dev, obj); | |
4927 | } | |
4928 | ||
71acb5eb DA |
4929 | /* create a new object */ |
4930 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4931 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4932 | obj->size, align); |
71acb5eb | 4933 | if (ret) { |
aeb565df | 4934 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
e5281ccd | 4935 | return ret; |
71acb5eb DA |
4936 | } |
4937 | } | |
4938 | ||
4939 | /* bind to the object */ | |
4940 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4941 | obj_priv->phys_obj->cur_obj = obj; | |
4942 | ||
71acb5eb DA |
4943 | page_count = obj->size / PAGE_SIZE; |
4944 | ||
4945 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4946 | struct page *page; |
4947 | char *dst, *src; | |
4948 | ||
4949 | page = read_cache_page_gfp(mapping, i, | |
4950 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4951 | if (IS_ERR(page)) | |
4952 | return PTR_ERR(page); | |
71acb5eb | 4953 | |
ff75b9bc | 4954 | src = kmap_atomic(page); |
e5281ccd | 4955 | dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4956 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4957 | kunmap_atomic(src); |
71acb5eb | 4958 | |
e5281ccd CW |
4959 | mark_page_accessed(page); |
4960 | page_cache_release(page); | |
4961 | } | |
d78b47b9 | 4962 | |
71acb5eb | 4963 | return 0; |
71acb5eb DA |
4964 | } |
4965 | ||
4966 | static int | |
4967 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4968 | struct drm_i915_gem_pwrite *args, | |
4969 | struct drm_file *file_priv) | |
4970 | { | |
23010e43 | 4971 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4972 | void *obj_addr; |
4973 | int ret; | |
4974 | char __user *user_data; | |
4975 | ||
4976 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4977 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4978 | ||
44d98a61 | 4979 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4980 | ret = copy_from_user(obj_addr, user_data, args->size); |
4981 | if (ret) | |
4982 | return -EFAULT; | |
4983 | ||
4984 | drm_agp_chipset_flush(dev); | |
4985 | return 0; | |
4986 | } | |
b962442e | 4987 | |
f787a5f5 | 4988 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4989 | { |
f787a5f5 | 4990 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4991 | |
4992 | /* Clean up our request list when the client is going away, so that | |
4993 | * later retire_requests won't dereference our soon-to-be-gone | |
4994 | * file_priv. | |
4995 | */ | |
1c25595f | 4996 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4997 | while (!list_empty(&file_priv->mm.request_list)) { |
4998 | struct drm_i915_gem_request *request; | |
4999 | ||
5000 | request = list_first_entry(&file_priv->mm.request_list, | |
5001 | struct drm_i915_gem_request, | |
5002 | client_list); | |
5003 | list_del(&request->client_list); | |
5004 | request->file_priv = NULL; | |
5005 | } | |
1c25595f | 5006 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5007 | } |
31169714 | 5008 | |
1637ef41 CW |
5009 | static int |
5010 | i915_gpu_is_active(struct drm_device *dev) | |
5011 | { | |
5012 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5013 | int lists_empty; | |
5014 | ||
1637ef41 | 5015 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 5016 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
5017 | |
5018 | return !lists_empty; | |
5019 | } | |
5020 | ||
31169714 | 5021 | static int |
17250b71 CW |
5022 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
5023 | int nr_to_scan, | |
5024 | gfp_t gfp_mask) | |
31169714 | 5025 | { |
17250b71 CW |
5026 | struct drm_i915_private *dev_priv = |
5027 | container_of(shrinker, | |
5028 | struct drm_i915_private, | |
5029 | mm.inactive_shrinker); | |
5030 | struct drm_device *dev = dev_priv->dev; | |
5031 | struct drm_i915_gem_object *obj, *next; | |
5032 | int cnt; | |
5033 | ||
5034 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 5035 | return 0; |
31169714 CW |
5036 | |
5037 | /* "fast-path" to count number of available objects */ | |
5038 | if (nr_to_scan == 0) { | |
17250b71 CW |
5039 | cnt = 0; |
5040 | list_for_each_entry(obj, | |
5041 | &dev_priv->mm.inactive_list, | |
5042 | mm_list) | |
5043 | cnt++; | |
5044 | mutex_unlock(&dev->struct_mutex); | |
5045 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5046 | } |
5047 | ||
1637ef41 | 5048 | rescan: |
31169714 | 5049 | /* first scan for clean buffers */ |
17250b71 | 5050 | i915_gem_retire_requests(dev); |
31169714 | 5051 | |
17250b71 CW |
5052 | list_for_each_entry_safe(obj, next, |
5053 | &dev_priv->mm.inactive_list, | |
5054 | mm_list) { | |
5055 | if (i915_gem_object_is_purgeable(obj)) { | |
5056 | i915_gem_object_unbind(&obj->base); | |
5057 | if (--nr_to_scan == 0) | |
5058 | break; | |
31169714 | 5059 | } |
31169714 CW |
5060 | } |
5061 | ||
5062 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5063 | cnt = 0; |
5064 | list_for_each_entry_safe(obj, next, | |
5065 | &dev_priv->mm.inactive_list, | |
5066 | mm_list) { | |
5067 | if (nr_to_scan) { | |
5068 | i915_gem_object_unbind(&obj->base); | |
5069 | nr_to_scan--; | |
5070 | } else | |
5071 | cnt++; | |
5072 | } | |
5073 | ||
5074 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5075 | /* |
5076 | * We are desperate for pages, so as a last resort, wait | |
5077 | * for the GPU to finish and discard whatever we can. | |
5078 | * This has a dramatic impact to reduce the number of | |
5079 | * OOM-killer events whilst running the GPU aggressively. | |
5080 | */ | |
17250b71 | 5081 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5082 | goto rescan; |
5083 | } | |
17250b71 CW |
5084 | mutex_unlock(&dev->struct_mutex); |
5085 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5086 | } |