Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 CW |
89 | static int |
90 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
91 | { |
92 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93 | struct completion *x = &dev_priv->error_completion; | |
94 | unsigned long flags; | |
95 | int ret; | |
96 | ||
97 | if (!atomic_read(&dev_priv->mm.wedged)) | |
98 | return 0; | |
99 | ||
0a6759c6 DV |
100 | /* |
101 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
102 | * userspace. If it takes that long something really bad is going on and | |
103 | * we should simply try to bail out and fail as gracefully as possible. | |
104 | */ | |
105 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
106 | if (ret == 0) { | |
107 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
108 | return -EIO; | |
109 | } else if (ret < 0) { | |
30dbf0c0 | 110 | return ret; |
0a6759c6 | 111 | } |
30dbf0c0 | 112 | |
21dd3734 CW |
113 | if (atomic_read(&dev_priv->mm.wedged)) { |
114 | /* GPU is hung, bump the completion count to account for | |
115 | * the token we just consumed so that we never hit zero and | |
116 | * end up waiting upon a subsequent completion event that | |
117 | * will never happen. | |
118 | */ | |
119 | spin_lock_irqsave(&x->wait.lock, flags); | |
120 | x->done++; | |
121 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
122 | } | |
123 | return 0; | |
30dbf0c0 CW |
124 | } |
125 | ||
54cf91dc | 126 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 127 | { |
76c1dec1 CW |
128 | int ret; |
129 | ||
21dd3734 | 130 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
131 | if (ret) |
132 | return ret; | |
133 | ||
134 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
23bc5982 | 138 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
139 | return 0; |
140 | } | |
30dbf0c0 | 141 | |
7d1c4804 | 142 | static inline bool |
05394f39 | 143 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 144 | { |
6c085a72 | 145 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
146 | } |
147 | ||
79e53945 JB |
148 | int |
149 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
79e53945 JB |
151 | { |
152 | struct drm_i915_gem_init *args = data; | |
2021746e | 153 | |
7bb6fb8d DV |
154 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
155 | return -ENODEV; | |
156 | ||
2021746e CW |
157 | if (args->gtt_start >= args->gtt_end || |
158 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
159 | return -EINVAL; | |
79e53945 | 160 | |
f534bc0b DV |
161 | /* GEM with user mode setting was never supported on ilk and later. */ |
162 | if (INTEL_INFO(dev)->gen >= 5) | |
163 | return -ENODEV; | |
164 | ||
79e53945 | 165 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
166 | i915_gem_init_global_gtt(dev, args->gtt_start, |
167 | args->gtt_end, args->gtt_end); | |
673a394b EA |
168 | mutex_unlock(&dev->struct_mutex); |
169 | ||
2021746e | 170 | return 0; |
673a394b EA |
171 | } |
172 | ||
5a125c3c EA |
173 | int |
174 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 175 | struct drm_file *file) |
5a125c3c | 176 | { |
73aa808f | 177 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 178 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
179 | struct drm_i915_gem_object *obj; |
180 | size_t pinned; | |
5a125c3c | 181 | |
6299f992 | 182 | pinned = 0; |
73aa808f | 183 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 184 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
185 | if (obj->pin_count) |
186 | pinned += obj->gtt_space->size; | |
73aa808f | 187 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 188 | |
6299f992 | 189 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 190 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 191 | |
5a125c3c EA |
192 | return 0; |
193 | } | |
194 | ||
ff72145b DA |
195 | static int |
196 | i915_gem_create(struct drm_file *file, | |
197 | struct drm_device *dev, | |
198 | uint64_t size, | |
199 | uint32_t *handle_p) | |
673a394b | 200 | { |
05394f39 | 201 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
202 | int ret; |
203 | u32 handle; | |
673a394b | 204 | |
ff72145b | 205 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
206 | if (size == 0) |
207 | return -EINVAL; | |
673a394b EA |
208 | |
209 | /* Allocate the new object */ | |
ff72145b | 210 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
211 | if (obj == NULL) |
212 | return -ENOMEM; | |
213 | ||
05394f39 | 214 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 215 | if (ret) { |
05394f39 CW |
216 | drm_gem_object_release(&obj->base); |
217 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 218 | kfree(obj); |
673a394b | 219 | return ret; |
1dfd9754 | 220 | } |
673a394b | 221 | |
202f2fef | 222 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 223 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
224 | trace_i915_gem_object_create(obj); |
225 | ||
ff72145b | 226 | *handle_p = handle; |
673a394b EA |
227 | return 0; |
228 | } | |
229 | ||
ff72145b DA |
230 | int |
231 | i915_gem_dumb_create(struct drm_file *file, | |
232 | struct drm_device *dev, | |
233 | struct drm_mode_create_dumb *args) | |
234 | { | |
235 | /* have to work out size/pitch and return them */ | |
ed0291fd | 236 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
237 | args->size = args->pitch * args->height; |
238 | return i915_gem_create(file, dev, | |
239 | args->size, &args->handle); | |
240 | } | |
241 | ||
242 | int i915_gem_dumb_destroy(struct drm_file *file, | |
243 | struct drm_device *dev, | |
244 | uint32_t handle) | |
245 | { | |
246 | return drm_gem_handle_delete(file, handle); | |
247 | } | |
248 | ||
249 | /** | |
250 | * Creates a new mm object and returns a handle to it. | |
251 | */ | |
252 | int | |
253 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
254 | struct drm_file *file) | |
255 | { | |
256 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 257 | |
ff72145b DA |
258 | return i915_gem_create(file, dev, |
259 | args->size, &args->handle); | |
260 | } | |
261 | ||
05394f39 | 262 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 263 | { |
05394f39 | 264 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
265 | |
266 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 267 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
268 | } |
269 | ||
8461d226 DV |
270 | static inline int |
271 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
272 | const char *gpu_vaddr, int gpu_offset, | |
273 | int length) | |
274 | { | |
275 | int ret, cpu_offset = 0; | |
276 | ||
277 | while (length > 0) { | |
278 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
279 | int this_length = min(cacheline_end - gpu_offset, length); | |
280 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
281 | ||
282 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
283 | gpu_vaddr + swizzled_gpu_offset, | |
284 | this_length); | |
285 | if (ret) | |
286 | return ret + length; | |
287 | ||
288 | cpu_offset += this_length; | |
289 | gpu_offset += this_length; | |
290 | length -= this_length; | |
291 | } | |
292 | ||
293 | return 0; | |
294 | } | |
295 | ||
8c59967c | 296 | static inline int |
4f0c7cfb BW |
297 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
298 | const char __user *cpu_vaddr, | |
8c59967c DV |
299 | int length) |
300 | { | |
301 | int ret, cpu_offset = 0; | |
302 | ||
303 | while (length > 0) { | |
304 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
305 | int this_length = min(cacheline_end - gpu_offset, length); | |
306 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
307 | ||
308 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
309 | cpu_vaddr + cpu_offset, | |
310 | this_length); | |
311 | if (ret) | |
312 | return ret + length; | |
313 | ||
314 | cpu_offset += this_length; | |
315 | gpu_offset += this_length; | |
316 | length -= this_length; | |
317 | } | |
318 | ||
319 | return 0; | |
320 | } | |
321 | ||
d174bd64 DV |
322 | /* Per-page copy function for the shmem pread fastpath. |
323 | * Flushes invalid cachelines before reading the target if | |
324 | * needs_clflush is set. */ | |
eb01459f | 325 | static int |
d174bd64 DV |
326 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
327 | char __user *user_data, | |
328 | bool page_do_bit17_swizzling, bool needs_clflush) | |
329 | { | |
330 | char *vaddr; | |
331 | int ret; | |
332 | ||
e7e58eb5 | 333 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
334 | return -EINVAL; |
335 | ||
336 | vaddr = kmap_atomic(page); | |
337 | if (needs_clflush) | |
338 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
339 | page_length); | |
340 | ret = __copy_to_user_inatomic(user_data, | |
341 | vaddr + shmem_page_offset, | |
342 | page_length); | |
343 | kunmap_atomic(vaddr); | |
344 | ||
f60d7f0c | 345 | return ret ? -EFAULT : 0; |
d174bd64 DV |
346 | } |
347 | ||
23c18c71 DV |
348 | static void |
349 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
350 | bool swizzled) | |
351 | { | |
e7e58eb5 | 352 | if (unlikely(swizzled)) { |
23c18c71 DV |
353 | unsigned long start = (unsigned long) addr; |
354 | unsigned long end = (unsigned long) addr + length; | |
355 | ||
356 | /* For swizzling simply ensure that we always flush both | |
357 | * channels. Lame, but simple and it works. Swizzled | |
358 | * pwrite/pread is far from a hotpath - current userspace | |
359 | * doesn't use it at all. */ | |
360 | start = round_down(start, 128); | |
361 | end = round_up(end, 128); | |
362 | ||
363 | drm_clflush_virt_range((void *)start, end - start); | |
364 | } else { | |
365 | drm_clflush_virt_range(addr, length); | |
366 | } | |
367 | ||
368 | } | |
369 | ||
d174bd64 DV |
370 | /* Only difference to the fast-path function is that this can handle bit17 |
371 | * and uses non-atomic copy and kmap functions. */ | |
372 | static int | |
373 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
374 | char __user *user_data, | |
375 | bool page_do_bit17_swizzling, bool needs_clflush) | |
376 | { | |
377 | char *vaddr; | |
378 | int ret; | |
379 | ||
380 | vaddr = kmap(page); | |
381 | if (needs_clflush) | |
23c18c71 DV |
382 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
383 | page_length, | |
384 | page_do_bit17_swizzling); | |
d174bd64 DV |
385 | |
386 | if (page_do_bit17_swizzling) | |
387 | ret = __copy_to_user_swizzled(user_data, | |
388 | vaddr, shmem_page_offset, | |
389 | page_length); | |
390 | else | |
391 | ret = __copy_to_user(user_data, | |
392 | vaddr + shmem_page_offset, | |
393 | page_length); | |
394 | kunmap(page); | |
395 | ||
f60d7f0c | 396 | return ret ? - EFAULT : 0; |
d174bd64 DV |
397 | } |
398 | ||
eb01459f | 399 | static int |
dbf7bff0 DV |
400 | i915_gem_shmem_pread(struct drm_device *dev, |
401 | struct drm_i915_gem_object *obj, | |
402 | struct drm_i915_gem_pread *args, | |
403 | struct drm_file *file) | |
eb01459f | 404 | { |
8461d226 | 405 | char __user *user_data; |
eb01459f | 406 | ssize_t remain; |
8461d226 | 407 | loff_t offset; |
eb2c0c81 | 408 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 409 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 410 | int hit_slowpath = 0; |
96d79b52 | 411 | int prefaulted = 0; |
8489731c | 412 | int needs_clflush = 0; |
9da3da66 CW |
413 | struct scatterlist *sg; |
414 | int i; | |
eb01459f | 415 | |
8461d226 | 416 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
417 | remain = args->size; |
418 | ||
8461d226 | 419 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 420 | |
8489731c DV |
421 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
422 | /* If we're not in the cpu read domain, set ourself into the gtt | |
423 | * read domain and manually flush cachelines (if required). This | |
424 | * optimizes for the case when the gpu will dirty the data | |
425 | * anyway again before the next pread happens. */ | |
426 | if (obj->cache_level == I915_CACHE_NONE) | |
427 | needs_clflush = 1; | |
6c085a72 CW |
428 | if (obj->gtt_space) { |
429 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
430 | if (ret) | |
431 | return ret; | |
432 | } | |
8489731c | 433 | } |
eb01459f | 434 | |
f60d7f0c CW |
435 | ret = i915_gem_object_get_pages(obj); |
436 | if (ret) | |
437 | return ret; | |
438 | ||
439 | i915_gem_object_pin_pages(obj); | |
440 | ||
8461d226 | 441 | offset = args->offset; |
eb01459f | 442 | |
9da3da66 | 443 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
444 | struct page *page; |
445 | ||
9da3da66 CW |
446 | if (i < offset >> PAGE_SHIFT) |
447 | continue; | |
448 | ||
449 | if (remain <= 0) | |
450 | break; | |
451 | ||
eb01459f EA |
452 | /* Operation in this page |
453 | * | |
eb01459f | 454 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
455 | * page_length = bytes to copy for this page |
456 | */ | |
c8cbbb8b | 457 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
458 | page_length = remain; |
459 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
460 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 461 | |
9da3da66 | 462 | page = sg_page(sg); |
8461d226 DV |
463 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
464 | (page_to_phys(page) & (1 << 17)) != 0; | |
465 | ||
d174bd64 DV |
466 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
467 | user_data, page_do_bit17_swizzling, | |
468 | needs_clflush); | |
469 | if (ret == 0) | |
470 | goto next_page; | |
dbf7bff0 DV |
471 | |
472 | hit_slowpath = 1; | |
dbf7bff0 DV |
473 | mutex_unlock(&dev->struct_mutex); |
474 | ||
96d79b52 | 475 | if (!prefaulted) { |
f56f821f | 476 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
477 | /* Userspace is tricking us, but we've already clobbered |
478 | * its pages with the prefault and promised to write the | |
479 | * data up to the first fault. Hence ignore any errors | |
480 | * and just continue. */ | |
481 | (void)ret; | |
482 | prefaulted = 1; | |
483 | } | |
eb01459f | 484 | |
d174bd64 DV |
485 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
486 | user_data, page_do_bit17_swizzling, | |
487 | needs_clflush); | |
eb01459f | 488 | |
dbf7bff0 | 489 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 490 | |
dbf7bff0 | 491 | next_page: |
e5281ccd | 492 | mark_page_accessed(page); |
e5281ccd | 493 | |
f60d7f0c | 494 | if (ret) |
8461d226 | 495 | goto out; |
8461d226 | 496 | |
eb01459f | 497 | remain -= page_length; |
8461d226 | 498 | user_data += page_length; |
eb01459f EA |
499 | offset += page_length; |
500 | } | |
501 | ||
4f27b75d | 502 | out: |
f60d7f0c CW |
503 | i915_gem_object_unpin_pages(obj); |
504 | ||
dbf7bff0 DV |
505 | if (hit_slowpath) { |
506 | /* Fixup: Kill any reinstated backing storage pages */ | |
507 | if (obj->madv == __I915_MADV_PURGED) | |
508 | i915_gem_object_truncate(obj); | |
509 | } | |
eb01459f EA |
510 | |
511 | return ret; | |
512 | } | |
513 | ||
673a394b EA |
514 | /** |
515 | * Reads data from the object referenced by handle. | |
516 | * | |
517 | * On error, the contents of *data are undefined. | |
518 | */ | |
519 | int | |
520 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 521 | struct drm_file *file) |
673a394b EA |
522 | { |
523 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 524 | struct drm_i915_gem_object *obj; |
35b62a89 | 525 | int ret = 0; |
673a394b | 526 | |
51311d0a CW |
527 | if (args->size == 0) |
528 | return 0; | |
529 | ||
530 | if (!access_ok(VERIFY_WRITE, | |
531 | (char __user *)(uintptr_t)args->data_ptr, | |
532 | args->size)) | |
533 | return -EFAULT; | |
534 | ||
4f27b75d | 535 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 536 | if (ret) |
4f27b75d | 537 | return ret; |
673a394b | 538 | |
05394f39 | 539 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 540 | if (&obj->base == NULL) { |
1d7cfea1 CW |
541 | ret = -ENOENT; |
542 | goto unlock; | |
4f27b75d | 543 | } |
673a394b | 544 | |
7dcd2499 | 545 | /* Bounds check source. */ |
05394f39 CW |
546 | if (args->offset > obj->base.size || |
547 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 548 | ret = -EINVAL; |
35b62a89 | 549 | goto out; |
ce9d419d CW |
550 | } |
551 | ||
1286ff73 DV |
552 | /* prime objects have no backing filp to GEM pread/pwrite |
553 | * pages from. | |
554 | */ | |
555 | if (!obj->base.filp) { | |
556 | ret = -EINVAL; | |
557 | goto out; | |
558 | } | |
559 | ||
db53a302 CW |
560 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
561 | ||
dbf7bff0 | 562 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 563 | |
35b62a89 | 564 | out: |
05394f39 | 565 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 566 | unlock: |
4f27b75d | 567 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 568 | return ret; |
673a394b EA |
569 | } |
570 | ||
0839ccb8 KP |
571 | /* This is the fast write path which cannot handle |
572 | * page faults in the source data | |
9b7530cc | 573 | */ |
0839ccb8 KP |
574 | |
575 | static inline int | |
576 | fast_user_write(struct io_mapping *mapping, | |
577 | loff_t page_base, int page_offset, | |
578 | char __user *user_data, | |
579 | int length) | |
9b7530cc | 580 | { |
4f0c7cfb BW |
581 | void __iomem *vaddr_atomic; |
582 | void *vaddr; | |
0839ccb8 | 583 | unsigned long unwritten; |
9b7530cc | 584 | |
3e4d3af5 | 585 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
586 | /* We can use the cpu mem copy function because this is X86. */ |
587 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
588 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 589 | user_data, length); |
3e4d3af5 | 590 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 591 | return unwritten; |
0839ccb8 KP |
592 | } |
593 | ||
3de09aa3 EA |
594 | /** |
595 | * This is the fast pwrite path, where we copy the data directly from the | |
596 | * user into the GTT, uncached. | |
597 | */ | |
673a394b | 598 | static int |
05394f39 CW |
599 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
600 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 601 | struct drm_i915_gem_pwrite *args, |
05394f39 | 602 | struct drm_file *file) |
673a394b | 603 | { |
0839ccb8 | 604 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 605 | ssize_t remain; |
0839ccb8 | 606 | loff_t offset, page_base; |
673a394b | 607 | char __user *user_data; |
935aaa69 DV |
608 | int page_offset, page_length, ret; |
609 | ||
86a1ee26 | 610 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
611 | if (ret) |
612 | goto out; | |
613 | ||
614 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
615 | if (ret) | |
616 | goto out_unpin; | |
617 | ||
618 | ret = i915_gem_object_put_fence(obj); | |
619 | if (ret) | |
620 | goto out_unpin; | |
673a394b EA |
621 | |
622 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
623 | remain = args->size; | |
673a394b | 624 | |
05394f39 | 625 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
626 | |
627 | while (remain > 0) { | |
628 | /* Operation in this page | |
629 | * | |
0839ccb8 KP |
630 | * page_base = page offset within aperture |
631 | * page_offset = offset within page | |
632 | * page_length = bytes to copy for this page | |
673a394b | 633 | */ |
c8cbbb8b CW |
634 | page_base = offset & PAGE_MASK; |
635 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
636 | page_length = remain; |
637 | if ((page_offset + remain) > PAGE_SIZE) | |
638 | page_length = PAGE_SIZE - page_offset; | |
639 | ||
0839ccb8 | 640 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
641 | * source page isn't available. Return the error and we'll |
642 | * retry in the slow path. | |
0839ccb8 | 643 | */ |
fbd5a26d | 644 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
645 | page_offset, user_data, page_length)) { |
646 | ret = -EFAULT; | |
647 | goto out_unpin; | |
648 | } | |
673a394b | 649 | |
0839ccb8 KP |
650 | remain -= page_length; |
651 | user_data += page_length; | |
652 | offset += page_length; | |
673a394b | 653 | } |
673a394b | 654 | |
935aaa69 DV |
655 | out_unpin: |
656 | i915_gem_object_unpin(obj); | |
657 | out: | |
3de09aa3 | 658 | return ret; |
673a394b EA |
659 | } |
660 | ||
d174bd64 DV |
661 | /* Per-page copy function for the shmem pwrite fastpath. |
662 | * Flushes invalid cachelines before writing to the target if | |
663 | * needs_clflush_before is set and flushes out any written cachelines after | |
664 | * writing if needs_clflush is set. */ | |
3043c60c | 665 | static int |
d174bd64 DV |
666 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
667 | char __user *user_data, | |
668 | bool page_do_bit17_swizzling, | |
669 | bool needs_clflush_before, | |
670 | bool needs_clflush_after) | |
673a394b | 671 | { |
d174bd64 | 672 | char *vaddr; |
673a394b | 673 | int ret; |
3de09aa3 | 674 | |
e7e58eb5 | 675 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 676 | return -EINVAL; |
3de09aa3 | 677 | |
d174bd64 DV |
678 | vaddr = kmap_atomic(page); |
679 | if (needs_clflush_before) | |
680 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
681 | page_length); | |
682 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
683 | user_data, | |
684 | page_length); | |
685 | if (needs_clflush_after) | |
686 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
687 | page_length); | |
688 | kunmap_atomic(vaddr); | |
3de09aa3 | 689 | |
755d2218 | 690 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
691 | } |
692 | ||
d174bd64 DV |
693 | /* Only difference to the fast-path function is that this can handle bit17 |
694 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 695 | static int |
d174bd64 DV |
696 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
697 | char __user *user_data, | |
698 | bool page_do_bit17_swizzling, | |
699 | bool needs_clflush_before, | |
700 | bool needs_clflush_after) | |
673a394b | 701 | { |
d174bd64 DV |
702 | char *vaddr; |
703 | int ret; | |
e5281ccd | 704 | |
d174bd64 | 705 | vaddr = kmap(page); |
e7e58eb5 | 706 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
707 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
708 | page_length, | |
709 | page_do_bit17_swizzling); | |
d174bd64 DV |
710 | if (page_do_bit17_swizzling) |
711 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
712 | user_data, |
713 | page_length); | |
d174bd64 DV |
714 | else |
715 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
716 | user_data, | |
717 | page_length); | |
718 | if (needs_clflush_after) | |
23c18c71 DV |
719 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
720 | page_length, | |
721 | page_do_bit17_swizzling); | |
d174bd64 | 722 | kunmap(page); |
40123c1f | 723 | |
755d2218 | 724 | return ret ? -EFAULT : 0; |
40123c1f EA |
725 | } |
726 | ||
40123c1f | 727 | static int |
e244a443 DV |
728 | i915_gem_shmem_pwrite(struct drm_device *dev, |
729 | struct drm_i915_gem_object *obj, | |
730 | struct drm_i915_gem_pwrite *args, | |
731 | struct drm_file *file) | |
40123c1f | 732 | { |
40123c1f | 733 | ssize_t remain; |
8c59967c DV |
734 | loff_t offset; |
735 | char __user *user_data; | |
eb2c0c81 | 736 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 737 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 738 | int hit_slowpath = 0; |
58642885 DV |
739 | int needs_clflush_after = 0; |
740 | int needs_clflush_before = 0; | |
9da3da66 CW |
741 | int i; |
742 | struct scatterlist *sg; | |
40123c1f | 743 | |
8c59967c | 744 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
745 | remain = args->size; |
746 | ||
8c59967c | 747 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 748 | |
58642885 DV |
749 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
750 | /* If we're not in the cpu write domain, set ourself into the gtt | |
751 | * write domain and manually flush cachelines (if required). This | |
752 | * optimizes for the case when the gpu will use the data | |
753 | * right away and we therefore have to clflush anyway. */ | |
754 | if (obj->cache_level == I915_CACHE_NONE) | |
755 | needs_clflush_after = 1; | |
6c085a72 CW |
756 | if (obj->gtt_space) { |
757 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
758 | if (ret) | |
759 | return ret; | |
760 | } | |
58642885 DV |
761 | } |
762 | /* Same trick applies for invalidate partially written cachelines before | |
763 | * writing. */ | |
764 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
765 | && obj->cache_level == I915_CACHE_NONE) | |
766 | needs_clflush_before = 1; | |
767 | ||
755d2218 CW |
768 | ret = i915_gem_object_get_pages(obj); |
769 | if (ret) | |
770 | return ret; | |
771 | ||
772 | i915_gem_object_pin_pages(obj); | |
773 | ||
673a394b | 774 | offset = args->offset; |
05394f39 | 775 | obj->dirty = 1; |
673a394b | 776 | |
9da3da66 | 777 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 778 | struct page *page; |
58642885 | 779 | int partial_cacheline_write; |
e5281ccd | 780 | |
9da3da66 CW |
781 | if (i < offset >> PAGE_SHIFT) |
782 | continue; | |
783 | ||
784 | if (remain <= 0) | |
785 | break; | |
786 | ||
40123c1f EA |
787 | /* Operation in this page |
788 | * | |
40123c1f | 789 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
790 | * page_length = bytes to copy for this page |
791 | */ | |
c8cbbb8b | 792 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
793 | |
794 | page_length = remain; | |
795 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
796 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 797 | |
58642885 DV |
798 | /* If we don't overwrite a cacheline completely we need to be |
799 | * careful to have up-to-date data by first clflushing. Don't | |
800 | * overcomplicate things and flush the entire patch. */ | |
801 | partial_cacheline_write = needs_clflush_before && | |
802 | ((shmem_page_offset | page_length) | |
803 | & (boot_cpu_data.x86_clflush_size - 1)); | |
804 | ||
9da3da66 | 805 | page = sg_page(sg); |
8c59967c DV |
806 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
807 | (page_to_phys(page) & (1 << 17)) != 0; | |
808 | ||
d174bd64 DV |
809 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
810 | user_data, page_do_bit17_swizzling, | |
811 | partial_cacheline_write, | |
812 | needs_clflush_after); | |
813 | if (ret == 0) | |
814 | goto next_page; | |
e244a443 DV |
815 | |
816 | hit_slowpath = 1; | |
e244a443 | 817 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
818 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
819 | user_data, page_do_bit17_swizzling, | |
820 | partial_cacheline_write, | |
821 | needs_clflush_after); | |
40123c1f | 822 | |
e244a443 | 823 | mutex_lock(&dev->struct_mutex); |
755d2218 | 824 | |
e244a443 | 825 | next_page: |
e5281ccd CW |
826 | set_page_dirty(page); |
827 | mark_page_accessed(page); | |
e5281ccd | 828 | |
755d2218 | 829 | if (ret) |
8c59967c | 830 | goto out; |
8c59967c | 831 | |
40123c1f | 832 | remain -= page_length; |
8c59967c | 833 | user_data += page_length; |
40123c1f | 834 | offset += page_length; |
673a394b EA |
835 | } |
836 | ||
fbd5a26d | 837 | out: |
755d2218 CW |
838 | i915_gem_object_unpin_pages(obj); |
839 | ||
e244a443 DV |
840 | if (hit_slowpath) { |
841 | /* Fixup: Kill any reinstated backing storage pages */ | |
842 | if (obj->madv == __I915_MADV_PURGED) | |
843 | i915_gem_object_truncate(obj); | |
844 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
845 | * domain anymore. */ | |
846 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
847 | i915_gem_clflush_object(obj); | |
e76e9aeb | 848 | i915_gem_chipset_flush(dev); |
e244a443 | 849 | } |
8c59967c | 850 | } |
673a394b | 851 | |
58642885 | 852 | if (needs_clflush_after) |
e76e9aeb | 853 | i915_gem_chipset_flush(dev); |
58642885 | 854 | |
40123c1f | 855 | return ret; |
673a394b EA |
856 | } |
857 | ||
858 | /** | |
859 | * Writes data to the object referenced by handle. | |
860 | * | |
861 | * On error, the contents of the buffer that were to be modified are undefined. | |
862 | */ | |
863 | int | |
864 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 865 | struct drm_file *file) |
673a394b EA |
866 | { |
867 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 868 | struct drm_i915_gem_object *obj; |
51311d0a CW |
869 | int ret; |
870 | ||
871 | if (args->size == 0) | |
872 | return 0; | |
873 | ||
874 | if (!access_ok(VERIFY_READ, | |
875 | (char __user *)(uintptr_t)args->data_ptr, | |
876 | args->size)) | |
877 | return -EFAULT; | |
878 | ||
f56f821f DV |
879 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
880 | args->size); | |
51311d0a CW |
881 | if (ret) |
882 | return -EFAULT; | |
673a394b | 883 | |
fbd5a26d | 884 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 885 | if (ret) |
fbd5a26d | 886 | return ret; |
1d7cfea1 | 887 | |
05394f39 | 888 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 889 | if (&obj->base == NULL) { |
1d7cfea1 CW |
890 | ret = -ENOENT; |
891 | goto unlock; | |
fbd5a26d | 892 | } |
673a394b | 893 | |
7dcd2499 | 894 | /* Bounds check destination. */ |
05394f39 CW |
895 | if (args->offset > obj->base.size || |
896 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 897 | ret = -EINVAL; |
35b62a89 | 898 | goto out; |
ce9d419d CW |
899 | } |
900 | ||
1286ff73 DV |
901 | /* prime objects have no backing filp to GEM pread/pwrite |
902 | * pages from. | |
903 | */ | |
904 | if (!obj->base.filp) { | |
905 | ret = -EINVAL; | |
906 | goto out; | |
907 | } | |
908 | ||
db53a302 CW |
909 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
910 | ||
935aaa69 | 911 | ret = -EFAULT; |
673a394b EA |
912 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
913 | * it would end up going through the fenced access, and we'll get | |
914 | * different detiling behavior between reading and writing. | |
915 | * pread/pwrite currently are reading and writing from the CPU | |
916 | * perspective, requiring manual detiling by the client. | |
917 | */ | |
5c0480f2 | 918 | if (obj->phys_obj) { |
fbd5a26d | 919 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
920 | goto out; |
921 | } | |
922 | ||
86a1ee26 | 923 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 924 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 925 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 926 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
927 | /* Note that the gtt paths might fail with non-page-backed user |
928 | * pointers (e.g. gtt mappings when moving data between | |
929 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 930 | } |
673a394b | 931 | |
86a1ee26 | 932 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 933 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 934 | |
35b62a89 | 935 | out: |
05394f39 | 936 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 937 | unlock: |
fbd5a26d | 938 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
939 | return ret; |
940 | } | |
941 | ||
b361237b CW |
942 | int |
943 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
944 | bool interruptible) | |
945 | { | |
946 | if (atomic_read(&dev_priv->mm.wedged)) { | |
947 | struct completion *x = &dev_priv->error_completion; | |
948 | bool recovery_complete; | |
949 | unsigned long flags; | |
950 | ||
951 | /* Give the error handler a chance to run. */ | |
952 | spin_lock_irqsave(&x->wait.lock, flags); | |
953 | recovery_complete = x->done > 0; | |
954 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
955 | ||
956 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
957 | * -EIO unconditionally for these. */ | |
958 | if (!interruptible) | |
959 | return -EIO; | |
960 | ||
961 | /* Recovery complete, but still wedged means reset failure. */ | |
962 | if (recovery_complete) | |
963 | return -EIO; | |
964 | ||
965 | return -EAGAIN; | |
966 | } | |
967 | ||
968 | return 0; | |
969 | } | |
970 | ||
971 | /* | |
972 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
973 | * equal. | |
974 | */ | |
975 | static int | |
976 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
977 | { | |
978 | int ret; | |
979 | ||
980 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
981 | ||
982 | ret = 0; | |
983 | if (seqno == ring->outstanding_lazy_request) | |
984 | ret = i915_add_request(ring, NULL, NULL); | |
985 | ||
986 | return ret; | |
987 | } | |
988 | ||
989 | /** | |
990 | * __wait_seqno - wait until execution of seqno has finished | |
991 | * @ring: the ring expected to report seqno | |
992 | * @seqno: duh! | |
993 | * @interruptible: do an interruptible wait (normally yes) | |
994 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
995 | * | |
996 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
997 | * errno with remaining time filled in timeout argument. | |
998 | */ | |
999 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
1000 | bool interruptible, struct timespec *timeout) | |
1001 | { | |
1002 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1003 | struct timespec before, now, wait_time={1,0}; | |
1004 | unsigned long timeout_jiffies; | |
1005 | long end; | |
1006 | bool wait_forever = true; | |
1007 | int ret; | |
1008 | ||
1009 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1010 | return 0; | |
1011 | ||
1012 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1013 | ||
1014 | if (timeout != NULL) { | |
1015 | wait_time = *timeout; | |
1016 | wait_forever = false; | |
1017 | } | |
1018 | ||
1019 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1020 | ||
1021 | if (WARN_ON(!ring->irq_get(ring))) | |
1022 | return -ENODEV; | |
1023 | ||
1024 | /* Record current time in case interrupted by signal, or wedged * */ | |
1025 | getrawmonotonic(&before); | |
1026 | ||
1027 | #define EXIT_COND \ | |
1028 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1029 | atomic_read(&dev_priv->mm.wedged)) | |
1030 | do { | |
1031 | if (interruptible) | |
1032 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1033 | EXIT_COND, | |
1034 | timeout_jiffies); | |
1035 | else | |
1036 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1037 | timeout_jiffies); | |
1038 | ||
1039 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1040 | if (ret) | |
1041 | end = ret; | |
1042 | } while (end == 0 && wait_forever); | |
1043 | ||
1044 | getrawmonotonic(&now); | |
1045 | ||
1046 | ring->irq_put(ring); | |
1047 | trace_i915_gem_request_wait_end(ring, seqno); | |
1048 | #undef EXIT_COND | |
1049 | ||
1050 | if (timeout) { | |
1051 | struct timespec sleep_time = timespec_sub(now, before); | |
1052 | *timeout = timespec_sub(*timeout, sleep_time); | |
1053 | } | |
1054 | ||
1055 | switch (end) { | |
1056 | case -EIO: | |
1057 | case -EAGAIN: /* Wedged */ | |
1058 | case -ERESTARTSYS: /* Signal */ | |
1059 | return (int)end; | |
1060 | case 0: /* Timeout */ | |
1061 | if (timeout) | |
1062 | set_normalized_timespec(timeout, 0, 0); | |
1063 | return -ETIME; | |
1064 | default: /* Completed */ | |
1065 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1066 | return 0; | |
1067 | } | |
1068 | } | |
1069 | ||
1070 | /** | |
1071 | * Waits for a sequence number to be signaled, and cleans up the | |
1072 | * request and object lists appropriately for that event. | |
1073 | */ | |
1074 | int | |
1075 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1076 | { | |
1077 | struct drm_device *dev = ring->dev; | |
1078 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1079 | bool interruptible = dev_priv->mm.interruptible; | |
1080 | int ret; | |
1081 | ||
1082 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1083 | BUG_ON(seqno == 0); | |
1084 | ||
1085 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1086 | if (ret) | |
1087 | return ret; | |
1088 | ||
1089 | ret = i915_gem_check_olr(ring, seqno); | |
1090 | if (ret) | |
1091 | return ret; | |
1092 | ||
1093 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1094 | } | |
1095 | ||
1096 | /** | |
1097 | * Ensures that all rendering to the object has completed and the object is | |
1098 | * safe to unbind from the GTT or access from the CPU. | |
1099 | */ | |
1100 | static __must_check int | |
1101 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1102 | bool readonly) | |
1103 | { | |
1104 | struct intel_ring_buffer *ring = obj->ring; | |
1105 | u32 seqno; | |
1106 | int ret; | |
1107 | ||
1108 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1109 | if (seqno == 0) | |
1110 | return 0; | |
1111 | ||
1112 | ret = i915_wait_seqno(ring, seqno); | |
1113 | if (ret) | |
1114 | return ret; | |
1115 | ||
1116 | i915_gem_retire_requests_ring(ring); | |
1117 | ||
1118 | /* Manually manage the write flush as we may have not yet | |
1119 | * retired the buffer. | |
1120 | */ | |
1121 | if (obj->last_write_seqno && | |
1122 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1123 | obj->last_write_seqno = 0; | |
1124 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1125 | } | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
3236f57a CW |
1130 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1131 | * as the object state may change during this call. | |
1132 | */ | |
1133 | static __must_check int | |
1134 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1135 | bool readonly) | |
1136 | { | |
1137 | struct drm_device *dev = obj->base.dev; | |
1138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1139 | struct intel_ring_buffer *ring = obj->ring; | |
1140 | u32 seqno; | |
1141 | int ret; | |
1142 | ||
1143 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1144 | BUG_ON(!dev_priv->mm.interruptible); | |
1145 | ||
1146 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1147 | if (seqno == 0) | |
1148 | return 0; | |
1149 | ||
1150 | ret = i915_gem_check_wedge(dev_priv, true); | |
1151 | if (ret) | |
1152 | return ret; | |
1153 | ||
1154 | ret = i915_gem_check_olr(ring, seqno); | |
1155 | if (ret) | |
1156 | return ret; | |
1157 | ||
1158 | mutex_unlock(&dev->struct_mutex); | |
1159 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1160 | mutex_lock(&dev->struct_mutex); | |
1161 | ||
1162 | i915_gem_retire_requests_ring(ring); | |
1163 | ||
1164 | /* Manually manage the write flush as we may have not yet | |
1165 | * retired the buffer. | |
1166 | */ | |
1167 | if (obj->last_write_seqno && | |
1168 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1169 | obj->last_write_seqno = 0; | |
1170 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1171 | } | |
1172 | ||
1173 | return ret; | |
1174 | } | |
1175 | ||
673a394b | 1176 | /** |
2ef7eeaa EA |
1177 | * Called when user space prepares to use an object with the CPU, either |
1178 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1179 | */ |
1180 | int | |
1181 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1182 | struct drm_file *file) |
673a394b EA |
1183 | { |
1184 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1185 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1186 | uint32_t read_domains = args->read_domains; |
1187 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1188 | int ret; |
1189 | ||
2ef7eeaa | 1190 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1191 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1192 | return -EINVAL; |
1193 | ||
21d509e3 | 1194 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1195 | return -EINVAL; |
1196 | ||
1197 | /* Having something in the write domain implies it's in the read | |
1198 | * domain, and only that read domain. Enforce that in the request. | |
1199 | */ | |
1200 | if (write_domain != 0 && read_domains != write_domain) | |
1201 | return -EINVAL; | |
1202 | ||
76c1dec1 | 1203 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1204 | if (ret) |
76c1dec1 | 1205 | return ret; |
1d7cfea1 | 1206 | |
05394f39 | 1207 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1208 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1209 | ret = -ENOENT; |
1210 | goto unlock; | |
76c1dec1 | 1211 | } |
673a394b | 1212 | |
3236f57a CW |
1213 | /* Try to flush the object off the GPU without holding the lock. |
1214 | * We will repeat the flush holding the lock in the normal manner | |
1215 | * to catch cases where we are gazumped. | |
1216 | */ | |
1217 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1218 | if (ret) | |
1219 | goto unref; | |
1220 | ||
2ef7eeaa EA |
1221 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1222 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1223 | |
1224 | /* Silently promote "you're not bound, there was nothing to do" | |
1225 | * to success, since the client was just asking us to | |
1226 | * make sure everything was done. | |
1227 | */ | |
1228 | if (ret == -EINVAL) | |
1229 | ret = 0; | |
2ef7eeaa | 1230 | } else { |
e47c68e9 | 1231 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1232 | } |
1233 | ||
3236f57a | 1234 | unref: |
05394f39 | 1235 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1236 | unlock: |
673a394b EA |
1237 | mutex_unlock(&dev->struct_mutex); |
1238 | return ret; | |
1239 | } | |
1240 | ||
1241 | /** | |
1242 | * Called when user space has done writes to this buffer | |
1243 | */ | |
1244 | int | |
1245 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1246 | struct drm_file *file) |
673a394b EA |
1247 | { |
1248 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1249 | struct drm_i915_gem_object *obj; |
673a394b EA |
1250 | int ret = 0; |
1251 | ||
76c1dec1 | 1252 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1253 | if (ret) |
76c1dec1 | 1254 | return ret; |
1d7cfea1 | 1255 | |
05394f39 | 1256 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1257 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1258 | ret = -ENOENT; |
1259 | goto unlock; | |
673a394b EA |
1260 | } |
1261 | ||
673a394b | 1262 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1263 | if (obj->pin_count) |
e47c68e9 EA |
1264 | i915_gem_object_flush_cpu_write_domain(obj); |
1265 | ||
05394f39 | 1266 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1267 | unlock: |
673a394b EA |
1268 | mutex_unlock(&dev->struct_mutex); |
1269 | return ret; | |
1270 | } | |
1271 | ||
1272 | /** | |
1273 | * Maps the contents of an object, returning the address it is mapped | |
1274 | * into. | |
1275 | * | |
1276 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1277 | * imply a ref on the object itself. | |
1278 | */ | |
1279 | int | |
1280 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1281 | struct drm_file *file) |
673a394b EA |
1282 | { |
1283 | struct drm_i915_gem_mmap *args = data; | |
1284 | struct drm_gem_object *obj; | |
673a394b EA |
1285 | unsigned long addr; |
1286 | ||
05394f39 | 1287 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1288 | if (obj == NULL) |
bf79cb91 | 1289 | return -ENOENT; |
673a394b | 1290 | |
1286ff73 DV |
1291 | /* prime objects have no backing filp to GEM mmap |
1292 | * pages from. | |
1293 | */ | |
1294 | if (!obj->filp) { | |
1295 | drm_gem_object_unreference_unlocked(obj); | |
1296 | return -EINVAL; | |
1297 | } | |
1298 | ||
6be5ceb0 | 1299 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1300 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1301 | args->offset); | |
bc9025bd | 1302 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1303 | if (IS_ERR((void *)addr)) |
1304 | return addr; | |
1305 | ||
1306 | args->addr_ptr = (uint64_t) addr; | |
1307 | ||
1308 | return 0; | |
1309 | } | |
1310 | ||
de151cf6 JB |
1311 | /** |
1312 | * i915_gem_fault - fault a page into the GTT | |
1313 | * vma: VMA in question | |
1314 | * vmf: fault info | |
1315 | * | |
1316 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1317 | * from userspace. The fault handler takes care of binding the object to | |
1318 | * the GTT (if needed), allocating and programming a fence register (again, | |
1319 | * only if needed based on whether the old reg is still valid or the object | |
1320 | * is tiled) and inserting a new PTE into the faulting process. | |
1321 | * | |
1322 | * Note that the faulting process may involve evicting existing objects | |
1323 | * from the GTT and/or fence registers to make room. So performance may | |
1324 | * suffer if the GTT working set is large or there are few fence registers | |
1325 | * left. | |
1326 | */ | |
1327 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1328 | { | |
05394f39 CW |
1329 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1330 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1331 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1332 | pgoff_t page_offset; |
1333 | unsigned long pfn; | |
1334 | int ret = 0; | |
0f973f27 | 1335 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1336 | |
1337 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1338 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1339 | PAGE_SHIFT; | |
1340 | ||
d9bc7e9f CW |
1341 | ret = i915_mutex_lock_interruptible(dev); |
1342 | if (ret) | |
1343 | goto out; | |
a00b10c3 | 1344 | |
db53a302 CW |
1345 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1346 | ||
d9bc7e9f | 1347 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1348 | ret = i915_gem_object_pin(obj, 0, true, false); |
1349 | if (ret) | |
1350 | goto unlock; | |
4a684a41 | 1351 | |
c9839303 CW |
1352 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1353 | if (ret) | |
1354 | goto unpin; | |
74898d7e | 1355 | |
06d98131 | 1356 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1357 | if (ret) |
c9839303 | 1358 | goto unpin; |
7d1c4804 | 1359 | |
6299f992 CW |
1360 | obj->fault_mappable = true; |
1361 | ||
dd2757f8 | 1362 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1363 | page_offset; |
1364 | ||
1365 | /* Finally, remap it using the new GTT offset */ | |
1366 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1367 | unpin: |
1368 | i915_gem_object_unpin(obj); | |
c715089f | 1369 | unlock: |
de151cf6 | 1370 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1371 | out: |
de151cf6 | 1372 | switch (ret) { |
d9bc7e9f | 1373 | case -EIO: |
a9340cca DV |
1374 | /* If this -EIO is due to a gpu hang, give the reset code a |
1375 | * chance to clean up the mess. Otherwise return the proper | |
1376 | * SIGBUS. */ | |
1377 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1378 | return VM_FAULT_SIGBUS; | |
045e769a | 1379 | case -EAGAIN: |
d9bc7e9f CW |
1380 | /* Give the error handler a chance to run and move the |
1381 | * objects off the GPU active list. Next time we service the | |
1382 | * fault, we should be able to transition the page into the | |
1383 | * GTT without touching the GPU (and so avoid further | |
1384 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1385 | * with coherency, just lost writes. | |
1386 | */ | |
045e769a | 1387 | set_need_resched(); |
c715089f CW |
1388 | case 0: |
1389 | case -ERESTARTSYS: | |
bed636ab | 1390 | case -EINTR: |
e79e0fe3 DR |
1391 | case -EBUSY: |
1392 | /* | |
1393 | * EBUSY is ok: this just means that another thread | |
1394 | * already did the job. | |
1395 | */ | |
c715089f | 1396 | return VM_FAULT_NOPAGE; |
de151cf6 | 1397 | case -ENOMEM: |
de151cf6 | 1398 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1399 | case -ENOSPC: |
1400 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1401 | default: |
a7c2e1aa | 1402 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1403 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1404 | } |
1405 | } | |
1406 | ||
901782b2 CW |
1407 | /** |
1408 | * i915_gem_release_mmap - remove physical page mappings | |
1409 | * @obj: obj in question | |
1410 | * | |
af901ca1 | 1411 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1412 | * relinquish ownership of the pages back to the system. |
1413 | * | |
1414 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1415 | * object through the GTT and then lose the fence register due to | |
1416 | * resource pressure. Similarly if the object has been moved out of the | |
1417 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1418 | * mapping will then trigger a page fault on the next user access, allowing | |
1419 | * fixup by i915_gem_fault(). | |
1420 | */ | |
d05ca301 | 1421 | void |
05394f39 | 1422 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1423 | { |
6299f992 CW |
1424 | if (!obj->fault_mappable) |
1425 | return; | |
901782b2 | 1426 | |
f6e47884 CW |
1427 | if (obj->base.dev->dev_mapping) |
1428 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1429 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1430 | obj->base.size, 1); | |
fb7d516a | 1431 | |
6299f992 | 1432 | obj->fault_mappable = false; |
901782b2 CW |
1433 | } |
1434 | ||
92b88aeb | 1435 | static uint32_t |
e28f8711 | 1436 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1437 | { |
e28f8711 | 1438 | uint32_t gtt_size; |
92b88aeb CW |
1439 | |
1440 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1441 | tiling_mode == I915_TILING_NONE) |
1442 | return size; | |
92b88aeb CW |
1443 | |
1444 | /* Previous chips need a power-of-two fence region when tiling */ | |
1445 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1446 | gtt_size = 1024*1024; |
92b88aeb | 1447 | else |
e28f8711 | 1448 | gtt_size = 512*1024; |
92b88aeb | 1449 | |
e28f8711 CW |
1450 | while (gtt_size < size) |
1451 | gtt_size <<= 1; | |
92b88aeb | 1452 | |
e28f8711 | 1453 | return gtt_size; |
92b88aeb CW |
1454 | } |
1455 | ||
de151cf6 JB |
1456 | /** |
1457 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1458 | * @obj: object to check | |
1459 | * | |
1460 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1461 | * potential fence register mapping. |
de151cf6 JB |
1462 | */ |
1463 | static uint32_t | |
e28f8711 CW |
1464 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1465 | uint32_t size, | |
1466 | int tiling_mode) | |
de151cf6 | 1467 | { |
de151cf6 JB |
1468 | /* |
1469 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1470 | * if a fence register is needed for the object. | |
1471 | */ | |
a00b10c3 | 1472 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1473 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1474 | return 4096; |
1475 | ||
a00b10c3 CW |
1476 | /* |
1477 | * Previous chips need to be aligned to the size of the smallest | |
1478 | * fence register that can contain the object. | |
1479 | */ | |
e28f8711 | 1480 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1481 | } |
1482 | ||
5e783301 DV |
1483 | /** |
1484 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1485 | * unfenced object | |
e28f8711 CW |
1486 | * @dev: the device |
1487 | * @size: size of the object | |
1488 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1489 | * |
1490 | * Return the required GTT alignment for an object, only taking into account | |
1491 | * unfenced tiled surface requirements. | |
1492 | */ | |
467cffba | 1493 | uint32_t |
e28f8711 CW |
1494 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1495 | uint32_t size, | |
1496 | int tiling_mode) | |
5e783301 | 1497 | { |
5e783301 DV |
1498 | /* |
1499 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1500 | */ | |
1501 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1502 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1503 | return 4096; |
1504 | ||
e28f8711 CW |
1505 | /* Previous hardware however needs to be aligned to a power-of-two |
1506 | * tile height. The simplest method for determining this is to reuse | |
1507 | * the power-of-tile object size. | |
5e783301 | 1508 | */ |
e28f8711 | 1509 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1510 | } |
1511 | ||
d8cb5086 CW |
1512 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1513 | { | |
1514 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1515 | int ret; | |
1516 | ||
1517 | if (obj->base.map_list.map) | |
1518 | return 0; | |
1519 | ||
1520 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1521 | if (ret != -ENOSPC) | |
1522 | return ret; | |
1523 | ||
1524 | /* Badly fragmented mmap space? The only way we can recover | |
1525 | * space is by destroying unwanted objects. We can't randomly release | |
1526 | * mmap_offsets as userspace expects them to be persistent for the | |
1527 | * lifetime of the objects. The closest we can is to release the | |
1528 | * offsets on purgeable objects by truncating it and marking it purged, | |
1529 | * which prevents userspace from ever using that object again. | |
1530 | */ | |
1531 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1532 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1533 | if (ret != -ENOSPC) | |
1534 | return ret; | |
1535 | ||
1536 | i915_gem_shrink_all(dev_priv); | |
1537 | return drm_gem_create_mmap_offset(&obj->base); | |
1538 | } | |
1539 | ||
1540 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1541 | { | |
1542 | if (!obj->base.map_list.map) | |
1543 | return; | |
1544 | ||
1545 | drm_gem_free_mmap_offset(&obj->base); | |
1546 | } | |
1547 | ||
de151cf6 | 1548 | int |
ff72145b DA |
1549 | i915_gem_mmap_gtt(struct drm_file *file, |
1550 | struct drm_device *dev, | |
1551 | uint32_t handle, | |
1552 | uint64_t *offset) | |
de151cf6 | 1553 | { |
da761a6e | 1554 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1555 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1556 | int ret; |
1557 | ||
76c1dec1 | 1558 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1559 | if (ret) |
76c1dec1 | 1560 | return ret; |
de151cf6 | 1561 | |
ff72145b | 1562 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1563 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1564 | ret = -ENOENT; |
1565 | goto unlock; | |
1566 | } | |
de151cf6 | 1567 | |
05394f39 | 1568 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1569 | ret = -E2BIG; |
ff56b0bc | 1570 | goto out; |
da761a6e CW |
1571 | } |
1572 | ||
05394f39 | 1573 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1574 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1575 | ret = -EINVAL; |
1576 | goto out; | |
ab18282d CW |
1577 | } |
1578 | ||
d8cb5086 CW |
1579 | ret = i915_gem_object_create_mmap_offset(obj); |
1580 | if (ret) | |
1581 | goto out; | |
de151cf6 | 1582 | |
ff72145b | 1583 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1584 | |
1d7cfea1 | 1585 | out: |
05394f39 | 1586 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1587 | unlock: |
de151cf6 | 1588 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1589 | return ret; |
de151cf6 JB |
1590 | } |
1591 | ||
ff72145b DA |
1592 | /** |
1593 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1594 | * @dev: DRM device | |
1595 | * @data: GTT mapping ioctl data | |
1596 | * @file: GEM object info | |
1597 | * | |
1598 | * Simply returns the fake offset to userspace so it can mmap it. | |
1599 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1600 | * up so we can get faults in the handler above. | |
1601 | * | |
1602 | * The fault handler will take care of binding the object into the GTT | |
1603 | * (since it may have been evicted to make room for something), allocating | |
1604 | * a fence register, and mapping the appropriate aperture address into | |
1605 | * userspace. | |
1606 | */ | |
1607 | int | |
1608 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1609 | struct drm_file *file) | |
1610 | { | |
1611 | struct drm_i915_gem_mmap_gtt *args = data; | |
1612 | ||
ff72145b DA |
1613 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1614 | } | |
1615 | ||
225067ee DV |
1616 | /* Immediately discard the backing storage */ |
1617 | static void | |
1618 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1619 | { |
e5281ccd | 1620 | struct inode *inode; |
e5281ccd | 1621 | |
4d6294bf | 1622 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1623 | |
4d6294bf CW |
1624 | if (obj->base.filp == NULL) |
1625 | return; | |
e5281ccd | 1626 | |
225067ee DV |
1627 | /* Our goal here is to return as much of the memory as |
1628 | * is possible back to the system as we are called from OOM. | |
1629 | * To do this we must instruct the shmfs to drop all of its | |
1630 | * backing pages, *now*. | |
1631 | */ | |
05394f39 | 1632 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1633 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1634 | |
225067ee DV |
1635 | obj->madv = __I915_MADV_PURGED; |
1636 | } | |
e5281ccd | 1637 | |
225067ee DV |
1638 | static inline int |
1639 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1640 | { | |
1641 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1642 | } |
1643 | ||
5cdf5881 | 1644 | static void |
05394f39 | 1645 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1646 | { |
05394f39 | 1647 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1648 | struct scatterlist *sg; |
6c085a72 | 1649 | int ret, i; |
1286ff73 | 1650 | |
05394f39 | 1651 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1652 | |
6c085a72 CW |
1653 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1654 | if (ret) { | |
1655 | /* In the event of a disaster, abandon all caches and | |
1656 | * hope for the best. | |
1657 | */ | |
1658 | WARN_ON(ret != -EIO); | |
1659 | i915_gem_clflush_object(obj); | |
1660 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1661 | } | |
1662 | ||
6dacfd2f | 1663 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1664 | i915_gem_object_save_bit_17_swizzle(obj); |
1665 | ||
05394f39 CW |
1666 | if (obj->madv == I915_MADV_DONTNEED) |
1667 | obj->dirty = 0; | |
3ef94daa | 1668 | |
9da3da66 CW |
1669 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1670 | struct page *page = sg_page(sg); | |
1671 | ||
05394f39 | 1672 | if (obj->dirty) |
9da3da66 | 1673 | set_page_dirty(page); |
3ef94daa | 1674 | |
05394f39 | 1675 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1676 | mark_page_accessed(page); |
3ef94daa | 1677 | |
9da3da66 | 1678 | page_cache_release(page); |
3ef94daa | 1679 | } |
05394f39 | 1680 | obj->dirty = 0; |
673a394b | 1681 | |
9da3da66 CW |
1682 | sg_free_table(obj->pages); |
1683 | kfree(obj->pages); | |
37e680a1 | 1684 | } |
6c085a72 | 1685 | |
37e680a1 CW |
1686 | static int |
1687 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) | |
1688 | { | |
1689 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1690 | ||
2f745ad3 | 1691 | if (obj->pages == NULL) |
37e680a1 CW |
1692 | return 0; |
1693 | ||
1694 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1695 | |
a5570178 CW |
1696 | if (obj->pages_pin_count) |
1697 | return -EBUSY; | |
1698 | ||
a2165e31 CW |
1699 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1700 | * array, hence protect them from being reaped by removing them from gtt | |
1701 | * lists early. */ | |
1702 | list_del(&obj->gtt_list); | |
1703 | ||
37e680a1 | 1704 | ops->put_pages(obj); |
05394f39 | 1705 | obj->pages = NULL; |
37e680a1 | 1706 | |
6c085a72 CW |
1707 | if (i915_gem_object_is_purgeable(obj)) |
1708 | i915_gem_object_truncate(obj); | |
1709 | ||
1710 | return 0; | |
1711 | } | |
1712 | ||
1713 | static long | |
1714 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1715 | { | |
1716 | struct drm_i915_gem_object *obj, *next; | |
1717 | long count = 0; | |
1718 | ||
1719 | list_for_each_entry_safe(obj, next, | |
1720 | &dev_priv->mm.unbound_list, | |
1721 | gtt_list) { | |
1722 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1723 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1724 | count += obj->base.size >> PAGE_SHIFT; |
1725 | if (count >= target) | |
1726 | return count; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | list_for_each_entry_safe(obj, next, | |
1731 | &dev_priv->mm.inactive_list, | |
1732 | mm_list) { | |
1733 | if (i915_gem_object_is_purgeable(obj) && | |
1734 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1735 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1736 | count += obj->base.size >> PAGE_SHIFT; |
1737 | if (count >= target) | |
1738 | return count; | |
1739 | } | |
1740 | } | |
1741 | ||
1742 | return count; | |
1743 | } | |
1744 | ||
1745 | static void | |
1746 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1747 | { | |
1748 | struct drm_i915_gem_object *obj, *next; | |
1749 | ||
1750 | i915_gem_evict_everything(dev_priv->dev); | |
1751 | ||
1752 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1753 | i915_gem_object_put_pages(obj); |
225067ee DV |
1754 | } |
1755 | ||
37e680a1 | 1756 | static int |
6c085a72 | 1757 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1758 | { |
6c085a72 | 1759 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1760 | int page_count, i; |
1761 | struct address_space *mapping; | |
9da3da66 CW |
1762 | struct sg_table *st; |
1763 | struct scatterlist *sg; | |
e5281ccd | 1764 | struct page *page; |
6c085a72 | 1765 | gfp_t gfp; |
e5281ccd | 1766 | |
6c085a72 CW |
1767 | /* Assert that the object is not currently in any GPU domain. As it |
1768 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1769 | * a GPU cache | |
1770 | */ | |
1771 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1772 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1773 | ||
9da3da66 CW |
1774 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1775 | if (st == NULL) | |
1776 | return -ENOMEM; | |
1777 | ||
05394f39 | 1778 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1779 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1780 | sg_free_table(st); | |
1781 | kfree(st); | |
e5281ccd | 1782 | return -ENOMEM; |
9da3da66 | 1783 | } |
e5281ccd | 1784 | |
9da3da66 CW |
1785 | /* Get the list of pages out of our struct file. They'll be pinned |
1786 | * at this point until we release them. | |
1787 | * | |
1788 | * Fail silently without starting the shrinker | |
1789 | */ | |
6c085a72 CW |
1790 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1791 | gfp = mapping_gfp_mask(mapping); | |
d7c3b937 | 1792 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 | 1793 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1794 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1795 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1796 | if (IS_ERR(page)) { | |
1797 | i915_gem_purge(dev_priv, page_count); | |
1798 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1799 | } | |
1800 | if (IS_ERR(page)) { | |
1801 | /* We've tried hard to allocate the memory by reaping | |
1802 | * our own buffer, now let the real VM do its job and | |
1803 | * go down in flames if truly OOM. | |
1804 | */ | |
d7c3b937 | 1805 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN); |
6c085a72 CW |
1806 | gfp |= __GFP_IO | __GFP_WAIT; |
1807 | ||
1808 | i915_gem_shrink_all(dev_priv); | |
1809 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1810 | if (IS_ERR(page)) | |
1811 | goto err_pages; | |
1812 | ||
d7c3b937 | 1813 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 CW |
1814 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1815 | } | |
e5281ccd | 1816 | |
9da3da66 | 1817 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1818 | } |
1819 | ||
74ce6b6c CW |
1820 | obj->pages = st; |
1821 | ||
6dacfd2f | 1822 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1823 | i915_gem_object_do_bit_17_swizzle(obj); |
1824 | ||
1825 | return 0; | |
1826 | ||
1827 | err_pages: | |
9da3da66 CW |
1828 | for_each_sg(st->sgl, sg, i, page_count) |
1829 | page_cache_release(sg_page(sg)); | |
1830 | sg_free_table(st); | |
1831 | kfree(st); | |
e5281ccd | 1832 | return PTR_ERR(page); |
673a394b EA |
1833 | } |
1834 | ||
37e680a1 CW |
1835 | /* Ensure that the associated pages are gathered from the backing storage |
1836 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1837 | * multiple times before they are released by a single call to | |
1838 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1839 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1840 | * or as the object is itself released. | |
1841 | */ | |
1842 | int | |
1843 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1844 | { | |
1845 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1846 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1847 | int ret; | |
1848 | ||
2f745ad3 | 1849 | if (obj->pages) |
37e680a1 CW |
1850 | return 0; |
1851 | ||
a5570178 CW |
1852 | BUG_ON(obj->pages_pin_count); |
1853 | ||
37e680a1 CW |
1854 | ret = ops->get_pages(obj); |
1855 | if (ret) | |
1856 | return ret; | |
1857 | ||
1858 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1859 | return 0; | |
673a394b EA |
1860 | } |
1861 | ||
54cf91dc | 1862 | void |
05394f39 | 1863 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1864 | struct intel_ring_buffer *ring) |
673a394b | 1865 | { |
05394f39 | 1866 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1867 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1868 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1869 | |
852835f3 | 1870 | BUG_ON(ring == NULL); |
05394f39 | 1871 | obj->ring = ring; |
673a394b EA |
1872 | |
1873 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1874 | if (!obj->active) { |
1875 | drm_gem_object_reference(&obj->base); | |
1876 | obj->active = 1; | |
673a394b | 1877 | } |
e35a41de | 1878 | |
673a394b | 1879 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1880 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1881 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1882 | |
0201f1ec | 1883 | obj->last_read_seqno = seqno; |
caea7476 | 1884 | |
7dd49065 | 1885 | if (obj->fenced_gpu_access) { |
caea7476 | 1886 | obj->last_fenced_seqno = seqno; |
caea7476 | 1887 | |
7dd49065 CW |
1888 | /* Bump MRU to take account of the delayed flush */ |
1889 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1890 | struct drm_i915_fence_reg *reg; | |
1891 | ||
1892 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1893 | list_move_tail(®->lru_list, | |
1894 | &dev_priv->mm.fence_list); | |
1895 | } | |
caea7476 CW |
1896 | } |
1897 | } | |
1898 | ||
1899 | static void | |
caea7476 | 1900 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1901 | { |
05394f39 | 1902 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1903 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1904 | |
65ce3027 | 1905 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1906 | BUG_ON(!obj->active); |
caea7476 | 1907 | |
f047e395 CW |
1908 | if (obj->pin_count) /* are we a framebuffer? */ |
1909 | intel_mark_fb_idle(obj); | |
caea7476 | 1910 | |
1b50247a | 1911 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1912 | |
65ce3027 | 1913 | list_del_init(&obj->ring_list); |
caea7476 CW |
1914 | obj->ring = NULL; |
1915 | ||
65ce3027 CW |
1916 | obj->last_read_seqno = 0; |
1917 | obj->last_write_seqno = 0; | |
1918 | obj->base.write_domain = 0; | |
1919 | ||
1920 | obj->last_fenced_seqno = 0; | |
caea7476 | 1921 | obj->fenced_gpu_access = false; |
caea7476 CW |
1922 | |
1923 | obj->active = 0; | |
1924 | drm_gem_object_unreference(&obj->base); | |
1925 | ||
1926 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1927 | } |
673a394b | 1928 | |
9d773091 CW |
1929 | static int |
1930 | i915_gem_handle_seqno_wrap(struct drm_device *dev) | |
53d227f2 | 1931 | { |
9d773091 CW |
1932 | struct drm_i915_private *dev_priv = dev->dev_private; |
1933 | struct intel_ring_buffer *ring; | |
1934 | int ret, i, j; | |
53d227f2 | 1935 | |
9d773091 CW |
1936 | /* The hardware uses various monotonic 32-bit counters, if we |
1937 | * detect that they will wraparound we need to idle the GPU | |
1938 | * and reset those counters. | |
1939 | */ | |
1940 | ret = 0; | |
1941 | for_each_ring(ring, dev_priv, i) { | |
1942 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) | |
1943 | ret |= ring->sync_seqno[j] != 0; | |
1944 | } | |
1945 | if (ret == 0) | |
1946 | return ret; | |
1947 | ||
1948 | ret = i915_gpu_idle(dev); | |
1949 | if (ret) | |
1950 | return ret; | |
1951 | ||
1952 | i915_gem_retire_requests(dev); | |
1953 | for_each_ring(ring, dev_priv, i) { | |
1954 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) | |
1955 | ring->sync_seqno[j] = 0; | |
1956 | } | |
53d227f2 | 1957 | |
9d773091 | 1958 | return 0; |
53d227f2 DV |
1959 | } |
1960 | ||
9d773091 CW |
1961 | int |
1962 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1963 | { |
9d773091 CW |
1964 | struct drm_i915_private *dev_priv = dev->dev_private; |
1965 | ||
1966 | /* reserve 0 for non-seqno */ | |
1967 | if (dev_priv->next_seqno == 0) { | |
1968 | int ret = i915_gem_handle_seqno_wrap(dev); | |
1969 | if (ret) | |
1970 | return ret; | |
1971 | ||
1972 | dev_priv->next_seqno = 1; | |
1973 | } | |
53d227f2 | 1974 | |
9d773091 CW |
1975 | *seqno = dev_priv->next_seqno++; |
1976 | return 0; | |
53d227f2 DV |
1977 | } |
1978 | ||
3cce469c | 1979 | int |
db53a302 | 1980 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1981 | struct drm_file *file, |
acb868d3 | 1982 | u32 *out_seqno) |
673a394b | 1983 | { |
db53a302 | 1984 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 1985 | struct drm_i915_gem_request *request; |
a71d8d94 | 1986 | u32 request_ring_position; |
673a394b | 1987 | int was_empty; |
3cce469c CW |
1988 | int ret; |
1989 | ||
cc889e0f DV |
1990 | /* |
1991 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1992 | * after having emitted the batchbuffer command. Hence we need to fix | |
1993 | * things up similar to emitting the lazy request. The difference here | |
1994 | * is that the flush _must_ happen before the next request, no matter | |
1995 | * what. | |
1996 | */ | |
a7b9761d CW |
1997 | ret = intel_ring_flush_all_caches(ring); |
1998 | if (ret) | |
1999 | return ret; | |
cc889e0f | 2000 | |
acb868d3 CW |
2001 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2002 | if (request == NULL) | |
2003 | return -ENOMEM; | |
cc889e0f | 2004 | |
673a394b | 2005 | |
a71d8d94 CW |
2006 | /* Record the position of the start of the request so that |
2007 | * should we detect the updated seqno part-way through the | |
2008 | * GPU processing the request, we never over-estimate the | |
2009 | * position of the head. | |
2010 | */ | |
2011 | request_ring_position = intel_ring_get_tail(ring); | |
2012 | ||
9d773091 | 2013 | ret = ring->add_request(ring); |
3bb73aba CW |
2014 | if (ret) { |
2015 | kfree(request); | |
2016 | return ret; | |
2017 | } | |
673a394b | 2018 | |
9d773091 | 2019 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2020 | request->ring = ring; |
a71d8d94 | 2021 | request->tail = request_ring_position; |
673a394b | 2022 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2023 | was_empty = list_empty(&ring->request_list); |
2024 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2025 | request->file_priv = NULL; |
852835f3 | 2026 | |
db53a302 CW |
2027 | if (file) { |
2028 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2029 | ||
1c25595f | 2030 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2031 | request->file_priv = file_priv; |
b962442e | 2032 | list_add_tail(&request->client_list, |
f787a5f5 | 2033 | &file_priv->mm.request_list); |
1c25595f | 2034 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2035 | } |
673a394b | 2036 | |
9d773091 | 2037 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2038 | ring->outstanding_lazy_request = 0; |
db53a302 | 2039 | |
f65d9421 | 2040 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
2041 | if (i915_enable_hangcheck) { |
2042 | mod_timer(&dev_priv->hangcheck_timer, | |
cecc21fe | 2043 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2044 | } |
f047e395 | 2045 | if (was_empty) { |
b3b079db | 2046 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2047 | &dev_priv->mm.retire_work, |
2048 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2049 | intel_mark_busy(dev_priv->dev); |
2050 | } | |
f65d9421 | 2051 | } |
cc889e0f | 2052 | |
acb868d3 | 2053 | if (out_seqno) |
9d773091 | 2054 | *out_seqno = request->seqno; |
3cce469c | 2055 | return 0; |
673a394b EA |
2056 | } |
2057 | ||
f787a5f5 CW |
2058 | static inline void |
2059 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2060 | { |
1c25595f | 2061 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2062 | |
1c25595f CW |
2063 | if (!file_priv) |
2064 | return; | |
1c5d22f7 | 2065 | |
1c25595f | 2066 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2067 | if (request->file_priv) { |
2068 | list_del(&request->client_list); | |
2069 | request->file_priv = NULL; | |
2070 | } | |
1c25595f | 2071 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2072 | } |
673a394b | 2073 | |
dfaae392 CW |
2074 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2075 | struct intel_ring_buffer *ring) | |
9375e446 | 2076 | { |
dfaae392 CW |
2077 | while (!list_empty(&ring->request_list)) { |
2078 | struct drm_i915_gem_request *request; | |
673a394b | 2079 | |
dfaae392 CW |
2080 | request = list_first_entry(&ring->request_list, |
2081 | struct drm_i915_gem_request, | |
2082 | list); | |
de151cf6 | 2083 | |
dfaae392 | 2084 | list_del(&request->list); |
f787a5f5 | 2085 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2086 | kfree(request); |
2087 | } | |
673a394b | 2088 | |
dfaae392 | 2089 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2090 | struct drm_i915_gem_object *obj; |
9375e446 | 2091 | |
05394f39 CW |
2092 | obj = list_first_entry(&ring->active_list, |
2093 | struct drm_i915_gem_object, | |
2094 | ring_list); | |
9375e446 | 2095 | |
05394f39 | 2096 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2097 | } |
2098 | } | |
2099 | ||
312817a3 CW |
2100 | static void i915_gem_reset_fences(struct drm_device *dev) |
2101 | { | |
2102 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2103 | int i; | |
2104 | ||
4b9de737 | 2105 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2106 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2107 | |
ada726c7 | 2108 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2109 | |
ada726c7 CW |
2110 | if (reg->obj) |
2111 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2112 | |
ada726c7 CW |
2113 | reg->pin_count = 0; |
2114 | reg->obj = NULL; | |
2115 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2116 | } |
ada726c7 CW |
2117 | |
2118 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2119 | } |
2120 | ||
069efc1d | 2121 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2122 | { |
77f01230 | 2123 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2124 | struct drm_i915_gem_object *obj; |
b4519513 | 2125 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2126 | int i; |
673a394b | 2127 | |
b4519513 CW |
2128 | for_each_ring(ring, dev_priv, i) |
2129 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2130 | |
dfaae392 CW |
2131 | /* Move everything out of the GPU domains to ensure we do any |
2132 | * necessary invalidation upon reuse. | |
2133 | */ | |
05394f39 | 2134 | list_for_each_entry(obj, |
77f01230 | 2135 | &dev_priv->mm.inactive_list, |
69dc4987 | 2136 | mm_list) |
77f01230 | 2137 | { |
05394f39 | 2138 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2139 | } |
069efc1d CW |
2140 | |
2141 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2142 | i915_gem_reset_fences(dev); |
673a394b EA |
2143 | } |
2144 | ||
2145 | /** | |
2146 | * This function clears the request list as sequence numbers are passed. | |
2147 | */ | |
a71d8d94 | 2148 | void |
db53a302 | 2149 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2150 | { |
673a394b EA |
2151 | uint32_t seqno; |
2152 | ||
db53a302 | 2153 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2154 | return; |
2155 | ||
db53a302 | 2156 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2157 | |
b2eadbc8 | 2158 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2159 | |
852835f3 | 2160 | while (!list_empty(&ring->request_list)) { |
673a394b | 2161 | struct drm_i915_gem_request *request; |
673a394b | 2162 | |
852835f3 | 2163 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2164 | struct drm_i915_gem_request, |
2165 | list); | |
673a394b | 2166 | |
dfaae392 | 2167 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2168 | break; |
2169 | ||
db53a302 | 2170 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2171 | /* We know the GPU must have read the request to have |
2172 | * sent us the seqno + interrupt, so use the position | |
2173 | * of tail of the request to update the last known position | |
2174 | * of the GPU head. | |
2175 | */ | |
2176 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
2177 | |
2178 | list_del(&request->list); | |
f787a5f5 | 2179 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2180 | kfree(request); |
2181 | } | |
673a394b | 2182 | |
b84d5f0c CW |
2183 | /* Move any buffers on the active list that are no longer referenced |
2184 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2185 | */ | |
2186 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2187 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2188 | |
0206e353 | 2189 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2190 | struct drm_i915_gem_object, |
2191 | ring_list); | |
673a394b | 2192 | |
0201f1ec | 2193 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2194 | break; |
b84d5f0c | 2195 | |
65ce3027 | 2196 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2197 | } |
9d34e5db | 2198 | |
db53a302 CW |
2199 | if (unlikely(ring->trace_irq_seqno && |
2200 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2201 | ring->irq_put(ring); |
db53a302 | 2202 | ring->trace_irq_seqno = 0; |
9d34e5db | 2203 | } |
23bc5982 | 2204 | |
db53a302 | 2205 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2206 | } |
2207 | ||
b09a1fec CW |
2208 | void |
2209 | i915_gem_retire_requests(struct drm_device *dev) | |
2210 | { | |
2211 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2212 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2213 | int i; |
b09a1fec | 2214 | |
b4519513 CW |
2215 | for_each_ring(ring, dev_priv, i) |
2216 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2217 | } |
2218 | ||
75ef9da2 | 2219 | static void |
673a394b EA |
2220 | i915_gem_retire_work_handler(struct work_struct *work) |
2221 | { | |
2222 | drm_i915_private_t *dev_priv; | |
2223 | struct drm_device *dev; | |
b4519513 | 2224 | struct intel_ring_buffer *ring; |
0a58705b CW |
2225 | bool idle; |
2226 | int i; | |
673a394b EA |
2227 | |
2228 | dev_priv = container_of(work, drm_i915_private_t, | |
2229 | mm.retire_work.work); | |
2230 | dev = dev_priv->dev; | |
2231 | ||
891b48cf CW |
2232 | /* Come back later if the device is busy... */ |
2233 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2234 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2235 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2236 | return; |
2237 | } | |
673a394b | 2238 | |
b09a1fec | 2239 | i915_gem_retire_requests(dev); |
673a394b | 2240 | |
0a58705b CW |
2241 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2242 | * objects indefinitely. | |
673a394b | 2243 | */ |
0a58705b | 2244 | idle = true; |
b4519513 | 2245 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2246 | if (ring->gpu_caches_dirty) |
2247 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2248 | |
2249 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2250 | } |
2251 | ||
0a58705b | 2252 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2253 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2254 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2255 | if (idle) |
2256 | intel_mark_idle(dev); | |
0a58705b | 2257 | |
673a394b | 2258 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2259 | } |
2260 | ||
30dfebf3 DV |
2261 | /** |
2262 | * Ensures that an object will eventually get non-busy by flushing any required | |
2263 | * write domains, emitting any outstanding lazy request and retiring and | |
2264 | * completed requests. | |
2265 | */ | |
2266 | static int | |
2267 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2268 | { | |
2269 | int ret; | |
2270 | ||
2271 | if (obj->active) { | |
0201f1ec | 2272 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2273 | if (ret) |
2274 | return ret; | |
2275 | ||
30dfebf3 DV |
2276 | i915_gem_retire_requests_ring(obj->ring); |
2277 | } | |
2278 | ||
2279 | return 0; | |
2280 | } | |
2281 | ||
23ba4fd0 BW |
2282 | /** |
2283 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2284 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2285 | * | |
2286 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2287 | * the timeout parameter. | |
2288 | * -ETIME: object is still busy after timeout | |
2289 | * -ERESTARTSYS: signal interrupted the wait | |
2290 | * -ENONENT: object doesn't exist | |
2291 | * Also possible, but rare: | |
2292 | * -EAGAIN: GPU wedged | |
2293 | * -ENOMEM: damn | |
2294 | * -ENODEV: Internal IRQ fail | |
2295 | * -E?: The add request failed | |
2296 | * | |
2297 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2298 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2299 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2300 | * without holding struct_mutex the object may become re-busied before this | |
2301 | * function completes. A similar but shorter * race condition exists in the busy | |
2302 | * ioctl | |
2303 | */ | |
2304 | int | |
2305 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2306 | { | |
2307 | struct drm_i915_gem_wait *args = data; | |
2308 | struct drm_i915_gem_object *obj; | |
2309 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2310 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2311 | u32 seqno = 0; |
2312 | int ret = 0; | |
2313 | ||
eac1f14f BW |
2314 | if (args->timeout_ns >= 0) { |
2315 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2316 | timeout = &timeout_stack; | |
2317 | } | |
23ba4fd0 BW |
2318 | |
2319 | ret = i915_mutex_lock_interruptible(dev); | |
2320 | if (ret) | |
2321 | return ret; | |
2322 | ||
2323 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2324 | if (&obj->base == NULL) { | |
2325 | mutex_unlock(&dev->struct_mutex); | |
2326 | return -ENOENT; | |
2327 | } | |
2328 | ||
30dfebf3 DV |
2329 | /* Need to make sure the object gets inactive eventually. */ |
2330 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2331 | if (ret) |
2332 | goto out; | |
2333 | ||
2334 | if (obj->active) { | |
0201f1ec | 2335 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2336 | ring = obj->ring; |
2337 | } | |
2338 | ||
2339 | if (seqno == 0) | |
2340 | goto out; | |
2341 | ||
23ba4fd0 BW |
2342 | /* Do this after OLR check to make sure we make forward progress polling |
2343 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2344 | */ | |
2345 | if (!args->timeout_ns) { | |
2346 | ret = -ETIME; | |
2347 | goto out; | |
2348 | } | |
2349 | ||
2350 | drm_gem_object_unreference(&obj->base); | |
2351 | mutex_unlock(&dev->struct_mutex); | |
2352 | ||
eac1f14f BW |
2353 | ret = __wait_seqno(ring, seqno, true, timeout); |
2354 | if (timeout) { | |
2355 | WARN_ON(!timespec_valid(timeout)); | |
2356 | args->timeout_ns = timespec_to_ns(timeout); | |
2357 | } | |
23ba4fd0 BW |
2358 | return ret; |
2359 | ||
2360 | out: | |
2361 | drm_gem_object_unreference(&obj->base); | |
2362 | mutex_unlock(&dev->struct_mutex); | |
2363 | return ret; | |
2364 | } | |
2365 | ||
5816d648 BW |
2366 | /** |
2367 | * i915_gem_object_sync - sync an object to a ring. | |
2368 | * | |
2369 | * @obj: object which may be in use on another ring. | |
2370 | * @to: ring we wish to use the object on. May be NULL. | |
2371 | * | |
2372 | * This code is meant to abstract object synchronization with the GPU. | |
2373 | * Calling with NULL implies synchronizing the object with the CPU | |
2374 | * rather than a particular GPU ring. | |
2375 | * | |
2376 | * Returns 0 if successful, else propagates up the lower layer error. | |
2377 | */ | |
2911a35b BW |
2378 | int |
2379 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2380 | struct intel_ring_buffer *to) | |
2381 | { | |
2382 | struct intel_ring_buffer *from = obj->ring; | |
2383 | u32 seqno; | |
2384 | int ret, idx; | |
2385 | ||
2386 | if (from == NULL || to == from) | |
2387 | return 0; | |
2388 | ||
5816d648 | 2389 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2390 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2391 | |
2392 | idx = intel_ring_sync_index(from, to); | |
2393 | ||
0201f1ec | 2394 | seqno = obj->last_read_seqno; |
2911a35b BW |
2395 | if (seqno <= from->sync_seqno[idx]) |
2396 | return 0; | |
2397 | ||
b4aca010 BW |
2398 | ret = i915_gem_check_olr(obj->ring, seqno); |
2399 | if (ret) | |
2400 | return ret; | |
2911a35b | 2401 | |
1500f7ea | 2402 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2403 | if (!ret) |
7b01e260 MK |
2404 | /* We use last_read_seqno because sync_to() |
2405 | * might have just caused seqno wrap under | |
2406 | * the radar. | |
2407 | */ | |
2408 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2409 | |
e3a5a225 | 2410 | return ret; |
2911a35b BW |
2411 | } |
2412 | ||
b5ffc9bc CW |
2413 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2414 | { | |
2415 | u32 old_write_domain, old_read_domains; | |
2416 | ||
b5ffc9bc CW |
2417 | /* Act a barrier for all accesses through the GTT */ |
2418 | mb(); | |
2419 | ||
2420 | /* Force a pagefault for domain tracking on next user access */ | |
2421 | i915_gem_release_mmap(obj); | |
2422 | ||
b97c3d9c KP |
2423 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2424 | return; | |
2425 | ||
b5ffc9bc CW |
2426 | old_read_domains = obj->base.read_domains; |
2427 | old_write_domain = obj->base.write_domain; | |
2428 | ||
2429 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2430 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2431 | ||
2432 | trace_i915_gem_object_change_domain(obj, | |
2433 | old_read_domains, | |
2434 | old_write_domain); | |
2435 | } | |
2436 | ||
673a394b EA |
2437 | /** |
2438 | * Unbinds an object from the GTT aperture. | |
2439 | */ | |
0f973f27 | 2440 | int |
05394f39 | 2441 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2442 | { |
7bddb01f | 2443 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2444 | int ret = 0; |
2445 | ||
05394f39 | 2446 | if (obj->gtt_space == NULL) |
673a394b EA |
2447 | return 0; |
2448 | ||
31d8d651 CW |
2449 | if (obj->pin_count) |
2450 | return -EBUSY; | |
673a394b | 2451 | |
c4670ad0 CW |
2452 | BUG_ON(obj->pages == NULL); |
2453 | ||
a8198eea | 2454 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2455 | if (ret) |
a8198eea CW |
2456 | return ret; |
2457 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2458 | * should be safe and we need to cleanup or else we might | |
2459 | * cause memory corruption through use-after-free. | |
2460 | */ | |
2461 | ||
b5ffc9bc | 2462 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2463 | |
96b47b65 | 2464 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2465 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2466 | if (ret) |
d9e86c0e | 2467 | return ret; |
96b47b65 | 2468 | |
db53a302 CW |
2469 | trace_i915_gem_object_unbind(obj); |
2470 | ||
74898d7e DV |
2471 | if (obj->has_global_gtt_mapping) |
2472 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2473 | if (obj->has_aliasing_ppgtt_mapping) { |
2474 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2475 | obj->has_aliasing_ppgtt_mapping = 0; | |
2476 | } | |
74163907 | 2477 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2478 | |
6c085a72 CW |
2479 | list_del(&obj->mm_list); |
2480 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2481 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2482 | obj->map_and_fenceable = true; |
673a394b | 2483 | |
05394f39 CW |
2484 | drm_mm_put_block(obj->gtt_space); |
2485 | obj->gtt_space = NULL; | |
2486 | obj->gtt_offset = 0; | |
673a394b | 2487 | |
88241785 | 2488 | return 0; |
54cf91dc CW |
2489 | } |
2490 | ||
b2da9fe5 | 2491 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2492 | { |
2493 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2494 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2495 | int ret, i; |
4df2faf4 | 2496 | |
4df2faf4 | 2497 | /* Flush everything onto the inactive list. */ |
b4519513 | 2498 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2499 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2500 | if (ret) | |
2501 | return ret; | |
2502 | ||
3e960501 | 2503 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2504 | if (ret) |
2505 | return ret; | |
2506 | } | |
4df2faf4 | 2507 | |
8a1a49f9 | 2508 | return 0; |
4df2faf4 DV |
2509 | } |
2510 | ||
9ce079e4 CW |
2511 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2512 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2513 | { |
4e901fdc | 2514 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2515 | uint64_t val; |
2516 | ||
9ce079e4 CW |
2517 | if (obj) { |
2518 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2519 | |
9ce079e4 CW |
2520 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2521 | 0xfffff000) << 32; | |
2522 | val |= obj->gtt_offset & 0xfffff000; | |
2523 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2524 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2525 | |
9ce079e4 CW |
2526 | if (obj->tiling_mode == I915_TILING_Y) |
2527 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2528 | val |= I965_FENCE_REG_VALID; | |
2529 | } else | |
2530 | val = 0; | |
c6642782 | 2531 | |
9ce079e4 CW |
2532 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2533 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2534 | } |
2535 | ||
9ce079e4 CW |
2536 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2537 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2538 | { |
de151cf6 | 2539 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2540 | uint64_t val; |
2541 | ||
9ce079e4 CW |
2542 | if (obj) { |
2543 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2544 | |
9ce079e4 CW |
2545 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2546 | 0xfffff000) << 32; | |
2547 | val |= obj->gtt_offset & 0xfffff000; | |
2548 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2549 | if (obj->tiling_mode == I915_TILING_Y) | |
2550 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2551 | val |= I965_FENCE_REG_VALID; | |
2552 | } else | |
2553 | val = 0; | |
c6642782 | 2554 | |
9ce079e4 CW |
2555 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2556 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2557 | } |
2558 | ||
9ce079e4 CW |
2559 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2560 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2561 | { |
de151cf6 | 2562 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2563 | u32 val; |
de151cf6 | 2564 | |
9ce079e4 CW |
2565 | if (obj) { |
2566 | u32 size = obj->gtt_space->size; | |
2567 | int pitch_val; | |
2568 | int tile_width; | |
c6642782 | 2569 | |
9ce079e4 CW |
2570 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2571 | (size & -size) != size || | |
2572 | (obj->gtt_offset & (size - 1)), | |
2573 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2574 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2575 | |
9ce079e4 CW |
2576 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2577 | tile_width = 128; | |
2578 | else | |
2579 | tile_width = 512; | |
2580 | ||
2581 | /* Note: pitch better be a power of two tile widths */ | |
2582 | pitch_val = obj->stride / tile_width; | |
2583 | pitch_val = ffs(pitch_val) - 1; | |
2584 | ||
2585 | val = obj->gtt_offset; | |
2586 | if (obj->tiling_mode == I915_TILING_Y) | |
2587 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2588 | val |= I915_FENCE_SIZE_BITS(size); | |
2589 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2590 | val |= I830_FENCE_REG_VALID; | |
2591 | } else | |
2592 | val = 0; | |
2593 | ||
2594 | if (reg < 8) | |
2595 | reg = FENCE_REG_830_0 + reg * 4; | |
2596 | else | |
2597 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2598 | ||
2599 | I915_WRITE(reg, val); | |
2600 | POSTING_READ(reg); | |
de151cf6 JB |
2601 | } |
2602 | ||
9ce079e4 CW |
2603 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2604 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2605 | { |
de151cf6 | 2606 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2607 | uint32_t val; |
de151cf6 | 2608 | |
9ce079e4 CW |
2609 | if (obj) { |
2610 | u32 size = obj->gtt_space->size; | |
2611 | uint32_t pitch_val; | |
de151cf6 | 2612 | |
9ce079e4 CW |
2613 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2614 | (size & -size) != size || | |
2615 | (obj->gtt_offset & (size - 1)), | |
2616 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2617 | obj->gtt_offset, size); | |
e76a16de | 2618 | |
9ce079e4 CW |
2619 | pitch_val = obj->stride / 128; |
2620 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2621 | |
9ce079e4 CW |
2622 | val = obj->gtt_offset; |
2623 | if (obj->tiling_mode == I915_TILING_Y) | |
2624 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2625 | val |= I830_FENCE_SIZE_BITS(size); | |
2626 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2627 | val |= I830_FENCE_REG_VALID; | |
2628 | } else | |
2629 | val = 0; | |
c6642782 | 2630 | |
9ce079e4 CW |
2631 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2632 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2633 | } | |
2634 | ||
2635 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2636 | struct drm_i915_gem_object *obj) | |
2637 | { | |
2638 | switch (INTEL_INFO(dev)->gen) { | |
2639 | case 7: | |
2640 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2641 | case 5: | |
2642 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2643 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2644 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2645 | default: break; | |
2646 | } | |
de151cf6 JB |
2647 | } |
2648 | ||
61050808 CW |
2649 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2650 | struct drm_i915_fence_reg *fence) | |
2651 | { | |
2652 | return fence - dev_priv->fence_regs; | |
2653 | } | |
2654 | ||
2655 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2656 | struct drm_i915_fence_reg *fence, | |
2657 | bool enable) | |
2658 | { | |
2659 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2660 | int reg = fence_number(dev_priv, fence); | |
2661 | ||
2662 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2663 | ||
2664 | if (enable) { | |
2665 | obj->fence_reg = reg; | |
2666 | fence->obj = obj; | |
2667 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2668 | } else { | |
2669 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2670 | fence->obj = NULL; | |
2671 | list_del_init(&fence->lru_list); | |
2672 | } | |
2673 | } | |
2674 | ||
d9e86c0e | 2675 | static int |
a360bb1a | 2676 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2677 | { |
1c293ea3 | 2678 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2679 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2680 | if (ret) |
2681 | return ret; | |
d9e86c0e CW |
2682 | |
2683 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2684 | } |
2685 | ||
63256ec5 CW |
2686 | /* Ensure that all CPU reads are completed before installing a fence |
2687 | * and all writes before removing the fence. | |
2688 | */ | |
2689 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2690 | mb(); | |
2691 | ||
86d5bc37 | 2692 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2693 | return 0; |
2694 | } | |
2695 | ||
2696 | int | |
2697 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2698 | { | |
61050808 | 2699 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2700 | int ret; |
2701 | ||
a360bb1a | 2702 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2703 | if (ret) |
2704 | return ret; | |
2705 | ||
61050808 CW |
2706 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2707 | return 0; | |
d9e86c0e | 2708 | |
61050808 CW |
2709 | i915_gem_object_update_fence(obj, |
2710 | &dev_priv->fence_regs[obj->fence_reg], | |
2711 | false); | |
2712 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2713 | |
2714 | return 0; | |
2715 | } | |
2716 | ||
2717 | static struct drm_i915_fence_reg * | |
a360bb1a | 2718 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2719 | { |
ae3db24a | 2720 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2721 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2722 | int i; |
ae3db24a DV |
2723 | |
2724 | /* First try to find a free reg */ | |
d9e86c0e | 2725 | avail = NULL; |
ae3db24a DV |
2726 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2727 | reg = &dev_priv->fence_regs[i]; | |
2728 | if (!reg->obj) | |
d9e86c0e | 2729 | return reg; |
ae3db24a | 2730 | |
1690e1eb | 2731 | if (!reg->pin_count) |
d9e86c0e | 2732 | avail = reg; |
ae3db24a DV |
2733 | } |
2734 | ||
d9e86c0e CW |
2735 | if (avail == NULL) |
2736 | return NULL; | |
ae3db24a DV |
2737 | |
2738 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2739 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2740 | if (reg->pin_count) |
ae3db24a DV |
2741 | continue; |
2742 | ||
8fe301ad | 2743 | return reg; |
ae3db24a DV |
2744 | } |
2745 | ||
8fe301ad | 2746 | return NULL; |
ae3db24a DV |
2747 | } |
2748 | ||
de151cf6 | 2749 | /** |
9a5a53b3 | 2750 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2751 | * @obj: object to map through a fence reg |
2752 | * | |
2753 | * When mapping objects through the GTT, userspace wants to be able to write | |
2754 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2755 | * This function walks the fence regs looking for a free one for @obj, |
2756 | * stealing one if it can't find any. | |
2757 | * | |
2758 | * It then sets up the reg based on the object's properties: address, pitch | |
2759 | * and tiling format. | |
9a5a53b3 CW |
2760 | * |
2761 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2762 | */ |
8c4b8c3f | 2763 | int |
06d98131 | 2764 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2765 | { |
05394f39 | 2766 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2767 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2768 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2769 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2770 | int ret; |
de151cf6 | 2771 | |
14415745 CW |
2772 | /* Have we updated the tiling parameters upon the object and so |
2773 | * will need to serialise the write to the associated fence register? | |
2774 | */ | |
5d82e3e6 | 2775 | if (obj->fence_dirty) { |
14415745 CW |
2776 | ret = i915_gem_object_flush_fence(obj); |
2777 | if (ret) | |
2778 | return ret; | |
2779 | } | |
9a5a53b3 | 2780 | |
d9e86c0e | 2781 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2782 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2783 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2784 | if (!obj->fence_dirty) { |
14415745 CW |
2785 | list_move_tail(®->lru_list, |
2786 | &dev_priv->mm.fence_list); | |
2787 | return 0; | |
2788 | } | |
2789 | } else if (enable) { | |
2790 | reg = i915_find_fence_reg(dev); | |
2791 | if (reg == NULL) | |
2792 | return -EDEADLK; | |
d9e86c0e | 2793 | |
14415745 CW |
2794 | if (reg->obj) { |
2795 | struct drm_i915_gem_object *old = reg->obj; | |
2796 | ||
2797 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2798 | if (ret) |
2799 | return ret; | |
2800 | ||
14415745 | 2801 | i915_gem_object_fence_lost(old); |
29c5a587 | 2802 | } |
14415745 | 2803 | } else |
a09ba7fa | 2804 | return 0; |
a09ba7fa | 2805 | |
14415745 | 2806 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2807 | obj->fence_dirty = false; |
14415745 | 2808 | |
9ce079e4 | 2809 | return 0; |
de151cf6 JB |
2810 | } |
2811 | ||
42d6ab48 CW |
2812 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2813 | struct drm_mm_node *gtt_space, | |
2814 | unsigned long cache_level) | |
2815 | { | |
2816 | struct drm_mm_node *other; | |
2817 | ||
2818 | /* On non-LLC machines we have to be careful when putting differing | |
2819 | * types of snoopable memory together to avoid the prefetcher | |
2820 | * crossing memory domains and dieing. | |
2821 | */ | |
2822 | if (HAS_LLC(dev)) | |
2823 | return true; | |
2824 | ||
2825 | if (gtt_space == NULL) | |
2826 | return true; | |
2827 | ||
2828 | if (list_empty(>t_space->node_list)) | |
2829 | return true; | |
2830 | ||
2831 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2832 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2833 | return false; | |
2834 | ||
2835 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2836 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2837 | return false; | |
2838 | ||
2839 | return true; | |
2840 | } | |
2841 | ||
2842 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2843 | { | |
2844 | #if WATCH_GTT | |
2845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2846 | struct drm_i915_gem_object *obj; | |
2847 | int err = 0; | |
2848 | ||
2849 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2850 | if (obj->gtt_space == NULL) { | |
2851 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2852 | err++; | |
2853 | continue; | |
2854 | } | |
2855 | ||
2856 | if (obj->cache_level != obj->gtt_space->color) { | |
2857 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2858 | obj->gtt_space->start, | |
2859 | obj->gtt_space->start + obj->gtt_space->size, | |
2860 | obj->cache_level, | |
2861 | obj->gtt_space->color); | |
2862 | err++; | |
2863 | continue; | |
2864 | } | |
2865 | ||
2866 | if (!i915_gem_valid_gtt_space(dev, | |
2867 | obj->gtt_space, | |
2868 | obj->cache_level)) { | |
2869 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2870 | obj->gtt_space->start, | |
2871 | obj->gtt_space->start + obj->gtt_space->size, | |
2872 | obj->cache_level); | |
2873 | err++; | |
2874 | continue; | |
2875 | } | |
2876 | } | |
2877 | ||
2878 | WARN_ON(err); | |
2879 | #endif | |
2880 | } | |
2881 | ||
673a394b EA |
2882 | /** |
2883 | * Finds free space in the GTT aperture and binds the object there. | |
2884 | */ | |
2885 | static int | |
05394f39 | 2886 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2887 | unsigned alignment, |
86a1ee26 CW |
2888 | bool map_and_fenceable, |
2889 | bool nonblocking) | |
673a394b | 2890 | { |
05394f39 | 2891 | struct drm_device *dev = obj->base.dev; |
673a394b | 2892 | drm_i915_private_t *dev_priv = dev->dev_private; |
dc9dd7a2 | 2893 | struct drm_mm_node *node; |
5e783301 | 2894 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2895 | bool mappable, fenceable; |
07f73f69 | 2896 | int ret; |
673a394b | 2897 | |
05394f39 | 2898 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2899 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2900 | return -EINVAL; | |
2901 | } | |
2902 | ||
e28f8711 CW |
2903 | fence_size = i915_gem_get_gtt_size(dev, |
2904 | obj->base.size, | |
2905 | obj->tiling_mode); | |
2906 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2907 | obj->base.size, | |
2908 | obj->tiling_mode); | |
2909 | unfenced_alignment = | |
2910 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2911 | obj->base.size, | |
2912 | obj->tiling_mode); | |
a00b10c3 | 2913 | |
673a394b | 2914 | if (alignment == 0) |
5e783301 DV |
2915 | alignment = map_and_fenceable ? fence_alignment : |
2916 | unfenced_alignment; | |
75e9e915 | 2917 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2918 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2919 | return -EINVAL; | |
2920 | } | |
2921 | ||
05394f39 | 2922 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2923 | |
654fc607 CW |
2924 | /* If the object is bigger than the entire aperture, reject it early |
2925 | * before evicting everything in a vain attempt to find space. | |
2926 | */ | |
05394f39 | 2927 | if (obj->base.size > |
75e9e915 | 2928 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2929 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2930 | return -E2BIG; | |
2931 | } | |
2932 | ||
37e680a1 | 2933 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2934 | if (ret) |
2935 | return ret; | |
2936 | ||
fbdda6fb CW |
2937 | i915_gem_object_pin_pages(obj); |
2938 | ||
dc9dd7a2 CW |
2939 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
2940 | if (node == NULL) { | |
2941 | i915_gem_object_unpin_pages(obj); | |
2942 | return -ENOMEM; | |
2943 | } | |
2944 | ||
673a394b | 2945 | search_free: |
75e9e915 | 2946 | if (map_and_fenceable) |
dc9dd7a2 CW |
2947 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
2948 | size, alignment, obj->cache_level, | |
2949 | 0, dev_priv->mm.gtt_mappable_end); | |
920afa77 | 2950 | else |
dc9dd7a2 CW |
2951 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
2952 | size, alignment, obj->cache_level); | |
2953 | if (ret) { | |
75e9e915 | 2954 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2955 | obj->cache_level, |
86a1ee26 CW |
2956 | map_and_fenceable, |
2957 | nonblocking); | |
dc9dd7a2 CW |
2958 | if (ret == 0) |
2959 | goto search_free; | |
9731129c | 2960 | |
dc9dd7a2 CW |
2961 | i915_gem_object_unpin_pages(obj); |
2962 | kfree(node); | |
2963 | return ret; | |
673a394b | 2964 | } |
dc9dd7a2 | 2965 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
fbdda6fb | 2966 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2967 | drm_mm_put_block(node); |
42d6ab48 | 2968 | return -EINVAL; |
673a394b EA |
2969 | } |
2970 | ||
74163907 | 2971 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2972 | if (ret) { |
fbdda6fb | 2973 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2974 | drm_mm_put_block(node); |
6c085a72 | 2975 | return ret; |
673a394b | 2976 | } |
673a394b | 2977 | |
6c085a72 | 2978 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2979 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2980 | |
dc9dd7a2 CW |
2981 | obj->gtt_space = node; |
2982 | obj->gtt_offset = node->start; | |
1c5d22f7 | 2983 | |
75e9e915 | 2984 | fenceable = |
dc9dd7a2 CW |
2985 | node->size == fence_size && |
2986 | (node->start & (fence_alignment - 1)) == 0; | |
a00b10c3 | 2987 | |
75e9e915 | 2988 | mappable = |
05394f39 | 2989 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2990 | |
05394f39 | 2991 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2992 | |
fbdda6fb | 2993 | i915_gem_object_unpin_pages(obj); |
db53a302 | 2994 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2995 | i915_gem_verify_gtt(dev); |
673a394b EA |
2996 | return 0; |
2997 | } | |
2998 | ||
2999 | void | |
05394f39 | 3000 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3001 | { |
673a394b EA |
3002 | /* If we don't have a page list set up, then we're not pinned |
3003 | * to GPU, and we can ignore the cache flush because it'll happen | |
3004 | * again at bind time. | |
3005 | */ | |
05394f39 | 3006 | if (obj->pages == NULL) |
673a394b EA |
3007 | return; |
3008 | ||
9c23f7fc CW |
3009 | /* If the GPU is snooping the contents of the CPU cache, |
3010 | * we do not need to manually clear the CPU cache lines. However, | |
3011 | * the caches are only snooped when the render cache is | |
3012 | * flushed/invalidated. As we always have to emit invalidations | |
3013 | * and flushes when moving into and out of the RENDER domain, correct | |
3014 | * snooping behaviour occurs naturally as the result of our domain | |
3015 | * tracking. | |
3016 | */ | |
3017 | if (obj->cache_level != I915_CACHE_NONE) | |
3018 | return; | |
3019 | ||
1c5d22f7 | 3020 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3021 | |
9da3da66 | 3022 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3023 | } |
3024 | ||
3025 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3026 | static void | |
05394f39 | 3027 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3028 | { |
1c5d22f7 CW |
3029 | uint32_t old_write_domain; |
3030 | ||
05394f39 | 3031 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3032 | return; |
3033 | ||
63256ec5 | 3034 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3035 | * to it immediately go to main memory as far as we know, so there's |
3036 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3037 | * |
3038 | * However, we do have to enforce the order so that all writes through | |
3039 | * the GTT land before any writes to the device, such as updates to | |
3040 | * the GATT itself. | |
e47c68e9 | 3041 | */ |
63256ec5 CW |
3042 | wmb(); |
3043 | ||
05394f39 CW |
3044 | old_write_domain = obj->base.write_domain; |
3045 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3046 | |
3047 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3048 | obj->base.read_domains, |
1c5d22f7 | 3049 | old_write_domain); |
e47c68e9 EA |
3050 | } |
3051 | ||
3052 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3053 | static void | |
05394f39 | 3054 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3055 | { |
1c5d22f7 | 3056 | uint32_t old_write_domain; |
e47c68e9 | 3057 | |
05394f39 | 3058 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3059 | return; |
3060 | ||
3061 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3062 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3063 | old_write_domain = obj->base.write_domain; |
3064 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3065 | |
3066 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3067 | obj->base.read_domains, |
1c5d22f7 | 3068 | old_write_domain); |
e47c68e9 EA |
3069 | } |
3070 | ||
2ef7eeaa EA |
3071 | /** |
3072 | * Moves a single object to the GTT read, and possibly write domain. | |
3073 | * | |
3074 | * This function returns when the move is complete, including waiting on | |
3075 | * flushes to occur. | |
3076 | */ | |
79e53945 | 3077 | int |
2021746e | 3078 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3079 | { |
8325a09d | 3080 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3081 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3082 | int ret; |
2ef7eeaa | 3083 | |
02354392 | 3084 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3085 | if (obj->gtt_space == NULL) |
02354392 EA |
3086 | return -EINVAL; |
3087 | ||
8d7e3de1 CW |
3088 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3089 | return 0; | |
3090 | ||
0201f1ec | 3091 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3092 | if (ret) |
3093 | return ret; | |
3094 | ||
7213342d | 3095 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3096 | |
05394f39 CW |
3097 | old_write_domain = obj->base.write_domain; |
3098 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3099 | |
e47c68e9 EA |
3100 | /* It should now be out of any other write domains, and we can update |
3101 | * the domain values for our changes. | |
3102 | */ | |
05394f39 CW |
3103 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3104 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3105 | if (write) { |
05394f39 CW |
3106 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3107 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3108 | obj->dirty = 1; | |
2ef7eeaa EA |
3109 | } |
3110 | ||
1c5d22f7 CW |
3111 | trace_i915_gem_object_change_domain(obj, |
3112 | old_read_domains, | |
3113 | old_write_domain); | |
3114 | ||
8325a09d CW |
3115 | /* And bump the LRU for this access */ |
3116 | if (i915_gem_object_is_inactive(obj)) | |
3117 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3118 | ||
e47c68e9 EA |
3119 | return 0; |
3120 | } | |
3121 | ||
e4ffd173 CW |
3122 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3123 | enum i915_cache_level cache_level) | |
3124 | { | |
7bddb01f DV |
3125 | struct drm_device *dev = obj->base.dev; |
3126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3127 | int ret; |
3128 | ||
3129 | if (obj->cache_level == cache_level) | |
3130 | return 0; | |
3131 | ||
3132 | if (obj->pin_count) { | |
3133 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3134 | return -EBUSY; | |
3135 | } | |
3136 | ||
42d6ab48 CW |
3137 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3138 | ret = i915_gem_object_unbind(obj); | |
3139 | if (ret) | |
3140 | return ret; | |
3141 | } | |
3142 | ||
e4ffd173 CW |
3143 | if (obj->gtt_space) { |
3144 | ret = i915_gem_object_finish_gpu(obj); | |
3145 | if (ret) | |
3146 | return ret; | |
3147 | ||
3148 | i915_gem_object_finish_gtt(obj); | |
3149 | ||
3150 | /* Before SandyBridge, you could not use tiling or fence | |
3151 | * registers with snooped memory, so relinquish any fences | |
3152 | * currently pointing to our region in the aperture. | |
3153 | */ | |
42d6ab48 | 3154 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3155 | ret = i915_gem_object_put_fence(obj); |
3156 | if (ret) | |
3157 | return ret; | |
3158 | } | |
3159 | ||
74898d7e DV |
3160 | if (obj->has_global_gtt_mapping) |
3161 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3162 | if (obj->has_aliasing_ppgtt_mapping) |
3163 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3164 | obj, cache_level); | |
42d6ab48 CW |
3165 | |
3166 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3167 | } |
3168 | ||
3169 | if (cache_level == I915_CACHE_NONE) { | |
3170 | u32 old_read_domains, old_write_domain; | |
3171 | ||
3172 | /* If we're coming from LLC cached, then we haven't | |
3173 | * actually been tracking whether the data is in the | |
3174 | * CPU cache or not, since we only allow one bit set | |
3175 | * in obj->write_domain and have been skipping the clflushes. | |
3176 | * Just set it to the CPU cache for now. | |
3177 | */ | |
3178 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3179 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3180 | ||
3181 | old_read_domains = obj->base.read_domains; | |
3182 | old_write_domain = obj->base.write_domain; | |
3183 | ||
3184 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3185 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3186 | ||
3187 | trace_i915_gem_object_change_domain(obj, | |
3188 | old_read_domains, | |
3189 | old_write_domain); | |
3190 | } | |
3191 | ||
3192 | obj->cache_level = cache_level; | |
42d6ab48 | 3193 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3194 | return 0; |
3195 | } | |
3196 | ||
199adf40 BW |
3197 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3198 | struct drm_file *file) | |
e6994aee | 3199 | { |
199adf40 | 3200 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3201 | struct drm_i915_gem_object *obj; |
3202 | int ret; | |
3203 | ||
3204 | ret = i915_mutex_lock_interruptible(dev); | |
3205 | if (ret) | |
3206 | return ret; | |
3207 | ||
3208 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3209 | if (&obj->base == NULL) { | |
3210 | ret = -ENOENT; | |
3211 | goto unlock; | |
3212 | } | |
3213 | ||
199adf40 | 3214 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3215 | |
3216 | drm_gem_object_unreference(&obj->base); | |
3217 | unlock: | |
3218 | mutex_unlock(&dev->struct_mutex); | |
3219 | return ret; | |
3220 | } | |
3221 | ||
199adf40 BW |
3222 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3223 | struct drm_file *file) | |
e6994aee | 3224 | { |
199adf40 | 3225 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3226 | struct drm_i915_gem_object *obj; |
3227 | enum i915_cache_level level; | |
3228 | int ret; | |
3229 | ||
199adf40 BW |
3230 | switch (args->caching) { |
3231 | case I915_CACHING_NONE: | |
e6994aee CW |
3232 | level = I915_CACHE_NONE; |
3233 | break; | |
199adf40 | 3234 | case I915_CACHING_CACHED: |
e6994aee CW |
3235 | level = I915_CACHE_LLC; |
3236 | break; | |
3237 | default: | |
3238 | return -EINVAL; | |
3239 | } | |
3240 | ||
3bc2913e BW |
3241 | ret = i915_mutex_lock_interruptible(dev); |
3242 | if (ret) | |
3243 | return ret; | |
3244 | ||
e6994aee CW |
3245 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3246 | if (&obj->base == NULL) { | |
3247 | ret = -ENOENT; | |
3248 | goto unlock; | |
3249 | } | |
3250 | ||
3251 | ret = i915_gem_object_set_cache_level(obj, level); | |
3252 | ||
3253 | drm_gem_object_unreference(&obj->base); | |
3254 | unlock: | |
3255 | mutex_unlock(&dev->struct_mutex); | |
3256 | return ret; | |
3257 | } | |
3258 | ||
b9241ea3 | 3259 | /* |
2da3b9b9 CW |
3260 | * Prepare buffer for display plane (scanout, cursors, etc). |
3261 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3262 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3263 | */ |
3264 | int | |
2da3b9b9 CW |
3265 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3266 | u32 alignment, | |
919926ae | 3267 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3268 | { |
2da3b9b9 | 3269 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3270 | int ret; |
3271 | ||
0be73284 | 3272 | if (pipelined != obj->ring) { |
2911a35b BW |
3273 | ret = i915_gem_object_sync(obj, pipelined); |
3274 | if (ret) | |
b9241ea3 ZW |
3275 | return ret; |
3276 | } | |
3277 | ||
a7ef0640 EA |
3278 | /* The display engine is not coherent with the LLC cache on gen6. As |
3279 | * a result, we make sure that the pinning that is about to occur is | |
3280 | * done with uncached PTEs. This is lowest common denominator for all | |
3281 | * chipsets. | |
3282 | * | |
3283 | * However for gen6+, we could do better by using the GFDT bit instead | |
3284 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3285 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3286 | */ | |
3287 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3288 | if (ret) | |
3289 | return ret; | |
3290 | ||
2da3b9b9 CW |
3291 | /* As the user may map the buffer once pinned in the display plane |
3292 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3293 | * always use map_and_fenceable for all scanout buffers. | |
3294 | */ | |
86a1ee26 | 3295 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3296 | if (ret) |
3297 | return ret; | |
3298 | ||
b118c1e3 CW |
3299 | i915_gem_object_flush_cpu_write_domain(obj); |
3300 | ||
2da3b9b9 | 3301 | old_write_domain = obj->base.write_domain; |
05394f39 | 3302 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3303 | |
3304 | /* It should now be out of any other write domains, and we can update | |
3305 | * the domain values for our changes. | |
3306 | */ | |
e5f1d962 | 3307 | obj->base.write_domain = 0; |
05394f39 | 3308 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3309 | |
3310 | trace_i915_gem_object_change_domain(obj, | |
3311 | old_read_domains, | |
2da3b9b9 | 3312 | old_write_domain); |
b9241ea3 ZW |
3313 | |
3314 | return 0; | |
3315 | } | |
3316 | ||
85345517 | 3317 | int |
a8198eea | 3318 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3319 | { |
88241785 CW |
3320 | int ret; |
3321 | ||
a8198eea | 3322 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3323 | return 0; |
3324 | ||
0201f1ec | 3325 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3326 | if (ret) |
3327 | return ret; | |
3328 | ||
a8198eea CW |
3329 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3330 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3331 | return 0; |
85345517 CW |
3332 | } |
3333 | ||
e47c68e9 EA |
3334 | /** |
3335 | * Moves a single object to the CPU read, and possibly write domain. | |
3336 | * | |
3337 | * This function returns when the move is complete, including waiting on | |
3338 | * flushes to occur. | |
3339 | */ | |
dabdfe02 | 3340 | int |
919926ae | 3341 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3342 | { |
1c5d22f7 | 3343 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3344 | int ret; |
3345 | ||
8d7e3de1 CW |
3346 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3347 | return 0; | |
3348 | ||
0201f1ec | 3349 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3350 | if (ret) |
3351 | return ret; | |
3352 | ||
e47c68e9 | 3353 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3354 | |
05394f39 CW |
3355 | old_write_domain = obj->base.write_domain; |
3356 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3357 | |
e47c68e9 | 3358 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3359 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3360 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3361 | |
05394f39 | 3362 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3363 | } |
3364 | ||
3365 | /* It should now be out of any other write domains, and we can update | |
3366 | * the domain values for our changes. | |
3367 | */ | |
05394f39 | 3368 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3369 | |
3370 | /* If we're writing through the CPU, then the GPU read domains will | |
3371 | * need to be invalidated at next use. | |
3372 | */ | |
3373 | if (write) { | |
05394f39 CW |
3374 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3375 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3376 | } |
2ef7eeaa | 3377 | |
1c5d22f7 CW |
3378 | trace_i915_gem_object_change_domain(obj, |
3379 | old_read_domains, | |
3380 | old_write_domain); | |
3381 | ||
2ef7eeaa EA |
3382 | return 0; |
3383 | } | |
3384 | ||
673a394b EA |
3385 | /* Throttle our rendering by waiting until the ring has completed our requests |
3386 | * emitted over 20 msec ago. | |
3387 | * | |
b962442e EA |
3388 | * Note that if we were to use the current jiffies each time around the loop, |
3389 | * we wouldn't escape the function with any frames outstanding if the time to | |
3390 | * render a frame was over 20ms. | |
3391 | * | |
673a394b EA |
3392 | * This should get us reasonable parallelism between CPU and GPU but also |
3393 | * relatively low latency when blocking on a particular request to finish. | |
3394 | */ | |
40a5f0de | 3395 | static int |
f787a5f5 | 3396 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3397 | { |
f787a5f5 CW |
3398 | struct drm_i915_private *dev_priv = dev->dev_private; |
3399 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3400 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3401 | struct drm_i915_gem_request *request; |
3402 | struct intel_ring_buffer *ring = NULL; | |
3403 | u32 seqno = 0; | |
3404 | int ret; | |
93533c29 | 3405 | |
e110e8d6 CW |
3406 | if (atomic_read(&dev_priv->mm.wedged)) |
3407 | return -EIO; | |
3408 | ||
1c25595f | 3409 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3410 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3411 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3412 | break; | |
40a5f0de | 3413 | |
f787a5f5 CW |
3414 | ring = request->ring; |
3415 | seqno = request->seqno; | |
b962442e | 3416 | } |
1c25595f | 3417 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3418 | |
f787a5f5 CW |
3419 | if (seqno == 0) |
3420 | return 0; | |
2bc43b5c | 3421 | |
5c81fe85 | 3422 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3423 | if (ret == 0) |
3424 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3425 | |
3426 | return ret; | |
3427 | } | |
3428 | ||
673a394b | 3429 | int |
05394f39 CW |
3430 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3431 | uint32_t alignment, | |
86a1ee26 CW |
3432 | bool map_and_fenceable, |
3433 | bool nonblocking) | |
673a394b | 3434 | { |
673a394b EA |
3435 | int ret; |
3436 | ||
7e81a42e CW |
3437 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3438 | return -EBUSY; | |
ac0c6b5a | 3439 | |
05394f39 CW |
3440 | if (obj->gtt_space != NULL) { |
3441 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3442 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3443 | WARN(obj->pin_count, | |
ae7d49d8 | 3444 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3445 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3446 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3447 | obj->gtt_offset, alignment, |
75e9e915 | 3448 | map_and_fenceable, |
05394f39 | 3449 | obj->map_and_fenceable); |
ac0c6b5a CW |
3450 | ret = i915_gem_object_unbind(obj); |
3451 | if (ret) | |
3452 | return ret; | |
3453 | } | |
3454 | } | |
3455 | ||
05394f39 | 3456 | if (obj->gtt_space == NULL) { |
8742267a CW |
3457 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3458 | ||
a00b10c3 | 3459 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3460 | map_and_fenceable, |
3461 | nonblocking); | |
9731129c | 3462 | if (ret) |
673a394b | 3463 | return ret; |
8742267a CW |
3464 | |
3465 | if (!dev_priv->mm.aliasing_ppgtt) | |
3466 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3467 | } |
76446cac | 3468 | |
74898d7e DV |
3469 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3470 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3471 | ||
1b50247a | 3472 | obj->pin_count++; |
6299f992 | 3473 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3474 | |
3475 | return 0; | |
3476 | } | |
3477 | ||
3478 | void | |
05394f39 | 3479 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3480 | { |
05394f39 CW |
3481 | BUG_ON(obj->pin_count == 0); |
3482 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3483 | |
1b50247a | 3484 | if (--obj->pin_count == 0) |
6299f992 | 3485 | obj->pin_mappable = false; |
673a394b EA |
3486 | } |
3487 | ||
3488 | int | |
3489 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3490 | struct drm_file *file) |
673a394b EA |
3491 | { |
3492 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3493 | struct drm_i915_gem_object *obj; |
673a394b EA |
3494 | int ret; |
3495 | ||
1d7cfea1 CW |
3496 | ret = i915_mutex_lock_interruptible(dev); |
3497 | if (ret) | |
3498 | return ret; | |
673a394b | 3499 | |
05394f39 | 3500 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3501 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3502 | ret = -ENOENT; |
3503 | goto unlock; | |
673a394b | 3504 | } |
673a394b | 3505 | |
05394f39 | 3506 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3507 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3508 | ret = -EINVAL; |
3509 | goto out; | |
3ef94daa CW |
3510 | } |
3511 | ||
05394f39 | 3512 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3513 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3514 | args->handle); | |
1d7cfea1 CW |
3515 | ret = -EINVAL; |
3516 | goto out; | |
79e53945 JB |
3517 | } |
3518 | ||
05394f39 CW |
3519 | obj->user_pin_count++; |
3520 | obj->pin_filp = file; | |
3521 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3522 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3523 | if (ret) |
3524 | goto out; | |
673a394b EA |
3525 | } |
3526 | ||
3527 | /* XXX - flush the CPU caches for pinned objects | |
3528 | * as the X server doesn't manage domains yet | |
3529 | */ | |
e47c68e9 | 3530 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3531 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3532 | out: |
05394f39 | 3533 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3534 | unlock: |
673a394b | 3535 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3536 | return ret; |
673a394b EA |
3537 | } |
3538 | ||
3539 | int | |
3540 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3541 | struct drm_file *file) |
673a394b EA |
3542 | { |
3543 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3544 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3545 | int ret; |
673a394b | 3546 | |
1d7cfea1 CW |
3547 | ret = i915_mutex_lock_interruptible(dev); |
3548 | if (ret) | |
3549 | return ret; | |
673a394b | 3550 | |
05394f39 | 3551 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3552 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3553 | ret = -ENOENT; |
3554 | goto unlock; | |
673a394b | 3555 | } |
76c1dec1 | 3556 | |
05394f39 | 3557 | if (obj->pin_filp != file) { |
79e53945 JB |
3558 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3559 | args->handle); | |
1d7cfea1 CW |
3560 | ret = -EINVAL; |
3561 | goto out; | |
79e53945 | 3562 | } |
05394f39 CW |
3563 | obj->user_pin_count--; |
3564 | if (obj->user_pin_count == 0) { | |
3565 | obj->pin_filp = NULL; | |
79e53945 JB |
3566 | i915_gem_object_unpin(obj); |
3567 | } | |
673a394b | 3568 | |
1d7cfea1 | 3569 | out: |
05394f39 | 3570 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3571 | unlock: |
673a394b | 3572 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3573 | return ret; |
673a394b EA |
3574 | } |
3575 | ||
3576 | int | |
3577 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3578 | struct drm_file *file) |
673a394b EA |
3579 | { |
3580 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3581 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3582 | int ret; |
3583 | ||
76c1dec1 | 3584 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3585 | if (ret) |
76c1dec1 | 3586 | return ret; |
673a394b | 3587 | |
05394f39 | 3588 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3589 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3590 | ret = -ENOENT; |
3591 | goto unlock; | |
673a394b | 3592 | } |
d1b851fc | 3593 | |
0be555b6 CW |
3594 | /* Count all active objects as busy, even if they are currently not used |
3595 | * by the gpu. Users of this interface expect objects to eventually | |
3596 | * become non-busy without any further actions, therefore emit any | |
3597 | * necessary flushes here. | |
c4de0a5d | 3598 | */ |
30dfebf3 | 3599 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3600 | |
30dfebf3 | 3601 | args->busy = obj->active; |
e9808edd CW |
3602 | if (obj->ring) { |
3603 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3604 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3605 | } | |
673a394b | 3606 | |
05394f39 | 3607 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3608 | unlock: |
673a394b | 3609 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3610 | return ret; |
673a394b EA |
3611 | } |
3612 | ||
3613 | int | |
3614 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3615 | struct drm_file *file_priv) | |
3616 | { | |
0206e353 | 3617 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3618 | } |
3619 | ||
3ef94daa CW |
3620 | int |
3621 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3622 | struct drm_file *file_priv) | |
3623 | { | |
3624 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3625 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3626 | int ret; |
3ef94daa CW |
3627 | |
3628 | switch (args->madv) { | |
3629 | case I915_MADV_DONTNEED: | |
3630 | case I915_MADV_WILLNEED: | |
3631 | break; | |
3632 | default: | |
3633 | return -EINVAL; | |
3634 | } | |
3635 | ||
1d7cfea1 CW |
3636 | ret = i915_mutex_lock_interruptible(dev); |
3637 | if (ret) | |
3638 | return ret; | |
3639 | ||
05394f39 | 3640 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3641 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3642 | ret = -ENOENT; |
3643 | goto unlock; | |
3ef94daa | 3644 | } |
3ef94daa | 3645 | |
05394f39 | 3646 | if (obj->pin_count) { |
1d7cfea1 CW |
3647 | ret = -EINVAL; |
3648 | goto out; | |
3ef94daa CW |
3649 | } |
3650 | ||
05394f39 CW |
3651 | if (obj->madv != __I915_MADV_PURGED) |
3652 | obj->madv = args->madv; | |
3ef94daa | 3653 | |
6c085a72 CW |
3654 | /* if the object is no longer attached, discard its backing storage */ |
3655 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3656 | i915_gem_object_truncate(obj); |
3657 | ||
05394f39 | 3658 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3659 | |
1d7cfea1 | 3660 | out: |
05394f39 | 3661 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3662 | unlock: |
3ef94daa | 3663 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3664 | return ret; |
3ef94daa CW |
3665 | } |
3666 | ||
37e680a1 CW |
3667 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3668 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3669 | { |
0327d6ba CW |
3670 | INIT_LIST_HEAD(&obj->mm_list); |
3671 | INIT_LIST_HEAD(&obj->gtt_list); | |
3672 | INIT_LIST_HEAD(&obj->ring_list); | |
3673 | INIT_LIST_HEAD(&obj->exec_list); | |
3674 | ||
37e680a1 CW |
3675 | obj->ops = ops; |
3676 | ||
0327d6ba CW |
3677 | obj->fence_reg = I915_FENCE_REG_NONE; |
3678 | obj->madv = I915_MADV_WILLNEED; | |
3679 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3680 | obj->map_and_fenceable = true; | |
3681 | ||
3682 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3683 | } | |
3684 | ||
37e680a1 CW |
3685 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3686 | .get_pages = i915_gem_object_get_pages_gtt, | |
3687 | .put_pages = i915_gem_object_put_pages_gtt, | |
3688 | }; | |
3689 | ||
05394f39 CW |
3690 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3691 | size_t size) | |
ac52bc56 | 3692 | { |
c397b908 | 3693 | struct drm_i915_gem_object *obj; |
5949eac4 | 3694 | struct address_space *mapping; |
bed1ea95 | 3695 | u32 mask; |
ac52bc56 | 3696 | |
c397b908 DV |
3697 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3698 | if (obj == NULL) | |
3699 | return NULL; | |
673a394b | 3700 | |
c397b908 DV |
3701 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3702 | kfree(obj); | |
3703 | return NULL; | |
3704 | } | |
673a394b | 3705 | |
bed1ea95 CW |
3706 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3707 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3708 | /* 965gm cannot relocate objects above 4GiB. */ | |
3709 | mask &= ~__GFP_HIGHMEM; | |
3710 | mask |= __GFP_DMA32; | |
3711 | } | |
3712 | ||
5949eac4 | 3713 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3714 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3715 | |
37e680a1 | 3716 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3717 | |
c397b908 DV |
3718 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3719 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3720 | |
3d29b842 ED |
3721 | if (HAS_LLC(dev)) { |
3722 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3723 | * cache) for about a 10% performance improvement |
3724 | * compared to uncached. Graphics requests other than | |
3725 | * display scanout are coherent with the CPU in | |
3726 | * accessing this cache. This means in this mode we | |
3727 | * don't need to clflush on the CPU side, and on the | |
3728 | * GPU side we only need to flush internal caches to | |
3729 | * get data visible to the CPU. | |
3730 | * | |
3731 | * However, we maintain the display planes as UC, and so | |
3732 | * need to rebind when first used as such. | |
3733 | */ | |
3734 | obj->cache_level = I915_CACHE_LLC; | |
3735 | } else | |
3736 | obj->cache_level = I915_CACHE_NONE; | |
3737 | ||
05394f39 | 3738 | return obj; |
c397b908 DV |
3739 | } |
3740 | ||
3741 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3742 | { | |
3743 | BUG(); | |
de151cf6 | 3744 | |
673a394b EA |
3745 | return 0; |
3746 | } | |
3747 | ||
1488fc08 | 3748 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3749 | { |
1488fc08 | 3750 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3751 | struct drm_device *dev = obj->base.dev; |
be72615b | 3752 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3753 | |
26e12f89 CW |
3754 | trace_i915_gem_object_destroy(obj); |
3755 | ||
1488fc08 CW |
3756 | if (obj->phys_obj) |
3757 | i915_gem_detach_phys_object(dev, obj); | |
3758 | ||
3759 | obj->pin_count = 0; | |
3760 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3761 | bool was_interruptible; | |
3762 | ||
3763 | was_interruptible = dev_priv->mm.interruptible; | |
3764 | dev_priv->mm.interruptible = false; | |
3765 | ||
3766 | WARN_ON(i915_gem_object_unbind(obj)); | |
3767 | ||
3768 | dev_priv->mm.interruptible = was_interruptible; | |
3769 | } | |
3770 | ||
a5570178 | 3771 | obj->pages_pin_count = 0; |
37e680a1 | 3772 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3773 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 3774 | |
9da3da66 CW |
3775 | BUG_ON(obj->pages); |
3776 | ||
2f745ad3 CW |
3777 | if (obj->base.import_attach) |
3778 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3779 | |
05394f39 CW |
3780 | drm_gem_object_release(&obj->base); |
3781 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3782 | |
05394f39 CW |
3783 | kfree(obj->bit_17); |
3784 | kfree(obj); | |
673a394b EA |
3785 | } |
3786 | ||
29105ccc CW |
3787 | int |
3788 | i915_gem_idle(struct drm_device *dev) | |
3789 | { | |
3790 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3791 | int ret; | |
28dfe52a | 3792 | |
29105ccc | 3793 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3794 | |
87acb0a5 | 3795 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3796 | mutex_unlock(&dev->struct_mutex); |
3797 | return 0; | |
28dfe52a EA |
3798 | } |
3799 | ||
b2da9fe5 | 3800 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3801 | if (ret) { |
3802 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3803 | return ret; |
6dbe2772 | 3804 | } |
b2da9fe5 | 3805 | i915_gem_retire_requests(dev); |
673a394b | 3806 | |
29105ccc | 3807 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3808 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3809 | i915_gem_evict_everything(dev); |
29105ccc | 3810 | |
312817a3 CW |
3811 | i915_gem_reset_fences(dev); |
3812 | ||
29105ccc CW |
3813 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3814 | * We need to replace this with a semaphore, or something. | |
3815 | * And not confound mm.suspended! | |
3816 | */ | |
3817 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3818 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3819 | |
3820 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3821 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3822 | |
6dbe2772 KP |
3823 | mutex_unlock(&dev->struct_mutex); |
3824 | ||
29105ccc CW |
3825 | /* Cancel the retire work handler, which should be idle now. */ |
3826 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3827 | ||
673a394b EA |
3828 | return 0; |
3829 | } | |
3830 | ||
b9524a1e BW |
3831 | void i915_gem_l3_remap(struct drm_device *dev) |
3832 | { | |
3833 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3834 | u32 misccpctl; | |
3835 | int i; | |
3836 | ||
3837 | if (!IS_IVYBRIDGE(dev)) | |
3838 | return; | |
3839 | ||
a4da4fa4 | 3840 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3841 | return; |
3842 | ||
3843 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3844 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3845 | POSTING_READ(GEN7_MISCCPCTL); | |
3846 | ||
3847 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3848 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3849 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3850 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3851 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3852 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3853 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3854 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3855 | } |
3856 | ||
3857 | /* Make sure all the writes land before disabling dop clock gating */ | |
3858 | POSTING_READ(GEN7_L3LOG_BASE); | |
3859 | ||
3860 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3861 | } | |
3862 | ||
f691e2f4 DV |
3863 | void i915_gem_init_swizzling(struct drm_device *dev) |
3864 | { | |
3865 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3866 | ||
11782b02 | 3867 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3868 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3869 | return; | |
3870 | ||
3871 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3872 | DISP_TILE_SURFACE_SWIZZLING); | |
3873 | ||
11782b02 DV |
3874 | if (IS_GEN5(dev)) |
3875 | return; | |
3876 | ||
f691e2f4 DV |
3877 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3878 | if (IS_GEN6(dev)) | |
6b26c86d | 3879 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3880 | else |
6b26c86d | 3881 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3882 | } |
e21af88d | 3883 | |
67b1b571 CW |
3884 | static bool |
3885 | intel_enable_blt(struct drm_device *dev) | |
3886 | { | |
3887 | if (!HAS_BLT(dev)) | |
3888 | return false; | |
3889 | ||
3890 | /* The blitter was dysfunctional on early prototypes */ | |
3891 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3892 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3893 | " graphics performance will be degraded.\n"); | |
3894 | return false; | |
3895 | } | |
3896 | ||
3897 | return true; | |
3898 | } | |
3899 | ||
8187a2b7 | 3900 | int |
f691e2f4 | 3901 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3902 | { |
3903 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3904 | int ret; | |
68f95ba9 | 3905 | |
e76e9aeb | 3906 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
8ecd1a66 DV |
3907 | return -EIO; |
3908 | ||
eda2d7f5 RV |
3909 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3910 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3911 | ||
b9524a1e BW |
3912 | i915_gem_l3_remap(dev); |
3913 | ||
f691e2f4 DV |
3914 | i915_gem_init_swizzling(dev); |
3915 | ||
5c1143bb | 3916 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3917 | if (ret) |
b6913e4b | 3918 | return ret; |
68f95ba9 CW |
3919 | |
3920 | if (HAS_BSD(dev)) { | |
5c1143bb | 3921 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3922 | if (ret) |
3923 | goto cleanup_render_ring; | |
d1b851fc | 3924 | } |
68f95ba9 | 3925 | |
67b1b571 | 3926 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3927 | ret = intel_init_blt_ring_buffer(dev); |
3928 | if (ret) | |
3929 | goto cleanup_bsd_ring; | |
3930 | } | |
3931 | ||
6f392d54 CW |
3932 | dev_priv->next_seqno = 1; |
3933 | ||
254f965c BW |
3934 | /* |
3935 | * XXX: There was some w/a described somewhere suggesting loading | |
3936 | * contexts before PPGTT. | |
3937 | */ | |
3938 | i915_gem_context_init(dev); | |
e21af88d DV |
3939 | i915_gem_init_ppgtt(dev); |
3940 | ||
68f95ba9 CW |
3941 | return 0; |
3942 | ||
549f7365 | 3943 | cleanup_bsd_ring: |
1ec14ad3 | 3944 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3945 | cleanup_render_ring: |
1ec14ad3 | 3946 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3947 | return ret; |
3948 | } | |
3949 | ||
1070a42b CW |
3950 | static bool |
3951 | intel_enable_ppgtt(struct drm_device *dev) | |
3952 | { | |
3953 | if (i915_enable_ppgtt >= 0) | |
3954 | return i915_enable_ppgtt; | |
3955 | ||
3956 | #ifdef CONFIG_INTEL_IOMMU | |
3957 | /* Disable ppgtt on SNB if VT-d is on. */ | |
3958 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
3959 | return false; | |
3960 | #endif | |
3961 | ||
3962 | return true; | |
3963 | } | |
3964 | ||
3965 | int i915_gem_init(struct drm_device *dev) | |
3966 | { | |
3967 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3968 | unsigned long gtt_size, mappable_size; | |
3969 | int ret; | |
3970 | ||
3971 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
3972 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
3973 | ||
3974 | mutex_lock(&dev->struct_mutex); | |
3975 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
3976 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
3977 | * aperture accordingly when using aliasing ppgtt. */ | |
3978 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
3979 | ||
3980 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
3981 | ||
3982 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
3983 | if (ret) { | |
3984 | mutex_unlock(&dev->struct_mutex); | |
3985 | return ret; | |
3986 | } | |
3987 | } else { | |
3988 | /* Let GEM Manage all of the aperture. | |
3989 | * | |
3990 | * However, leave one page at the end still bound to the scratch | |
3991 | * page. There are a number of places where the hardware | |
3992 | * apparently prefetches past the end of the object, and we've | |
3993 | * seen multiple hangs with the GPU head pointer stuck in a | |
3994 | * batchbuffer bound at the last page of the aperture. One page | |
3995 | * should be enough to keep any prefetching inside of the | |
3996 | * aperture. | |
3997 | */ | |
3998 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
3999 | gtt_size); | |
4000 | } | |
4001 | ||
4002 | ret = i915_gem_init_hw(dev); | |
4003 | mutex_unlock(&dev->struct_mutex); | |
4004 | if (ret) { | |
4005 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4006 | return ret; | |
4007 | } | |
4008 | ||
53ca26ca DV |
4009 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4010 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4011 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4012 | return 0; |
4013 | } | |
4014 | ||
8187a2b7 ZN |
4015 | void |
4016 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4017 | { | |
4018 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4019 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4020 | int i; |
8187a2b7 | 4021 | |
b4519513 CW |
4022 | for_each_ring(ring, dev_priv, i) |
4023 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4024 | } |
4025 | ||
673a394b EA |
4026 | int |
4027 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4028 | struct drm_file *file_priv) | |
4029 | { | |
4030 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4031 | int ret; |
673a394b | 4032 | |
79e53945 JB |
4033 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4034 | return 0; | |
4035 | ||
ba1234d1 | 4036 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4037 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4038 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4039 | } |
4040 | ||
673a394b | 4041 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4042 | dev_priv->mm.suspended = 0; |
4043 | ||
f691e2f4 | 4044 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4045 | if (ret != 0) { |
4046 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4047 | return ret; |
d816f6ac | 4048 | } |
9bb2d6f9 | 4049 | |
69dc4987 | 4050 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4051 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4052 | |
5f35308b CW |
4053 | ret = drm_irq_install(dev); |
4054 | if (ret) | |
4055 | goto cleanup_ringbuffer; | |
dbb19d30 | 4056 | |
673a394b | 4057 | return 0; |
5f35308b CW |
4058 | |
4059 | cleanup_ringbuffer: | |
4060 | mutex_lock(&dev->struct_mutex); | |
4061 | i915_gem_cleanup_ringbuffer(dev); | |
4062 | dev_priv->mm.suspended = 1; | |
4063 | mutex_unlock(&dev->struct_mutex); | |
4064 | ||
4065 | return ret; | |
673a394b EA |
4066 | } |
4067 | ||
4068 | int | |
4069 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4070 | struct drm_file *file_priv) | |
4071 | { | |
79e53945 JB |
4072 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4073 | return 0; | |
4074 | ||
dbb19d30 | 4075 | drm_irq_uninstall(dev); |
e6890f6f | 4076 | return i915_gem_idle(dev); |
673a394b EA |
4077 | } |
4078 | ||
4079 | void | |
4080 | i915_gem_lastclose(struct drm_device *dev) | |
4081 | { | |
4082 | int ret; | |
673a394b | 4083 | |
e806b495 EA |
4084 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4085 | return; | |
4086 | ||
6dbe2772 KP |
4087 | ret = i915_gem_idle(dev); |
4088 | if (ret) | |
4089 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4090 | } |
4091 | ||
64193406 CW |
4092 | static void |
4093 | init_ring_lists(struct intel_ring_buffer *ring) | |
4094 | { | |
4095 | INIT_LIST_HEAD(&ring->active_list); | |
4096 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4097 | } |
4098 | ||
673a394b EA |
4099 | void |
4100 | i915_gem_load(struct drm_device *dev) | |
4101 | { | |
b5aa8a0f | 4102 | int i; |
673a394b EA |
4103 | drm_i915_private_t *dev_priv = dev->dev_private; |
4104 | ||
69dc4987 | 4105 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4106 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4107 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4108 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4109 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4110 | for (i = 0; i < I915_NUM_RINGS; i++) |
4111 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4112 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4113 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4114 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4115 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4116 | init_completion(&dev_priv->error_completion); |
31169714 | 4117 | |
94400120 DA |
4118 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4119 | if (IS_GEN3(dev)) { | |
50743298 DV |
4120 | I915_WRITE(MI_ARB_STATE, |
4121 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4122 | } |
4123 | ||
72bfa19c CW |
4124 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4125 | ||
de151cf6 | 4126 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4127 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4128 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4129 | |
a6c45cf0 | 4130 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4131 | dev_priv->num_fence_regs = 16; |
4132 | else | |
4133 | dev_priv->num_fence_regs = 8; | |
4134 | ||
b5aa8a0f | 4135 | /* Initialize fence registers to zero */ |
ada726c7 | 4136 | i915_gem_reset_fences(dev); |
10ed13e4 | 4137 | |
673a394b | 4138 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4139 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4140 | |
ce453d81 CW |
4141 | dev_priv->mm.interruptible = true; |
4142 | ||
17250b71 CW |
4143 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4144 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4145 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4146 | } |
71acb5eb DA |
4147 | |
4148 | /* | |
4149 | * Create a physically contiguous memory object for this object | |
4150 | * e.g. for cursor + overlay regs | |
4151 | */ | |
995b6762 CW |
4152 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4153 | int id, int size, int align) | |
71acb5eb DA |
4154 | { |
4155 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4156 | struct drm_i915_gem_phys_object *phys_obj; | |
4157 | int ret; | |
4158 | ||
4159 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4160 | return 0; | |
4161 | ||
9a298b2a | 4162 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4163 | if (!phys_obj) |
4164 | return -ENOMEM; | |
4165 | ||
4166 | phys_obj->id = id; | |
4167 | ||
6eeefaf3 | 4168 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4169 | if (!phys_obj->handle) { |
4170 | ret = -ENOMEM; | |
4171 | goto kfree_obj; | |
4172 | } | |
4173 | #ifdef CONFIG_X86 | |
4174 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4175 | #endif | |
4176 | ||
4177 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4178 | ||
4179 | return 0; | |
4180 | kfree_obj: | |
9a298b2a | 4181 | kfree(phys_obj); |
71acb5eb DA |
4182 | return ret; |
4183 | } | |
4184 | ||
995b6762 | 4185 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4186 | { |
4187 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4188 | struct drm_i915_gem_phys_object *phys_obj; | |
4189 | ||
4190 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4191 | return; | |
4192 | ||
4193 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4194 | if (phys_obj->cur_obj) { | |
4195 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4196 | } | |
4197 | ||
4198 | #ifdef CONFIG_X86 | |
4199 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4200 | #endif | |
4201 | drm_pci_free(dev, phys_obj->handle); | |
4202 | kfree(phys_obj); | |
4203 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4204 | } | |
4205 | ||
4206 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4207 | { | |
4208 | int i; | |
4209 | ||
260883c8 | 4210 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4211 | i915_gem_free_phys_object(dev, i); |
4212 | } | |
4213 | ||
4214 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4215 | struct drm_i915_gem_object *obj) |
71acb5eb | 4216 | { |
05394f39 | 4217 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4218 | char *vaddr; |
71acb5eb | 4219 | int i; |
71acb5eb DA |
4220 | int page_count; |
4221 | ||
05394f39 | 4222 | if (!obj->phys_obj) |
71acb5eb | 4223 | return; |
05394f39 | 4224 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4225 | |
05394f39 | 4226 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4227 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4228 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4229 | if (!IS_ERR(page)) { |
4230 | char *dst = kmap_atomic(page); | |
4231 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4232 | kunmap_atomic(dst); | |
4233 | ||
4234 | drm_clflush_pages(&page, 1); | |
4235 | ||
4236 | set_page_dirty(page); | |
4237 | mark_page_accessed(page); | |
4238 | page_cache_release(page); | |
4239 | } | |
71acb5eb | 4240 | } |
e76e9aeb | 4241 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4242 | |
05394f39 CW |
4243 | obj->phys_obj->cur_obj = NULL; |
4244 | obj->phys_obj = NULL; | |
71acb5eb DA |
4245 | } |
4246 | ||
4247 | int | |
4248 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4249 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4250 | int id, |
4251 | int align) | |
71acb5eb | 4252 | { |
05394f39 | 4253 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4254 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4255 | int ret = 0; |
4256 | int page_count; | |
4257 | int i; | |
4258 | ||
4259 | if (id > I915_MAX_PHYS_OBJECT) | |
4260 | return -EINVAL; | |
4261 | ||
05394f39 CW |
4262 | if (obj->phys_obj) { |
4263 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4264 | return 0; |
4265 | i915_gem_detach_phys_object(dev, obj); | |
4266 | } | |
4267 | ||
71acb5eb DA |
4268 | /* create a new object */ |
4269 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4270 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4271 | obj->base.size, align); |
71acb5eb | 4272 | if (ret) { |
05394f39 CW |
4273 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4274 | id, obj->base.size); | |
e5281ccd | 4275 | return ret; |
71acb5eb DA |
4276 | } |
4277 | } | |
4278 | ||
4279 | /* bind to the object */ | |
05394f39 CW |
4280 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4281 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4282 | |
05394f39 | 4283 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4284 | |
4285 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4286 | struct page *page; |
4287 | char *dst, *src; | |
4288 | ||
5949eac4 | 4289 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4290 | if (IS_ERR(page)) |
4291 | return PTR_ERR(page); | |
71acb5eb | 4292 | |
ff75b9bc | 4293 | src = kmap_atomic(page); |
05394f39 | 4294 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4295 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4296 | kunmap_atomic(src); |
71acb5eb | 4297 | |
e5281ccd CW |
4298 | mark_page_accessed(page); |
4299 | page_cache_release(page); | |
4300 | } | |
d78b47b9 | 4301 | |
71acb5eb | 4302 | return 0; |
71acb5eb DA |
4303 | } |
4304 | ||
4305 | static int | |
05394f39 CW |
4306 | i915_gem_phys_pwrite(struct drm_device *dev, |
4307 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4308 | struct drm_i915_gem_pwrite *args, |
4309 | struct drm_file *file_priv) | |
4310 | { | |
05394f39 | 4311 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4312 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4313 | |
b47b30cc CW |
4314 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4315 | unsigned long unwritten; | |
4316 | ||
4317 | /* The physical object once assigned is fixed for the lifetime | |
4318 | * of the obj, so we can safely drop the lock and continue | |
4319 | * to access vaddr. | |
4320 | */ | |
4321 | mutex_unlock(&dev->struct_mutex); | |
4322 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4323 | mutex_lock(&dev->struct_mutex); | |
4324 | if (unwritten) | |
4325 | return -EFAULT; | |
4326 | } | |
71acb5eb | 4327 | |
e76e9aeb | 4328 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4329 | return 0; |
4330 | } | |
b962442e | 4331 | |
f787a5f5 | 4332 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4333 | { |
f787a5f5 | 4334 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4335 | |
4336 | /* Clean up our request list when the client is going away, so that | |
4337 | * later retire_requests won't dereference our soon-to-be-gone | |
4338 | * file_priv. | |
4339 | */ | |
1c25595f | 4340 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4341 | while (!list_empty(&file_priv->mm.request_list)) { |
4342 | struct drm_i915_gem_request *request; | |
4343 | ||
4344 | request = list_first_entry(&file_priv->mm.request_list, | |
4345 | struct drm_i915_gem_request, | |
4346 | client_list); | |
4347 | list_del(&request->client_list); | |
4348 | request->file_priv = NULL; | |
4349 | } | |
1c25595f | 4350 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4351 | } |
31169714 | 4352 | |
5774506f CW |
4353 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4354 | { | |
4355 | if (!mutex_is_locked(mutex)) | |
4356 | return false; | |
4357 | ||
4358 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4359 | return mutex->owner == task; | |
4360 | #else | |
4361 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4362 | return false; | |
4363 | #endif | |
4364 | } | |
4365 | ||
31169714 | 4366 | static int |
1495f230 | 4367 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4368 | { |
17250b71 CW |
4369 | struct drm_i915_private *dev_priv = |
4370 | container_of(shrinker, | |
4371 | struct drm_i915_private, | |
4372 | mm.inactive_shrinker); | |
4373 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4374 | struct drm_i915_gem_object *obj; |
1495f230 | 4375 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4376 | bool unlock = true; |
17250b71 CW |
4377 | int cnt; |
4378 | ||
5774506f CW |
4379 | if (!mutex_trylock(&dev->struct_mutex)) { |
4380 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4381 | return 0; | |
4382 | ||
4383 | unlock = false; | |
4384 | } | |
31169714 | 4385 | |
6c085a72 CW |
4386 | if (nr_to_scan) { |
4387 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4388 | if (nr_to_scan > 0) | |
4389 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4390 | } |
4391 | ||
17250b71 | 4392 | cnt = 0; |
6c085a72 | 4393 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4394 | if (obj->pages_pin_count == 0) |
4395 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4396 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4397 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4398 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4399 | |
5774506f CW |
4400 | if (unlock) |
4401 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4402 | return cnt; |
31169714 | 4403 | } |