Commit | Line | Data |
---|---|---|
673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5d723d7a | 35 | #include "intel_frontbuffer.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
c13d87ea | 37 | #include <linux/reservation.h> |
5949eac4 | 38 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
673a394b | 40 | #include <linux/swap.h> |
79e53945 | 41 | #include <linux/pci.h> |
1286ff73 | 42 | #include <linux/dma-buf.h> |
673a394b | 43 | |
fbbd37b3 | 44 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
05394f39 | 45 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 46 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 47 | |
c76ce038 CW |
48 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
49 | enum i915_cache_level level) | |
50 | { | |
51 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
52 | } | |
53 | ||
2c22569b CW |
54 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
55 | { | |
b50a5371 AS |
56 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
57 | return false; | |
58 | ||
2c22569b CW |
59 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
60 | return true; | |
61 | ||
62 | return obj->pin_display; | |
63 | } | |
64 | ||
4f1959ee | 65 | static int |
bb6dc8d9 | 66 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
67 | struct drm_mm_node *node, u32 size) |
68 | { | |
69 | memset(node, 0, sizeof(*node)); | |
bb6dc8d9 CW |
70 | return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node, |
71 | size, 0, -1, | |
72 | 0, ggtt->mappable_end, | |
4f1959ee AS |
73 | DRM_MM_SEARCH_DEFAULT, |
74 | DRM_MM_CREATE_DEFAULT); | |
75 | } | |
76 | ||
77 | static void | |
78 | remove_mappable_node(struct drm_mm_node *node) | |
79 | { | |
80 | drm_mm_remove_node(node); | |
81 | } | |
82 | ||
73aa808f CW |
83 | /* some bookkeeping */ |
84 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 85 | u64 size) |
73aa808f | 86 | { |
c20e8355 | 87 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | dev_priv->mm.object_count++; |
89 | dev_priv->mm.object_memory += size; | |
c20e8355 | 90 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | } |
92 | ||
93 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 94 | u64 size) |
73aa808f | 95 | { |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count--; |
98 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
21dd3734 | 102 | static int |
33196ded | 103 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 104 | { |
30dbf0c0 CW |
105 | int ret; |
106 | ||
4c7d62c6 CW |
107 | might_sleep(); |
108 | ||
d98c52cf | 109 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
110 | return 0; |
111 | ||
0a6759c6 DV |
112 | /* |
113 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
114 | * userspace. If it takes that long something really bad is going on and | |
115 | * we should simply try to bail out and fail as gracefully as possible. | |
116 | */ | |
1f83fee0 | 117 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 118 | !i915_reset_in_progress(error), |
b52992c0 | 119 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
120 | if (ret == 0) { |
121 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
122 | return -EIO; | |
123 | } else if (ret < 0) { | |
30dbf0c0 | 124 | return ret; |
d98c52cf CW |
125 | } else { |
126 | return 0; | |
0a6759c6 | 127 | } |
30dbf0c0 CW |
128 | } |
129 | ||
54cf91dc | 130 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 131 | { |
fac5e23e | 132 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
133 | int ret; |
134 | ||
33196ded | 135 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
136 | if (ret) |
137 | return ret; | |
138 | ||
139 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
140 | if (ret) | |
141 | return ret; | |
142 | ||
76c1dec1 CW |
143 | return 0; |
144 | } | |
30dbf0c0 | 145 | |
5a125c3c EA |
146 | int |
147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
5a125c3c | 149 | { |
72e96d64 | 150 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 151 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 152 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 153 | struct i915_vma *vma; |
6299f992 | 154 | size_t pinned; |
5a125c3c | 155 | |
6299f992 | 156 | pinned = 0; |
73aa808f | 157 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 158 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 159 | if (i915_vma_is_pinned(vma)) |
ca1543be | 160 | pinned += vma->node.size; |
1c7f4bca | 161 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 162 | if (i915_vma_is_pinned(vma)) |
ca1543be | 163 | pinned += vma->node.size; |
73aa808f | 164 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 165 | |
72e96d64 | 166 | args->aper_size = ggtt->base.total; |
0206e353 | 167 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 168 | |
5a125c3c EA |
169 | return 0; |
170 | } | |
171 | ||
03ac84f1 | 172 | static struct sg_table * |
6a2c4232 | 173 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 174 | { |
93c76a3d | 175 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 CW |
176 | char *vaddr = obj->phys_handle->vaddr; |
177 | struct sg_table *st; | |
178 | struct scatterlist *sg; | |
179 | int i; | |
00731155 | 180 | |
6a2c4232 | 181 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 182 | return ERR_PTR(-EINVAL); |
6a2c4232 CW |
183 | |
184 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
185 | struct page *page; | |
186 | char *src; | |
187 | ||
188 | page = shmem_read_mapping_page(mapping, i); | |
189 | if (IS_ERR(page)) | |
03ac84f1 | 190 | return ERR_CAST(page); |
6a2c4232 CW |
191 | |
192 | src = kmap_atomic(page); | |
193 | memcpy(vaddr, src, PAGE_SIZE); | |
194 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
195 | kunmap_atomic(src); | |
196 | ||
09cbfeaf | 197 | put_page(page); |
6a2c4232 CW |
198 | vaddr += PAGE_SIZE; |
199 | } | |
200 | ||
c033666a | 201 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
202 | |
203 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
204 | if (st == NULL) | |
03ac84f1 | 205 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
206 | |
207 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
208 | kfree(st); | |
03ac84f1 | 209 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
210 | } |
211 | ||
212 | sg = st->sgl; | |
213 | sg->offset = 0; | |
214 | sg->length = obj->base.size; | |
00731155 | 215 | |
6a2c4232 CW |
216 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
217 | sg_dma_len(sg) = obj->base.size; | |
218 | ||
03ac84f1 | 219 | return st; |
6a2c4232 CW |
220 | } |
221 | ||
222 | static void | |
03ac84f1 | 223 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj) |
6a2c4232 | 224 | { |
a4f5ea64 | 225 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 226 | |
a4f5ea64 CW |
227 | if (obj->mm.madv == I915_MADV_DONTNEED) |
228 | obj->mm.dirty = false; | |
6a2c4232 | 229 | |
03ac84f1 CW |
230 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
231 | i915_gem_clflush_object(obj, false); | |
232 | ||
233 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
234 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
235 | } | |
236 | ||
237 | static void | |
238 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
239 | struct sg_table *pages) | |
240 | { | |
241 | __i915_gem_object_release_shmem(obj); | |
242 | ||
a4f5ea64 | 243 | if (obj->mm.dirty) { |
93c76a3d | 244 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 245 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
246 | int i; |
247 | ||
248 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
249 | struct page *page; |
250 | char *dst; | |
251 | ||
252 | page = shmem_read_mapping_page(mapping, i); | |
253 | if (IS_ERR(page)) | |
254 | continue; | |
255 | ||
256 | dst = kmap_atomic(page); | |
257 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
258 | memcpy(dst, vaddr, PAGE_SIZE); | |
259 | kunmap_atomic(dst); | |
260 | ||
261 | set_page_dirty(page); | |
a4f5ea64 | 262 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 263 | mark_page_accessed(page); |
09cbfeaf | 264 | put_page(page); |
00731155 CW |
265 | vaddr += PAGE_SIZE; |
266 | } | |
a4f5ea64 | 267 | obj->mm.dirty = false; |
00731155 CW |
268 | } |
269 | ||
03ac84f1 CW |
270 | sg_free_table(pages); |
271 | kfree(pages); | |
6a2c4232 CW |
272 | } |
273 | ||
274 | static void | |
275 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
276 | { | |
277 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
a4f5ea64 | 278 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
279 | } |
280 | ||
281 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
282 | .get_pages = i915_gem_object_get_pages_phys, | |
283 | .put_pages = i915_gem_object_put_pages_phys, | |
284 | .release = i915_gem_object_release_phys, | |
285 | }; | |
286 | ||
35a9611c | 287 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
288 | { |
289 | struct i915_vma *vma; | |
290 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
291 | int ret; |
292 | ||
293 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 294 | |
02bef8f9 CW |
295 | /* Closed vma are removed from the obj->vma_list - but they may |
296 | * still have an active binding on the object. To remove those we | |
297 | * must wait for all rendering to complete to the object (as unbinding | |
298 | * must anyway), and retire the requests. | |
aa653a68 | 299 | */ |
e95433c7 CW |
300 | ret = i915_gem_object_wait(obj, |
301 | I915_WAIT_INTERRUPTIBLE | | |
302 | I915_WAIT_LOCKED | | |
303 | I915_WAIT_ALL, | |
304 | MAX_SCHEDULE_TIMEOUT, | |
305 | NULL); | |
02bef8f9 CW |
306 | if (ret) |
307 | return ret; | |
308 | ||
309 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
310 | ||
aa653a68 CW |
311 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
312 | struct i915_vma, | |
313 | obj_link))) { | |
314 | list_move_tail(&vma->obj_link, &still_in_list); | |
315 | ret = i915_vma_unbind(vma); | |
316 | if (ret) | |
317 | break; | |
318 | } | |
319 | list_splice(&still_in_list, &obj->vma_list); | |
320 | ||
321 | return ret; | |
322 | } | |
323 | ||
e95433c7 CW |
324 | static long |
325 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
326 | unsigned int flags, | |
327 | long timeout, | |
328 | struct intel_rps_client *rps) | |
00e60f26 | 329 | { |
e95433c7 | 330 | struct drm_i915_gem_request *rq; |
00e60f26 | 331 | |
e95433c7 | 332 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 333 | |
e95433c7 CW |
334 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
335 | return timeout; | |
336 | ||
337 | if (!dma_fence_is_i915(fence)) | |
338 | return dma_fence_wait_timeout(fence, | |
339 | flags & I915_WAIT_INTERRUPTIBLE, | |
340 | timeout); | |
341 | ||
342 | rq = to_request(fence); | |
343 | if (i915_gem_request_completed(rq)) | |
344 | goto out; | |
345 | ||
346 | /* This client is about to stall waiting for the GPU. In many cases | |
347 | * this is undesirable and limits the throughput of the system, as | |
348 | * many clients cannot continue processing user input/output whilst | |
349 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
350 | * to the GPU load and thus incurs additional latency for the client. | |
351 | * We can circumvent that by promoting the GPU frequency to maximum | |
352 | * before we wait. This makes the GPU throttle up much more quickly | |
353 | * (good for benchmarks and user experience, e.g. window animations), | |
354 | * but at a cost of spending more power processing the workload | |
355 | * (bad for battery). Not all clients even want their results | |
356 | * immediately and for them we should just let the GPU select its own | |
357 | * frequency to maximise efficiency. To prevent a single client from | |
358 | * forcing the clocks too high for the whole system, we only allow | |
359 | * each client to waitboost once in a busy period. | |
360 | */ | |
361 | if (rps) { | |
362 | if (INTEL_GEN(rq->i915) >= 6) | |
363 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
364 | else | |
365 | rps = NULL; | |
00e60f26 CW |
366 | } |
367 | ||
e95433c7 CW |
368 | timeout = i915_wait_request(rq, flags, timeout); |
369 | ||
370 | out: | |
371 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
372 | i915_gem_request_retire_upto(rq); | |
373 | ||
cb399eab | 374 | if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) { |
e95433c7 CW |
375 | /* The GPU is now idle and this client has stalled. |
376 | * Since no other client has submitted a request in the | |
377 | * meantime, assume that this client is the only one | |
378 | * supplying work to the GPU but is unable to keep that | |
379 | * work supplied because it is waiting. Since the GPU is | |
380 | * then never kept fully busy, RPS autoclocking will | |
381 | * keep the clocks relatively low, causing further delays. | |
382 | * Compensate by giving the synchronous client credit for | |
383 | * a waitboost next time. | |
384 | */ | |
385 | spin_lock(&rq->i915->rps.client_lock); | |
386 | list_del_init(&rps->link); | |
387 | spin_unlock(&rq->i915->rps.client_lock); | |
388 | } | |
389 | ||
390 | return timeout; | |
391 | } | |
392 | ||
393 | static long | |
394 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
395 | unsigned int flags, | |
396 | long timeout, | |
397 | struct intel_rps_client *rps) | |
398 | { | |
399 | struct dma_fence *excl; | |
400 | ||
401 | if (flags & I915_WAIT_ALL) { | |
402 | struct dma_fence **shared; | |
403 | unsigned int count, i; | |
00e60f26 CW |
404 | int ret; |
405 | ||
e95433c7 CW |
406 | ret = reservation_object_get_fences_rcu(resv, |
407 | &excl, &count, &shared); | |
00e60f26 CW |
408 | if (ret) |
409 | return ret; | |
00e60f26 | 410 | |
e95433c7 CW |
411 | for (i = 0; i < count; i++) { |
412 | timeout = i915_gem_object_wait_fence(shared[i], | |
413 | flags, timeout, | |
414 | rps); | |
415 | if (timeout <= 0) | |
416 | break; | |
00e60f26 | 417 | |
e95433c7 CW |
418 | dma_fence_put(shared[i]); |
419 | } | |
420 | ||
421 | for (; i < count; i++) | |
422 | dma_fence_put(shared[i]); | |
423 | kfree(shared); | |
424 | } else { | |
425 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
426 | } |
427 | ||
e95433c7 CW |
428 | if (excl && timeout > 0) |
429 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); | |
430 | ||
431 | dma_fence_put(excl); | |
432 | ||
433 | return timeout; | |
00e60f26 CW |
434 | } |
435 | ||
e95433c7 CW |
436 | /** |
437 | * Waits for rendering to the object to be completed | |
438 | * @obj: i915 gem object | |
439 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
440 | * @timeout: how long to wait | |
441 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 442 | */ |
e95433c7 CW |
443 | int |
444 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
445 | unsigned int flags, | |
446 | long timeout, | |
447 | struct intel_rps_client *rps) | |
00e60f26 | 448 | { |
e95433c7 CW |
449 | might_sleep(); |
450 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
451 | GEM_BUG_ON(debug_locks && | |
452 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
453 | !!(flags & I915_WAIT_LOCKED)); | |
454 | #endif | |
455 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 456 | |
d07f0e59 CW |
457 | timeout = i915_gem_object_wait_reservation(obj->resv, |
458 | flags, timeout, | |
459 | rps); | |
e95433c7 | 460 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
461 | } |
462 | ||
463 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
464 | { | |
465 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
466 | ||
467 | return &fpriv->rps; | |
468 | } | |
469 | ||
00731155 CW |
470 | int |
471 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
472 | int align) | |
473 | { | |
474 | drm_dma_handle_t *phys; | |
6a2c4232 | 475 | int ret; |
00731155 CW |
476 | |
477 | if (obj->phys_handle) { | |
478 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
479 | return -EBUSY; | |
480 | ||
481 | return 0; | |
482 | } | |
483 | ||
a4f5ea64 | 484 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
485 | return -EFAULT; |
486 | ||
487 | if (obj->base.filp == NULL) | |
488 | return -EINVAL; | |
489 | ||
4717ca9e CW |
490 | ret = i915_gem_object_unbind(obj); |
491 | if (ret) | |
492 | return ret; | |
493 | ||
548625ee | 494 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
495 | if (obj->mm.pages) |
496 | return -EBUSY; | |
6a2c4232 | 497 | |
00731155 CW |
498 | /* create a new object */ |
499 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
500 | if (!phys) | |
501 | return -ENOMEM; | |
502 | ||
00731155 | 503 | obj->phys_handle = phys; |
6a2c4232 CW |
504 | obj->ops = &i915_gem_phys_ops; |
505 | ||
a4f5ea64 | 506 | return i915_gem_object_pin_pages(obj); |
00731155 CW |
507 | } |
508 | ||
509 | static int | |
510 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
511 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 512 | struct drm_file *file) |
00731155 CW |
513 | { |
514 | struct drm_device *dev = obj->base.dev; | |
515 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 516 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
e95433c7 | 517 | int ret; |
6a2c4232 CW |
518 | |
519 | /* We manually control the domain here and pretend that it | |
520 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
521 | */ | |
e95433c7 CW |
522 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
523 | ret = i915_gem_object_wait(obj, | |
524 | I915_WAIT_INTERRUPTIBLE | | |
525 | I915_WAIT_LOCKED | | |
526 | I915_WAIT_ALL, | |
527 | MAX_SCHEDULE_TIMEOUT, | |
03ac84f1 | 528 | to_rps_client(file)); |
6a2c4232 CW |
529 | if (ret) |
530 | return ret; | |
00731155 | 531 | |
77a0d1ca | 532 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
533 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
534 | unsigned long unwritten; | |
535 | ||
536 | /* The physical object once assigned is fixed for the lifetime | |
537 | * of the obj, so we can safely drop the lock and continue | |
538 | * to access vaddr. | |
539 | */ | |
540 | mutex_unlock(&dev->struct_mutex); | |
541 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
542 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
543 | if (unwritten) { |
544 | ret = -EFAULT; | |
545 | goto out; | |
546 | } | |
00731155 CW |
547 | } |
548 | ||
6a2c4232 | 549 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 550 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
551 | |
552 | out: | |
de152b62 | 553 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 554 | return ret; |
00731155 CW |
555 | } |
556 | ||
42dcedd4 CW |
557 | void *i915_gem_object_alloc(struct drm_device *dev) |
558 | { | |
fac5e23e | 559 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 560 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
561 | } |
562 | ||
563 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
564 | { | |
fac5e23e | 565 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 566 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
567 | } |
568 | ||
ff72145b DA |
569 | static int |
570 | i915_gem_create(struct drm_file *file, | |
571 | struct drm_device *dev, | |
572 | uint64_t size, | |
573 | uint32_t *handle_p) | |
673a394b | 574 | { |
05394f39 | 575 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
576 | int ret; |
577 | u32 handle; | |
673a394b | 578 | |
ff72145b | 579 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
580 | if (size == 0) |
581 | return -EINVAL; | |
673a394b EA |
582 | |
583 | /* Allocate the new object */ | |
d37cd8a8 | 584 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
585 | if (IS_ERR(obj)) |
586 | return PTR_ERR(obj); | |
673a394b | 587 | |
05394f39 | 588 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 589 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 590 | i915_gem_object_put(obj); |
d861e338 DV |
591 | if (ret) |
592 | return ret; | |
202f2fef | 593 | |
ff72145b | 594 | *handle_p = handle; |
673a394b EA |
595 | return 0; |
596 | } | |
597 | ||
ff72145b DA |
598 | int |
599 | i915_gem_dumb_create(struct drm_file *file, | |
600 | struct drm_device *dev, | |
601 | struct drm_mode_create_dumb *args) | |
602 | { | |
603 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 604 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
605 | args->size = args->pitch * args->height; |
606 | return i915_gem_create(file, dev, | |
da6b51d0 | 607 | args->size, &args->handle); |
ff72145b DA |
608 | } |
609 | ||
ff72145b DA |
610 | /** |
611 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
612 | * @dev: drm device pointer |
613 | * @data: ioctl data blob | |
614 | * @file: drm file pointer | |
ff72145b DA |
615 | */ |
616 | int | |
617 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
618 | struct drm_file *file) | |
619 | { | |
620 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 621 | |
fbbd37b3 CW |
622 | i915_gem_flush_free_objects(to_i915(dev)); |
623 | ||
ff72145b | 624 | return i915_gem_create(file, dev, |
da6b51d0 | 625 | args->size, &args->handle); |
ff72145b DA |
626 | } |
627 | ||
8461d226 DV |
628 | static inline int |
629 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
630 | const char *gpu_vaddr, int gpu_offset, | |
631 | int length) | |
632 | { | |
633 | int ret, cpu_offset = 0; | |
634 | ||
635 | while (length > 0) { | |
636 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
637 | int this_length = min(cacheline_end - gpu_offset, length); | |
638 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
639 | ||
640 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
641 | gpu_vaddr + swizzled_gpu_offset, | |
642 | this_length); | |
643 | if (ret) | |
644 | return ret + length; | |
645 | ||
646 | cpu_offset += this_length; | |
647 | gpu_offset += this_length; | |
648 | length -= this_length; | |
649 | } | |
650 | ||
651 | return 0; | |
652 | } | |
653 | ||
8c59967c | 654 | static inline int |
4f0c7cfb BW |
655 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
656 | const char __user *cpu_vaddr, | |
8c59967c DV |
657 | int length) |
658 | { | |
659 | int ret, cpu_offset = 0; | |
660 | ||
661 | while (length > 0) { | |
662 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
663 | int this_length = min(cacheline_end - gpu_offset, length); | |
664 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
665 | ||
666 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
667 | cpu_vaddr + cpu_offset, | |
668 | this_length); | |
669 | if (ret) | |
670 | return ret + length; | |
671 | ||
672 | cpu_offset += this_length; | |
673 | gpu_offset += this_length; | |
674 | length -= this_length; | |
675 | } | |
676 | ||
677 | return 0; | |
678 | } | |
679 | ||
4c914c0c BV |
680 | /* |
681 | * Pins the specified object's pages and synchronizes the object with | |
682 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
683 | * flush the object from the CPU cache. | |
684 | */ | |
685 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 686 | unsigned int *needs_clflush) |
4c914c0c BV |
687 | { |
688 | int ret; | |
689 | ||
e95433c7 | 690 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 691 | |
e95433c7 | 692 | *needs_clflush = 0; |
43394c7d CW |
693 | if (!i915_gem_object_has_struct_page(obj)) |
694 | return -ENODEV; | |
4c914c0c | 695 | |
e95433c7 CW |
696 | ret = i915_gem_object_wait(obj, |
697 | I915_WAIT_INTERRUPTIBLE | | |
698 | I915_WAIT_LOCKED, | |
699 | MAX_SCHEDULE_TIMEOUT, | |
700 | NULL); | |
c13d87ea CW |
701 | if (ret) |
702 | return ret; | |
703 | ||
a4f5ea64 | 704 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
705 | if (ret) |
706 | return ret; | |
707 | ||
a314d5cb CW |
708 | i915_gem_object_flush_gtt_write_domain(obj); |
709 | ||
43394c7d CW |
710 | /* If we're not in the cpu read domain, set ourself into the gtt |
711 | * read domain and manually flush cachelines (if required). This | |
712 | * optimizes for the case when the gpu will dirty the data | |
713 | * anyway again before the next pread happens. | |
714 | */ | |
715 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
716 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
717 | obj->cache_level); | |
43394c7d | 718 | |
43394c7d CW |
719 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
720 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
721 | if (ret) |
722 | goto err_unpin; | |
723 | ||
43394c7d | 724 | *needs_clflush = 0; |
4c914c0c BV |
725 | } |
726 | ||
9764951e | 727 | /* return with the pages pinned */ |
43394c7d | 728 | return 0; |
9764951e CW |
729 | |
730 | err_unpin: | |
731 | i915_gem_object_unpin_pages(obj); | |
732 | return ret; | |
43394c7d CW |
733 | } |
734 | ||
735 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
736 | unsigned int *needs_clflush) | |
737 | { | |
738 | int ret; | |
739 | ||
e95433c7 CW |
740 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
741 | ||
43394c7d CW |
742 | *needs_clflush = 0; |
743 | if (!i915_gem_object_has_struct_page(obj)) | |
744 | return -ENODEV; | |
745 | ||
e95433c7 CW |
746 | ret = i915_gem_object_wait(obj, |
747 | I915_WAIT_INTERRUPTIBLE | | |
748 | I915_WAIT_LOCKED | | |
749 | I915_WAIT_ALL, | |
750 | MAX_SCHEDULE_TIMEOUT, | |
751 | NULL); | |
43394c7d CW |
752 | if (ret) |
753 | return ret; | |
754 | ||
a4f5ea64 | 755 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
756 | if (ret) |
757 | return ret; | |
758 | ||
a314d5cb CW |
759 | i915_gem_object_flush_gtt_write_domain(obj); |
760 | ||
43394c7d CW |
761 | /* If we're not in the cpu write domain, set ourself into the |
762 | * gtt write domain and manually flush cachelines (as required). | |
763 | * This optimizes for the case when the gpu will use the data | |
764 | * right away and we therefore have to clflush anyway. | |
765 | */ | |
766 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
767 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
768 | ||
769 | /* Same trick applies to invalidate partially written cachelines read | |
770 | * before writing. | |
771 | */ | |
772 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
773 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
774 | obj->cache_level); | |
775 | ||
43394c7d CW |
776 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
777 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
778 | if (ret) |
779 | goto err_unpin; | |
780 | ||
43394c7d CW |
781 | *needs_clflush = 0; |
782 | } | |
783 | ||
784 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
785 | obj->cache_dirty = true; | |
786 | ||
787 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
a4f5ea64 | 788 | obj->mm.dirty = true; |
9764951e | 789 | /* return with the pages pinned */ |
43394c7d | 790 | return 0; |
9764951e CW |
791 | |
792 | err_unpin: | |
793 | i915_gem_object_unpin_pages(obj); | |
794 | return ret; | |
4c914c0c BV |
795 | } |
796 | ||
23c18c71 DV |
797 | static void |
798 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
799 | bool swizzled) | |
800 | { | |
e7e58eb5 | 801 | if (unlikely(swizzled)) { |
23c18c71 DV |
802 | unsigned long start = (unsigned long) addr; |
803 | unsigned long end = (unsigned long) addr + length; | |
804 | ||
805 | /* For swizzling simply ensure that we always flush both | |
806 | * channels. Lame, but simple and it works. Swizzled | |
807 | * pwrite/pread is far from a hotpath - current userspace | |
808 | * doesn't use it at all. */ | |
809 | start = round_down(start, 128); | |
810 | end = round_up(end, 128); | |
811 | ||
812 | drm_clflush_virt_range((void *)start, end - start); | |
813 | } else { | |
814 | drm_clflush_virt_range(addr, length); | |
815 | } | |
816 | ||
817 | } | |
818 | ||
d174bd64 DV |
819 | /* Only difference to the fast-path function is that this can handle bit17 |
820 | * and uses non-atomic copy and kmap functions. */ | |
821 | static int | |
bb6dc8d9 | 822 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
823 | char __user *user_data, |
824 | bool page_do_bit17_swizzling, bool needs_clflush) | |
825 | { | |
826 | char *vaddr; | |
827 | int ret; | |
828 | ||
829 | vaddr = kmap(page); | |
830 | if (needs_clflush) | |
bb6dc8d9 | 831 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 832 | page_do_bit17_swizzling); |
d174bd64 DV |
833 | |
834 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 835 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 836 | else |
bb6dc8d9 | 837 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
838 | kunmap(page); |
839 | ||
f60d7f0c | 840 | return ret ? - EFAULT : 0; |
d174bd64 DV |
841 | } |
842 | ||
bb6dc8d9 CW |
843 | static int |
844 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
845 | bool page_do_bit17_swizzling, bool needs_clflush) | |
846 | { | |
847 | int ret; | |
848 | ||
849 | ret = -ENODEV; | |
850 | if (!page_do_bit17_swizzling) { | |
851 | char *vaddr = kmap_atomic(page); | |
852 | ||
853 | if (needs_clflush) | |
854 | drm_clflush_virt_range(vaddr + offset, length); | |
855 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
856 | kunmap_atomic(vaddr); | |
857 | } | |
858 | if (ret == 0) | |
859 | return 0; | |
860 | ||
861 | return shmem_pread_slow(page, offset, length, user_data, | |
862 | page_do_bit17_swizzling, needs_clflush); | |
863 | } | |
864 | ||
865 | static int | |
866 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
867 | struct drm_i915_gem_pread *args) | |
868 | { | |
869 | char __user *user_data; | |
870 | u64 remain; | |
871 | unsigned int obj_do_bit17_swizzling; | |
872 | unsigned int needs_clflush; | |
873 | unsigned int idx, offset; | |
874 | int ret; | |
875 | ||
876 | obj_do_bit17_swizzling = 0; | |
877 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
878 | obj_do_bit17_swizzling = BIT(17); | |
879 | ||
880 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
881 | if (ret) | |
882 | return ret; | |
883 | ||
884 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
885 | mutex_unlock(&obj->base.dev->struct_mutex); | |
886 | if (ret) | |
887 | return ret; | |
888 | ||
889 | remain = args->size; | |
890 | user_data = u64_to_user_ptr(args->data_ptr); | |
891 | offset = offset_in_page(args->offset); | |
892 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
893 | struct page *page = i915_gem_object_get_page(obj, idx); | |
894 | int length; | |
895 | ||
896 | length = remain; | |
897 | if (offset + length > PAGE_SIZE) | |
898 | length = PAGE_SIZE - offset; | |
899 | ||
900 | ret = shmem_pread(page, offset, length, user_data, | |
901 | page_to_phys(page) & obj_do_bit17_swizzling, | |
902 | needs_clflush); | |
903 | if (ret) | |
904 | break; | |
905 | ||
906 | remain -= length; | |
907 | user_data += length; | |
908 | offset = 0; | |
909 | } | |
910 | ||
911 | i915_gem_obj_finish_shmem_access(obj); | |
912 | return ret; | |
913 | } | |
914 | ||
915 | static inline bool | |
916 | gtt_user_read(struct io_mapping *mapping, | |
917 | loff_t base, int offset, | |
918 | char __user *user_data, int length) | |
b50a5371 | 919 | { |
b50a5371 | 920 | void *vaddr; |
bb6dc8d9 | 921 | unsigned long unwritten; |
b50a5371 | 922 | |
b50a5371 | 923 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
924 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
925 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
926 | io_mapping_unmap_atomic(vaddr); | |
927 | if (unwritten) { | |
928 | vaddr = (void __force *) | |
929 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
930 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
931 | io_mapping_unmap(vaddr); | |
932 | } | |
b50a5371 AS |
933 | return unwritten; |
934 | } | |
935 | ||
936 | static int | |
bb6dc8d9 CW |
937 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
938 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 939 | { |
bb6dc8d9 CW |
940 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
941 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 942 | struct drm_mm_node node; |
bb6dc8d9 CW |
943 | struct i915_vma *vma; |
944 | void __user *user_data; | |
945 | u64 remain, offset; | |
b50a5371 AS |
946 | int ret; |
947 | ||
bb6dc8d9 CW |
948 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
949 | if (ret) | |
950 | return ret; | |
951 | ||
952 | intel_runtime_pm_get(i915); | |
953 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
954 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
955 | if (!IS_ERR(vma)) { |
956 | node.start = i915_ggtt_offset(vma); | |
957 | node.allocated = false; | |
49ef5294 | 958 | ret = i915_vma_put_fence(vma); |
18034584 CW |
959 | if (ret) { |
960 | i915_vma_unpin(vma); | |
961 | vma = ERR_PTR(ret); | |
962 | } | |
963 | } | |
058d88c4 | 964 | if (IS_ERR(vma)) { |
bb6dc8d9 | 965 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 966 | if (ret) |
bb6dc8d9 CW |
967 | goto out_unlock; |
968 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
969 | } |
970 | ||
971 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
972 | if (ret) | |
973 | goto out_unpin; | |
974 | ||
bb6dc8d9 | 975 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 976 | |
bb6dc8d9 CW |
977 | user_data = u64_to_user_ptr(args->data_ptr); |
978 | remain = args->size; | |
979 | offset = args->offset; | |
b50a5371 AS |
980 | |
981 | while (remain > 0) { | |
982 | /* Operation in this page | |
983 | * | |
984 | * page_base = page offset within aperture | |
985 | * page_offset = offset within page | |
986 | * page_length = bytes to copy for this page | |
987 | */ | |
988 | u32 page_base = node.start; | |
989 | unsigned page_offset = offset_in_page(offset); | |
990 | unsigned page_length = PAGE_SIZE - page_offset; | |
991 | page_length = remain < page_length ? remain : page_length; | |
992 | if (node.allocated) { | |
993 | wmb(); | |
994 | ggtt->base.insert_page(&ggtt->base, | |
995 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 996 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
997 | wmb(); |
998 | } else { | |
999 | page_base += offset & PAGE_MASK; | |
1000 | } | |
bb6dc8d9 CW |
1001 | |
1002 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1003 | user_data, page_length)) { | |
b50a5371 AS |
1004 | ret = -EFAULT; |
1005 | break; | |
1006 | } | |
1007 | ||
1008 | remain -= page_length; | |
1009 | user_data += page_length; | |
1010 | offset += page_length; | |
1011 | } | |
1012 | ||
bb6dc8d9 | 1013 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1014 | out_unpin: |
1015 | if (node.allocated) { | |
1016 | wmb(); | |
1017 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1018 | node.start, node.size); |
b50a5371 AS |
1019 | remove_mappable_node(&node); |
1020 | } else { | |
058d88c4 | 1021 | i915_vma_unpin(vma); |
b50a5371 | 1022 | } |
bb6dc8d9 CW |
1023 | out_unlock: |
1024 | intel_runtime_pm_put(i915); | |
1025 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1026 | |
eb01459f EA |
1027 | return ret; |
1028 | } | |
1029 | ||
673a394b EA |
1030 | /** |
1031 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1032 | * @dev: drm device pointer |
1033 | * @data: ioctl data blob | |
1034 | * @file: drm file pointer | |
673a394b EA |
1035 | * |
1036 | * On error, the contents of *data are undefined. | |
1037 | */ | |
1038 | int | |
1039 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1040 | struct drm_file *file) |
673a394b EA |
1041 | { |
1042 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1043 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1044 | int ret; |
673a394b | 1045 | |
51311d0a CW |
1046 | if (args->size == 0) |
1047 | return 0; | |
1048 | ||
1049 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1050 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1051 | args->size)) |
1052 | return -EFAULT; | |
1053 | ||
03ac0642 | 1054 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1055 | if (!obj) |
1056 | return -ENOENT; | |
673a394b | 1057 | |
7dcd2499 | 1058 | /* Bounds check source. */ |
05394f39 CW |
1059 | if (args->offset > obj->base.size || |
1060 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1061 | ret = -EINVAL; |
bb6dc8d9 | 1062 | goto out; |
ce9d419d CW |
1063 | } |
1064 | ||
db53a302 CW |
1065 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1066 | ||
e95433c7 CW |
1067 | ret = i915_gem_object_wait(obj, |
1068 | I915_WAIT_INTERRUPTIBLE, | |
1069 | MAX_SCHEDULE_TIMEOUT, | |
1070 | to_rps_client(file)); | |
258a5ede | 1071 | if (ret) |
bb6dc8d9 | 1072 | goto out; |
258a5ede | 1073 | |
bb6dc8d9 | 1074 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1075 | if (ret) |
bb6dc8d9 | 1076 | goto out; |
673a394b | 1077 | |
bb6dc8d9 | 1078 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1079 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1080 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1081 | |
bb6dc8d9 CW |
1082 | i915_gem_object_unpin_pages(obj); |
1083 | out: | |
f0cd5182 | 1084 | i915_gem_object_put(obj); |
eb01459f | 1085 | return ret; |
673a394b EA |
1086 | } |
1087 | ||
0839ccb8 KP |
1088 | /* This is the fast write path which cannot handle |
1089 | * page faults in the source data | |
9b7530cc | 1090 | */ |
0839ccb8 | 1091 | |
fe115628 CW |
1092 | static inline bool |
1093 | ggtt_write(struct io_mapping *mapping, | |
1094 | loff_t base, int offset, | |
1095 | char __user *user_data, int length) | |
9b7530cc | 1096 | { |
4f0c7cfb | 1097 | void *vaddr; |
0839ccb8 | 1098 | unsigned long unwritten; |
9b7530cc | 1099 | |
4f0c7cfb | 1100 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1101 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1102 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1103 | user_data, length); |
fe115628 CW |
1104 | io_mapping_unmap_atomic(vaddr); |
1105 | if (unwritten) { | |
1106 | vaddr = (void __force *) | |
1107 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1108 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1109 | io_mapping_unmap(vaddr); | |
1110 | } | |
bb6dc8d9 | 1111 | |
bb6dc8d9 CW |
1112 | return unwritten; |
1113 | } | |
1114 | ||
3de09aa3 EA |
1115 | /** |
1116 | * This is the fast pwrite path, where we copy the data directly from the | |
1117 | * user into the GTT, uncached. | |
fe115628 | 1118 | * @obj: i915 GEM object |
14bb2c11 | 1119 | * @args: pwrite arguments structure |
3de09aa3 | 1120 | */ |
673a394b | 1121 | static int |
fe115628 CW |
1122 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1123 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1124 | { |
fe115628 | 1125 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1126 | struct i915_ggtt *ggtt = &i915->ggtt; |
1127 | struct drm_mm_node node; | |
fe115628 CW |
1128 | struct i915_vma *vma; |
1129 | u64 remain, offset; | |
1130 | void __user *user_data; | |
4f1959ee | 1131 | int ret; |
b50a5371 | 1132 | |
fe115628 CW |
1133 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1134 | if (ret) | |
1135 | return ret; | |
935aaa69 | 1136 | |
9c870d03 | 1137 | intel_runtime_pm_get(i915); |
058d88c4 | 1138 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1139 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1140 | if (!IS_ERR(vma)) { |
1141 | node.start = i915_ggtt_offset(vma); | |
1142 | node.allocated = false; | |
49ef5294 | 1143 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1144 | if (ret) { |
1145 | i915_vma_unpin(vma); | |
1146 | vma = ERR_PTR(ret); | |
1147 | } | |
1148 | } | |
058d88c4 | 1149 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1150 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1151 | if (ret) |
fe115628 CW |
1152 | goto out_unlock; |
1153 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1154 | } |
935aaa69 DV |
1155 | |
1156 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1157 | if (ret) | |
1158 | goto out_unpin; | |
1159 | ||
fe115628 CW |
1160 | mutex_unlock(&i915->drm.struct_mutex); |
1161 | ||
b19482d7 | 1162 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1163 | |
4f1959ee AS |
1164 | user_data = u64_to_user_ptr(args->data_ptr); |
1165 | offset = args->offset; | |
1166 | remain = args->size; | |
1167 | while (remain) { | |
673a394b EA |
1168 | /* Operation in this page |
1169 | * | |
0839ccb8 KP |
1170 | * page_base = page offset within aperture |
1171 | * page_offset = offset within page | |
1172 | * page_length = bytes to copy for this page | |
673a394b | 1173 | */ |
4f1959ee | 1174 | u32 page_base = node.start; |
bb6dc8d9 CW |
1175 | unsigned int page_offset = offset_in_page(offset); |
1176 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1177 | page_length = remain < page_length ? remain : page_length; |
1178 | if (node.allocated) { | |
1179 | wmb(); /* flush the write before we modify the GGTT */ | |
1180 | ggtt->base.insert_page(&ggtt->base, | |
1181 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1182 | node.start, I915_CACHE_NONE, 0); | |
1183 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1184 | } else { | |
1185 | page_base += offset & PAGE_MASK; | |
1186 | } | |
0839ccb8 | 1187 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1188 | * source page isn't available. Return the error and we'll |
1189 | * retry in the slow path. | |
b50a5371 AS |
1190 | * If the object is non-shmem backed, we retry again with the |
1191 | * path that handles page fault. | |
0839ccb8 | 1192 | */ |
fe115628 CW |
1193 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1194 | user_data, page_length)) { | |
1195 | ret = -EFAULT; | |
1196 | break; | |
935aaa69 | 1197 | } |
673a394b | 1198 | |
0839ccb8 KP |
1199 | remain -= page_length; |
1200 | user_data += page_length; | |
1201 | offset += page_length; | |
673a394b | 1202 | } |
b19482d7 | 1203 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 CW |
1204 | |
1205 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1206 | out_unpin: |
4f1959ee AS |
1207 | if (node.allocated) { |
1208 | wmb(); | |
1209 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1210 | node.start, node.size); |
4f1959ee AS |
1211 | remove_mappable_node(&node); |
1212 | } else { | |
058d88c4 | 1213 | i915_vma_unpin(vma); |
4f1959ee | 1214 | } |
fe115628 | 1215 | out_unlock: |
9c870d03 | 1216 | intel_runtime_pm_put(i915); |
fe115628 | 1217 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1218 | return ret; |
673a394b EA |
1219 | } |
1220 | ||
3043c60c | 1221 | static int |
fe115628 | 1222 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1223 | char __user *user_data, |
1224 | bool page_do_bit17_swizzling, | |
1225 | bool needs_clflush_before, | |
1226 | bool needs_clflush_after) | |
673a394b | 1227 | { |
d174bd64 DV |
1228 | char *vaddr; |
1229 | int ret; | |
e5281ccd | 1230 | |
d174bd64 | 1231 | vaddr = kmap(page); |
e7e58eb5 | 1232 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1233 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1234 | page_do_bit17_swizzling); |
d174bd64 | 1235 | if (page_do_bit17_swizzling) |
fe115628 CW |
1236 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1237 | length); | |
d174bd64 | 1238 | else |
fe115628 | 1239 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1240 | if (needs_clflush_after) |
fe115628 | 1241 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1242 | page_do_bit17_swizzling); |
d174bd64 | 1243 | kunmap(page); |
40123c1f | 1244 | |
755d2218 | 1245 | return ret ? -EFAULT : 0; |
40123c1f EA |
1246 | } |
1247 | ||
fe115628 CW |
1248 | /* Per-page copy function for the shmem pwrite fastpath. |
1249 | * Flushes invalid cachelines before writing to the target if | |
1250 | * needs_clflush_before is set and flushes out any written cachelines after | |
1251 | * writing if needs_clflush is set. | |
1252 | */ | |
40123c1f | 1253 | static int |
fe115628 CW |
1254 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1255 | bool page_do_bit17_swizzling, | |
1256 | bool needs_clflush_before, | |
1257 | bool needs_clflush_after) | |
40123c1f | 1258 | { |
fe115628 CW |
1259 | int ret; |
1260 | ||
1261 | ret = -ENODEV; | |
1262 | if (!page_do_bit17_swizzling) { | |
1263 | char *vaddr = kmap_atomic(page); | |
1264 | ||
1265 | if (needs_clflush_before) | |
1266 | drm_clflush_virt_range(vaddr + offset, len); | |
1267 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1268 | if (needs_clflush_after) | |
1269 | drm_clflush_virt_range(vaddr + offset, len); | |
1270 | ||
1271 | kunmap_atomic(vaddr); | |
1272 | } | |
1273 | if (ret == 0) | |
1274 | return ret; | |
1275 | ||
1276 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1277 | page_do_bit17_swizzling, | |
1278 | needs_clflush_before, | |
1279 | needs_clflush_after); | |
1280 | } | |
1281 | ||
1282 | static int | |
1283 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1284 | const struct drm_i915_gem_pwrite *args) | |
1285 | { | |
1286 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1287 | void __user *user_data; | |
1288 | u64 remain; | |
1289 | unsigned int obj_do_bit17_swizzling; | |
1290 | unsigned int partial_cacheline_write; | |
43394c7d | 1291 | unsigned int needs_clflush; |
fe115628 CW |
1292 | unsigned int offset, idx; |
1293 | int ret; | |
40123c1f | 1294 | |
fe115628 | 1295 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1296 | if (ret) |
1297 | return ret; | |
1298 | ||
fe115628 CW |
1299 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1300 | mutex_unlock(&i915->drm.struct_mutex); | |
1301 | if (ret) | |
1302 | return ret; | |
673a394b | 1303 | |
fe115628 CW |
1304 | obj_do_bit17_swizzling = 0; |
1305 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1306 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1307 | |
fe115628 CW |
1308 | /* If we don't overwrite a cacheline completely we need to be |
1309 | * careful to have up-to-date data by first clflushing. Don't | |
1310 | * overcomplicate things and flush the entire patch. | |
1311 | */ | |
1312 | partial_cacheline_write = 0; | |
1313 | if (needs_clflush & CLFLUSH_BEFORE) | |
1314 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1315 | |
fe115628 CW |
1316 | user_data = u64_to_user_ptr(args->data_ptr); |
1317 | remain = args->size; | |
1318 | offset = offset_in_page(args->offset); | |
1319 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1320 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1321 | int length; | |
40123c1f | 1322 | |
fe115628 CW |
1323 | length = remain; |
1324 | if (offset + length > PAGE_SIZE) | |
1325 | length = PAGE_SIZE - offset; | |
755d2218 | 1326 | |
fe115628 CW |
1327 | ret = shmem_pwrite(page, offset, length, user_data, |
1328 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1329 | (offset | length) & partial_cacheline_write, | |
1330 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1331 | if (ret) |
fe115628 | 1332 | break; |
755d2218 | 1333 | |
fe115628 CW |
1334 | remain -= length; |
1335 | user_data += length; | |
1336 | offset = 0; | |
8c59967c | 1337 | } |
673a394b | 1338 | |
de152b62 | 1339 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 | 1340 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1341 | return ret; |
673a394b EA |
1342 | } |
1343 | ||
1344 | /** | |
1345 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1346 | * @dev: drm device |
1347 | * @data: ioctl data blob | |
1348 | * @file: drm file | |
673a394b EA |
1349 | * |
1350 | * On error, the contents of the buffer that were to be modified are undefined. | |
1351 | */ | |
1352 | int | |
1353 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1354 | struct drm_file *file) |
673a394b EA |
1355 | { |
1356 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1357 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1358 | int ret; |
1359 | ||
1360 | if (args->size == 0) | |
1361 | return 0; | |
1362 | ||
1363 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1364 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1365 | args->size)) |
1366 | return -EFAULT; | |
1367 | ||
03ac0642 | 1368 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1369 | if (!obj) |
1370 | return -ENOENT; | |
673a394b | 1371 | |
7dcd2499 | 1372 | /* Bounds check destination. */ |
05394f39 CW |
1373 | if (args->offset > obj->base.size || |
1374 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1375 | ret = -EINVAL; |
258a5ede | 1376 | goto err; |
ce9d419d CW |
1377 | } |
1378 | ||
db53a302 CW |
1379 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1380 | ||
e95433c7 CW |
1381 | ret = i915_gem_object_wait(obj, |
1382 | I915_WAIT_INTERRUPTIBLE | | |
1383 | I915_WAIT_ALL, | |
1384 | MAX_SCHEDULE_TIMEOUT, | |
1385 | to_rps_client(file)); | |
258a5ede CW |
1386 | if (ret) |
1387 | goto err; | |
1388 | ||
fe115628 | 1389 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1390 | if (ret) |
fe115628 | 1391 | goto err; |
258a5ede | 1392 | |
935aaa69 | 1393 | ret = -EFAULT; |
673a394b EA |
1394 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1395 | * it would end up going through the fenced access, and we'll get | |
1396 | * different detiling behavior between reading and writing. | |
1397 | * pread/pwrite currently are reading and writing from the CPU | |
1398 | * perspective, requiring manual detiling by the client. | |
1399 | */ | |
6eae0059 | 1400 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1401 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1402 | /* Note that the gtt paths might fail with non-page-backed user |
1403 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1404 | * textures). Fallback to the shmem path in that case. |
1405 | */ | |
fe115628 | 1406 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1407 | |
d1054ee4 | 1408 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1409 | if (obj->phys_handle) |
1410 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1411 | else |
fe115628 | 1412 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1413 | } |
5c0480f2 | 1414 | |
fe115628 | 1415 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1416 | err: |
f0cd5182 | 1417 | i915_gem_object_put(obj); |
258a5ede | 1418 | return ret; |
673a394b EA |
1419 | } |
1420 | ||
d243ad82 | 1421 | static inline enum fb_op_origin |
aeecc969 CW |
1422 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1423 | { | |
50349247 CW |
1424 | return (domain == I915_GEM_DOMAIN_GTT ? |
1425 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1426 | } |
1427 | ||
40e62d5d CW |
1428 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1429 | { | |
1430 | struct drm_i915_private *i915; | |
1431 | struct list_head *list; | |
1432 | struct i915_vma *vma; | |
1433 | ||
1434 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1435 | if (!i915_vma_is_ggtt(vma)) | |
1436 | continue; | |
1437 | ||
1438 | if (i915_vma_is_active(vma)) | |
1439 | continue; | |
1440 | ||
1441 | if (!drm_mm_node_allocated(&vma->node)) | |
1442 | continue; | |
1443 | ||
1444 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1445 | } | |
1446 | ||
1447 | i915 = to_i915(obj->base.dev); | |
1448 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1449 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1450 | } |
1451 | ||
673a394b | 1452 | /** |
2ef7eeaa EA |
1453 | * Called when user space prepares to use an object with the CPU, either |
1454 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1455 | * @dev: drm device |
1456 | * @data: ioctl data blob | |
1457 | * @file: drm file | |
673a394b EA |
1458 | */ |
1459 | int | |
1460 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1461 | struct drm_file *file) |
673a394b EA |
1462 | { |
1463 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1464 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1465 | uint32_t read_domains = args->read_domains; |
1466 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1467 | int err; |
673a394b | 1468 | |
2ef7eeaa | 1469 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1470 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1471 | return -EINVAL; |
1472 | ||
1473 | /* Having something in the write domain implies it's in the read | |
1474 | * domain, and only that read domain. Enforce that in the request. | |
1475 | */ | |
1476 | if (write_domain != 0 && read_domains != write_domain) | |
1477 | return -EINVAL; | |
1478 | ||
03ac0642 | 1479 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1480 | if (!obj) |
1481 | return -ENOENT; | |
673a394b | 1482 | |
3236f57a CW |
1483 | /* Try to flush the object off the GPU without holding the lock. |
1484 | * We will repeat the flush holding the lock in the normal manner | |
1485 | * to catch cases where we are gazumped. | |
1486 | */ | |
40e62d5d | 1487 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1488 | I915_WAIT_INTERRUPTIBLE | |
1489 | (write_domain ? I915_WAIT_ALL : 0), | |
1490 | MAX_SCHEDULE_TIMEOUT, | |
1491 | to_rps_client(file)); | |
40e62d5d | 1492 | if (err) |
f0cd5182 | 1493 | goto out; |
b8f9096d | 1494 | |
40e62d5d CW |
1495 | /* Flush and acquire obj->pages so that we are coherent through |
1496 | * direct access in memory with previous cached writes through | |
1497 | * shmemfs and that our cache domain tracking remains valid. | |
1498 | * For example, if the obj->filp was moved to swap without us | |
1499 | * being notified and releasing the pages, we would mistakenly | |
1500 | * continue to assume that the obj remained out of the CPU cached | |
1501 | * domain. | |
1502 | */ | |
1503 | err = i915_gem_object_pin_pages(obj); | |
1504 | if (err) | |
f0cd5182 | 1505 | goto out; |
40e62d5d CW |
1506 | |
1507 | err = i915_mutex_lock_interruptible(dev); | |
1508 | if (err) | |
f0cd5182 | 1509 | goto out_unpin; |
3236f57a | 1510 | |
43566ded | 1511 | if (read_domains & I915_GEM_DOMAIN_GTT) |
40e62d5d | 1512 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1513 | else |
40e62d5d | 1514 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1515 | |
40e62d5d CW |
1516 | /* And bump the LRU for this access */ |
1517 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1518 | |
673a394b | 1519 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1520 | |
40e62d5d CW |
1521 | if (write_domain != 0) |
1522 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); | |
1523 | ||
f0cd5182 | 1524 | out_unpin: |
40e62d5d | 1525 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1526 | out: |
1527 | i915_gem_object_put(obj); | |
40e62d5d | 1528 | return err; |
673a394b EA |
1529 | } |
1530 | ||
1531 | /** | |
1532 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1533 | * @dev: drm device |
1534 | * @data: ioctl data blob | |
1535 | * @file: drm file | |
673a394b EA |
1536 | */ |
1537 | int | |
1538 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1539 | struct drm_file *file) |
673a394b EA |
1540 | { |
1541 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1542 | struct drm_i915_gem_object *obj; |
c21724cc | 1543 | int err = 0; |
1d7cfea1 | 1544 | |
03ac0642 | 1545 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1546 | if (!obj) |
1547 | return -ENOENT; | |
673a394b | 1548 | |
673a394b | 1549 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1550 | if (READ_ONCE(obj->pin_display)) { |
1551 | err = i915_mutex_lock_interruptible(dev); | |
1552 | if (!err) { | |
1553 | i915_gem_object_flush_cpu_write_domain(obj); | |
1554 | mutex_unlock(&dev->struct_mutex); | |
1555 | } | |
1556 | } | |
e47c68e9 | 1557 | |
f0cd5182 | 1558 | i915_gem_object_put(obj); |
c21724cc | 1559 | return err; |
673a394b EA |
1560 | } |
1561 | ||
1562 | /** | |
14bb2c11 TU |
1563 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1564 | * it is mapped to. | |
1565 | * @dev: drm device | |
1566 | * @data: ioctl data blob | |
1567 | * @file: drm file | |
673a394b EA |
1568 | * |
1569 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1570 | * imply a ref on the object itself. | |
34367381 DV |
1571 | * |
1572 | * IMPORTANT: | |
1573 | * | |
1574 | * DRM driver writers who look a this function as an example for how to do GEM | |
1575 | * mmap support, please don't implement mmap support like here. The modern way | |
1576 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1577 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1578 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1579 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1580 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1581 | */ |
1582 | int | |
1583 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1584 | struct drm_file *file) |
673a394b EA |
1585 | { |
1586 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1587 | struct drm_i915_gem_object *obj; |
673a394b EA |
1588 | unsigned long addr; |
1589 | ||
1816f923 AG |
1590 | if (args->flags & ~(I915_MMAP_WC)) |
1591 | return -EINVAL; | |
1592 | ||
568a58e5 | 1593 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1594 | return -ENODEV; |
1595 | ||
03ac0642 CW |
1596 | obj = i915_gem_object_lookup(file, args->handle); |
1597 | if (!obj) | |
bf79cb91 | 1598 | return -ENOENT; |
673a394b | 1599 | |
1286ff73 DV |
1600 | /* prime objects have no backing filp to GEM mmap |
1601 | * pages from. | |
1602 | */ | |
03ac0642 | 1603 | if (!obj->base.filp) { |
f0cd5182 | 1604 | i915_gem_object_put(obj); |
1286ff73 DV |
1605 | return -EINVAL; |
1606 | } | |
1607 | ||
03ac0642 | 1608 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1609 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1610 | args->offset); | |
1816f923 AG |
1611 | if (args->flags & I915_MMAP_WC) { |
1612 | struct mm_struct *mm = current->mm; | |
1613 | struct vm_area_struct *vma; | |
1614 | ||
80a89a5e | 1615 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1616 | i915_gem_object_put(obj); |
80a89a5e MH |
1617 | return -EINTR; |
1618 | } | |
1816f923 AG |
1619 | vma = find_vma(mm, addr); |
1620 | if (vma) | |
1621 | vma->vm_page_prot = | |
1622 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1623 | else | |
1624 | addr = -ENOMEM; | |
1625 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1626 | |
1627 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1628 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1629 | } |
f0cd5182 | 1630 | i915_gem_object_put(obj); |
673a394b EA |
1631 | if (IS_ERR((void *)addr)) |
1632 | return addr; | |
1633 | ||
1634 | args->addr_ptr = (uint64_t) addr; | |
1635 | ||
1636 | return 0; | |
1637 | } | |
1638 | ||
03af84fe CW |
1639 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1640 | { | |
1641 | u64 size; | |
1642 | ||
1643 | size = i915_gem_object_get_stride(obj); | |
1644 | size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8; | |
1645 | ||
1646 | return size >> PAGE_SHIFT; | |
1647 | } | |
1648 | ||
4cc69075 CW |
1649 | /** |
1650 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1651 | * | |
1652 | * A history of the GTT mmap interface: | |
1653 | * | |
1654 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1655 | * aligned and suitable for fencing, and still fit into the available | |
1656 | * mappable space left by the pinned display objects. A classic problem | |
1657 | * we called the page-fault-of-doom where we would ping-pong between | |
1658 | * two objects that could not fit inside the GTT and so the memcpy | |
1659 | * would page one object in at the expense of the other between every | |
1660 | * single byte. | |
1661 | * | |
1662 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1663 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1664 | * object is too large for the available space (or simply too large | |
1665 | * for the mappable aperture!), a view is created instead and faulted | |
1666 | * into userspace. (This view is aligned and sized appropriately for | |
1667 | * fenced access.) | |
1668 | * | |
1669 | * Restrictions: | |
1670 | * | |
1671 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1672 | * hangs on some architectures, corruption on others. An attempt to service | |
1673 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1674 | * | |
1675 | * * the object must be able to fit into RAM (physical memory, though no | |
1676 | * limited to the mappable aperture). | |
1677 | * | |
1678 | * | |
1679 | * Caveats: | |
1680 | * | |
1681 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1682 | * all data to system memory. Subsequent access will not be synchronized. | |
1683 | * | |
1684 | * * all mappings are revoked on runtime device suspend. | |
1685 | * | |
1686 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1687 | * (older machines require fence register for display and blitter access | |
1688 | * as well). Contention of the fence registers will cause the previous users | |
1689 | * to be unmapped and any new access will generate new page faults. | |
1690 | * | |
1691 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1692 | * rather than the expected SIGSEGV. | |
1693 | */ | |
1694 | int i915_gem_mmap_gtt_version(void) | |
1695 | { | |
1696 | return 1; | |
1697 | } | |
1698 | ||
de151cf6 JB |
1699 | /** |
1700 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1701 | * @area: CPU VMA in question |
d9072a3e | 1702 | * @vmf: fault info |
de151cf6 JB |
1703 | * |
1704 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1705 | * from userspace. The fault handler takes care of binding the object to | |
1706 | * the GTT (if needed), allocating and programming a fence register (again, | |
1707 | * only if needed based on whether the old reg is still valid or the object | |
1708 | * is tiled) and inserting a new PTE into the faulting process. | |
1709 | * | |
1710 | * Note that the faulting process may involve evicting existing objects | |
1711 | * from the GTT and/or fence registers to make room. So performance may | |
1712 | * suffer if the GTT working set is large or there are few fence registers | |
1713 | * left. | |
4cc69075 CW |
1714 | * |
1715 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1716 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1717 | */ |
058d88c4 | 1718 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1719 | { |
03af84fe | 1720 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1721 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1722 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1723 | struct drm_i915_private *dev_priv = to_i915(dev); |
1724 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1725 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1726 | struct i915_vma *vma; |
de151cf6 | 1727 | pgoff_t page_offset; |
82118877 | 1728 | unsigned int flags; |
b8f9096d | 1729 | int ret; |
f65c9168 | 1730 | |
de151cf6 | 1731 | /* We don't use vmf->pgoff since that has the fake offset */ |
058d88c4 | 1732 | page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >> |
de151cf6 JB |
1733 | PAGE_SHIFT; |
1734 | ||
db53a302 CW |
1735 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1736 | ||
6e4930f6 | 1737 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1738 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1739 | * repeat the flush holding the lock in the normal manner to catch cases |
1740 | * where we are gazumped. | |
1741 | */ | |
e95433c7 CW |
1742 | ret = i915_gem_object_wait(obj, |
1743 | I915_WAIT_INTERRUPTIBLE, | |
1744 | MAX_SCHEDULE_TIMEOUT, | |
1745 | NULL); | |
6e4930f6 | 1746 | if (ret) |
b8f9096d CW |
1747 | goto err; |
1748 | ||
40e62d5d CW |
1749 | ret = i915_gem_object_pin_pages(obj); |
1750 | if (ret) | |
1751 | goto err; | |
1752 | ||
b8f9096d CW |
1753 | intel_runtime_pm_get(dev_priv); |
1754 | ||
1755 | ret = i915_mutex_lock_interruptible(dev); | |
1756 | if (ret) | |
1757 | goto err_rpm; | |
6e4930f6 | 1758 | |
eb119bd6 CW |
1759 | /* Access to snoopable pages through the GTT is incoherent. */ |
1760 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1761 | ret = -EFAULT; |
b8f9096d | 1762 | goto err_unlock; |
eb119bd6 CW |
1763 | } |
1764 | ||
82118877 CW |
1765 | /* If the object is smaller than a couple of partial vma, it is |
1766 | * not worth only creating a single partial vma - we may as well | |
1767 | * clear enough space for the full object. | |
1768 | */ | |
1769 | flags = PIN_MAPPABLE; | |
1770 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1771 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1772 | ||
a61007a8 | 1773 | /* Now pin it into the GTT as needed */ |
82118877 | 1774 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 CW |
1775 | if (IS_ERR(vma)) { |
1776 | struct i915_ggtt_view view; | |
03af84fe CW |
1777 | unsigned int chunk_size; |
1778 | ||
a61007a8 | 1779 | /* Use a partial view if it is bigger than available space */ |
03af84fe CW |
1780 | chunk_size = MIN_CHUNK_PAGES; |
1781 | if (i915_gem_object_is_tiled(obj)) | |
0ef723cb | 1782 | chunk_size = roundup(chunk_size, tile_row_pages(obj)); |
e7ded2d7 | 1783 | |
c5ad54cf JL |
1784 | memset(&view, 0, sizeof(view)); |
1785 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1786 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1787 | view.params.partial.size = | |
a61007a8 | 1788 | min_t(unsigned int, chunk_size, |
908b1232 | 1789 | vma_pages(area) - view.params.partial.offset); |
c5ad54cf | 1790 | |
aa136d9d CW |
1791 | /* If the partial covers the entire object, just create a |
1792 | * normal VMA. | |
1793 | */ | |
1794 | if (chunk_size >= obj->base.size >> PAGE_SHIFT) | |
1795 | view.type = I915_GGTT_VIEW_NORMAL; | |
1796 | ||
50349247 CW |
1797 | /* Userspace is now writing through an untracked VMA, abandon |
1798 | * all hope that the hardware is able to track future writes. | |
1799 | */ | |
1800 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1801 | ||
a61007a8 CW |
1802 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1803 | } | |
058d88c4 CW |
1804 | if (IS_ERR(vma)) { |
1805 | ret = PTR_ERR(vma); | |
b8f9096d | 1806 | goto err_unlock; |
058d88c4 | 1807 | } |
4a684a41 | 1808 | |
c9839303 CW |
1809 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1810 | if (ret) | |
b8f9096d | 1811 | goto err_unpin; |
74898d7e | 1812 | |
49ef5294 | 1813 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1814 | if (ret) |
b8f9096d | 1815 | goto err_unpin; |
7d1c4804 | 1816 | |
275f039d | 1817 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1818 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1819 | if (list_empty(&obj->userfault_link)) |
1820 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1821 | |
b90b91d8 | 1822 | /* Finally, remap it using the new GTT offset */ |
c58305af CW |
1823 | ret = remap_io_mapping(area, |
1824 | area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT), | |
1825 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, | |
1826 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1827 | &ggtt->mappable); | |
a61007a8 | 1828 | |
b8f9096d | 1829 | err_unpin: |
058d88c4 | 1830 | __i915_vma_unpin(vma); |
b8f9096d | 1831 | err_unlock: |
de151cf6 | 1832 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1833 | err_rpm: |
1834 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1835 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1836 | err: |
de151cf6 | 1837 | switch (ret) { |
d9bc7e9f | 1838 | case -EIO: |
2232f031 DV |
1839 | /* |
1840 | * We eat errors when the gpu is terminally wedged to avoid | |
1841 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1842 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1843 | * and so needs to be reported. | |
1844 | */ | |
1845 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1846 | ret = VM_FAULT_SIGBUS; |
1847 | break; | |
1848 | } | |
045e769a | 1849 | case -EAGAIN: |
571c608d DV |
1850 | /* |
1851 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1852 | * handler to reset everything when re-faulting in | |
1853 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1854 | */ |
c715089f CW |
1855 | case 0: |
1856 | case -ERESTARTSYS: | |
bed636ab | 1857 | case -EINTR: |
e79e0fe3 DR |
1858 | case -EBUSY: |
1859 | /* | |
1860 | * EBUSY is ok: this just means that another thread | |
1861 | * already did the job. | |
1862 | */ | |
f65c9168 PZ |
1863 | ret = VM_FAULT_NOPAGE; |
1864 | break; | |
de151cf6 | 1865 | case -ENOMEM: |
f65c9168 PZ |
1866 | ret = VM_FAULT_OOM; |
1867 | break; | |
a7c2e1aa | 1868 | case -ENOSPC: |
45d67817 | 1869 | case -EFAULT: |
f65c9168 PZ |
1870 | ret = VM_FAULT_SIGBUS; |
1871 | break; | |
de151cf6 | 1872 | default: |
a7c2e1aa | 1873 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1874 | ret = VM_FAULT_SIGBUS; |
1875 | break; | |
de151cf6 | 1876 | } |
f65c9168 | 1877 | return ret; |
de151cf6 JB |
1878 | } |
1879 | ||
901782b2 CW |
1880 | /** |
1881 | * i915_gem_release_mmap - remove physical page mappings | |
1882 | * @obj: obj in question | |
1883 | * | |
af901ca1 | 1884 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1885 | * relinquish ownership of the pages back to the system. |
1886 | * | |
1887 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1888 | * object through the GTT and then lose the fence register due to | |
1889 | * resource pressure. Similarly if the object has been moved out of the | |
1890 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1891 | * mapping will then trigger a page fault on the next user access, allowing | |
1892 | * fixup by i915_gem_fault(). | |
1893 | */ | |
d05ca301 | 1894 | void |
05394f39 | 1895 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1896 | { |
275f039d | 1897 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 1898 | |
349f2ccf CW |
1899 | /* Serialisation between user GTT access and our code depends upon |
1900 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1901 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
1902 | * |
1903 | * Note that RPM complicates somewhat by adding an additional | |
1904 | * requirement that operations to the GGTT be made holding the RPM | |
1905 | * wakeref. | |
349f2ccf | 1906 | */ |
275f039d | 1907 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 1908 | intel_runtime_pm_get(i915); |
349f2ccf | 1909 | |
3594a3e2 | 1910 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 1911 | goto out; |
901782b2 | 1912 | |
3594a3e2 | 1913 | list_del_init(&obj->userfault_link); |
6796cb16 DH |
1914 | drm_vma_node_unmap(&obj->base.vma_node, |
1915 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1916 | |
1917 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1918 | * memory transactions from userspace before we return. The TLB | |
1919 | * flushing implied above by changing the PTE above *should* be | |
1920 | * sufficient, an extra barrier here just provides us with a bit | |
1921 | * of paranoid documentation about our requirement to serialise | |
1922 | * memory writes before touching registers / GSM. | |
1923 | */ | |
1924 | wmb(); | |
9c870d03 CW |
1925 | |
1926 | out: | |
1927 | intel_runtime_pm_put(i915); | |
901782b2 CW |
1928 | } |
1929 | ||
7c108fd8 | 1930 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 1931 | { |
3594a3e2 | 1932 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 1933 | int i; |
eedd10f4 | 1934 | |
3594a3e2 CW |
1935 | /* |
1936 | * Only called during RPM suspend. All users of the userfault_list | |
1937 | * must be holding an RPM wakeref to ensure that this can not | |
1938 | * run concurrently with themselves (and use the struct_mutex for | |
1939 | * protection between themselves). | |
1940 | */ | |
275f039d | 1941 | |
3594a3e2 CW |
1942 | list_for_each_entry_safe(obj, on, |
1943 | &dev_priv->mm.userfault_list, userfault_link) { | |
1944 | list_del_init(&obj->userfault_link); | |
275f039d CW |
1945 | drm_vma_node_unmap(&obj->base.vma_node, |
1946 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 1947 | } |
7c108fd8 CW |
1948 | |
1949 | /* The fence will be lost when the device powers down. If any were | |
1950 | * in use by hardware (i.e. they are pinned), we should not be powering | |
1951 | * down! All other fences will be reacquired by the user upon waking. | |
1952 | */ | |
1953 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
1954 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
1955 | ||
1956 | if (WARN_ON(reg->pin_count)) | |
1957 | continue; | |
1958 | ||
1959 | if (!reg->vma) | |
1960 | continue; | |
1961 | ||
1962 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
1963 | reg->dirty = true; | |
1964 | } | |
eedd10f4 CW |
1965 | } |
1966 | ||
ad1a7d20 CW |
1967 | /** |
1968 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 1969 | * @dev_priv: i915 device |
ad1a7d20 CW |
1970 | * @size: object size |
1971 | * @tiling_mode: tiling mode | |
1972 | * | |
1973 | * Return the required global GTT size for an object, taking into account | |
1974 | * potential fence register mapping. | |
1975 | */ | |
a9f1481f CW |
1976 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
1977 | u64 size, int tiling_mode) | |
92b88aeb | 1978 | { |
ad1a7d20 | 1979 | u64 ggtt_size; |
92b88aeb | 1980 | |
ad1a7d20 CW |
1981 | GEM_BUG_ON(size == 0); |
1982 | ||
a9f1481f | 1983 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
1984 | tiling_mode == I915_TILING_NONE) |
1985 | return size; | |
92b88aeb CW |
1986 | |
1987 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 1988 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 1989 | ggtt_size = 1024*1024; |
92b88aeb | 1990 | else |
ad1a7d20 | 1991 | ggtt_size = 512*1024; |
92b88aeb | 1992 | |
ad1a7d20 CW |
1993 | while (ggtt_size < size) |
1994 | ggtt_size <<= 1; | |
92b88aeb | 1995 | |
ad1a7d20 | 1996 | return ggtt_size; |
92b88aeb CW |
1997 | } |
1998 | ||
de151cf6 | 1999 | /** |
ad1a7d20 | 2000 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 2001 | * @dev_priv: i915 device |
14bb2c11 TU |
2002 | * @size: object size |
2003 | * @tiling_mode: tiling mode | |
ad1a7d20 | 2004 | * @fenced: is fenced alignment required or not |
de151cf6 | 2005 | * |
ad1a7d20 | 2006 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 2007 | * potential fence register mapping. |
de151cf6 | 2008 | */ |
a9f1481f | 2009 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 2010 | int tiling_mode, bool fenced) |
de151cf6 | 2011 | { |
ad1a7d20 CW |
2012 | GEM_BUG_ON(size == 0); |
2013 | ||
de151cf6 JB |
2014 | /* |
2015 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2016 | * if a fence register is needed for the object. | |
2017 | */ | |
a9f1481f | 2018 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 2019 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2020 | return 4096; |
2021 | ||
a00b10c3 CW |
2022 | /* |
2023 | * Previous chips need to be aligned to the size of the smallest | |
2024 | * fence register that can contain the object. | |
2025 | */ | |
a9f1481f | 2026 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
2027 | } |
2028 | ||
d8cb5086 CW |
2029 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2030 | { | |
fac5e23e | 2031 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2032 | int err; |
da494d7c | 2033 | |
f3f6184c CW |
2034 | err = drm_gem_create_mmap_offset(&obj->base); |
2035 | if (!err) | |
2036 | return 0; | |
d8cb5086 | 2037 | |
f3f6184c CW |
2038 | /* We can idle the GPU locklessly to flush stale objects, but in order |
2039 | * to claim that space for ourselves, we need to take the big | |
2040 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 2041 | */ |
ea746f36 | 2042 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); |
f3f6184c CW |
2043 | if (err) |
2044 | return err; | |
2045 | ||
2046 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
2047 | if (!err) { | |
2048 | i915_gem_retire_requests(dev_priv); | |
2049 | err = drm_gem_create_mmap_offset(&obj->base); | |
2050 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2051 | } | |
da494d7c | 2052 | |
f3f6184c | 2053 | return err; |
d8cb5086 CW |
2054 | } |
2055 | ||
2056 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2057 | { | |
d8cb5086 CW |
2058 | drm_gem_free_mmap_offset(&obj->base); |
2059 | } | |
2060 | ||
da6b51d0 | 2061 | int |
ff72145b DA |
2062 | i915_gem_mmap_gtt(struct drm_file *file, |
2063 | struct drm_device *dev, | |
da6b51d0 | 2064 | uint32_t handle, |
ff72145b | 2065 | uint64_t *offset) |
de151cf6 | 2066 | { |
05394f39 | 2067 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2068 | int ret; |
2069 | ||
03ac0642 | 2070 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2071 | if (!obj) |
2072 | return -ENOENT; | |
ab18282d | 2073 | |
d8cb5086 | 2074 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2075 | if (ret == 0) |
2076 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2077 | |
f0cd5182 | 2078 | i915_gem_object_put(obj); |
1d7cfea1 | 2079 | return ret; |
de151cf6 JB |
2080 | } |
2081 | ||
ff72145b DA |
2082 | /** |
2083 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2084 | * @dev: DRM device | |
2085 | * @data: GTT mapping ioctl data | |
2086 | * @file: GEM object info | |
2087 | * | |
2088 | * Simply returns the fake offset to userspace so it can mmap it. | |
2089 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2090 | * up so we can get faults in the handler above. | |
2091 | * | |
2092 | * The fault handler will take care of binding the object into the GTT | |
2093 | * (since it may have been evicted to make room for something), allocating | |
2094 | * a fence register, and mapping the appropriate aperture address into | |
2095 | * userspace. | |
2096 | */ | |
2097 | int | |
2098 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2099 | struct drm_file *file) | |
2100 | { | |
2101 | struct drm_i915_gem_mmap_gtt *args = data; | |
2102 | ||
da6b51d0 | 2103 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2104 | } |
2105 | ||
225067ee DV |
2106 | /* Immediately discard the backing storage */ |
2107 | static void | |
2108 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2109 | { |
4d6294bf | 2110 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2111 | |
4d6294bf CW |
2112 | if (obj->base.filp == NULL) |
2113 | return; | |
e5281ccd | 2114 | |
225067ee DV |
2115 | /* Our goal here is to return as much of the memory as |
2116 | * is possible back to the system as we are called from OOM. | |
2117 | * To do this we must instruct the shmfs to drop all of its | |
2118 | * backing pages, *now*. | |
2119 | */ | |
5537252b | 2120 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2121 | obj->mm.madv = __I915_MADV_PURGED; |
225067ee | 2122 | } |
e5281ccd | 2123 | |
5537252b | 2124 | /* Try to discard unwanted pages */ |
03ac84f1 | 2125 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2126 | { |
5537252b CW |
2127 | struct address_space *mapping; |
2128 | ||
1233e2db CW |
2129 | lockdep_assert_held(&obj->mm.lock); |
2130 | GEM_BUG_ON(obj->mm.pages); | |
2131 | ||
a4f5ea64 | 2132 | switch (obj->mm.madv) { |
5537252b CW |
2133 | case I915_MADV_DONTNEED: |
2134 | i915_gem_object_truncate(obj); | |
2135 | case __I915_MADV_PURGED: | |
2136 | return; | |
2137 | } | |
2138 | ||
2139 | if (obj->base.filp == NULL) | |
2140 | return; | |
2141 | ||
93c76a3d | 2142 | mapping = obj->base.filp->f_mapping, |
5537252b | 2143 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2144 | } |
2145 | ||
5cdf5881 | 2146 | static void |
03ac84f1 CW |
2147 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2148 | struct sg_table *pages) | |
673a394b | 2149 | { |
85d1225e DG |
2150 | struct sgt_iter sgt_iter; |
2151 | struct page *page; | |
1286ff73 | 2152 | |
03ac84f1 | 2153 | __i915_gem_object_release_shmem(obj); |
673a394b | 2154 | |
03ac84f1 | 2155 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2156 | |
6dacfd2f | 2157 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2158 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2159 | |
03ac84f1 | 2160 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2161 | if (obj->mm.dirty) |
9da3da66 | 2162 | set_page_dirty(page); |
3ef94daa | 2163 | |
a4f5ea64 | 2164 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2165 | mark_page_accessed(page); |
3ef94daa | 2166 | |
09cbfeaf | 2167 | put_page(page); |
3ef94daa | 2168 | } |
a4f5ea64 | 2169 | obj->mm.dirty = false; |
673a394b | 2170 | |
03ac84f1 CW |
2171 | sg_free_table(pages); |
2172 | kfree(pages); | |
37e680a1 | 2173 | } |
6c085a72 | 2174 | |
96d77634 CW |
2175 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2176 | { | |
2177 | struct radix_tree_iter iter; | |
2178 | void **slot; | |
2179 | ||
a4f5ea64 CW |
2180 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2181 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2182 | } |
2183 | ||
548625ee CW |
2184 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2185 | enum i915_mm_subclass subclass) | |
37e680a1 | 2186 | { |
03ac84f1 | 2187 | struct sg_table *pages; |
37e680a1 | 2188 | |
a4f5ea64 | 2189 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2190 | return; |
a5570178 | 2191 | |
15717de2 | 2192 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2193 | if (!READ_ONCE(obj->mm.pages)) |
2194 | return; | |
2195 | ||
2196 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2197 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2198 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2199 | goto unlock; | |
3e123027 | 2200 | |
a2165e31 CW |
2201 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2202 | * array, hence protect them from being reaped by removing them from gtt | |
2203 | * lists early. */ | |
03ac84f1 CW |
2204 | pages = fetch_and_zero(&obj->mm.pages); |
2205 | GEM_BUG_ON(!pages); | |
a2165e31 | 2206 | |
a4f5ea64 | 2207 | if (obj->mm.mapping) { |
4b30cb23 CW |
2208 | void *ptr; |
2209 | ||
a4f5ea64 | 2210 | ptr = ptr_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2211 | if (is_vmalloc_addr(ptr)) |
2212 | vunmap(ptr); | |
fb8621d3 | 2213 | else |
4b30cb23 CW |
2214 | kunmap(kmap_to_page(ptr)); |
2215 | ||
a4f5ea64 | 2216 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2217 | } |
2218 | ||
96d77634 CW |
2219 | __i915_gem_object_reset_page_iter(obj); |
2220 | ||
03ac84f1 | 2221 | obj->ops->put_pages(obj, pages); |
1233e2db CW |
2222 | unlock: |
2223 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2224 | } |
2225 | ||
4ff340f0 | 2226 | static unsigned int swiotlb_max_size(void) |
871dfbd6 CW |
2227 | { |
2228 | #if IS_ENABLED(CONFIG_SWIOTLB) | |
2229 | return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE); | |
2230 | #else | |
2231 | return 0; | |
2232 | #endif | |
2233 | } | |
2234 | ||
03ac84f1 | 2235 | static struct sg_table * |
6c085a72 | 2236 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2237 | { |
fac5e23e | 2238 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2239 | int page_count, i; |
2240 | struct address_space *mapping; | |
9da3da66 CW |
2241 | struct sg_table *st; |
2242 | struct scatterlist *sg; | |
85d1225e | 2243 | struct sgt_iter sgt_iter; |
e5281ccd | 2244 | struct page *page; |
90797e6d | 2245 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2246 | unsigned int max_segment; |
e2273302 | 2247 | int ret; |
6c085a72 | 2248 | gfp_t gfp; |
e5281ccd | 2249 | |
6c085a72 CW |
2250 | /* Assert that the object is not currently in any GPU domain. As it |
2251 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2252 | * a GPU cache | |
2253 | */ | |
03ac84f1 CW |
2254 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2255 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2256 | |
871dfbd6 CW |
2257 | max_segment = swiotlb_max_size(); |
2258 | if (!max_segment) | |
4ff340f0 | 2259 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2260 | |
9da3da66 CW |
2261 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2262 | if (st == NULL) | |
03ac84f1 | 2263 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2264 | |
05394f39 | 2265 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2266 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2267 | kfree(st); |
03ac84f1 | 2268 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2269 | } |
e5281ccd | 2270 | |
9da3da66 CW |
2271 | /* Get the list of pages out of our struct file. They'll be pinned |
2272 | * at this point until we release them. | |
2273 | * | |
2274 | * Fail silently without starting the shrinker | |
2275 | */ | |
93c76a3d | 2276 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2277 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2278 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2279 | sg = st->sgl; |
2280 | st->nents = 0; | |
2281 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2282 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2283 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2284 | i915_gem_shrink(dev_priv, |
2285 | page_count, | |
2286 | I915_SHRINK_BOUND | | |
2287 | I915_SHRINK_UNBOUND | | |
2288 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2289 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2290 | } | |
2291 | if (IS_ERR(page)) { | |
2292 | /* We've tried hard to allocate the memory by reaping | |
2293 | * our own buffer, now let the real VM do its job and | |
2294 | * go down in flames if truly OOM. | |
2295 | */ | |
f461d1be | 2296 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2297 | if (IS_ERR(page)) { |
2298 | ret = PTR_ERR(page); | |
6c085a72 | 2299 | goto err_pages; |
e2273302 | 2300 | } |
6c085a72 | 2301 | } |
871dfbd6 CW |
2302 | if (!i || |
2303 | sg->length >= max_segment || | |
2304 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2305 | if (i) |
2306 | sg = sg_next(sg); | |
2307 | st->nents++; | |
2308 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2309 | } else { | |
2310 | sg->length += PAGE_SIZE; | |
2311 | } | |
2312 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2313 | |
2314 | /* Check that the i965g/gm workaround works. */ | |
2315 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2316 | } |
871dfbd6 | 2317 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2318 | sg_mark_end(sg); |
74ce6b6c | 2319 | |
03ac84f1 | 2320 | ret = i915_gem_gtt_prepare_pages(obj, st); |
e2273302 ID |
2321 | if (ret) |
2322 | goto err_pages; | |
2323 | ||
6dacfd2f | 2324 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2325 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2326 | |
03ac84f1 | 2327 | return st; |
e5281ccd CW |
2328 | |
2329 | err_pages: | |
90797e6d | 2330 | sg_mark_end(sg); |
85d1225e DG |
2331 | for_each_sgt_page(page, sgt_iter, st) |
2332 | put_page(page); | |
9da3da66 CW |
2333 | sg_free_table(st); |
2334 | kfree(st); | |
0820baf3 CW |
2335 | |
2336 | /* shmemfs first checks if there is enough memory to allocate the page | |
2337 | * and reports ENOSPC should there be insufficient, along with the usual | |
2338 | * ENOMEM for a genuine allocation failure. | |
2339 | * | |
2340 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2341 | * space and so want to translate the error from shmemfs back to our | |
2342 | * usual understanding of ENOMEM. | |
2343 | */ | |
e2273302 ID |
2344 | if (ret == -ENOSPC) |
2345 | ret = -ENOMEM; | |
2346 | ||
03ac84f1 CW |
2347 | return ERR_PTR(ret); |
2348 | } | |
2349 | ||
2350 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2351 | struct sg_table *pages) | |
2352 | { | |
1233e2db | 2353 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2354 | |
2355 | obj->mm.get_page.sg_pos = pages->sgl; | |
2356 | obj->mm.get_page.sg_idx = 0; | |
2357 | ||
2358 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2359 | |
2360 | if (i915_gem_object_is_tiled(obj) && | |
2361 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2362 | GEM_BUG_ON(obj->mm.quirked); | |
2363 | __i915_gem_object_pin_pages(obj); | |
2364 | obj->mm.quirked = true; | |
2365 | } | |
03ac84f1 CW |
2366 | } |
2367 | ||
2368 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2369 | { | |
2370 | struct sg_table *pages; | |
2371 | ||
2c3a3f44 CW |
2372 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2373 | ||
03ac84f1 CW |
2374 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2375 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2376 | return -EFAULT; | |
2377 | } | |
2378 | ||
2379 | pages = obj->ops->get_pages(obj); | |
2380 | if (unlikely(IS_ERR(pages))) | |
2381 | return PTR_ERR(pages); | |
2382 | ||
2383 | __i915_gem_object_set_pages(obj, pages); | |
2384 | return 0; | |
673a394b EA |
2385 | } |
2386 | ||
37e680a1 | 2387 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2388 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2389 | * multiple times before they are released by a single call to |
1233e2db | 2390 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2391 | * either as a result of memory pressure (reaping pages under the shrinker) |
2392 | * or as the object is itself released. | |
2393 | */ | |
a4f5ea64 | 2394 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2395 | { |
03ac84f1 | 2396 | int err; |
37e680a1 | 2397 | |
1233e2db CW |
2398 | err = mutex_lock_interruptible(&obj->mm.lock); |
2399 | if (err) | |
2400 | return err; | |
4c7d62c6 | 2401 | |
2c3a3f44 CW |
2402 | if (unlikely(!obj->mm.pages)) { |
2403 | err = ____i915_gem_object_get_pages(obj); | |
2404 | if (err) | |
2405 | goto unlock; | |
37e680a1 | 2406 | |
2c3a3f44 CW |
2407 | smp_mb__before_atomic(); |
2408 | } | |
2409 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2410 | |
1233e2db CW |
2411 | unlock: |
2412 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2413 | return err; |
673a394b EA |
2414 | } |
2415 | ||
dd6034c6 | 2416 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2417 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2418 | enum i915_map_type type) | |
dd6034c6 DG |
2419 | { |
2420 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2421 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2422 | struct sgt_iter sgt_iter; |
2423 | struct page *page; | |
b338fa47 DG |
2424 | struct page *stack_pages[32]; |
2425 | struct page **pages = stack_pages; | |
dd6034c6 | 2426 | unsigned long i = 0; |
d31d7cb1 | 2427 | pgprot_t pgprot; |
dd6034c6 DG |
2428 | void *addr; |
2429 | ||
2430 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2431 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2432 | return kmap(sg_page(sgt->sgl)); |
2433 | ||
b338fa47 DG |
2434 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2435 | /* Too big for stack -- allocate temporary array instead */ | |
2436 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2437 | if (!pages) | |
2438 | return NULL; | |
2439 | } | |
dd6034c6 | 2440 | |
85d1225e DG |
2441 | for_each_sgt_page(page, sgt_iter, sgt) |
2442 | pages[i++] = page; | |
dd6034c6 DG |
2443 | |
2444 | /* Check that we have the expected number of pages */ | |
2445 | GEM_BUG_ON(i != n_pages); | |
2446 | ||
d31d7cb1 CW |
2447 | switch (type) { |
2448 | case I915_MAP_WB: | |
2449 | pgprot = PAGE_KERNEL; | |
2450 | break; | |
2451 | case I915_MAP_WC: | |
2452 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2453 | break; | |
2454 | } | |
2455 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2456 | |
b338fa47 DG |
2457 | if (pages != stack_pages) |
2458 | drm_free_large(pages); | |
dd6034c6 DG |
2459 | |
2460 | return addr; | |
2461 | } | |
2462 | ||
2463 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2464 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2465 | enum i915_map_type type) | |
0a798eb9 | 2466 | { |
d31d7cb1 CW |
2467 | enum i915_map_type has_type; |
2468 | bool pinned; | |
2469 | void *ptr; | |
0a798eb9 CW |
2470 | int ret; |
2471 | ||
d31d7cb1 | 2472 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2473 | |
1233e2db | 2474 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2475 | if (ret) |
2476 | return ERR_PTR(ret); | |
2477 | ||
1233e2db CW |
2478 | pinned = true; |
2479 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
2c3a3f44 CW |
2480 | if (unlikely(!obj->mm.pages)) { |
2481 | ret = ____i915_gem_object_get_pages(obj); | |
2482 | if (ret) | |
2483 | goto err_unlock; | |
1233e2db | 2484 | |
2c3a3f44 CW |
2485 | smp_mb__before_atomic(); |
2486 | } | |
2487 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2488 | pinned = false; |
2489 | } | |
2490 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2491 | |
a4f5ea64 | 2492 | ptr = ptr_unpack_bits(obj->mm.mapping, has_type); |
d31d7cb1 CW |
2493 | if (ptr && has_type != type) { |
2494 | if (pinned) { | |
2495 | ret = -EBUSY; | |
1233e2db | 2496 | goto err_unpin; |
0a798eb9 | 2497 | } |
d31d7cb1 CW |
2498 | |
2499 | if (is_vmalloc_addr(ptr)) | |
2500 | vunmap(ptr); | |
2501 | else | |
2502 | kunmap(kmap_to_page(ptr)); | |
2503 | ||
a4f5ea64 | 2504 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2505 | } |
2506 | ||
d31d7cb1 CW |
2507 | if (!ptr) { |
2508 | ptr = i915_gem_object_map(obj, type); | |
2509 | if (!ptr) { | |
2510 | ret = -ENOMEM; | |
1233e2db | 2511 | goto err_unpin; |
d31d7cb1 CW |
2512 | } |
2513 | ||
a4f5ea64 | 2514 | obj->mm.mapping = ptr_pack_bits(ptr, type); |
d31d7cb1 CW |
2515 | } |
2516 | ||
1233e2db CW |
2517 | out_unlock: |
2518 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2519 | return ptr; |
2520 | ||
1233e2db CW |
2521 | err_unpin: |
2522 | atomic_dec(&obj->mm.pages_pin_count); | |
2523 | err_unlock: | |
2524 | ptr = ERR_PTR(ret); | |
2525 | goto out_unlock; | |
0a798eb9 CW |
2526 | } |
2527 | ||
7b4d3a16 | 2528 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2529 | { |
44e2c070 | 2530 | unsigned long elapsed; |
be62acb4 | 2531 | |
44e2c070 | 2532 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2533 | return true; |
2534 | ||
7b4d3a16 | 2535 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2536 | if (ctx->hang_stats.ban_period_seconds && |
2537 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2538 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2539 | return true; | |
be62acb4 MK |
2540 | } |
2541 | ||
2542 | return false; | |
2543 | } | |
2544 | ||
7b4d3a16 | 2545 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2546 | const bool guilty) |
aa60c664 | 2547 | { |
7b4d3a16 | 2548 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2549 | |
2550 | if (guilty) { | |
7b4d3a16 | 2551 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2552 | hs->batch_active++; |
2553 | hs->guilty_ts = get_seconds(); | |
2554 | } else { | |
2555 | hs->batch_pending++; | |
aa60c664 MK |
2556 | } |
2557 | } | |
2558 | ||
8d9fc7fd | 2559 | struct drm_i915_gem_request * |
0bc40be8 | 2560 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2561 | { |
4db080f9 CW |
2562 | struct drm_i915_gem_request *request; |
2563 | ||
f69a02c9 CW |
2564 | /* We are called by the error capture and reset at a random |
2565 | * point in time. In particular, note that neither is crucially | |
2566 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2567 | * assume that no more writes can happen (we waited long enough for | |
2568 | * all writes that were in transaction to be flushed) - adding an | |
2569 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2570 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2571 | */ | |
73cb9701 | 2572 | list_for_each_entry(request, &engine->timeline->requests, link) { |
80b204bc | 2573 | if (__i915_gem_request_completed(request)) |
4db080f9 | 2574 | continue; |
aa60c664 | 2575 | |
b6b0fac0 | 2576 | return request; |
4db080f9 | 2577 | } |
b6b0fac0 MK |
2578 | |
2579 | return NULL; | |
2580 | } | |
2581 | ||
821ed7df CW |
2582 | static void reset_request(struct drm_i915_gem_request *request) |
2583 | { | |
2584 | void *vaddr = request->ring->vaddr; | |
2585 | u32 head; | |
2586 | ||
2587 | /* As this request likely depends on state from the lost | |
2588 | * context, clear out all the user operations leaving the | |
2589 | * breadcrumb at the end (so we get the fence notifications). | |
2590 | */ | |
2591 | head = request->head; | |
2592 | if (request->postfix < head) { | |
2593 | memset(vaddr + head, 0, request->ring->size - head); | |
2594 | head = 0; | |
2595 | } | |
2596 | memset(vaddr + head, 0, request->postfix - head); | |
2597 | } | |
2598 | ||
2599 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) | |
b6b0fac0 MK |
2600 | { |
2601 | struct drm_i915_gem_request *request; | |
821ed7df | 2602 | struct i915_gem_context *incomplete_ctx; |
80b204bc | 2603 | struct intel_timeline *timeline; |
b6b0fac0 MK |
2604 | bool ring_hung; |
2605 | ||
821ed7df CW |
2606 | if (engine->irq_seqno_barrier) |
2607 | engine->irq_seqno_barrier(engine); | |
2608 | ||
0bc40be8 | 2609 | request = i915_gem_find_active_request(engine); |
821ed7df | 2610 | if (!request) |
b6b0fac0 MK |
2611 | return; |
2612 | ||
0bc40be8 | 2613 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
77c60701 CW |
2614 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) |
2615 | ring_hung = false; | |
2616 | ||
7b4d3a16 | 2617 | i915_set_reset_status(request->ctx, ring_hung); |
821ed7df CW |
2618 | if (!ring_hung) |
2619 | return; | |
2620 | ||
2621 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
65e4760e | 2622 | engine->name, request->global_seqno); |
821ed7df CW |
2623 | |
2624 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2625 | engine->reset_hw(engine, request); | |
2626 | ||
2627 | /* Users of the default context do not rely on logical state | |
2628 | * preserved between batches. They have to emit full state on | |
2629 | * every batch and so it is safe to execute queued requests following | |
2630 | * the hang. | |
2631 | * | |
2632 | * Other contexts preserve state, now corrupt. We want to skip all | |
2633 | * queued requests that reference the corrupt context. | |
2634 | */ | |
2635 | incomplete_ctx = request->ctx; | |
2636 | if (i915_gem_context_is_default(incomplete_ctx)) | |
2637 | return; | |
2638 | ||
73cb9701 | 2639 | list_for_each_entry_continue(request, &engine->timeline->requests, link) |
821ed7df CW |
2640 | if (request->ctx == incomplete_ctx) |
2641 | reset_request(request); | |
80b204bc CW |
2642 | |
2643 | timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine); | |
2644 | list_for_each_entry(request, &timeline->requests, link) | |
2645 | reset_request(request); | |
4db080f9 | 2646 | } |
aa60c664 | 2647 | |
821ed7df | 2648 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2649 | { |
821ed7df | 2650 | struct intel_engine_cs *engine; |
3b3f1650 | 2651 | enum intel_engine_id id; |
608c1a52 | 2652 | |
4c7d62c6 CW |
2653 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2654 | ||
821ed7df CW |
2655 | i915_gem_retire_requests(dev_priv); |
2656 | ||
3b3f1650 | 2657 | for_each_engine(engine, dev_priv, id) |
821ed7df CW |
2658 | i915_gem_reset_engine(engine); |
2659 | ||
2660 | i915_gem_restore_fences(&dev_priv->drm); | |
f2a91d1a CW |
2661 | |
2662 | if (dev_priv->gt.awake) { | |
2663 | intel_sanitize_gt_powersave(dev_priv); | |
2664 | intel_enable_gt_powersave(dev_priv); | |
2665 | if (INTEL_GEN(dev_priv) >= 6) | |
2666 | gen6_rps_busy(dev_priv); | |
2667 | } | |
821ed7df CW |
2668 | } |
2669 | ||
2670 | static void nop_submit_request(struct drm_i915_gem_request *request) | |
2671 | { | |
2672 | } | |
2673 | ||
2674 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) | |
2675 | { | |
2676 | engine->submit_request = nop_submit_request; | |
70c2a24d | 2677 | |
c4b0930b CW |
2678 | /* Mark all pending requests as complete so that any concurrent |
2679 | * (lockless) lookup doesn't try and wait upon the request as we | |
2680 | * reset it. | |
2681 | */ | |
73cb9701 | 2682 | intel_engine_init_global_seqno(engine, |
cb399eab | 2683 | intel_engine_last_submit(engine)); |
c4b0930b | 2684 | |
dcb4c12a OM |
2685 | /* |
2686 | * Clear the execlists queue up before freeing the requests, as those | |
2687 | * are the ones that keep the context and ringbuffer backing objects | |
2688 | * pinned in place. | |
2689 | */ | |
dcb4c12a | 2690 | |
7de1691a | 2691 | if (i915.enable_execlists) { |
70c2a24d CW |
2692 | spin_lock(&engine->execlist_lock); |
2693 | INIT_LIST_HEAD(&engine->execlist_queue); | |
2694 | i915_gem_request_put(engine->execlist_port[0].request); | |
2695 | i915_gem_request_put(engine->execlist_port[1].request); | |
2696 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
2697 | spin_unlock(&engine->execlist_lock); | |
dcb4c12a | 2698 | } |
673a394b EA |
2699 | } |
2700 | ||
821ed7df | 2701 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) |
673a394b | 2702 | { |
e2f80391 | 2703 | struct intel_engine_cs *engine; |
3b3f1650 | 2704 | enum intel_engine_id id; |
673a394b | 2705 | |
821ed7df CW |
2706 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2707 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2708 | |
821ed7df | 2709 | i915_gem_context_lost(dev_priv); |
3b3f1650 | 2710 | for_each_engine(engine, dev_priv, id) |
821ed7df | 2711 | i915_gem_cleanup_engine(engine); |
b913b33c | 2712 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2713 | |
821ed7df | 2714 | i915_gem_retire_requests(dev_priv); |
673a394b EA |
2715 | } |
2716 | ||
75ef9da2 | 2717 | static void |
673a394b EA |
2718 | i915_gem_retire_work_handler(struct work_struct *work) |
2719 | { | |
b29c19b6 | 2720 | struct drm_i915_private *dev_priv = |
67d97da3 | 2721 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2722 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2723 | |
891b48cf | 2724 | /* Come back later if the device is busy... */ |
b29c19b6 | 2725 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2726 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2727 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2728 | } |
67d97da3 CW |
2729 | |
2730 | /* Keep the retire handler running until we are finally idle. | |
2731 | * We do not need to do this test under locking as in the worst-case | |
2732 | * we queue the retire worker once too often. | |
2733 | */ | |
c9615613 CW |
2734 | if (READ_ONCE(dev_priv->gt.awake)) { |
2735 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2736 | queue_delayed_work(dev_priv->wq, |
2737 | &dev_priv->gt.retire_work, | |
bcb45086 | 2738 | round_jiffies_up_relative(HZ)); |
c9615613 | 2739 | } |
b29c19b6 | 2740 | } |
0a58705b | 2741 | |
b29c19b6 CW |
2742 | static void |
2743 | i915_gem_idle_work_handler(struct work_struct *work) | |
2744 | { | |
2745 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2746 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2747 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2748 | struct intel_engine_cs *engine; |
3b3f1650 | 2749 | enum intel_engine_id id; |
67d97da3 CW |
2750 | bool rearm_hangcheck; |
2751 | ||
2752 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2753 | return; | |
2754 | ||
0cb5670b ID |
2755 | /* |
2756 | * Wait for last execlists context complete, but bail out in case a | |
2757 | * new request is submitted. | |
2758 | */ | |
2759 | wait_for(READ_ONCE(dev_priv->gt.active_requests) || | |
2760 | intel_execlists_idle(dev_priv), 10); | |
2761 | ||
28176ef4 | 2762 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
2763 | return; |
2764 | ||
2765 | rearm_hangcheck = | |
2766 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2767 | ||
2768 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2769 | /* Currently busy, come back later */ | |
2770 | mod_delayed_work(dev_priv->wq, | |
2771 | &dev_priv->gt.idle_work, | |
2772 | msecs_to_jiffies(50)); | |
2773 | goto out_rearm; | |
2774 | } | |
2775 | ||
93c97dc1 ID |
2776 | /* |
2777 | * New request retired after this work handler started, extend active | |
2778 | * period until next instance of the work. | |
2779 | */ | |
2780 | if (work_pending(work)) | |
2781 | goto out_unlock; | |
2782 | ||
28176ef4 | 2783 | if (dev_priv->gt.active_requests) |
67d97da3 | 2784 | goto out_unlock; |
b29c19b6 | 2785 | |
0cb5670b ID |
2786 | if (wait_for(intel_execlists_idle(dev_priv), 10)) |
2787 | DRM_ERROR("Timeout waiting for engines to idle\n"); | |
2788 | ||
3b3f1650 | 2789 | for_each_engine(engine, dev_priv, id) |
67d97da3 | 2790 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2791 | |
67d97da3 CW |
2792 | GEM_BUG_ON(!dev_priv->gt.awake); |
2793 | dev_priv->gt.awake = false; | |
2794 | rearm_hangcheck = false; | |
30ecad77 | 2795 | |
67d97da3 CW |
2796 | if (INTEL_GEN(dev_priv) >= 6) |
2797 | gen6_rps_idle(dev_priv); | |
2798 | intel_runtime_pm_put(dev_priv); | |
2799 | out_unlock: | |
2800 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2801 | |
67d97da3 CW |
2802 | out_rearm: |
2803 | if (rearm_hangcheck) { | |
2804 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2805 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2806 | } |
673a394b EA |
2807 | } |
2808 | ||
b1f788c6 CW |
2809 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2810 | { | |
2811 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2812 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2813 | struct i915_vma *vma, *vn; | |
2814 | ||
2815 | mutex_lock(&obj->base.dev->struct_mutex); | |
2816 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2817 | if (vma->vm->file == fpriv) | |
2818 | i915_vma_close(vma); | |
f8a7fde4 CW |
2819 | |
2820 | if (i915_gem_object_is_active(obj) && | |
2821 | !i915_gem_object_has_active_reference(obj)) { | |
2822 | i915_gem_object_set_active_reference(obj); | |
2823 | i915_gem_object_get(obj); | |
2824 | } | |
b1f788c6 CW |
2825 | mutex_unlock(&obj->base.dev->struct_mutex); |
2826 | } | |
2827 | ||
e95433c7 CW |
2828 | static unsigned long to_wait_timeout(s64 timeout_ns) |
2829 | { | |
2830 | if (timeout_ns < 0) | |
2831 | return MAX_SCHEDULE_TIMEOUT; | |
2832 | ||
2833 | if (timeout_ns == 0) | |
2834 | return 0; | |
2835 | ||
2836 | return nsecs_to_jiffies_timeout(timeout_ns); | |
2837 | } | |
2838 | ||
23ba4fd0 BW |
2839 | /** |
2840 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2841 | * @dev: drm device pointer |
2842 | * @data: ioctl data blob | |
2843 | * @file: drm file pointer | |
23ba4fd0 BW |
2844 | * |
2845 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2846 | * the timeout parameter. | |
2847 | * -ETIME: object is still busy after timeout | |
2848 | * -ERESTARTSYS: signal interrupted the wait | |
2849 | * -ENONENT: object doesn't exist | |
2850 | * Also possible, but rare: | |
2851 | * -EAGAIN: GPU wedged | |
2852 | * -ENOMEM: damn | |
2853 | * -ENODEV: Internal IRQ fail | |
2854 | * -E?: The add request failed | |
2855 | * | |
2856 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2857 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2858 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2859 | * without holding struct_mutex the object may become re-busied before this | |
2860 | * function completes. A similar but shorter * race condition exists in the busy | |
2861 | * ioctl | |
2862 | */ | |
2863 | int | |
2864 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2865 | { | |
2866 | struct drm_i915_gem_wait *args = data; | |
2867 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
2868 | ktime_t start; |
2869 | long ret; | |
23ba4fd0 | 2870 | |
11b5d511 DV |
2871 | if (args->flags != 0) |
2872 | return -EINVAL; | |
2873 | ||
03ac0642 | 2874 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 2875 | if (!obj) |
23ba4fd0 | 2876 | return -ENOENT; |
23ba4fd0 | 2877 | |
e95433c7 CW |
2878 | start = ktime_get(); |
2879 | ||
2880 | ret = i915_gem_object_wait(obj, | |
2881 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
2882 | to_wait_timeout(args->timeout_ns), | |
2883 | to_rps_client(file)); | |
2884 | ||
2885 | if (args->timeout_ns > 0) { | |
2886 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
2887 | if (args->timeout_ns < 0) | |
2888 | args->timeout_ns = 0; | |
b4716185 CW |
2889 | } |
2890 | ||
f0cd5182 | 2891 | i915_gem_object_put(obj); |
ff865885 | 2892 | return ret; |
23ba4fd0 BW |
2893 | } |
2894 | ||
8ef8561f CW |
2895 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2896 | { | |
20dfbde4 | 2897 | GEM_BUG_ON(i915_vma_is_pinned(vma)); |
8ef8561f CW |
2898 | |
2899 | if (vma->iomap == NULL) | |
2900 | return; | |
2901 | ||
2902 | io_mapping_unmap(vma->iomap); | |
2903 | vma->iomap = NULL; | |
2904 | } | |
2905 | ||
df0e9a28 | 2906 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2907 | { |
07fe0b12 | 2908 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 | 2909 | unsigned long active; |
43e28f09 | 2910 | int ret; |
673a394b | 2911 | |
4c7d62c6 CW |
2912 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
2913 | ||
b0decaf7 CW |
2914 | /* First wait upon any activity as retiring the request may |
2915 | * have side-effects such as unpinning or even unbinding this vma. | |
2916 | */ | |
2917 | active = i915_vma_get_active(vma); | |
df0e9a28 | 2918 | if (active) { |
b0decaf7 CW |
2919 | int idx; |
2920 | ||
b1f788c6 CW |
2921 | /* When a closed VMA is retired, it is unbound - eek. |
2922 | * In order to prevent it from being recursively closed, | |
2923 | * take a pin on the vma so that the second unbind is | |
2924 | * aborted. | |
d07f0e59 CW |
2925 | * |
2926 | * Even more scary is that the retire callback may free | |
2927 | * the object (last active vma). To prevent the explosion | |
2928 | * we defer the actual object free to a worker that can | |
2929 | * only proceed once it acquires the struct_mutex (which | |
2930 | * we currently hold, therefore it cannot free this object | |
2931 | * before we are finished). | |
b1f788c6 | 2932 | */ |
20dfbde4 | 2933 | __i915_vma_pin(vma); |
b1f788c6 | 2934 | |
b0decaf7 CW |
2935 | for_each_active(active, idx) { |
2936 | ret = i915_gem_active_retire(&vma->last_read[idx], | |
2937 | &vma->vm->dev->struct_mutex); | |
2938 | if (ret) | |
b1f788c6 | 2939 | break; |
b0decaf7 CW |
2940 | } |
2941 | ||
20dfbde4 | 2942 | __i915_vma_unpin(vma); |
b1f788c6 CW |
2943 | if (ret) |
2944 | return ret; | |
2945 | ||
b0decaf7 CW |
2946 | GEM_BUG_ON(i915_vma_is_active(vma)); |
2947 | } | |
2948 | ||
20dfbde4 | 2949 | if (i915_vma_is_pinned(vma)) |
b0decaf7 CW |
2950 | return -EBUSY; |
2951 | ||
b1f788c6 CW |
2952 | if (!drm_mm_node_allocated(&vma->node)) |
2953 | goto destroy; | |
433544bd | 2954 | |
15717de2 | 2955 | GEM_BUG_ON(obj->bind_count == 0); |
2c3a3f44 | 2956 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
c4670ad0 | 2957 | |
05a20d09 | 2958 | if (i915_vma_is_map_and_fenceable(vma)) { |
8b1bc9b4 | 2959 | /* release the fence reg _after_ flushing */ |
49ef5294 | 2960 | ret = i915_vma_put_fence(vma); |
8b1bc9b4 DV |
2961 | if (ret) |
2962 | return ret; | |
8ef8561f | 2963 | |
cd3127d6 CW |
2964 | /* Force a pagefault for domain tracking on next user access */ |
2965 | i915_gem_release_mmap(obj); | |
2966 | ||
8ef8561f | 2967 | __i915_vma_iounmap(vma); |
05a20d09 | 2968 | vma->flags &= ~I915_VMA_CAN_FENCE; |
8b1bc9b4 | 2969 | } |
96b47b65 | 2970 | |
50e046b6 CW |
2971 | if (likely(!vma->vm->closed)) { |
2972 | trace_i915_vma_unbind(vma); | |
2973 | vma->vm->unbind_vma(vma); | |
2974 | } | |
3272db53 | 2975 | vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
6f65e29a | 2976 | |
50e046b6 CW |
2977 | drm_mm_remove_node(&vma->node); |
2978 | list_move_tail(&vma->vm_link, &vma->vm->unbound_list); | |
2979 | ||
a4f5ea64 | 2980 | if (vma->pages != obj->mm.pages) { |
05a20d09 CW |
2981 | GEM_BUG_ON(!vma->pages); |
2982 | sg_free_table(vma->pages); | |
2983 | kfree(vma->pages); | |
fe14d5f4 | 2984 | } |
247177dd | 2985 | vma->pages = NULL; |
673a394b | 2986 | |
2f633156 | 2987 | /* Since the unbound list is global, only move to that list if |
b93dab6e | 2988 | * no more VMAs exist. */ |
15717de2 | 2989 | if (--obj->bind_count == 0) |
56cea323 | 2990 | list_move_tail(&obj->global_link, |
15717de2 | 2991 | &to_i915(obj->base.dev)->mm.unbound_list); |
673a394b | 2992 | |
70903c3b CW |
2993 | /* And finally now the object is completely decoupled from this vma, |
2994 | * we can drop its hold on the backing storage and allow it to be | |
2995 | * reaped by the shrinker. | |
2996 | */ | |
2997 | i915_gem_object_unpin_pages(obj); | |
2998 | ||
b1f788c6 | 2999 | destroy: |
3272db53 | 3000 | if (unlikely(i915_vma_is_closed(vma))) |
b1f788c6 CW |
3001 | i915_vma_destroy(vma); |
3002 | ||
88241785 | 3003 | return 0; |
54cf91dc CW |
3004 | } |
3005 | ||
73cb9701 | 3006 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3007 | { |
73cb9701 | 3008 | int ret, i; |
4df2faf4 | 3009 | |
73cb9701 CW |
3010 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3011 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3012 | if (ret) | |
3013 | return ret; | |
3014 | } | |
62e63007 | 3015 | |
73cb9701 CW |
3016 | return 0; |
3017 | } | |
3018 | ||
3019 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) | |
3020 | { | |
3021 | struct i915_gem_timeline *tl; | |
3022 | int ret; | |
3023 | ||
3024 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3025 | ret = wait_for_timeline(tl, flags); | |
1ec14ad3 CW |
3026 | if (ret) |
3027 | return ret; | |
3028 | } | |
4df2faf4 | 3029 | |
8a1a49f9 | 3030 | return 0; |
4df2faf4 DV |
3031 | } |
3032 | ||
4144f9b5 | 3033 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3034 | unsigned long cache_level) |
3035 | { | |
4144f9b5 | 3036 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3037 | struct drm_mm_node *other; |
3038 | ||
4144f9b5 CW |
3039 | /* |
3040 | * On some machines we have to be careful when putting differing types | |
3041 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3042 | * domains and dying. During vm initialisation, we decide whether or not | |
3043 | * these constraints apply and set the drm_mm.color_adjust | |
3044 | * appropriately. | |
42d6ab48 | 3045 | */ |
4144f9b5 | 3046 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3047 | return true; |
3048 | ||
c6cfb325 | 3049 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3050 | return true; |
3051 | ||
3052 | if (list_empty(>t_space->node_list)) | |
3053 | return true; | |
3054 | ||
3055 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3056 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3057 | return false; | |
3058 | ||
3059 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3060 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3061 | return false; | |
3062 | ||
3063 | return true; | |
3064 | } | |
3065 | ||
673a394b | 3066 | /** |
59bfa124 CW |
3067 | * i915_vma_insert - finds a slot for the vma in its address space |
3068 | * @vma: the vma | |
91b2db6f | 3069 | * @size: requested size in bytes (can be larger than the VMA) |
59bfa124 | 3070 | * @alignment: required alignment |
14bb2c11 | 3071 | * @flags: mask of PIN_* flags to use |
59bfa124 CW |
3072 | * |
3073 | * First we try to allocate some free space that meets the requirements for | |
3074 | * the VMA. Failiing that, if the flags permit, it will evict an old VMA, | |
3075 | * preferrably the oldest idle entry to make room for the new VMA. | |
3076 | * | |
3077 | * Returns: | |
3078 | * 0 on success, negative error code otherwise. | |
673a394b | 3079 | */ |
59bfa124 CW |
3080 | static int |
3081 | i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 3082 | { |
59bfa124 CW |
3083 | struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); |
3084 | struct drm_i915_gem_object *obj = vma->obj; | |
de180033 | 3085 | u64 start, end; |
07f73f69 | 3086 | int ret; |
673a394b | 3087 | |
3272db53 | 3088 | GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); |
59bfa124 | 3089 | GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); |
de180033 CW |
3090 | |
3091 | size = max(size, vma->size); | |
3092 | if (flags & PIN_MAPPABLE) | |
3e510a8e CW |
3093 | size = i915_gem_get_ggtt_size(dev_priv, size, |
3094 | i915_gem_object_get_tiling(obj)); | |
de180033 | 3095 | |
d8923dcf CW |
3096 | alignment = max(max(alignment, vma->display_alignment), |
3097 | i915_gem_get_ggtt_alignment(dev_priv, size, | |
3098 | i915_gem_object_get_tiling(obj), | |
3099 | flags & PIN_MAPPABLE)); | |
a00b10c3 | 3100 | |
101b506a | 3101 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
de180033 CW |
3102 | |
3103 | end = vma->vm->total; | |
101b506a | 3104 | if (flags & PIN_MAPPABLE) |
91b2db6f | 3105 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 3106 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3107 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3108 | |
91e6711e JL |
3109 | /* If binding the object/GGTT view requires more space than the entire |
3110 | * aperture has, reject it early before evicting everything in a vain | |
3111 | * attempt to find space. | |
654fc607 | 3112 | */ |
91e6711e | 3113 | if (size > end) { |
de180033 | 3114 | DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", |
91b2db6f | 3115 | size, obj->base.size, |
1ec9e26d | 3116 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3117 | end); |
59bfa124 | 3118 | return -E2BIG; |
654fc607 CW |
3119 | } |
3120 | ||
a4f5ea64 | 3121 | ret = i915_gem_object_pin_pages(obj); |
6c085a72 | 3122 | if (ret) |
59bfa124 | 3123 | return ret; |
6c085a72 | 3124 | |
506a8e87 | 3125 | if (flags & PIN_OFFSET_FIXED) { |
59bfa124 | 3126 | u64 offset = flags & PIN_OFFSET_MASK; |
de180033 | 3127 | if (offset & (alignment - 1) || offset > end - size) { |
506a8e87 | 3128 | ret = -EINVAL; |
de180033 | 3129 | goto err_unpin; |
506a8e87 | 3130 | } |
de180033 | 3131 | |
506a8e87 CW |
3132 | vma->node.start = offset; |
3133 | vma->node.size = size; | |
3134 | vma->node.color = obj->cache_level; | |
de180033 | 3135 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
506a8e87 CW |
3136 | if (ret) { |
3137 | ret = i915_gem_evict_for_vma(vma); | |
3138 | if (ret == 0) | |
de180033 CW |
3139 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
3140 | if (ret) | |
3141 | goto err_unpin; | |
506a8e87 | 3142 | } |
101b506a | 3143 | } else { |
de180033 CW |
3144 | u32 search_flag, alloc_flag; |
3145 | ||
506a8e87 CW |
3146 | if (flags & PIN_HIGH) { |
3147 | search_flag = DRM_MM_SEARCH_BELOW; | |
3148 | alloc_flag = DRM_MM_CREATE_TOP; | |
3149 | } else { | |
3150 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3151 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3152 | } | |
101b506a | 3153 | |
954c4691 CW |
3154 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, |
3155 | * so we know that we always have a minimum alignment of 4096. | |
3156 | * The drm_mm range manager is optimised to return results | |
3157 | * with zero alignment, so where possible use the optimal | |
3158 | * path. | |
3159 | */ | |
3160 | if (alignment <= 4096) | |
3161 | alignment = 0; | |
3162 | ||
0a9ae0d7 | 3163 | search_free: |
de180033 CW |
3164 | ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, |
3165 | &vma->node, | |
506a8e87 CW |
3166 | size, alignment, |
3167 | obj->cache_level, | |
3168 | start, end, | |
3169 | search_flag, | |
3170 | alloc_flag); | |
3171 | if (ret) { | |
de180033 | 3172 | ret = i915_gem_evict_something(vma->vm, size, alignment, |
506a8e87 CW |
3173 | obj->cache_level, |
3174 | start, end, | |
3175 | flags); | |
3176 | if (ret == 0) | |
3177 | goto search_free; | |
9731129c | 3178 | |
de180033 | 3179 | goto err_unpin; |
506a8e87 | 3180 | } |
ad16d2ed CW |
3181 | |
3182 | GEM_BUG_ON(vma->node.start < start); | |
3183 | GEM_BUG_ON(vma->node.start + vma->node.size > end); | |
673a394b | 3184 | } |
37508589 | 3185 | GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); |
673a394b | 3186 | |
56cea323 | 3187 | list_move_tail(&obj->global_link, &dev_priv->mm.bound_list); |
de180033 | 3188 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
15717de2 | 3189 | obj->bind_count++; |
2c3a3f44 | 3190 | GEM_BUG_ON(atomic_read(&obj->mm.pages_pin_count) < obj->bind_count); |
bf1a1092 | 3191 | |
59bfa124 | 3192 | return 0; |
2f633156 | 3193 | |
bc6bc15b | 3194 | err_unpin: |
2f633156 | 3195 | i915_gem_object_unpin_pages(obj); |
59bfa124 | 3196 | return ret; |
673a394b EA |
3197 | } |
3198 | ||
000433b6 | 3199 | bool |
2c22569b CW |
3200 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3201 | bool force) | |
673a394b | 3202 | { |
673a394b EA |
3203 | /* If we don't have a page list set up, then we're not pinned |
3204 | * to GPU, and we can ignore the cache flush because it'll happen | |
3205 | * again at bind time. | |
3206 | */ | |
a4f5ea64 | 3207 | if (!obj->mm.pages) |
000433b6 | 3208 | return false; |
673a394b | 3209 | |
769ce464 ID |
3210 | /* |
3211 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3212 | * marked as wc by the system, or the system is cache-coherent. | |
3213 | */ | |
6a2c4232 | 3214 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3215 | return false; |
769ce464 | 3216 | |
9c23f7fc CW |
3217 | /* If the GPU is snooping the contents of the CPU cache, |
3218 | * we do not need to manually clear the CPU cache lines. However, | |
3219 | * the caches are only snooped when the render cache is | |
3220 | * flushed/invalidated. As we always have to emit invalidations | |
3221 | * and flushes when moving into and out of the RENDER domain, correct | |
3222 | * snooping behaviour occurs naturally as the result of our domain | |
3223 | * tracking. | |
3224 | */ | |
0f71979a CW |
3225 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3226 | obj->cache_dirty = true; | |
000433b6 | 3227 | return false; |
0f71979a | 3228 | } |
9c23f7fc | 3229 | |
1c5d22f7 | 3230 | trace_i915_gem_object_clflush(obj); |
a4f5ea64 | 3231 | drm_clflush_sg(obj->mm.pages); |
0f71979a | 3232 | obj->cache_dirty = false; |
000433b6 CW |
3233 | |
3234 | return true; | |
e47c68e9 EA |
3235 | } |
3236 | ||
3237 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3238 | static void | |
05394f39 | 3239 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3240 | { |
3b5724d7 | 3241 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3242 | |
05394f39 | 3243 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3244 | return; |
3245 | ||
63256ec5 | 3246 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3247 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3248 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3249 | * |
3250 | * However, we do have to enforce the order so that all writes through | |
3251 | * the GTT land before any writes to the device, such as updates to | |
3252 | * the GATT itself. | |
3b5724d7 CW |
3253 | * |
3254 | * We also have to wait a bit for the writes to land from the GTT. | |
3255 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3256 | * timing. This issue has only been observed when switching quickly | |
3257 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3258 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3259 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3260 | */ |
63256ec5 | 3261 | wmb(); |
3b5724d7 | 3262 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3b3f1650 | 3263 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); |
63256ec5 | 3264 | |
d243ad82 | 3265 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3266 | |
b0dc465f | 3267 | obj->base.write_domain = 0; |
1c5d22f7 | 3268 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3269 | obj->base.read_domains, |
b0dc465f | 3270 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3271 | } |
3272 | ||
3273 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3274 | static void | |
e62b59e4 | 3275 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3276 | { |
05394f39 | 3277 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3278 | return; |
3279 | ||
e62b59e4 | 3280 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3281 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3282 | |
de152b62 | 3283 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3284 | |
b0dc465f | 3285 | obj->base.write_domain = 0; |
1c5d22f7 | 3286 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3287 | obj->base.read_domains, |
b0dc465f | 3288 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3289 | } |
3290 | ||
2ef7eeaa EA |
3291 | /** |
3292 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3293 | * @obj: object to act on |
3294 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3295 | * |
3296 | * This function returns when the move is complete, including waiting on | |
3297 | * flushes to occur. | |
3298 | */ | |
79e53945 | 3299 | int |
2021746e | 3300 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3301 | { |
1c5d22f7 | 3302 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3303 | int ret; |
2ef7eeaa | 3304 | |
e95433c7 | 3305 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3306 | |
e95433c7 CW |
3307 | ret = i915_gem_object_wait(obj, |
3308 | I915_WAIT_INTERRUPTIBLE | | |
3309 | I915_WAIT_LOCKED | | |
3310 | (write ? I915_WAIT_ALL : 0), | |
3311 | MAX_SCHEDULE_TIMEOUT, | |
3312 | NULL); | |
88241785 CW |
3313 | if (ret) |
3314 | return ret; | |
3315 | ||
c13d87ea CW |
3316 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3317 | return 0; | |
3318 | ||
43566ded CW |
3319 | /* Flush and acquire obj->pages so that we are coherent through |
3320 | * direct access in memory with previous cached writes through | |
3321 | * shmemfs and that our cache domain tracking remains valid. | |
3322 | * For example, if the obj->filp was moved to swap without us | |
3323 | * being notified and releasing the pages, we would mistakenly | |
3324 | * continue to assume that the obj remained out of the CPU cached | |
3325 | * domain. | |
3326 | */ | |
a4f5ea64 | 3327 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3328 | if (ret) |
3329 | return ret; | |
3330 | ||
e62b59e4 | 3331 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3332 | |
d0a57789 CW |
3333 | /* Serialise direct access to this object with the barriers for |
3334 | * coherent writes from the GPU, by effectively invalidating the | |
3335 | * GTT domain upon first access. | |
3336 | */ | |
3337 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3338 | mb(); | |
3339 | ||
05394f39 CW |
3340 | old_write_domain = obj->base.write_domain; |
3341 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3342 | |
e47c68e9 EA |
3343 | /* It should now be out of any other write domains, and we can update |
3344 | * the domain values for our changes. | |
3345 | */ | |
40e62d5d | 3346 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3347 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3348 | if (write) { |
05394f39 CW |
3349 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3350 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3351 | obj->mm.dirty = true; |
2ef7eeaa EA |
3352 | } |
3353 | ||
1c5d22f7 CW |
3354 | trace_i915_gem_object_change_domain(obj, |
3355 | old_read_domains, | |
3356 | old_write_domain); | |
3357 | ||
a4f5ea64 | 3358 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3359 | return 0; |
3360 | } | |
3361 | ||
ef55f92a CW |
3362 | /** |
3363 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3364 | * @obj: object to act on |
3365 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3366 | * |
3367 | * After this function returns, the object will be in the new cache-level | |
3368 | * across all GTT and the contents of the backing storage will be coherent, | |
3369 | * with respect to the new cache-level. In order to keep the backing storage | |
3370 | * coherent for all users, we only allow a single cache level to be set | |
3371 | * globally on the object and prevent it from being changed whilst the | |
3372 | * hardware is reading from the object. That is if the object is currently | |
3373 | * on the scanout it will be set to uncached (or equivalent display | |
3374 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3375 | * that all direct access to the scanout remains coherent. | |
3376 | */ | |
e4ffd173 CW |
3377 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3378 | enum i915_cache_level cache_level) | |
3379 | { | |
aa653a68 | 3380 | struct i915_vma *vma; |
ed75a55b | 3381 | int ret = 0; |
e4ffd173 | 3382 | |
4c7d62c6 CW |
3383 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3384 | ||
e4ffd173 | 3385 | if (obj->cache_level == cache_level) |
ed75a55b | 3386 | goto out; |
e4ffd173 | 3387 | |
ef55f92a CW |
3388 | /* Inspect the list of currently bound VMA and unbind any that would |
3389 | * be invalid given the new cache-level. This is principally to | |
3390 | * catch the issue of the CS prefetch crossing page boundaries and | |
3391 | * reading an invalid PTE on older architectures. | |
3392 | */ | |
aa653a68 CW |
3393 | restart: |
3394 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3395 | if (!drm_mm_node_allocated(&vma->node)) |
3396 | continue; | |
3397 | ||
20dfbde4 | 3398 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3399 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3400 | return -EBUSY; | |
3401 | } | |
3402 | ||
aa653a68 CW |
3403 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3404 | continue; | |
3405 | ||
3406 | ret = i915_vma_unbind(vma); | |
3407 | if (ret) | |
3408 | return ret; | |
3409 | ||
3410 | /* As unbinding may affect other elements in the | |
3411 | * obj->vma_list (due to side-effects from retiring | |
3412 | * an active vma), play safe and restart the iterator. | |
3413 | */ | |
3414 | goto restart; | |
42d6ab48 CW |
3415 | } |
3416 | ||
ef55f92a CW |
3417 | /* We can reuse the existing drm_mm nodes but need to change the |
3418 | * cache-level on the PTE. We could simply unbind them all and | |
3419 | * rebind with the correct cache-level on next use. However since | |
3420 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3421 | * rewrite the PTE in the belief that doing so tramples upon less | |
3422 | * state and so involves less work. | |
3423 | */ | |
15717de2 | 3424 | if (obj->bind_count) { |
ef55f92a CW |
3425 | /* Before we change the PTE, the GPU must not be accessing it. |
3426 | * If we wait upon the object, we know that all the bound | |
3427 | * VMA are no longer active. | |
3428 | */ | |
e95433c7 CW |
3429 | ret = i915_gem_object_wait(obj, |
3430 | I915_WAIT_INTERRUPTIBLE | | |
3431 | I915_WAIT_LOCKED | | |
3432 | I915_WAIT_ALL, | |
3433 | MAX_SCHEDULE_TIMEOUT, | |
3434 | NULL); | |
e4ffd173 CW |
3435 | if (ret) |
3436 | return ret; | |
3437 | ||
aa653a68 | 3438 | if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { |
ef55f92a CW |
3439 | /* Access to snoopable pages through the GTT is |
3440 | * incoherent and on some machines causes a hard | |
3441 | * lockup. Relinquish the CPU mmaping to force | |
3442 | * userspace to refault in the pages and we can | |
3443 | * then double check if the GTT mapping is still | |
3444 | * valid for that pointer access. | |
3445 | */ | |
3446 | i915_gem_release_mmap(obj); | |
3447 | ||
3448 | /* As we no longer need a fence for GTT access, | |
3449 | * we can relinquish it now (and so prevent having | |
3450 | * to steal a fence from someone else on the next | |
3451 | * fence request). Note GPU activity would have | |
3452 | * dropped the fence as all snoopable access is | |
3453 | * supposed to be linear. | |
3454 | */ | |
49ef5294 CW |
3455 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3456 | ret = i915_vma_put_fence(vma); | |
3457 | if (ret) | |
3458 | return ret; | |
3459 | } | |
ef55f92a CW |
3460 | } else { |
3461 | /* We either have incoherent backing store and | |
3462 | * so no GTT access or the architecture is fully | |
3463 | * coherent. In such cases, existing GTT mmaps | |
3464 | * ignore the cache bit in the PTE and we can | |
3465 | * rewrite it without confusing the GPU or having | |
3466 | * to force userspace to fault back in its mmaps. | |
3467 | */ | |
e4ffd173 CW |
3468 | } |
3469 | ||
1c7f4bca | 3470 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3471 | if (!drm_mm_node_allocated(&vma->node)) |
3472 | continue; | |
3473 | ||
3474 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3475 | if (ret) | |
3476 | return ret; | |
3477 | } | |
e4ffd173 CW |
3478 | } |
3479 | ||
1c7f4bca | 3480 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3481 | vma->node.color = cache_level; |
3482 | obj->cache_level = cache_level; | |
3483 | ||
ed75a55b | 3484 | out: |
ef55f92a CW |
3485 | /* Flush the dirty CPU caches to the backing storage so that the |
3486 | * object is now coherent at its new cache level (with respect | |
3487 | * to the access domain). | |
3488 | */ | |
b50a5371 | 3489 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3490 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3491 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3492 | } |
3493 | ||
e4ffd173 CW |
3494 | return 0; |
3495 | } | |
3496 | ||
199adf40 BW |
3497 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3498 | struct drm_file *file) | |
e6994aee | 3499 | { |
199adf40 | 3500 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3501 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3502 | int err = 0; |
e6994aee | 3503 | |
fbbd37b3 CW |
3504 | rcu_read_lock(); |
3505 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3506 | if (!obj) { | |
3507 | err = -ENOENT; | |
3508 | goto out; | |
3509 | } | |
e6994aee | 3510 | |
651d794f CW |
3511 | switch (obj->cache_level) { |
3512 | case I915_CACHE_LLC: | |
3513 | case I915_CACHE_L3_LLC: | |
3514 | args->caching = I915_CACHING_CACHED; | |
3515 | break; | |
3516 | ||
4257d3ba CW |
3517 | case I915_CACHE_WT: |
3518 | args->caching = I915_CACHING_DISPLAY; | |
3519 | break; | |
3520 | ||
651d794f CW |
3521 | default: |
3522 | args->caching = I915_CACHING_NONE; | |
3523 | break; | |
3524 | } | |
fbbd37b3 CW |
3525 | out: |
3526 | rcu_read_unlock(); | |
3527 | return err; | |
e6994aee CW |
3528 | } |
3529 | ||
199adf40 BW |
3530 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3531 | struct drm_file *file) | |
e6994aee | 3532 | { |
9c870d03 | 3533 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3534 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3535 | struct drm_i915_gem_object *obj; |
3536 | enum i915_cache_level level; | |
3537 | int ret; | |
3538 | ||
199adf40 BW |
3539 | switch (args->caching) { |
3540 | case I915_CACHING_NONE: | |
e6994aee CW |
3541 | level = I915_CACHE_NONE; |
3542 | break; | |
199adf40 | 3543 | case I915_CACHING_CACHED: |
e5756c10 ID |
3544 | /* |
3545 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3546 | * snooped mapping may leave stale data in a corresponding CPU | |
3547 | * cacheline, whereas normally such cachelines would get | |
3548 | * invalidated. | |
3549 | */ | |
9c870d03 | 3550 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3551 | return -ENODEV; |
3552 | ||
e6994aee CW |
3553 | level = I915_CACHE_LLC; |
3554 | break; | |
4257d3ba | 3555 | case I915_CACHING_DISPLAY: |
9c870d03 | 3556 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3557 | break; |
e6994aee CW |
3558 | default: |
3559 | return -EINVAL; | |
3560 | } | |
3561 | ||
3bc2913e BW |
3562 | ret = i915_mutex_lock_interruptible(dev); |
3563 | if (ret) | |
9c870d03 | 3564 | return ret; |
3bc2913e | 3565 | |
03ac0642 CW |
3566 | obj = i915_gem_object_lookup(file, args->handle); |
3567 | if (!obj) { | |
e6994aee CW |
3568 | ret = -ENOENT; |
3569 | goto unlock; | |
3570 | } | |
3571 | ||
3572 | ret = i915_gem_object_set_cache_level(obj, level); | |
f8c417cd | 3573 | i915_gem_object_put(obj); |
e6994aee CW |
3574 | unlock: |
3575 | mutex_unlock(&dev->struct_mutex); | |
3576 | return ret; | |
3577 | } | |
3578 | ||
b9241ea3 | 3579 | /* |
2da3b9b9 CW |
3580 | * Prepare buffer for display plane (scanout, cursors, etc). |
3581 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3582 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3583 | */ |
058d88c4 | 3584 | struct i915_vma * |
2da3b9b9 CW |
3585 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3586 | u32 alignment, | |
e6617330 | 3587 | const struct i915_ggtt_view *view) |
b9241ea3 | 3588 | { |
058d88c4 | 3589 | struct i915_vma *vma; |
2da3b9b9 | 3590 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3591 | int ret; |
3592 | ||
4c7d62c6 CW |
3593 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3594 | ||
cc98b413 CW |
3595 | /* Mark the pin_display early so that we account for the |
3596 | * display coherency whilst setting up the cache domains. | |
3597 | */ | |
8a0c39b1 | 3598 | obj->pin_display++; |
cc98b413 | 3599 | |
a7ef0640 EA |
3600 | /* The display engine is not coherent with the LLC cache on gen6. As |
3601 | * a result, we make sure that the pinning that is about to occur is | |
3602 | * done with uncached PTEs. This is lowest common denominator for all | |
3603 | * chipsets. | |
3604 | * | |
3605 | * However for gen6+, we could do better by using the GFDT bit instead | |
3606 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3607 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3608 | */ | |
651d794f | 3609 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3610 | HAS_WT(to_i915(obj->base.dev)) ? |
3611 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3612 | if (ret) { |
3613 | vma = ERR_PTR(ret); | |
cc98b413 | 3614 | goto err_unpin_display; |
058d88c4 | 3615 | } |
a7ef0640 | 3616 | |
2da3b9b9 CW |
3617 | /* As the user may map the buffer once pinned in the display plane |
3618 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3619 | * always use map_and_fenceable for all scanout buffers. However, |
3620 | * it may simply be too big to fit into mappable, in which case | |
3621 | * put it anyway and hope that userspace can cope (but always first | |
3622 | * try to preserve the existing ABI). | |
2da3b9b9 | 3623 | */ |
2efb813d CW |
3624 | vma = ERR_PTR(-ENOSPC); |
3625 | if (view->type == I915_GGTT_VIEW_NORMAL) | |
3626 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, | |
3627 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3628 | if (IS_ERR(vma)) { |
3629 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3630 | unsigned int flags; | |
3631 | ||
3632 | /* Valleyview is definitely limited to scanning out the first | |
3633 | * 512MiB. Lets presume this behaviour was inherited from the | |
3634 | * g4x display engine and that all earlier gen are similarly | |
3635 | * limited. Testing suggests that it is a little more | |
3636 | * complicated than this. For example, Cherryview appears quite | |
3637 | * happy to scanout from anywhere within its global aperture. | |
3638 | */ | |
3639 | flags = 0; | |
3640 | if (HAS_GMCH_DISPLAY(i915)) | |
3641 | flags = PIN_MAPPABLE; | |
3642 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3643 | } | |
058d88c4 | 3644 | if (IS_ERR(vma)) |
cc98b413 | 3645 | goto err_unpin_display; |
2da3b9b9 | 3646 | |
d8923dcf CW |
3647 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3648 | ||
e62b59e4 | 3649 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3650 | |
2da3b9b9 | 3651 | old_write_domain = obj->base.write_domain; |
05394f39 | 3652 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3653 | |
3654 | /* It should now be out of any other write domains, and we can update | |
3655 | * the domain values for our changes. | |
3656 | */ | |
e5f1d962 | 3657 | obj->base.write_domain = 0; |
05394f39 | 3658 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3659 | |
3660 | trace_i915_gem_object_change_domain(obj, | |
3661 | old_read_domains, | |
2da3b9b9 | 3662 | old_write_domain); |
b9241ea3 | 3663 | |
058d88c4 | 3664 | return vma; |
cc98b413 CW |
3665 | |
3666 | err_unpin_display: | |
8a0c39b1 | 3667 | obj->pin_display--; |
058d88c4 | 3668 | return vma; |
cc98b413 CW |
3669 | } |
3670 | ||
3671 | void | |
058d88c4 | 3672 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3673 | { |
4c7d62c6 CW |
3674 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
3675 | ||
058d88c4 | 3676 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3677 | return; |
3678 | ||
d8923dcf CW |
3679 | if (--vma->obj->pin_display == 0) |
3680 | vma->display_alignment = 0; | |
e6617330 | 3681 | |
383d5823 CW |
3682 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
3683 | if (!i915_vma_is_active(vma)) | |
3684 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3685 | ||
058d88c4 | 3686 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3687 | } |
3688 | ||
e47c68e9 EA |
3689 | /** |
3690 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3691 | * @obj: object to act on |
3692 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3693 | * |
3694 | * This function returns when the move is complete, including waiting on | |
3695 | * flushes to occur. | |
3696 | */ | |
dabdfe02 | 3697 | int |
919926ae | 3698 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3699 | { |
1c5d22f7 | 3700 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3701 | int ret; |
3702 | ||
e95433c7 | 3703 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3704 | |
e95433c7 CW |
3705 | ret = i915_gem_object_wait(obj, |
3706 | I915_WAIT_INTERRUPTIBLE | | |
3707 | I915_WAIT_LOCKED | | |
3708 | (write ? I915_WAIT_ALL : 0), | |
3709 | MAX_SCHEDULE_TIMEOUT, | |
3710 | NULL); | |
88241785 CW |
3711 | if (ret) |
3712 | return ret; | |
3713 | ||
c13d87ea CW |
3714 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3715 | return 0; | |
3716 | ||
e47c68e9 | 3717 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3718 | |
05394f39 CW |
3719 | old_write_domain = obj->base.write_domain; |
3720 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3721 | |
e47c68e9 | 3722 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3723 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3724 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3725 | |
05394f39 | 3726 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3727 | } |
3728 | ||
3729 | /* It should now be out of any other write domains, and we can update | |
3730 | * the domain values for our changes. | |
3731 | */ | |
40e62d5d | 3732 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3733 | |
3734 | /* If we're writing through the CPU, then the GPU read domains will | |
3735 | * need to be invalidated at next use. | |
3736 | */ | |
3737 | if (write) { | |
05394f39 CW |
3738 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3739 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3740 | } |
2ef7eeaa | 3741 | |
1c5d22f7 CW |
3742 | trace_i915_gem_object_change_domain(obj, |
3743 | old_read_domains, | |
3744 | old_write_domain); | |
3745 | ||
2ef7eeaa EA |
3746 | return 0; |
3747 | } | |
3748 | ||
673a394b EA |
3749 | /* Throttle our rendering by waiting until the ring has completed our requests |
3750 | * emitted over 20 msec ago. | |
3751 | * | |
b962442e EA |
3752 | * Note that if we were to use the current jiffies each time around the loop, |
3753 | * we wouldn't escape the function with any frames outstanding if the time to | |
3754 | * render a frame was over 20ms. | |
3755 | * | |
673a394b EA |
3756 | * This should get us reasonable parallelism between CPU and GPU but also |
3757 | * relatively low latency when blocking on a particular request to finish. | |
3758 | */ | |
40a5f0de | 3759 | static int |
f787a5f5 | 3760 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3761 | { |
fac5e23e | 3762 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3763 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3764 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3765 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3766 | long ret; |
93533c29 | 3767 | |
f4457ae7 CW |
3768 | /* ABI: return -EIO if already wedged */ |
3769 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3770 | return -EIO; | |
e110e8d6 | 3771 | |
1c25595f | 3772 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3773 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3774 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3775 | break; | |
40a5f0de | 3776 | |
fcfa423c JH |
3777 | /* |
3778 | * Note that the request might not have been submitted yet. | |
3779 | * In which case emitted_jiffies will be zero. | |
3780 | */ | |
3781 | if (!request->emitted_jiffies) | |
3782 | continue; | |
3783 | ||
54fb2411 | 3784 | target = request; |
b962442e | 3785 | } |
ff865885 | 3786 | if (target) |
e8a261ea | 3787 | i915_gem_request_get(target); |
1c25595f | 3788 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3789 | |
54fb2411 | 3790 | if (target == NULL) |
f787a5f5 | 3791 | return 0; |
2bc43b5c | 3792 | |
e95433c7 CW |
3793 | ret = i915_wait_request(target, |
3794 | I915_WAIT_INTERRUPTIBLE, | |
3795 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3796 | i915_gem_request_put(target); |
ff865885 | 3797 | |
e95433c7 | 3798 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3799 | } |
3800 | ||
d23db88c | 3801 | static bool |
91b2db6f | 3802 | i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) |
d23db88c | 3803 | { |
59bfa124 CW |
3804 | if (!drm_mm_node_allocated(&vma->node)) |
3805 | return false; | |
3806 | ||
91b2db6f CW |
3807 | if (vma->node.size < size) |
3808 | return true; | |
3809 | ||
3810 | if (alignment && vma->node.start & (alignment - 1)) | |
d23db88c CW |
3811 | return true; |
3812 | ||
05a20d09 | 3813 | if (flags & PIN_MAPPABLE && !i915_vma_is_map_and_fenceable(vma)) |
d23db88c CW |
3814 | return true; |
3815 | ||
3816 | if (flags & PIN_OFFSET_BIAS && | |
3817 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3818 | return true; | |
3819 | ||
506a8e87 CW |
3820 | if (flags & PIN_OFFSET_FIXED && |
3821 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3822 | return true; | |
3823 | ||
d23db88c CW |
3824 | return false; |
3825 | } | |
3826 | ||
d0710abb CW |
3827 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3828 | { | |
3829 | struct drm_i915_gem_object *obj = vma->obj; | |
a9f1481f | 3830 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d0710abb CW |
3831 | bool mappable, fenceable; |
3832 | u32 fence_size, fence_alignment; | |
3833 | ||
a9f1481f | 3834 | fence_size = i915_gem_get_ggtt_size(dev_priv, |
05a20d09 | 3835 | vma->size, |
3e510a8e | 3836 | i915_gem_object_get_tiling(obj)); |
a9f1481f | 3837 | fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, |
05a20d09 | 3838 | vma->size, |
3e510a8e | 3839 | i915_gem_object_get_tiling(obj), |
ad1a7d20 | 3840 | true); |
d0710abb CW |
3841 | |
3842 | fenceable = (vma->node.size == fence_size && | |
3843 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3844 | ||
3845 | mappable = (vma->node.start + fence_size <= | |
a9f1481f | 3846 | dev_priv->ggtt.mappable_end); |
d0710abb | 3847 | |
07ee2bce TU |
3848 | /* |
3849 | * Explicitly disable for rotated VMA since the display does not | |
3850 | * need the fence and the VMA is not accessible to other users. | |
3851 | */ | |
3852 | if (mappable && fenceable && | |
3853 | vma->ggtt_view.type != I915_GGTT_VIEW_ROTATED) | |
05a20d09 CW |
3854 | vma->flags |= I915_VMA_CAN_FENCE; |
3855 | else | |
3856 | vma->flags &= ~I915_VMA_CAN_FENCE; | |
d0710abb CW |
3857 | } |
3858 | ||
305bc234 CW |
3859 | int __i915_vma_do_pin(struct i915_vma *vma, |
3860 | u64 size, u64 alignment, u64 flags) | |
673a394b | 3861 | { |
305bc234 | 3862 | unsigned int bound = vma->flags; |
673a394b EA |
3863 | int ret; |
3864 | ||
4c7d62c6 | 3865 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
59bfa124 | 3866 | GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); |
3272db53 | 3867 | GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); |
d7f46fc4 | 3868 | |
305bc234 CW |
3869 | if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { |
3870 | ret = -EBUSY; | |
3871 | goto err; | |
3872 | } | |
ac0c6b5a | 3873 | |
de895082 | 3874 | if ((bound & I915_VMA_BIND_MASK) == 0) { |
59bfa124 CW |
3875 | ret = i915_vma_insert(vma, size, alignment, flags); |
3876 | if (ret) | |
3877 | goto err; | |
fe14d5f4 | 3878 | } |
74898d7e | 3879 | |
59bfa124 | 3880 | ret = i915_vma_bind(vma, vma->obj->cache_level, flags); |
3b16525c | 3881 | if (ret) |
59bfa124 | 3882 | goto err; |
3b16525c | 3883 | |
3272db53 | 3884 | if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) |
d0710abb | 3885 | __i915_vma_set_map_and_fenceable(vma); |
ef79e17c | 3886 | |
3b16525c | 3887 | GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); |
673a394b | 3888 | return 0; |
673a394b | 3889 | |
59bfa124 CW |
3890 | err: |
3891 | __i915_vma_unpin(vma); | |
3892 | return ret; | |
ec7adb6e JL |
3893 | } |
3894 | ||
058d88c4 | 3895 | struct i915_vma * |
ec7adb6e JL |
3896 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3897 | const struct i915_ggtt_view *view, | |
91b2db6f | 3898 | u64 size, |
2ffffd0f CW |
3899 | u64 alignment, |
3900 | u64 flags) | |
ec7adb6e | 3901 | { |
ad16d2ed CW |
3902 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3903 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3904 | struct i915_vma *vma; |
3905 | int ret; | |
72e96d64 | 3906 | |
4c7d62c6 CW |
3907 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3908 | ||
058d88c4 | 3909 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view); |
59bfa124 | 3910 | if (IS_ERR(vma)) |
058d88c4 | 3911 | return vma; |
59bfa124 CW |
3912 | |
3913 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3914 | if (flags & PIN_NONBLOCK && | |
3915 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3916 | return ERR_PTR(-ENOSPC); |
59bfa124 | 3917 | |
ad16d2ed CW |
3918 | if (flags & PIN_MAPPABLE) { |
3919 | u32 fence_size; | |
3920 | ||
3921 | fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size, | |
3922 | i915_gem_object_get_tiling(obj)); | |
3923 | /* If the required space is larger than the available | |
3924 | * aperture, we will not able to find a slot for the | |
3925 | * object and unbinding the object now will be in | |
3926 | * vain. Worse, doing so may cause us to ping-pong | |
3927 | * the object in and out of the Global GTT and | |
3928 | * waste a lot of cycles under the mutex. | |
3929 | */ | |
3930 | if (fence_size > dev_priv->ggtt.mappable_end) | |
3931 | return ERR_PTR(-E2BIG); | |
3932 | ||
3933 | /* If NONBLOCK is set the caller is optimistically | |
3934 | * trying to cache the full object within the mappable | |
3935 | * aperture, and *must* have a fallback in place for | |
3936 | * situations where we cannot bind the object. We | |
3937 | * can be a little more lax here and use the fallback | |
3938 | * more often to avoid costly migrations of ourselves | |
3939 | * and other objects within the aperture. | |
3940 | * | |
3941 | * Half-the-aperture is used as a simple heuristic. | |
3942 | * More interesting would to do search for a free | |
3943 | * block prior to making the commitment to unbind. | |
3944 | * That caters for the self-harm case, and with a | |
3945 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
3946 | * we could try to minimise harm to others. | |
3947 | */ | |
3948 | if (flags & PIN_NONBLOCK && | |
3949 | fence_size > dev_priv->ggtt.mappable_end / 2) | |
3950 | return ERR_PTR(-ENOSPC); | |
3951 | } | |
3952 | ||
59bfa124 CW |
3953 | WARN(i915_vma_is_pinned(vma), |
3954 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3955 | " offset=%08x, req.alignment=%llx," |
3956 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3957 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3958 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3959 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3960 | ret = i915_vma_unbind(vma); |
3961 | if (ret) | |
058d88c4 | 3962 | return ERR_PTR(ret); |
59bfa124 CW |
3963 | } |
3964 | ||
058d88c4 CW |
3965 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3966 | if (ret) | |
3967 | return ERR_PTR(ret); | |
ec7adb6e | 3968 | |
058d88c4 | 3969 | return vma; |
673a394b EA |
3970 | } |
3971 | ||
edf6b76f | 3972 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3973 | { |
3974 | /* Note that we could alias engines in the execbuf API, but | |
3975 | * that would be very unwise as it prevents userspace from | |
3976 | * fine control over engine selection. Ahem. | |
3977 | * | |
3978 | * This should be something like EXEC_MAX_ENGINE instead of | |
3979 | * I915_NUM_ENGINES. | |
3980 | */ | |
3981 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3982 | return 0x10000 << id; | |
3983 | } | |
3984 | ||
3985 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3986 | { | |
70cb472c CW |
3987 | /* The uABI guarantees an active writer is also amongst the read |
3988 | * engines. This would be true if we accessed the activity tracking | |
3989 | * under the lock, but as we perform the lookup of the object and | |
3990 | * its activity locklessly we can not guarantee that the last_write | |
3991 | * being active implies that we have set the same engine flag from | |
3992 | * last_read - hence we always set both read and write busy for | |
3993 | * last_write. | |
3994 | */ | |
3995 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3996 | } |
3997 | ||
edf6b76f | 3998 | static __always_inline unsigned int |
d07f0e59 | 3999 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
4000 | unsigned int (*flag)(unsigned int id)) |
4001 | { | |
d07f0e59 | 4002 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 4003 | |
d07f0e59 CW |
4004 | /* We have to check the current hw status of the fence as the uABI |
4005 | * guarantees forward progress. We could rely on the idle worker | |
4006 | * to eventually flush us, but to minimise latency just ask the | |
4007 | * hardware. | |
1255501d | 4008 | * |
d07f0e59 | 4009 | * Note we only report on the status of native fences. |
1255501d | 4010 | */ |
d07f0e59 CW |
4011 | if (!dma_fence_is_i915(fence)) |
4012 | return 0; | |
4013 | ||
4014 | /* opencode to_request() in order to avoid const warnings */ | |
4015 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
4016 | if (i915_gem_request_completed(rq)) | |
4017 | return 0; | |
4018 | ||
4019 | return flag(rq->engine->exec_id); | |
3fdc13c7 CW |
4020 | } |
4021 | ||
edf6b76f | 4022 | static __always_inline unsigned int |
d07f0e59 | 4023 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 4024 | { |
d07f0e59 | 4025 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
4026 | } |
4027 | ||
edf6b76f | 4028 | static __always_inline unsigned int |
d07f0e59 | 4029 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 4030 | { |
d07f0e59 CW |
4031 | if (!fence) |
4032 | return 0; | |
4033 | ||
4034 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
4035 | } |
4036 | ||
673a394b EA |
4037 | int |
4038 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4039 | struct drm_file *file) |
673a394b EA |
4040 | { |
4041 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4042 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
4043 | struct reservation_object_list *list; |
4044 | unsigned int seq; | |
fbbd37b3 | 4045 | int err; |
673a394b | 4046 | |
d07f0e59 | 4047 | err = -ENOENT; |
fbbd37b3 CW |
4048 | rcu_read_lock(); |
4049 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 4050 | if (!obj) |
fbbd37b3 | 4051 | goto out; |
d1b851fc | 4052 | |
d07f0e59 CW |
4053 | /* A discrepancy here is that we do not report the status of |
4054 | * non-i915 fences, i.e. even though we may report the object as idle, | |
4055 | * a call to set-domain may still stall waiting for foreign rendering. | |
4056 | * This also means that wait-ioctl may report an object as busy, | |
4057 | * where busy-ioctl considers it idle. | |
4058 | * | |
4059 | * We trade the ability to warn of foreign fences to report on which | |
4060 | * i915 engines are active for the object. | |
4061 | * | |
4062 | * Alternatively, we can trade that extra information on read/write | |
4063 | * activity with | |
4064 | * args->busy = | |
4065 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
4066 | * to report the overall busyness. This is what the wait-ioctl does. | |
4067 | * | |
4068 | */ | |
4069 | retry: | |
4070 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 4071 | |
d07f0e59 CW |
4072 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
4073 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 4074 | |
d07f0e59 CW |
4075 | /* Translate shared fences to READ set of engines */ |
4076 | list = rcu_dereference(obj->resv->fence); | |
4077 | if (list) { | |
4078 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 4079 | |
d07f0e59 CW |
4080 | for (i = 0; i < shared_count; ++i) { |
4081 | struct dma_fence *fence = | |
4082 | rcu_dereference(list->shared[i]); | |
4083 | ||
4084 | args->busy |= busy_check_reader(fence); | |
4085 | } | |
426960be | 4086 | } |
673a394b | 4087 | |
d07f0e59 CW |
4088 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
4089 | goto retry; | |
4090 | ||
4091 | err = 0; | |
fbbd37b3 CW |
4092 | out: |
4093 | rcu_read_unlock(); | |
4094 | return err; | |
673a394b EA |
4095 | } |
4096 | ||
4097 | int | |
4098 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4099 | struct drm_file *file_priv) | |
4100 | { | |
0206e353 | 4101 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4102 | } |
4103 | ||
3ef94daa CW |
4104 | int |
4105 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4106 | struct drm_file *file_priv) | |
4107 | { | |
fac5e23e | 4108 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4109 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4110 | struct drm_i915_gem_object *obj; |
1233e2db | 4111 | int err; |
3ef94daa CW |
4112 | |
4113 | switch (args->madv) { | |
4114 | case I915_MADV_DONTNEED: | |
4115 | case I915_MADV_WILLNEED: | |
4116 | break; | |
4117 | default: | |
4118 | return -EINVAL; | |
4119 | } | |
4120 | ||
03ac0642 | 4121 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
4122 | if (!obj) |
4123 | return -ENOENT; | |
4124 | ||
4125 | err = mutex_lock_interruptible(&obj->mm.lock); | |
4126 | if (err) | |
4127 | goto out; | |
3ef94daa | 4128 | |
a4f5ea64 | 4129 | if (obj->mm.pages && |
3e510a8e | 4130 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 4131 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
4132 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
4133 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 4134 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
4135 | obj->mm.quirked = false; |
4136 | } | |
4137 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 4138 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 4139 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
4140 | obj->mm.quirked = true; |
4141 | } | |
656bfa3a DV |
4142 | } |
4143 | ||
a4f5ea64 CW |
4144 | if (obj->mm.madv != __I915_MADV_PURGED) |
4145 | obj->mm.madv = args->madv; | |
3ef94daa | 4146 | |
6c085a72 | 4147 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 4148 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
4149 | i915_gem_object_truncate(obj); |
4150 | ||
a4f5ea64 | 4151 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 4152 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 4153 | |
1233e2db | 4154 | out: |
f8c417cd | 4155 | i915_gem_object_put(obj); |
1233e2db | 4156 | return err; |
3ef94daa CW |
4157 | } |
4158 | ||
37e680a1 CW |
4159 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4160 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4161 | { |
1233e2db CW |
4162 | mutex_init(&obj->mm.lock); |
4163 | ||
56cea323 | 4164 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 4165 | INIT_LIST_HEAD(&obj->userfault_link); |
b25cb2f8 | 4166 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4167 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4168 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4169 | |
37e680a1 CW |
4170 | obj->ops = ops; |
4171 | ||
d07f0e59 CW |
4172 | reservation_object_init(&obj->__builtin_resv); |
4173 | obj->resv = &obj->__builtin_resv; | |
4174 | ||
50349247 | 4175 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
a4f5ea64 CW |
4176 | |
4177 | obj->mm.madv = I915_MADV_WILLNEED; | |
4178 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4179 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4180 | |
f19ec8cb | 4181 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4182 | } |
4183 | ||
37e680a1 | 4184 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
4185 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
4186 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
37e680a1 CW |
4187 | .get_pages = i915_gem_object_get_pages_gtt, |
4188 | .put_pages = i915_gem_object_put_pages_gtt, | |
4189 | }; | |
4190 | ||
b4bcbe2a CW |
4191 | /* Note we don't consider signbits :| */ |
4192 | #define overflows_type(x, T) \ | |
4193 | (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE)) | |
4194 | ||
4195 | struct drm_i915_gem_object * | |
4196 | i915_gem_object_create(struct drm_device *dev, u64 size) | |
ac52bc56 | 4197 | { |
a26e5239 | 4198 | struct drm_i915_private *dev_priv = to_i915(dev); |
c397b908 | 4199 | struct drm_i915_gem_object *obj; |
5949eac4 | 4200 | struct address_space *mapping; |
1a240d4d | 4201 | gfp_t mask; |
fe3db79b | 4202 | int ret; |
ac52bc56 | 4203 | |
b4bcbe2a CW |
4204 | /* There is a prevalence of the assumption that we fit the object's |
4205 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4206 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4207 | * such a local variable, please consider fixing! | |
4208 | */ | |
4209 | if (WARN_ON(size >> PAGE_SHIFT > INT_MAX)) | |
4210 | return ERR_PTR(-E2BIG); | |
4211 | ||
4212 | if (overflows_type(size, obj->base.size)) | |
4213 | return ERR_PTR(-E2BIG); | |
4214 | ||
42dcedd4 | 4215 | obj = i915_gem_object_alloc(dev); |
c397b908 | 4216 | if (obj == NULL) |
fe3db79b | 4217 | return ERR_PTR(-ENOMEM); |
673a394b | 4218 | |
fe3db79b CW |
4219 | ret = drm_gem_object_init(dev, &obj->base, size); |
4220 | if (ret) | |
4221 | goto fail; | |
673a394b | 4222 | |
bed1ea95 | 4223 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
a26e5239 | 4224 | if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) { |
bed1ea95 CW |
4225 | /* 965gm cannot relocate objects above 4GiB. */ |
4226 | mask &= ~__GFP_HIGHMEM; | |
4227 | mask |= __GFP_DMA32; | |
4228 | } | |
4229 | ||
93c76a3d | 4230 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4231 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4232 | |
37e680a1 | 4233 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4234 | |
c397b908 DV |
4235 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4236 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4237 | |
3d29b842 ED |
4238 | if (HAS_LLC(dev)) { |
4239 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4240 | * cache) for about a 10% performance improvement |
4241 | * compared to uncached. Graphics requests other than | |
4242 | * display scanout are coherent with the CPU in | |
4243 | * accessing this cache. This means in this mode we | |
4244 | * don't need to clflush on the CPU side, and on the | |
4245 | * GPU side we only need to flush internal caches to | |
4246 | * get data visible to the CPU. | |
4247 | * | |
4248 | * However, we maintain the display planes as UC, and so | |
4249 | * need to rebind when first used as such. | |
4250 | */ | |
4251 | obj->cache_level = I915_CACHE_LLC; | |
4252 | } else | |
4253 | obj->cache_level = I915_CACHE_NONE; | |
4254 | ||
d861e338 DV |
4255 | trace_i915_gem_object_create(obj); |
4256 | ||
05394f39 | 4257 | return obj; |
fe3db79b CW |
4258 | |
4259 | fail: | |
4260 | i915_gem_object_free(obj); | |
fe3db79b | 4261 | return ERR_PTR(ret); |
c397b908 DV |
4262 | } |
4263 | ||
340fbd8c CW |
4264 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4265 | { | |
4266 | /* If we are the last user of the backing storage (be it shmemfs | |
4267 | * pages or stolen etc), we know that the pages are going to be | |
4268 | * immediately released. In this case, we can then skip copying | |
4269 | * back the contents from the GPU. | |
4270 | */ | |
4271 | ||
a4f5ea64 | 4272 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4273 | return false; |
4274 | ||
4275 | if (obj->base.filp == NULL) | |
4276 | return true; | |
4277 | ||
4278 | /* At first glance, this looks racy, but then again so would be | |
4279 | * userspace racing mmap against close. However, the first external | |
4280 | * reference to the filp can only be obtained through the | |
4281 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4282 | * acquiring such a reference whilst we are in the middle of | |
4283 | * freeing the object. | |
4284 | */ | |
4285 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4286 | } | |
4287 | ||
fbbd37b3 CW |
4288 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4289 | struct llist_node *freed) | |
673a394b | 4290 | { |
fbbd37b3 | 4291 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4292 | |
fbbd37b3 CW |
4293 | mutex_lock(&i915->drm.struct_mutex); |
4294 | intel_runtime_pm_get(i915); | |
4295 | llist_for_each_entry(obj, freed, freed) { | |
4296 | struct i915_vma *vma, *vn; | |
4297 | ||
4298 | trace_i915_gem_object_destroy(obj); | |
4299 | ||
4300 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4301 | list_for_each_entry_safe(vma, vn, | |
4302 | &obj->vma_list, obj_link) { | |
4303 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); | |
4304 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
4305 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4306 | i915_vma_close(vma); | |
4307 | } | |
db6c2b41 CW |
4308 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4309 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4310 | |
56cea323 | 4311 | list_del(&obj->global_link); |
fbbd37b3 CW |
4312 | } |
4313 | intel_runtime_pm_put(i915); | |
4314 | mutex_unlock(&i915->drm.struct_mutex); | |
4315 | ||
4316 | llist_for_each_entry_safe(obj, on, freed, freed) { | |
4317 | GEM_BUG_ON(obj->bind_count); | |
4318 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4319 | ||
4320 | if (obj->ops->release) | |
4321 | obj->ops->release(obj); | |
f65c9168 | 4322 | |
fbbd37b3 CW |
4323 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4324 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4325 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4326 | GEM_BUG_ON(obj->mm.pages); |
4327 | ||
4328 | if (obj->base.import_attach) | |
4329 | drm_prime_gem_destroy(&obj->base, NULL); | |
4330 | ||
d07f0e59 | 4331 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4332 | drm_gem_object_release(&obj->base); |
4333 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4334 | ||
4335 | kfree(obj->bit_17); | |
4336 | i915_gem_object_free(obj); | |
4337 | } | |
4338 | } | |
4339 | ||
4340 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4341 | { | |
4342 | struct llist_node *freed; | |
4343 | ||
4344 | freed = llist_del_all(&i915->mm.free_list); | |
4345 | if (unlikely(freed)) | |
4346 | __i915_gem_free_objects(i915, freed); | |
4347 | } | |
4348 | ||
4349 | static void __i915_gem_free_work(struct work_struct *work) | |
4350 | { | |
4351 | struct drm_i915_private *i915 = | |
4352 | container_of(work, struct drm_i915_private, mm.free_work); | |
4353 | struct llist_node *freed; | |
26e12f89 | 4354 | |
b1f788c6 CW |
4355 | /* All file-owned VMA should have been released by this point through |
4356 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4357 | * However, the object may also be bound into the global GTT (e.g. | |
4358 | * older GPUs without per-process support, or for direct access through | |
4359 | * the GTT either for the user or for scanout). Those VMA still need to | |
4360 | * unbound now. | |
4361 | */ | |
1488fc08 | 4362 | |
fbbd37b3 CW |
4363 | while ((freed = llist_del_all(&i915->mm.free_list))) |
4364 | __i915_gem_free_objects(i915, freed); | |
4365 | } | |
a071fa00 | 4366 | |
fbbd37b3 CW |
4367 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4368 | { | |
4369 | struct drm_i915_gem_object *obj = | |
4370 | container_of(head, typeof(*obj), rcu); | |
4371 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4372 | ||
4373 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4374 | * as we need to block whilst unbinding, and the call_rcu | |
4375 | * task may be called from softirq context. So we take a | |
4376 | * detour through a worker. | |
4377 | */ | |
4378 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4379 | schedule_work(&i915->mm.free_work); | |
4380 | } | |
656bfa3a | 4381 | |
fbbd37b3 CW |
4382 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4383 | { | |
4384 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4385 | |
bc0629a7 CW |
4386 | if (obj->mm.quirked) |
4387 | __i915_gem_object_unpin_pages(obj); | |
4388 | ||
340fbd8c | 4389 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4390 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4391 | |
fbbd37b3 CW |
4392 | /* Before we free the object, make sure any pure RCU-only |
4393 | * read-side critical sections are complete, e.g. | |
4394 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4395 | * lookup see i915_gem_object_lookup_rcu(). | |
4396 | */ | |
4397 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4398 | } |
4399 | ||
f8a7fde4 CW |
4400 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4401 | { | |
4402 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4403 | ||
4404 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4405 | if (i915_gem_object_is_active(obj)) | |
4406 | i915_gem_object_set_active_reference(obj); | |
4407 | else | |
4408 | i915_gem_object_put(obj); | |
4409 | } | |
4410 | ||
3033acab CW |
4411 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4412 | { | |
4413 | struct intel_engine_cs *engine; | |
4414 | enum intel_engine_id id; | |
4415 | ||
4416 | for_each_engine(engine, dev_priv, id) | |
4417 | GEM_BUG_ON(engine->last_context != dev_priv->kernel_context); | |
4418 | } | |
4419 | ||
dcff85c8 | 4420 | int i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4421 | { |
fac5e23e | 4422 | struct drm_i915_private *dev_priv = to_i915(dev); |
dcff85c8 | 4423 | int ret; |
28dfe52a | 4424 | |
54b4f68f CW |
4425 | intel_suspend_gt_powersave(dev_priv); |
4426 | ||
45c5f202 | 4427 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4428 | |
4429 | /* We have to flush all the executing contexts to main memory so | |
4430 | * that they can saved in the hibernation image. To ensure the last | |
4431 | * context image is coherent, we have to switch away from it. That | |
4432 | * leaves the dev_priv->kernel_context still active when | |
4433 | * we actually suspend, and its image in memory may not match the GPU | |
4434 | * state. Fortunately, the kernel_context is disposable and we do | |
4435 | * not rely on its state. | |
4436 | */ | |
4437 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4438 | if (ret) | |
4439 | goto err; | |
4440 | ||
22dd3bb9 CW |
4441 | ret = i915_gem_wait_for_idle(dev_priv, |
4442 | I915_WAIT_INTERRUPTIBLE | | |
4443 | I915_WAIT_LOCKED); | |
f7403347 | 4444 | if (ret) |
45c5f202 | 4445 | goto err; |
f7403347 | 4446 | |
c033666a | 4447 | i915_gem_retire_requests(dev_priv); |
28176ef4 | 4448 | GEM_BUG_ON(dev_priv->gt.active_requests); |
673a394b | 4449 | |
3033acab | 4450 | assert_kernel_context_is_current(dev_priv); |
b2e862d0 | 4451 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4452 | mutex_unlock(&dev->struct_mutex); |
4453 | ||
737b1506 | 4454 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4455 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4456 | flush_delayed_work(&dev_priv->gt.idle_work); | |
fbbd37b3 | 4457 | flush_work(&dev_priv->mm.free_work); |
29105ccc | 4458 | |
bdcf120b CW |
4459 | /* Assert that we sucessfully flushed all the work and |
4460 | * reset the GPU back to its idle, low power state. | |
4461 | */ | |
67d97da3 | 4462 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4463 | |
1c777c5d ID |
4464 | /* |
4465 | * Neither the BIOS, ourselves or any other kernel | |
4466 | * expects the system to be in execlists mode on startup, | |
4467 | * so we need to reset the GPU back to legacy mode. And the only | |
4468 | * known way to disable logical contexts is through a GPU reset. | |
4469 | * | |
4470 | * So in order to leave the system in a known default configuration, | |
4471 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4472 | * clean up the GEM state tracking, flushing off the requests and | |
4473 | * leaving the system in a known idle state. | |
4474 | * | |
4475 | * Note that is of the upmost importance that the GPU is idle and | |
4476 | * all stray writes are flushed *before* we dismantle the backing | |
4477 | * storage for the pinned objects. | |
4478 | * | |
4479 | * However, since we are uncertain that resetting the GPU on older | |
4480 | * machines is a good idea, we don't - just in case it leaves the | |
4481 | * machine in an unusable condition. | |
4482 | */ | |
4483 | if (HAS_HW_CONTEXTS(dev)) { | |
4484 | int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); | |
4485 | WARN_ON(reset && reset != -ENODEV); | |
4486 | } | |
4487 | ||
673a394b | 4488 | return 0; |
45c5f202 CW |
4489 | |
4490 | err: | |
4491 | mutex_unlock(&dev->struct_mutex); | |
4492 | return ret; | |
673a394b EA |
4493 | } |
4494 | ||
5ab57c70 CW |
4495 | void i915_gem_resume(struct drm_device *dev) |
4496 | { | |
4497 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4498 | ||
4499 | mutex_lock(&dev->struct_mutex); | |
4500 | i915_gem_restore_gtt_mappings(dev); | |
4501 | ||
4502 | /* As we didn't flush the kernel context before suspend, we cannot | |
4503 | * guarantee that the context image is complete. So let's just reset | |
4504 | * it and start again. | |
4505 | */ | |
821ed7df | 4506 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4507 | |
4508 | mutex_unlock(&dev->struct_mutex); | |
4509 | } | |
4510 | ||
f691e2f4 DV |
4511 | void i915_gem_init_swizzling(struct drm_device *dev) |
4512 | { | |
fac5e23e | 4513 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4514 | |
11782b02 | 4515 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4516 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4517 | return; | |
4518 | ||
4519 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4520 | DISP_TILE_SURFACE_SWIZZLING); | |
4521 | ||
5db94019 | 4522 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4523 | return; |
4524 | ||
f691e2f4 | 4525 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4526 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4527 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4528 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4529 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4530 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4531 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4532 | else |
4533 | BUG(); | |
f691e2f4 | 4534 | } |
e21af88d | 4535 | |
50a0bc90 | 4536 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4537 | { |
81e7f200 VS |
4538 | I915_WRITE(RING_CTL(base), 0); |
4539 | I915_WRITE(RING_HEAD(base), 0); | |
4540 | I915_WRITE(RING_TAIL(base), 0); | |
4541 | I915_WRITE(RING_START(base), 0); | |
4542 | } | |
4543 | ||
50a0bc90 | 4544 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4545 | { |
50a0bc90 TU |
4546 | if (IS_I830(dev_priv)) { |
4547 | init_unused_ring(dev_priv, PRB1_BASE); | |
4548 | init_unused_ring(dev_priv, SRB0_BASE); | |
4549 | init_unused_ring(dev_priv, SRB1_BASE); | |
4550 | init_unused_ring(dev_priv, SRB2_BASE); | |
4551 | init_unused_ring(dev_priv, SRB3_BASE); | |
4552 | } else if (IS_GEN2(dev_priv)) { | |
4553 | init_unused_ring(dev_priv, SRB0_BASE); | |
4554 | init_unused_ring(dev_priv, SRB1_BASE); | |
4555 | } else if (IS_GEN3(dev_priv)) { | |
4556 | init_unused_ring(dev_priv, PRB1_BASE); | |
4557 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4558 | } |
4559 | } | |
4560 | ||
4fc7c971 BW |
4561 | int |
4562 | i915_gem_init_hw(struct drm_device *dev) | |
4563 | { | |
fac5e23e | 4564 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4565 | struct intel_engine_cs *engine; |
3b3f1650 | 4566 | enum intel_engine_id id; |
d200cda6 | 4567 | int ret; |
4fc7c971 | 4568 | |
de867c20 CW |
4569 | dev_priv->gt.last_init_time = ktime_get(); |
4570 | ||
5e4f5189 CW |
4571 | /* Double layer security blanket, see i915_gem_init() */ |
4572 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4573 | ||
3accaf7e | 4574 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4575 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4576 | |
772c2a51 | 4577 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4578 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4579 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4580 | |
6e266956 | 4581 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4582 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4583 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4584 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4585 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4586 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4587 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4588 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4589 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4590 | } | |
88a2b2a3 BW |
4591 | } |
4592 | ||
4fc7c971 BW |
4593 | i915_gem_init_swizzling(dev); |
4594 | ||
d5abdfda DV |
4595 | /* |
4596 | * At least 830 can leave some of the unused rings | |
4597 | * "active" (ie. head != tail) after resume which | |
4598 | * will prevent c3 entry. Makes sure all unused rings | |
4599 | * are totally idle. | |
4600 | */ | |
50a0bc90 | 4601 | init_unused_rings(dev_priv); |
d5abdfda | 4602 | |
ed54c1a1 | 4603 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4604 | |
4ad2fd88 JH |
4605 | ret = i915_ppgtt_init_hw(dev); |
4606 | if (ret) { | |
4607 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4608 | goto out; | |
4609 | } | |
4610 | ||
4611 | /* Need to do basic initialisation of all rings first: */ | |
3b3f1650 | 4612 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 4613 | ret = engine->init_hw(engine); |
35a57ffb | 4614 | if (ret) |
5e4f5189 | 4615 | goto out; |
35a57ffb | 4616 | } |
99433931 | 4617 | |
0ccdacf6 PA |
4618 | intel_mocs_init_l3cc_table(dev); |
4619 | ||
33a732f4 | 4620 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4621 | ret = intel_guc_setup(dev); |
4622 | if (ret) | |
4623 | goto out; | |
33a732f4 | 4624 | |
5e4f5189 CW |
4625 | out: |
4626 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4627 | return ret; |
8187a2b7 ZN |
4628 | } |
4629 | ||
39df9190 CW |
4630 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4631 | { | |
4632 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4633 | return false; | |
4634 | ||
4635 | /* TODO: make semaphores and Execlists play nicely together */ | |
4636 | if (i915.enable_execlists) | |
4637 | return false; | |
4638 | ||
4639 | if (value >= 0) | |
4640 | return value; | |
4641 | ||
4642 | #ifdef CONFIG_INTEL_IOMMU | |
4643 | /* Enable semaphores on SNB when IO remapping is off */ | |
4644 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4645 | return false; | |
4646 | #endif | |
4647 | ||
4648 | return true; | |
4649 | } | |
4650 | ||
1070a42b CW |
4651 | int i915_gem_init(struct drm_device *dev) |
4652 | { | |
fac5e23e | 4653 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4654 | int ret; |
4655 | ||
1070a42b | 4656 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4657 | |
a83014d3 | 4658 | if (!i915.enable_execlists) { |
821ed7df | 4659 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4660 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4661 | } else { |
821ed7df | 4662 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4663 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4664 | } |
4665 | ||
5e4f5189 CW |
4666 | /* This is just a security blanket to placate dragons. |
4667 | * On some systems, we very sporadically observe that the first TLBs | |
4668 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4669 | * we hold the forcewake during initialisation these problems | |
4670 | * just magically go away. | |
4671 | */ | |
4672 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4673 | ||
72778cb2 | 4674 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4675 | |
4676 | ret = i915_gem_init_ggtt(dev_priv); | |
4677 | if (ret) | |
4678 | goto out_unlock; | |
d62b4892 | 4679 | |
2fa48d8d | 4680 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4681 | if (ret) |
4682 | goto out_unlock; | |
2fa48d8d | 4683 | |
8b3e2d36 | 4684 | ret = intel_engines_init(dev); |
35a57ffb | 4685 | if (ret) |
7bcc3777 | 4686 | goto out_unlock; |
2fa48d8d | 4687 | |
1070a42b | 4688 | ret = i915_gem_init_hw(dev); |
60990320 | 4689 | if (ret == -EIO) { |
7e21d648 | 4690 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4691 | * wedged. But we only want to do this where the GPU is angry, |
4692 | * for all other failure, such as an allocation failure, bail. | |
4693 | */ | |
4694 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4695 | i915_gem_set_wedged(dev_priv); |
60990320 | 4696 | ret = 0; |
1070a42b | 4697 | } |
7bcc3777 JN |
4698 | |
4699 | out_unlock: | |
5e4f5189 | 4700 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4701 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4702 | |
60990320 | 4703 | return ret; |
1070a42b CW |
4704 | } |
4705 | ||
8187a2b7 | 4706 | void |
117897f4 | 4707 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4708 | { |
fac5e23e | 4709 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4710 | struct intel_engine_cs *engine; |
3b3f1650 | 4711 | enum intel_engine_id id; |
8187a2b7 | 4712 | |
3b3f1650 | 4713 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4714 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4715 | } |
4716 | ||
40ae4e16 ID |
4717 | void |
4718 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4719 | { | |
91c8a326 | 4720 | struct drm_device *dev = &dev_priv->drm; |
49ef5294 | 4721 | int i; |
40ae4e16 ID |
4722 | |
4723 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4724 | !IS_CHERRYVIEW(dev_priv)) | |
4725 | dev_priv->num_fence_regs = 32; | |
4726 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4727 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4728 | dev_priv->num_fence_regs = 16; | |
4729 | else | |
4730 | dev_priv->num_fence_regs = 8; | |
4731 | ||
c033666a | 4732 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4733 | dev_priv->num_fence_regs = |
4734 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4735 | ||
4736 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4737 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4738 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4739 | ||
4740 | fence->i915 = dev_priv; | |
4741 | fence->id = i; | |
4742 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4743 | } | |
40ae4e16 ID |
4744 | i915_gem_restore_fences(dev); |
4745 | ||
4746 | i915_gem_detect_bit_6_swizzle(dev); | |
4747 | } | |
4748 | ||
73cb9701 | 4749 | int |
d64aa096 | 4750 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4751 | { |
fac5e23e | 4752 | struct drm_i915_private *dev_priv = to_i915(dev); |
a933568e | 4753 | int err = -ENOMEM; |
42dcedd4 | 4754 | |
a933568e TU |
4755 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4756 | if (!dev_priv->objects) | |
73cb9701 | 4757 | goto err_out; |
73cb9701 | 4758 | |
a933568e TU |
4759 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4760 | if (!dev_priv->vmas) | |
73cb9701 | 4761 | goto err_objects; |
73cb9701 | 4762 | |
a933568e TU |
4763 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4764 | SLAB_HWCACHE_ALIGN | | |
4765 | SLAB_RECLAIM_ACCOUNT | | |
4766 | SLAB_DESTROY_BY_RCU); | |
4767 | if (!dev_priv->requests) | |
73cb9701 | 4768 | goto err_vmas; |
73cb9701 CW |
4769 | |
4770 | mutex_lock(&dev_priv->drm.struct_mutex); | |
4771 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
4772 | err = i915_gem_timeline_init(dev_priv, | |
4773 | &dev_priv->gt.global_timeline, | |
4774 | "[execution]"); | |
4775 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4776 | if (err) | |
4777 | goto err_requests; | |
673a394b | 4778 | |
a33afea5 | 4779 | INIT_LIST_HEAD(&dev_priv->context_list); |
fbbd37b3 CW |
4780 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4781 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4782 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4783 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4784 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4785 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4786 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4787 | i915_gem_retire_work_handler); |
67d97da3 | 4788 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4789 | i915_gem_idle_work_handler); |
1f15b76f | 4790 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4791 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4792 | |
72bfa19c CW |
4793 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4794 | ||
6b95a207 | 4795 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4796 | |
ce453d81 CW |
4797 | dev_priv->mm.interruptible = true; |
4798 | ||
6f633402 JL |
4799 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4800 | ||
b5add959 | 4801 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4802 | |
4803 | return 0; | |
4804 | ||
4805 | err_requests: | |
4806 | kmem_cache_destroy(dev_priv->requests); | |
4807 | err_vmas: | |
4808 | kmem_cache_destroy(dev_priv->vmas); | |
4809 | err_objects: | |
4810 | kmem_cache_destroy(dev_priv->objects); | |
4811 | err_out: | |
4812 | return err; | |
673a394b | 4813 | } |
71acb5eb | 4814 | |
d64aa096 ID |
4815 | void i915_gem_load_cleanup(struct drm_device *dev) |
4816 | { | |
4817 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4818 | ||
7d5d59e5 CW |
4819 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
4820 | ||
d64aa096 ID |
4821 | kmem_cache_destroy(dev_priv->requests); |
4822 | kmem_cache_destroy(dev_priv->vmas); | |
4823 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4824 | |
4825 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4826 | rcu_barrier(); | |
d64aa096 ID |
4827 | } |
4828 | ||
6a800eab CW |
4829 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4830 | { | |
4831 | intel_runtime_pm_get(dev_priv); | |
4832 | ||
4833 | mutex_lock(&dev_priv->drm.struct_mutex); | |
4834 | i915_gem_shrink_all(dev_priv); | |
4835 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4836 | ||
4837 | intel_runtime_pm_put(dev_priv); | |
4838 | ||
4839 | return 0; | |
4840 | } | |
4841 | ||
461fb99c CW |
4842 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4843 | { | |
4844 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4845 | struct list_head *phases[] = { |
4846 | &dev_priv->mm.unbound_list, | |
4847 | &dev_priv->mm.bound_list, | |
4848 | NULL | |
4849 | }, **p; | |
461fb99c CW |
4850 | |
4851 | /* Called just before we write the hibernation image. | |
4852 | * | |
4853 | * We need to update the domain tracking to reflect that the CPU | |
4854 | * will be accessing all the pages to create and restore from the | |
4855 | * hibernation, and so upon restoration those pages will be in the | |
4856 | * CPU domain. | |
4857 | * | |
4858 | * To make sure the hibernation image contains the latest state, | |
4859 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4860 | * |
4861 | * To try and reduce the hibernation image, we manually shrink | |
4862 | * the objects as well. | |
461fb99c CW |
4863 | */ |
4864 | ||
6a800eab CW |
4865 | mutex_lock(&dev_priv->drm.struct_mutex); |
4866 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); | |
461fb99c | 4867 | |
7aab2d53 | 4868 | for (p = phases; *p; p++) { |
56cea323 | 4869 | list_for_each_entry(obj, *p, global_link) { |
7aab2d53 CW |
4870 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4871 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4872 | } | |
461fb99c | 4873 | } |
6a800eab | 4874 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
4875 | |
4876 | return 0; | |
4877 | } | |
4878 | ||
f787a5f5 | 4879 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4880 | { |
f787a5f5 | 4881 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4882 | struct drm_i915_gem_request *request; |
b962442e EA |
4883 | |
4884 | /* Clean up our request list when the client is going away, so that | |
4885 | * later retire_requests won't dereference our soon-to-be-gone | |
4886 | * file_priv. | |
4887 | */ | |
1c25595f | 4888 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4889 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4890 | request->file_priv = NULL; |
1c25595f | 4891 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4892 | |
2e1b8730 | 4893 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4894 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4895 | list_del(&file_priv->rps.link); |
8d3afd7d | 4896 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4897 | } |
b29c19b6 CW |
4898 | } |
4899 | ||
4900 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4901 | { | |
4902 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4903 | int ret; |
b29c19b6 CW |
4904 | |
4905 | DRM_DEBUG_DRIVER("\n"); | |
4906 | ||
4907 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4908 | if (!file_priv) | |
4909 | return -ENOMEM; | |
4910 | ||
4911 | file->driver_priv = file_priv; | |
f19ec8cb | 4912 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4913 | file_priv->file = file; |
2e1b8730 | 4914 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4915 | |
4916 | spin_lock_init(&file_priv->mm.lock); | |
4917 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4918 | |
c80ff16e | 4919 | file_priv->bsd_engine = -1; |
de1add36 | 4920 | |
e422b888 BW |
4921 | ret = i915_gem_context_open(dev, file); |
4922 | if (ret) | |
4923 | kfree(file_priv); | |
b29c19b6 | 4924 | |
e422b888 | 4925 | return ret; |
b29c19b6 CW |
4926 | } |
4927 | ||
b680c37a DV |
4928 | /** |
4929 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4930 | * @old: current GEM buffer for the frontbuffer slots |
4931 | * @new: new GEM buffer for the frontbuffer slots | |
4932 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4933 | * |
4934 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4935 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4936 | */ | |
a071fa00 DV |
4937 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4938 | struct drm_i915_gem_object *new, | |
4939 | unsigned frontbuffer_bits) | |
4940 | { | |
faf5bf0a CW |
4941 | /* Control of individual bits within the mask are guarded by |
4942 | * the owning plane->mutex, i.e. we can never see concurrent | |
4943 | * manipulation of individual bits. But since the bitfield as a whole | |
4944 | * is updated using RMW, we need to use atomics in order to update | |
4945 | * the bits. | |
4946 | */ | |
4947 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4948 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4949 | ||
a071fa00 | 4950 | if (old) { |
faf5bf0a CW |
4951 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4952 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4953 | } |
4954 | ||
4955 | if (new) { | |
faf5bf0a CW |
4956 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4957 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4958 | } |
4959 | } | |
4960 | ||
ea70299d DG |
4961 | /* Allocate a new GEM object and fill it with the supplied data */ |
4962 | struct drm_i915_gem_object * | |
4963 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4964 | const void *data, size_t size) | |
4965 | { | |
4966 | struct drm_i915_gem_object *obj; | |
4967 | struct sg_table *sg; | |
4968 | size_t bytes; | |
4969 | int ret; | |
4970 | ||
d37cd8a8 | 4971 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4972 | if (IS_ERR(obj)) |
ea70299d DG |
4973 | return obj; |
4974 | ||
4975 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4976 | if (ret) | |
4977 | goto fail; | |
4978 | ||
a4f5ea64 | 4979 | ret = i915_gem_object_pin_pages(obj); |
ea70299d DG |
4980 | if (ret) |
4981 | goto fail; | |
4982 | ||
a4f5ea64 | 4983 | sg = obj->mm.pages; |
ea70299d | 4984 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
a4f5ea64 | 4985 | obj->mm.dirty = true; /* Backing store is now out of date */ |
ea70299d DG |
4986 | i915_gem_object_unpin_pages(obj); |
4987 | ||
4988 | if (WARN_ON(bytes != size)) { | |
4989 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4990 | ret = -EFAULT; | |
4991 | goto fail; | |
4992 | } | |
4993 | ||
4994 | return obj; | |
4995 | ||
4996 | fail: | |
f8c417cd | 4997 | i915_gem_object_put(obj); |
ea70299d DG |
4998 | return ERR_PTR(ret); |
4999 | } | |
96d77634 CW |
5000 | |
5001 | struct scatterlist * | |
5002 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
5003 | unsigned int n, | |
5004 | unsigned int *offset) | |
5005 | { | |
a4f5ea64 | 5006 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
5007 | struct scatterlist *sg; |
5008 | unsigned int idx, count; | |
5009 | ||
5010 | might_sleep(); | |
5011 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 5012 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
5013 | |
5014 | /* As we iterate forward through the sg, we record each entry in a | |
5015 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
5016 | * this index previously, we will have an entry for it. | |
5017 | * | |
5018 | * Initial lookup is O(N), but this is amortized to O(1) for | |
5019 | * sequential page access (where each new request is consecutive | |
5020 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
5021 | * i.e. O(1) with a large constant! | |
5022 | */ | |
5023 | if (n < READ_ONCE(iter->sg_idx)) | |
5024 | goto lookup; | |
5025 | ||
5026 | mutex_lock(&iter->lock); | |
5027 | ||
5028 | /* We prefer to reuse the last sg so that repeated lookup of this | |
5029 | * (or the subsequent) sg are fast - comparing against the last | |
5030 | * sg is faster than going through the radixtree. | |
5031 | */ | |
5032 | ||
5033 | sg = iter->sg_pos; | |
5034 | idx = iter->sg_idx; | |
5035 | count = __sg_page_count(sg); | |
5036 | ||
5037 | while (idx + count <= n) { | |
5038 | unsigned long exception, i; | |
5039 | int ret; | |
5040 | ||
5041 | /* If we cannot allocate and insert this entry, or the | |
5042 | * individual pages from this range, cancel updating the | |
5043 | * sg_idx so that on this lookup we are forced to linearly | |
5044 | * scan onwards, but on future lookups we will try the | |
5045 | * insertion again (in which case we need to be careful of | |
5046 | * the error return reporting that we have already inserted | |
5047 | * this index). | |
5048 | */ | |
5049 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
5050 | if (ret && ret != -EEXIST) | |
5051 | goto scan; | |
5052 | ||
5053 | exception = | |
5054 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
5055 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5056 | for (i = 1; i < count; i++) { | |
5057 | ret = radix_tree_insert(&iter->radix, idx + i, | |
5058 | (void *)exception); | |
5059 | if (ret && ret != -EEXIST) | |
5060 | goto scan; | |
5061 | } | |
5062 | ||
5063 | idx += count; | |
5064 | sg = ____sg_next(sg); | |
5065 | count = __sg_page_count(sg); | |
5066 | } | |
5067 | ||
5068 | scan: | |
5069 | iter->sg_pos = sg; | |
5070 | iter->sg_idx = idx; | |
5071 | ||
5072 | mutex_unlock(&iter->lock); | |
5073 | ||
5074 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
5075 | goto lookup; | |
5076 | ||
5077 | /* In case we failed to insert the entry into the radixtree, we need | |
5078 | * to look beyond the current sg. | |
5079 | */ | |
5080 | while (idx + count <= n) { | |
5081 | idx += count; | |
5082 | sg = ____sg_next(sg); | |
5083 | count = __sg_page_count(sg); | |
5084 | } | |
5085 | ||
5086 | *offset = n - idx; | |
5087 | return sg; | |
5088 | ||
5089 | lookup: | |
5090 | rcu_read_lock(); | |
5091 | ||
5092 | sg = radix_tree_lookup(&iter->radix, n); | |
5093 | GEM_BUG_ON(!sg); | |
5094 | ||
5095 | /* If this index is in the middle of multi-page sg entry, | |
5096 | * the radixtree will contain an exceptional entry that points | |
5097 | * to the start of that range. We will return the pointer to | |
5098 | * the base page and the offset of this page within the | |
5099 | * sg entry's range. | |
5100 | */ | |
5101 | *offset = 0; | |
5102 | if (unlikely(radix_tree_exception(sg))) { | |
5103 | unsigned long base = | |
5104 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5105 | ||
5106 | sg = radix_tree_lookup(&iter->radix, base); | |
5107 | GEM_BUG_ON(!sg); | |
5108 | ||
5109 | *offset = n - base; | |
5110 | } | |
5111 | ||
5112 | rcu_read_unlock(); | |
5113 | ||
5114 | return sg; | |
5115 | } | |
5116 | ||
5117 | struct page * | |
5118 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
5119 | { | |
5120 | struct scatterlist *sg; | |
5121 | unsigned int offset; | |
5122 | ||
5123 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
5124 | ||
5125 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5126 | return nth_page(sg_page(sg), offset); | |
5127 | } | |
5128 | ||
5129 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
5130 | struct page * | |
5131 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
5132 | unsigned int n) | |
5133 | { | |
5134 | struct page *page; | |
5135 | ||
5136 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 5137 | if (!obj->mm.dirty) |
96d77634 CW |
5138 | set_page_dirty(page); |
5139 | ||
5140 | return page; | |
5141 | } | |
5142 | ||
5143 | dma_addr_t | |
5144 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
5145 | unsigned long n) | |
5146 | { | |
5147 | struct scatterlist *sg; | |
5148 | unsigned int offset; | |
5149 | ||
5150 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5151 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
5152 | } |