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1da177e4 LT |
1 | /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 | 29 | |
5669fcac | 30 | #include <linux/device.h> |
1da177e4 LT |
31 | #include "drmP.h" |
32 | #include "drm.h" | |
33 | #include "i915_drm.h" | |
34 | #include "i915_drv.h" | |
f49f0586 | 35 | #include "intel_drv.h" |
1da177e4 | 36 | |
79e53945 | 37 | #include <linux/console.h> |
e0cd3608 | 38 | #include <linux/module.h> |
354ff967 | 39 | #include "drm_crtc_helper.h" |
79e53945 | 40 | |
a35d9d3c | 41 | static int i915_modeset __read_mostly = -1; |
79e53945 | 42 | module_param_named(modeset, i915_modeset, int, 0400); |
6e96e775 BW |
43 | MODULE_PARM_DESC(modeset, |
44 | "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, " | |
45 | "1=on, -1=force vga console preference [default])"); | |
79e53945 | 46 | |
a35d9d3c | 47 | unsigned int i915_fbpercrtc __always_unused = 0; |
79e53945 | 48 | module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400); |
1da177e4 | 49 | |
a35d9d3c | 50 | int i915_panel_ignore_lid __read_mostly = 0; |
fca87409 | 51 | module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600); |
6e96e775 BW |
52 | MODULE_PARM_DESC(panel_ignore_lid, |
53 | "Override lid status (0=autodetect [default], 1=lid open, " | |
54 | "-1=lid closed)"); | |
fca87409 | 55 | |
a35d9d3c | 56 | unsigned int i915_powersave __read_mostly = 1; |
0aa99277 | 57 | module_param_named(powersave, i915_powersave, int, 0600); |
6e96e775 BW |
58 | MODULE_PARM_DESC(powersave, |
59 | "Enable powersavings, fbc, downclocking, etc. (default: true)"); | |
652c393a | 60 | |
f45b5557 | 61 | int i915_semaphores __read_mostly = -1; |
a1656b90 | 62 | module_param_named(semaphores, i915_semaphores, int, 0600); |
6e96e775 | 63 | MODULE_PARM_DESC(semaphores, |
f45b5557 | 64 | "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))"); |
a1656b90 | 65 | |
c0f372b3 | 66 | int i915_enable_rc6 __read_mostly = -1; |
ac668088 | 67 | module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600); |
6e96e775 | 68 | MODULE_PARM_DESC(i915_enable_rc6, |
83b7f9ac ED |
69 | "Enable power-saving render C-state 6. " |
70 | "Different stages can be selected via bitmask values " | |
71 | "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). " | |
72 | "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. " | |
73 | "default: -1 (use per-chip default)"); | |
ac668088 | 74 | |
4415e63b | 75 | int i915_enable_fbc __read_mostly = -1; |
c1a9f047 | 76 | module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600); |
6e96e775 BW |
77 | MODULE_PARM_DESC(i915_enable_fbc, |
78 | "Enable frame buffer compression for power savings " | |
cd0de039 | 79 | "(default: -1 (use per-chip default))"); |
c1a9f047 | 80 | |
a35d9d3c | 81 | unsigned int i915_lvds_downclock __read_mostly = 0; |
33814341 | 82 | module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400); |
6e96e775 BW |
83 | MODULE_PARM_DESC(lvds_downclock, |
84 | "Use panel (LVDS/eDP) downclocking for power savings " | |
85 | "(default: false)"); | |
33814341 | 86 | |
4415e63b | 87 | int i915_panel_use_ssc __read_mostly = -1; |
a7615030 | 88 | module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600); |
6e96e775 BW |
89 | MODULE_PARM_DESC(lvds_use_ssc, |
90 | "Use Spread Spectrum Clock with panels [LVDS/eDP] " | |
72bbe58c | 91 | "(default: auto from VBT)"); |
a7615030 | 92 | |
a35d9d3c | 93 | int i915_vbt_sdvo_panel_type __read_mostly = -1; |
5a1e5b6c | 94 | module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600); |
6e96e775 BW |
95 | MODULE_PARM_DESC(vbt_sdvo_panel_type, |
96 | "Override selection of SDVO panel mode in the VBT " | |
97 | "(default: auto)"); | |
5a1e5b6c | 98 | |
a35d9d3c | 99 | static bool i915_try_reset __read_mostly = true; |
d78cb50b | 100 | module_param_named(reset, i915_try_reset, bool, 0600); |
6e96e775 | 101 | MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)"); |
d78cb50b | 102 | |
a35d9d3c | 103 | bool i915_enable_hangcheck __read_mostly = true; |
3e0dc6b0 | 104 | module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644); |
6e96e775 BW |
105 | MODULE_PARM_DESC(enable_hangcheck, |
106 | "Periodically check GPU activity for detecting hangs. " | |
107 | "WARNING: Disabling this can cause system wide hangs. " | |
108 | "(default: true)"); | |
3e0dc6b0 | 109 | |
650dc07e DV |
110 | int i915_enable_ppgtt __read_mostly = -1; |
111 | module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); | |
e21af88d DV |
112 | MODULE_PARM_DESC(i915_enable_ppgtt, |
113 | "Enable PPGTT (default: true)"); | |
114 | ||
112b715e | 115 | static struct drm_driver driver; |
1f7a6e37 | 116 | extern int intel_agp_enabled; |
112b715e | 117 | |
cfdf1fa2 | 118 | #define INTEL_VGA_DEVICE(id, info) { \ |
80a2901d | 119 | .class = PCI_BASE_CLASS_DISPLAY << 16, \ |
934f992c | 120 | .class_mask = 0xff0000, \ |
49ae35f2 KH |
121 | .vendor = 0x8086, \ |
122 | .device = id, \ | |
123 | .subvendor = PCI_ANY_ID, \ | |
124 | .subdevice = PCI_ANY_ID, \ | |
cfdf1fa2 KH |
125 | .driver_data = (unsigned long) info } |
126 | ||
9a7e8492 | 127 | static const struct intel_device_info intel_i830_info = { |
a6c45cf0 | 128 | .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, |
31578148 | 129 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
130 | }; |
131 | ||
9a7e8492 | 132 | static const struct intel_device_info intel_845g_info = { |
a6c45cf0 | 133 | .gen = 2, |
31578148 | 134 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
135 | }; |
136 | ||
9a7e8492 | 137 | static const struct intel_device_info intel_i85x_info = { |
a6c45cf0 | 138 | .gen = 2, .is_i85x = 1, .is_mobile = 1, |
5ce8ba7c | 139 | .cursor_needs_physical = 1, |
31578148 | 140 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
141 | }; |
142 | ||
9a7e8492 | 143 | static const struct intel_device_info intel_i865g_info = { |
a6c45cf0 | 144 | .gen = 2, |
31578148 | 145 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 KH |
146 | }; |
147 | ||
9a7e8492 | 148 | static const struct intel_device_info intel_i915g_info = { |
a6c45cf0 | 149 | .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, |
31578148 | 150 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 151 | }; |
9a7e8492 | 152 | static const struct intel_device_info intel_i915gm_info = { |
a6c45cf0 | 153 | .gen = 3, .is_mobile = 1, |
b295d1b6 | 154 | .cursor_needs_physical = 1, |
31578148 | 155 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 156 | .supports_tv = 1, |
cfdf1fa2 | 157 | }; |
9a7e8492 | 158 | static const struct intel_device_info intel_i945g_info = { |
a6c45cf0 | 159 | .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 160 | .has_overlay = 1, .overlay_needs_physical = 1, |
cfdf1fa2 | 161 | }; |
9a7e8492 | 162 | static const struct intel_device_info intel_i945gm_info = { |
a6c45cf0 | 163 | .gen = 3, .is_i945gm = 1, .is_mobile = 1, |
b295d1b6 | 164 | .has_hotplug = 1, .cursor_needs_physical = 1, |
31578148 | 165 | .has_overlay = 1, .overlay_needs_physical = 1, |
a6c45cf0 | 166 | .supports_tv = 1, |
cfdf1fa2 KH |
167 | }; |
168 | ||
9a7e8492 | 169 | static const struct intel_device_info intel_i965g_info = { |
a6c45cf0 | 170 | .gen = 4, .is_broadwater = 1, |
c96c3a8c | 171 | .has_hotplug = 1, |
31578148 | 172 | .has_overlay = 1, |
cfdf1fa2 KH |
173 | }; |
174 | ||
9a7e8492 | 175 | static const struct intel_device_info intel_i965gm_info = { |
a6c45cf0 | 176 | .gen = 4, .is_crestline = 1, |
e3c4e5dd | 177 | .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1, |
31578148 | 178 | .has_overlay = 1, |
a6c45cf0 | 179 | .supports_tv = 1, |
cfdf1fa2 KH |
180 | }; |
181 | ||
9a7e8492 | 182 | static const struct intel_device_info intel_g33_info = { |
a6c45cf0 | 183 | .gen = 3, .is_g33 = 1, |
c96c3a8c | 184 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 185 | .has_overlay = 1, |
cfdf1fa2 KH |
186 | }; |
187 | ||
9a7e8492 | 188 | static const struct intel_device_info intel_g45_info = { |
a6c45cf0 | 189 | .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, |
c96c3a8c | 190 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
92f49d9c | 191 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
192 | }; |
193 | ||
9a7e8492 | 194 | static const struct intel_device_info intel_gm45_info = { |
a6c45cf0 | 195 | .gen = 4, .is_g4x = 1, |
e3c4e5dd | 196 | .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1, |
c96c3a8c | 197 | .has_pipe_cxsr = 1, .has_hotplug = 1, |
a6c45cf0 | 198 | .supports_tv = 1, |
92f49d9c | 199 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
200 | }; |
201 | ||
9a7e8492 | 202 | static const struct intel_device_info intel_pineview_info = { |
a6c45cf0 | 203 | .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, |
c96c3a8c | 204 | .need_gfx_hws = 1, .has_hotplug = 1, |
31578148 | 205 | .has_overlay = 1, |
cfdf1fa2 KH |
206 | }; |
207 | ||
9a7e8492 | 208 | static const struct intel_device_info intel_ironlake_d_info = { |
f00a3ddf | 209 | .gen = 5, |
5a117db7 | 210 | .need_gfx_hws = 1, .has_hotplug = 1, |
92f49d9c | 211 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
212 | }; |
213 | ||
9a7e8492 | 214 | static const struct intel_device_info intel_ironlake_m_info = { |
f00a3ddf | 215 | .gen = 5, .is_mobile = 1, |
e3c4e5dd | 216 | .need_gfx_hws = 1, .has_hotplug = 1, |
c1a9f047 | 217 | .has_fbc = 1, |
92f49d9c | 218 | .has_bsd_ring = 1, |
cfdf1fa2 KH |
219 | }; |
220 | ||
9a7e8492 | 221 | static const struct intel_device_info intel_sandybridge_d_info = { |
a6c45cf0 | 222 | .gen = 6, |
c96c3a8c | 223 | .need_gfx_hws = 1, .has_hotplug = 1, |
881f47b6 | 224 | .has_bsd_ring = 1, |
549f7365 | 225 | .has_blt_ring = 1, |
3d29b842 | 226 | .has_llc = 1, |
f6e450a6 EA |
227 | }; |
228 | ||
9a7e8492 | 229 | static const struct intel_device_info intel_sandybridge_m_info = { |
a6c45cf0 | 230 | .gen = 6, .is_mobile = 1, |
c96c3a8c | 231 | .need_gfx_hws = 1, .has_hotplug = 1, |
9c04f015 | 232 | .has_fbc = 1, |
881f47b6 | 233 | .has_bsd_ring = 1, |
549f7365 | 234 | .has_blt_ring = 1, |
3d29b842 | 235 | .has_llc = 1, |
a13e4093 EA |
236 | }; |
237 | ||
c76b615c JB |
238 | static const struct intel_device_info intel_ivybridge_d_info = { |
239 | .is_ivybridge = 1, .gen = 7, | |
240 | .need_gfx_hws = 1, .has_hotplug = 1, | |
241 | .has_bsd_ring = 1, | |
242 | .has_blt_ring = 1, | |
3d29b842 | 243 | .has_llc = 1, |
c76b615c JB |
244 | }; |
245 | ||
246 | static const struct intel_device_info intel_ivybridge_m_info = { | |
247 | .is_ivybridge = 1, .gen = 7, .is_mobile = 1, | |
248 | .need_gfx_hws = 1, .has_hotplug = 1, | |
249 | .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */ | |
250 | .has_bsd_ring = 1, | |
251 | .has_blt_ring = 1, | |
3d29b842 | 252 | .has_llc = 1, |
c76b615c JB |
253 | }; |
254 | ||
6103da0d CW |
255 | static const struct pci_device_id pciidlist[] = { /* aka */ |
256 | INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */ | |
257 | INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */ | |
258 | INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */ | |
5ce8ba7c | 259 | INTEL_VGA_DEVICE(0x358e, &intel_i85x_info), |
6103da0d CW |
260 | INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */ |
261 | INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */ | |
262 | INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */ | |
263 | INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */ | |
264 | INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */ | |
265 | INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */ | |
266 | INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */ | |
267 | INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */ | |
268 | INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */ | |
269 | INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */ | |
270 | INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */ | |
271 | INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */ | |
272 | INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */ | |
273 | INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */ | |
274 | INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */ | |
275 | INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */ | |
276 | INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */ | |
277 | INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */ | |
278 | INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */ | |
279 | INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */ | |
280 | INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */ | |
281 | INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */ | |
41a51428 | 282 | INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */ |
cfdf1fa2 KH |
283 | INTEL_VGA_DEVICE(0xa001, &intel_pineview_info), |
284 | INTEL_VGA_DEVICE(0xa011, &intel_pineview_info), | |
285 | INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info), | |
286 | INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info), | |
f6e450a6 | 287 | INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info), |
85540480 ZW |
288 | INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info), |
289 | INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info), | |
a13e4093 | 290 | INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info), |
85540480 | 291 | INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info), |
4fefe435 | 292 | INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info), |
85540480 | 293 | INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info), |
c76b615c JB |
294 | INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */ |
295 | INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */ | |
296 | INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */ | |
297 | INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */ | |
298 | INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */ | |
cc22a938 | 299 | INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */ |
49ae35f2 | 300 | {0, 0, 0} |
1da177e4 LT |
301 | }; |
302 | ||
79e53945 JB |
303 | #if defined(CONFIG_DRM_I915_KMS) |
304 | MODULE_DEVICE_TABLE(pci, pciidlist); | |
305 | #endif | |
306 | ||
3bad0781 | 307 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
90711d50 | 308 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
3bad0781 | 309 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 |
c792513b | 310 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 |
3bad0781 | 311 | |
0206e353 | 312 | void intel_detect_pch(struct drm_device *dev) |
3bad0781 ZW |
313 | { |
314 | struct drm_i915_private *dev_priv = dev->dev_private; | |
315 | struct pci_dev *pch; | |
316 | ||
317 | /* | |
318 | * The reason to probe ISA bridge instead of Dev31:Fun0 is to | |
319 | * make graphics device passthrough work easy for VMM, that only | |
320 | * need to expose ISA bridge to let driver know the real hardware | |
321 | * underneath. This is a requirement from virtualization team. | |
322 | */ | |
323 | pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL); | |
324 | if (pch) { | |
325 | if (pch->vendor == PCI_VENDOR_ID_INTEL) { | |
326 | int id; | |
327 | id = pch->device & INTEL_PCH_DEVICE_ID_MASK; | |
328 | ||
90711d50 JB |
329 | if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) { |
330 | dev_priv->pch_type = PCH_IBX; | |
331 | DRM_DEBUG_KMS("Found Ibex Peak PCH\n"); | |
332 | } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) { | |
3bad0781 ZW |
333 | dev_priv->pch_type = PCH_CPT; |
334 | DRM_DEBUG_KMS("Found CougarPoint PCH\n"); | |
c792513b JB |
335 | } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) { |
336 | /* PantherPoint is CPT compatible */ | |
337 | dev_priv->pch_type = PCH_CPT; | |
338 | DRM_DEBUG_KMS("Found PatherPoint PCH\n"); | |
3bad0781 ZW |
339 | } |
340 | } | |
341 | pci_dev_put(pch); | |
342 | } | |
343 | } | |
344 | ||
8d715f00 | 345 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) |
eb43f4af CW |
346 | { |
347 | int count; | |
348 | ||
349 | count = 0; | |
350 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1)) | |
351 | udelay(10); | |
352 | ||
353 | I915_WRITE_NOTRACE(FORCEWAKE, 1); | |
354 | POSTING_READ(FORCEWAKE); | |
355 | ||
356 | count = 0; | |
357 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0) | |
358 | udelay(10); | |
359 | } | |
360 | ||
8d715f00 KP |
361 | void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) |
362 | { | |
363 | int count; | |
364 | ||
365 | count = 0; | |
366 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1)) | |
367 | udelay(10); | |
368 | ||
369 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1); | |
370 | POSTING_READ(FORCEWAKE_MT); | |
371 | ||
372 | count = 0; | |
373 | while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0) | |
374 | udelay(10); | |
375 | } | |
376 | ||
fcca7926 BW |
377 | /* |
378 | * Generally this is called implicitly by the register read function. However, | |
379 | * if some sequence requires the GT to not power down then this function should | |
380 | * be called at the beginning of the sequence followed by a call to | |
381 | * gen6_gt_force_wake_put() at the end of the sequence. | |
382 | */ | |
383 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) | |
384 | { | |
9f1f46a4 | 385 | unsigned long irqflags; |
fcca7926 | 386 | |
9f1f46a4 DV |
387 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
388 | if (dev_priv->forcewake_count++ == 0) | |
8d715f00 | 389 | dev_priv->display.force_wake_get(dev_priv); |
9f1f46a4 | 390 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
391 | } |
392 | ||
ee64cbdb BW |
393 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
394 | { | |
395 | u32 gtfifodbg; | |
396 | gtfifodbg = I915_READ_NOTRACE(GTFIFODBG); | |
397 | if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, | |
398 | "MMIO read or write has been dropped %x\n", gtfifodbg)) | |
399 | I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK); | |
400 | } | |
401 | ||
8d715f00 | 402 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) |
eb43f4af CW |
403 | { |
404 | I915_WRITE_NOTRACE(FORCEWAKE, 0); | |
ee64cbdb BW |
405 | /* The below doubles as a POSTING_READ */ |
406 | gen6_gt_check_fifodbg(dev_priv); | |
eb43f4af CW |
407 | } |
408 | ||
8d715f00 KP |
409 | void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) |
410 | { | |
411 | I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0); | |
ee64cbdb BW |
412 | /* The below doubles as a POSTING_READ */ |
413 | gen6_gt_check_fifodbg(dev_priv); | |
8d715f00 KP |
414 | } |
415 | ||
fcca7926 BW |
416 | /* |
417 | * see gen6_gt_force_wake_get() | |
418 | */ | |
419 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) | |
420 | { | |
9f1f46a4 | 421 | unsigned long irqflags; |
fcca7926 | 422 | |
9f1f46a4 DV |
423 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
424 | if (--dev_priv->forcewake_count == 0) | |
8d715f00 | 425 | dev_priv->display.force_wake_put(dev_priv); |
9f1f46a4 | 426 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
fcca7926 BW |
427 | } |
428 | ||
67a3744f | 429 | int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
91355834 | 430 | { |
67a3744f BW |
431 | int ret = 0; |
432 | ||
0206e353 | 433 | if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
95736720 CW |
434 | int loop = 500; |
435 | u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
436 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { | |
437 | udelay(10); | |
438 | fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
439 | } | |
67a3744f BW |
440 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
441 | ++ret; | |
95736720 | 442 | dev_priv->gt_fifo_count = fifo; |
91355834 | 443 | } |
95736720 | 444 | dev_priv->gt_fifo_count--; |
67a3744f BW |
445 | |
446 | return ret; | |
91355834 CW |
447 | } |
448 | ||
84b79f8d | 449 | static int i915_drm_freeze(struct drm_device *dev) |
ba8bbcf6 | 450 | { |
61caf87c RW |
451 | struct drm_i915_private *dev_priv = dev->dev_private; |
452 | ||
5bcf719b DA |
453 | drm_kms_helper_poll_disable(dev); |
454 | ||
ba8bbcf6 | 455 | pci_save_state(dev->pdev); |
ba8bbcf6 | 456 | |
5669fcac | 457 | /* If KMS is active, we do the leavevt stuff here */ |
226485e9 | 458 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
84b79f8d RW |
459 | int error = i915_gem_idle(dev); |
460 | if (error) { | |
226485e9 | 461 | dev_err(&dev->pdev->dev, |
84b79f8d RW |
462 | "GEM idle failed, resume might fail\n"); |
463 | return error; | |
464 | } | |
226485e9 | 465 | drm_irq_uninstall(dev); |
5669fcac JB |
466 | } |
467 | ||
9e06dd39 JB |
468 | i915_save_state(dev); |
469 | ||
44834a67 | 470 | intel_opregion_fini(dev); |
8ee1c3db | 471 | |
84b79f8d RW |
472 | /* Modeset on resume, not lid events */ |
473 | dev_priv->modeset_on_lid = 0; | |
61caf87c | 474 | |
3fa016a0 DA |
475 | console_lock(); |
476 | intel_fbdev_set_suspend(dev, 1); | |
477 | console_unlock(); | |
478 | ||
61caf87c | 479 | return 0; |
84b79f8d RW |
480 | } |
481 | ||
6a9ee8af | 482 | int i915_suspend(struct drm_device *dev, pm_message_t state) |
84b79f8d RW |
483 | { |
484 | int error; | |
485 | ||
486 | if (!dev || !dev->dev_private) { | |
487 | DRM_ERROR("dev: %p\n", dev); | |
488 | DRM_ERROR("DRM not initialized, aborting suspend.\n"); | |
489 | return -ENODEV; | |
490 | } | |
491 | ||
492 | if (state.event == PM_EVENT_PRETHAW) | |
493 | return 0; | |
494 | ||
5bcf719b DA |
495 | |
496 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) | |
497 | return 0; | |
6eecba33 | 498 | |
84b79f8d RW |
499 | error = i915_drm_freeze(dev); |
500 | if (error) | |
501 | return error; | |
502 | ||
b932ccb5 DA |
503 | if (state.event == PM_EVENT_SUSPEND) { |
504 | /* Shut down the device */ | |
505 | pci_disable_device(dev->pdev); | |
506 | pci_set_power_state(dev->pdev, PCI_D3hot); | |
507 | } | |
ba8bbcf6 JB |
508 | |
509 | return 0; | |
510 | } | |
511 | ||
84b79f8d | 512 | static int i915_drm_thaw(struct drm_device *dev) |
ba8bbcf6 | 513 | { |
5669fcac | 514 | struct drm_i915_private *dev_priv = dev->dev_private; |
84b79f8d | 515 | int error = 0; |
8ee1c3db | 516 | |
d1c3b177 CW |
517 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
518 | mutex_lock(&dev->struct_mutex); | |
519 | i915_gem_restore_gtt_mappings(dev); | |
520 | mutex_unlock(&dev->struct_mutex); | |
521 | } | |
522 | ||
61caf87c | 523 | i915_restore_state(dev); |
44834a67 | 524 | intel_opregion_setup(dev); |
61caf87c | 525 | |
5669fcac JB |
526 | /* KMS EnterVT equivalent */ |
527 | if (drm_core_check_feature(dev, DRIVER_MODESET)) { | |
528 | mutex_lock(&dev->struct_mutex); | |
529 | dev_priv->mm.suspended = 0; | |
530 | ||
f691e2f4 | 531 | error = i915_gem_init_hw(dev); |
5669fcac | 532 | mutex_unlock(&dev->struct_mutex); |
226485e9 | 533 | |
9fb526db KP |
534 | if (HAS_PCH_SPLIT(dev)) |
535 | ironlake_init_pch_refclk(dev); | |
536 | ||
500f7147 | 537 | drm_mode_config_reset(dev); |
226485e9 | 538 | drm_irq_install(dev); |
84b79f8d | 539 | |
354ff967 | 540 | /* Resume the modeset for every activated CRTC */ |
927a2f11 | 541 | mutex_lock(&dev->mode_config.mutex); |
354ff967 | 542 | drm_helper_resume_force_mode(dev); |
927a2f11 | 543 | mutex_unlock(&dev->mode_config.mutex); |
5669fcac | 544 | |
ac668088 | 545 | if (IS_IRONLAKE_M(dev)) |
d5bb081b JB |
546 | ironlake_enable_rc6(dev); |
547 | } | |
1daed3fb | 548 | |
44834a67 CW |
549 | intel_opregion_init(dev); |
550 | ||
c9354c85 | 551 | dev_priv->modeset_on_lid = 0; |
06891e27 | 552 | |
3fa016a0 DA |
553 | console_lock(); |
554 | intel_fbdev_set_suspend(dev, 0); | |
555 | console_unlock(); | |
84b79f8d RW |
556 | return error; |
557 | } | |
558 | ||
6a9ee8af | 559 | int i915_resume(struct drm_device *dev) |
84b79f8d | 560 | { |
6eecba33 CW |
561 | int ret; |
562 | ||
5bcf719b DA |
563 | if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
564 | return 0; | |
565 | ||
84b79f8d RW |
566 | if (pci_enable_device(dev->pdev)) |
567 | return -EIO; | |
568 | ||
569 | pci_set_master(dev->pdev); | |
570 | ||
6eecba33 CW |
571 | ret = i915_drm_thaw(dev); |
572 | if (ret) | |
573 | return ret; | |
574 | ||
575 | drm_kms_helper_poll_enable(dev); | |
576 | return 0; | |
ba8bbcf6 JB |
577 | } |
578 | ||
dc96e9b8 CW |
579 | static int i8xx_do_reset(struct drm_device *dev, u8 flags) |
580 | { | |
581 | struct drm_i915_private *dev_priv = dev->dev_private; | |
582 | ||
583 | if (IS_I85X(dev)) | |
584 | return -ENODEV; | |
585 | ||
586 | I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830); | |
587 | POSTING_READ(D_STATE); | |
588 | ||
589 | if (IS_I830(dev) || IS_845G(dev)) { | |
590 | I915_WRITE(DEBUG_RESET_I830, | |
591 | DEBUG_RESET_DISPLAY | | |
592 | DEBUG_RESET_RENDER | | |
593 | DEBUG_RESET_FULL); | |
594 | POSTING_READ(DEBUG_RESET_I830); | |
595 | msleep(1); | |
596 | ||
597 | I915_WRITE(DEBUG_RESET_I830, 0); | |
598 | POSTING_READ(DEBUG_RESET_I830); | |
599 | } | |
600 | ||
601 | msleep(1); | |
602 | ||
603 | I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830); | |
604 | POSTING_READ(D_STATE); | |
605 | ||
606 | return 0; | |
607 | } | |
608 | ||
f49f0586 KG |
609 | static int i965_reset_complete(struct drm_device *dev) |
610 | { | |
611 | u8 gdrst; | |
eeccdcac | 612 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
f49f0586 KG |
613 | return gdrst & 0x1; |
614 | } | |
615 | ||
0573ed4a KG |
616 | static int i965_do_reset(struct drm_device *dev, u8 flags) |
617 | { | |
618 | u8 gdrst; | |
619 | ||
ae681d96 CW |
620 | /* |
621 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as | |
622 | * well as the reset bit (GR/bit 0). Setting the GR bit | |
623 | * triggers the reset; when done, the hardware will clear it. | |
624 | */ | |
0573ed4a KG |
625 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
626 | pci_write_config_byte(dev->pdev, I965_GDRST, gdrst | flags | 0x1); | |
627 | ||
628 | return wait_for(i965_reset_complete(dev), 500); | |
629 | } | |
630 | ||
631 | static int ironlake_do_reset(struct drm_device *dev, u8 flags) | |
632 | { | |
633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
634 | u32 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); | |
635 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1); | |
636 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); | |
ba8bbcf6 JB |
637 | } |
638 | ||
cff458c2 EA |
639 | static int gen6_do_reset(struct drm_device *dev, u8 flags) |
640 | { | |
641 | struct drm_i915_private *dev_priv = dev->dev_private; | |
b6e45f86 KP |
642 | int ret; |
643 | unsigned long irqflags; | |
cff458c2 | 644 | |
286fed41 KP |
645 | /* Hold gt_lock across reset to prevent any register access |
646 | * with forcewake not set correctly | |
647 | */ | |
b6e45f86 | 648 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); |
286fed41 KP |
649 | |
650 | /* Reset the chip */ | |
651 | ||
652 | /* GEN6_GDRST is not in the gt power well, no need to check | |
653 | * for fifo space for the write or forcewake the chip for | |
654 | * the read | |
655 | */ | |
656 | I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL); | |
657 | ||
658 | /* Spin waiting for the device to ack the reset request */ | |
659 | ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); | |
660 | ||
661 | /* If reset with a user forcewake, try to restore, otherwise turn it off */ | |
b6e45f86 KP |
662 | if (dev_priv->forcewake_count) |
663 | dev_priv->display.force_wake_get(dev_priv); | |
286fed41 KP |
664 | else |
665 | dev_priv->display.force_wake_put(dev_priv); | |
666 | ||
667 | /* Restore fifo count */ | |
668 | dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES); | |
669 | ||
b6e45f86 KP |
670 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); |
671 | return ret; | |
cff458c2 EA |
672 | } |
673 | ||
11ed50ec | 674 | /** |
f3953dcb | 675 | * i915_reset - reset chip after a hang |
11ed50ec BG |
676 | * @dev: drm device to reset |
677 | * @flags: reset domains | |
678 | * | |
679 | * Reset the chip. Useful if a hang is detected. Returns zero on successful | |
680 | * reset or otherwise an error code. | |
681 | * | |
682 | * Procedure is fairly simple: | |
683 | * - reset the chip using the reset reg | |
684 | * - re-init context state | |
685 | * - re-init hardware status page | |
686 | * - re-init ring buffer | |
687 | * - re-init interrupt state | |
688 | * - re-init display | |
689 | */ | |
f803aa55 | 690 | int i915_reset(struct drm_device *dev, u8 flags) |
11ed50ec BG |
691 | { |
692 | drm_i915_private_t *dev_priv = dev->dev_private; | |
11ed50ec BG |
693 | /* |
694 | * We really should only reset the display subsystem if we actually | |
695 | * need to | |
696 | */ | |
697 | bool need_display = true; | |
0573ed4a | 698 | int ret; |
11ed50ec | 699 | |
d78cb50b CW |
700 | if (!i915_try_reset) |
701 | return 0; | |
702 | ||
340479aa CW |
703 | if (!mutex_trylock(&dev->struct_mutex)) |
704 | return -EBUSY; | |
11ed50ec | 705 | |
069efc1d | 706 | i915_gem_reset(dev); |
77f01230 | 707 | |
f803aa55 | 708 | ret = -ENODEV; |
ae681d96 CW |
709 | if (get_seconds() - dev_priv->last_gpu_reset < 5) { |
710 | DRM_ERROR("GPU hanging too fast, declaring wedged!\n"); | |
711 | } else switch (INTEL_INFO(dev)->gen) { | |
1083694a | 712 | case 7: |
cff458c2 EA |
713 | case 6: |
714 | ret = gen6_do_reset(dev, flags); | |
715 | break; | |
f803aa55 | 716 | case 5: |
0573ed4a | 717 | ret = ironlake_do_reset(dev, flags); |
f803aa55 CW |
718 | break; |
719 | case 4: | |
0573ed4a | 720 | ret = i965_do_reset(dev, flags); |
f803aa55 | 721 | break; |
dc96e9b8 CW |
722 | case 2: |
723 | ret = i8xx_do_reset(dev, flags); | |
724 | break; | |
f803aa55 | 725 | } |
ae681d96 | 726 | dev_priv->last_gpu_reset = get_seconds(); |
0573ed4a | 727 | if (ret) { |
f803aa55 | 728 | DRM_ERROR("Failed to reset chip.\n"); |
f953c935 | 729 | mutex_unlock(&dev->struct_mutex); |
f803aa55 | 730 | return ret; |
11ed50ec BG |
731 | } |
732 | ||
733 | /* Ok, now get things going again... */ | |
734 | ||
735 | /* | |
736 | * Everything depends on having the GTT running, so we need to start | |
737 | * there. Fortunately we don't need to do this unless we reset the | |
738 | * chip at a PCI level. | |
739 | * | |
740 | * Next we need to restore the context, but we don't use those | |
741 | * yet either... | |
742 | * | |
743 | * Ring buffer needs to be re-initialized in the KMS case, or if X | |
744 | * was running at the time of the reset (i.e. we weren't VT | |
745 | * switched away). | |
746 | */ | |
747 | if (drm_core_check_feature(dev, DRIVER_MODESET) || | |
8187a2b7 | 748 | !dev_priv->mm.suspended) { |
11ed50ec | 749 | dev_priv->mm.suspended = 0; |
75a6898f | 750 | |
f691e2f4 DV |
751 | i915_gem_init_swizzling(dev); |
752 | ||
1ec14ad3 | 753 | dev_priv->ring[RCS].init(&dev_priv->ring[RCS]); |
75a6898f | 754 | if (HAS_BSD(dev)) |
1ec14ad3 | 755 | dev_priv->ring[VCS].init(&dev_priv->ring[VCS]); |
75a6898f | 756 | if (HAS_BLT(dev)) |
1ec14ad3 | 757 | dev_priv->ring[BCS].init(&dev_priv->ring[BCS]); |
75a6898f | 758 | |
e21af88d DV |
759 | i915_gem_init_ppgtt(dev); |
760 | ||
11ed50ec BG |
761 | mutex_unlock(&dev->struct_mutex); |
762 | drm_irq_uninstall(dev); | |
500f7147 | 763 | drm_mode_config_reset(dev); |
11ed50ec BG |
764 | drm_irq_install(dev); |
765 | mutex_lock(&dev->struct_mutex); | |
766 | } | |
767 | ||
9fd98141 CW |
768 | mutex_unlock(&dev->struct_mutex); |
769 | ||
11ed50ec | 770 | /* |
9fd98141 CW |
771 | * Perform a full modeset as on later generations, e.g. Ironlake, we may |
772 | * need to retrain the display link and cannot just restore the register | |
773 | * values. | |
11ed50ec | 774 | */ |
9fd98141 CW |
775 | if (need_display) { |
776 | mutex_lock(&dev->mode_config.mutex); | |
777 | drm_helper_resume_force_mode(dev); | |
778 | mutex_unlock(&dev->mode_config.mutex); | |
779 | } | |
11ed50ec | 780 | |
11ed50ec BG |
781 | return 0; |
782 | } | |
783 | ||
784 | ||
112b715e KH |
785 | static int __devinit |
786 | i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) | |
787 | { | |
5fe49d86 CW |
788 | /* Only bind to function 0 of the device. Early generations |
789 | * used function 1 as a placeholder for multi-head. This causes | |
790 | * us confusion instead, especially on the systems where both | |
791 | * functions have the same PCI-ID! | |
792 | */ | |
793 | if (PCI_FUNC(pdev->devfn)) | |
794 | return -ENODEV; | |
795 | ||
dcdb1674 | 796 | return drm_get_pci_dev(pdev, ent, &driver); |
112b715e KH |
797 | } |
798 | ||
799 | static void | |
800 | i915_pci_remove(struct pci_dev *pdev) | |
801 | { | |
802 | struct drm_device *dev = pci_get_drvdata(pdev); | |
803 | ||
804 | drm_put_dev(dev); | |
805 | } | |
806 | ||
84b79f8d | 807 | static int i915_pm_suspend(struct device *dev) |
112b715e | 808 | { |
84b79f8d RW |
809 | struct pci_dev *pdev = to_pci_dev(dev); |
810 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
811 | int error; | |
112b715e | 812 | |
84b79f8d RW |
813 | if (!drm_dev || !drm_dev->dev_private) { |
814 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
815 | return -ENODEV; | |
816 | } | |
112b715e | 817 | |
5bcf719b DA |
818 | if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF) |
819 | return 0; | |
820 | ||
84b79f8d RW |
821 | error = i915_drm_freeze(drm_dev); |
822 | if (error) | |
823 | return error; | |
112b715e | 824 | |
84b79f8d RW |
825 | pci_disable_device(pdev); |
826 | pci_set_power_state(pdev, PCI_D3hot); | |
cbda12d7 | 827 | |
84b79f8d | 828 | return 0; |
cbda12d7 ZW |
829 | } |
830 | ||
84b79f8d | 831 | static int i915_pm_resume(struct device *dev) |
cbda12d7 | 832 | { |
84b79f8d RW |
833 | struct pci_dev *pdev = to_pci_dev(dev); |
834 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
835 | ||
836 | return i915_resume(drm_dev); | |
cbda12d7 ZW |
837 | } |
838 | ||
84b79f8d | 839 | static int i915_pm_freeze(struct device *dev) |
cbda12d7 | 840 | { |
84b79f8d RW |
841 | struct pci_dev *pdev = to_pci_dev(dev); |
842 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
843 | ||
844 | if (!drm_dev || !drm_dev->dev_private) { | |
845 | dev_err(dev, "DRM not initialized, aborting suspend.\n"); | |
846 | return -ENODEV; | |
847 | } | |
848 | ||
849 | return i915_drm_freeze(drm_dev); | |
cbda12d7 ZW |
850 | } |
851 | ||
84b79f8d | 852 | static int i915_pm_thaw(struct device *dev) |
cbda12d7 | 853 | { |
84b79f8d RW |
854 | struct pci_dev *pdev = to_pci_dev(dev); |
855 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
856 | ||
857 | return i915_drm_thaw(drm_dev); | |
cbda12d7 ZW |
858 | } |
859 | ||
84b79f8d | 860 | static int i915_pm_poweroff(struct device *dev) |
cbda12d7 | 861 | { |
84b79f8d RW |
862 | struct pci_dev *pdev = to_pci_dev(dev); |
863 | struct drm_device *drm_dev = pci_get_drvdata(pdev); | |
84b79f8d | 864 | |
61caf87c | 865 | return i915_drm_freeze(drm_dev); |
cbda12d7 ZW |
866 | } |
867 | ||
b4b78d12 | 868 | static const struct dev_pm_ops i915_pm_ops = { |
0206e353 AJ |
869 | .suspend = i915_pm_suspend, |
870 | .resume = i915_pm_resume, | |
871 | .freeze = i915_pm_freeze, | |
872 | .thaw = i915_pm_thaw, | |
873 | .poweroff = i915_pm_poweroff, | |
874 | .restore = i915_pm_resume, | |
cbda12d7 ZW |
875 | }; |
876 | ||
de151cf6 JB |
877 | static struct vm_operations_struct i915_gem_vm_ops = { |
878 | .fault = i915_gem_fault, | |
ab00b3e5 JB |
879 | .open = drm_gem_vm_open, |
880 | .close = drm_gem_vm_close, | |
de151cf6 JB |
881 | }; |
882 | ||
e08e96de AV |
883 | static const struct file_operations i915_driver_fops = { |
884 | .owner = THIS_MODULE, | |
885 | .open = drm_open, | |
886 | .release = drm_release, | |
887 | .unlocked_ioctl = drm_ioctl, | |
888 | .mmap = drm_gem_mmap, | |
889 | .poll = drm_poll, | |
890 | .fasync = drm_fasync, | |
891 | .read = drm_read, | |
892 | #ifdef CONFIG_COMPAT | |
893 | .compat_ioctl = i915_compat_ioctl, | |
894 | #endif | |
895 | .llseek = noop_llseek, | |
896 | }; | |
897 | ||
1da177e4 | 898 | static struct drm_driver driver = { |
0c54781b MW |
899 | /* Don't use MTRRs here; the Xserver or userspace app should |
900 | * deal with them for Intel hardware. | |
792d2b9a | 901 | */ |
673a394b EA |
902 | .driver_features = |
903 | DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/ | |
904 | DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM, | |
22eae947 | 905 | .load = i915_driver_load, |
ba8bbcf6 | 906 | .unload = i915_driver_unload, |
673a394b | 907 | .open = i915_driver_open, |
22eae947 DA |
908 | .lastclose = i915_driver_lastclose, |
909 | .preclose = i915_driver_preclose, | |
673a394b | 910 | .postclose = i915_driver_postclose, |
d8e29209 RW |
911 | |
912 | /* Used in place of i915_pm_ops for non-DRIVER_MODESET */ | |
913 | .suspend = i915_suspend, | |
914 | .resume = i915_resume, | |
915 | ||
cda17380 | 916 | .device_is_agp = i915_driver_device_is_agp, |
1da177e4 | 917 | .reclaim_buffers = drm_core_reclaim_buffers, |
7c1c2871 DA |
918 | .master_create = i915_master_create, |
919 | .master_destroy = i915_master_destroy, | |
955b12de | 920 | #if defined(CONFIG_DEBUG_FS) |
27c202ad BG |
921 | .debugfs_init = i915_debugfs_init, |
922 | .debugfs_cleanup = i915_debugfs_cleanup, | |
955b12de | 923 | #endif |
673a394b EA |
924 | .gem_init_object = i915_gem_init_object, |
925 | .gem_free_object = i915_gem_free_object, | |
de151cf6 | 926 | .gem_vm_ops = &i915_gem_vm_ops, |
ff72145b DA |
927 | .dumb_create = i915_gem_dumb_create, |
928 | .dumb_map_offset = i915_gem_mmap_gtt, | |
929 | .dumb_destroy = i915_gem_dumb_destroy, | |
1da177e4 | 930 | .ioctls = i915_ioctls, |
e08e96de | 931 | .fops = &i915_driver_fops, |
22eae947 DA |
932 | .name = DRIVER_NAME, |
933 | .desc = DRIVER_DESC, | |
934 | .date = DRIVER_DATE, | |
935 | .major = DRIVER_MAJOR, | |
936 | .minor = DRIVER_MINOR, | |
937 | .patchlevel = DRIVER_PATCHLEVEL, | |
1da177e4 LT |
938 | }; |
939 | ||
8410ea3b DA |
940 | static struct pci_driver i915_pci_driver = { |
941 | .name = DRIVER_NAME, | |
942 | .id_table = pciidlist, | |
943 | .probe = i915_pci_probe, | |
944 | .remove = i915_pci_remove, | |
945 | .driver.pm = &i915_pm_ops, | |
946 | }; | |
947 | ||
1da177e4 LT |
948 | static int __init i915_init(void) |
949 | { | |
1f7a6e37 ZW |
950 | if (!intel_agp_enabled) { |
951 | DRM_ERROR("drm/i915 can't work without intel_agp module!\n"); | |
952 | return -ENODEV; | |
953 | } | |
954 | ||
1da177e4 | 955 | driver.num_ioctls = i915_max_ioctl; |
79e53945 JB |
956 | |
957 | /* | |
958 | * If CONFIG_DRM_I915_KMS is set, default to KMS unless | |
959 | * explicitly disabled with the module pararmeter. | |
960 | * | |
961 | * Otherwise, just follow the parameter (defaulting to off). | |
962 | * | |
963 | * Allow optional vga_text_mode_force boot option to override | |
964 | * the default behavior. | |
965 | */ | |
966 | #if defined(CONFIG_DRM_I915_KMS) | |
967 | if (i915_modeset != 0) | |
968 | driver.driver_features |= DRIVER_MODESET; | |
969 | #endif | |
970 | if (i915_modeset == 1) | |
971 | driver.driver_features |= DRIVER_MODESET; | |
972 | ||
973 | #ifdef CONFIG_VGA_CONSOLE | |
974 | if (vgacon_text_force() && i915_modeset == -1) | |
975 | driver.driver_features &= ~DRIVER_MODESET; | |
976 | #endif | |
977 | ||
3885c6bb CW |
978 | if (!(driver.driver_features & DRIVER_MODESET)) |
979 | driver.get_vblank_timestamp = NULL; | |
980 | ||
8410ea3b | 981 | return drm_pci_init(&driver, &i915_pci_driver); |
1da177e4 LT |
982 | } |
983 | ||
984 | static void __exit i915_exit(void) | |
985 | { | |
8410ea3b | 986 | drm_pci_exit(&driver, &i915_pci_driver); |
1da177e4 LT |
987 | } |
988 | ||
989 | module_init(i915_init); | |
990 | module_exit(i915_exit); | |
991 | ||
b5e89ed5 DA |
992 | MODULE_AUTHOR(DRIVER_AUTHOR); |
993 | MODULE_DESCRIPTION(DRIVER_DESC); | |
1da177e4 | 994 | MODULE_LICENSE("GPL and additional rights"); |
f7000883 | 995 | |
f7000883 AK |
996 | #define __i915_read(x, y) \ |
997 | u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
998 | u##x val = 0; \ | |
999 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
c937504e KP |
1000 | unsigned long irqflags; \ |
1001 | spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \ | |
1002 | if (dev_priv->forcewake_count == 0) \ | |
1003 | dev_priv->display.force_wake_get(dev_priv); \ | |
f7000883 | 1004 | val = read##y(dev_priv->regs + reg); \ |
c937504e KP |
1005 | if (dev_priv->forcewake_count == 0) \ |
1006 | dev_priv->display.force_wake_put(dev_priv); \ | |
1007 | spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \ | |
f7000883 AK |
1008 | } else { \ |
1009 | val = read##y(dev_priv->regs + reg); \ | |
1010 | } \ | |
1011 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ | |
1012 | return val; \ | |
1013 | } | |
1014 | ||
1015 | __i915_read(8, b) | |
1016 | __i915_read(16, w) | |
1017 | __i915_read(32, l) | |
1018 | __i915_read(64, q) | |
1019 | #undef __i915_read | |
1020 | ||
1021 | #define __i915_write(x, y) \ | |
1022 | void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
67a3744f | 1023 | u32 __fifo_ret = 0; \ |
f7000883 AK |
1024 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
1025 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
67a3744f | 1026 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
f7000883 AK |
1027 | } \ |
1028 | write##y(val, dev_priv->regs + reg); \ | |
67a3744f BW |
1029 | if (unlikely(__fifo_ret)) { \ |
1030 | gen6_gt_check_fifodbg(dev_priv); \ | |
1031 | } \ | |
f7000883 AK |
1032 | } |
1033 | __i915_write(8, b) | |
1034 | __i915_write(16, w) | |
1035 | __i915_write(32, l) | |
1036 | __i915_write(64, q) | |
1037 | #undef __i915_write |