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Merge tag 'topic/drm-misc-2016-01-17' of git://anongit.freedesktop.org/drm-intel...
[GitHub/moto-9609/android_kernel_motorola_exynos9610.git] / drivers / gpu / drm / i2c / tda998x_drv.c
CommitLineData
e7792ce2
RC		 1/*
2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
c707c361 18#include <linux/component.h>
893c3e53 19#include <linux/hdmi.h>
e7792ce2 20#include <linux/module.h>
12473b7d 21#include <linux/irq.h>
f0b33b28 22#include <sound/asoundef.h>
e7792ce2
RC		 23
24#include <drm/drmP.h>
9736e988 25#include <drm/drm_atomic_helper.h>
e7792ce2 26#include <drm/drm_crtc_helper.h>
e7792ce2 27#include <drm/drm_edid.h>
5dbcf319 28#include <drm/drm_of.h>
c4c11dd1 29#include <drm/i2c/tda998x.h>
e7792ce2
RC		 30
31#define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
32
33struct tda998x_priv {
34 struct i2c_client *cec;
2f7f730a 35 struct i2c_client *hdmi;
ed9a8426 36 struct mutex mutex;
e66e03ab
RK		 37 u16 rev;
38 u8 current_page;
e7792ce2 39 int dpms;
c4c11dd1 40 bool is_hdmi_sink;
5e74c22c
RK		 41 u8 vip_cntrl_0;
42 u8 vip_cntrl_1;
43 u8 vip_cntrl_2;
c4c11dd1 44 struct tda998x_encoder_params params;
12473b7d
JFM		 45
46 wait_queue_head_t wq_edid;
47 volatile int wq_edid_wait;
0fc6f44d
RK		 48
49 struct work_struct detect_work;
50 struct timer_list edid_delay_timer;
51 wait_queue_head_t edid_delay_waitq;
52 bool edid_delay_active;
78e401f9
RK		 53
54 struct drm_encoder encoder;
eed64b59 55 struct drm_connector connector;
e7792ce2
RC		 56};
57
9525c4dd
RK		 58#define conn_to_tda998x_priv(x) \
59 container_of(x, struct tda998x_priv, connector)
60
61#define enc_to_tda998x_priv(x) \
62 container_of(x, struct tda998x_priv, encoder)
63
e7792ce2
RC		 64/* The TDA9988 series of devices use a paged register scheme.. to simplify
65 * things we encode the page # in upper bits of the register #. To read/
66 * write a given register, we need to make sure CURPAGE register is set
67 * appropriately. Which implies reads/writes are not atomic. Fun!
68 */
69
70#define REG(page, addr) (((page) << 8) | (addr))
71#define REG2ADDR(reg) ((reg) & 0xff)
72#define REG2PAGE(reg) (((reg) >> 8) & 0xff)
73
74#define REG_CURPAGE 0xff /* write */
75
76
77/* Page 00h: General Control */
78#define REG_VERSION_LSB REG(0x00, 0x00) /* read */
79#define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
80# define MAIN_CNTRL0_SR (1 << 0)
81# define MAIN_CNTRL0_DECS (1 << 1)
82# define MAIN_CNTRL0_DEHS (1 << 2)
83# define MAIN_CNTRL0_CECS (1 << 3)
84# define MAIN_CNTRL0_CEHS (1 << 4)
85# define MAIN_CNTRL0_SCALER (1 << 7)
86#define REG_VERSION_MSB REG(0x00, 0x02) /* read */
87#define REG_SOFTRESET REG(0x00, 0x0a) /* write */
88# define SOFTRESET_AUDIO (1 << 0)
89# define SOFTRESET_I2C_MASTER (1 << 1)
90#define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
91#define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
92#define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
93# define I2C_MASTER_DIS_MM (1 << 0)
94# define I2C_MASTER_DIS_FILT (1 << 1)
95# define I2C_MASTER_APP_STRT_LAT (1 << 2)
c4c11dd1
RK		 96#define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
97# define FEAT_POWERDOWN_SPDIF (1 << 3)
e7792ce2
RC		 98#define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
99#define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */
100#define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */
101# define INT_FLAGS_2_EDID_BLK_RD (1 << 1)
c4c11dd1 102#define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */
e7792ce2
RC		 103#define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */
104#define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */
105#define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */
106#define REG_ENA_AP REG(0x00, 0x1e) /* read/write */
107#define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */
108# define VIP_CNTRL_0_MIRR_A (1 << 7)
109# define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4)
110# define VIP_CNTRL_0_MIRR_B (1 << 3)
111# define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0)
112#define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */
113# define VIP_CNTRL_1_MIRR_C (1 << 7)
114# define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4)
115# define VIP_CNTRL_1_MIRR_D (1 << 3)
116# define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0)
117#define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */
118# define VIP_CNTRL_2_MIRR_E (1 << 7)
119# define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4)
120# define VIP_CNTRL_2_MIRR_F (1 << 3)
121# define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0)
122#define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */
123# define VIP_CNTRL_3_X_TGL (1 << 0)
124# define VIP_CNTRL_3_H_TGL (1 << 1)
125# define VIP_CNTRL_3_V_TGL (1 << 2)
126# define VIP_CNTRL_3_EMB (1 << 3)
127# define VIP_CNTRL_3_SYNC_DE (1 << 4)
128# define VIP_CNTRL_3_SYNC_HS (1 << 5)
129# define VIP_CNTRL_3_DE_INT (1 << 6)
130# define VIP_CNTRL_3_EDGE (1 << 7)
131#define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */
132# define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0)
133# define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2)
134# define VIP_CNTRL_4_CCIR656 (1 << 4)
135# define VIP_CNTRL_4_656_ALT (1 << 5)
136# define VIP_CNTRL_4_TST_656 (1 << 6)
137# define VIP_CNTRL_4_TST_PAT (1 << 7)
138#define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */
139# define VIP_CNTRL_5_CKCASE (1 << 0)
140# define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1)
c4c11dd1 141#define REG_MUX_AP REG(0x00, 0x26) /* read/write */
10df1a95
JFM		 142# define MUX_AP_SELECT_I2S 0x64
143# define MUX_AP_SELECT_SPDIF 0x40
bcb2481d 144#define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */
e7792ce2
RC		 145#define REG_MAT_CONTRL REG(0x00, 0x80) /* write */
146# define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0)
147# define MAT_CONTRL_MAT_BP (1 << 2)
148#define REG_VIDFORMAT REG(0x00, 0xa0) /* write */
149#define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */
150#define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */
151#define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */
152#define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */
153#define REG_NPIX_MSB REG(0x00, 0xa5) /* write */
154#define REG_NPIX_LSB REG(0x00, 0xa6) /* write */
155#define REG_NLINE_MSB REG(0x00, 0xa7) /* write */
156#define REG_NLINE_LSB REG(0x00, 0xa8) /* write */
157#define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */
158#define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */
159#define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */
160#define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */
161#define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */
162#define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */
163#define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */
164#define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */
088d61d1
SH		 165#define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */
166#define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */
e7792ce2
RC		 167#define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */
168#define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */
088d61d1
SH		 169#define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */
170#define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */
e7792ce2
RC		 171#define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */
172#define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */
173#define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */
174#define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */
175#define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */
176#define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */
177#define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */
178#define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */
179#define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */
180#define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */
088d61d1
SH		 181#define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */
182#define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */
183#define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */
184#define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */
e7792ce2
RC		 185#define REG_DE_START_MSB REG(0x00, 0xc5) /* write */
186#define REG_DE_START_LSB REG(0x00, 0xc6) /* write */
187#define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */
188#define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */
189#define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */
088d61d1
SH		 190# define TBG_CNTRL_0_TOP_TGL (1 << 0)
191# define TBG_CNTRL_0_TOP_SEL (1 << 1)
192# define TBG_CNTRL_0_DE_EXT (1 << 2)
193# define TBG_CNTRL_0_TOP_EXT (1 << 3)
e7792ce2
RC		 194# define TBG_CNTRL_0_FRAME_DIS (1 << 5)
195# define TBG_CNTRL_0_SYNC_MTHD (1 << 6)
196# define TBG_CNTRL_0_SYNC_ONCE (1 << 7)
197#define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */
088d61d1
SH		 198# define TBG_CNTRL_1_H_TGL (1 << 0)
199# define TBG_CNTRL_1_V_TGL (1 << 1)
200# define TBG_CNTRL_1_TGL_EN (1 << 2)
201# define TBG_CNTRL_1_X_EXT (1 << 3)
202# define TBG_CNTRL_1_H_EXT (1 << 4)
203# define TBG_CNTRL_1_V_EXT (1 << 5)
e7792ce2
RC		 204# define TBG_CNTRL_1_DWIN_DIS (1 << 6)
205#define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */
206#define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */
207# define HVF_CNTRL_0_SM (1 << 7)
208# define HVF_CNTRL_0_RWB (1 << 6)
209# define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2)
210# define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0)
211#define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */
212# define HVF_CNTRL_1_FOR (1 << 0)
213# define HVF_CNTRL_1_YUVBLK (1 << 1)
214# define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2)
215# define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4)
216# define HVF_CNTRL_1_SEMI_PLANAR (1 << 6)
217#define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */
c4c11dd1
RK		 218#define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */
219# define I2S_FORMAT(x) (((x) & 3) << 0)
220#define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */
10df1a95
JFM		 221# define AIP_CLKSEL_AIP_SPDIF (0 << 3)
222# define AIP_CLKSEL_AIP_I2S (1 << 3)
223# define AIP_CLKSEL_FS_ACLK (0 << 0)
224# define AIP_CLKSEL_FS_MCLK (1 << 0)
225# define AIP_CLKSEL_FS_FS64SPDIF (2 << 0)
e7792ce2
RC		 226
227/* Page 02h: PLL settings */
228#define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */
229# define PLL_SERIAL_1_SRL_FDN (1 << 0)
230# define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1)
231# define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6)
232#define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */
3ae471f7 233# define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0)
e7792ce2
RC		 234# define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4)
235#define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */
236# define PLL_SERIAL_3_SRL_CCIR (1 << 0)
237# define PLL_SERIAL_3_SRL_DE (1 << 2)
238# define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4)
239#define REG_SERIALIZER REG(0x02, 0x03) /* read/write */
240#define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */
241#define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */
242#define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */
243#define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */
244#define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */
245#define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */
246#define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */
247#define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */
c4c11dd1
RK		 248# define AUDIO_DIV_SERCLK_1 0
249# define AUDIO_DIV_SERCLK_2 1
250# define AUDIO_DIV_SERCLK_4 2
251# define AUDIO_DIV_SERCLK_8 3
252# define AUDIO_DIV_SERCLK_16 4
253# define AUDIO_DIV_SERCLK_32 5
e7792ce2
RC		 254#define REG_SEL_CLK REG(0x02, 0x11) /* read/write */
255# define SEL_CLK_SEL_CLK1 (1 << 0)
256# define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1)
257# define SEL_CLK_ENA_SC_CLK (1 << 3)
258#define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */
259
260
261/* Page 09h: EDID Control */
262#define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */
263/* next 127 successive registers are the EDID block */
264#define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */
265#define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */
266#define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */
267#define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */
268#define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */
269
270
271/* Page 10h: information frames and packets */
c4c11dd1
RK		 272#define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */
273#define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */
274#define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */
275#define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */
276#define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */
e7792ce2
RC		 277
278
279/* Page 11h: audio settings and content info packets */
280#define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */
281# define AIP_CNTRL_0_RST_FIFO (1 << 0)
282# define AIP_CNTRL_0_SWAP (1 << 1)
283# define AIP_CNTRL_0_LAYOUT (1 << 2)
284# define AIP_CNTRL_0_ACR_MAN (1 << 5)
285# define AIP_CNTRL_0_RST_CTS (1 << 6)
c4c11dd1
RK		 286#define REG_CA_I2S REG(0x11, 0x01) /* read/write */
287# define CA_I2S_CA_I2S(x) (((x) & 31) << 0)
288# define CA_I2S_HBR_CHSTAT (1 << 6)
289#define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */
290#define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */
291#define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */
292#define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */
293#define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */
294#define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */
295#define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */
296#define REG_CTS_N REG(0x11, 0x0c) /* read/write */
297# define CTS_N_K(x) (((x) & 7) << 0)
298# define CTS_N_M(x) (((x) & 3) << 4)
e7792ce2
RC		 299#define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */
300# define ENC_CNTRL_RST_ENC (1 << 0)
301# define ENC_CNTRL_RST_SEL (1 << 1)
302# define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2)
c4c11dd1
RK		 303#define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */
304# define DIP_FLAGS_ACR (1 << 0)
305# define DIP_FLAGS_GC (1 << 1)
306#define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */
307# define DIP_IF_FLAGS_IF1 (1 << 1)
308# define DIP_IF_FLAGS_IF2 (1 << 2)
309# define DIP_IF_FLAGS_IF3 (1 << 3)
310# define DIP_IF_FLAGS_IF4 (1 << 4)
311# define DIP_IF_FLAGS_IF5 (1 << 5)
312#define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */
e7792ce2
RC		 313
314
315/* Page 12h: HDCP and OTP */
316#define REG_TX3 REG(0x12, 0x9a) /* read/write */
063b472f
RK		 317#define REG_TX4 REG(0x12, 0x9b) /* read/write */
318# define TX4_PD_RAM (1 << 1)
e7792ce2
RC		 319#define REG_TX33 REG(0x12, 0xb8) /* read/write */
320# define TX33_HDMI (1 << 1)
321
322
323/* Page 13h: Gamut related metadata packets */
324
325
326
327/* CEC registers: (not paged)
328 */
12473b7d
JFM		 329#define REG_CEC_INTSTATUS 0xee /* read */
330# define CEC_INTSTATUS_CEC (1 << 0)
331# define CEC_INTSTATUS_HDMI (1 << 1)
e7792ce2
RC		 332#define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */
333# define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7)
334# define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6)
335# define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1)
336# define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0)
12473b7d
JFM		 337#define REG_CEC_RXSHPDINTENA 0xfc /* read/write */
338#define REG_CEC_RXSHPDINT 0xfd /* read */
ec5d3e83
RK		 339# define CEC_RXSHPDINT_RXSENS BIT(0)
340# define CEC_RXSHPDINT_HPD BIT(1)
e7792ce2
RC		 341#define REG_CEC_RXSHPDLEV 0xfe /* read */
342# define CEC_RXSHPDLEV_RXSENS (1 << 0)
343# define CEC_RXSHPDLEV_HPD (1 << 1)
344
345#define REG_CEC_ENAMODS 0xff /* read/write */
346# define CEC_ENAMODS_DIS_FRO (1 << 6)
347# define CEC_ENAMODS_DIS_CCLK (1 << 5)
348# define CEC_ENAMODS_EN_RXSENS (1 << 2)
349# define CEC_ENAMODS_EN_HDMI (1 << 1)
350# define CEC_ENAMODS_EN_CEC (1 << 0)
351
352
353/* Device versions: */
354#define TDA9989N2 0x0101
355#define TDA19989 0x0201
356#define TDA19989N2 0x0202
357#define TDA19988 0x0301
358
359static void
e66e03ab 360cec_write(struct tda998x_priv *priv, u16 addr, u8 val)
e7792ce2 361{
2f7f730a 362 struct i2c_client *client = priv->cec;
e66e03ab 363 u8 buf[] = {addr, val};
e7792ce2
RC		 364 int ret;
365
704d63f5 366 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 367 if (ret < 0)
368 dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr);
369}
370
e66e03ab
RK		 371static u8
372cec_read(struct tda998x_priv *priv, u8 addr)
e7792ce2 373{
2f7f730a 374 struct i2c_client *client = priv->cec;
e66e03ab 375 u8 val;
e7792ce2
RC		 376 int ret;
377
378 ret = i2c_master_send(client, &addr, sizeof(addr));
379 if (ret < 0)
380 goto fail;
381
382 ret = i2c_master_recv(client, &val, sizeof(val));
383 if (ret < 0)
384 goto fail;
385
386 return val;
387
388fail:
389 dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr);
390 return 0;
391}
392
7d2eadc9 393static int
e66e03ab 394set_page(struct tda998x_priv *priv, u16 reg)
e7792ce2 395{
e7792ce2 396 if (REG2PAGE(reg) != priv->current_page) {
2f7f730a 397 struct i2c_client *client = priv->hdmi;
e66e03ab 398 u8 buf[] = {
e7792ce2
RC		 399 REG_CURPAGE, REG2PAGE(reg)
400 };
401 int ret = i2c_master_send(client, buf, sizeof(buf));
7d2eadc9 402 if (ret < 0) {
288ffc73 403 dev_err(&client->dev, "%s %04x err %d\n", __func__,
704d63f5 404 reg, ret);
7d2eadc9
JFM		 405 return ret;
406 }
e7792ce2
RC		 407
408 priv->current_page = REG2PAGE(reg);
409 }
7d2eadc9 410 return 0;
e7792ce2
RC		 411}
412
413static int
e66e03ab 414reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt)
e7792ce2 415{
2f7f730a 416 struct i2c_client *client = priv->hdmi;
e66e03ab 417 u8 addr = REG2ADDR(reg);
e7792ce2
RC		 418 int ret;
419
ed9a8426 420 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 421 ret = set_page(priv, reg);
422 if (ret < 0)
ed9a8426 423 goto out;
e7792ce2
RC		 424
425 ret = i2c_master_send(client, &addr, sizeof(addr));
426 if (ret < 0)
427 goto fail;
428
429 ret = i2c_master_recv(client, buf, cnt);
430 if (ret < 0)
431 goto fail;
432
ed9a8426 433 goto out;
e7792ce2
RC		 434
435fail:
436 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg);
ed9a8426
JFM		 437out:
438 mutex_unlock(&priv->mutex);
e7792ce2
RC		 439 return ret;
440}
441
c4c11dd1 442static void
e66e03ab 443reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt)
c4c11dd1 444{
2f7f730a 445 struct i2c_client *client = priv->hdmi;
e66e03ab 446 u8 buf[cnt+1];
c4c11dd1
RK		 447 int ret;
448
449 buf[0] = REG2ADDR(reg);
450 memcpy(&buf[1], p, cnt);
451
ed9a8426 452 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 453 ret = set_page(priv, reg);
454 if (ret < 0)
ed9a8426 455 goto out;
c4c11dd1
RK		 456
457 ret = i2c_master_send(client, buf, cnt + 1);
458 if (ret < 0)
459 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 460out:
461 mutex_unlock(&priv->mutex);
c4c11dd1
RK		 462}
463
7d2eadc9 464static int
e66e03ab 465reg_read(struct tda998x_priv *priv, u16 reg)
e7792ce2 466{
e66e03ab 467 u8 val = 0;
7d2eadc9
JFM		 468 int ret;
469
470 ret = reg_read_range(priv, reg, &val, sizeof(val));
471 if (ret < 0)
472 return ret;
e7792ce2
RC		 473 return val;
474}
475
476static void
e66e03ab 477reg_write(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 478{
2f7f730a 479 struct i2c_client *client = priv->hdmi;
e66e03ab 480 u8 buf[] = {REG2ADDR(reg), val};
e7792ce2
RC		 481 int ret;
482
ed9a8426 483 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 484 ret = set_page(priv, reg);
485 if (ret < 0)
ed9a8426 486 goto out;
e7792ce2 487
704d63f5 488 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 489 if (ret < 0)
490 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 491out:
492 mutex_unlock(&priv->mutex);
e7792ce2
RC		 493}
494
495static void
e66e03ab 496reg_write16(struct tda998x_priv *priv, u16 reg, u16 val)
e7792ce2 497{
2f7f730a 498 struct i2c_client *client = priv->hdmi;
e66e03ab 499 u8 buf[] = {REG2ADDR(reg), val >> 8, val};
e7792ce2
RC		 500 int ret;
501
ed9a8426 502 mutex_lock(&priv->mutex);
7d2eadc9
JFM		 503 ret = set_page(priv, reg);
504 if (ret < 0)
ed9a8426 505 goto out;
e7792ce2 506
704d63f5 507 ret = i2c_master_send(client, buf, sizeof(buf));
e7792ce2
RC		 508 if (ret < 0)
509 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg);
ed9a8426
JFM		 510out:
511 mutex_unlock(&priv->mutex);
e7792ce2
RC		 512}
513
514static void
e66e03ab 515reg_set(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 516{
7d2eadc9
JFM		 517 int old_val;
518
519 old_val = reg_read(priv, reg);
520 if (old_val >= 0)
521 reg_write(priv, reg, old_val | val);
e7792ce2
RC		 522}
523
524static void
e66e03ab 525reg_clear(struct tda998x_priv *priv, u16 reg, u8 val)
e7792ce2 526{
7d2eadc9
JFM		 527 int old_val;
528
529 old_val = reg_read(priv, reg);
530 if (old_val >= 0)
531 reg_write(priv, reg, old_val & ~val);
e7792ce2
RC		 532}
533
534static void
2f7f730a 535tda998x_reset(struct tda998x_priv *priv)
e7792ce2
RC		 536{
537 /* reset audio and i2c master: */
81b53a16 538 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER);
e7792ce2 539 msleep(50);
81b53a16 540 reg_write(priv, REG_SOFTRESET, 0);
e7792ce2
RC		 541 msleep(50);
542
543 /* reset transmitter: */
2f7f730a
JFM		 544 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
545 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR);
e7792ce2
RC		 546
547 /* PLL registers common configuration */
2f7f730a
JFM		 548 reg_write(priv, REG_PLL_SERIAL_1, 0x00);
549 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1));
550 reg_write(priv, REG_PLL_SERIAL_3, 0x00);
551 reg_write(priv, REG_SERIALIZER, 0x00);
552 reg_write(priv, REG_BUFFER_OUT, 0x00);
553 reg_write(priv, REG_PLL_SCG1, 0x00);
554 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8);
555 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
556 reg_write(priv, REG_PLL_SCGN1, 0xfa);
557 reg_write(priv, REG_PLL_SCGN2, 0x00);
558 reg_write(priv, REG_PLL_SCGR1, 0x5b);
559 reg_write(priv, REG_PLL_SCGR2, 0x00);
560 reg_write(priv, REG_PLL_SCG2, 0x10);
bcb2481d
RK		 561
562 /* Write the default value MUX register */
2f7f730a 563 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24);
e7792ce2
RC		 564}
565
0fc6f44d
RK		 566/*
567 * The TDA998x has a problem when trying to read the EDID close to a
568 * HPD assertion: it needs a delay of 100ms to avoid timing out while
569 * trying to read EDID data.
570 *
571 * However, tda998x_encoder_get_modes() may be called at any moment
9525c4dd 572 * after tda998x_connector_detect() indicates that we are connected, so
0fc6f44d
RK		 573 * we need to delay probing modes in tda998x_encoder_get_modes() after
574 * we have seen a HPD inactive->active transition. This code implements
575 * that delay.
576 */
577static void tda998x_edid_delay_done(unsigned long data)
578{
579 struct tda998x_priv *priv = (struct tda998x_priv *)data;
580
581 priv->edid_delay_active = false;
582 wake_up(&priv->edid_delay_waitq);
583 schedule_work(&priv->detect_work);
584}
585
586static void tda998x_edid_delay_start(struct tda998x_priv *priv)
587{
588 priv->edid_delay_active = true;
589 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10);
590}
591
592static int tda998x_edid_delay_wait(struct tda998x_priv *priv)
593{
594 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active);
595}
596
597/*
598 * We need to run the KMS hotplug event helper outside of our threaded
599 * interrupt routine as this can call back into our get_modes method,
600 * which will want to make use of interrupts.
601 */
602static void tda998x_detect_work(struct work_struct *work)
6833d26e 603{
6833d26e 604 struct tda998x_priv *priv =
0fc6f44d 605 container_of(work, struct tda998x_priv, detect_work);
78e401f9 606 struct drm_device *dev = priv->encoder.dev;
6833d26e 607
0fc6f44d
RK		 608 if (dev)
609 drm_kms_helper_hotplug_event(dev);
6833d26e
JFM		 610}
611
12473b7d
JFM		 612/*
613 * only 2 interrupts may occur: screen plug/unplug and EDID read
614 */
615static irqreturn_t tda998x_irq_thread(int irq, void *data)
616{
617 struct tda998x_priv *priv = data;
618 u8 sta, cec, lvl, flag0, flag1, flag2;
f84a97d4 619 bool handled = false;
12473b7d 620
12473b7d
JFM		 621 sta = cec_read(priv, REG_CEC_INTSTATUS);
622 cec = cec_read(priv, REG_CEC_RXSHPDINT);
623 lvl = cec_read(priv, REG_CEC_RXSHPDLEV);
624 flag0 = reg_read(priv, REG_INT_FLAGS_0);
625 flag1 = reg_read(priv, REG_INT_FLAGS_1);
626 flag2 = reg_read(priv, REG_INT_FLAGS_2);
627 DRM_DEBUG_DRIVER(
628 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n",
629 sta, cec, lvl, flag0, flag1, flag2);
ec5d3e83
RK		 630
631 if (cec & CEC_RXSHPDINT_HPD) {
0fc6f44d
RK		 632 if (lvl & CEC_RXSHPDLEV_HPD)
633 tda998x_edid_delay_start(priv);
634 else
635 schedule_work(&priv->detect_work);
636
f84a97d4 637 handled = true;
12473b7d 638 }
ec5d3e83
RK		 639
640 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) {
641 priv->wq_edid_wait = 0;
642 wake_up(&priv->wq_edid);
643 handled = true;
644 }
645
f84a97d4 646 return IRQ_RETVAL(handled);
12473b7d
JFM		 647}
648
c4c11dd1 649static void
e66e03ab 650tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr,
96795df1 651 union hdmi_infoframe *frame)
c4c11dd1 652{
96795df1
RK		 653 u8 buf[32];
654 ssize_t len;
655
656 len = hdmi_infoframe_pack(frame, buf, sizeof(buf));
657 if (len < 0) {
658 dev_err(&priv->hdmi->dev,
659 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n",
660 frame->any.type, len);
661 return;
662 }
663
2f7f730a 664 reg_clear(priv, REG_DIP_IF_FLAGS, bit);
96795df1 665 reg_write_range(priv, addr, buf, len);
2f7f730a 666 reg_set(priv, REG_DIP_IF_FLAGS, bit);
c4c11dd1
RK		 667}
668
669static void
2f7f730a 670tda998x_write_aif(struct tda998x_priv *priv, struct tda998x_encoder_params *p)
c4c11dd1 671{
96795df1
RK		 672 union hdmi_infoframe frame;
673
674 hdmi_audio_infoframe_init(&frame.audio);
c4c11dd1 675
96795df1
RK		 676 frame.audio.channels = p->audio_frame[1] & 0x07;
677 frame.audio.channel_allocation = p->audio_frame[4];
678 frame.audio.level_shift_value = (p->audio_frame[5] & 0x78) >> 3;
679 frame.audio.downmix_inhibit = (p->audio_frame[5] & 0x80) >> 7;
c4c11dd1 680
96795df1
RK		 681 /*
682 * L-PCM and IEC61937 compressed audio shall always set sample
683 * frequency to "refer to stream". For others, see the HDMI
684 * specification.
685 */
686 frame.audio.sample_frequency = (p->audio_frame[2] & 0x1c) >> 2;
4a6ca1a2 687
96795df1 688 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame);
c4c11dd1
RK		 689}
690
691static void
2f7f730a 692tda998x_write_avi(struct tda998x_priv *priv, struct drm_display_mode *mode)
c4c11dd1 693{
96795df1 694 union hdmi_infoframe frame;
8c7a075d 695
96795df1
RK		 696 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode);
697 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL;
8c7a075d 698
96795df1 699 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame);
c4c11dd1
RK		 700}
701
2f7f730a 702static void tda998x_audio_mute(struct tda998x_priv *priv, bool on)
c4c11dd1
RK		 703{
704 if (on) {
2f7f730a
JFM		 705 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
706 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO);
707 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1 708 } else {
2f7f730a 709 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
c4c11dd1
RK		 710 }
711}
712
713static void
2f7f730a 714tda998x_configure_audio(struct tda998x_priv *priv,
c4c11dd1
RK		 715 struct drm_display_mode *mode, struct tda998x_encoder_params *p)
716{
e66e03ab
RK		 717 u8 buf[6], clksel_aip, clksel_fs, cts_n, adiv;
718 u32 n;
c4c11dd1
RK		 719
720 /* Enable audio ports */
2f7f730a
JFM		 721 reg_write(priv, REG_ENA_AP, p->audio_cfg);
722 reg_write(priv, REG_ENA_ACLK, p->audio_clk_cfg);
c4c11dd1
RK		 723
724 /* Set audio input source */
725 switch (p->audio_format) {
726 case AFMT_SPDIF:
10df1a95
JFM		 727 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_SPDIF);
728 clksel_aip = AIP_CLKSEL_AIP_SPDIF;
729 clksel_fs = AIP_CLKSEL_FS_FS64SPDIF;
c4c11dd1 730 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1
RK		 731 break;
732
733 case AFMT_I2S:
10df1a95
JFM		 734 reg_write(priv, REG_MUX_AP, MUX_AP_SELECT_I2S);
735 clksel_aip = AIP_CLKSEL_AIP_I2S;
736 clksel_fs = AIP_CLKSEL_FS_ACLK;
c4c11dd1 737 cts_n = CTS_N_M(3) | CTS_N_K(3);
c4c11dd1 738 break;
3b28802e
DH		 739
740 default:
741 BUG();
742 return;
c4c11dd1
RK		 743 }
744
2f7f730a 745 reg_write(priv, REG_AIP_CLKSEL, clksel_aip);
a8b517e5
JFM		 746 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT |
747 AIP_CNTRL_0_ACR_MAN); /* auto CTS */
2f7f730a 748 reg_write(priv, REG_CTS_N, cts_n);
c4c11dd1
RK		 749
750 /*
751 * Audio input somehow depends on HDMI line rate which is
752 * related to pixclk. Testing showed that modes with pixclk
753 * >100MHz need a larger divider while <40MHz need the default.
754 * There is no detailed info in the datasheet, so we just
755 * assume 100MHz requires larger divider.
756 */
2470fecc 757 adiv = AUDIO_DIV_SERCLK_8;
c4c11dd1 758 if (mode->clock > 100000)
2470fecc
JFM		 759 adiv++; /* AUDIO_DIV_SERCLK_16 */
760
761 /* S/PDIF asks for a larger divider */
762 if (p->audio_format == AFMT_SPDIF)
763 adiv++; /* AUDIO_DIV_SERCLK_16 or _32 */
764
2f7f730a 765 reg_write(priv, REG_AUDIO_DIV, adiv);
c4c11dd1
RK		 766
767 /*
768 * This is the approximate value of N, which happens to be
769 * the recommended values for non-coherent clocks.
770 */
771 n = 128 * p->audio_sample_rate / 1000;
772
773 /* Write the CTS and N values */
774 buf[0] = 0x44;
775 buf[1] = 0x42;
776 buf[2] = 0x01;
777 buf[3] = n;
778 buf[4] = n >> 8;
779 buf[5] = n >> 16;
2f7f730a 780 reg_write_range(priv, REG_ACR_CTS_0, buf, 6);
c4c11dd1
RK		 781
782 /* Set CTS clock reference */
2f7f730a 783 reg_write(priv, REG_AIP_CLKSEL, clksel_aip | clksel_fs);
c4c11dd1
RK		 784
785 /* Reset CTS generator */
2f7f730a
JFM		 786 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
787 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS);
c4c11dd1
RK		 788
789 /* Write the channel status */
f0b33b28 790 buf[0] = IEC958_AES0_CON_NOT_COPYRIGHT;
c4c11dd1 791 buf[1] = 0x00;
f0b33b28
JFM		 792 buf[2] = IEC958_AES3_CON_FS_NOTID;
793 buf[3] = IEC958_AES4_CON_ORIGFS_NOTID |
794 IEC958_AES4_CON_MAX_WORDLEN_24;
2f7f730a 795 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4);
c4c11dd1 796
2f7f730a 797 tda998x_audio_mute(priv, true);
73d5e253 798 msleep(20);
2f7f730a 799 tda998x_audio_mute(priv, false);
c4c11dd1
RK		 800
801 /* Write the audio information packet */
2f7f730a 802 tda998x_write_aif(priv, p);
c4c11dd1
RK		 803}
804
e7792ce2
RC		 805/* DRM encoder functions */
806
a8f4d4d6
RK		 807static void tda998x_encoder_set_config(struct tda998x_priv *priv,
808 const struct tda998x_encoder_params *p)
e7792ce2 809{
c4c11dd1
RK		 810 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(p->swap_a) |
811 (p->mirr_a ? VIP_CNTRL_0_MIRR_A : 0) |
812 VIP_CNTRL_0_SWAP_B(p->swap_b) |
813 (p->mirr_b ? VIP_CNTRL_0_MIRR_B : 0);
814 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(p->swap_c) |
815 (p->mirr_c ? VIP_CNTRL_1_MIRR_C : 0) |
816 VIP_CNTRL_1_SWAP_D(p->swap_d) |
817 (p->mirr_d ? VIP_CNTRL_1_MIRR_D : 0);
818 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(p->swap_e) |
819 (p->mirr_e ? VIP_CNTRL_2_MIRR_E : 0) |
820 VIP_CNTRL_2_SWAP_F(p->swap_f) |
821 (p->mirr_f ? VIP_CNTRL_2_MIRR_F : 0);
822
823 priv->params = *p;
e7792ce2
RC		 824}
825
9525c4dd 826static void tda998x_encoder_dpms(struct drm_encoder *encoder, int mode)
e7792ce2 827{
9525c4dd
RK		 828 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
829
e7792ce2
RC		 830 /* we only care about on or off: */
831 if (mode != DRM_MODE_DPMS_ON)
832 mode = DRM_MODE_DPMS_OFF;
833
834 if (mode == priv->dpms)
835 return;
836
837 switch (mode) {
838 case DRM_MODE_DPMS_ON:
c4c11dd1 839 /* enable video ports, audio will be enabled later */
2f7f730a
JFM		 840 reg_write(priv, REG_ENA_VP_0, 0xff);
841 reg_write(priv, REG_ENA_VP_1, 0xff);
842 reg_write(priv, REG_ENA_VP_2, 0xff);
e7792ce2 843 /* set muxing after enabling ports: */
2f7f730a
JFM		 844 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0);
845 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1);
846 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2);
e7792ce2
RC		 847 break;
848 case DRM_MODE_DPMS_OFF:
db6aaf4d 849 /* disable video ports */
2f7f730a
JFM		 850 reg_write(priv, REG_ENA_VP_0, 0x00);
851 reg_write(priv, REG_ENA_VP_1, 0x00);
852 reg_write(priv, REG_ENA_VP_2, 0x00);
e7792ce2
RC		 853 break;
854 }
855
856 priv->dpms = mode;
857}
858
e7792ce2
RC		 859static bool
860tda998x_encoder_mode_fixup(struct drm_encoder *encoder,
861 const struct drm_display_mode *mode,
862 struct drm_display_mode *adjusted_mode)
863{
864 return true;
865}
866
9525c4dd
RK		 867static int tda998x_connector_mode_valid(struct drm_connector *connector,
868 struct drm_display_mode *mode)
e7792ce2 869{
e4618c46
LDA		 870 /* TDA19988 dotclock can go up to 165MHz */
871 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
872
873 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000))
92fbdfcd
RK		 874 return MODE_CLOCK_HIGH;
875 if (mode->htotal >= BIT(13))
876 return MODE_BAD_HVALUE;
877 if (mode->vtotal >= BIT(11))
878 return MODE_BAD_VVALUE;
e7792ce2
RC		 879 return MODE_OK;
880}
881
882static void
9525c4dd 883tda998x_encoder_mode_set(struct drm_encoder *encoder,
a8f4d4d6
RK		 884 struct drm_display_mode *mode,
885 struct drm_display_mode *adjusted_mode)
e7792ce2 886{
9525c4dd 887 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
e66e03ab
RK		 888 u16 ref_pix, ref_line, n_pix, n_line;
889 u16 hs_pix_s, hs_pix_e;
890 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e;
891 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e;
892 u16 vwin1_line_s, vwin1_line_e;
893 u16 vwin2_line_s, vwin2_line_e;
894 u16 de_pix_s, de_pix_e;
895 u8 reg, div, rep;
e7792ce2 896
088d61d1
SH		 897 /*
898 * Internally TDA998x is using ITU-R BT.656 style sync but
899 * we get VESA style sync. TDA998x is using a reference pixel
900 * relative to ITU to sync to the input frame and for output
901 * sync generation. Currently, we are using reference detection
902 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point
903 * which is position of rising VS with coincident rising HS.
904 *
905 * Now there is some issues to take care of:
906 * - HDMI data islands require sync-before-active
907 * - TDA998x register values must be > 0 to be enabled
908 * - REFLINE needs an additional offset of +1
909 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB
910 *
911 * So we add +1 to all horizontal and vertical register values,
912 * plus an additional +3 for REFPIX as we are using RGB input only.
e7792ce2 913 */
088d61d1
SH		 914 n_pix = mode->htotal;
915 n_line = mode->vtotal;
916
917 hs_pix_e = mode->hsync_end - mode->hdisplay;
918 hs_pix_s = mode->hsync_start - mode->hdisplay;
919 de_pix_e = mode->htotal;
920 de_pix_s = mode->htotal - mode->hdisplay;
921 ref_pix = 3 + hs_pix_s;
922
179f1aa4
SH		 923 /*
924 * Attached LCD controllers may generate broken sync. Allow
925 * those to adjust the position of the rising VS edge by adding
926 * HSKEW to ref_pix.
927 */
928 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW)
929 ref_pix += adjusted_mode->hskew;
930
088d61d1
SH		 931 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) {
932 ref_line = 1 + mode->vsync_start - mode->vdisplay;
933 vwin1_line_s = mode->vtotal - mode->vdisplay - 1;
934 vwin1_line_e = vwin1_line_s + mode->vdisplay;
935 vs1_pix_s = vs1_pix_e = hs_pix_s;
936 vs1_line_s = mode->vsync_start - mode->vdisplay;
937 vs1_line_e = vs1_line_s +
938 mode->vsync_end - mode->vsync_start;
939 vwin2_line_s = vwin2_line_e = 0;
940 vs2_pix_s = vs2_pix_e = 0;
941 vs2_line_s = vs2_line_e = 0;
942 } else {
943 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2;
944 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2;
945 vwin1_line_e = vwin1_line_s + mode->vdisplay/2;
946 vs1_pix_s = vs1_pix_e = hs_pix_s;
947 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2;
948 vs1_line_e = vs1_line_s +
949 (mode->vsync_end - mode->vsync_start)/2;
950 vwin2_line_s = vwin1_line_s + mode->vtotal/2;
951 vwin2_line_e = vwin2_line_s + mode->vdisplay/2;
952 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2;
953 vs2_line_s = vs1_line_s + mode->vtotal/2 ;
954 vs2_line_e = vs2_line_s +
955 (mode->vsync_end - mode->vsync_start)/2;
956 }
e7792ce2
RC		 957
958 div = 148500 / mode->clock;
3ae471f7
JFM		 959 if (div != 0) {
960 div--;
961 if (div > 3)
962 div = 3;
963 }
e7792ce2 964
e7792ce2 965 /* mute the audio FIFO: */
2f7f730a 966 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO);
e7792ce2
RC		 967
968 /* set HDMI HDCP mode off: */
81b53a16 969 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS);
2f7f730a
JFM		 970 reg_clear(priv, REG_TX33, TX33_HDMI);
971 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0));
e7792ce2 972
e7792ce2 973 /* no pre-filter or interpolator: */
2f7f730a 974 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) |
e7792ce2 975 HVF_CNTRL_0_INTPOL(0));
2f7f730a
JFM		 976 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0));
977 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) |
e7792ce2 978 VIP_CNTRL_4_BLC(0));
e7792ce2 979
2f7f730a 980 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ);
a8b517e5
JFM		 981 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR |
982 PLL_SERIAL_3_SRL_DE);
2f7f730a
JFM		 983 reg_write(priv, REG_SERIALIZER, 0);
984 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0));
e7792ce2
RC		 985
986 /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */
987 rep = 0;
2f7f730a
JFM		 988 reg_write(priv, REG_RPT_CNTRL, 0);
989 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) |
e7792ce2
RC		 990 SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK);
991
2f7f730a 992 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) |
e7792ce2
RC		 993 PLL_SERIAL_2_SRL_PR(rep));
994
e7792ce2 995 /* set color matrix bypass flag: */
81b53a16
JFM		 996 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP |
997 MAT_CONTRL_MAT_SC(1));
e7792ce2
RC		 998
999 /* set BIAS tmds value: */
2f7f730a 1000 reg_write(priv, REG_ANA_GENERAL, 0x09);
e7792ce2 1001
088d61d1
SH		 1002 /*
1003 * Sync on rising HSYNC/VSYNC
1004 */
81b53a16 1005 reg = VIP_CNTRL_3_SYNC_HS;
088d61d1
SH		 1006
1007 /*
1008 * TDA19988 requires high-active sync at input stage,
1009 * so invert low-active sync provided by master encoder here
1010 */
1011 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
81b53a16 1012 reg |= VIP_CNTRL_3_H_TGL;
e7792ce2 1013 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
81b53a16
JFM		 1014 reg |= VIP_CNTRL_3_V_TGL;
1015 reg_write(priv, REG_VIP_CNTRL_3, reg);
2f7f730a
JFM		 1016
1017 reg_write(priv, REG_VIDFORMAT, 0x00);
1018 reg_write16(priv, REG_REFPIX_MSB, ref_pix);
1019 reg_write16(priv, REG_REFLINE_MSB, ref_line);
1020 reg_write16(priv, REG_NPIX_MSB, n_pix);
1021 reg_write16(priv, REG_NLINE_MSB, n_line);
1022 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s);
1023 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s);
1024 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e);
1025 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e);
1026 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s);
1027 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s);
1028 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e);
1029 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e);
1030 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s);
1031 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e);
1032 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s);
1033 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e);
1034 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s);
1035 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e);
1036 reg_write16(priv, REG_DE_START_MSB, de_pix_s);
1037 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e);
e7792ce2
RC		 1038
1039 if (priv->rev == TDA19988) {
1040 /* let incoming pixels fill the active space (if any) */
2f7f730a 1041 reg_write(priv, REG_ENABLE_SPACE, 0x00);
e7792ce2
RC		 1042 }
1043
81b53a16
JFM		 1044 /*
1045 * Always generate sync polarity relative to input sync and
1046 * revert input stage toggled sync at output stage
1047 */
1048 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN;
1049 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1050 reg |= TBG_CNTRL_1_H_TGL;
1051 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1052 reg |= TBG_CNTRL_1_V_TGL;
1053 reg_write(priv, REG_TBG_CNTRL_1, reg);
1054
e7792ce2 1055 /* must be last register set: */
81b53a16 1056 reg_write(priv, REG_TBG_CNTRL_0, 0);
c4c11dd1
RK		 1057
1058 /* Only setup the info frames if the sink is HDMI */
1059 if (priv->is_hdmi_sink) {
1060 /* We need to turn HDMI HDCP stuff on to get audio through */
81b53a16
JFM		 1061 reg &= ~TBG_CNTRL_1_DWIN_DIS;
1062 reg_write(priv, REG_TBG_CNTRL_1, reg);
2f7f730a
JFM		 1063 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1));
1064 reg_set(priv, REG_TX33, TX33_HDMI);
c4c11dd1 1065
2f7f730a 1066 tda998x_write_avi(priv, adjusted_mode);
c4c11dd1
RK		 1067
1068 if (priv->params.audio_cfg)
2f7f730a 1069 tda998x_configure_audio(priv, adjusted_mode,
c4c11dd1
RK		 1070 &priv->params);
1071 }
e7792ce2
RC		 1072}
1073
1074static enum drm_connector_status
9525c4dd 1075tda998x_connector_detect(struct drm_connector *connector, bool force)
e7792ce2 1076{
9525c4dd 1077 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
e66e03ab 1078 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV);
2f7f730a 1079
e7792ce2
RC		 1080 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected :
1081 connector_status_disconnected;
1082}
1083
07259f8b 1084static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length)
e7792ce2 1085{
07259f8b 1086 struct tda998x_priv *priv = data;
e66e03ab 1087 u8 offset, segptr;
e7792ce2
RC		 1088 int ret, i;
1089
e7792ce2
RC		 1090 offset = (blk & 1) ? 128 : 0;
1091 segptr = blk / 2;
1092
2f7f730a
JFM		 1093 reg_write(priv, REG_DDC_ADDR, 0xa0);
1094 reg_write(priv, REG_DDC_OFFS, offset);
1095 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60);
1096 reg_write(priv, REG_DDC_SEGM, segptr);
e7792ce2
RC		 1097
1098 /* enable reading EDID: */
12473b7d 1099 priv->wq_edid_wait = 1;
2f7f730a 1100 reg_write(priv, REG_EDID_CTRL, 0x1);
e7792ce2
RC		 1101
1102 /* flag must be cleared by sw: */
2f7f730a 1103 reg_write(priv, REG_EDID_CTRL, 0x0);
e7792ce2
RC		 1104
1105 /* wait for block read to complete: */
12473b7d
JFM		 1106 if (priv->hdmi->irq) {
1107 i = wait_event_timeout(priv->wq_edid,
1108 !priv->wq_edid_wait,
1109 msecs_to_jiffies(100));
1110 if (i < 0) {
5e7fe2fe 1111 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i);
12473b7d
JFM		 1112 return i;
1113 }
1114 } else {
713456db
RK		 1115 for (i = 100; i > 0; i--) {
1116 msleep(1);
12473b7d
JFM		 1117 ret = reg_read(priv, REG_INT_FLAGS_2);
1118 if (ret < 0)
1119 return ret;
1120 if (ret & INT_FLAGS_2_EDID_BLK_RD)
1121 break;
1122 }
e7792ce2
RC		 1123 }
1124
12473b7d 1125 if (i == 0) {
5e7fe2fe 1126 dev_err(&priv->hdmi->dev, "read edid timeout\n");
e7792ce2 1127 return -ETIMEDOUT;
12473b7d 1128 }
e7792ce2 1129
07259f8b
LP		 1130 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length);
1131 if (ret != length) {
5e7fe2fe
RK		 1132 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n",
1133 blk, ret);
e7792ce2
RC		 1134 return ret;
1135 }
1136
e7792ce2
RC		 1137 return 0;
1138}
1139
9525c4dd 1140static int tda998x_connector_get_modes(struct drm_connector *connector)
e7792ce2 1141{
9525c4dd 1142 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
07259f8b
LP		 1143 struct edid *edid;
1144 int n;
e7792ce2 1145
0fc6f44d
RK		 1146 /*
1147 * If we get killed while waiting for the HPD timeout, return
1148 * no modes found: we are not in a restartable path, so we
1149 * can't handle signals gracefully.
1150 */
1151 if (tda998x_edid_delay_wait(priv))
1152 return 0;
1153
063b472f 1154 if (priv->rev == TDA19988)
2f7f730a 1155 reg_clear(priv, REG_TX4, TX4_PD_RAM);
063b472f 1156
07259f8b 1157 edid = drm_do_get_edid(connector, read_edid_block, priv);
e7792ce2 1158
063b472f 1159 if (priv->rev == TDA19988)
2f7f730a 1160 reg_set(priv, REG_TX4, TX4_PD_RAM);
063b472f 1161
07259f8b
LP		 1162 if (!edid) {
1163 dev_warn(&priv->hdmi->dev, "failed to read EDID\n");
1164 return 0;
e7792ce2
RC		 1165 }
1166
07259f8b
LP		 1167 drm_mode_connector_update_edid_property(connector, edid);
1168 n = drm_add_edid_modes(connector, edid);
1169 priv->is_hdmi_sink = drm_detect_hdmi_monitor(edid);
1170 kfree(edid);
1171
e7792ce2
RC		 1172 return n;
1173}
1174
a8f4d4d6
RK		 1175static void tda998x_encoder_set_polling(struct tda998x_priv *priv,
1176 struct drm_connector *connector)
e7792ce2 1177{
12473b7d
JFM		 1178 if (priv->hdmi->irq)
1179 connector->polled = DRM_CONNECTOR_POLL_HPD;
1180 else
1181 connector->polled = DRM_CONNECTOR_POLL_CONNECT |
1182 DRM_CONNECTOR_POLL_DISCONNECT;
e7792ce2
RC		 1183}
1184
a8f4d4d6 1185static void tda998x_destroy(struct tda998x_priv *priv)
e7792ce2 1186{
12473b7d
JFM		 1187 /* disable all IRQs and free the IRQ handler */
1188 cec_write(priv, REG_CEC_RXSHPDINTENA, 0);
1189 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
0fc6f44d
RK		 1190
1191 if (priv->hdmi->irq)
12473b7d 1192 free_irq(priv->hdmi->irq, priv);
0fc6f44d
RK		 1193
1194 del_timer_sync(&priv->edid_delay_timer);
1195 cancel_work_sync(&priv->detect_work);
12473b7d 1196
89fc8686 1197 i2c_unregister_device(priv->cec);
a8f4d4d6
RK		 1198}
1199
e7792ce2
RC		 1200/* I2C driver functions */
1201
a8f4d4d6 1202static int tda998x_create(struct i2c_client *client, struct tda998x_priv *priv)
e7792ce2 1203{
0d44ea19
JFM		 1204 struct device_node *np = client->dev.of_node;
1205 u32 video;
fb7544d7 1206 int rev_lo, rev_hi, ret;
cfe38757 1207 unsigned short cec_addr;
e7792ce2 1208
5e74c22c
RK		 1209 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3);
1210 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1);
1211 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5);
1212
2eb4c7b1 1213 priv->current_page = 0xff;
2f7f730a 1214 priv->hdmi = client;
cfe38757
AJ		 1215 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */
1216 cec_addr = 0x34 + (client->addr & 0x03);
1217 priv->cec = i2c_new_dummy(client->adapter, cec_addr);
a8f4d4d6 1218 if (!priv->cec)
6ae668cc 1219 return -ENODEV;
12473b7d 1220
e7792ce2
RC		 1221 priv->dpms = DRM_MODE_DPMS_OFF;
1222
ed9a8426 1223 mutex_init(&priv->mutex); /* protect the page access */
0fc6f44d
RK		 1224 init_waitqueue_head(&priv->edid_delay_waitq);
1225 setup_timer(&priv->edid_delay_timer, tda998x_edid_delay_done,
1226 (unsigned long)priv);
1227 INIT_WORK(&priv->detect_work, tda998x_detect_work);
ed9a8426 1228
e7792ce2 1229 /* wake up the device: */
2f7f730a 1230 cec_write(priv, REG_CEC_ENAMODS,
e7792ce2
RC		 1231 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI);
1232
2f7f730a 1233 tda998x_reset(priv);
e7792ce2
RC		 1234
1235 /* read version: */
fb7544d7
RK		 1236 rev_lo = reg_read(priv, REG_VERSION_LSB);
1237 rev_hi = reg_read(priv, REG_VERSION_MSB);
1238 if (rev_lo < 0 || rev_hi < 0) {
1239 ret = rev_lo < 0 ? rev_lo : rev_hi;
7d2eadc9 1240 goto fail;
fb7544d7
RK		 1241 }
1242
1243 priv->rev = rev_lo | rev_hi << 8;
e7792ce2
RC		 1244
1245 /* mask off feature bits: */
1246 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */
1247
1248 switch (priv->rev) {
b728fab7
JFM		 1249 case TDA9989N2:
1250 dev_info(&client->dev, "found TDA9989 n2");
1251 break;
1252 case TDA19989:
1253 dev_info(&client->dev, "found TDA19989");
1254 break;
1255 case TDA19989N2:
1256 dev_info(&client->dev, "found TDA19989 n2");
1257 break;
1258 case TDA19988:
1259 dev_info(&client->dev, "found TDA19988");
1260 break;
e7792ce2 1261 default:
b728fab7
JFM		 1262 dev_err(&client->dev, "found unsupported device: %04x\n",
1263 priv->rev);
e7792ce2
RC		 1264 goto fail;
1265 }
1266
1267 /* after reset, enable DDC: */
2f7f730a 1268 reg_write(priv, REG_DDC_DISABLE, 0x00);
e7792ce2
RC		 1269
1270 /* set clock on DDC channel: */
2f7f730a 1271 reg_write(priv, REG_TX3, 39);
e7792ce2
RC		 1272
1273 /* if necessary, disable multi-master: */
1274 if (priv->rev == TDA19989)
2f7f730a 1275 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM);
e7792ce2 1276
2f7f730a 1277 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL,
e7792ce2
RC		 1278 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL);
1279
12473b7d
JFM		 1280 /* initialize the optional IRQ */
1281 if (client->irq) {
1282 int irqf_trigger;
1283
6833d26e 1284 /* init read EDID waitqueue and HDP work */
12473b7d
JFM		 1285 init_waitqueue_head(&priv->wq_edid);
1286
1287 /* clear pending interrupts */
1288 reg_read(priv, REG_INT_FLAGS_0);
1289 reg_read(priv, REG_INT_FLAGS_1);
1290 reg_read(priv, REG_INT_FLAGS_2);
1291
1292 irqf_trigger =
1293 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1294 ret = request_threaded_irq(client->irq, NULL,
1295 tda998x_irq_thread,
1296 irqf_trigger | IRQF_ONESHOT,
1297 "tda998x", priv);
1298 if (ret) {
1299 dev_err(&client->dev,
1300 "failed to request IRQ#%u: %d\n",
1301 client->irq, ret);
1302 goto fail;
1303 }
1304
1305 /* enable HPD irq */
1306 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD);
1307 }
1308
e4782627
JFM		 1309 /* enable EDID read irq: */
1310 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD);
1311
0d44ea19
JFM		 1312 if (!np)
1313 return 0; /* non-DT */
1314
1315 /* get the optional video properties */
1316 ret = of_property_read_u32(np, "video-ports", &video);
1317 if (ret == 0) {
1318 priv->vip_cntrl_0 = video >> 16;
1319 priv->vip_cntrl_1 = video >> 8;
1320 priv->vip_cntrl_2 = video;
1321 }
1322
e7792ce2
RC		 1323 return 0;
1324
1325fail:
1326 /* if encoder_init fails, the encoder slave is never registered,
1327 * so cleanup here:
1328 */
1329 if (priv->cec)
1330 i2c_unregister_device(priv->cec);
e7792ce2
RC		 1331 return -ENXIO;
1332}
1333
c707c361
RK		 1334static void tda998x_encoder_prepare(struct drm_encoder *encoder)
1335{
9525c4dd 1336 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
c707c361
RK		 1337}
1338
1339static void tda998x_encoder_commit(struct drm_encoder *encoder)
1340{
9525c4dd 1341 tda998x_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
c707c361
RK		 1342}
1343
1344static const struct drm_encoder_helper_funcs tda998x_encoder_helper_funcs = {
9525c4dd 1345 .dpms = tda998x_encoder_dpms,
c707c361
RK		 1346 .mode_fixup = tda998x_encoder_mode_fixup,
1347 .prepare = tda998x_encoder_prepare,
1348 .commit = tda998x_encoder_commit,
9525c4dd 1349 .mode_set = tda998x_encoder_mode_set,
c707c361
RK		 1350};
1351
1352static void tda998x_encoder_destroy(struct drm_encoder *encoder)
1353{
a3584f60 1354 struct tda998x_priv *priv = enc_to_tda998x_priv(encoder);
c707c361 1355
a3584f60 1356 tda998x_destroy(priv);
c707c361
RK		 1357 drm_encoder_cleanup(encoder);
1358}
1359
1360static const struct drm_encoder_funcs tda998x_encoder_funcs = {
1361 .destroy = tda998x_encoder_destroy,
1362};
1363
c707c361
RK		 1364static struct drm_encoder *
1365tda998x_connector_best_encoder(struct drm_connector *connector)
1366{
a3584f60 1367 struct tda998x_priv *priv = conn_to_tda998x_priv(connector);
c707c361 1368
a3584f60 1369 return &priv->encoder;
c707c361
RK		 1370}
1371
1372static
1373const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = {
1374 .get_modes = tda998x_connector_get_modes,
1375 .mode_valid = tda998x_connector_mode_valid,
1376 .best_encoder = tda998x_connector_best_encoder,
1377};
1378
c707c361
RK		 1379static void tda998x_connector_destroy(struct drm_connector *connector)
1380{
74cd62ea 1381 drm_connector_unregister(connector);
c707c361
RK		 1382 drm_connector_cleanup(connector);
1383}
1384
1385static const struct drm_connector_funcs tda998x_connector_funcs = {
9736e988
LDA		 1386 .dpms = drm_atomic_helper_connector_dpms,
1387 .reset = drm_atomic_helper_connector_reset,
c707c361
RK		 1388 .fill_modes = drm_helper_probe_single_connector_modes,
1389 .detect = tda998x_connector_detect,
1390 .destroy = tda998x_connector_destroy,
9736e988
LDA		 1391 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1392 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
c707c361
RK		 1393};
1394
1395static int tda998x_bind(struct device *dev, struct device *master, void *data)
1396{
1397 struct tda998x_encoder_params *params = dev->platform_data;
1398 struct i2c_client *client = to_i2c_client(dev);
1399 struct drm_device *drm = data;
a3584f60 1400 struct tda998x_priv *priv;
e66e03ab 1401 u32 crtcs = 0;
c707c361
RK		 1402 int ret;
1403
1404 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1405 if (!priv)
1406 return -ENOMEM;
1407
1408 dev_set_drvdata(dev, priv);
1409
5dbcf319
RK		 1410 if (dev->of_node)
1411 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
1412
1413 /* If no CRTCs were found, fall back to our old behaviour */
1414 if (crtcs == 0) {
1415 dev_warn(dev, "Falling back to first CRTC\n");
1416 crtcs = 1 << 0;
1417 }
1418
a3584f60
RK		 1419 priv->connector.interlace_allowed = 1;
1420 priv->encoder.possible_crtcs = crtcs;
c707c361 1421
a3584f60 1422 ret = tda998x_create(client, priv);
c707c361
RK		 1423 if (ret)
1424 return ret;
1425
1426 if (!dev->of_node && params)
a3584f60 1427 tda998x_encoder_set_config(priv, params);
c707c361 1428
a3584f60 1429 tda998x_encoder_set_polling(priv, &priv->connector);
c707c361 1430
a3584f60
RK		 1431 drm_encoder_helper_add(&priv->encoder, &tda998x_encoder_helper_funcs);
1432 ret = drm_encoder_init(drm, &priv->encoder, &tda998x_encoder_funcs,
13a3d91f 1433 DRM_MODE_ENCODER_TMDS, NULL);
c707c361
RK		 1434 if (ret)
1435 goto err_encoder;
1436
a3584f60 1437 drm_connector_helper_add(&priv->connector,
c707c361 1438 &tda998x_connector_helper_funcs);
a3584f60 1439 ret = drm_connector_init(drm, &priv->connector,
c707c361
RK		 1440 &tda998x_connector_funcs,
1441 DRM_MODE_CONNECTOR_HDMIA);
1442 if (ret)
1443 goto err_connector;
1444
a3584f60 1445 ret = drm_connector_register(&priv->connector);
c707c361
RK		 1446 if (ret)
1447 goto err_sysfs;
1448
a3584f60 1449 drm_mode_connector_attach_encoder(&priv->connector, &priv->encoder);
c707c361
RK		 1450
1451 return 0;
1452
1453err_sysfs:
a3584f60 1454 drm_connector_cleanup(&priv->connector);
c707c361 1455err_connector:
a3584f60 1456 drm_encoder_cleanup(&priv->encoder);
c707c361 1457err_encoder:
a3584f60 1458 tda998x_destroy(priv);
c707c361
RK		 1459 return ret;
1460}
1461
1462static void tda998x_unbind(struct device *dev, struct device *master,
1463 void *data)
1464{
a3584f60 1465 struct tda998x_priv *priv = dev_get_drvdata(dev);
c707c361 1466
debd15ce 1467 drm_connector_unregister(&priv->connector);
a3584f60
RK		 1468 drm_connector_cleanup(&priv->connector);
1469 drm_encoder_cleanup(&priv->encoder);
1470 tda998x_destroy(priv);
c707c361
RK		 1471}
1472
1473static const struct component_ops tda998x_ops = {
1474 .bind = tda998x_bind,
1475 .unbind = tda998x_unbind,
1476};
1477
1478static int
1479tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id)
1480{
1481 return component_add(&client->dev, &tda998x_ops);
1482}
1483
1484static int tda998x_remove(struct i2c_client *client)
1485{
1486 component_del(&client->dev, &tda998x_ops);
1487 return 0;
1488}
1489
0d44ea19
JFM		 1490#ifdef CONFIG_OF
1491static const struct of_device_id tda998x_dt_ids[] = {
1492 { .compatible = "nxp,tda998x", },
1493 { }
1494};
1495MODULE_DEVICE_TABLE(of, tda998x_dt_ids);
1496#endif
1497
e7792ce2
RC		 1498static struct i2c_device_id tda998x_ids[] = {
1499 { "tda998x", 0 },
1500 { }
1501};
1502MODULE_DEVICE_TABLE(i2c, tda998x_ids);
1503
3d58e318
RK		 1504static struct i2c_driver tda998x_driver = {
1505 .probe = tda998x_probe,
1506 .remove = tda998x_remove,
1507 .driver = {
1508 .name = "tda998x",
1509 .of_match_table = of_match_ptr(tda998x_dt_ids),
e7792ce2 1510 },
3d58e318 1511 .id_table = tda998x_ids,
e7792ce2
RC		 1512};
1513
3d58e318 1514module_i2c_driver(tda998x_driver);
e7792ce2
RC		 1515
1516MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
1517MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder");
1518MODULE_LICENSE("GPL");