[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpu / drm / gma500 / psb_device.c

/**************************************************************************
 * Copyright (c) 2011, Intel Corporation.
 * All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program; if not, write to the Free Software Foundation, Inc.,
 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
 *
 **************************************************************************/

#include <linux/backlight.h>
#include <drm/drmP.h>
#include <drm/drm.h>
#include <drm/gma_drm.h>
#include "psb_drv.h"
#include "psb_reg.h"
#include "psb_intel_reg.h"
#include "intel_bios.h"


static int psb_output_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	psb_intel_lvds_init(dev, &dev_priv->mode_dev);
	psb_intel_sdvo_init(dev, SDVOB);
	return 0;
}

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE

/*
 *	Poulsbo Backlight Interfaces
 */

#define BLC_PWM_PRECISION_FACTOR 100	/* 10000000 */
#define BLC_PWM_FREQ_CALC_CONSTANT 32
#define MHz 1000000

#define PSB_BLC_PWM_PRECISION_FACTOR    10
#define PSB_BLC_MAX_PWM_REG_FREQ        0xFFFE
#define PSB_BLC_MIN_PWM_REG_FREQ        0x2

#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
#define PSB_BACKLIGHT_PWM_CTL_SHIFT	(16)

static int psb_brightness;
static struct backlight_device *psb_backlight_device;

static int psb_get_brightness(struct backlight_device *bd)
{
	/* return locally cached var instead of HW read (due to DPST etc.) */
	/* FIXME: ideally return actual value in case firmware fiddled with
	   it */
	return psb_brightness;
}


static int psb_backlight_setup(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	unsigned long core_clock;
	/* u32 bl_max_freq; */
	/* unsigned long value; */
	u16 bl_max_freq;
	uint32_t value;
	uint32_t blc_pwm_precision_factor;

	/* get bl_max_freq and pol from dev_priv*/
	if (!dev_priv->lvds_bl) {
		dev_err(dev->dev, "Has no valid LVDS backlight info\n");
		return -ENOENT;
	}
	bl_max_freq = dev_priv->lvds_bl->freq;
	blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;

	core_clock = dev_priv->core_freq;

	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
	value *= blc_pwm_precision_factor;
	value /= bl_max_freq;
	value /= blc_pwm_precision_factor;

	if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
		 value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
				return -ERANGE;
	else {
		value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
		REG_WRITE(BLC_PWM_CTL,
			(value << PSB_BACKLIGHT_PWM_CTL_SHIFT) | (value));
	}
	return 0;
}

static int psb_set_brightness(struct backlight_device *bd)
{
	struct drm_device *dev = bl_get_data(psb_backlight_device);
	int level = bd->props.brightness;

	/* Percentage 1-100% being valid */
	if (level < 1)
		level = 1;

	psb_intel_lvds_set_brightness(dev, level);
	psb_brightness = level;
	return 0;
}

static const struct backlight_ops psb_ops = {
	.get_brightness = psb_get_brightness,
	.update_status  = psb_set_brightness,
};

static int psb_backlight_init(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	int ret;
	struct backlight_properties props;

	memset(&props, 0, sizeof(struct backlight_properties));
	props.max_brightness = 100;
	props.type = BACKLIGHT_PLATFORM;

	psb_backlight_device = backlight_device_register("psb-bl",
					NULL, (void *)dev, &psb_ops, &props);
	if (IS_ERR(psb_backlight_device))
		return PTR_ERR(psb_backlight_device);

	ret = psb_backlight_setup(dev);
	if (ret < 0) {
		backlight_device_unregister(psb_backlight_device);
		psb_backlight_device = NULL;
		return ret;
	}
	psb_backlight_device->props.brightness = 100;
	psb_backlight_device->props.max_brightness = 100;
	backlight_update_status(psb_backlight_device);
	dev_priv->backlight_device = psb_backlight_device;

	/* This must occur after the backlight is properly initialised */
	psb_lid_timer_init(dev_priv);

	return 0;
}

#endif

/*
 *	Provide the Poulsbo specific chip logic and low level methods
 *	for power management
 */

static void psb_init_pm(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;

	u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
	gating &= ~3;	/* Disable 2D clock gating */
	gating |= 1;
	PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
	PSB_RSGX32(PSB_CR_CLKGATECTL);
}

/**
 *	psb_save_display_registers	-	save registers lost on suspend
 *	@dev: our DRM device
 *
 *	Save the state we need in order to be able to restore the interface
 *	upon resume from suspend
 */
static int psb_save_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	struct drm_connector *connector;
	struct psb_state *regs = &dev_priv->regs.psb;

	/* Display arbitration control + watermarks */
	regs->saveDSPARB = PSB_RVDC32(DSPARB);
	regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
	regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
	regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
	regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
	regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
	regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
	regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);

	/* Save crtc and output state */
	mutex_lock(&dev->mode_config.mutex);
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
		if (drm_helper_crtc_in_use(crtc))
			crtc->funcs->save(crtc);
	}

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		if (connector->funcs->save)
			connector->funcs->save(connector);

	mutex_unlock(&dev->mode_config.mutex);
	return 0;
}

/**
 *	psb_restore_display_registers	-	restore lost register state
 *	@dev: our DRM device
 *
 *	Restore register state that was lost during suspend and resume.
 */
static int psb_restore_display_registers(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	struct drm_crtc *crtc;
	struct drm_connector *connector;
	struct psb_state *regs = &dev_priv->regs.psb;

	/* Display arbitration + watermarks */
	PSB_WVDC32(regs->saveDSPARB, DSPARB);
	PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
	PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
	PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
	PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
	PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
	PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
	PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);

	/*make sure VGA plane is off. it initializes to on after reset!*/
	PSB_WVDC32(0x80000000, VGACNTRL);

	mutex_lock(&dev->mode_config.mutex);
	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
		if (drm_helper_crtc_in_use(crtc))
			crtc->funcs->restore(crtc);

	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
		if (connector->funcs->restore)
			connector->funcs->restore(connector);

	mutex_unlock(&dev->mode_config.mutex);
	return 0;
}

static int psb_power_down(struct drm_device *dev)
{
	return 0;
}

static int psb_power_up(struct drm_device *dev)
{
	return 0;
}

static void psb_get_core_freq(struct drm_device *dev)
{
	uint32_t clock;
	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	struct drm_psb_private *dev_priv = dev->dev_private;

	/*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
	/*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/

	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	pci_read_config_dword(pci_root, 0xD4, &clock);
	pci_dev_put(pci_root);

	switch (clock & 0x07) {
	case 0:
		dev_priv->core_freq = 100;
		break;
	case 1:
		dev_priv->core_freq = 133;
		break;
	case 2:
		dev_priv->core_freq = 150;
		break;
	case 3:
		dev_priv->core_freq = 178;
		break;
	case 4:
		dev_priv->core_freq = 200;
		break;
	case 5:
	case 6:
	case 7:
		dev_priv->core_freq = 266;
	default:
		dev_priv->core_freq = 0;
	}
}

/* Poulsbo */
static const struct psb_offset psb_regmap[2] = {
	{
		.fp0 = FPA0,
		.fp1 = FPA1,
		.cntr = DSPACNTR,
		.conf = PIPEACONF,
		.src = PIPEASRC,
		.dpll = DPLL_A,
		.htotal = HTOTAL_A,
		.hblank = HBLANK_A,
		.hsync = HSYNC_A,
		.vtotal = VTOTAL_A,
		.vblank = VBLANK_A,
		.vsync = VSYNC_A,
		.stride = DSPASTRIDE,
		.size = DSPASIZE,
		.pos = DSPAPOS,
		.base = DSPABASE,
		.surf = DSPASURF,
		.addr = DSPABASE,
		.status = PIPEASTAT,
		.linoff = DSPALINOFF,
		.tileoff = DSPATILEOFF,
		.palette = PALETTE_A,
	},
	{
		.fp0 = FPB0,
		.fp1 = FPB1,
		.cntr = DSPBCNTR,
		.conf = PIPEBCONF,
		.src = PIPEBSRC,
		.dpll = DPLL_B,
		.htotal = HTOTAL_B,
		.hblank = HBLANK_B,
		.hsync = HSYNC_B,
		.vtotal = VTOTAL_B,
		.vblank = VBLANK_B,
		.vsync = VSYNC_B,
		.stride = DSPBSTRIDE,
		.size = DSPBSIZE,
		.pos = DSPBPOS,
		.base = DSPBBASE,
		.surf = DSPBSURF,
		.addr = DSPBBASE,
		.status = PIPEBSTAT,
		.linoff = DSPBLINOFF,
		.tileoff = DSPBTILEOFF,
		.palette = PALETTE_B,
	}
};

static int psb_chip_setup(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	dev_priv->regmap = psb_regmap;
	psb_get_core_freq(dev);
	gma_intel_setup_gmbus(dev);
	psb_intel_opregion_init(dev);
	psb_intel_init_bios(dev);
	return 0;
}

static void psb_chip_teardown(struct drm_device *dev)
{
	struct drm_psb_private *dev_priv = dev->dev_private;
	psb_lid_timer_takedown(dev_priv);
	gma_intel_teardown_gmbus(dev);
}

const struct psb_ops psb_chip_ops = {
	.name = "Poulsbo",
	.accel_2d = 1,
	.pipes = 2,
	.crtcs = 2,
	.hdmi_mask = (1 << 0),
	.lvds_mask = (1 << 1),
	.cursor_needs_phys = 1,
	.sgx_offset = PSB_SGX_OFFSET,
	.chip_setup = psb_chip_setup,
	.chip_teardown = psb_chip_teardown,

	.crtc_helper = &psb_intel_helper_funcs,
	.crtc_funcs = &psb_intel_crtc_funcs,

	.output_init = psb_output_init,

#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	.backlight_init = psb_backlight_init,
#endif

	.init_pm = psb_init_pm,
	.save_regs = psb_save_display_registers,
	.restore_regs = psb_restore_display_registers,
	.power_down = psb_power_down,
	.power_up = psb_power_up,
};
Commit	Line	Data
89c78134 AC	1	/**************************************************************************
	2	* Copyright (c) 2011, Intel Corporation.
	3	* All Rights Reserved.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms and conditions of the GNU General Public License,
	7	* version 2, as published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope it will be useful, but WITHOUT
	10	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	11	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	12	* more details.
	13	*
	14	* You should have received a copy of the GNU General Public License along with
	15	* this program; if not, write to the Free Software Foundation, Inc.,
	16	* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	17	*
	18	**************************************************************************/
	19
	20	#include <linux/backlight.h>
	21	#include <drm/drmP.h>
	22	#include <drm/drm.h>
760285e7	23	#include <drm/gma_drm.h>
89c78134 AC	24	#include "psb_drv.h"
	25	#include "psb_reg.h"
	26	#include "psb_intel_reg.h"
	27	#include "intel_bios.h"
	28
	29
	30	static int psb_output_init(struct drm_device *dev)
	31	{
	32	struct drm_psb_private *dev_priv = dev->dev_private;
	33	psb_intel_lvds_init(dev, &dev_priv->mode_dev);
	34	psb_intel_sdvo_init(dev, SDVOB);
	35	return 0;
	36	}
	37
	38	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	39
	40	/*
	41	* Poulsbo Backlight Interfaces
	42	*/
	43
	44	#define BLC_PWM_PRECISION_FACTOR 100 /* 10000000 */
	45	#define BLC_PWM_FREQ_CALC_CONSTANT 32
	46	#define MHz 1000000
	47
	48	#define PSB_BLC_PWM_PRECISION_FACTOR 10
	49	#define PSB_BLC_MAX_PWM_REG_FREQ 0xFFFE
	50	#define PSB_BLC_MIN_PWM_REG_FREQ 0x2
	51
	52	#define PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR (0xFFFE)
	53	#define PSB_BACKLIGHT_PWM_CTL_SHIFT (16)
	54
	55	static int psb_brightness;
	56	static struct backlight_device *psb_backlight_device;
	57
	58	static int psb_get_brightness(struct backlight_device *bd)
	59	{
	60	/* return locally cached var instead of HW read (due to DPST etc.) */
	61	/* FIXME: ideally return actual value in case firmware fiddled with
	62	it */
	63	return psb_brightness;
	64	}
	65
	66
	67	static int psb_backlight_setup(struct drm_device *dev)
	68	{
	69	struct drm_psb_private *dev_priv = dev->dev_private;
	70	unsigned long core_clock;
	71	/* u32 bl_max_freq; */
	72	/* unsigned long value; */
	73	u16 bl_max_freq;
	74	uint32_t value;
	75	uint32_t blc_pwm_precision_factor;
	76
	77	/* get bl_max_freq and pol from dev_priv*/
	78	if (!dev_priv->lvds_bl) {
	79	dev_err(dev->dev, "Has no valid LVDS backlight info\n");
	80	return -ENOENT;
	81	}
	82	bl_max_freq = dev_priv->lvds_bl->freq;
	83	blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
	84
	85	core_clock = dev_priv->core_freq;
	86
	87	value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT;
88	value *= blc_pwm_precision_factor;
89	value /= bl_max_freq;
90	value /= blc_pwm_precision_factor;
91
92	if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ \|\|
93	value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
94	return -ERANGE;
95	else {
96	value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
97	REG_WRITE(BLC_PWM_CTL,
98	(value << PSB_BACKLIGHT_PWM_CTL_SHIFT) \| (value));
99	}
100	return 0;
101	}
102
103	static int psb_set_brightness(struct backlight_device *bd)
104	{
105	struct drm_device *dev = bl_get_data(psb_backlight_device);
106	int level = bd->props.brightness;
107
108	/* Percentage 1-100% being valid */
109	if (level < 1)
110	level = 1;
111
112	psb_intel_lvds_set_brightness(dev, level);
113	psb_brightness = level;
114	return 0;
115	}
116
117	static const struct backlight_ops psb_ops = {
118	.get_brightness = psb_get_brightness,
119	.update_status = psb_set_brightness,
120	};
121
122	static int psb_backlight_init(struct drm_device *dev)
123	{
124	struct drm_psb_private *dev_priv = dev->dev_private;
125	int ret;
126	struct backlight_properties props;
127
128	memset(&props, 0, sizeof(struct backlight_properties));
129	props.max_brightness = 100;
130	props.type = BACKLIGHT_PLATFORM;
131
132	psb_backlight_device = backlight_device_register("psb-bl",
133	NULL, (void *)dev, &psb_ops, &props);
134	if (IS_ERR(psb_backlight_device))
135	return PTR_ERR(psb_backlight_device);
136
137	ret = psb_backlight_setup(dev);
138	if (ret < 0) {
139	backlight_device_unregister(psb_backlight_device);
140	psb_backlight_device = NULL;
141	return ret;
142	}
143	psb_backlight_device->props.brightness = 100;
144	psb_backlight_device->props.max_brightness = 100;
145	backlight_update_status(psb_backlight_device);
146	dev_priv->backlight_device = psb_backlight_device;
f507598b AC	147
	148	/* This must occur after the backlight is properly initialised */
	149	psb_lid_timer_init(dev_priv);
	150
89c78134 AC	151	return 0;
	152	}
	153
	154	#endif
	155
	156	/*
	157	* Provide the Poulsbo specific chip logic and low level methods
	158	* for power management
	159	*/
	160
	161	static void psb_init_pm(struct drm_device *dev)
	162	{
	163	struct drm_psb_private *dev_priv = dev->dev_private;
	164
	165	u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
	166	gating &= ~3; /* Disable 2D clock gating */
	167	gating \|= 1;
	168	PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
	169	PSB_RSGX32(PSB_CR_CLKGATECTL);
	170	}
	171
	172	/**
	173	* psb_save_display_registers - save registers lost on suspend
	174	* @dev: our DRM device
	175	*
	176	* Save the state we need in order to be able to restore the interface
	177	* upon resume from suspend
	178	*/
	179	static int psb_save_display_registers(struct drm_device *dev)
	180	{
	181	struct drm_psb_private *dev_priv = dev->dev_private;
	182	struct drm_crtc *crtc;
	183	struct drm_connector *connector;
c6265ff5	184	struct psb_state *regs = &dev_priv->regs.psb;
89c78134 AC	185
89c78134 AC	186	/* Display arbitration control + watermarks */
648a8e34 AC	187	regs->saveDSPARB = PSB_RVDC32(DSPARB);
	188	regs->saveDSPFW1 = PSB_RVDC32(DSPFW1);
	189	regs->saveDSPFW2 = PSB_RVDC32(DSPFW2);
	190	regs->saveDSPFW3 = PSB_RVDC32(DSPFW3);
	191	regs->saveDSPFW4 = PSB_RVDC32(DSPFW4);
	192	regs->saveDSPFW5 = PSB_RVDC32(DSPFW5);
	193	regs->saveDSPFW6 = PSB_RVDC32(DSPFW6);
	194	regs->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
89c78134 AC	195
	196	/* Save crtc and output state */
	197	mutex_lock(&dev->mode_config.mutex);
	198	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
	199	if (drm_helper_crtc_in_use(crtc))
	200	crtc->funcs->save(crtc);
	201	}
	202
	203	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
7beff62e AC	204	if (connector->funcs->save)
7beff62e AC	205	connector->funcs->save(connector);
89c78134 AC	206
	207	mutex_unlock(&dev->mode_config.mutex);
	208	return 0;
	209	}
	210
	211	/**
	212	* psb_restore_display_registers - restore lost register state
	213	* @dev: our DRM device
	214	*
	215	* Restore register state that was lost during suspend and resume.
	216	*/
	217	static int psb_restore_display_registers(struct drm_device *dev)
	218	{
	219	struct drm_psb_private *dev_priv = dev->dev_private;
	220	struct drm_crtc *crtc;
	221	struct drm_connector *connector;
c6265ff5	222	struct psb_state *regs = &dev_priv->regs.psb;
89c78134 AC	223
89c78134 AC	224	/* Display arbitration + watermarks */
648a8e34 AC	225	PSB_WVDC32(regs->saveDSPARB, DSPARB);
	226	PSB_WVDC32(regs->saveDSPFW1, DSPFW1);
	227	PSB_WVDC32(regs->saveDSPFW2, DSPFW2);
	228	PSB_WVDC32(regs->saveDSPFW3, DSPFW3);
	229	PSB_WVDC32(regs->saveDSPFW4, DSPFW4);
	230	PSB_WVDC32(regs->saveDSPFW5, DSPFW5);
	231	PSB_WVDC32(regs->saveDSPFW6, DSPFW6);
	232	PSB_WVDC32(regs->saveCHICKENBIT, DSPCHICKENBIT);
89c78134 AC	233
	234	/make sure VGA plane is off. it initializes to on after reset!/
	235	PSB_WVDC32(0x80000000, VGACNTRL);
	236
	237	mutex_lock(&dev->mode_config.mutex);
	238	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
	239	if (drm_helper_crtc_in_use(crtc))
	240	crtc->funcs->restore(crtc);
	241
	242	list_for_each_entry(connector, &dev->mode_config.connector_list, head)
7beff62e AC	243	if (connector->funcs->restore)
7beff62e AC	244	connector->funcs->restore(connector);
89c78134 AC	245
89c78134 AC	246	mutex_unlock(&dev->mode_config.mutex);
89c78134 AC	247	return 0;
	248	}
	249
	250	static int psb_power_down(struct drm_device *dev)
	251	{
	252	return 0;
	253	}
	254
	255	static int psb_power_up(struct drm_device *dev)
	256	{
	257	return 0;
	258	}
	259
	260	static void psb_get_core_freq(struct drm_device *dev)
	261	{
	262	uint32_t clock;
	263	struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
	264	struct drm_psb_private *dev_priv = dev->dev_private;
	265
	266	/pci_write_config_dword(pci_root, 0xD4, 0x00C32004);/
	267	/pci_write_config_dword(pci_root, 0xD0, 0xE0033000);/
	268
	269	pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
	270	pci_read_config_dword(pci_root, 0xD4, &clock);
	271	pci_dev_put(pci_root);
	272
	273	switch (clock & 0x07) {
	274	case 0:
	275	dev_priv->core_freq = 100;
	276	break;
	277	case 1:
	278	dev_priv->core_freq = 133;
	279	break;
	280	case 2:
	281	dev_priv->core_freq = 150;
	282	break;
	283	case 3:
	284	dev_priv->core_freq = 178;
	285	break;
	286	case 4:
	287	dev_priv->core_freq = 200;
	288	break;
	289	case 5:
	290	case 6:
	291	case 7:
	292	dev_priv->core_freq = 266;
	293	default:
	294	dev_priv->core_freq = 0;
	295	}
	296	}
	297
8512e074 AC	298	/* Poulsbo */
	299	static const struct psb_offset psb_regmap[2] = {
	300	{
	301	.fp0 = FPA0,
	302	.fp1 = FPA1,
	303	.cntr = DSPACNTR,
	304	.conf = PIPEACONF,
	305	.src = PIPEASRC,
	306	.dpll = DPLL_A,
	307	.htotal = HTOTAL_A,
	308	.hblank = HBLANK_A,
	309	.hsync = HSYNC_A,
	310	.vtotal = VTOTAL_A,
	311	.vblank = VBLANK_A,
	312	.vsync = VSYNC_A,
	313	.stride = DSPASTRIDE,
	314	.size = DSPASIZE,
	315	.pos = DSPAPOS,
	316	.base = DSPABASE,
	317	.surf = DSPASURF,
	318	.addr = DSPABASE,
	319	.status = PIPEASTAT,
	320	.linoff = DSPALINOFF,
	321	.tileoff = DSPATILEOFF,
	322	.palette = PALETTE_A,
	323	},
	324	{
	325	.fp0 = FPB0,
	326	.fp1 = FPB1,
	327	.cntr = DSPBCNTR,
	328	.conf = PIPEBCONF,
	329	.src = PIPEBSRC,
	330	.dpll = DPLL_B,
	331	.htotal = HTOTAL_B,
	332	.hblank = HBLANK_B,
	333	.hsync = HSYNC_B,
	334	.vtotal = VTOTAL_B,
	335	.vblank = VBLANK_B,
	336	.vsync = VSYNC_B,
	337	.stride = DSPBSTRIDE,
	338	.size = DSPBSIZE,
	339	.pos = DSPBPOS,
	340	.base = DSPBBASE,
	341	.surf = DSPBSURF,
	342	.addr = DSPBBASE,
	343	.status = PIPEBSTAT,
	344	.linoff = DSPBLINOFF,
	345	.tileoff = DSPBTILEOFF,
	346	.palette = PALETTE_B,
	347	}
	348	};
	349
89c78134 AC	350	static int psb_chip_setup(struct drm_device *dev)
89c78134 AC	351	{
8512e074 AC	352	struct drm_psb_private *dev_priv = dev->dev_private;
8512e074 AC	353	dev_priv->regmap = psb_regmap;
89c78134	354	psb_get_core_freq(dev);
5c0c1d50	355	gma_intel_setup_gmbus(dev);
d839ede4	356	psb_intel_opregion_init(dev);
89c78134 AC	357	psb_intel_init_bios(dev);
	358	return 0;
	359	}
	360
5c0c1d50 PJ	361	static void psb_chip_teardown(struct drm_device *dev)
5c0c1d50 PJ	362	{
6607e024 AC	363	struct drm_psb_private *dev_priv = dev->dev_private;
6607e024 AC	364	psb_lid_timer_takedown(dev_priv);
5c0c1d50 PJ	365	gma_intel_teardown_gmbus(dev);
	366	}
	367
89c78134 AC	368	const struct psb_ops psb_chip_ops = {
	369	.name = "Poulsbo",
	370	.accel_2d = 1,
	371	.pipes = 2,
	372	.crtcs = 2,
d235e64a AC	373	.hdmi_mask = (1 << 0),
d235e64a AC	374	.lvds_mask = (1 << 1),
bc794829	375	.cursor_needs_phys = 1,
89c78134 AC	376	.sgx_offset = PSB_SGX_OFFSET,
89c78134 AC	377	.chip_setup = psb_chip_setup,
5c0c1d50	378	.chip_teardown = psb_chip_teardown,
89c78134 AC	379
	380	.crtc_helper = &psb_intel_helper_funcs,
	381	.crtc_funcs = &psb_intel_crtc_funcs,
	382
	383	.output_init = psb_output_init,
	384
	385	#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
	386	.backlight_init = psb_backlight_init,
	387	#endif
	388
	389	.init_pm = psb_init_pm,
	390	.save_regs = psb_save_display_registers,
	391	.restore_regs = psb_restore_display_registers,
	392	.power_down = psb_power_down,
	393	.power_up = psb_power_up,
	394	};
	395