Commit | Line | Data |
---|---|---|
1c248b7d ID |
1 | /* exynos_drm_fimd.c |
2 | * | |
3 | * Copyright (C) 2011 Samsung Electronics Co.Ltd | |
4 | * Authors: | |
5 | * Joonyoung Shim <jy0922.shim@samsung.com> | |
6 | * Inki Dae <inki.dae@samsung.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify it | |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2 of the License, or (at your | |
11 | * option) any later version. | |
12 | * | |
13 | */ | |
760285e7 | 14 | #include <drm/drmP.h> |
1c248b7d ID |
15 | |
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/platform_device.h> | |
19 | #include <linux/clk.h> | |
d636ead8 | 20 | #include <linux/of_device.h> |
cb91f6a0 | 21 | #include <linux/pm_runtime.h> |
1c248b7d | 22 | |
5a213a55 | 23 | #include <video/samsung_fimd.h> |
1c248b7d | 24 | #include <drm/exynos_drm.h> |
1c248b7d ID |
25 | |
26 | #include "exynos_drm_drv.h" | |
27 | #include "exynos_drm_fbdev.h" | |
28 | #include "exynos_drm_crtc.h" | |
bcc5cd1c | 29 | #include "exynos_drm_iommu.h" |
1c248b7d ID |
30 | |
31 | /* | |
32 | * FIMD is stand for Fully Interactive Mobile Display and | |
33 | * as a display controller, it transfers contents drawn on memory | |
34 | * to a LCD Panel through Display Interfaces such as RGB or | |
35 | * CPU Interface. | |
36 | */ | |
37 | ||
38 | /* position control register for hardware window 0, 2 ~ 4.*/ | |
39 | #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16) | |
40 | #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16) | |
41 | /* size control register for hardware window 0. */ | |
42 | #define VIDOSD_C_SIZE_W0 (VIDOSD_BASE + 0x08) | |
43 | /* alpha control register for hardware window 1 ~ 4. */ | |
44 | #define VIDOSD_C(win) (VIDOSD_BASE + 0x18 + (win) * 16) | |
45 | /* size control register for hardware window 1 ~ 4. */ | |
46 | #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16) | |
47 | ||
48 | #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8) | |
49 | #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8) | |
50 | #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4) | |
51 | ||
52 | /* color key control register for hardware window 1 ~ 4. */ | |
53 | #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + (x * 8)) | |
54 | /* color key value register for hardware window 1 ~ 4. */ | |
55 | #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + (x * 8)) | |
56 | ||
57 | /* FIMD has totally five hardware windows. */ | |
58 | #define WINDOWS_NR 5 | |
59 | ||
60 | #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev)) | |
61 | ||
e2e13389 LKA |
62 | struct fimd_driver_data { |
63 | unsigned int timing_base; | |
64 | }; | |
65 | ||
6ecf18f9 | 66 | static struct fimd_driver_data exynos4_fimd_driver_data = { |
e2e13389 LKA |
67 | .timing_base = 0x0, |
68 | }; | |
69 | ||
6ecf18f9 | 70 | static struct fimd_driver_data exynos5_fimd_driver_data = { |
e2e13389 LKA |
71 | .timing_base = 0x20000, |
72 | }; | |
73 | ||
1c248b7d ID |
74 | struct fimd_win_data { |
75 | unsigned int offset_x; | |
76 | unsigned int offset_y; | |
19c8b834 ID |
77 | unsigned int ovl_width; |
78 | unsigned int ovl_height; | |
79 | unsigned int fb_width; | |
80 | unsigned int fb_height; | |
1c248b7d | 81 | unsigned int bpp; |
2c871127 | 82 | dma_addr_t dma_addr; |
1c248b7d ID |
83 | unsigned int buf_offsize; |
84 | unsigned int line_size; /* bytes */ | |
ec05da95 | 85 | bool enabled; |
db7e55ae | 86 | bool resume; |
1c248b7d ID |
87 | }; |
88 | ||
89 | struct fimd_context { | |
90 | struct exynos_drm_subdrv subdrv; | |
91 | int irq; | |
92 | struct drm_crtc *crtc; | |
93 | struct clk *bus_clk; | |
94 | struct clk *lcd_clk; | |
1c248b7d ID |
95 | void __iomem *regs; |
96 | struct fimd_win_data win_data[WINDOWS_NR]; | |
97 | unsigned int clkdiv; | |
98 | unsigned int default_win; | |
99 | unsigned long irq_flags; | |
100 | u32 vidcon0; | |
101 | u32 vidcon1; | |
cb91f6a0 | 102 | bool suspended; |
c32b06ef | 103 | struct mutex lock; |
01ce113c P |
104 | wait_queue_head_t wait_vsync_queue; |
105 | atomic_t wait_vsync_event; | |
1c248b7d | 106 | |
607c50d4 | 107 | struct exynos_drm_panel_info *panel; |
1c248b7d ID |
108 | }; |
109 | ||
d636ead8 JS |
110 | #ifdef CONFIG_OF |
111 | static const struct of_device_id fimd_driver_dt_match[] = { | |
112 | { .compatible = "samsung,exynos4-fimd", | |
113 | .data = &exynos4_fimd_driver_data }, | |
114 | { .compatible = "samsung,exynos5-fimd", | |
115 | .data = &exynos5_fimd_driver_data }, | |
116 | {}, | |
117 | }; | |
118 | MODULE_DEVICE_TABLE(of, fimd_driver_dt_match); | |
119 | #endif | |
120 | ||
e2e13389 LKA |
121 | static inline struct fimd_driver_data *drm_fimd_get_driver_data( |
122 | struct platform_device *pdev) | |
123 | { | |
d636ead8 JS |
124 | #ifdef CONFIG_OF |
125 | const struct of_device_id *of_id = | |
126 | of_match_device(fimd_driver_dt_match, &pdev->dev); | |
127 | ||
128 | if (of_id) | |
129 | return (struct fimd_driver_data *)of_id->data; | |
130 | #endif | |
131 | ||
e2e13389 LKA |
132 | return (struct fimd_driver_data *) |
133 | platform_get_device_id(pdev)->driver_data; | |
134 | } | |
135 | ||
1c248b7d ID |
136 | static bool fimd_display_is_connected(struct device *dev) |
137 | { | |
1c248b7d ID |
138 | DRM_DEBUG_KMS("%s\n", __FILE__); |
139 | ||
140 | /* TODO. */ | |
141 | ||
142 | return true; | |
143 | } | |
144 | ||
607c50d4 | 145 | static void *fimd_get_panel(struct device *dev) |
1c248b7d ID |
146 | { |
147 | struct fimd_context *ctx = get_fimd_context(dev); | |
148 | ||
149 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
150 | ||
607c50d4 | 151 | return ctx->panel; |
1c248b7d ID |
152 | } |
153 | ||
154 | static int fimd_check_timing(struct device *dev, void *timing) | |
155 | { | |
1c248b7d ID |
156 | DRM_DEBUG_KMS("%s\n", __FILE__); |
157 | ||
158 | /* TODO. */ | |
159 | ||
160 | return 0; | |
161 | } | |
162 | ||
163 | static int fimd_display_power_on(struct device *dev, int mode) | |
164 | { | |
1c248b7d ID |
165 | DRM_DEBUG_KMS("%s\n", __FILE__); |
166 | ||
ec05da95 | 167 | /* TODO */ |
1c248b7d ID |
168 | |
169 | return 0; | |
170 | } | |
171 | ||
74ccc539 | 172 | static struct exynos_drm_display_ops fimd_display_ops = { |
1c248b7d ID |
173 | .type = EXYNOS_DISPLAY_TYPE_LCD, |
174 | .is_connected = fimd_display_is_connected, | |
607c50d4 | 175 | .get_panel = fimd_get_panel, |
1c248b7d ID |
176 | .check_timing = fimd_check_timing, |
177 | .power_on = fimd_display_power_on, | |
178 | }; | |
179 | ||
ec05da95 ID |
180 | static void fimd_dpms(struct device *subdrv_dev, int mode) |
181 | { | |
c32b06ef ID |
182 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); |
183 | ||
ec05da95 ID |
184 | DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode); |
185 | ||
c32b06ef ID |
186 | mutex_lock(&ctx->lock); |
187 | ||
cb91f6a0 JS |
188 | switch (mode) { |
189 | case DRM_MODE_DPMS_ON: | |
c32b06ef ID |
190 | /* |
191 | * enable fimd hardware only if suspended status. | |
192 | * | |
193 | * P.S. fimd_dpms function would be called at booting time so | |
194 | * clk_enable could be called double time. | |
195 | */ | |
196 | if (ctx->suspended) | |
197 | pm_runtime_get_sync(subdrv_dev); | |
cb91f6a0 JS |
198 | break; |
199 | case DRM_MODE_DPMS_STANDBY: | |
200 | case DRM_MODE_DPMS_SUSPEND: | |
201 | case DRM_MODE_DPMS_OFF: | |
373af0c0 ID |
202 | if (!ctx->suspended) |
203 | pm_runtime_put_sync(subdrv_dev); | |
cb91f6a0 JS |
204 | break; |
205 | default: | |
206 | DRM_DEBUG_KMS("unspecified mode %d\n", mode); | |
207 | break; | |
208 | } | |
c32b06ef ID |
209 | |
210 | mutex_unlock(&ctx->lock); | |
ec05da95 ID |
211 | } |
212 | ||
213 | static void fimd_apply(struct device *subdrv_dev) | |
214 | { | |
215 | struct fimd_context *ctx = get_fimd_context(subdrv_dev); | |
677e84c1 | 216 | struct exynos_drm_manager *mgr = ctx->subdrv.manager; |
ec05da95 ID |
217 | struct exynos_drm_manager_ops *mgr_ops = mgr->ops; |
218 | struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops; | |
219 | struct fimd_win_data *win_data; | |
864ee9e6 | 220 | int i; |
ec05da95 ID |
221 | |
222 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
223 | ||
864ee9e6 JS |
224 | for (i = 0; i < WINDOWS_NR; i++) { |
225 | win_data = &ctx->win_data[i]; | |
226 | if (win_data->enabled && (ovl_ops && ovl_ops->commit)) | |
227 | ovl_ops->commit(subdrv_dev, i); | |
228 | } | |
ec05da95 ID |
229 | |
230 | if (mgr_ops && mgr_ops->commit) | |
231 | mgr_ops->commit(subdrv_dev); | |
232 | } | |
233 | ||
1c248b7d ID |
234 | static void fimd_commit(struct device *dev) |
235 | { | |
236 | struct fimd_context *ctx = get_fimd_context(dev); | |
607c50d4 ECK |
237 | struct exynos_drm_panel_info *panel = ctx->panel; |
238 | struct fb_videomode *timing = &panel->timing; | |
e2e13389 LKA |
239 | struct fimd_driver_data *driver_data; |
240 | struct platform_device *pdev = to_platform_device(dev); | |
1c248b7d ID |
241 | u32 val; |
242 | ||
e2e13389 | 243 | driver_data = drm_fimd_get_driver_data(pdev); |
e30d4bcf ID |
244 | if (ctx->suspended) |
245 | return; | |
246 | ||
1c248b7d ID |
247 | DRM_DEBUG_KMS("%s\n", __FILE__); |
248 | ||
249 | /* setup polarity values from machine code. */ | |
e2e13389 | 250 | writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1); |
1c248b7d ID |
251 | |
252 | /* setup vertical timing values. */ | |
253 | val = VIDTCON0_VBPD(timing->upper_margin - 1) | | |
254 | VIDTCON0_VFPD(timing->lower_margin - 1) | | |
255 | VIDTCON0_VSPW(timing->vsync_len - 1); | |
e2e13389 | 256 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); |
1c248b7d ID |
257 | |
258 | /* setup horizontal timing values. */ | |
259 | val = VIDTCON1_HBPD(timing->left_margin - 1) | | |
260 | VIDTCON1_HFPD(timing->right_margin - 1) | | |
261 | VIDTCON1_HSPW(timing->hsync_len - 1); | |
e2e13389 | 262 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); |
1c248b7d ID |
263 | |
264 | /* setup horizontal and vertical display size. */ | |
265 | val = VIDTCON2_LINEVAL(timing->yres - 1) | | |
ca555e5a JS |
266 | VIDTCON2_HOZVAL(timing->xres - 1) | |
267 | VIDTCON2_LINEVAL_E(timing->yres - 1) | | |
268 | VIDTCON2_HOZVAL_E(timing->xres - 1); | |
e2e13389 | 269 | writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); |
1c248b7d ID |
270 | |
271 | /* setup clock source, clock divider, enable dma. */ | |
272 | val = ctx->vidcon0; | |
273 | val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR); | |
274 | ||
275 | if (ctx->clkdiv > 1) | |
276 | val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR; | |
277 | else | |
278 | val &= ~VIDCON0_CLKDIR; /* 1:1 clock */ | |
279 | ||
280 | /* | |
281 | * fields of register with prefix '_F' would be updated | |
282 | * at vsync(same as dma start) | |
283 | */ | |
284 | val |= VIDCON0_ENVID | VIDCON0_ENVID_F; | |
285 | writel(val, ctx->regs + VIDCON0); | |
286 | } | |
287 | ||
288 | static int fimd_enable_vblank(struct device *dev) | |
289 | { | |
290 | struct fimd_context *ctx = get_fimd_context(dev); | |
291 | u32 val; | |
292 | ||
293 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
294 | ||
cb91f6a0 JS |
295 | if (ctx->suspended) |
296 | return -EPERM; | |
297 | ||
1c248b7d ID |
298 | if (!test_and_set_bit(0, &ctx->irq_flags)) { |
299 | val = readl(ctx->regs + VIDINTCON0); | |
300 | ||
301 | val |= VIDINTCON0_INT_ENABLE; | |
302 | val |= VIDINTCON0_INT_FRAME; | |
303 | ||
304 | val &= ~VIDINTCON0_FRAMESEL0_MASK; | |
305 | val |= VIDINTCON0_FRAMESEL0_VSYNC; | |
306 | val &= ~VIDINTCON0_FRAMESEL1_MASK; | |
307 | val |= VIDINTCON0_FRAMESEL1_NONE; | |
308 | ||
309 | writel(val, ctx->regs + VIDINTCON0); | |
310 | } | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | static void fimd_disable_vblank(struct device *dev) | |
316 | { | |
317 | struct fimd_context *ctx = get_fimd_context(dev); | |
318 | u32 val; | |
319 | ||
320 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
321 | ||
cb91f6a0 JS |
322 | if (ctx->suspended) |
323 | return; | |
324 | ||
1c248b7d ID |
325 | if (test_and_clear_bit(0, &ctx->irq_flags)) { |
326 | val = readl(ctx->regs + VIDINTCON0); | |
327 | ||
328 | val &= ~VIDINTCON0_INT_FRAME; | |
329 | val &= ~VIDINTCON0_INT_ENABLE; | |
330 | ||
331 | writel(val, ctx->regs + VIDINTCON0); | |
332 | } | |
333 | } | |
334 | ||
07033970 P |
335 | static void fimd_wait_for_vblank(struct device *dev) |
336 | { | |
337 | struct fimd_context *ctx = get_fimd_context(dev); | |
07033970 | 338 | |
01ce113c P |
339 | if (ctx->suspended) |
340 | return; | |
341 | ||
342 | atomic_set(&ctx->wait_vsync_event, 1); | |
343 | ||
344 | /* | |
345 | * wait for FIMD to signal VSYNC interrupt or return after | |
346 | * timeout which is set to 50ms (refresh rate of 20). | |
347 | */ | |
348 | if (!wait_event_timeout(ctx->wait_vsync_queue, | |
349 | !atomic_read(&ctx->wait_vsync_event), | |
350 | DRM_HZ/20)) | |
07033970 P |
351 | DRM_DEBUG_KMS("vblank wait timed out.\n"); |
352 | } | |
353 | ||
1c248b7d | 354 | static struct exynos_drm_manager_ops fimd_manager_ops = { |
ec05da95 ID |
355 | .dpms = fimd_dpms, |
356 | .apply = fimd_apply, | |
1c248b7d ID |
357 | .commit = fimd_commit, |
358 | .enable_vblank = fimd_enable_vblank, | |
359 | .disable_vblank = fimd_disable_vblank, | |
07033970 | 360 | .wait_for_vblank = fimd_wait_for_vblank, |
1c248b7d ID |
361 | }; |
362 | ||
363 | static void fimd_win_mode_set(struct device *dev, | |
364 | struct exynos_drm_overlay *overlay) | |
365 | { | |
366 | struct fimd_context *ctx = get_fimd_context(dev); | |
367 | struct fimd_win_data *win_data; | |
864ee9e6 | 368 | int win; |
19c8b834 | 369 | unsigned long offset; |
1c248b7d ID |
370 | |
371 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
372 | ||
373 | if (!overlay) { | |
374 | dev_err(dev, "overlay is NULL\n"); | |
375 | return; | |
376 | } | |
377 | ||
864ee9e6 JS |
378 | win = overlay->zpos; |
379 | if (win == DEFAULT_ZPOS) | |
380 | win = ctx->default_win; | |
381 | ||
382 | if (win < 0 || win > WINDOWS_NR) | |
383 | return; | |
384 | ||
19c8b834 ID |
385 | offset = overlay->fb_x * (overlay->bpp >> 3); |
386 | offset += overlay->fb_y * overlay->pitch; | |
387 | ||
388 | DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch); | |
389 | ||
864ee9e6 | 390 | win_data = &ctx->win_data[win]; |
1c248b7d | 391 | |
19c8b834 ID |
392 | win_data->offset_x = overlay->crtc_x; |
393 | win_data->offset_y = overlay->crtc_y; | |
394 | win_data->ovl_width = overlay->crtc_width; | |
395 | win_data->ovl_height = overlay->crtc_height; | |
396 | win_data->fb_width = overlay->fb_width; | |
397 | win_data->fb_height = overlay->fb_height; | |
229d3534 | 398 | win_data->dma_addr = overlay->dma_addr[0] + offset; |
1c248b7d | 399 | win_data->bpp = overlay->bpp; |
19c8b834 ID |
400 | win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) * |
401 | (overlay->bpp >> 3); | |
402 | win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3); | |
403 | ||
404 | DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n", | |
405 | win_data->offset_x, win_data->offset_y); | |
406 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", | |
407 | win_data->ovl_width, win_data->ovl_height); | |
ddd8e959 | 408 | DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr); |
19c8b834 ID |
409 | DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n", |
410 | overlay->fb_width, overlay->crtc_width); | |
1c248b7d ID |
411 | } |
412 | ||
413 | static void fimd_win_set_pixfmt(struct device *dev, unsigned int win) | |
414 | { | |
415 | struct fimd_context *ctx = get_fimd_context(dev); | |
416 | struct fimd_win_data *win_data = &ctx->win_data[win]; | |
417 | unsigned long val; | |
418 | ||
419 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
420 | ||
421 | val = WINCONx_ENWIN; | |
422 | ||
423 | switch (win_data->bpp) { | |
424 | case 1: | |
425 | val |= WINCON0_BPPMODE_1BPP; | |
426 | val |= WINCONx_BITSWP; | |
427 | val |= WINCONx_BURSTLEN_4WORD; | |
428 | break; | |
429 | case 2: | |
430 | val |= WINCON0_BPPMODE_2BPP; | |
431 | val |= WINCONx_BITSWP; | |
432 | val |= WINCONx_BURSTLEN_8WORD; | |
433 | break; | |
434 | case 4: | |
435 | val |= WINCON0_BPPMODE_4BPP; | |
436 | val |= WINCONx_BITSWP; | |
437 | val |= WINCONx_BURSTLEN_8WORD; | |
438 | break; | |
439 | case 8: | |
440 | val |= WINCON0_BPPMODE_8BPP_PALETTE; | |
441 | val |= WINCONx_BURSTLEN_8WORD; | |
442 | val |= WINCONx_BYTSWP; | |
443 | break; | |
444 | case 16: | |
445 | val |= WINCON0_BPPMODE_16BPP_565; | |
446 | val |= WINCONx_HAWSWP; | |
447 | val |= WINCONx_BURSTLEN_16WORD; | |
448 | break; | |
449 | case 24: | |
450 | val |= WINCON0_BPPMODE_24BPP_888; | |
451 | val |= WINCONx_WSWP; | |
452 | val |= WINCONx_BURSTLEN_16WORD; | |
453 | break; | |
454 | case 32: | |
455 | val |= WINCON1_BPPMODE_28BPP_A4888 | |
456 | | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL; | |
457 | val |= WINCONx_WSWP; | |
458 | val |= WINCONx_BURSTLEN_16WORD; | |
459 | break; | |
460 | default: | |
461 | DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n"); | |
462 | ||
463 | val |= WINCON0_BPPMODE_24BPP_888; | |
464 | val |= WINCONx_WSWP; | |
465 | val |= WINCONx_BURSTLEN_16WORD; | |
466 | break; | |
467 | } | |
468 | ||
469 | DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp); | |
470 | ||
471 | writel(val, ctx->regs + WINCON(win)); | |
472 | } | |
473 | ||
474 | static void fimd_win_set_colkey(struct device *dev, unsigned int win) | |
475 | { | |
476 | struct fimd_context *ctx = get_fimd_context(dev); | |
477 | unsigned int keycon0 = 0, keycon1 = 0; | |
478 | ||
479 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
480 | ||
481 | keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F | | |
482 | WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0); | |
483 | ||
484 | keycon1 = WxKEYCON1_COLVAL(0xffffffff); | |
485 | ||
486 | writel(keycon0, ctx->regs + WKEYCON0_BASE(win)); | |
487 | writel(keycon1, ctx->regs + WKEYCON1_BASE(win)); | |
488 | } | |
489 | ||
864ee9e6 | 490 | static void fimd_win_commit(struct device *dev, int zpos) |
1c248b7d ID |
491 | { |
492 | struct fimd_context *ctx = get_fimd_context(dev); | |
493 | struct fimd_win_data *win_data; | |
864ee9e6 | 494 | int win = zpos; |
1c248b7d | 495 | unsigned long val, alpha, size; |
f56aad3a JS |
496 | unsigned int last_x; |
497 | unsigned int last_y; | |
1c248b7d ID |
498 | |
499 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
500 | ||
e30d4bcf ID |
501 | if (ctx->suspended) |
502 | return; | |
503 | ||
864ee9e6 JS |
504 | if (win == DEFAULT_ZPOS) |
505 | win = ctx->default_win; | |
506 | ||
1c248b7d ID |
507 | if (win < 0 || win > WINDOWS_NR) |
508 | return; | |
509 | ||
510 | win_data = &ctx->win_data[win]; | |
511 | ||
512 | /* | |
513 | * SHADOWCON register is used for enabling timing. | |
514 | * | |
515 | * for example, once only width value of a register is set, | |
516 | * if the dma is started then fimd hardware could malfunction so | |
517 | * with protect window setting, the register fields with prefix '_F' | |
518 | * wouldn't be updated at vsync also but updated once unprotect window | |
519 | * is set. | |
520 | */ | |
521 | ||
522 | /* protect windows */ | |
523 | val = readl(ctx->regs + SHADOWCON); | |
524 | val |= SHADOWCON_WINx_PROTECT(win); | |
525 | writel(val, ctx->regs + SHADOWCON); | |
526 | ||
527 | /* buffer start address */ | |
2c871127 | 528 | val = (unsigned long)win_data->dma_addr; |
1c248b7d ID |
529 | writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); |
530 | ||
531 | /* buffer end address */ | |
19c8b834 | 532 | size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3); |
2c871127 | 533 | val = (unsigned long)(win_data->dma_addr + size); |
1c248b7d ID |
534 | writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); |
535 | ||
536 | DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n", | |
2c871127 | 537 | (unsigned long)win_data->dma_addr, val, size); |
19c8b834 ID |
538 | DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n", |
539 | win_data->ovl_width, win_data->ovl_height); | |
1c248b7d ID |
540 | |
541 | /* buffer size */ | |
542 | val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) | | |
ca555e5a JS |
543 | VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) | |
544 | VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) | | |
545 | VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size); | |
1c248b7d ID |
546 | writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); |
547 | ||
548 | /* OSD position */ | |
549 | val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) | | |
ca555e5a JS |
550 | VIDOSDxA_TOPLEFT_Y(win_data->offset_y) | |
551 | VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) | | |
552 | VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y); | |
1c248b7d ID |
553 | writel(val, ctx->regs + VIDOSD_A(win)); |
554 | ||
f56aad3a JS |
555 | last_x = win_data->offset_x + win_data->ovl_width; |
556 | if (last_x) | |
557 | last_x--; | |
558 | last_y = win_data->offset_y + win_data->ovl_height; | |
559 | if (last_y) | |
560 | last_y--; | |
561 | ||
ca555e5a JS |
562 | val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | |
563 | VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y); | |
564 | ||
1c248b7d ID |
565 | writel(val, ctx->regs + VIDOSD_B(win)); |
566 | ||
19c8b834 | 567 | DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n", |
f56aad3a | 568 | win_data->offset_x, win_data->offset_y, last_x, last_y); |
1c248b7d ID |
569 | |
570 | /* hardware window 0 doesn't support alpha channel. */ | |
571 | if (win != 0) { | |
572 | /* OSD alpha */ | |
573 | alpha = VIDISD14C_ALPHA1_R(0xf) | | |
574 | VIDISD14C_ALPHA1_G(0xf) | | |
575 | VIDISD14C_ALPHA1_B(0xf); | |
576 | ||
577 | writel(alpha, ctx->regs + VIDOSD_C(win)); | |
578 | } | |
579 | ||
580 | /* OSD size */ | |
581 | if (win != 3 && win != 4) { | |
582 | u32 offset = VIDOSD_D(win); | |
583 | if (win == 0) | |
584 | offset = VIDOSD_C_SIZE_W0; | |
19c8b834 | 585 | val = win_data->ovl_width * win_data->ovl_height; |
1c248b7d ID |
586 | writel(val, ctx->regs + offset); |
587 | ||
588 | DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); | |
589 | } | |
590 | ||
591 | fimd_win_set_pixfmt(dev, win); | |
592 | ||
593 | /* hardware window 0 doesn't support color key. */ | |
594 | if (win != 0) | |
595 | fimd_win_set_colkey(dev, win); | |
596 | ||
ec05da95 ID |
597 | /* wincon */ |
598 | val = readl(ctx->regs + WINCON(win)); | |
599 | val |= WINCONx_ENWIN; | |
600 | writel(val, ctx->regs + WINCON(win)); | |
601 | ||
1c248b7d ID |
602 | /* Enable DMA channel and unprotect windows */ |
603 | val = readl(ctx->regs + SHADOWCON); | |
604 | val |= SHADOWCON_CHx_ENABLE(win); | |
605 | val &= ~SHADOWCON_WINx_PROTECT(win); | |
606 | writel(val, ctx->regs + SHADOWCON); | |
ec05da95 ID |
607 | |
608 | win_data->enabled = true; | |
1c248b7d ID |
609 | } |
610 | ||
864ee9e6 | 611 | static void fimd_win_disable(struct device *dev, int zpos) |
1c248b7d ID |
612 | { |
613 | struct fimd_context *ctx = get_fimd_context(dev); | |
ec05da95 | 614 | struct fimd_win_data *win_data; |
864ee9e6 | 615 | int win = zpos; |
1c248b7d ID |
616 | u32 val; |
617 | ||
618 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
619 | ||
864ee9e6 JS |
620 | if (win == DEFAULT_ZPOS) |
621 | win = ctx->default_win; | |
622 | ||
1c248b7d ID |
623 | if (win < 0 || win > WINDOWS_NR) |
624 | return; | |
625 | ||
ec05da95 ID |
626 | win_data = &ctx->win_data[win]; |
627 | ||
db7e55ae P |
628 | if (ctx->suspended) { |
629 | /* do not resume this window*/ | |
630 | win_data->resume = false; | |
631 | return; | |
632 | } | |
633 | ||
1c248b7d ID |
634 | /* protect windows */ |
635 | val = readl(ctx->regs + SHADOWCON); | |
636 | val |= SHADOWCON_WINx_PROTECT(win); | |
637 | writel(val, ctx->regs + SHADOWCON); | |
638 | ||
639 | /* wincon */ | |
640 | val = readl(ctx->regs + WINCON(win)); | |
641 | val &= ~WINCONx_ENWIN; | |
642 | writel(val, ctx->regs + WINCON(win)); | |
643 | ||
644 | /* unprotect windows */ | |
645 | val = readl(ctx->regs + SHADOWCON); | |
646 | val &= ~SHADOWCON_CHx_ENABLE(win); | |
647 | val &= ~SHADOWCON_WINx_PROTECT(win); | |
648 | writel(val, ctx->regs + SHADOWCON); | |
ec05da95 ID |
649 | |
650 | win_data->enabled = false; | |
1c248b7d ID |
651 | } |
652 | ||
653 | static struct exynos_drm_overlay_ops fimd_overlay_ops = { | |
654 | .mode_set = fimd_win_mode_set, | |
655 | .commit = fimd_win_commit, | |
656 | .disable = fimd_win_disable, | |
657 | }; | |
658 | ||
677e84c1 JS |
659 | static struct exynos_drm_manager fimd_manager = { |
660 | .pipe = -1, | |
661 | .ops = &fimd_manager_ops, | |
662 | .overlay_ops = &fimd_overlay_ops, | |
663 | .display_ops = &fimd_display_ops, | |
664 | }; | |
665 | ||
1c248b7d ID |
666 | static void fimd_finish_pageflip(struct drm_device *drm_dev, int crtc) |
667 | { | |
668 | struct exynos_drm_private *dev_priv = drm_dev->dev_private; | |
669 | struct drm_pending_vblank_event *e, *t; | |
670 | struct timeval now; | |
671 | unsigned long flags; | |
1c248b7d ID |
672 | |
673 | spin_lock_irqsave(&drm_dev->event_lock, flags); | |
674 | ||
1c248b7d ID |
675 | list_for_each_entry_safe(e, t, &dev_priv->pageflip_event_list, |
676 | base.link) { | |
a88cab2b | 677 | /* if event's pipe isn't same as crtc then ignore it. */ |
ccf4d883 ID |
678 | if (crtc != e->pipe) |
679 | continue; | |
680 | ||
1c248b7d ID |
681 | do_gettimeofday(&now); |
682 | e->event.sequence = 0; | |
683 | e->event.tv_sec = now.tv_sec; | |
684 | e->event.tv_usec = now.tv_usec; | |
685 | ||
686 | list_move_tail(&e->base.link, &e->base.file_priv->event_list); | |
687 | wake_up_interruptible(&e->base.file_priv->event_wait); | |
e1f48ee5 | 688 | drm_vblank_put(drm_dev, crtc); |
1c248b7d ID |
689 | } |
690 | ||
1c248b7d ID |
691 | spin_unlock_irqrestore(&drm_dev->event_lock, flags); |
692 | } | |
693 | ||
694 | static irqreturn_t fimd_irq_handler(int irq, void *dev_id) | |
695 | { | |
696 | struct fimd_context *ctx = (struct fimd_context *)dev_id; | |
697 | struct exynos_drm_subdrv *subdrv = &ctx->subdrv; | |
698 | struct drm_device *drm_dev = subdrv->drm_dev; | |
677e84c1 | 699 | struct exynos_drm_manager *manager = subdrv->manager; |
1c248b7d ID |
700 | u32 val; |
701 | ||
702 | val = readl(ctx->regs + VIDINTCON1); | |
703 | ||
704 | if (val & VIDINTCON1_INT_FRAME) | |
705 | /* VSYNC interrupt */ | |
706 | writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1); | |
707 | ||
ec05da95 ID |
708 | /* check the crtc is detached already from encoder */ |
709 | if (manager->pipe < 0) | |
710 | goto out; | |
483b88f8 | 711 | |
1c248b7d ID |
712 | drm_handle_vblank(drm_dev, manager->pipe); |
713 | fimd_finish_pageflip(drm_dev, manager->pipe); | |
714 | ||
01ce113c P |
715 | /* set wait vsync event to zero and wake up queue. */ |
716 | if (atomic_read(&ctx->wait_vsync_event)) { | |
717 | atomic_set(&ctx->wait_vsync_event, 0); | |
718 | DRM_WAKEUP(&ctx->wait_vsync_queue); | |
719 | } | |
ec05da95 | 720 | out: |
1c248b7d ID |
721 | return IRQ_HANDLED; |
722 | } | |
723 | ||
41c24346 | 724 | static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 725 | { |
1c248b7d ID |
726 | DRM_DEBUG_KMS("%s\n", __FILE__); |
727 | ||
728 | /* | |
729 | * enable drm irq mode. | |
730 | * - with irq_enabled = 1, we can use the vblank feature. | |
731 | * | |
732 | * P.S. note that we wouldn't use drm irq handler but | |
733 | * just specific driver own one instead because | |
734 | * drm framework supports only one irq handler. | |
735 | */ | |
736 | drm_dev->irq_enabled = 1; | |
737 | ||
ec05da95 ID |
738 | /* |
739 | * with vblank_disable_allowed = 1, vblank interrupt will be disabled | |
740 | * by drm timer once a current process gives up ownership of | |
741 | * vblank event.(after drm_vblank_put function is called) | |
742 | */ | |
743 | drm_dev->vblank_disable_allowed = 1; | |
744 | ||
bcc5cd1c ID |
745 | /* attach this sub driver to iommu mapping if supported. */ |
746 | if (is_drm_iommu_supported(drm_dev)) | |
747 | drm_iommu_attach_device(drm_dev, dev); | |
748 | ||
1c248b7d ID |
749 | return 0; |
750 | } | |
751 | ||
29cb6025 | 752 | static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev) |
1c248b7d | 753 | { |
1c248b7d ID |
754 | DRM_DEBUG_KMS("%s\n", __FILE__); |
755 | ||
bcc5cd1c ID |
756 | /* detach this sub driver from iommu mapping if supported. */ |
757 | if (is_drm_iommu_supported(drm_dev)) | |
758 | drm_iommu_detach_device(drm_dev, dev); | |
1c248b7d ID |
759 | } |
760 | ||
761 | static int fimd_calc_clkdiv(struct fimd_context *ctx, | |
762 | struct fb_videomode *timing) | |
763 | { | |
764 | unsigned long clk = clk_get_rate(ctx->lcd_clk); | |
765 | u32 retrace; | |
766 | u32 clkdiv; | |
767 | u32 best_framerate = 0; | |
768 | u32 framerate; | |
769 | ||
770 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
771 | ||
772 | retrace = timing->left_margin + timing->hsync_len + | |
773 | timing->right_margin + timing->xres; | |
774 | retrace *= timing->upper_margin + timing->vsync_len + | |
775 | timing->lower_margin + timing->yres; | |
776 | ||
777 | /* default framerate is 60Hz */ | |
778 | if (!timing->refresh) | |
779 | timing->refresh = 60; | |
780 | ||
781 | clk /= retrace; | |
782 | ||
783 | for (clkdiv = 1; clkdiv < 0x100; clkdiv++) { | |
784 | int tmp; | |
785 | ||
786 | /* get best framerate */ | |
787 | framerate = clk / clkdiv; | |
788 | tmp = timing->refresh - framerate; | |
789 | if (tmp < 0) { | |
790 | best_framerate = framerate; | |
791 | continue; | |
792 | } else { | |
793 | if (!best_framerate) | |
794 | best_framerate = framerate; | |
795 | else if (tmp < (best_framerate - framerate)) | |
796 | best_framerate = framerate; | |
797 | break; | |
798 | } | |
799 | } | |
800 | ||
801 | return clkdiv; | |
802 | } | |
803 | ||
804 | static void fimd_clear_win(struct fimd_context *ctx, int win) | |
805 | { | |
806 | u32 val; | |
807 | ||
808 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
809 | ||
810 | writel(0, ctx->regs + WINCON(win)); | |
811 | writel(0, ctx->regs + VIDOSD_A(win)); | |
812 | writel(0, ctx->regs + VIDOSD_B(win)); | |
813 | writel(0, ctx->regs + VIDOSD_C(win)); | |
814 | ||
815 | if (win == 1 || win == 2) | |
816 | writel(0, ctx->regs + VIDOSD_D(win)); | |
817 | ||
818 | val = readl(ctx->regs + SHADOWCON); | |
819 | val &= ~SHADOWCON_WINx_PROTECT(win); | |
820 | writel(val, ctx->regs + SHADOWCON); | |
821 | } | |
822 | ||
5d55393a | 823 | static int fimd_clock(struct fimd_context *ctx, bool enable) |
373af0c0 | 824 | { |
373af0c0 ID |
825 | DRM_DEBUG_KMS("%s\n", __FILE__); |
826 | ||
373af0c0 ID |
827 | if (enable) { |
828 | int ret; | |
829 | ||
830 | ret = clk_enable(ctx->bus_clk); | |
831 | if (ret < 0) | |
832 | return ret; | |
833 | ||
834 | ret = clk_enable(ctx->lcd_clk); | |
835 | if (ret < 0) { | |
836 | clk_disable(ctx->bus_clk); | |
837 | return ret; | |
838 | } | |
5d55393a ID |
839 | } else { |
840 | clk_disable(ctx->lcd_clk); | |
841 | clk_disable(ctx->bus_clk); | |
842 | } | |
843 | ||
844 | return 0; | |
845 | } | |
846 | ||
db7e55ae P |
847 | static void fimd_window_suspend(struct device *dev) |
848 | { | |
849 | struct fimd_context *ctx = get_fimd_context(dev); | |
850 | struct fimd_win_data *win_data; | |
851 | int i; | |
852 | ||
853 | for (i = 0; i < WINDOWS_NR; i++) { | |
854 | win_data = &ctx->win_data[i]; | |
855 | win_data->resume = win_data->enabled; | |
856 | fimd_win_disable(dev, i); | |
857 | } | |
858 | fimd_wait_for_vblank(dev); | |
859 | } | |
860 | ||
861 | static void fimd_window_resume(struct device *dev) | |
862 | { | |
863 | struct fimd_context *ctx = get_fimd_context(dev); | |
864 | struct fimd_win_data *win_data; | |
865 | int i; | |
866 | ||
867 | for (i = 0; i < WINDOWS_NR; i++) { | |
868 | win_data = &ctx->win_data[i]; | |
869 | win_data->enabled = win_data->resume; | |
870 | win_data->resume = false; | |
871 | } | |
872 | } | |
873 | ||
5d55393a ID |
874 | static int fimd_activate(struct fimd_context *ctx, bool enable) |
875 | { | |
db7e55ae | 876 | struct device *dev = ctx->subdrv.dev; |
5d55393a ID |
877 | if (enable) { |
878 | int ret; | |
5d55393a ID |
879 | |
880 | ret = fimd_clock(ctx, true); | |
881 | if (ret < 0) | |
882 | return ret; | |
373af0c0 ID |
883 | |
884 | ctx->suspended = false; | |
885 | ||
886 | /* if vblank was enabled status, enable it again. */ | |
887 | if (test_and_clear_bit(0, &ctx->irq_flags)) | |
888 | fimd_enable_vblank(dev); | |
db7e55ae P |
889 | |
890 | fimd_window_resume(dev); | |
373af0c0 | 891 | } else { |
db7e55ae P |
892 | fimd_window_suspend(dev); |
893 | ||
5d55393a | 894 | fimd_clock(ctx, false); |
373af0c0 ID |
895 | ctx->suspended = true; |
896 | } | |
897 | ||
898 | return 0; | |
899 | } | |
900 | ||
1c248b7d ID |
901 | static int __devinit fimd_probe(struct platform_device *pdev) |
902 | { | |
903 | struct device *dev = &pdev->dev; | |
904 | struct fimd_context *ctx; | |
905 | struct exynos_drm_subdrv *subdrv; | |
906 | struct exynos_drm_fimd_pdata *pdata; | |
607c50d4 | 907 | struct exynos_drm_panel_info *panel; |
1c248b7d ID |
908 | struct resource *res; |
909 | int win; | |
910 | int ret = -EINVAL; | |
911 | ||
912 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
913 | ||
914 | pdata = pdev->dev.platform_data; | |
915 | if (!pdata) { | |
916 | dev_err(dev, "no platform data specified\n"); | |
917 | return -EINVAL; | |
918 | } | |
919 | ||
607c50d4 ECK |
920 | panel = &pdata->panel; |
921 | if (!panel) { | |
922 | dev_err(dev, "panel is null.\n"); | |
1c248b7d ID |
923 | return -EINVAL; |
924 | } | |
925 | ||
edc57266 | 926 | ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL); |
1c248b7d ID |
927 | if (!ctx) |
928 | return -ENOMEM; | |
929 | ||
a4d8de5f | 930 | ctx->bus_clk = devm_clk_get(dev, "fimd"); |
1c248b7d ID |
931 | if (IS_ERR(ctx->bus_clk)) { |
932 | dev_err(dev, "failed to get bus clock\n"); | |
a4d8de5f | 933 | return PTR_ERR(ctx->bus_clk); |
1c248b7d ID |
934 | } |
935 | ||
a4d8de5f | 936 | ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd"); |
1c248b7d ID |
937 | if (IS_ERR(ctx->lcd_clk)) { |
938 | dev_err(dev, "failed to get lcd clock\n"); | |
a4d8de5f | 939 | return PTR_ERR(ctx->lcd_clk); |
1c248b7d ID |
940 | } |
941 | ||
1c248b7d | 942 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
1c248b7d | 943 | |
edc57266 | 944 | ctx->regs = devm_request_and_ioremap(&pdev->dev, res); |
1c248b7d ID |
945 | if (!ctx->regs) { |
946 | dev_err(dev, "failed to map registers\n"); | |
a4d8de5f | 947 | return -ENXIO; |
1c248b7d ID |
948 | } |
949 | ||
950 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); | |
951 | if (!res) { | |
952 | dev_err(dev, "irq request failed.\n"); | |
a4d8de5f | 953 | return -ENXIO; |
1c248b7d ID |
954 | } |
955 | ||
956 | ctx->irq = res->start; | |
957 | ||
edc57266 SK |
958 | ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler, |
959 | 0, "drm_fimd", ctx); | |
960 | if (ret) { | |
1c248b7d | 961 | dev_err(dev, "irq request failed.\n"); |
a4d8de5f | 962 | return ret; |
1c248b7d ID |
963 | } |
964 | ||
1c248b7d ID |
965 | ctx->vidcon0 = pdata->vidcon0; |
966 | ctx->vidcon1 = pdata->vidcon1; | |
967 | ctx->default_win = pdata->default_win; | |
607c50d4 | 968 | ctx->panel = panel; |
01ce113c P |
969 | DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue); |
970 | atomic_set(&ctx->wait_vsync_event, 0); | |
1c248b7d | 971 | |
1c248b7d ID |
972 | subdrv = &ctx->subdrv; |
973 | ||
677e84c1 JS |
974 | subdrv->dev = dev; |
975 | subdrv->manager = &fimd_manager; | |
1c248b7d ID |
976 | subdrv->probe = fimd_subdrv_probe; |
977 | subdrv->remove = fimd_subdrv_remove; | |
1c248b7d | 978 | |
c32b06ef ID |
979 | mutex_init(&ctx->lock); |
980 | ||
1c248b7d | 981 | platform_set_drvdata(pdev, ctx); |
c32b06ef | 982 | |
c32b06ef ID |
983 | pm_runtime_enable(dev); |
984 | pm_runtime_get_sync(dev); | |
985 | ||
0d8ce3ae MS |
986 | ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing); |
987 | panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv; | |
988 | ||
989 | DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n", | |
990 | panel->timing.pixclock, ctx->clkdiv); | |
991 | ||
c32b06ef ID |
992 | for (win = 0; win < WINDOWS_NR; win++) |
993 | fimd_clear_win(ctx, win); | |
994 | ||
1c248b7d ID |
995 | exynos_drm_subdrv_register(subdrv); |
996 | ||
997 | return 0; | |
1c248b7d ID |
998 | } |
999 | ||
1000 | static int __devexit fimd_remove(struct platform_device *pdev) | |
1001 | { | |
cb91f6a0 | 1002 | struct device *dev = &pdev->dev; |
1c248b7d ID |
1003 | struct fimd_context *ctx = platform_get_drvdata(pdev); |
1004 | ||
1005 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
1006 | ||
1007 | exynos_drm_subdrv_unregister(&ctx->subdrv); | |
1008 | ||
cb91f6a0 JS |
1009 | if (ctx->suspended) |
1010 | goto out; | |
1011 | ||
1c248b7d ID |
1012 | clk_disable(ctx->lcd_clk); |
1013 | clk_disable(ctx->bus_clk); | |
cb91f6a0 JS |
1014 | |
1015 | pm_runtime_set_suspended(dev); | |
1016 | pm_runtime_put_sync(dev); | |
1017 | ||
1018 | out: | |
1019 | pm_runtime_disable(dev); | |
1020 | ||
1c248b7d ID |
1021 | return 0; |
1022 | } | |
1023 | ||
e30d4bcf ID |
1024 | #ifdef CONFIG_PM_SLEEP |
1025 | static int fimd_suspend(struct device *dev) | |
1026 | { | |
373af0c0 | 1027 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 1028 | |
373af0c0 ID |
1029 | /* |
1030 | * do not use pm_runtime_suspend(). if pm_runtime_suspend() is | |
1031 | * called here, an error would be returned by that interface | |
1032 | * because the usage_count of pm runtime is more than 1. | |
1033 | */ | |
5d55393a ID |
1034 | if (!pm_runtime_suspended(dev)) |
1035 | return fimd_activate(ctx, false); | |
1036 | ||
1037 | return 0; | |
e30d4bcf ID |
1038 | } |
1039 | ||
1040 | static int fimd_resume(struct device *dev) | |
1041 | { | |
373af0c0 | 1042 | struct fimd_context *ctx = get_fimd_context(dev); |
e30d4bcf | 1043 | |
373af0c0 ID |
1044 | /* |
1045 | * if entered to sleep when lcd panel was on, the usage_count | |
1046 | * of pm runtime would still be 1 so in this case, fimd driver | |
1047 | * should be on directly not drawing on pm runtime interface. | |
1048 | */ | |
28998afa | 1049 | if (!pm_runtime_suspended(dev)) { |
5d55393a ID |
1050 | int ret; |
1051 | ||
1052 | ret = fimd_activate(ctx, true); | |
1053 | if (ret < 0) | |
1054 | return ret; | |
1055 | ||
1056 | /* | |
1057 | * in case of dpms on(standby), fimd_apply function will | |
1058 | * be called by encoder's dpms callback to update fimd's | |
1059 | * registers but in case of sleep wakeup, it's not. | |
1060 | * so fimd_apply function should be called at here. | |
1061 | */ | |
1062 | fimd_apply(dev); | |
1063 | } | |
e30d4bcf | 1064 | |
e30d4bcf ID |
1065 | return 0; |
1066 | } | |
1067 | #endif | |
1068 | ||
cb91f6a0 JS |
1069 | #ifdef CONFIG_PM_RUNTIME |
1070 | static int fimd_runtime_suspend(struct device *dev) | |
1071 | { | |
1072 | struct fimd_context *ctx = get_fimd_context(dev); | |
1073 | ||
1074 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
1075 | ||
5d55393a | 1076 | return fimd_activate(ctx, false); |
cb91f6a0 JS |
1077 | } |
1078 | ||
1079 | static int fimd_runtime_resume(struct device *dev) | |
1080 | { | |
1081 | struct fimd_context *ctx = get_fimd_context(dev); | |
cb91f6a0 JS |
1082 | |
1083 | DRM_DEBUG_KMS("%s\n", __FILE__); | |
1084 | ||
5d55393a | 1085 | return fimd_activate(ctx, true); |
cb91f6a0 JS |
1086 | } |
1087 | #endif | |
1088 | ||
e2e13389 LKA |
1089 | static struct platform_device_id fimd_driver_ids[] = { |
1090 | { | |
1091 | .name = "exynos4-fb", | |
1092 | .driver_data = (unsigned long)&exynos4_fimd_driver_data, | |
1093 | }, { | |
1094 | .name = "exynos5-fb", | |
1095 | .driver_data = (unsigned long)&exynos5_fimd_driver_data, | |
1096 | }, | |
1097 | {}, | |
1098 | }; | |
1099 | MODULE_DEVICE_TABLE(platform, fimd_driver_ids); | |
1100 | ||
cb91f6a0 | 1101 | static const struct dev_pm_ops fimd_pm_ops = { |
e30d4bcf | 1102 | SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume) |
cb91f6a0 JS |
1103 | SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL) |
1104 | }; | |
1105 | ||
132a5b91 | 1106 | struct platform_driver fimd_driver = { |
1c248b7d ID |
1107 | .probe = fimd_probe, |
1108 | .remove = __devexit_p(fimd_remove), | |
e2e13389 | 1109 | .id_table = fimd_driver_ids, |
1c248b7d ID |
1110 | .driver = { |
1111 | .name = "exynos4-fb", | |
1112 | .owner = THIS_MODULE, | |
cb91f6a0 | 1113 | .pm = &fimd_pm_ops, |
d636ead8 | 1114 | .of_match_table = of_match_ptr(fimd_driver_dt_match), |
1c248b7d ID |
1115 | }, |
1116 | }; |