[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / timbgpio.c

/*
 * timbgpio.c timberdale FPGA GPIO driver
 * Copyright (c) 2009 Intel Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Timberdale FPGA GPIO
 */

#include <linux/module.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/timb_gpio.h>
#include <linux/interrupt.h>

#define DRIVER_NAME "timb-gpio"

#define TGPIOVAL	0x00
#define TGPIODIR	0x04
#define TGPIO_IER	0x08
#define TGPIO_ISR	0x0c
#define TGPIO_IPR	0x10
#define TGPIO_ICR	0x14
#define TGPIO_FLR	0x18
#define TGPIO_LVR	0x1c

struct timbgpio {
	void __iomem		*membase;
	spinlock_t		lock; /* mutual exclusion */
	struct gpio_chip	gpio;
	int			irq_base;
};

static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	unsigned offset, bool enabled)
{
	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	u32 reg;

	spin_lock(&tgpio->lock);
	reg = ioread32(tgpio->membase + offset);

	if (enabled)
		reg |= (1 << index);
	else
		reg &= ~(1 << index);

	iowrite32(reg, tgpio->membase + offset);
	spin_unlock(&tgpio->lock);

	return 0;
}

static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
}

static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
{
	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	u32 value;

	value = ioread32(tgpio->membase + TGPIOVAL);
	return (value & (1 << nr)) ? 1 : 0;
}

static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
						unsigned nr, int val)
{
	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
}

static void timbgpio_gpio_set(struct gpio_chip *gpio,
				unsigned nr, int val)
{
	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
}

static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
{
	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);

	if (tgpio->irq_base <= 0)
		return -EINVAL;

	return tgpio->irq_base + offset;
}

/*
 * GPIO IRQ
 */
static void timbgpio_irq_disable(unsigned irq)
{
	struct timbgpio *tgpio = get_irq_chip_data(irq);
	int offset = irq - tgpio->irq_base;

	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
}

static void timbgpio_irq_enable(unsigned irq)
{
	struct timbgpio *tgpio = get_irq_chip_data(irq);
	int offset = irq - tgpio->irq_base;

	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
}

static int timbgpio_irq_type(unsigned irq, unsigned trigger)
{
	struct timbgpio *tgpio = get_irq_chip_data(irq);
	int offset = irq - tgpio->irq_base;
	unsigned long flags;
	u32 lvr, flr;

	if (offset < 0 || offset > tgpio->gpio.ngpio)
		return -EINVAL;

	spin_lock_irqsave(&tgpio->lock, flags);

	lvr = ioread32(tgpio->membase + TGPIO_LVR);
	flr = ioread32(tgpio->membase + TGPIO_FLR);

	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		flr &= ~(1 << offset);
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			lvr |= 1 << offset;
		else
			lvr &= ~(1 << offset);
	}

	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
		return -EINVAL;
	else {
		flr |= 1 << offset;
		/* opposite compared to the datasheet, but it mirrors the
		 * reality
		 */
		if (trigger & IRQ_TYPE_EDGE_FALLING)
			lvr |= 1 << offset;
		else
			lvr &= ~(1 << offset);
	}

	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
	iowrite32(flr, tgpio->membase + TGPIO_FLR);
	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
	spin_unlock_irqrestore(&tgpio->lock, flags);

	return 0;
}

static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
{
	struct timbgpio *tgpio = get_irq_data(irq);
	unsigned long ipr;
	int offset;

	desc->chip->ack(irq);
	ipr = ioread32(tgpio->membase + TGPIO_IPR);
	iowrite32(ipr, tgpio->membase + TGPIO_ICR);

	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
		generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
}

static struct irq_chip timbgpio_irqchip = {
	.name		= "GPIO",
	.enable		= timbgpio_irq_enable,
	.disable	= timbgpio_irq_disable,
	.set_type	= timbgpio_irq_type,
};

static int __devinit timbgpio_probe(struct platform_device *pdev)
{
	int err, i;
	struct gpio_chip *gc;
	struct timbgpio *tgpio;
	struct resource *iomem;
	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
	int irq = platform_get_irq(pdev, 0);

	if (!pdata || pdata->nr_pins > 32) {
		err = -EINVAL;
		goto err_mem;
	}

	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!iomem) {
		err = -EINVAL;
		goto err_mem;
	}

	tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
	if (!tgpio) {
		err = -EINVAL;
		goto err_mem;
	}
	tgpio->irq_base = pdata->irq_base;

	spin_lock_init(&tgpio->lock);

	if (!request_mem_region(iomem->start, resource_size(iomem),
		DRIVER_NAME)) {
		err = -EBUSY;
		goto err_request;
	}

	tgpio->membase = ioremap(iomem->start, resource_size(iomem));
	if (!tgpio->membase) {
		err = -ENOMEM;
		goto err_ioremap;
	}

	gc = &tgpio->gpio;

	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->dev = &pdev->dev;
	gc->direction_input = timbgpio_gpio_direction_input;
	gc->get = timbgpio_gpio_get;
	gc->direction_output = timbgpio_gpio_direction_output;
	gc->set = timbgpio_gpio_set;
	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	gc->dbg_show = NULL;
	gc->base = pdata->gpio_base;
	gc->ngpio = pdata->nr_pins;
	gc->can_sleep = 0;

	err = gpiochip_add(gc);
	if (err)
		goto err_chipadd;

	platform_set_drvdata(pdev, tgpio);

	/* make sure to disable interrupts */
	iowrite32(0x0, tgpio->membase + TGPIO_IER);

	if (irq < 0 || tgpio->irq_base <= 0)
		return 0;

	for (i = 0; i < pdata->nr_pins; i++) {
		set_irq_chip_and_handler_name(tgpio->irq_base + i,
			&timbgpio_irqchip, handle_simple_irq, "mux");
		set_irq_chip_data(tgpio->irq_base + i, tgpio);
#ifdef CONFIG_ARM
		set_irq_flags(tgpio->irq_base + i, IRQF_VALID | IRQF_PROBE);
#endif
	}

	set_irq_data(irq, tgpio);
	set_irq_chained_handler(irq, timbgpio_irq);

	return 0;

err_chipadd:
	iounmap(tgpio->membase);
err_ioremap:
	release_mem_region(iomem->start, resource_size(iomem));
err_request:
	kfree(tgpio);
err_mem:
	printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);

	return err;
}

static int __devexit timbgpio_remove(struct platform_device *pdev)
{
	int err;
	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
	struct timbgpio *tgpio = platform_get_drvdata(pdev);
	struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	int irq = platform_get_irq(pdev, 0);

	if (irq >= 0 && tgpio->irq_base > 0) {
		int i;
		for (i = 0; i < pdata->nr_pins; i++) {
			set_irq_chip(tgpio->irq_base + i, NULL);
			set_irq_chip_data(tgpio->irq_base + i, NULL);
		}

		set_irq_handler(irq, NULL);
		set_irq_data(irq, NULL);
	}

	err = gpiochip_remove(&tgpio->gpio);
	if (err)
		printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");

	iounmap(tgpio->membase);
	release_mem_region(iomem->start, resource_size(iomem));
	kfree(tgpio);

	platform_set_drvdata(pdev, NULL);

	return 0;
}

static struct platform_driver timbgpio_platform_driver = {
	.driver = {
		.name	= DRIVER_NAME,
		.owner	= THIS_MODULE,
	},
	.probe		= timbgpio_probe,
	.remove		= timbgpio_remove,
};

/*--------------------------------------------------------------------------*/

static int __init timbgpio_init(void)
{
	return platform_driver_register(&timbgpio_platform_driver);
}

static void __exit timbgpio_exit(void)
{
	platform_driver_unregister(&timbgpio_platform_driver);
}

module_init(timbgpio_init);
module_exit(timbgpio_exit);

MODULE_DESCRIPTION("Timberdale GPIO driver");
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Mocean Laboratories");
MODULE_ALIAS("platform:"DRIVER_NAME);
Commit	Line	Data
35570ac6 RR	1	/*
	2	* timbgpio.c timberdale FPGA GPIO driver
	3	* Copyright (c) 2009 Intel Corporation
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*/
	18
	19	/* Supports:
	20	* Timberdale FPGA GPIO
	21	*/
	22
	23	#include <linux/module.h>
	24	#include <linux/gpio.h>
	25	#include <linux/platform_device.h>
e3cb91ce	26	#include <linux/irq.h>
35570ac6 RR	27	#include <linux/io.h>
	28	#include <linux/timb_gpio.h>
	29	#include <linux/interrupt.h>
	30
	31	#define DRIVER_NAME "timb-gpio"
	32
	33	#define TGPIOVAL 0x00
	34	#define TGPIODIR 0x04
	35	#define TGPIO_IER 0x08
	36	#define TGPIO_ISR 0x0c
	37	#define TGPIO_IPR 0x10
	38	#define TGPIO_ICR 0x14
	39	#define TGPIO_FLR 0x18
	40	#define TGPIO_LVR 0x1c
	41
	42	struct timbgpio {
	43	void __iomem *membase;
	44	spinlock_t lock; /* mutual exclusion */
	45	struct gpio_chip gpio;
	46	int irq_base;
	47	};
	48
	49	static int timbgpio_update_bit(struct gpio_chip *gpio, unsigned index,
	50	unsigned offset, bool enabled)
	51	{
	52	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	53	u32 reg;
	54
	55	spin_lock(&tgpio->lock);
	56	reg = ioread32(tgpio->membase + offset);
	57
	58	if (enabled)
	59	reg \|= (1 << index);
	60	else
	61	reg &= ~(1 << index);
	62
	63	iowrite32(reg, tgpio->membase + offset);
	64	spin_unlock(&tgpio->lock);
	65
	66	return 0;
	67	}
	68
	69	static int timbgpio_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
	70	{
	71	return timbgpio_update_bit(gpio, nr, TGPIODIR, true);
	72	}
	73
	74	static int timbgpio_gpio_get(struct gpio_chip *gpio, unsigned nr)
	75	{
	76	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
	77	u32 value;
	78
	79	value = ioread32(tgpio->membase + TGPIOVAL);
	80	return (value & (1 << nr)) ? 1 : 0;
	81	}
	82
	83	static int timbgpio_gpio_direction_output(struct gpio_chip *gpio,
	84	unsigned nr, int val)
	85	{
	86	return timbgpio_update_bit(gpio, nr, TGPIODIR, false);
	87	}
	88
	89	static void timbgpio_gpio_set(struct gpio_chip *gpio,
	90	unsigned nr, int val)
91	{
92	timbgpio_update_bit(gpio, nr, TGPIOVAL, val != 0);
93	}
94
95	static int timbgpio_to_irq(struct gpio_chip *gpio, unsigned offset)
96	{
97	struct timbgpio *tgpio = container_of(gpio, struct timbgpio, gpio);
98
99	if (tgpio->irq_base <= 0)
100	return -EINVAL;
101
102	return tgpio->irq_base + offset;
103	}
104
105	/*
106	* GPIO IRQ
107	*/
108	static void timbgpio_irq_disable(unsigned irq)
109	{
110	struct timbgpio *tgpio = get_irq_chip_data(irq);
111	int offset = irq - tgpio->irq_base;
112
113	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 0);
114	}
115
116	static void timbgpio_irq_enable(unsigned irq)
117	{
118	struct timbgpio *tgpio = get_irq_chip_data(irq);
119	int offset = irq - tgpio->irq_base;
120
121	timbgpio_update_bit(&tgpio->gpio, offset, TGPIO_IER, 1);
122	}
123
124	static int timbgpio_irq_type(unsigned irq, unsigned trigger)
125	{
126	struct timbgpio *tgpio = get_irq_chip_data(irq);
127	int offset = irq - tgpio->irq_base;
128	unsigned long flags;
129	u32 lvr, flr;
130
131	if (offset < 0 \|\| offset > tgpio->gpio.ngpio)
132	return -EINVAL;
133
134	spin_lock_irqsave(&tgpio->lock, flags);
135
136	lvr = ioread32(tgpio->membase + TGPIO_LVR);
137	flr = ioread32(tgpio->membase + TGPIO_FLR);
138
139	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
140	flr &= ~(1 << offset);
141	if (trigger & IRQ_TYPE_LEVEL_HIGH)
142	lvr \|= 1 << offset;
143	else
144	lvr &= ~(1 << offset);
145	}
146
147	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
148	return -EINVAL;
149	else {
150	flr \|= 1 << offset;
151	/* opposite compared to the datasheet, but it mirrors the
152	* reality
153	*/
154	if (trigger & IRQ_TYPE_EDGE_FALLING)
155	lvr \|= 1 << offset;
156	else
157	lvr &= ~(1 << offset);
158	}
159
160	iowrite32(lvr, tgpio->membase + TGPIO_LVR);
161	iowrite32(flr, tgpio->membase + TGPIO_FLR);
162	iowrite32(1 << offset, tgpio->membase + TGPIO_ICR);
163	spin_unlock_irqrestore(&tgpio->lock, flags);
164
165	return 0;
166	}
167
168	static void timbgpio_irq(unsigned int irq, struct irq_desc *desc)
169	{
170	struct timbgpio *tgpio = get_irq_data(irq);
171	unsigned long ipr;
172	int offset;
173
174	desc->chip->ack(irq);
175	ipr = ioread32(tgpio->membase + TGPIO_IPR);
176	iowrite32(ipr, tgpio->membase + TGPIO_ICR);
177
984b3f57	178	for_each_set_bit(offset, &ipr, tgpio->gpio.ngpio)
35570ac6 RR	179	generic_handle_irq(timbgpio_to_irq(&tgpio->gpio, offset));
	180	}
	181
	182	static struct irq_chip timbgpio_irqchip = {
	183	.name = "GPIO",
	184	.enable = timbgpio_irq_enable,
	185	.disable = timbgpio_irq_disable,
	186	.set_type = timbgpio_irq_type,
	187	};
	188
	189	static int __devinit timbgpio_probe(struct platform_device *pdev)
	190	{
	191	int err, i;
	192	struct gpio_chip *gc;
	193	struct timbgpio *tgpio;
	194	struct resource *iomem;
	195	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
	196	int irq = platform_get_irq(pdev, 0);
	197
	198	if (!pdata \|\| pdata->nr_pins > 32) {
	199	err = -EINVAL;
	200	goto err_mem;
	201	}
	202
	203	iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	204	if (!iomem) {
	205	err = -EINVAL;
	206	goto err_mem;
	207	}
	208
	209	tgpio = kzalloc(sizeof(*tgpio), GFP_KERNEL);
	210	if (!tgpio) {
	211	err = -EINVAL;
	212	goto err_mem;
	213	}
	214	tgpio->irq_base = pdata->irq_base;
	215
	216	spin_lock_init(&tgpio->lock);
	217
	218	if (!request_mem_region(iomem->start, resource_size(iomem),
	219	DRIVER_NAME)) {
	220	err = -EBUSY;
	221	goto err_request;
	222	}
	223
	224	tgpio->membase = ioremap(iomem->start, resource_size(iomem));
	225	if (!tgpio->membase) {
	226	err = -ENOMEM;
	227	goto err_ioremap;
	228	}
	229
	230	gc = &tgpio->gpio;
	231
	232	gc->label = dev_name(&pdev->dev);
	233	gc->owner = THIS_MODULE;
	234	gc->dev = &pdev->dev;
	235	gc->direction_input = timbgpio_gpio_direction_input;
	236	gc->get = timbgpio_gpio_get;
	237	gc->direction_output = timbgpio_gpio_direction_output;
	238	gc->set = timbgpio_gpio_set;
	239	gc->to_irq = (irq >= 0 && tgpio->irq_base > 0) ? timbgpio_to_irq : NULL;
	240	gc->dbg_show = NULL;
	241	gc->base = pdata->gpio_base;
	242	gc->ngpio = pdata->nr_pins;
243	gc->can_sleep = 0;
244
245	err = gpiochip_add(gc);
246	if (err)
247	goto err_chipadd;
248
249	platform_set_drvdata(pdev, tgpio);
250
251	/* make sure to disable interrupts */
252	iowrite32(0x0, tgpio->membase + TGPIO_IER);
253
254	if (irq < 0 \|\| tgpio->irq_base <= 0)
255	return 0;
256
257	for (i = 0; i < pdata->nr_pins; i++) {
258	set_irq_chip_and_handler_name(tgpio->irq_base + i,
259	&timbgpio_irqchip, handle_simple_irq, "mux");
260	set_irq_chip_data(tgpio->irq_base + i, tgpio);
261	#ifdef CONFIG_ARM
262	set_irq_flags(tgpio->irq_base + i, IRQF_VALID \| IRQF_PROBE);
263	#endif
264	}
265
266	set_irq_data(irq, tgpio);
267	set_irq_chained_handler(irq, timbgpio_irq);
268
269	return 0;
270
271	err_chipadd:
272	iounmap(tgpio->membase);
273	err_ioremap:
274	release_mem_region(iomem->start, resource_size(iomem));
275	err_request:
276	kfree(tgpio);
277	err_mem:
278	printk(KERN_ERR DRIVER_NAME": Failed to register GPIOs: %d\n", err);
279
280	return err;
281	}
282
283	static int __devexit timbgpio_remove(struct platform_device *pdev)
284	{
285	int err;
286	struct timbgpio_platform_data *pdata = pdev->dev.platform_data;
287	struct timbgpio *tgpio = platform_get_drvdata(pdev);
288	struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
289	int irq = platform_get_irq(pdev, 0);
290
291	if (irq >= 0 && tgpio->irq_base > 0) {
292	int i;
293	for (i = 0; i < pdata->nr_pins; i++) {
294	set_irq_chip(tgpio->irq_base + i, NULL);
295	set_irq_chip_data(tgpio->irq_base + i, NULL);
296	}
297
298	set_irq_handler(irq, NULL);
299	set_irq_data(irq, NULL);
300	}
301
302	err = gpiochip_remove(&tgpio->gpio);
303	if (err)
304	printk(KERN_ERR DRIVER_NAME": failed to remove gpio_chip\n");
305
306	iounmap(tgpio->membase);
307	release_mem_region(iomem->start, resource_size(iomem));
308	kfree(tgpio);
309
310	platform_set_drvdata(pdev, NULL);
311
312	return 0;
313	}
314
315	static struct platform_driver timbgpio_platform_driver = {
316	.driver = {
317	.name = DRIVER_NAME,
318	.owner = THIS_MODULE,
319	},
320	.probe = timbgpio_probe,
321	.remove = timbgpio_remove,
322	};
323
324	/--------------------------------------------------------------------------/
325
326	static int __init timbgpio_init(void)
327	{
328	return platform_driver_register(&timbgpio_platform_driver);
329	}
330
331	static void __exit timbgpio_exit(void)
332	{
333	platform_driver_unregister(&timbgpio_platform_driver);
334	}
335
336	module_init(timbgpio_init);
337	module_exit(timbgpio_exit);
338
339	MODULE_DESCRIPTION("Timberdale GPIO driver");
340	MODULE_LICENSE("GPL v2");
341	MODULE_AUTHOR("Mocean Laboratories");
342	MODULE_ALIAS("platform:"DRIVER_NAME);
343