Commit | Line | Data |
---|---|---|
3c92db9a EG |
1 | /* |
2 | * arch/arm/mach-tegra/gpio.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/irq.h> | |
2e47b8b3 | 22 | #include <linux/interrupt.h> |
3c92db9a EG |
23 | #include <linux/io.h> |
24 | #include <linux/gpio.h> | |
df221227 | 25 | #include <linux/of.h> |
88d8951e SW |
26 | #include <linux/platform_device.h> |
27 | #include <linux/module.h> | |
6f74dc9b | 28 | #include <linux/irqdomain.h> |
3c92db9a | 29 | |
98022940 WD |
30 | #include <asm/mach/irq.h> |
31 | ||
ea5abbd2 | 32 | #include <mach/gpio-tegra.h> |
3c92db9a | 33 | #include <mach/iomap.h> |
2ea67fd1 | 34 | #include <mach/suspend.h> |
3c92db9a EG |
35 | |
36 | #define GPIO_BANK(x) ((x) >> 5) | |
37 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
38 | #define GPIO_BIT(x) ((x) & 0x7) | |
39 | ||
88d8951e | 40 | #define GPIO_REG(x) (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4) |
3c92db9a EG |
41 | |
42 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) | |
43 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) | |
44 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) | |
45 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) | |
46 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) | |
47 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) | |
48 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) | |
49 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) | |
50 | ||
51 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800) | |
52 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810) | |
53 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820) | |
54 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840) | |
55 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850) | |
56 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860) | |
57 | ||
58 | #define GPIO_INT_LVL_MASK 0x010101 | |
59 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
60 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
61 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
62 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
63 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
64 | ||
65 | struct tegra_gpio_bank { | |
66 | int bank; | |
67 | int irq; | |
68 | spinlock_t lvl_lock[4]; | |
2e47b8b3 CC |
69 | #ifdef CONFIG_PM |
70 | u32 cnf[4]; | |
71 | u32 out[4]; | |
72 | u32 oe[4]; | |
73 | u32 int_enb[4]; | |
74 | u32 int_lvl[4]; | |
75 | #endif | |
3c92db9a EG |
76 | }; |
77 | ||
6f74dc9b | 78 | static struct irq_domain irq_domain; |
88d8951e | 79 | static void __iomem *regs; |
3391811c SW |
80 | static u32 tegra_gpio_bank_count; |
81 | static struct tegra_gpio_bank *tegra_gpio_banks; | |
88d8951e SW |
82 | |
83 | static inline void tegra_gpio_writel(u32 val, u32 reg) | |
84 | { | |
85 | __raw_writel(val, regs + reg); | |
86 | } | |
87 | ||
88 | static inline u32 tegra_gpio_readl(u32 reg) | |
89 | { | |
90 | return __raw_readl(regs + reg); | |
91 | } | |
3c92db9a EG |
92 | |
93 | static int tegra_gpio_compose(int bank, int port, int bit) | |
94 | { | |
95 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
96 | } | |
97 | ||
98 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) | |
99 | { | |
100 | u32 val; | |
101 | ||
102 | val = 0x100 << GPIO_BIT(gpio); | |
103 | if (value) | |
104 | val |= 1 << GPIO_BIT(gpio); | |
88d8951e | 105 | tegra_gpio_writel(val, reg); |
3c92db9a EG |
106 | } |
107 | ||
108 | void tegra_gpio_enable(int gpio) | |
109 | { | |
110 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); | |
111 | } | |
112 | ||
113 | void tegra_gpio_disable(int gpio) | |
114 | { | |
115 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); | |
116 | } | |
117 | ||
118 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
119 | { | |
120 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); | |
121 | } | |
122 | ||
123 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |
124 | { | |
88d8951e | 125 | return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; |
3c92db9a EG |
126 | } |
127 | ||
128 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
129 | { | |
130 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); | |
131 | return 0; | |
132 | } | |
133 | ||
134 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
135 | int value) | |
136 | { | |
137 | tegra_gpio_set(chip, offset, value); | |
138 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); | |
139 | return 0; | |
140 | } | |
141 | ||
438a99c0 SW |
142 | static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
143 | { | |
6f74dc9b | 144 | return irq_domain_to_irq(&irq_domain, offset); |
438a99c0 | 145 | } |
3c92db9a EG |
146 | |
147 | static struct gpio_chip tegra_gpio_chip = { | |
148 | .label = "tegra-gpio", | |
149 | .direction_input = tegra_gpio_direction_input, | |
150 | .get = tegra_gpio_get, | |
151 | .direction_output = tegra_gpio_direction_output, | |
152 | .set = tegra_gpio_set, | |
438a99c0 | 153 | .to_irq = tegra_gpio_to_irq, |
3c92db9a | 154 | .base = 0, |
2e47b8b3 | 155 | .ngpio = TEGRA_NR_GPIOS, |
3c92db9a EG |
156 | }; |
157 | ||
37337a8d | 158 | static void tegra_gpio_irq_ack(struct irq_data *d) |
3c92db9a | 159 | { |
6f74dc9b | 160 | int gpio = d->hwirq; |
3c92db9a | 161 | |
88d8951e | 162 | tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); |
3c92db9a EG |
163 | } |
164 | ||
37337a8d | 165 | static void tegra_gpio_irq_mask(struct irq_data *d) |
3c92db9a | 166 | { |
6f74dc9b | 167 | int gpio = d->hwirq; |
3c92db9a EG |
168 | |
169 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); | |
170 | } | |
171 | ||
37337a8d | 172 | static void tegra_gpio_irq_unmask(struct irq_data *d) |
3c92db9a | 173 | { |
6f74dc9b | 174 | int gpio = d->hwirq; |
3c92db9a EG |
175 | |
176 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); | |
177 | } | |
178 | ||
37337a8d | 179 | static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
3c92db9a | 180 | { |
6f74dc9b | 181 | int gpio = d->hwirq; |
37337a8d | 182 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
3c92db9a EG |
183 | int port = GPIO_PORT(gpio); |
184 | int lvl_type; | |
185 | int val; | |
186 | unsigned long flags; | |
187 | ||
188 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
189 | case IRQ_TYPE_EDGE_RISING: | |
190 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
191 | break; | |
192 | ||
193 | case IRQ_TYPE_EDGE_FALLING: | |
194 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
195 | break; | |
196 | ||
197 | case IRQ_TYPE_EDGE_BOTH: | |
198 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
199 | break; | |
200 | ||
201 | case IRQ_TYPE_LEVEL_HIGH: | |
202 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
203 | break; | |
204 | ||
205 | case IRQ_TYPE_LEVEL_LOW: | |
206 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
207 | break; | |
208 | ||
209 | default: | |
210 | return -EINVAL; | |
211 | } | |
212 | ||
213 | spin_lock_irqsave(&bank->lvl_lock[port], flags); | |
214 | ||
88d8951e | 215 | val = tegra_gpio_readl(GPIO_INT_LVL(gpio)); |
3c92db9a EG |
216 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); |
217 | val |= lvl_type << GPIO_BIT(gpio); | |
88d8951e | 218 | tegra_gpio_writel(val, GPIO_INT_LVL(gpio)); |
3c92db9a EG |
219 | |
220 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
221 | ||
222 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
6845664a | 223 | __irq_set_handler_locked(d->irq, handle_level_irq); |
3c92db9a | 224 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
6845664a | 225 | __irq_set_handler_locked(d->irq, handle_edge_irq); |
3c92db9a EG |
226 | |
227 | return 0; | |
228 | } | |
229 | ||
230 | static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
231 | { | |
232 | struct tegra_gpio_bank *bank; | |
233 | int port; | |
234 | int pin; | |
235 | int unmasked = 0; | |
98022940 | 236 | struct irq_chip *chip = irq_desc_get_chip(desc); |
3c92db9a | 237 | |
98022940 | 238 | chained_irq_enter(chip, desc); |
3c92db9a | 239 | |
6845664a | 240 | bank = irq_get_handler_data(irq); |
3c92db9a EG |
241 | |
242 | for (port = 0; port < 4; port++) { | |
243 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | |
88d8951e SW |
244 | unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) & |
245 | tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
246 | u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
3c92db9a EG |
247 | |
248 | for_each_set_bit(pin, &sta, 8) { | |
88d8951e | 249 | tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio)); |
3c92db9a EG |
250 | |
251 | /* if gpio is edge triggered, clear condition | |
252 | * before executing the hander so that we don't | |
253 | * miss edges | |
254 | */ | |
255 | if (lvl & (0x100 << pin)) { | |
256 | unmasked = 1; | |
98022940 | 257 | chained_irq_exit(chip, desc); |
3c92db9a EG |
258 | } |
259 | ||
260 | generic_handle_irq(gpio_to_irq(gpio + pin)); | |
261 | } | |
262 | } | |
263 | ||
264 | if (!unmasked) | |
98022940 | 265 | chained_irq_exit(chip, desc); |
3c92db9a EG |
266 | |
267 | } | |
268 | ||
2e47b8b3 CC |
269 | #ifdef CONFIG_PM |
270 | void tegra_gpio_resume(void) | |
271 | { | |
272 | unsigned long flags; | |
c8309ef6 CC |
273 | int b; |
274 | int p; | |
2e47b8b3 CC |
275 | |
276 | local_irq_save(flags); | |
277 | ||
3391811c | 278 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
2e47b8b3 CC |
279 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
280 | ||
281 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
282 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
283 | tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio)); |
284 | tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio)); | |
285 | tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio)); | |
286 | tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); | |
287 | tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); | |
2e47b8b3 CC |
288 | } |
289 | } | |
290 | ||
291 | local_irq_restore(flags); | |
2e47b8b3 CC |
292 | } |
293 | ||
294 | void tegra_gpio_suspend(void) | |
295 | { | |
296 | unsigned long flags; | |
c8309ef6 CC |
297 | int b; |
298 | int p; | |
2e47b8b3 | 299 | |
2e47b8b3 | 300 | local_irq_save(flags); |
3391811c | 301 | for (b = 0; b < tegra_gpio_bank_count; b++) { |
2e47b8b3 CC |
302 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; |
303 | ||
304 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
305 | unsigned int gpio = (b<<5) | (p<<3); | |
88d8951e SW |
306 | bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio)); |
307 | bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio)); | |
308 | bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio)); | |
309 | bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio)); | |
310 | bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio)); | |
2e47b8b3 CC |
311 | } |
312 | } | |
313 | local_irq_restore(flags); | |
314 | } | |
315 | ||
37337a8d | 316 | static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable) |
2e47b8b3 | 317 | { |
37337a8d | 318 | struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d); |
6845664a | 319 | return irq_set_irq_wake(bank->irq, enable); |
2e47b8b3 CC |
320 | } |
321 | #endif | |
3c92db9a EG |
322 | |
323 | static struct irq_chip tegra_gpio_irq_chip = { | |
324 | .name = "GPIO", | |
37337a8d LB |
325 | .irq_ack = tegra_gpio_irq_ack, |
326 | .irq_mask = tegra_gpio_irq_mask, | |
327 | .irq_unmask = tegra_gpio_irq_unmask, | |
328 | .irq_set_type = tegra_gpio_irq_set_type, | |
2e47b8b3 | 329 | #ifdef CONFIG_PM |
37337a8d | 330 | .irq_set_wake = tegra_gpio_wake_enable, |
2e47b8b3 | 331 | #endif |
3c92db9a EG |
332 | }; |
333 | ||
334 | ||
335 | /* This lock class tells lockdep that GPIO irqs are in a different | |
336 | * category than their parents, so it won't report false recursion. | |
337 | */ | |
338 | static struct lock_class_key gpio_lock_class; | |
339 | ||
88d8951e | 340 | static int __devinit tegra_gpio_probe(struct platform_device *pdev) |
3c92db9a | 341 | { |
3391811c | 342 | int irq_base; |
88d8951e | 343 | struct resource *res; |
3c92db9a | 344 | struct tegra_gpio_bank *bank; |
47008001 | 345 | int gpio; |
3c92db9a EG |
346 | int i; |
347 | int j; | |
348 | ||
3391811c SW |
349 | for (;;) { |
350 | res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count); | |
351 | if (!res) | |
352 | break; | |
353 | tegra_gpio_bank_count++; | |
354 | } | |
355 | if (!tegra_gpio_bank_count) { | |
356 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
357 | return -ENODEV; | |
358 | } | |
359 | ||
360 | tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32; | |
361 | ||
362 | tegra_gpio_banks = devm_kzalloc(&pdev->dev, | |
363 | tegra_gpio_bank_count * sizeof(*tegra_gpio_banks), | |
364 | GFP_KERNEL); | |
365 | if (!tegra_gpio_banks) { | |
366 | dev_err(&pdev->dev, "Couldn't allocate bank structure\n"); | |
367 | return -ENODEV; | |
368 | } | |
369 | ||
370 | irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0); | |
371 | if (irq_base < 0) { | |
6f74dc9b SW |
372 | dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n"); |
373 | return -ENODEV; | |
374 | } | |
3391811c SW |
375 | irq_domain.irq_base = irq_base; |
376 | irq_domain.nr_irq = tegra_gpio_chip.ngpio; | |
6f74dc9b SW |
377 | irq_domain.ops = &irq_domain_simple_ops; |
378 | irq_domain.of_node = pdev->dev.of_node; | |
379 | irq_domain_add(&irq_domain); | |
380 | ||
3391811c | 381 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
88d8951e SW |
382 | res = platform_get_resource(pdev, IORESOURCE_IRQ, i); |
383 | if (!res) { | |
384 | dev_err(&pdev->dev, "Missing IRQ resource\n"); | |
385 | return -ENODEV; | |
386 | } | |
387 | ||
388 | bank = &tegra_gpio_banks[i]; | |
389 | bank->bank = i; | |
390 | bank->irq = res->start; | |
391 | } | |
392 | ||
393 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
394 | if (!res) { | |
395 | dev_err(&pdev->dev, "Missing MEM resource\n"); | |
396 | return -ENODEV; | |
397 | } | |
398 | ||
aedd4fdf | 399 | regs = devm_request_and_ioremap(&pdev->dev, res); |
88d8951e SW |
400 | if (!regs) { |
401 | dev_err(&pdev->dev, "Couldn't ioremap regs\n"); | |
402 | return -ENODEV; | |
403 | } | |
404 | ||
3c92db9a EG |
405 | for (i = 0; i < 7; i++) { |
406 | for (j = 0; j < 4; j++) { | |
407 | int gpio = tegra_gpio_compose(i, j, 0); | |
88d8951e | 408 | tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio)); |
3c92db9a EG |
409 | } |
410 | } | |
411 | ||
df221227 | 412 | #ifdef CONFIG_OF_GPIO |
88d8951e SW |
413 | tegra_gpio_chip.of_node = pdev->dev.of_node; |
414 | #endif | |
df221227 | 415 | |
3c92db9a EG |
416 | gpiochip_add(&tegra_gpio_chip); |
417 | ||
3391811c | 418 | for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) { |
6f74dc9b | 419 | int irq = irq_domain_to_irq(&irq_domain, gpio); |
47008001 | 420 | /* No validity check; all Tegra GPIOs are valid IRQs */ |
3c92db9a | 421 | |
47008001 | 422 | bank = &tegra_gpio_banks[GPIO_BANK(gpio)]; |
3c92db9a | 423 | |
47008001 SW |
424 | irq_set_lockdep_class(irq, &gpio_lock_class); |
425 | irq_set_chip_data(irq, bank); | |
426 | irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip, | |
f38c02f3 | 427 | handle_simple_irq); |
47008001 | 428 | set_irq_flags(irq, IRQF_VALID); |
3c92db9a EG |
429 | } |
430 | ||
3391811c | 431 | for (i = 0; i < tegra_gpio_bank_count; i++) { |
3c92db9a EG |
432 | bank = &tegra_gpio_banks[i]; |
433 | ||
6845664a TG |
434 | irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler); |
435 | irq_set_handler_data(bank->irq, bank); | |
3c92db9a EG |
436 | |
437 | for (j = 0; j < 4; j++) | |
438 | spin_lock_init(&bank->lvl_lock[j]); | |
439 | } | |
440 | ||
441 | return 0; | |
442 | } | |
443 | ||
88d8951e SW |
444 | static struct of_device_id tegra_gpio_of_match[] __devinitdata = { |
445 | { .compatible = "nvidia,tegra20-gpio", }, | |
446 | { }, | |
447 | }; | |
448 | ||
449 | static struct platform_driver tegra_gpio_driver = { | |
450 | .driver = { | |
451 | .name = "tegra-gpio", | |
452 | .owner = THIS_MODULE, | |
453 | .of_match_table = tegra_gpio_of_match, | |
454 | }, | |
455 | .probe = tegra_gpio_probe, | |
456 | }; | |
457 | ||
458 | static int __init tegra_gpio_init(void) | |
459 | { | |
460 | return platform_driver_register(&tegra_gpio_driver); | |
461 | } | |
3c92db9a EG |
462 | postcore_initcall(tegra_gpio_init); |
463 | ||
632095ea OJ |
464 | void __init tegra_gpio_config(struct tegra_gpio_table *table, int num) |
465 | { | |
466 | int i; | |
467 | ||
468 | for (i = 0; i < num; i++) { | |
469 | int gpio = table[i].gpio; | |
470 | ||
471 | if (table[i].enable) | |
472 | tegra_gpio_enable(gpio); | |
473 | else | |
474 | tegra_gpio_disable(gpio); | |
475 | } | |
476 | } | |
477 | ||
3c92db9a EG |
478 | #ifdef CONFIG_DEBUG_FS |
479 | ||
480 | #include <linux/debugfs.h> | |
481 | #include <linux/seq_file.h> | |
482 | ||
483 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
484 | { | |
485 | int i; | |
486 | int j; | |
487 | ||
488 | for (i = 0; i < 7; i++) { | |
489 | for (j = 0; j < 4; j++) { | |
490 | int gpio = tegra_gpio_compose(i, j, 0); | |
2e47b8b3 CC |
491 | seq_printf(s, |
492 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", | |
493 | i, j, | |
88d8951e SW |
494 | tegra_gpio_readl(GPIO_CNF(gpio)), |
495 | tegra_gpio_readl(GPIO_OE(gpio)), | |
496 | tegra_gpio_readl(GPIO_OUT(gpio)), | |
497 | tegra_gpio_readl(GPIO_IN(gpio)), | |
498 | tegra_gpio_readl(GPIO_INT_STA(gpio)), | |
499 | tegra_gpio_readl(GPIO_INT_ENB(gpio)), | |
500 | tegra_gpio_readl(GPIO_INT_LVL(gpio))); | |
3c92db9a EG |
501 | } |
502 | } | |
503 | return 0; | |
504 | } | |
505 | ||
506 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
507 | { | |
508 | return single_open(file, dbg_gpio_show, &inode->i_private); | |
509 | } | |
510 | ||
511 | static const struct file_operations debug_fops = { | |
512 | .open = dbg_gpio_open, | |
513 | .read = seq_read, | |
514 | .llseek = seq_lseek, | |
515 | .release = single_release, | |
516 | }; | |
517 | ||
518 | static int __init tegra_gpio_debuginit(void) | |
519 | { | |
520 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, | |
521 | NULL, NULL, &debug_fops); | |
522 | return 0; | |
523 | } | |
524 | late_initcall(tegra_gpio_debuginit); | |
525 | #endif |