[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-tegra.c

/*
 * arch/arm/mach-tegra/gpio.c
 *
 * Copyright (c) 2010 Google, Inc
 *
 * Author:
 *	Erik Gilling <konkers@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/module.h>
#include <linux/irqdomain.h>

#include <asm/mach/irq.h>

#include <mach/gpio-tegra.h>
#include <mach/iomap.h>
#include <mach/suspend.h>

#define GPIO_BANK(x)		((x) >> 5)
#define GPIO_PORT(x)		(((x) >> 3) & 0x3)
#define GPIO_BIT(x)		((x) & 0x7)

#define GPIO_REG(x)		(GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4)

#define GPIO_CNF(x)		(GPIO_REG(x) + 0x00)
#define GPIO_OE(x)		(GPIO_REG(x) + 0x10)
#define GPIO_OUT(x)		(GPIO_REG(x) + 0X20)
#define GPIO_IN(x)		(GPIO_REG(x) + 0x30)
#define GPIO_INT_STA(x)		(GPIO_REG(x) + 0x40)
#define GPIO_INT_ENB(x)		(GPIO_REG(x) + 0x50)
#define GPIO_INT_LVL(x)		(GPIO_REG(x) + 0x60)
#define GPIO_INT_CLR(x)		(GPIO_REG(x) + 0x70)

#define GPIO_MSK_CNF(x)		(GPIO_REG(x) + 0x800)
#define GPIO_MSK_OE(x)		(GPIO_REG(x) + 0x810)
#define GPIO_MSK_OUT(x)		(GPIO_REG(x) + 0X820)
#define GPIO_MSK_INT_STA(x)	(GPIO_REG(x) + 0x840)
#define GPIO_MSK_INT_ENB(x)	(GPIO_REG(x) + 0x850)
#define GPIO_MSK_INT_LVL(x)	(GPIO_REG(x) + 0x860)

#define GPIO_INT_LVL_MASK		0x010101
#define GPIO_INT_LVL_EDGE_RISING	0x000101
#define GPIO_INT_LVL_EDGE_FALLING	0x000100
#define GPIO_INT_LVL_EDGE_BOTH		0x010100
#define GPIO_INT_LVL_LEVEL_HIGH		0x000001
#define GPIO_INT_LVL_LEVEL_LOW		0x000000

struct tegra_gpio_bank {
	int bank;
	int irq;
	spinlock_t lvl_lock[4];
#ifdef CONFIG_PM
	u32 cnf[4];
	u32 out[4];
	u32 oe[4];
	u32 int_enb[4];
	u32 int_lvl[4];
#endif
};

static struct irq_domain *irq_domain;
static void __iomem *regs;
static u32 tegra_gpio_bank_count;
static struct tegra_gpio_bank *tegra_gpio_banks;

static inline void tegra_gpio_writel(u32 val, u32 reg)
{
	__raw_writel(val, regs + reg);
}

static inline u32 tegra_gpio_readl(u32 reg)
{
	return __raw_readl(regs + reg);
}

static int tegra_gpio_compose(int bank, int port, int bit)
{
	return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
}

static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
{
	u32 val;

	val = 0x100 << GPIO_BIT(gpio);
	if (value)
		val |= 1 << GPIO_BIT(gpio);
	tegra_gpio_writel(val, reg);
}

void tegra_gpio_enable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
}
EXPORT_SYMBOL_GPL(tegra_gpio_enable);

void tegra_gpio_disable(int gpio)
{
	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
}
EXPORT_SYMBOL_GPL(tegra_gpio_disable);

static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
}

static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
}

static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	return 0;
}

static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
					int value)
{
	tegra_gpio_set(chip, offset, value);
	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	return 0;
}

static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	return irq_find_mapping(irq_domain, offset);
}

static struct gpio_chip tegra_gpio_chip = {
	.label			= "tegra-gpio",
	.direction_input	= tegra_gpio_direction_input,
	.get			= tegra_gpio_get,
	.direction_output	= tegra_gpio_direction_output,
	.set			= tegra_gpio_set,
	.to_irq			= tegra_gpio_to_irq,
	.base			= 0,
	.ngpio			= TEGRA_NR_GPIOS,
};

static void tegra_gpio_irq_ack(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
}

static void tegra_gpio_irq_mask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
}

static void tegra_gpio_irq_unmask(struct irq_data *d)
{
	int gpio = d->hwirq;

	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
}

static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
{
	int gpio = d->hwirq;
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	int port = GPIO_PORT(gpio);
	int lvl_type;
	int val;
	unsigned long flags;

	switch (type & IRQ_TYPE_SENSE_MASK) {
	case IRQ_TYPE_EDGE_RISING:
		lvl_type = GPIO_INT_LVL_EDGE_RISING;
		break;

	case IRQ_TYPE_EDGE_FALLING:
		lvl_type = GPIO_INT_LVL_EDGE_FALLING;
		break;

	case IRQ_TYPE_EDGE_BOTH:
		lvl_type = GPIO_INT_LVL_EDGE_BOTH;
		break;

	case IRQ_TYPE_LEVEL_HIGH:
		lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
		break;

	case IRQ_TYPE_LEVEL_LOW:
		lvl_type = GPIO_INT_LVL_LEVEL_LOW;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&bank->lvl_lock[port], flags);

	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
	val |= lvl_type << GPIO_BIT(gpio);
	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));

	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);

	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
		__irq_set_handler_locked(d->irq, handle_level_irq);
	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
		__irq_set_handler_locked(d->irq, handle_edge_irq);

	return 0;
}

static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
{
	struct tegra_gpio_bank *bank;
	int port;
	int pin;
	int unmasked = 0;
	struct irq_chip *chip = irq_desc_get_chip(desc);

	chained_irq_enter(chip, desc);

	bank = irq_get_handler_data(irq);

	for (port = 0; port < 4; port++) {
		int gpio = tegra_gpio_compose(bank->bank, port, 0);
		unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
			tegra_gpio_readl(GPIO_INT_ENB(gpio));
		u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));

		for_each_set_bit(pin, &sta, 8) {
			tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));

			/* if gpio is edge triggered, clear condition
			 * before executing the hander so that we don't
			 * miss edges
			 */
			if (lvl & (0x100 << pin)) {
				unmasked = 1;
				chained_irq_exit(chip, desc);
			}

			generic_handle_irq(gpio_to_irq(gpio + pin));
		}
	}

	if (!unmasked)
		chained_irq_exit(chip, desc);

}

#ifdef CONFIG_PM
void tegra_gpio_resume(void)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);

	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
			tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
			tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
			tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
			tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
		}
	}

	local_irq_restore(flags);
}

void tegra_gpio_suspend(void)
{
	unsigned long flags;
	int b;
	int p;

	local_irq_save(flags);
	for (b = 0; b < tegra_gpio_bank_count; b++) {
		struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];

		for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
			unsigned int gpio = (b<<5) | (p<<3);
			bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
			bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
			bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
			bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
			bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
		}
	}
	local_irq_restore(flags);
}

static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
{
	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
	return irq_set_irq_wake(bank->irq, enable);
}
#endif

static struct irq_chip tegra_gpio_irq_chip = {
	.name		= "GPIO",
	.irq_ack	= tegra_gpio_irq_ack,
	.irq_mask	= tegra_gpio_irq_mask,
	.irq_unmask	= tegra_gpio_irq_unmask,
	.irq_set_type	= tegra_gpio_irq_set_type,
#ifdef CONFIG_PM
	.irq_set_wake	= tegra_gpio_wake_enable,
#endif
};


/* This lock class tells lockdep that GPIO irqs are in a different
 * category than their parents, so it won't report false recursion.
 */
static struct lock_class_key gpio_lock_class;

static int __devinit tegra_gpio_probe(struct platform_device *pdev)
{
	int irq_base;
	struct resource *res;
	struct tegra_gpio_bank *bank;
	int gpio;
	int i;
	int j;

	for (;;) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
		if (!res)
			break;
		tegra_gpio_bank_count++;
	}
	if (!tegra_gpio_bank_count) {
		dev_err(&pdev->dev, "Missing IRQ resource\n");
		return -ENODEV;
	}

	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;

	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
			tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
			GFP_KERNEL);
	if (!tegra_gpio_banks) {
		dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
		return -ENODEV;
	}

	irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0);
	if (irq_base < 0) {
		dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n");
		return -ENODEV;
	}
	irq_domain = irq_domain_add_legacy(pdev->dev.of_node,
					   tegra_gpio_chip.ngpio, irq_base, 0,
					   &irq_domain_simple_ops, NULL);

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
		if (!res) {
			dev_err(&pdev->dev, "Missing IRQ resource\n");
			return -ENODEV;
		}

		bank = &tegra_gpio_banks[i];
		bank->bank = i;
		bank->irq = res->start;
	}

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res) {
		dev_err(&pdev->dev, "Missing MEM resource\n");
		return -ENODEV;
	}

	regs = devm_request_and_ioremap(&pdev->dev, res);
	if (!regs) {
		dev_err(&pdev->dev, "Couldn't ioremap regs\n");
		return -ENODEV;
	}

	for (i = 0; i < 7; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
		}
	}

#ifdef CONFIG_OF_GPIO
	tegra_gpio_chip.of_node = pdev->dev.of_node;
#endif

	gpiochip_add(&tegra_gpio_chip);

	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
		int irq = irq_find_mapping(irq_domain, gpio);
		/* No validity check; all Tegra GPIOs are valid IRQs */

		bank = &tegra_gpio_banks[GPIO_BANK(gpio)];

		irq_set_lockdep_class(irq, &gpio_lock_class);
		irq_set_chip_data(irq, bank);
		irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
					 handle_simple_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	for (i = 0; i < tegra_gpio_bank_count; i++) {
		bank = &tegra_gpio_banks[i];

		irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
		irq_set_handler_data(bank->irq, bank);

		for (j = 0; j < 4; j++)
			spin_lock_init(&bank->lvl_lock[j]);
	}

	return 0;
}

static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
	{ .compatible = "nvidia,tegra20-gpio", },
	{ },
};

static struct platform_driver tegra_gpio_driver = {
	.driver		= {
		.name	= "tegra-gpio",
		.owner	= THIS_MODULE,
		.of_match_table = tegra_gpio_of_match,
	},
	.probe		= tegra_gpio_probe,
};

static int __init tegra_gpio_init(void)
{
	return platform_driver_register(&tegra_gpio_driver);
}
postcore_initcall(tegra_gpio_init);

void tegra_gpio_config(struct tegra_gpio_table *table, int num)
{
	int i;

	for (i = 0; i < num; i++) {
		int gpio = table[i].gpio;

		if (table[i].enable)
			tegra_gpio_enable(gpio);
		else
			tegra_gpio_disable(gpio);
	}
}

#ifdef	CONFIG_DEBUG_FS

#include <linux/debugfs.h>
#include <linux/seq_file.h>

static int dbg_gpio_show(struct seq_file *s, void *unused)
{
	int i;
	int j;

	for (i = 0; i < 7; i++) {
		for (j = 0; j < 4; j++) {
			int gpio = tegra_gpio_compose(i, j, 0);
			seq_printf(s,
				"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
				i, j,
				tegra_gpio_readl(GPIO_CNF(gpio)),
				tegra_gpio_readl(GPIO_OE(gpio)),
				tegra_gpio_readl(GPIO_OUT(gpio)),
				tegra_gpio_readl(GPIO_IN(gpio)),
				tegra_gpio_readl(GPIO_INT_STA(gpio)),
				tegra_gpio_readl(GPIO_INT_ENB(gpio)),
				tegra_gpio_readl(GPIO_INT_LVL(gpio)));
		}
	}
	return 0;
}

static int dbg_gpio_open(struct inode *inode, struct file *file)
{
	return single_open(file, dbg_gpio_show, &inode->i_private);
}

static const struct file_operations debug_fops = {
	.open		= dbg_gpio_open,
	.read		= seq_read,
	.llseek		= seq_lseek,
	.release	= single_release,
};

static int __init tegra_gpio_debuginit(void)
{
	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
					NULL, NULL, &debug_fops);
	return 0;
}
late_initcall(tegra_gpio_debuginit);
#endif
Commit	Line	Data
3c92db9a EG	1	/*
	2	* arch/arm/mach-tegra/gpio.c
	3	*
	4	* Copyright (c) 2010 Google, Inc
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/irq.h>
2e47b8b3	22	#include <linux/interrupt.h>
3c92db9a EG	23	#include <linux/io.h>
3c92db9a EG	24	#include <linux/gpio.h>
df221227	25	#include <linux/of.h>
88d8951e SW	26	#include <linux/platform_device.h>
88d8951e SW	27	#include <linux/module.h>
6f74dc9b	28	#include <linux/irqdomain.h>
3c92db9a	29
98022940 WD	30	#include <asm/mach/irq.h>
98022940 WD	31
ea5abbd2	32	#include <mach/gpio-tegra.h>
3c92db9a	33	#include <mach/iomap.h>
2ea67fd1	34	#include <mach/suspend.h>
3c92db9a EG	35
	36	#define GPIO_BANK(x) ((x) >> 5)
	37	#define GPIO_PORT(x) (((x) >> 3) & 0x3)
	38	#define GPIO_BIT(x) ((x) & 0x7)
	39
88d8951e	40	#define GPIO_REG(x) (GPIO_BANK(x) * 0x80 + GPIO_PORT(x) * 4)
3c92db9a EG	41
	42	#define GPIO_CNF(x) (GPIO_REG(x) + 0x00)
	43	#define GPIO_OE(x) (GPIO_REG(x) + 0x10)
	44	#define GPIO_OUT(x) (GPIO_REG(x) + 0X20)
	45	#define GPIO_IN(x) (GPIO_REG(x) + 0x30)
	46	#define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40)
	47	#define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50)
	48	#define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60)
	49	#define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70)
	50
	51	#define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800)
	52	#define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810)
	53	#define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820)
	54	#define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840)
	55	#define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850)
	56	#define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860)
	57
	58	#define GPIO_INT_LVL_MASK 0x010101
	59	#define GPIO_INT_LVL_EDGE_RISING 0x000101
	60	#define GPIO_INT_LVL_EDGE_FALLING 0x000100
	61	#define GPIO_INT_LVL_EDGE_BOTH 0x010100
	62	#define GPIO_INT_LVL_LEVEL_HIGH 0x000001
	63	#define GPIO_INT_LVL_LEVEL_LOW 0x000000
	64
	65	struct tegra_gpio_bank {
	66	int bank;
	67	int irq;
	68	spinlock_t lvl_lock[4];
2e47b8b3 CC	69	#ifdef CONFIG_PM
	70	u32 cnf[4];
	71	u32 out[4];
	72	u32 oe[4];
	73	u32 int_enb[4];
	74	u32 int_lvl[4];
	75	#endif
3c92db9a EG	76	};
3c92db9a EG	77
bdc93a77	78	static struct irq_domain *irq_domain;
88d8951e	79	static void __iomem *regs;
3391811c SW	80	static u32 tegra_gpio_bank_count;
3391811c SW	81	static struct tegra_gpio_bank *tegra_gpio_banks;
88d8951e SW	82
	83	static inline void tegra_gpio_writel(u32 val, u32 reg)
	84	{
	85	__raw_writel(val, regs + reg);
	86	}
	87
	88	static inline u32 tegra_gpio_readl(u32 reg)
	89	{
	90	return __raw_readl(regs + reg);
	91	}
3c92db9a EG	92
	93	static int tegra_gpio_compose(int bank, int port, int bit)
	94	{
	95	return (bank << 5) \| ((port & 0x3) << 3) \| (bit & 0x7);
	96	}
	97
	98	static void tegra_gpio_mask_write(u32 reg, int gpio, int value)
	99	{
	100	u32 val;
	101
	102	val = 0x100 << GPIO_BIT(gpio);
	103	if (value)
	104	val \|= 1 << GPIO_BIT(gpio);
88d8951e	105	tegra_gpio_writel(val, reg);
3c92db9a EG	106	}
	107
	108	void tegra_gpio_enable(int gpio)
	109	{
	110	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1);
	111	}
691e06c0	112	EXPORT_SYMBOL_GPL(tegra_gpio_enable);
3c92db9a EG	113
	114	void tegra_gpio_disable(int gpio)
	115	{
	116	tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0);
	117	}
691e06c0	118	EXPORT_SYMBOL_GPL(tegra_gpio_disable);
3c92db9a EG	119
	120	static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	121	{
	122	tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value);
	123	}
	124
	125	static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset)
	126	{
88d8951e	127	return (tegra_gpio_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1;
3c92db9a EG	128	}
	129
	130	static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	131	{
	132	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0);
	133	return 0;
	134	}
	135
	136	static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	137	int value)
	138	{
	139	tegra_gpio_set(chip, offset, value);
	140	tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1);
	141	return 0;
	142	}
	143
438a99c0 SW	144	static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
438a99c0 SW	145	{
bdc93a77	146	return irq_find_mapping(irq_domain, offset);
438a99c0	147	}
3c92db9a EG	148
	149	static struct gpio_chip tegra_gpio_chip = {
	150	.label = "tegra-gpio",
	151	.direction_input = tegra_gpio_direction_input,
	152	.get = tegra_gpio_get,
	153	.direction_output = tegra_gpio_direction_output,
	154	.set = tegra_gpio_set,
438a99c0	155	.to_irq = tegra_gpio_to_irq,
3c92db9a	156	.base = 0,
2e47b8b3	157	.ngpio = TEGRA_NR_GPIOS,
3c92db9a EG	158	};
3c92db9a EG	159
37337a8d	160	static void tegra_gpio_irq_ack(struct irq_data *d)
3c92db9a	161	{
6f74dc9b	162	int gpio = d->hwirq;
3c92db9a	163
88d8951e	164	tegra_gpio_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio));
3c92db9a EG	165	}
3c92db9a EG	166
37337a8d	167	static void tegra_gpio_irq_mask(struct irq_data *d)
3c92db9a	168	{
6f74dc9b	169	int gpio = d->hwirq;
3c92db9a EG	170
	171	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0);
	172	}
	173
37337a8d	174	static void tegra_gpio_irq_unmask(struct irq_data *d)
3c92db9a	175	{
6f74dc9b	176	int gpio = d->hwirq;
3c92db9a EG	177
	178	tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1);
	179	}
	180
37337a8d	181	static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
3c92db9a	182	{
6f74dc9b	183	int gpio = d->hwirq;
37337a8d	184	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
3c92db9a EG	185	int port = GPIO_PORT(gpio);
	186	int lvl_type;
	187	int val;
	188	unsigned long flags;
	189
	190	switch (type & IRQ_TYPE_SENSE_MASK) {
	191	case IRQ_TYPE_EDGE_RISING:
	192	lvl_type = GPIO_INT_LVL_EDGE_RISING;
	193	break;
	194
	195	case IRQ_TYPE_EDGE_FALLING:
	196	lvl_type = GPIO_INT_LVL_EDGE_FALLING;
	197	break;
	198
	199	case IRQ_TYPE_EDGE_BOTH:
	200	lvl_type = GPIO_INT_LVL_EDGE_BOTH;
	201	break;
	202
	203	case IRQ_TYPE_LEVEL_HIGH:
	204	lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
	205	break;
	206
	207	case IRQ_TYPE_LEVEL_LOW:
	208	lvl_type = GPIO_INT_LVL_LEVEL_LOW;
	209	break;
	210
	211	default:
	212	return -EINVAL;
	213	}
	214
	215	spin_lock_irqsave(&bank->lvl_lock[port], flags);
	216
88d8951e	217	val = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	218	val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
3c92db9a EG	219	val \|= lvl_type << GPIO_BIT(gpio);
88d8951e	220	tegra_gpio_writel(val, GPIO_INT_LVL(gpio));
3c92db9a EG	221
	222	spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
	223
	224	if (type & (IRQ_TYPE_LEVEL_LOW \| IRQ_TYPE_LEVEL_HIGH))
6845664a	225	__irq_set_handler_locked(d->irq, handle_level_irq);
3c92db9a	226	else if (type & (IRQ_TYPE_EDGE_FALLING \| IRQ_TYPE_EDGE_RISING))
6845664a	227	__irq_set_handler_locked(d->irq, handle_edge_irq);
3c92db9a EG	228
	229	return 0;
	230	}
	231
	232	static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
	233	{
	234	struct tegra_gpio_bank *bank;
	235	int port;
	236	int pin;
	237	int unmasked = 0;
98022940	238	struct irq_chip *chip = irq_desc_get_chip(desc);
3c92db9a	239
98022940	240	chained_irq_enter(chip, desc);
3c92db9a	241
6845664a	242	bank = irq_get_handler_data(irq);
3c92db9a EG	243
	244	for (port = 0; port < 4; port++) {
	245	int gpio = tegra_gpio_compose(bank->bank, port, 0);
88d8951e SW	246	unsigned long sta = tegra_gpio_readl(GPIO_INT_STA(gpio)) &
	247	tegra_gpio_readl(GPIO_INT_ENB(gpio));
	248	u32 lvl = tegra_gpio_readl(GPIO_INT_LVL(gpio));
3c92db9a EG	249
3c92db9a EG	250	for_each_set_bit(pin, &sta, 8) {
88d8951e	251	tegra_gpio_writel(1 << pin, GPIO_INT_CLR(gpio));
3c92db9a EG	252
	253	/* if gpio is edge triggered, clear condition
	254	* before executing the hander so that we don't
	255	* miss edges
	256	*/
	257	if (lvl & (0x100 << pin)) {
	258	unmasked = 1;
98022940	259	chained_irq_exit(chip, desc);
3c92db9a EG	260	}
	261
	262	generic_handle_irq(gpio_to_irq(gpio + pin));
	263	}
	264	}
	265
	266	if (!unmasked)
98022940	267	chained_irq_exit(chip, desc);
3c92db9a EG	268
	269	}
	270
2e47b8b3 CC	271	#ifdef CONFIG_PM
	272	void tegra_gpio_resume(void)
	273	{
	274	unsigned long flags;
c8309ef6 CC	275	int b;
c8309ef6 CC	276	int p;
2e47b8b3 CC	277
	278	local_irq_save(flags);
	279
3391811c	280	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	281	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	282
	283	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	284	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	285	tegra_gpio_writel(bank->cnf[p], GPIO_CNF(gpio));
	286	tegra_gpio_writel(bank->out[p], GPIO_OUT(gpio));
	287	tegra_gpio_writel(bank->oe[p], GPIO_OE(gpio));
	288	tegra_gpio_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio));
	289	tegra_gpio_writel(bank->int_enb[p], GPIO_INT_ENB(gpio));
2e47b8b3 CC	290	}
	291	}
	292
	293	local_irq_restore(flags);
2e47b8b3 CC	294	}
	295
	296	void tegra_gpio_suspend(void)
	297	{
	298	unsigned long flags;
c8309ef6 CC	299	int b;
c8309ef6 CC	300	int p;
2e47b8b3	301
2e47b8b3	302	local_irq_save(flags);
3391811c	303	for (b = 0; b < tegra_gpio_bank_count; b++) {
2e47b8b3 CC	304	struct tegra_gpio_bank *bank = &tegra_gpio_banks[b];
	305
	306	for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
	307	unsigned int gpio = (b<<5) \| (p<<3);
88d8951e SW	308	bank->cnf[p] = tegra_gpio_readl(GPIO_CNF(gpio));
	309	bank->out[p] = tegra_gpio_readl(GPIO_OUT(gpio));
	310	bank->oe[p] = tegra_gpio_readl(GPIO_OE(gpio));
	311	bank->int_enb[p] = tegra_gpio_readl(GPIO_INT_ENB(gpio));
	312	bank->int_lvl[p] = tegra_gpio_readl(GPIO_INT_LVL(gpio));
2e47b8b3 CC	313	}
	314	}
	315	local_irq_restore(flags);
	316	}
	317
37337a8d	318	static int tegra_gpio_wake_enable(struct irq_data *d, unsigned int enable)
2e47b8b3	319	{
37337a8d	320	struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
6845664a	321	return irq_set_irq_wake(bank->irq, enable);
2e47b8b3 CC	322	}
2e47b8b3 CC	323	#endif
3c92db9a EG	324
	325	static struct irq_chip tegra_gpio_irq_chip = {
	326	.name = "GPIO",
37337a8d LB	327	.irq_ack = tegra_gpio_irq_ack,
	328	.irq_mask = tegra_gpio_irq_mask,
	329	.irq_unmask = tegra_gpio_irq_unmask,
	330	.irq_set_type = tegra_gpio_irq_set_type,
2e47b8b3	331	#ifdef CONFIG_PM
37337a8d	332	.irq_set_wake = tegra_gpio_wake_enable,
2e47b8b3	333	#endif
3c92db9a EG	334	};
	335
	336
	337	/* This lock class tells lockdep that GPIO irqs are in a different
	338	* category than their parents, so it won't report false recursion.
	339	*/
	340	static struct lock_class_key gpio_lock_class;
	341
88d8951e	342	static int __devinit tegra_gpio_probe(struct platform_device *pdev)
3c92db9a	343	{
3391811c	344	int irq_base;
88d8951e	345	struct resource *res;
3c92db9a	346	struct tegra_gpio_bank *bank;
47008001	347	int gpio;
3c92db9a EG	348	int i;
	349	int j;
	350
3391811c SW	351	for (;;) {
	352	res = platform_get_resource(pdev, IORESOURCE_IRQ, tegra_gpio_bank_count);
	353	if (!res)
	354	break;
	355	tegra_gpio_bank_count++;
	356	}
	357	if (!tegra_gpio_bank_count) {
	358	dev_err(&pdev->dev, "Missing IRQ resource\n");
	359	return -ENODEV;
	360	}
	361
	362	tegra_gpio_chip.ngpio = tegra_gpio_bank_count * 32;
	363
	364	tegra_gpio_banks = devm_kzalloc(&pdev->dev,
	365	tegra_gpio_bank_count * sizeof(*tegra_gpio_banks),
	366	GFP_KERNEL);
	367	if (!tegra_gpio_banks) {
	368	dev_err(&pdev->dev, "Couldn't allocate bank structure\n");
	369	return -ENODEV;
	370	}
	371
	372	irq_base = irq_alloc_descs(-1, 0, tegra_gpio_chip.ngpio, 0);
	373	if (irq_base < 0) {
6f74dc9b SW	374	dev_err(&pdev->dev, "Couldn't allocate IRQ numbers\n");
	375	return -ENODEV;
	376	}
bdc93a77 SW	377	irq_domain = irq_domain_add_legacy(pdev->dev.of_node,
	378	tegra_gpio_chip.ngpio, irq_base, 0,
	379	&irq_domain_simple_ops, NULL);
6f74dc9b	380
3391811c	381	for (i = 0; i < tegra_gpio_bank_count; i++) {
88d8951e SW	382	res = platform_get_resource(pdev, IORESOURCE_IRQ, i);
	383	if (!res) {
	384	dev_err(&pdev->dev, "Missing IRQ resource\n");
	385	return -ENODEV;
	386	}
	387
	388	bank = &tegra_gpio_banks[i];
	389	bank->bank = i;
	390	bank->irq = res->start;
	391	}
	392
	393	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	394	if (!res) {
	395	dev_err(&pdev->dev, "Missing MEM resource\n");
	396	return -ENODEV;
	397	}
	398
aedd4fdf	399	regs = devm_request_and_ioremap(&pdev->dev, res);
88d8951e SW	400	if (!regs) {
	401	dev_err(&pdev->dev, "Couldn't ioremap regs\n");
	402	return -ENODEV;
	403	}
	404
3c92db9a EG	405	for (i = 0; i < 7; i++) {
	406	for (j = 0; j < 4; j++) {
	407	int gpio = tegra_gpio_compose(i, j, 0);
88d8951e	408	tegra_gpio_writel(0x00, GPIO_INT_ENB(gpio));
3c92db9a EG	409	}
	410	}
	411
df221227	412	#ifdef CONFIG_OF_GPIO
88d8951e SW	413	tegra_gpio_chip.of_node = pdev->dev.of_node;
88d8951e SW	414	#endif
df221227	415
3c92db9a EG	416	gpiochip_add(&tegra_gpio_chip);
3c92db9a EG	417
3391811c	418	for (gpio = 0; gpio < tegra_gpio_chip.ngpio; gpio++) {
bdc93a77	419	int irq = irq_find_mapping(irq_domain, gpio);
47008001	420	/* No validity check; all Tegra GPIOs are valid IRQs */
3c92db9a	421
47008001	422	bank = &tegra_gpio_banks[GPIO_BANK(gpio)];
3c92db9a	423
47008001 SW	424	irq_set_lockdep_class(irq, &gpio_lock_class);
	425	irq_set_chip_data(irq, bank);
	426	irq_set_chip_and_handler(irq, &tegra_gpio_irq_chip,
f38c02f3	427	handle_simple_irq);
47008001	428	set_irq_flags(irq, IRQF_VALID);
3c92db9a EG	429	}
3c92db9a EG	430
3391811c	431	for (i = 0; i < tegra_gpio_bank_count; i++) {
3c92db9a EG	432	bank = &tegra_gpio_banks[i];
3c92db9a EG	433
6845664a TG	434	irq_set_chained_handler(bank->irq, tegra_gpio_irq_handler);
6845664a TG	435	irq_set_handler_data(bank->irq, bank);
3c92db9a EG	436
	437	for (j = 0; j < 4; j++)
	438	spin_lock_init(&bank->lvl_lock[j]);
	439	}
	440
	441	return 0;
	442	}
	443
88d8951e SW	444	static struct of_device_id tegra_gpio_of_match[] __devinitdata = {
	445	{ .compatible = "nvidia,tegra20-gpio", },
	446	{ },
	447	};
	448
	449	static struct platform_driver tegra_gpio_driver = {
	450	.driver = {
	451	.name = "tegra-gpio",
	452	.owner = THIS_MODULE,
	453	.of_match_table = tegra_gpio_of_match,
	454	},
	455	.probe = tegra_gpio_probe,
	456	};
	457
	458	static int __init tegra_gpio_init(void)
	459	{
	460	return platform_driver_register(&tegra_gpio_driver);
	461	}
3c92db9a EG	462	postcore_initcall(tegra_gpio_init);
3c92db9a EG	463
b0092f26	464	void tegra_gpio_config(struct tegra_gpio_table *table, int num)
632095ea OJ	465	{
	466	int i;
	467
	468	for (i = 0; i < num; i++) {
	469	int gpio = table[i].gpio;
	470
	471	if (table[i].enable)
	472	tegra_gpio_enable(gpio);
	473	else
	474	tegra_gpio_disable(gpio);
	475	}
	476	}
	477
3c92db9a EG	478	#ifdef CONFIG_DEBUG_FS
	479
	480	#include <linux/debugfs.h>
	481	#include <linux/seq_file.h>
	482
	483	static int dbg_gpio_show(struct seq_file s, void unused)
	484	{
	485	int i;
	486	int j;
	487
	488	for (i = 0; i < 7; i++) {
	489	for (j = 0; j < 4; j++) {
	490	int gpio = tegra_gpio_compose(i, j, 0);
2e47b8b3 CC	491	seq_printf(s,
	492	"%d:%d %02x %02x %02x %02x %02x %02x %06x\n",
	493	i, j,
88d8951e SW	494	tegra_gpio_readl(GPIO_CNF(gpio)),
	495	tegra_gpio_readl(GPIO_OE(gpio)),
	496	tegra_gpio_readl(GPIO_OUT(gpio)),
	497	tegra_gpio_readl(GPIO_IN(gpio)),
	498	tegra_gpio_readl(GPIO_INT_STA(gpio)),
	499	tegra_gpio_readl(GPIO_INT_ENB(gpio)),
	500	tegra_gpio_readl(GPIO_INT_LVL(gpio)));
3c92db9a EG	501	}
	502	}
	503	return 0;
	504	}
	505
	506	static int dbg_gpio_open(struct inode inode, struct file file)
	507	{
	508	return single_open(file, dbg_gpio_show, &inode->i_private);
	509	}
	510
	511	static const struct file_operations debug_fops = {
	512	.open = dbg_gpio_open,
	513	.read = seq_read,
	514	.llseek = seq_lseek,
	515	.release = single_release,
	516	};
	517
	518	static int __init tegra_gpio_debuginit(void)
	519	{
	520	(void) debugfs_create_file("tegra_gpio", S_IRUGO,
	521	NULL, NULL, &debug_fops);
	522	return 0;
	523	}
	524	late_initcall(tegra_gpio_debuginit);
	525	#endif