[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-pxa.c

/*
 *  linux/arch/arm/plat-pxa/gpio.c
 *
 *  Generic PXA GPIO handling
 *
 *  Author:	Nicolas Pitre
 *  Created:	Jun 15, 2001
 *  Copyright:	MontaVista Software Inc.
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License version 2 as
 *  published by the Free Software Foundation.
 */
#include <linux/clk.h>
#include <linux/err.h>
#include <linux/gpio.h>
#include <linux/gpio-pxa.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/platform_device.h>
#include <linux/syscore_ops.h>
#include <linux/slab.h>

#include <mach/irqs.h>

/*
 * We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
 * one set of registers. The register offsets are organized below:
 *
 *           GPLR    GPDR    GPSR    GPCR    GRER    GFER    GEDR
 * BANK 0 - 0x0000  0x000C  0x0018  0x0024  0x0030  0x003C  0x0048
 * BANK 1 - 0x0004  0x0010  0x001C  0x0028  0x0034  0x0040  0x004C
 * BANK 2 - 0x0008  0x0014  0x0020  0x002C  0x0038  0x0044  0x0050
 *
 * BANK 3 - 0x0100  0x010C  0x0118  0x0124  0x0130  0x013C  0x0148
 * BANK 4 - 0x0104  0x0110  0x011C  0x0128  0x0134  0x0140  0x014C
 * BANK 5 - 0x0108  0x0114  0x0120  0x012C  0x0138  0x0144  0x0150
 *
 * NOTE:
 *   BANK 3 is only available on PXA27x and later processors.
 *   BANK 4 and 5 are only available on PXA935
 */

#define GPLR_OFFSET	0x00
#define GPDR_OFFSET	0x0C
#define GPSR_OFFSET	0x18
#define GPCR_OFFSET	0x24
#define GRER_OFFSET	0x30
#define GFER_OFFSET	0x3C
#define GEDR_OFFSET	0x48
#define GAFR_OFFSET	0x54
#define ED_MASK_OFFSET	0x9C	/* GPIO edge detection for AP side */

#define BANK_OFF(n)	(((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))

int pxa_last_gpio;

struct pxa_gpio_chip {
	struct gpio_chip chip;
	void __iomem	*regbase;
	char label[10];

	unsigned long	irq_mask;
	unsigned long	irq_edge_rise;
	unsigned long	irq_edge_fall;

#ifdef CONFIG_PM
	unsigned long	saved_gplr;
	unsigned long	saved_gpdr;
	unsigned long	saved_grer;
	unsigned long	saved_gfer;
#endif
};

enum {
	PXA25X_GPIO = 0,
	PXA26X_GPIO,
	PXA27X_GPIO,
	PXA3XX_GPIO,
	PXA93X_GPIO,
	MMP_GPIO = 0x10,
	MMP2_GPIO,
};

static DEFINE_SPINLOCK(gpio_lock);
static struct pxa_gpio_chip *pxa_gpio_chips;
static int gpio_type;
static void __iomem *gpio_reg_base;

#define for_each_gpio_chip(i, c)			\
	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)

static inline void __iomem *gpio_chip_base(struct gpio_chip *c)
{
	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
}

static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
{
	return &pxa_gpio_chips[gpio_to_bank(gpio)];
}

static inline int gpio_is_pxa_type(int type)
{
	return (type & MMP_GPIO) == 0;
}

static inline int gpio_is_mmp_type(int type)
{
	return (type & MMP_GPIO) != 0;
}

/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
 * as well as their Alternate Function value being '1' for GPIO in GAFRx.
 */
static inline int __gpio_is_inverted(int gpio)
{
	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
		return 1;
	return 0;
}

/*
 * On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
 * function of a GPIO, and GPDRx cannot be altered once configured. It
 * is attributed as "occupied" here (I know this terminology isn't
 * accurate, you are welcome to propose a better one :-)
 */
static inline int __gpio_is_occupied(unsigned gpio)
{
	struct pxa_gpio_chip *pxachip;
	void __iomem *base;
	unsigned long gafr = 0, gpdr = 0;
	int ret, af = 0, dir = 0;

	pxachip = gpio_to_pxachip(gpio);
	base = gpio_chip_base(&pxachip->chip);
	gpdr = readl_relaxed(base + GPDR_OFFSET);

	switch (gpio_type) {
	case PXA25X_GPIO:
	case PXA26X_GPIO:
	case PXA27X_GPIO:
		gafr = readl_relaxed(base + GAFR_OFFSET);
		af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
		dir = gpdr & GPIO_bit(gpio);

		if (__gpio_is_inverted(gpio))
			ret = (af != 1) || (dir == 0);
		else
			ret = (af != 0) || (dir != 0);
		break;
	default:
		ret = gpdr & GPIO_bit(gpio);
		break;
	}
	return ret;
}

#ifdef CONFIG_ARCH_PXA
static inline int __pxa_gpio_to_irq(int gpio)
{
	if (gpio_is_pxa_type(gpio_type))
		return PXA_GPIO_TO_IRQ(gpio);
	return -1;
}

static inline int __pxa_irq_to_gpio(int irq)
{
	if (gpio_is_pxa_type(gpio_type))
		return irq - PXA_GPIO_TO_IRQ(0);
	return -1;
}
#else
static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
static inline int __pxa_irq_to_gpio(int irq) { return -1; }
#endif

#ifdef CONFIG_ARCH_MMP
static inline int __mmp_gpio_to_irq(int gpio)
{
	if (gpio_is_mmp_type(gpio_type))
		return MMP_GPIO_TO_IRQ(gpio);
	return -1;
}

static inline int __mmp_irq_to_gpio(int irq)
{
	if (gpio_is_mmp_type(gpio_type))
		return irq - MMP_GPIO_TO_IRQ(0);
	return -1;
}
#else
static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
static inline int __mmp_irq_to_gpio(int irq) { return -1; }
#endif

static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	int gpio, ret;

	gpio = chip->base + offset;
	ret = __pxa_gpio_to_irq(gpio);
	if (ret >= 0)
		return ret;
	return __mmp_gpio_to_irq(gpio);
}

int pxa_irq_to_gpio(int irq)
{
	int ret;

	ret = __pxa_irq_to_gpio(irq);
	if (ret >= 0)
		return ret;
	return __mmp_irq_to_gpio(irq);
}

static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t value, mask = 1 << offset;
	unsigned long flags;

	spin_lock_irqsave(&gpio_lock, flags);

	value = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		value |= mask;
	else
		value &= ~mask;
	writel_relaxed(value, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_direction_output(struct gpio_chip *chip,
				     unsigned offset, int value)
{
	void __iomem *base = gpio_chip_base(chip);
	uint32_t tmp, mask = 1 << offset;
	unsigned long flags;

	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));

	spin_lock_irqsave(&gpio_lock, flags);

	tmp = readl_relaxed(base + GPDR_OFFSET);
	if (__gpio_is_inverted(chip->base + offset))
		tmp &= ~mask;
	else
		tmp |= mask;
	writel_relaxed(tmp, base + GPDR_OFFSET);

	spin_unlock_irqrestore(&gpio_lock, flags);
	return 0;
}

static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
}

static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	writel_relaxed(1 << offset, gpio_chip_base(chip) +
				(value ? GPSR_OFFSET : GPCR_OFFSET));
}

static int __devinit pxa_init_gpio_chip(int gpio_end)
{
	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
	struct pxa_gpio_chip *chips;

	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
	if (chips == NULL) {
		pr_err("%s: failed to allocate GPIO chips\n", __func__);
		return -ENOMEM;
	}

	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
		struct gpio_chip *c = &chips[i].chip;

		sprintf(chips[i].label, "gpio-%d", i);
		chips[i].regbase = gpio_reg_base + BANK_OFF(i);

		c->base  = gpio;
		c->label = chips[i].label;

		c->direction_input  = pxa_gpio_direction_input;
		c->direction_output = pxa_gpio_direction_output;
		c->get = pxa_gpio_get;
		c->set = pxa_gpio_set;
		c->to_irq = pxa_gpio_to_irq;

		/* number of GPIOs on last bank may be less than 32 */
		c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
		gpiochip_add(c);
	}
	pxa_gpio_chips = chips;
	return 0;
}

/* Update only those GRERx and GFERx edge detection register bits if those
 * bits are set in c->irq_mask
 */
static inline void update_edge_detect(struct pxa_gpio_chip *c)
{
	uint32_t grer, gfer;

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
	grer |= c->irq_edge_rise & c->irq_mask;
	gfer |= c->irq_edge_fall & c->irq_mask;
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
{
	struct pxa_gpio_chip *c;
	int gpio = pxa_irq_to_gpio(d->irq);
	unsigned long gpdr, mask = GPIO_bit(gpio);

	c = gpio_to_pxachip(gpio);

	if (type == IRQ_TYPE_PROBE) {
		/* Don't mess with enabled GPIOs using preconfigured edges or
		 * GPIOs set to alternate function or to output during probe
		 */
		if ((c->irq_edge_rise | c->irq_edge_fall) & GPIO_bit(gpio))
			return 0;

		if (__gpio_is_occupied(gpio))
			return 0;

		type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
	}

	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);

	if (__gpio_is_inverted(gpio))
		writel_relaxed(gpdr | mask,  c->regbase + GPDR_OFFSET);
	else
		writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);

	if (type & IRQ_TYPE_EDGE_RISING)
		c->irq_edge_rise |= mask;
	else
		c->irq_edge_rise &= ~mask;

	if (type & IRQ_TYPE_EDGE_FALLING)
		c->irq_edge_fall |= mask;
	else
		c->irq_edge_fall &= ~mask;

	update_edge_detect(c);

	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
		((type & IRQ_TYPE_EDGE_RISING)  ? " rising"  : ""),
		((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	return 0;
}

static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
{
	struct pxa_gpio_chip *c;
	int loop, gpio, gpio_base, n;
	unsigned long gedr;

	do {
		loop = 0;
		for_each_gpio_chip(gpio, c) {
			gpio_base = c->chip.base;

			gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
			gedr = gedr & c->irq_mask;
			writel_relaxed(gedr, c->regbase + GEDR_OFFSET);

			n = find_first_bit(&gedr, BITS_PER_LONG);
			while (n < BITS_PER_LONG) {
				loop = 1;

				generic_handle_irq(gpio_to_irq(gpio_base + n));
				n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
			}
		}
	} while (loop);
}

static void pxa_ack_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
}

static void pxa_mask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
	uint32_t grer, gfer;

	c->irq_mask &= ~GPIO_bit(gpio);

	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
}

static void pxa_unmask_muxed_gpio(struct irq_data *d)
{
	int gpio = pxa_irq_to_gpio(d->irq);
	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);

	c->irq_mask |= GPIO_bit(gpio);
	update_edge_detect(c);
}

static struct irq_chip pxa_muxed_gpio_chip = {
	.name		= "GPIO",
	.irq_ack	= pxa_ack_muxed_gpio,
	.irq_mask	= pxa_mask_muxed_gpio,
	.irq_unmask	= pxa_unmask_muxed_gpio,
	.irq_set_type	= pxa_gpio_irq_type,
};

static int pxa_gpio_nums(void)
{
	int count = 0;

#ifdef CONFIG_ARCH_PXA
	if (cpu_is_pxa25x()) {
#ifdef CONFIG_CPU_PXA26x
		count = 89;
		gpio_type = PXA26X_GPIO;
#elif defined(CONFIG_PXA25x)
		count = 84;
		gpio_type = PXA26X_GPIO;
#endif /* CONFIG_CPU_PXA26x */
	} else if (cpu_is_pxa27x()) {
		count = 120;
		gpio_type = PXA27X_GPIO;
	} else if (cpu_is_pxa93x() || cpu_is_pxa95x()) {
		count = 191;
		gpio_type = PXA93X_GPIO;
	} else if (cpu_is_pxa3xx()) {
		count = 127;
		gpio_type = PXA3XX_GPIO;
	}
#endif /* CONFIG_ARCH_PXA */

#ifdef CONFIG_ARCH_MMP
	if (cpu_is_pxa168() || cpu_is_pxa910()) {
		count = 127;
		gpio_type = MMP_GPIO;
	} else if (cpu_is_mmp2()) {
		count = 191;
		gpio_type = MMP2_GPIO;
	}
#endif /* CONFIG_ARCH_MMP */
	return count;
}

static int __devinit pxa_gpio_probe(struct platform_device *pdev)
{
	struct pxa_gpio_chip *c;
	struct resource *res;
	struct clk *clk;
	int gpio, irq, ret;
	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;

	pxa_last_gpio = pxa_gpio_nums();
	if (!pxa_last_gpio)
		return -EINVAL;

	irq0 = platform_get_irq_byname(pdev, "gpio0");
	irq1 = platform_get_irq_byname(pdev, "gpio1");
	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	if ((irq0 > 0 && irq1 <= 0) || (irq0 <= 0 && irq1 > 0)
		|| (irq_mux <= 0))
		return -EINVAL;
	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EINVAL;
	gpio_reg_base = ioremap(res->start, resource_size(res));
	if (!gpio_reg_base)
		return -EINVAL;

	if (irq0 > 0)
		gpio_offset = 2;

	clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(clk)) {
		dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
			PTR_ERR(clk));
		iounmap(gpio_reg_base);
		return PTR_ERR(clk);
	}
	ret = clk_prepare(clk);
	if (ret) {
		clk_put(clk);
		iounmap(gpio_reg_base);
		return ret;
	}
	ret = clk_enable(clk);
	if (ret) {
		clk_unprepare(clk);
		clk_put(clk);
		iounmap(gpio_reg_base);
		return ret;
	}

	/* Initialize GPIO chips */
	pxa_init_gpio_chip(pxa_last_gpio);

	/* clear all GPIO edge detects */
	for_each_gpio_chip(gpio, c) {
		writel_relaxed(0, c->regbase + GFER_OFFSET);
		writel_relaxed(0, c->regbase + GRER_OFFSET);
		writel_relaxed(~0,c->regbase + GEDR_OFFSET);
		/* unmask GPIO edge detect for AP side */
		if (gpio_is_mmp_type(gpio_type))
			writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
	}

#ifdef CONFIG_ARCH_PXA
	irq = gpio_to_irq(0);
	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
				 handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);

	irq = gpio_to_irq(1);
	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
				 handle_edge_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
#endif

	for (irq  = gpio_to_irq(gpio_offset);
		irq <= gpio_to_irq(pxa_last_gpio); irq++) {
		irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
					 handle_edge_irq);
		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	}

	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	return 0;
}

static struct platform_driver pxa_gpio_driver = {
	.probe		= pxa_gpio_probe,
	.driver		= {
		.name	= "pxa-gpio",
	},
};

static int __init pxa_gpio_init(void)
{
	return platform_driver_register(&pxa_gpio_driver);
}
postcore_initcall(pxa_gpio_init);

#ifdef CONFIG_PM
static int pxa_gpio_suspend(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
		c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
		c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
		c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);

		/* Clear GPIO transition detect bits */
		writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
	}
	return 0;
}

static void pxa_gpio_resume(void)
{
	struct pxa_gpio_chip *c;
	int gpio;

	for_each_gpio_chip(gpio, c) {
		/* restore level with set/clear */
		writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
		writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);

		writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
		writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
		writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
	}
}
#else
#define pxa_gpio_suspend	NULL
#define pxa_gpio_resume		NULL
#endif

struct syscore_ops pxa_gpio_syscore_ops = {
	.suspend	= pxa_gpio_suspend,
	.resume		= pxa_gpio_resume,
};

static int __init pxa_gpio_sysinit(void)
{
	register_syscore_ops(&pxa_gpio_syscore_ops);
	return 0;
}
postcore_initcall(pxa_gpio_sysinit);
Commit	Line	Data
1c44f5f1	1	/*
38f539a6	2	* linux/arch/arm/plat-pxa/gpio.c
1c44f5f1 PZ	3	*
	4	* Generic PXA GPIO handling
	5	*
	6	* Author: Nicolas Pitre
	7	* Created: Jun 15, 2001
	8	* Copyright: MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*/
389eda15 HZ	14	#include <linux/clk.h>
389eda15 HZ	15	#include <linux/err.h>
2f8163ba	16	#include <linux/gpio.h>
157d2644	17	#include <linux/gpio-pxa.h>
1c44f5f1	18	#include <linux/init.h>
e3630db1	19	#include <linux/irq.h>
fced80c7	20	#include <linux/io.h>
157d2644	21	#include <linux/platform_device.h>
2eaa03b5	22	#include <linux/syscore_ops.h>
4aa78264	23	#include <linux/slab.h>
1c44f5f1	24
feefe73f RH	25	#include <mach/irqs.h>
feefe73f RH	26
157d2644 HZ	27	/*
	28	* We handle the GPIOs by banks, each bank covers up to 32 GPIOs with
	29	* one set of registers. The register offsets are organized below:
	30	*
	31	* GPLR GPDR GPSR GPCR GRER GFER GEDR
	32	* BANK 0 - 0x0000 0x000C 0x0018 0x0024 0x0030 0x003C 0x0048
	33	* BANK 1 - 0x0004 0x0010 0x001C 0x0028 0x0034 0x0040 0x004C
	34	* BANK 2 - 0x0008 0x0014 0x0020 0x002C 0x0038 0x0044 0x0050
	35	*
	36	* BANK 3 - 0x0100 0x010C 0x0118 0x0124 0x0130 0x013C 0x0148
	37	* BANK 4 - 0x0104 0x0110 0x011C 0x0128 0x0134 0x0140 0x014C
	38	* BANK 5 - 0x0108 0x0114 0x0120 0x012C 0x0138 0x0144 0x0150
	39	*
	40	* NOTE:
	41	* BANK 3 is only available on PXA27x and later processors.
	42	* BANK 4 and 5 are only available on PXA935
	43	*/
	44
	45	#define GPLR_OFFSET 0x00
	46	#define GPDR_OFFSET 0x0C
	47	#define GPSR_OFFSET 0x18
	48	#define GPCR_OFFSET 0x24
	49	#define GRER_OFFSET 0x30
	50	#define GFER_OFFSET 0x3C
	51	#define GEDR_OFFSET 0x48
	52	#define GAFR_OFFSET 0x54
be24168f	53	#define ED_MASK_OFFSET 0x9C /* GPIO edge detection for AP side */
157d2644 HZ	54
157d2644 HZ	55	#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
1c44f5f1	56
3b8e285c EM	57	int pxa_last_gpio;
3b8e285c EM	58
1c44f5f1 PZ	59	struct pxa_gpio_chip {
1c44f5f1 PZ	60	struct gpio_chip chip;
0807da59 EM	61	void __iomem *regbase;
	62	char label[10];
	63
	64	unsigned long irq_mask;
	65	unsigned long irq_edge_rise;
	66	unsigned long irq_edge_fall;
	67
	68	#ifdef CONFIG_PM
	69	unsigned long saved_gplr;
	70	unsigned long saved_gpdr;
	71	unsigned long saved_grer;
	72	unsigned long saved_gfer;
	73	#endif
1c44f5f1 PZ	74	};
1c44f5f1 PZ	75
4929f5a8 HZ	76	enum {
	77	PXA25X_GPIO = 0,
	78	PXA26X_GPIO,
	79	PXA27X_GPIO,
	80	PXA3XX_GPIO,
	81	PXA93X_GPIO,
	82	MMP_GPIO = 0x10,
	83	MMP2_GPIO,
	84	};
	85
0807da59 EM	86	static DEFINE_SPINLOCK(gpio_lock);
0807da59 EM	87	static struct pxa_gpio_chip *pxa_gpio_chips;
4929f5a8	88	static int gpio_type;
157d2644	89	static void __iomem *gpio_reg_base;
0807da59 EM	90
	91	#define for_each_gpio_chip(i, c) \
	92	for (i = 0, c = &pxa_gpio_chips[0]; i <= pxa_last_gpio; i += 32, c++)
	93
	94	static inline void __iomem gpio_chip_base(struct gpio_chip c)
	95	{
	96	return container_of(c, struct pxa_gpio_chip, chip)->regbase;
	97	}
	98
a065685d	99	static inline struct pxa_gpio_chip *gpio_to_pxachip(unsigned gpio)
0807da59 EM	100	{
	101	return &pxa_gpio_chips[gpio_to_bank(gpio)];
	102	}
	103
4929f5a8 HZ	104	static inline int gpio_is_pxa_type(int type)
	105	{
	106	return (type & MMP_GPIO) == 0;
	107	}
	108
	109	static inline int gpio_is_mmp_type(int type)
	110	{
	111	return (type & MMP_GPIO) != 0;
	112	}
	113
157d2644 HZ	114	/* GPIO86/87/88/89 on PXA26x have their direction bits in PXA_GPDR(2 inverted,
	115	* as well as their Alternate Function value being '1' for GPIO in GAFRx.
	116	*/
	117	static inline int __gpio_is_inverted(int gpio)
	118	{
	119	if ((gpio_type == PXA26X_GPIO) && (gpio > 85))
	120	return 1;
	121	return 0;
	122	}
	123
	124	/*
	125	* On PXA25x and PXA27x, GAFRx and GPDRx together decide the alternate
	126	* function of a GPIO, and GPDRx cannot be altered once configured. It
	127	* is attributed as "occupied" here (I know this terminology isn't
	128	* accurate, you are welcome to propose a better one :-)
	129	*/
	130	static inline int __gpio_is_occupied(unsigned gpio)
	131	{
	132	struct pxa_gpio_chip *pxachip;
	133	void __iomem *base;
	134	unsigned long gafr = 0, gpdr = 0;
	135	int ret, af = 0, dir = 0;
	136
	137	pxachip = gpio_to_pxachip(gpio);
	138	base = gpio_chip_base(&pxachip->chip);
	139	gpdr = readl_relaxed(base + GPDR_OFFSET);
	140
	141	switch (gpio_type) {
	142	case PXA25X_GPIO:
	143	case PXA26X_GPIO:
	144	case PXA27X_GPIO:
	145	gafr = readl_relaxed(base + GAFR_OFFSET);
	146	af = (gafr >> ((gpio & 0xf) * 2)) & 0x3;
	147	dir = gpdr & GPIO_bit(gpio);
	148
	149	if (__gpio_is_inverted(gpio))
	150	ret = (af != 1) \|\| (dir == 0);
	151	else
	152	ret = (af != 0) \|\| (dir != 0);
	153	break;
	154	default:
	155	ret = gpdr & GPIO_bit(gpio);
	156	break;
	157	}
	158	return ret;
	159	}
	160
4929f5a8 HZ	161	#ifdef CONFIG_ARCH_PXA
	162	static inline int __pxa_gpio_to_irq(int gpio)
	163	{
	164	if (gpio_is_pxa_type(gpio_type))
	165	return PXA_GPIO_TO_IRQ(gpio);
	166	return -1;
	167	}
	168
	169	static inline int __pxa_irq_to_gpio(int irq)
	170	{
	171	if (gpio_is_pxa_type(gpio_type))
	172	return irq - PXA_GPIO_TO_IRQ(0);
	173	return -1;
	174	}
	175	#else
	176	static inline int __pxa_gpio_to_irq(int gpio) { return -1; }
	177	static inline int __pxa_irq_to_gpio(int irq) { return -1; }
	178	#endif
	179
	180	#ifdef CONFIG_ARCH_MMP
	181	static inline int __mmp_gpio_to_irq(int gpio)
	182	{
	183	if (gpio_is_mmp_type(gpio_type))
	184	return MMP_GPIO_TO_IRQ(gpio);
	185	return -1;
	186	}
	187
	188	static inline int __mmp_irq_to_gpio(int irq)
	189	{
	190	if (gpio_is_mmp_type(gpio_type))
	191	return irq - MMP_GPIO_TO_IRQ(0);
	192	return -1;
	193	}
	194	#else
	195	static inline int __mmp_gpio_to_irq(int gpio) { return -1; }
	196	static inline int __mmp_irq_to_gpio(int irq) { return -1; }
	197	#endif
	198
	199	static int pxa_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	200	{
	201	int gpio, ret;
	202
	203	gpio = chip->base + offset;
	204	ret = __pxa_gpio_to_irq(gpio);
	205	if (ret >= 0)
	206	return ret;
	207	return __mmp_gpio_to_irq(gpio);
	208	}
	209
	210	int pxa_irq_to_gpio(int irq)
	211	{
	212	int ret;
	213
	214	ret = __pxa_irq_to_gpio(irq);
	215	if (ret >= 0)
	216	return ret;
	217	return __mmp_irq_to_gpio(irq);
	218	}
	219
1c44f5f1 PZ	220	static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	221	{
0807da59 EM	222	void __iomem *base = gpio_chip_base(chip);
	223	uint32_t value, mask = 1 << offset;
	224	unsigned long flags;
	225
	226	spin_lock_irqsave(&gpio_lock, flags);
	227
df664d20	228	value = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	229	if (__gpio_is_inverted(chip->base + offset))
	230	value \|= mask;
	231	else
	232	value &= ~mask;
df664d20	233	writel_relaxed(value, base + GPDR_OFFSET);
1c44f5f1	234
0807da59	235	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	236	return 0;
	237	}
	238
	239	static int pxa_gpio_direction_output(struct gpio_chip *chip,
0807da59	240	unsigned offset, int value)
1c44f5f1	241	{
0807da59 EM	242	void __iomem *base = gpio_chip_base(chip);
	243	uint32_t tmp, mask = 1 << offset;
	244	unsigned long flags;
	245
df664d20	246	writel_relaxed(mask, base + (value ? GPSR_OFFSET : GPCR_OFFSET));
0807da59 EM	247
	248	spin_lock_irqsave(&gpio_lock, flags);
	249
df664d20	250	tmp = readl_relaxed(base + GPDR_OFFSET);
067455aa EM	251	if (__gpio_is_inverted(chip->base + offset))
	252	tmp &= ~mask;
	253	else
	254	tmp \|= mask;
df664d20	255	writel_relaxed(tmp, base + GPDR_OFFSET);
1c44f5f1	256
0807da59	257	spin_unlock_irqrestore(&gpio_lock, flags);
1c44f5f1 PZ	258	return 0;
	259	}
	260
1c44f5f1 PZ	261	static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
1c44f5f1 PZ	262	{
df664d20	263	return readl_relaxed(gpio_chip_base(chip) + GPLR_OFFSET) & (1 << offset);
1c44f5f1 PZ	264	}
1c44f5f1 PZ	265
1c44f5f1 PZ	266	static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1c44f5f1 PZ	267	{
df664d20	268	writel_relaxed(1 << offset, gpio_chip_base(chip) +
0807da59	269	(value ? GPSR_OFFSET : GPCR_OFFSET));
1c44f5f1 PZ	270	}
1c44f5f1 PZ	271
157d2644	272	static int __devinit pxa_init_gpio_chip(int gpio_end)
a58fbcd8	273	{
0807da59 EM	274	int i, gpio, nbanks = gpio_to_bank(gpio_end) + 1;
0807da59 EM	275	struct pxa_gpio_chip *chips;
a58fbcd8	276
4aa78264	277	chips = kzalloc(nbanks * sizeof(struct pxa_gpio_chip), GFP_KERNEL);
0807da59 EM	278	if (chips == NULL) {
	279	pr_err("%s: failed to allocate GPIO chips\n", __func__);
	280	return -ENOMEM;
a58fbcd8	281	}
a58fbcd8	282
0807da59 EM	283	for (i = 0, gpio = 0; i < nbanks; i++, gpio += 32) {
0807da59 EM	284	struct gpio_chip *c = &chips[i].chip;
e3630db1	285
0807da59	286	sprintf(chips[i].label, "gpio-%d", i);
157d2644	287	chips[i].regbase = gpio_reg_base + BANK_OFF(i);
0807da59 EM	288
	289	c->base = gpio;
	290	c->label = chips[i].label;
	291
	292	c->direction_input = pxa_gpio_direction_input;
	293	c->direction_output = pxa_gpio_direction_output;
	294	c->get = pxa_gpio_get;
	295	c->set = pxa_gpio_set;
4929f5a8	296	c->to_irq = pxa_gpio_to_irq;
0807da59 EM	297
	298	/* number of GPIOs on last bank may be less than 32 */
	299	c->ngpio = (gpio + 31 > gpio_end) ? (gpio_end - gpio + 1) : 32;
	300	gpiochip_add(c);
	301	}
	302	pxa_gpio_chips = chips;
	303	return 0;
	304	}
e3630db1	305
a8f6faeb EM	306	/* Update only those GRERx and GFERx edge detection register bits if those
	307	* bits are set in c->irq_mask
	308	*/
	309	static inline void update_edge_detect(struct pxa_gpio_chip *c)
	310	{
	311	uint32_t grer, gfer;
	312
df664d20 HZ	313	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~c->irq_mask;
df664d20 HZ	314	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~c->irq_mask;
a8f6faeb EM	315	grer \|= c->irq_edge_rise & c->irq_mask;
a8f6faeb EM	316	gfer \|= c->irq_edge_fall & c->irq_mask;
df664d20 HZ	317	writel_relaxed(grer, c->regbase + GRER_OFFSET);
df664d20 HZ	318	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
a8f6faeb EM	319	}
a8f6faeb EM	320
a3f4c927	321	static int pxa_gpio_irq_type(struct irq_data *d, unsigned int type)
e3630db1	322	{
0807da59	323	struct pxa_gpio_chip *c;
4929f5a8	324	int gpio = pxa_irq_to_gpio(d->irq);
0807da59	325	unsigned long gpdr, mask = GPIO_bit(gpio);
e3630db1	326
a065685d	327	c = gpio_to_pxachip(gpio);
e3630db1	328
	329	if (type == IRQ_TYPE_PROBE) {
	330	/* Don't mess with enabled GPIOs using preconfigured edges or
	331	* GPIOs set to alternate function or to output during probe
	332	*/
0807da59	333	if ((c->irq_edge_rise \| c->irq_edge_fall) & GPIO_bit(gpio))
e3630db1	334	return 0;
689c04a3	335
689c04a3	336	if (__gpio_is_occupied(gpio))
e3630db1	337	return 0;
689c04a3	338
e3630db1	339	type = IRQ_TYPE_EDGE_RISING \| IRQ_TYPE_EDGE_FALLING;
	340	}
	341
df664d20	342	gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
0807da59	343
067455aa	344	if (__gpio_is_inverted(gpio))
df664d20	345	writel_relaxed(gpdr \| mask, c->regbase + GPDR_OFFSET);
067455aa	346	else
df664d20	347	writel_relaxed(gpdr & ~mask, c->regbase + GPDR_OFFSET);
e3630db1	348
e3630db1	349	if (type & IRQ_TYPE_EDGE_RISING)
0807da59	350	c->irq_edge_rise \|= mask;
e3630db1	351	else
0807da59	352	c->irq_edge_rise &= ~mask;
e3630db1	353
e3630db1	354	if (type & IRQ_TYPE_EDGE_FALLING)
0807da59	355	c->irq_edge_fall \|= mask;
e3630db1	356	else
0807da59	357	c->irq_edge_fall &= ~mask;
e3630db1	358
a8f6faeb	359	update_edge_detect(c);
e3630db1	360
a3f4c927	361	pr_debug("%s: IRQ%d (GPIO%d) - edge%s%s\n", __func__, d->irq, gpio,
e3630db1	362	((type & IRQ_TYPE_EDGE_RISING) ? " rising" : ""),
	363	((type & IRQ_TYPE_EDGE_FALLING) ? " falling" : ""));
	364	return 0;
	365	}
	366
e3630db1	367	static void pxa_gpio_demux_handler(unsigned int irq, struct irq_desc *desc)
e3630db1	368	{
0807da59 EM	369	struct pxa_gpio_chip *c;
	370	int loop, gpio, gpio_base, n;
	371	unsigned long gedr;
e3630db1	372
e3630db1	373	do {
e3630db1	374	loop = 0;
0807da59 EM	375	for_each_gpio_chip(gpio, c) {
	376	gpio_base = c->chip.base;
	377
df664d20	378	gedr = readl_relaxed(c->regbase + GEDR_OFFSET);
0807da59	379	gedr = gedr & c->irq_mask;
df664d20	380	writel_relaxed(gedr, c->regbase + GEDR_OFFSET);
e3630db1	381
0807da59 EM	382	n = find_first_bit(&gedr, BITS_PER_LONG);
	383	while (n < BITS_PER_LONG) {
	384	loop = 1;
e3630db1	385
0807da59 EM	386	generic_handle_irq(gpio_to_irq(gpio_base + n));
	387	n = find_next_bit(&gedr, BITS_PER_LONG, n + 1);
	388	}
e3630db1	389	}
	390	} while (loop);
	391	}
	392
a3f4c927	393	static void pxa_ack_muxed_gpio(struct irq_data *d)
e3630db1	394	{
4929f5a8	395	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	396	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59	397
df664d20	398	writel_relaxed(GPIO_bit(gpio), c->regbase + GEDR_OFFSET);
e3630db1	399	}
e3630db1	400
a3f4c927	401	static void pxa_mask_muxed_gpio(struct irq_data *d)
e3630db1	402	{
4929f5a8	403	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	404	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	405	uint32_t grer, gfer;
	406
	407	c->irq_mask &= ~GPIO_bit(gpio);
	408
df664d20 HZ	409	grer = readl_relaxed(c->regbase + GRER_OFFSET) & ~GPIO_bit(gpio);
	410	gfer = readl_relaxed(c->regbase + GFER_OFFSET) & ~GPIO_bit(gpio);
	411	writel_relaxed(grer, c->regbase + GRER_OFFSET);
	412	writel_relaxed(gfer, c->regbase + GFER_OFFSET);
e3630db1	413	}
e3630db1	414
a3f4c927	415	static void pxa_unmask_muxed_gpio(struct irq_data *d)
e3630db1	416	{
4929f5a8	417	int gpio = pxa_irq_to_gpio(d->irq);
a065685d	418	struct pxa_gpio_chip *c = gpio_to_pxachip(gpio);
0807da59 EM	419
0807da59 EM	420	c->irq_mask \|= GPIO_bit(gpio);
a8f6faeb	421	update_edge_detect(c);
e3630db1	422	}
	423
	424	static struct irq_chip pxa_muxed_gpio_chip = {
	425	.name = "GPIO",
a3f4c927 LB	426	.irq_ack = pxa_ack_muxed_gpio,
	427	.irq_mask = pxa_mask_muxed_gpio,
	428	.irq_unmask = pxa_unmask_muxed_gpio,
	429	.irq_set_type = pxa_gpio_irq_type,
e3630db1	430	};
e3630db1	431
478e223c HZ	432	static int pxa_gpio_nums(void)
	433	{
	434	int count = 0;
	435
	436	#ifdef CONFIG_ARCH_PXA
	437	if (cpu_is_pxa25x()) {
	438	#ifdef CONFIG_CPU_PXA26x
	439	count = 89;
	440	gpio_type = PXA26X_GPIO;
	441	#elif defined(CONFIG_PXA25x)
	442	count = 84;
	443	gpio_type = PXA26X_GPIO;
	444	#endif /* CONFIG_CPU_PXA26x */
	445	} else if (cpu_is_pxa27x()) {
	446	count = 120;
	447	gpio_type = PXA27X_GPIO;
	448	} else if (cpu_is_pxa93x() \|\| cpu_is_pxa95x()) {
	449	count = 191;
	450	gpio_type = PXA93X_GPIO;
	451	} else if (cpu_is_pxa3xx()) {
	452	count = 127;
	453	gpio_type = PXA3XX_GPIO;
	454	}
	455	#endif /* CONFIG_ARCH_PXA */
	456
	457	#ifdef CONFIG_ARCH_MMP
	458	if (cpu_is_pxa168() \|\| cpu_is_pxa910()) {
	459	count = 127;
	460	gpio_type = MMP_GPIO;
	461	} else if (cpu_is_mmp2()) {
	462	count = 191;
	463	gpio_type = MMP2_GPIO;
	464	}
	465	#endif /* CONFIG_ARCH_MMP */
	466	return count;
	467	}
	468
157d2644	469	static int __devinit pxa_gpio_probe(struct platform_device *pdev)
e3630db1	470	{
0807da59	471	struct pxa_gpio_chip *c;
157d2644	472	struct resource *res;
389eda15 HZ	473	struct clk *clk;
389eda15 HZ	474	int gpio, irq, ret;
157d2644	475	int irq0 = 0, irq1 = 0, irq_mux, gpio_offset = 0;
e3630db1	476
478e223c HZ	477	pxa_last_gpio = pxa_gpio_nums();
478e223c HZ	478	if (!pxa_last_gpio)
157d2644 HZ	479	return -EINVAL;
	480
	481	irq0 = platform_get_irq_byname(pdev, "gpio0");
	482	irq1 = platform_get_irq_byname(pdev, "gpio1");
	483	irq_mux = platform_get_irq_byname(pdev, "gpio_mux");
	484	if ((irq0 > 0 && irq1 <= 0) \|\| (irq0 <= 0 && irq1 > 0)
	485	\|\| (irq_mux <= 0))
	486	return -EINVAL;
	487	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	488	if (!res)
	489	return -EINVAL;
	490	gpio_reg_base = ioremap(res->start, resource_size(res));
	491	if (!gpio_reg_base)
	492	return -EINVAL;
	493
	494	if (irq0 > 0)
	495	gpio_offset = 2;
e3630db1	496
389eda15 HZ	497	clk = clk_get(&pdev->dev, NULL);
	498	if (IS_ERR(clk)) {
	499	dev_err(&pdev->dev, "Error %ld to get gpio clock\n",
	500	PTR_ERR(clk));
	501	iounmap(gpio_reg_base);
	502	return PTR_ERR(clk);
	503	}
	504	ret = clk_prepare(clk);
	505	if (ret) {
	506	clk_put(clk);
	507	iounmap(gpio_reg_base);
	508	return ret;
	509	}
	510	ret = clk_enable(clk);
	511	if (ret) {
	512	clk_unprepare(clk);
	513	clk_put(clk);
	514	iounmap(gpio_reg_base);
	515	return ret;
	516	}
	517
0807da59	518	/* Initialize GPIO chips */
157d2644	519	pxa_init_gpio_chip(pxa_last_gpio);
0807da59	520
e3630db1	521	/* clear all GPIO edge detects */
0807da59	522	for_each_gpio_chip(gpio, c) {
df664d20 HZ	523	writel_relaxed(0, c->regbase + GFER_OFFSET);
	524	writel_relaxed(0, c->regbase + GRER_OFFSET);
	525	writel_relaxed(~0,c->regbase + GEDR_OFFSET);
be24168f HZ	526	/* unmask GPIO edge detect for AP side */
	527	if (gpio_is_mmp_type(gpio_type))
	528	writel_relaxed(~0, c->regbase + ED_MASK_OFFSET);
e3630db1	529	}
e3630db1	530
87c49e20 HZ	531	#ifdef CONFIG_ARCH_PXA
	532	irq = gpio_to_irq(0);
	533	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	534	handle_edge_irq);
	535	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	536	irq_set_chained_handler(IRQ_GPIO0, pxa_gpio_demux_handler);
	537
	538	irq = gpio_to_irq(1);
	539	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
	540	handle_edge_irq);
	541	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	542	irq_set_chained_handler(IRQ_GPIO1, pxa_gpio_demux_handler);
	543	#endif
	544
157d2644 HZ	545	for (irq = gpio_to_irq(gpio_offset);
157d2644 HZ	546	irq <= gpio_to_irq(pxa_last_gpio); irq++) {
f38c02f3 TG	547	irq_set_chip_and_handler(irq, &pxa_muxed_gpio_chip,
f38c02f3 TG	548	handle_edge_irq);
e3630db1	549	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	550	}
	551
157d2644 HZ	552	irq_set_chained_handler(irq_mux, pxa_gpio_demux_handler);
	553	return 0;
	554	}
	555
	556	static struct platform_driver pxa_gpio_driver = {
	557	.probe = pxa_gpio_probe,
	558	.driver = {
	559	.name = "pxa-gpio",
	560	},
	561	};
	562
	563	static int __init pxa_gpio_init(void)
	564	{
	565	return platform_driver_register(&pxa_gpio_driver);
e3630db1	566	}
157d2644	567	postcore_initcall(pxa_gpio_init);
663707c1	568
663707c1	569	#ifdef CONFIG_PM
2eaa03b5	570	static int pxa_gpio_suspend(void)
663707c1	571	{
0807da59 EM	572	struct pxa_gpio_chip *c;
0807da59 EM	573	int gpio;
663707c1	574
0807da59	575	for_each_gpio_chip(gpio, c) {
df664d20 HZ	576	c->saved_gplr = readl_relaxed(c->regbase + GPLR_OFFSET);
	577	c->saved_gpdr = readl_relaxed(c->regbase + GPDR_OFFSET);
	578	c->saved_grer = readl_relaxed(c->regbase + GRER_OFFSET);
	579	c->saved_gfer = readl_relaxed(c->regbase + GFER_OFFSET);
663707c1	580
663707c1	581	/* Clear GPIO transition detect bits */
df664d20	582	writel_relaxed(0xffffffff, c->regbase + GEDR_OFFSET);
663707c1	583	}
	584	return 0;
	585	}
	586
2eaa03b5	587	static void pxa_gpio_resume(void)
663707c1	588	{
0807da59 EM	589	struct pxa_gpio_chip *c;
0807da59 EM	590	int gpio;
663707c1	591
0807da59	592	for_each_gpio_chip(gpio, c) {
663707c1	593	/* restore level with set/clear */
df664d20 HZ	594	writel_relaxed( c->saved_gplr, c->regbase + GPSR_OFFSET);
df664d20 HZ	595	writel_relaxed(~c->saved_gplr, c->regbase + GPCR_OFFSET);
663707c1	596
df664d20 HZ	597	writel_relaxed(c->saved_grer, c->regbase + GRER_OFFSET);
	598	writel_relaxed(c->saved_gfer, c->regbase + GFER_OFFSET);
	599	writel_relaxed(c->saved_gpdr, c->regbase + GPDR_OFFSET);
663707c1	600	}
663707c1	601	}
	602	#else
	603	#define pxa_gpio_suspend NULL
	604	#define pxa_gpio_resume NULL
	605	#endif
	606
2eaa03b5	607	struct syscore_ops pxa_gpio_syscore_ops = {
663707c1	608	.suspend = pxa_gpio_suspend,
	609	.resume = pxa_gpio_resume,
	610	};
157d2644 HZ	611
	612	static int __init pxa_gpio_sysinit(void)
	613	{
	614	register_syscore_ops(&pxa_gpio_syscore_ops);
	615	return 0;
	616	}
	617	postcore_initcall(pxa_gpio_sysinit);