[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-pl061.c

/*
 * Copyright (C) 2008, 2009 Provigent Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
 *
 * Data sheet: ARM DDI 0190B, September 2000
 */
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/module.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/bitops.h>
#include <linux/workqueue.h>
#include <linux/gpio.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
#include <linux/amba/pl061.h>
#include <linux/slab.h>
#include <asm/mach/irq.h>

#define GPIODIR 0x400
#define GPIOIS  0x404
#define GPIOIBE 0x408
#define GPIOIEV 0x40C
#define GPIOIE  0x410
#define GPIORIS 0x414
#define GPIOMIS 0x418
#define GPIOIC  0x41C

#define PL061_GPIO_NR	8

struct pl061_gpio {
	/* We use a list of pl061_gpio structs for each trigger IRQ in the main
	 * interrupts controller of the system. We need this to support systems
	 * in which more that one PL061s are connected to the same IRQ. The ISR
	 * interates through this list to find the source of the interrupt.
	 */
	struct list_head	list;

	/* Each of the two spinlocks protects a different set of hardware
	 * regiters and data structurs. This decouples the code of the IRQ from
	 * the GPIO code. This also makes the case of a GPIO routine call from
	 * the IRQ code simpler.
	 */
	spinlock_t		lock;		/* GPIO registers */
	spinlock_t		irq_lock;	/* IRQ registers */

	void __iomem		*base;
	int			irq_base;
	struct gpio_chip	gc;
};

static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir &= ~(1 << offset);
	writeb(gpiodir, chip->base + GPIODIR);
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
		int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	unsigned long flags;
	unsigned char gpiodir;

	if (offset >= gc->ngpio)
		return -EINVAL;

	spin_lock_irqsave(&chip->lock, flags);
	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	gpiodir = readb(chip->base + GPIODIR);
	gpiodir |= 1 << offset;
	writeb(gpiodir, chip->base + GPIODIR);

	/*
	 * gpio value is set again, because pl061 doesn't allow to set value of
	 * a gpio pin before configuring it in OUT mode.
	 */
	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	spin_unlock_irqrestore(&chip->lock, flags);

	return 0;
}

static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	return !!readb(chip->base + (1 << (offset + 2)));
}

static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
}

static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
{
	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);

	if (chip->irq_base <= 0)
		return -EINVAL;

	return chip->irq_base + offset;
}

/*
 * PL061 GPIO IRQ
 */
static void pl061_irq_disable(struct irq_data *d)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	int offset = d->irq - chip->irq_base;
	unsigned long flags;
	u8 gpioie;

	spin_lock_irqsave(&chip->irq_lock, flags);
	gpioie = readb(chip->base + GPIOIE);
	gpioie &= ~(1 << offset);
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock_irqrestore(&chip->irq_lock, flags);
}

static void pl061_irq_enable(struct irq_data *d)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	int offset = d->irq - chip->irq_base;
	unsigned long flags;
	u8 gpioie;

	spin_lock_irqsave(&chip->irq_lock, flags);
	gpioie = readb(chip->base + GPIOIE);
	gpioie |= 1 << offset;
	writeb(gpioie, chip->base + GPIOIE);
	spin_unlock_irqrestore(&chip->irq_lock, flags);
}

static int pl061_irq_type(struct irq_data *d, unsigned trigger)
{
	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
	int offset = d->irq - chip->irq_base;
	unsigned long flags;
	u8 gpiois, gpioibe, gpioiev;

	if (offset < 0 || offset >= PL061_GPIO_NR)
		return -EINVAL;

	spin_lock_irqsave(&chip->irq_lock, flags);

	gpioiev = readb(chip->base + GPIOIEV);

	gpiois = readb(chip->base + GPIOIS);
	if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
		gpiois |= 1 << offset;
		if (trigger & IRQ_TYPE_LEVEL_HIGH)
			gpioiev |= 1 << offset;
		else
			gpioiev &= ~(1 << offset);
	} else
		gpiois &= ~(1 << offset);
	writeb(gpiois, chip->base + GPIOIS);

	gpioibe = readb(chip->base + GPIOIBE);
	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
		gpioibe |= 1 << offset;
	else {
		gpioibe &= ~(1 << offset);
		if (trigger & IRQ_TYPE_EDGE_RISING)
			gpioiev |= 1 << offset;
		else if (trigger & IRQ_TYPE_EDGE_FALLING)
			gpioiev &= ~(1 << offset);
	}
	writeb(gpioibe, chip->base + GPIOIBE);

	writeb(gpioiev, chip->base + GPIOIEV);

	spin_unlock_irqrestore(&chip->irq_lock, flags);

	return 0;
}

static struct irq_chip pl061_irqchip = {
	.name		= "GPIO",
	.irq_enable	= pl061_irq_enable,
	.irq_disable	= pl061_irq_disable,
	.irq_set_type	= pl061_irq_type,
};

static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct list_head *chip_list = irq_get_handler_data(irq);
	struct list_head *ptr;
	struct pl061_gpio *chip;
	struct irq_chip *irqchip = irq_desc_get_chip(desc);

	chained_irq_enter(irqchip, desc);
	list_for_each(ptr, chip_list) {
		unsigned long pending;
		int offset;

		chip = list_entry(ptr, struct pl061_gpio, list);
		pending = readb(chip->base + GPIOMIS);
		writeb(pending, chip->base + GPIOIC);

		if (pending == 0)
			continue;

		for_each_set_bit(offset, &pending, PL061_GPIO_NR)
			generic_handle_irq(pl061_to_irq(&chip->gc, offset));
	}
	chained_irq_exit(irqchip, desc);
}

static int pl061_probe(struct amba_device *dev, const struct amba_id *id)
{
	struct pl061_platform_data *pdata;
	struct pl061_gpio *chip;
	struct list_head *chip_list;
	int ret, irq, i;
	static DECLARE_BITMAP(init_irq, NR_IRQS);

	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	if (chip == NULL)
		return -ENOMEM;

	pdata = dev->dev.platform_data;
	if (pdata) {
		chip->gc.base = pdata->gpio_base;
		chip->irq_base = pdata->irq_base;
	} else if (dev->dev.of_node) {
		chip->gc.base = -1;
		chip->irq_base = 0;
	} else {
		ret = -ENODEV;
		goto free_mem;
	}

	if (!request_mem_region(dev->res.start,
				resource_size(&dev->res), "pl061")) {
		ret = -EBUSY;
		goto free_mem;
	}

	chip->base = ioremap(dev->res.start, resource_size(&dev->res));
	if (chip->base == NULL) {
		ret = -ENOMEM;
		goto release_region;
	}

	spin_lock_init(&chip->lock);
	spin_lock_init(&chip->irq_lock);
	INIT_LIST_HEAD(&chip->list);

	chip->gc.direction_input = pl061_direction_input;
	chip->gc.direction_output = pl061_direction_output;
	chip->gc.get = pl061_get_value;
	chip->gc.set = pl061_set_value;
	chip->gc.to_irq = pl061_to_irq;
	chip->gc.ngpio = PL061_GPIO_NR;
	chip->gc.label = dev_name(&dev->dev);
	chip->gc.dev = &dev->dev;
	chip->gc.owner = THIS_MODULE;

	ret = gpiochip_add(&chip->gc);
	if (ret)
		goto iounmap;

	/*
	 * irq_chip support
	 */

	if (chip->irq_base <= 0)
		return 0;

	writeb(0, chip->base + GPIOIE); /* disable irqs */
	irq = dev->irq[0];
	if (irq < 0) {
		ret = -ENODEV;
		goto iounmap;
	}
	irq_set_chained_handler(irq, pl061_irq_handler);
	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
		chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
		if (chip_list == NULL) {
			clear_bit(irq, init_irq);
			ret = -ENOMEM;
			goto iounmap;
		}
		INIT_LIST_HEAD(chip_list);
		irq_set_handler_data(irq, chip_list);
	} else
		chip_list = irq_get_handler_data(irq);
	list_add(&chip->list, chip_list);

	for (i = 0; i < PL061_GPIO_NR; i++) {
		if (pdata) {
			if (pdata->directions & (1 << i))
				pl061_direction_output(&chip->gc, i,
						pdata->values & (1 << i));
			else
				pl061_direction_input(&chip->gc, i);
		}

		irq_set_chip_and_handler(i + chip->irq_base, &pl061_irqchip,
					 handle_simple_irq);
		set_irq_flags(i+chip->irq_base, IRQF_VALID);
		irq_set_chip_data(i + chip->irq_base, chip);
	}

	return 0;

iounmap:
	iounmap(chip->base);
release_region:
	release_mem_region(dev->res.start, resource_size(&dev->res));
free_mem:
	kfree(chip);

	return ret;
}

static struct amba_id pl061_ids[] = {
	{
		.id	= 0x00041061,
		.mask	= 0x000fffff,
	},
	{ 0, 0 },
};

static struct amba_driver pl061_gpio_driver = {
	.drv = {
		.name	= "pl061_gpio",
	},
	.id_table	= pl061_ids,
	.probe		= pl061_probe,
};

static int __init pl061_gpio_init(void)
{
	return amba_driver_register(&pl061_gpio_driver);
}
subsys_initcall(pl061_gpio_init);

MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
MODULE_DESCRIPTION("PL061 GPIO driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
1e9c2859	1	/*
c103de24	2	* Copyright (C) 2008, 2009 Provigent Ltd.
1e9c2859 BS	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*
	8	* Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)
	9	*
	10	* Data sheet: ARM DDI 0190B, September 2000
	11	*/
	12	#include <linux/spinlock.h>
	13	#include <linux/errno.h>
	14	#include <linux/module.h>
	15	#include <linux/list.h>
	16	#include <linux/io.h>
	17	#include <linux/ioport.h>
	18	#include <linux/irq.h>
	19	#include <linux/bitops.h>
	20	#include <linux/workqueue.h>
	21	#include <linux/gpio.h>
	22	#include <linux/device.h>
	23	#include <linux/amba/bus.h>
	24	#include <linux/amba/pl061.h>
5a0e3ad6	25	#include <linux/slab.h>
dece904d	26	#include <asm/mach/irq.h>
1e9c2859 BS	27
	28	#define GPIODIR 0x400
	29	#define GPIOIS 0x404
	30	#define GPIOIBE 0x408
	31	#define GPIOIEV 0x40C
	32	#define GPIOIE 0x410
	33	#define GPIORIS 0x414
	34	#define GPIOMIS 0x418
	35	#define GPIOIC 0x41C
	36
	37	#define PL061_GPIO_NR 8
	38
	39	struct pl061_gpio {
	40	/* We use a list of pl061_gpio structs for each trigger IRQ in the main
	41	* interrupts controller of the system. We need this to support systems
	42	* in which more that one PL061s are connected to the same IRQ. The ISR
	43	* interates through this list to find the source of the interrupt.
	44	*/
	45	struct list_head list;
	46
	47	/* Each of the two spinlocks protects a different set of hardware
	48	* regiters and data structurs. This decouples the code of the IRQ from
	49	* the GPIO code. This also makes the case of a GPIO routine call from
	50	* the IRQ code simpler.
	51	*/
	52	spinlock_t lock; /* GPIO registers */
	53	spinlock_t irq_lock; /* IRQ registers */
	54
	55	void __iomem *base;
f2ab2ba0	56	int irq_base;
1e9c2859 BS	57	struct gpio_chip gc;
	58	};
	59
	60	static int pl061_direction_input(struct gpio_chip *gc, unsigned offset)
	61	{
	62	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	63	unsigned long flags;
	64	unsigned char gpiodir;
	65
	66	if (offset >= gc->ngpio)
	67	return -EINVAL;
	68
	69	spin_lock_irqsave(&chip->lock, flags);
	70	gpiodir = readb(chip->base + GPIODIR);
	71	gpiodir &= ~(1 << offset);
	72	writeb(gpiodir, chip->base + GPIODIR);
	73	spin_unlock_irqrestore(&chip->lock, flags);
	74
	75	return 0;
	76	}
	77
	78	static int pl061_direction_output(struct gpio_chip *gc, unsigned offset,
	79	int value)
	80	{
	81	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	82	unsigned long flags;
	83	unsigned char gpiodir;
	84
	85	if (offset >= gc->ngpio)
	86	return -EINVAL;
	87
	88	spin_lock_irqsave(&chip->lock, flags);
	89	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	90	gpiodir = readb(chip->base + GPIODIR);
	91	gpiodir \|= 1 << offset;
	92	writeb(gpiodir, chip->base + GPIODIR);
64b997c5 VK	93
	94	/*
	95	* gpio value is set again, because pl061 doesn't allow to set value of
	96	* a gpio pin before configuring it in OUT mode.
	97	*/
	98	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
1e9c2859 BS	99	spin_unlock_irqrestore(&chip->lock, flags);
	100
	101	return 0;
	102	}
	103
	104	static int pl061_get_value(struct gpio_chip *gc, unsigned offset)
	105	{
	106	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	107
	108	return !!readb(chip->base + (1 << (offset + 2)));
	109	}
	110
	111	static void pl061_set_value(struct gpio_chip *gc, unsigned offset, int value)
	112	{
	113	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	114
	115	writeb(!!value << offset, chip->base + (1 << (offset + 2)));
	116	}
	117
50efacf6 BS	118	static int pl061_to_irq(struct gpio_chip *gc, unsigned offset)
	119	{
	120	struct pl061_gpio *chip = container_of(gc, struct pl061_gpio, gc);
	121
f2ab2ba0	122	if (chip->irq_base <= 0)
50efacf6 BS	123	return -EINVAL;
	124
	125	return chip->irq_base + offset;
	126	}
	127
1e9c2859 BS	128	/*
	129	* PL061 GPIO IRQ
	130	*/
b2221869	131	static void pl061_irq_disable(struct irq_data *d)
1e9c2859	132	{
b2221869 LB	133	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
b2221869 LB	134	int offset = d->irq - chip->irq_base;
1e9c2859 BS	135	unsigned long flags;
	136	u8 gpioie;
	137
	138	spin_lock_irqsave(&chip->irq_lock, flags);
	139	gpioie = readb(chip->base + GPIOIE);
	140	gpioie &= ~(1 << offset);
	141	writeb(gpioie, chip->base + GPIOIE);
	142	spin_unlock_irqrestore(&chip->irq_lock, flags);
	143	}
	144
b2221869	145	static void pl061_irq_enable(struct irq_data *d)
1e9c2859	146	{
b2221869 LB	147	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
b2221869 LB	148	int offset = d->irq - chip->irq_base;
1e9c2859 BS	149	unsigned long flags;
	150	u8 gpioie;
	151
	152	spin_lock_irqsave(&chip->irq_lock, flags);
	153	gpioie = readb(chip->base + GPIOIE);
	154	gpioie \|= 1 << offset;
	155	writeb(gpioie, chip->base + GPIOIE);
	156	spin_unlock_irqrestore(&chip->irq_lock, flags);
	157	}
	158
b2221869	159	static int pl061_irq_type(struct irq_data *d, unsigned trigger)
1e9c2859	160	{
b2221869 LB	161	struct pl061_gpio *chip = irq_data_get_irq_chip_data(d);
b2221869 LB	162	int offset = d->irq - chip->irq_base;
1e9c2859 BS	163	unsigned long flags;
	164	u8 gpiois, gpioibe, gpioiev;
	165
c1cc9b97	166	if (offset < 0 \|\| offset >= PL061_GPIO_NR)
1e9c2859 BS	167	return -EINVAL;
	168
	169	spin_lock_irqsave(&chip->irq_lock, flags);
	170
	171	gpioiev = readb(chip->base + GPIOIEV);
	172
	173	gpiois = readb(chip->base + GPIOIS);
	174	if (trigger & (IRQ_TYPE_LEVEL_HIGH \| IRQ_TYPE_LEVEL_LOW)) {
	175	gpiois \|= 1 << offset;
	176	if (trigger & IRQ_TYPE_LEVEL_HIGH)
	177	gpioiev \|= 1 << offset;
	178	else
	179	gpioiev &= ~(1 << offset);
	180	} else
	181	gpiois &= ~(1 << offset);
	182	writeb(gpiois, chip->base + GPIOIS);
	183
	184	gpioibe = readb(chip->base + GPIOIBE);
	185	if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
	186	gpioibe \|= 1 << offset;
	187	else {
	188	gpioibe &= ~(1 << offset);
	189	if (trigger & IRQ_TYPE_EDGE_RISING)
	190	gpioiev \|= 1 << offset;
db7e1bc4	191	else if (trigger & IRQ_TYPE_EDGE_FALLING)
1e9c2859 BS	192	gpioiev &= ~(1 << offset);
	193	}
	194	writeb(gpioibe, chip->base + GPIOIBE);
	195
	196	writeb(gpioiev, chip->base + GPIOIEV);
	197
	198	spin_unlock_irqrestore(&chip->irq_lock, flags);
	199
	200	return 0;
	201	}
	202
	203	static struct irq_chip pl061_irqchip = {
	204	.name = "GPIO",
b2221869 LB	205	.irq_enable = pl061_irq_enable,
	206	.irq_disable = pl061_irq_disable,
	207	.irq_set_type = pl061_irq_type,
1e9c2859 BS	208	};
	209
	210	static void pl061_irq_handler(unsigned irq, struct irq_desc *desc)
	211	{
b51804bc	212	struct list_head *chip_list = irq_get_handler_data(irq);
1e9c2859 BS	213	struct list_head *ptr;
1e9c2859 BS	214	struct pl061_gpio *chip;
dece904d	215	struct irq_chip *irqchip = irq_desc_get_chip(desc);
1e9c2859	216
dece904d	217	chained_irq_enter(irqchip, desc);
1e9c2859 BS	218	list_for_each(ptr, chip_list) {
1e9c2859 BS	219	unsigned long pending;
50efacf6	220	int offset;
1e9c2859 BS	221
	222	chip = list_entry(ptr, struct pl061_gpio, list);
	223	pending = readb(chip->base + GPIOMIS);
	224	writeb(pending, chip->base + GPIOIC);
	225
	226	if (pending == 0)
	227	continue;
	228
984b3f57	229	for_each_set_bit(offset, &pending, PL061_GPIO_NR)
50efacf6	230	generic_handle_irq(pl061_to_irq(&chip->gc, offset));
1e9c2859	231	}
dece904d	232	chained_irq_exit(irqchip, desc);
1e9c2859 BS	233	}
1e9c2859 BS	234
aa25afad	235	static int pl061_probe(struct amba_device dev, const struct amba_id id)
1e9c2859 BS	236	{
	237	struct pl061_platform_data *pdata;
	238	struct pl061_gpio *chip;
	239	struct list_head *chip_list;
	240	int ret, irq, i;
79d7f4ee	241	static DECLARE_BITMAP(init_irq, NR_IRQS);
1e9c2859	242
1e9c2859 BS	243	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
	244	if (chip == NULL)
	245	return -ENOMEM;
	246
76c05c8a RH	247	pdata = dev->dev.platform_data;
	248	if (pdata) {
	249	chip->gc.base = pdata->gpio_base;
	250	chip->irq_base = pdata->irq_base;
	251	} else if (dev->dev.of_node) {
	252	chip->gc.base = -1;
f2ab2ba0	253	chip->irq_base = 0;
76c05c8a RH	254	} else {
	255	ret = -ENODEV;
	256	goto free_mem;
	257	}
	258
1e9c2859 BS	259	if (!request_mem_region(dev->res.start,
	260	resource_size(&dev->res), "pl061")) {
	261	ret = -EBUSY;
	262	goto free_mem;
	263	}
	264
	265	chip->base = ioremap(dev->res.start, resource_size(&dev->res));
	266	if (chip->base == NULL) {
	267	ret = -ENOMEM;
	268	goto release_region;
	269	}
	270
	271	spin_lock_init(&chip->lock);
	272	spin_lock_init(&chip->irq_lock);
	273	INIT_LIST_HEAD(&chip->list);
	274
	275	chip->gc.direction_input = pl061_direction_input;
	276	chip->gc.direction_output = pl061_direction_output;
	277	chip->gc.get = pl061_get_value;
	278	chip->gc.set = pl061_set_value;
50efacf6	279	chip->gc.to_irq = pl061_to_irq;
1e9c2859 BS	280	chip->gc.ngpio = PL061_GPIO_NR;
	281	chip->gc.label = dev_name(&dev->dev);
	282	chip->gc.dev = &dev->dev;
	283	chip->gc.owner = THIS_MODULE;
	284
1e9c2859 BS	285	ret = gpiochip_add(&chip->gc);
	286	if (ret)
	287	goto iounmap;
	288
	289	/*
	290	* irq_chip support
	291	*/
	292
f2ab2ba0	293	if (chip->irq_base <= 0)
1e9c2859 BS	294	return 0;
	295
	296	writeb(0, chip->base + GPIOIE); /* disable irqs */
	297	irq = dev->irq[0];
	298	if (irq < 0) {
	299	ret = -ENODEV;
	300	goto iounmap;
	301	}
b51804bc	302	irq_set_chained_handler(irq, pl061_irq_handler);
1e9c2859 BS	303	if (!test_and_set_bit(irq, init_irq)) { /* list initialized? */
	304	chip_list = kmalloc(sizeof(*chip_list), GFP_KERNEL);
	305	if (chip_list == NULL) {
79d7f4ee	306	clear_bit(irq, init_irq);
1e9c2859 BS	307	ret = -ENOMEM;
	308	goto iounmap;
	309	}
	310	INIT_LIST_HEAD(chip_list);
b51804bc	311	irq_set_handler_data(irq, chip_list);
1e9c2859	312	} else
b51804bc	313	chip_list = irq_get_handler_data(irq);
1e9c2859 BS	314	list_add(&chip->list, chip_list);
	315
	316	for (i = 0; i < PL061_GPIO_NR; i++) {
76c05c8a RH	317	if (pdata) {
	318	if (pdata->directions & (1 << i))
	319	pl061_direction_output(&chip->gc, i,
	320	pdata->values & (1 << i));
	321	else
	322	pl061_direction_input(&chip->gc, i);
	323	}
1e9c2859	324
08f1b807 TG	325	irq_set_chip_and_handler(i + chip->irq_base, &pl061_irqchip,
08f1b807 TG	326	handle_simple_irq);
1e9c2859	327	set_irq_flags(i+chip->irq_base, IRQF_VALID);
b51804bc	328	irq_set_chip_data(i + chip->irq_base, chip);
1e9c2859 BS	329	}
	330
	331	return 0;
	332
	333	iounmap:
	334	iounmap(chip->base);
	335	release_region:
	336	release_mem_region(dev->res.start, resource_size(&dev->res));
	337	free_mem:
	338	kfree(chip);
	339
	340	return ret;
	341	}
	342
2c39c9e1	343	static struct amba_id pl061_ids[] = {
1e9c2859 BS	344	{
	345	.id = 0x00041061,
	346	.mask = 0x000fffff,
	347	},
	348	{ 0, 0 },
	349	};
	350
	351	static struct amba_driver pl061_gpio_driver = {
	352	.drv = {
	353	.name = "pl061_gpio",
	354	},
	355	.id_table = pl061_ids,
	356	.probe = pl061_probe,
	357	};
	358
	359	static int __init pl061_gpio_init(void)
	360	{
	361	return amba_driver_register(&pl061_gpio_driver);
	362	}
	363	subsys_initcall(pl061_gpio_init);
	364
	365	MODULE_AUTHOR("Baruch Siach <baruch@tkos.co.il>");
	366	MODULE_DESCRIPTION("PL061 GPIO driver");
	367	MODULE_LICENSE("GPL");