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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris...
[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-omap.c
CommitLineData
5e1c5ff4 1/*
5e1c5ff4
TL		 2 * Support functions for OMAP GPIO
3 *
92105bb7 4 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 6 *
44169075
SS		 7 * Copyright (C) 2009 Texas Instruments
8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9 *
5e1c5ff4
TL		 10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
5e1c5ff4
TL		 15#include <linux/init.h>
16#include <linux/module.h>
5e1c5ff4 17#include <linux/interrupt.h>
3c437ffd 18#include <linux/syscore_ops.h>
92105bb7 19#include <linux/err.h>
f8ce2547 20#include <linux/clk.h>
fced80c7 21#include <linux/io.h>
96751fcb 22#include <linux/device.h>
77640aab 23#include <linux/pm_runtime.h>
55b93c32 24#include <linux/pm.h>
384ebe1c
BC		 25#include <linux/of.h>
26#include <linux/of_device.h>
27#include <linux/irqdomain.h>
5e1c5ff4 28
a09e64fb 29#include <mach/hardware.h>
5e1c5ff4 30#include <asm/irq.h>
a09e64fb 31#include <mach/irqs.h>
1bc857f7 32#include <asm/gpio.h>
5e1c5ff4
TL		 33#include <asm/mach/irq.h>
34
2dc983c5
TKD		 35#define OFF_MODE 1
36
03e128ca
C		 37static LIST_HEAD(omap_gpio_list);
38
6d62e216
C		 39struct gpio_regs {
40 u32 irqenable1;
41 u32 irqenable2;
42 u32 wake_en;
43 u32 ctrl;
44 u32 oe;
45 u32 leveldetect0;
46 u32 leveldetect1;
47 u32 risingdetect;
48 u32 fallingdetect;
49 u32 dataout;
ae547354
NM		 50 u32 debounce;
51 u32 debounce_en;
6d62e216
C		 52};
53
5e1c5ff4 54struct gpio_bank {
03e128ca 55 struct list_head node;
92105bb7 56 void __iomem *base;
5e1c5ff4 57 u16 irq;
384ebe1c
BC		 58 int irq_base;
59 struct irq_domain *domain;
92105bb7
TL		 60 u32 suspend_wakeup;
61 u32 saved_wakeup;
3ac4fa99
JY		 62 u32 non_wakeup_gpios;
63 u32 enabled_non_wakeup_gpios;
6d62e216 64 struct gpio_regs context;
3ac4fa99
JY		 65 u32 saved_datain;
66 u32 saved_fallingdetect;
67 u32 saved_risingdetect;
b144ff6f 68 u32 level_mask;
4318f36b 69 u32 toggle_mask;
5e1c5ff4 70 spinlock_t lock;
52e31344 71 struct gpio_chip chip;
89db9482 72 struct clk *dbck;
058af1ea 73 u32 mod_usage;
8865b9b6 74 u32 dbck_enable_mask;
72f83af9 75 bool dbck_enabled;
77640aab 76 struct device *dev;
d0d665a8 77 bool is_mpuio;
77640aab 78 bool dbck_flag;
0cde8d03 79 bool loses_context;
5de62b86 80 int stride;
d5f46247 81 u32 width;
60a3437d 82 int context_loss_count;
2dc983c5
TKD		 83 int power_mode;
84 bool workaround_enabled;
fa87931a
KH		 85
86 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
60a3437d 87 int (*get_context_loss_count)(struct device *dev);
fa87931a
KH		 88
89 struct omap_gpio_reg_offs *regs;
5e1c5ff4
TL		 90};
91
129fd223
KH		 92#define GPIO_INDEX(bank, gpio) (gpio % bank->width)
93#define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
c8eef65a 94#define GPIO_MOD_CTRL_BIT BIT(0)
5e1c5ff4 95
25db711d
BC		 96static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
97{
98 return gpio_irq - bank->irq_base + bank->chip.base;
99}
100
5e1c5ff4
TL		 101static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
102{
92105bb7 103 void __iomem *reg = bank->base;
5e1c5ff4
TL		 104 u32 l;
105
fa87931a 106 reg += bank->regs->direction;
5e1c5ff4
TL		 107 l = __raw_readl(reg);
108 if (is_input)
109 l |= 1 << gpio;
110 else
111 l &= ~(1 << gpio);
112 __raw_writel(l, reg);
41d87cbd 113 bank->context.oe = l;
5e1c5ff4
TL		 114}
115
fa87931a
KH		 116
117/* set data out value using dedicate set/clear register */
118static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 119{
92105bb7 120 void __iomem *reg = bank->base;
fa87931a 121 u32 l = GPIO_BIT(bank, gpio);
5e1c5ff4 122
2c836f7e 123 if (enable) {
fa87931a 124 reg += bank->regs->set_dataout;
2c836f7e
TKD		 125 bank->context.dataout |= l;
126 } else {
fa87931a 127 reg += bank->regs->clr_dataout;
2c836f7e
TKD		 128 bank->context.dataout &= ~l;
129 }
5e1c5ff4 130
5e1c5ff4
TL		 131 __raw_writel(l, reg);
132}
133
fa87931a
KH		 134/* set data out value using mask register */
135static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
5e1c5ff4 136{
fa87931a
KH		 137 void __iomem *reg = bank->base + bank->regs->dataout;
138 u32 gpio_bit = GPIO_BIT(bank, gpio);
139 u32 l;
5e1c5ff4 140
fa87931a
KH		 141 l = __raw_readl(reg);
142 if (enable)
143 l |= gpio_bit;
144 else
145 l &= ~gpio_bit;
5e1c5ff4 146 __raw_writel(l, reg);
41d87cbd 147 bank->context.dataout = l;
5e1c5ff4
TL		 148}
149
7fcca715 150static int _get_gpio_datain(struct gpio_bank *bank, int offset)
b37c45b8 151{
fa87931a 152 void __iomem *reg = bank->base + bank->regs->datain;
b37c45b8 153
7fcca715 154 return (__raw_readl(reg) & (1 << offset)) != 0;
5e1c5ff4 155}
b37c45b8 156
7fcca715 157static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
b37c45b8 158{
fa87931a 159 void __iomem *reg = bank->base + bank->regs->dataout;
b37c45b8 160
7fcca715 161 return (__raw_readl(reg) & (1 << offset)) != 0;
b37c45b8
RQ		 162}
163
ece9528e
KH		 164static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
165{
166 int l = __raw_readl(base + reg);
167
862ff640 168 if (set)
ece9528e
KH		 169 l |= mask;
170 else
171 l &= ~mask;
172
173 __raw_writel(l, base + reg);
174}
92105bb7 175
72f83af9
TKD		 176static inline void _gpio_dbck_enable(struct gpio_bank *bank)
177{
178 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
179 clk_enable(bank->dbck);
180 bank->dbck_enabled = true;
181 }
182}
183
184static inline void _gpio_dbck_disable(struct gpio_bank *bank)
185{
186 if (bank->dbck_enable_mask && bank->dbck_enabled) {
187 clk_disable(bank->dbck);
188 bank->dbck_enabled = false;
189 }
190}
191
168ef3d9
FB		 192/**
193 * _set_gpio_debounce - low level gpio debounce time
194 * @bank: the gpio bank we're acting upon
195 * @gpio: the gpio number on this @gpio
196 * @debounce: debounce time to use
197 *
198 * OMAP's debounce time is in 31us steps so we need
199 * to convert and round up to the closest unit.
200 */
201static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
202 unsigned debounce)
203{
9942da0e 204 void __iomem *reg;
168ef3d9
FB		 205 u32 val;
206 u32 l;
207
77640aab
VC		 208 if (!bank->dbck_flag)
209 return;
210
168ef3d9
FB		 211 if (debounce < 32)
212 debounce = 0x01;
213 else if (debounce > 7936)
214 debounce = 0xff;
215 else
216 debounce = (debounce / 0x1f) - 1;
217
129fd223 218 l = GPIO_BIT(bank, gpio);
168ef3d9 219
6fd9c421 220 clk_enable(bank->dbck);
9942da0e 221 reg = bank->base + bank->regs->debounce;
168ef3d9
FB		 222 __raw_writel(debounce, reg);
223
9942da0e 224 reg = bank->base + bank->regs->debounce_en;
168ef3d9
FB		 225 val = __raw_readl(reg);
226
6fd9c421 227 if (debounce)
168ef3d9 228 val |= l;
6fd9c421 229 else
168ef3d9 230 val &= ~l;
f7ec0b0b 231 bank->dbck_enable_mask = val;
168ef3d9
FB		 232
233 __raw_writel(val, reg);
6fd9c421
TKD		 234 clk_disable(bank->dbck);
235 /*
236 * Enable debounce clock per module.
237 * This call is mandatory because in omap_gpio_request() when
238 * *_runtime_get_sync() is called, _gpio_dbck_enable() within
239 * runtime callbck fails to turn on dbck because dbck_enable_mask
240 * used within _gpio_dbck_enable() is still not initialized at
241 * that point. Therefore we have to enable dbck here.
242 */
243 _gpio_dbck_enable(bank);
ae547354
NM		 244 if (bank->dbck_enable_mask) {
245 bank->context.debounce = debounce;
246 bank->context.debounce_en = val;
247 }
168ef3d9
FB		 248}
249
5e571f38 250static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
00ece7e4 251 unsigned trigger)
5e1c5ff4 252{
3ac4fa99 253 void __iomem *base = bank->base;
92105bb7
TL		 254 u32 gpio_bit = 1 << gpio;
255
5e571f38
TKD		 256 _gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
257 trigger & IRQ_TYPE_LEVEL_LOW);
258 _gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
259 trigger & IRQ_TYPE_LEVEL_HIGH);
260 _gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
261 trigger & IRQ_TYPE_EDGE_RISING);
262 _gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
263 trigger & IRQ_TYPE_EDGE_FALLING);
264
41d87cbd
TKD		 265 bank->context.leveldetect0 =
266 __raw_readl(bank->base + bank->regs->leveldetect0);
267 bank->context.leveldetect1 =
268 __raw_readl(bank->base + bank->regs->leveldetect1);
269 bank->context.risingdetect =
270 __raw_readl(bank->base + bank->regs->risingdetect);
271 bank->context.fallingdetect =
272 __raw_readl(bank->base + bank->regs->fallingdetect);
273
274 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
5e571f38 275 _gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
41d87cbd
TKD		 276 bank->context.wake_en =
277 __raw_readl(bank->base + bank->regs->wkup_en);
278 }
5e571f38 279
55b220ca 280 /* This part needs to be executed always for OMAP{34xx, 44xx} */
5e571f38
TKD		 281 if (!bank->regs->irqctrl) {
282 /* On omap24xx proceed only when valid GPIO bit is set */
283 if (bank->non_wakeup_gpios) {
284 if (!(bank->non_wakeup_gpios & gpio_bit))
285 goto exit;
286 }
287
699117a6
CW		 288 /*
289 * Log the edge gpio and manually trigger the IRQ
290 * after resume if the input level changes
291 * to avoid irq lost during PER RET/OFF mode
292 * Applies for omap2 non-wakeup gpio and all omap3 gpios
293 */
294 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 295 bank->enabled_non_wakeup_gpios |= gpio_bit;
296 else
297 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
298 }
5eb3bb9c 299
5e571f38 300exit:
9ea14d8c
TKD		 301 bank->level_mask =
302 __raw_readl(bank->base + bank->regs->leveldetect0) |
303 __raw_readl(bank->base + bank->regs->leveldetect1);
92105bb7
TL		 304}
305
9198bcd3 306#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 307/*
308 * This only applies to chips that can't do both rising and falling edge
309 * detection at once. For all other chips, this function is a noop.
310 */
311static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
312{
313 void __iomem *reg = bank->base;
314 u32 l = 0;
315
5e571f38 316 if (!bank->regs->irqctrl)
4318f36b 317 return;
5e571f38
TKD		 318
319 reg += bank->regs->irqctrl;
4318f36b
CM		 320
321 l = __raw_readl(reg);
322 if ((l >> gpio) & 1)
323 l &= ~(1 << gpio);
324 else
325 l |= 1 << gpio;
326
327 __raw_writel(l, reg);
328}
5e571f38
TKD		 329#else
330static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
9198bcd3 331#endif
4318f36b 332
00ece7e4
TKD		 333static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
334 unsigned trigger)
92105bb7
TL		 335{
336 void __iomem *reg = bank->base;
5e571f38 337 void __iomem *base = bank->base;
92105bb7 338 u32 l = 0;
5e1c5ff4 339
5e571f38
TKD		 340 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
341 set_gpio_trigger(bank, gpio, trigger);
342 } else if (bank->regs->irqctrl) {
343 reg += bank->regs->irqctrl;
344
5e1c5ff4 345 l = __raw_readl(reg);
29501577 346 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 347 bank->toggle_mask |= 1 << gpio;
6cab4860 348 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 349 l |= 1 << gpio;
6cab4860 350 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 351 l &= ~(1 << gpio);
92105bb7 352 else
5e571f38
TKD		 353 return -EINVAL;
354
355 __raw_writel(l, reg);
356 } else if (bank->regs->edgectrl1) {
5e1c5ff4 357 if (gpio & 0x08)
5e571f38 358 reg += bank->regs->edgectrl2;
5e1c5ff4 359 else
5e571f38
TKD		 360 reg += bank->regs->edgectrl1;
361
5e1c5ff4
TL		 362 gpio &= 0x07;
363 l = __raw_readl(reg);
364 l &= ~(3 << (gpio << 1));
6cab4860 365 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 366 l |= 2 << (gpio << 1);
6cab4860 367 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 368 l |= 1 << (gpio << 1);
5e571f38
TKD		 369
370 /* Enable wake-up during idle for dynamic tick */
371 _gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
41d87cbd
TKD		 372 bank->context.wake_en =
373 __raw_readl(bank->base + bank->regs->wkup_en);
5e571f38 374 __raw_writel(l, reg);
5e1c5ff4 375 }
92105bb7 376 return 0;
5e1c5ff4
TL		 377}
378
e9191028 379static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4 380{
25db711d 381 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
92105bb7
TL		 382 unsigned gpio;
383 int retval;
a6472533 384 unsigned long flags;
92105bb7 385
e9191028
LB		 386 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
387 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 388 else
25db711d 389 gpio = irq_to_gpio(bank, d->irq);
5e1c5ff4 390
e5c56ed3 391 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 392 return -EINVAL;
e5c56ed3 393
9ea14d8c
TKD		 394 if (!bank->regs->leveldetect0 &&
395 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 396 return -EINVAL;
397
a6472533 398 spin_lock_irqsave(&bank->lock, flags);
129fd223 399 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
a6472533 400 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 401
402 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 403 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 404 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 405 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 406
92105bb7 407 return retval;
5e1c5ff4
TL		 408}
409
410static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
411{
92105bb7 412 void __iomem *reg = bank->base;
5e1c5ff4 413
eef4bec7 414 reg += bank->regs->irqstatus;
5e1c5ff4 415 __raw_writel(gpio_mask, reg);
bee7930f
HD		 416
417 /* Workaround for clearing DSP GPIO interrupts to allow retention */
eef4bec7
KH		 418 if (bank->regs->irqstatus2) {
419 reg = bank->base + bank->regs->irqstatus2;
bedfd154 420 __raw_writel(gpio_mask, reg);
eef4bec7 421 }
bedfd154
RQ		 422
423 /* Flush posted write for the irq status to avoid spurious interrupts */
424 __raw_readl(reg);
5e1c5ff4
TL		 425}
426
427static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
428{
129fd223 429 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 430}
431
ea6dedd7
ID		 432static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
433{
434 void __iomem *reg = bank->base;
99c47707 435 u32 l;
c390aad0 436 u32 mask = (1 << bank->width) - 1;
ea6dedd7 437
28f3b5a0 438 reg += bank->regs->irqenable;
99c47707 439 l = __raw_readl(reg);
28f3b5a0 440 if (bank->regs->irqenable_inv)
99c47707
ID		 441 l = ~l;
442 l &= mask;
443 return l;
ea6dedd7
ID		 444}
445
28f3b5a0 446static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
5e1c5ff4 447{
92105bb7 448 void __iomem *reg = bank->base;
5e1c5ff4
TL		 449 u32 l;
450
28f3b5a0
KH		 451 if (bank->regs->set_irqenable) {
452 reg += bank->regs->set_irqenable;
453 l = gpio_mask;
2a900eb7 454 bank->context.irqenable1 |= gpio_mask;
28f3b5a0
KH		 455 } else {
456 reg += bank->regs->irqenable;
5e1c5ff4 457 l = __raw_readl(reg);
28f3b5a0
KH		 458 if (bank->regs->irqenable_inv)
459 l &= ~gpio_mask;
5e1c5ff4
TL		 460 else
461 l |= gpio_mask;
2a900eb7 462 bank->context.irqenable1 = l;
28f3b5a0
KH		 463 }
464
465 __raw_writel(l, reg);
466}
467
468static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
469{
470 void __iomem *reg = bank->base;
471 u32 l;
472
473 if (bank->regs->clr_irqenable) {
474 reg += bank->regs->clr_irqenable;
5e1c5ff4 475 l = gpio_mask;
2a900eb7 476 bank->context.irqenable1 &= ~gpio_mask;
28f3b5a0
KH		 477 } else {
478 reg += bank->regs->irqenable;
56739a69 479 l = __raw_readl(reg);
28f3b5a0 480 if (bank->regs->irqenable_inv)
56739a69 481 l |= gpio_mask;
92105bb7 482 else
28f3b5a0 483 l &= ~gpio_mask;
2a900eb7 484 bank->context.irqenable1 = l;
5e1c5ff4 485 }
28f3b5a0 486
5e1c5ff4
TL		 487 __raw_writel(l, reg);
488}
489
490static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
491{
8276536c
TKD		 492 if (enable)
493 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
494 else
495 _disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
5e1c5ff4
TL		 496}
497
92105bb7
TL		 498/*
499 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
500 * 1510 does not seem to have a wake-up register. If JTAG is connected
501 * to the target, system will wake up always on GPIO events. While
502 * system is running all registered GPIO interrupts need to have wake-up
503 * enabled. When system is suspended, only selected GPIO interrupts need
504 * to have wake-up enabled.
505 */
506static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
507{
f64ad1a0
KH		 508 u32 gpio_bit = GPIO_BIT(bank, gpio);
509 unsigned long flags;
a6472533 510
f64ad1a0 511 if (bank->non_wakeup_gpios & gpio_bit) {
862ff640 512 dev_err(bank->dev,
f64ad1a0 513 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
92105bb7
TL		 514 return -EINVAL;
515 }
f64ad1a0
KH		 516
517 spin_lock_irqsave(&bank->lock, flags);
518 if (enable)
519 bank->suspend_wakeup |= gpio_bit;
520 else
521 bank->suspend_wakeup &= ~gpio_bit;
522
381a752f 523 __raw_writel(bank->suspend_wakeup, bank->base + bank->regs->wkup_en);
f64ad1a0
KH		 524 spin_unlock_irqrestore(&bank->lock, flags);
525
526 return 0;
92105bb7
TL		 527}
528
4196dd6b
TL		 529static void _reset_gpio(struct gpio_bank *bank, int gpio)
530{
129fd223 531 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
4196dd6b
TL		 532 _set_gpio_irqenable(bank, gpio, 0);
533 _clear_gpio_irqstatus(bank, gpio);
129fd223 534 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 535}
536
92105bb7 537/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 538static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 539{
25db711d
BC		 540 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
541 unsigned int gpio = irq_to_gpio(bank, d->irq);
92105bb7 542
25db711d 543 return _set_gpio_wakeup(bank, gpio, enable);
92105bb7
TL		 544}
545
3ff164e1 546static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 547{
3ff164e1 548 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 549 unsigned long flags;
52e31344 550
55b93c32
TKD		 551 /*
552 * If this is the first gpio_request for the bank,
553 * enable the bank module.
554 */
555 if (!bank->mod_usage)
556 pm_runtime_get_sync(bank->dev);
92105bb7 557
55b93c32 558 spin_lock_irqsave(&bank->lock, flags);
4196dd6b
TL		 559 /* Set trigger to none. You need to enable the desired trigger with
560 * request_irq() or set_irq_type().
561 */
3ff164e1 562 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 563
fad96ea8
C		 564 if (bank->regs->pinctrl) {
565 void __iomem *reg = bank->base + bank->regs->pinctrl;
5e1c5ff4 566
92105bb7 567 /* Claim the pin for MPU */
3ff164e1 568 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4 569 }
fad96ea8 570
c8eef65a
C		 571 if (bank->regs->ctrl && !bank->mod_usage) {
572 void __iomem *reg = bank->base + bank->regs->ctrl;
573 u32 ctrl;
574
575 ctrl = __raw_readl(reg);
576 /* Module is enabled, clocks are not gated */
577 ctrl &= ~GPIO_MOD_CTRL_BIT;
578 __raw_writel(ctrl, reg);
41d87cbd 579 bank->context.ctrl = ctrl;
058af1ea 580 }
c8eef65a
C		 581
582 bank->mod_usage |= 1 << offset;
583
a6472533 584 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 585
586 return 0;
587}
588
3ff164e1 589static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 590{
3ff164e1 591 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
6ed87c5b 592 void __iomem *base = bank->base;
a6472533 593 unsigned long flags;
5e1c5ff4 594
a6472533 595 spin_lock_irqsave(&bank->lock, flags);
6ed87c5b 596
41d87cbd 597 if (bank->regs->wkup_en) {
9f096868 598 /* Disable wake-up during idle for dynamic tick */
6ed87c5b 599 _gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
41d87cbd
TKD		 600 bank->context.wake_en =
601 __raw_readl(bank->base + bank->regs->wkup_en);
602 }
6ed87c5b 603
c8eef65a
C		 604 bank->mod_usage &= ~(1 << offset);
605
606 if (bank->regs->ctrl && !bank->mod_usage) {
607 void __iomem *reg = bank->base + bank->regs->ctrl;
608 u32 ctrl;
609
610 ctrl = __raw_readl(reg);
611 /* Module is disabled, clocks are gated */
612 ctrl |= GPIO_MOD_CTRL_BIT;
613 __raw_writel(ctrl, reg);
41d87cbd 614 bank->context.ctrl = ctrl;
058af1ea 615 }
c8eef65a 616
3ff164e1 617 _reset_gpio(bank, bank->chip.base + offset);
a6472533 618 spin_unlock_irqrestore(&bank->lock, flags);
55b93c32
TKD		 619
620 /*
621 * If this is the last gpio to be freed in the bank,
622 * disable the bank module.
623 */
624 if (!bank->mod_usage)
625 pm_runtime_put(bank->dev);
5e1c5ff4
TL		 626}
627
628/*
629 * We need to unmask the GPIO bank interrupt as soon as possible to
630 * avoid missing GPIO interrupts for other lines in the bank.
631 * Then we need to mask-read-clear-unmask the triggered GPIO lines
632 * in the bank to avoid missing nested interrupts for a GPIO line.
633 * If we wait to unmask individual GPIO lines in the bank after the
634 * line's interrupt handler has been run, we may miss some nested
635 * interrupts.
636 */
10dd5ce2 637static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 638{
92105bb7 639 void __iomem *isr_reg = NULL;
5e1c5ff4 640 u32 isr;
4318f36b 641 unsigned int gpio_irq, gpio_index;
5e1c5ff4 642 struct gpio_bank *bank;
ea6dedd7
ID		 643 u32 retrigger = 0;
644 int unmasked = 0;
ee144182 645 struct irq_chip *chip = irq_desc_get_chip(desc);
5e1c5ff4 646
ee144182 647 chained_irq_enter(chip, desc);
5e1c5ff4 648
6845664a 649 bank = irq_get_handler_data(irq);
eef4bec7 650 isr_reg = bank->base + bank->regs->irqstatus;
55b93c32 651 pm_runtime_get_sync(bank->dev);
b1cc4c55
EK		 652
653 if (WARN_ON(!isr_reg))
654 goto exit;
655
92105bb7 656 while(1) {
6e60e79a 657 u32 isr_saved, level_mask = 0;
ea6dedd7 658 u32 enabled;
6e60e79a 659
ea6dedd7
ID		 660 enabled = _get_gpio_irqbank_mask(bank);
661 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a 662
9ea14d8c 663 if (bank->level_mask)
b144ff6f 664 level_mask = bank->level_mask & enabled;
6e60e79a
TL		 665
666 /* clear edge sensitive interrupts before handler(s) are
667 called so that we don't miss any interrupt occurred while
668 executing them */
28f3b5a0 669 _disable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a 670 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
28f3b5a0 671 _enable_gpio_irqbank(bank, isr_saved & ~level_mask);
6e60e79a
TL		 672
673 /* if there is only edge sensitive GPIO pin interrupts
674 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 675 if (!level_mask && !unmasked) {
676 unmasked = 1;
ee144182 677 chained_irq_exit(chip, desc);
ea6dedd7 678 }
92105bb7 679
ea6dedd7
ID		 680 isr |= retrigger;
681 retrigger = 0;
92105bb7
TL		 682 if (!isr)
683 break;
684
384ebe1c 685 gpio_irq = bank->irq_base;
92105bb7 686 for (; isr != 0; isr >>= 1, gpio_irq++) {
25db711d 687 int gpio = irq_to_gpio(bank, gpio_irq);
4318f36b 688
92105bb7
TL		 689 if (!(isr & 1))
690 continue;
29454dde 691
25db711d
BC		 692 gpio_index = GPIO_INDEX(bank, gpio);
693
4318f36b
CM		 694 /*
695 * Some chips can't respond to both rising and falling
696 * at the same time. If this irq was requested with
697 * both flags, we need to flip the ICR data for the IRQ
698 * to respond to the IRQ for the opposite direction.
699 * This will be indicated in the bank toggle_mask.
700 */
701 if (bank->toggle_mask & (1 << gpio_index))
702 _toggle_gpio_edge_triggering(bank, gpio_index);
4318f36b 703
d8aa0251 704 generic_handle_irq(gpio_irq);
92105bb7 705 }
1a8bfa1e 706 }
ea6dedd7
ID		 707 /* if bank has any level sensitive GPIO pin interrupt
708 configured, we must unmask the bank interrupt only after
709 handler(s) are executed in order to avoid spurious bank
710 interrupt */
b1cc4c55 711exit:
ea6dedd7 712 if (!unmasked)
ee144182 713 chained_irq_exit(chip, desc);
55b93c32 714 pm_runtime_put(bank->dev);
5e1c5ff4
TL		 715}
716
e9191028 717static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 718{
e9191028 719 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 720 unsigned int gpio = irq_to_gpio(bank, d->irq);
85ec7b97 721 unsigned long flags;
4196dd6b 722
85ec7b97 723 spin_lock_irqsave(&bank->lock, flags);
4196dd6b 724 _reset_gpio(bank, gpio);
85ec7b97 725 spin_unlock_irqrestore(&bank->lock, flags);
4196dd6b
TL		 726}
727
e9191028 728static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 729{
e9191028 730 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 731 unsigned int gpio = irq_to_gpio(bank, d->irq);
5e1c5ff4
TL		 732
733 _clear_gpio_irqstatus(bank, gpio);
734}
735
e9191028 736static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 737{
e9191028 738 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 739 unsigned int gpio = irq_to_gpio(bank, d->irq);
85ec7b97 740 unsigned long flags;
5e1c5ff4 741
85ec7b97 742 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 743 _set_gpio_irqenable(bank, gpio, 0);
129fd223 744 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
85ec7b97 745 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 746}
747
e9191028 748static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 749{
e9191028 750 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
25db711d 751 unsigned int gpio = irq_to_gpio(bank, d->irq);
129fd223 752 unsigned int irq_mask = GPIO_BIT(bank, gpio);
8c04a176 753 u32 trigger = irqd_get_trigger_type(d);
85ec7b97 754 unsigned long flags;
55b6019a 755
85ec7b97 756 spin_lock_irqsave(&bank->lock, flags);
55b6019a 757 if (trigger)
129fd223 758 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
b144ff6f
KH		 759
760 /* For level-triggered GPIOs, the clearing must be done after
761 * the HW source is cleared, thus after the handler has run */
762 if (bank->level_mask & irq_mask) {
763 _set_gpio_irqenable(bank, gpio, 0);
764 _clear_gpio_irqstatus(bank, gpio);
765 }
5e1c5ff4 766
4de8c75b 767 _set_gpio_irqenable(bank, gpio, 1);
85ec7b97 768 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 769}
770
e5c56ed3
DB		 771static struct irq_chip gpio_irq_chip = {
772 .name = "GPIO",
e9191028
LB		 773 .irq_shutdown = gpio_irq_shutdown,
774 .irq_ack = gpio_ack_irq,
775 .irq_mask = gpio_mask_irq,
776 .irq_unmask = gpio_unmask_irq,
777 .irq_set_type = gpio_irq_type,
778 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 779};
780
781/*---------------------------------------------------------------------*/
782
79ee031f 783static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 784{
79ee031f 785 struct platform_device *pdev = to_platform_device(dev);
11a78b79 786 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 787 void __iomem *mask_reg = bank->base +
788 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 789 unsigned long flags;
11a78b79 790
a6472533 791 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 792 bank->saved_wakeup = __raw_readl(mask_reg);
793 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 794 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 795
796 return 0;
797}
798
79ee031f 799static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 800{
79ee031f 801 struct platform_device *pdev = to_platform_device(dev);
11a78b79 802 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 803 void __iomem *mask_reg = bank->base +
804 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 805 unsigned long flags;
11a78b79 806
a6472533 807 spin_lock_irqsave(&bank->lock, flags);
11a78b79 808 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 809 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 810
811 return 0;
812}
813
47145210 814static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 815 .suspend_noirq = omap_mpuio_suspend_noirq,
816 .resume_noirq = omap_mpuio_resume_noirq,
817};
818
3c437ffd 819/* use platform_driver for this. */
11a78b79 820static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 821 .driver = {
822 .name = "mpuio",
79ee031f 823 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 824 },
825};
826
827static struct platform_device omap_mpuio_device = {
828 .name = "mpuio",
829 .id = -1,
830 .dev = {
831 .driver = &omap_mpuio_driver.driver,
832 }
833 /* could list the /proc/iomem resources */
834};
835
03e128ca 836static inline void mpuio_init(struct gpio_bank *bank)
11a78b79 837{
77640aab 838 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 839
11a78b79
DB		 840 if (platform_driver_register(&omap_mpuio_driver) == 0)
841 (void) platform_device_register(&omap_mpuio_device);
842}
843
e5c56ed3 844/*---------------------------------------------------------------------*/
5e1c5ff4 845
52e31344
DB		 846static int gpio_input(struct gpio_chip *chip, unsigned offset)
847{
848 struct gpio_bank *bank;
849 unsigned long flags;
850
851 bank = container_of(chip, struct gpio_bank, chip);
852 spin_lock_irqsave(&bank->lock, flags);
853 _set_gpio_direction(bank, offset, 1);
854 spin_unlock_irqrestore(&bank->lock, flags);
855 return 0;
856}
857
b37c45b8
RQ		 858static int gpio_is_input(struct gpio_bank *bank, int mask)
859{
fa87931a 860 void __iomem *reg = bank->base + bank->regs->direction;
b37c45b8 861
b37c45b8
RQ		 862 return __raw_readl(reg) & mask;
863}
864
52e31344
DB		 865static int gpio_get(struct gpio_chip *chip, unsigned offset)
866{
b37c45b8 867 struct gpio_bank *bank;
b37c45b8
RQ		 868 u32 mask;
869
a8be8daf 870 bank = container_of(chip, struct gpio_bank, chip);
7fcca715 871 mask = (1 << offset);
b37c45b8
RQ		 872
873 if (gpio_is_input(bank, mask))
7fcca715 874 return _get_gpio_datain(bank, offset);
b37c45b8 875 else
7fcca715 876 return _get_gpio_dataout(bank, offset);
52e31344
DB		 877}
878
879static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
880{
881 struct gpio_bank *bank;
882 unsigned long flags;
883
884 bank = container_of(chip, struct gpio_bank, chip);
885 spin_lock_irqsave(&bank->lock, flags);
fa87931a 886 bank->set_dataout(bank, offset, value);
52e31344
DB		 887 _set_gpio_direction(bank, offset, 0);
888 spin_unlock_irqrestore(&bank->lock, flags);
889 return 0;
890}
891
168ef3d9
FB		 892static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
893 unsigned debounce)
894{
895 struct gpio_bank *bank;
896 unsigned long flags;
897
898 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 899
900 if (!bank->dbck) {
901 bank->dbck = clk_get(bank->dev, "dbclk");
902 if (IS_ERR(bank->dbck))
903 dev_err(bank->dev, "Could not get gpio dbck\n");
904 }
905
168ef3d9
FB		 906 spin_lock_irqsave(&bank->lock, flags);
907 _set_gpio_debounce(bank, offset, debounce);
908 spin_unlock_irqrestore(&bank->lock, flags);
909
910 return 0;
911}
912
52e31344
DB		 913static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
914{
915 struct gpio_bank *bank;
916 unsigned long flags;
917
918 bank = container_of(chip, struct gpio_bank, chip);
919 spin_lock_irqsave(&bank->lock, flags);
fa87931a 920 bank->set_dataout(bank, offset, value);
52e31344
DB		 921 spin_unlock_irqrestore(&bank->lock, flags);
922}
923
a007b709
DB		 924static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
925{
926 struct gpio_bank *bank;
927
928 bank = container_of(chip, struct gpio_bank, chip);
384ebe1c 929 return bank->irq_base + offset;
a007b709
DB		 930}
931
52e31344
DB		 932/*---------------------------------------------------------------------*/
933
9a748053 934static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da 935{
e5ff4440 936 static bool called;
9f7065da
TL		 937 u32 rev;
938
e5ff4440 939 if (called || bank->regs->revision == USHRT_MAX)
9f7065da
TL		 940 return;
941
e5ff4440
KH		 942 rev = __raw_readw(bank->base + bank->regs->revision);
943 pr_info("OMAP GPIO hardware version %d.%d\n",
9f7065da 944 (rev >> 4) & 0x0f, rev & 0x0f);
e5ff4440
KH		 945
946 called = true;
9f7065da
TL		 947}
948
8ba55c5c
DB		 949/* This lock class tells lockdep that GPIO irqs are in a different
950 * category than their parents, so it won't report false recursion.
951 */
952static struct lock_class_key gpio_lock_class;
953
03e128ca 954static void omap_gpio_mod_init(struct gpio_bank *bank)
2fae7fbe 955{
ab985f0f
TKD		 956 void __iomem *base = bank->base;
957 u32 l = 0xffffffff;
2fae7fbe 958
ab985f0f
TKD		 959 if (bank->width == 16)
960 l = 0xffff;
961
d0d665a8 962 if (bank->is_mpuio) {
ab985f0f
TKD		 963 __raw_writel(l, bank->base + bank->regs->irqenable);
964 return;
2fae7fbe 965 }
ab985f0f
TKD		 966
967 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
968 _gpio_rmw(base, bank->regs->irqstatus, l,
969 bank->regs->irqenable_inv == false);
970 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->debounce_en != 0);
971 _gpio_rmw(base, bank->regs->irqenable, l, bank->regs->ctrl != 0);
972 if (bank->regs->debounce_en)
973 _gpio_rmw(base, bank->regs->debounce_en, 0, 1);
974
2dc983c5
TKD		 975 /* Save OE default value (0xffffffff) in the context */
976 bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
ab985f0f
TKD		 977 /* Initialize interface clk ungated, module enabled */
978 if (bank->regs->ctrl)
979 _gpio_rmw(base, bank->regs->ctrl, 0, 1);
2fae7fbe
VC		 980}
981
8805f410 982static __devinit void
f8b46b58
KH		 983omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
984 unsigned int num)
985{
986 struct irq_chip_generic *gc;
987 struct irq_chip_type *ct;
988
989 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
990 handle_simple_irq);
83233749
TP		 991 if (!gc) {
992 dev_err(bank->dev, "Memory alloc failed for gc\n");
993 return;
994 }
995
f8b46b58
KH		 996 ct = gc->chip_types;
997
998 /* NOTE: No ack required, reading IRQ status clears it. */
999 ct->chip.irq_mask = irq_gc_mask_set_bit;
1000 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
1001 ct->chip.irq_set_type = gpio_irq_type;
6ed87c5b
TKD		 1002
1003 if (bank->regs->wkup_en)
f8b46b58
KH		 1004 ct->chip.irq_set_wake = gpio_wake_enable,
1005
1006 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1007 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1008 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1009}
1010
d52b31de 1011static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
2fae7fbe 1012{
77640aab 1013 int j;
2fae7fbe
VC		 1014 static int gpio;
1015
2fae7fbe
VC		 1016 /*
1017 * REVISIT eventually switch from OMAP-specific gpio structs
1018 * over to the generic ones
1019 */
1020 bank->chip.request = omap_gpio_request;
1021 bank->chip.free = omap_gpio_free;
1022 bank->chip.direction_input = gpio_input;
1023 bank->chip.get = gpio_get;
1024 bank->chip.direction_output = gpio_output;
1025 bank->chip.set_debounce = gpio_debounce;
1026 bank->chip.set = gpio_set;
1027 bank->chip.to_irq = gpio_2irq;
d0d665a8 1028 if (bank->is_mpuio) {
2fae7fbe 1029 bank->chip.label = "mpuio";
6ed87c5b
TKD		 1030 if (bank->regs->wkup_en)
1031 bank->chip.dev = &omap_mpuio_device.dev;
2fae7fbe
VC		 1032 bank->chip.base = OMAP_MPUIO(0);
1033 } else {
1034 bank->chip.label = "gpio";
1035 bank->chip.base = gpio;
d5f46247 1036 gpio += bank->width;
2fae7fbe 1037 }
d5f46247 1038 bank->chip.ngpio = bank->width;
2fae7fbe
VC		 1039
1040 gpiochip_add(&bank->chip);
1041
384ebe1c 1042 for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1475b85d 1043 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1044 irq_set_chip_data(j, bank);
d0d665a8 1045 if (bank->is_mpuio) {
f8b46b58
KH		 1046 omap_mpuio_alloc_gc(bank, j, bank->width);
1047 } else {
6845664a 1048 irq_set_chip(j, &gpio_irq_chip);
f8b46b58
KH		 1049 irq_set_handler(j, handle_simple_irq);
1050 set_irq_flags(j, IRQF_VALID);
1051 }
2fae7fbe 1052 }
6845664a
TG		 1053 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1054 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1055}
1056
384ebe1c
BC		 1057static const struct of_device_id omap_gpio_match[];
1058
77640aab 1059static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1060{
862ff640 1061 struct device *dev = &pdev->dev;
384ebe1c
BC		 1062 struct device_node *node = dev->of_node;
1063 const struct of_device_id *match;
77640aab
VC		 1064 struct omap_gpio_platform_data *pdata;
1065 struct resource *res;
5e1c5ff4 1066 struct gpio_bank *bank;
03e128ca 1067 int ret = 0;
5e1c5ff4 1068
384ebe1c
BC		 1069 match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1070
1071 pdata = match ? match->data : dev->platform_data;
1072 if (!pdata)
96751fcb 1073 return -EINVAL;
5492fb1a 1074
96751fcb 1075 bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
03e128ca 1076 if (!bank) {
862ff640 1077 dev_err(dev, "Memory alloc failed\n");
96751fcb 1078 return -ENOMEM;
03e128ca 1079 }
92105bb7 1080
77640aab
VC		 1081 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1082 if (unlikely(!res)) {
862ff640 1083 dev_err(dev, "Invalid IRQ resource\n");
96751fcb 1084 return -ENODEV;
44169075 1085 }
5e1c5ff4 1086
77640aab 1087 bank->irq = res->start;
862ff640 1088 bank->dev = dev;
77640aab 1089 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1090 bank->stride = pdata->bank_stride;
d5f46247 1091 bank->width = pdata->bank_width;
d0d665a8 1092 bank->is_mpuio = pdata->is_mpuio;
803a2434 1093 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
0cde8d03 1094 bank->loses_context = pdata->loses_context;
60a3437d 1095 bank->get_context_loss_count = pdata->get_context_loss_count;
fa87931a 1096 bank->regs = pdata->regs;
384ebe1c
BC		 1097#ifdef CONFIG_OF_GPIO
1098 bank->chip.of_node = of_node_get(node);
1099#endif
1100
1101 bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1102 if (bank->irq_base < 0) {
1103 dev_err(dev, "Couldn't allocate IRQ numbers\n");
1104 return -ENODEV;
1105 }
1106
1107 bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1108 0, &irq_domain_simple_ops, NULL);
fa87931a
KH		 1109
1110 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1111 bank->set_dataout = _set_gpio_dataout_reg;
1112 else
1113 bank->set_dataout = _set_gpio_dataout_mask;
9f7065da 1114
77640aab 1115 spin_lock_init(&bank->lock);
9f7065da 1116
77640aab
VC		 1117 /* Static mapping, never released */
1118 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1119 if (unlikely(!res)) {
862ff640 1120 dev_err(dev, "Invalid mem resource\n");
96751fcb
BC		 1121 return -ENODEV;
1122 }
1123
1124 if (!devm_request_mem_region(dev, res->start, resource_size(res),
1125 pdev->name)) {
1126 dev_err(dev, "Region already claimed\n");
1127 return -EBUSY;
77640aab 1128 }
89db9482 1129
96751fcb 1130 bank->base = devm_ioremap(dev, res->start, resource_size(res));
77640aab 1131 if (!bank->base) {
862ff640 1132 dev_err(dev, "Could not ioremap\n");
96751fcb 1133 return -ENOMEM;
5e1c5ff4
TL		 1134 }
1135
065cd795
TKD		 1136 platform_set_drvdata(pdev, bank);
1137
77640aab 1138 pm_runtime_enable(bank->dev);
55b93c32 1139 pm_runtime_irq_safe(bank->dev);
77640aab
VC		 1140 pm_runtime_get_sync(bank->dev);
1141
d0d665a8 1142 if (bank->is_mpuio)
ab985f0f
TKD		 1143 mpuio_init(bank);
1144
03e128ca 1145 omap_gpio_mod_init(bank);
77640aab 1146 omap_gpio_chip_init(bank);
9a748053 1147 omap_gpio_show_rev(bank);
9f7065da 1148
55b93c32
TKD		 1149 pm_runtime_put(bank->dev);
1150
03e128ca 1151 list_add_tail(&bank->node, &omap_gpio_list);
77640aab 1152
03e128ca 1153 return ret;
5e1c5ff4
TL		 1154}
1155
55b93c32
TKD		 1156#ifdef CONFIG_ARCH_OMAP2PLUS
1157
1158#if defined(CONFIG_PM_SLEEP)
1159static int omap_gpio_suspend(struct device *dev)
92105bb7 1160{
065cd795
TKD		 1161 struct platform_device *pdev = to_platform_device(dev);
1162 struct gpio_bank *bank = platform_get_drvdata(pdev);
1163 void __iomem *base = bank->base;
1164 void __iomem *wakeup_enable;
1165 unsigned long flags;
92105bb7 1166
065cd795
TKD		 1167 if (!bank->mod_usage || !bank->loses_context)
1168 return 0;
92105bb7 1169
065cd795
TKD		 1170 if (!bank->regs->wkup_en || !bank->suspend_wakeup)
1171 return 0;
6ed87c5b 1172
065cd795 1173 wakeup_enable = bank->base + bank->regs->wkup_en;
92105bb7 1174
065cd795
TKD		 1175 spin_lock_irqsave(&bank->lock, flags);
1176 bank->saved_wakeup = __raw_readl(wakeup_enable);
1177 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1178 _gpio_rmw(base, bank->regs->wkup_en, bank->suspend_wakeup, 1);
1179 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1180
1181 return 0;
1182}
1183
55b93c32 1184static int omap_gpio_resume(struct device *dev)
92105bb7 1185{
065cd795
TKD		 1186 struct platform_device *pdev = to_platform_device(dev);
1187 struct gpio_bank *bank = platform_get_drvdata(pdev);
1188 void __iomem *base = bank->base;
1189 unsigned long flags;
92105bb7 1190
065cd795
TKD		 1191 if (!bank->mod_usage || !bank->loses_context)
1192 return 0;
92105bb7 1193
065cd795
TKD		 1194 if (!bank->regs->wkup_en || !bank->saved_wakeup)
1195 return 0;
92105bb7 1196
065cd795
TKD		 1197 spin_lock_irqsave(&bank->lock, flags);
1198 _gpio_rmw(base, bank->regs->wkup_en, 0xffffffff, 0);
1199 _gpio_rmw(base, bank->regs->wkup_en, bank->saved_wakeup, 1);
1200 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1201
55b93c32
TKD		 1202 return 0;
1203}
1204#endif /* CONFIG_PM_SLEEP */
3ac4fa99 1205
2dc983c5 1206#if defined(CONFIG_PM_RUNTIME)
60a3437d 1207static void omap_gpio_restore_context(struct gpio_bank *bank);
3ac4fa99 1208
2dc983c5 1209static int omap_gpio_runtime_suspend(struct device *dev)
3ac4fa99 1210{
2dc983c5
TKD		 1211 struct platform_device *pdev = to_platform_device(dev);
1212 struct gpio_bank *bank = platform_get_drvdata(pdev);
1213 u32 l1 = 0, l2 = 0;
1214 unsigned long flags;
68942edb 1215 u32 wake_low, wake_hi;
8865b9b6 1216
2dc983c5 1217 spin_lock_irqsave(&bank->lock, flags);
68942edb
KH		 1218
1219 /*
1220 * Only edges can generate a wakeup event to the PRCM.
1221 *
1222 * Therefore, ensure any wake-up capable GPIOs have
1223 * edge-detection enabled before going idle to ensure a wakeup
1224 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1225 * NDA TRM 25.5.3.1)
1226 *
1227 * The normal values will be restored upon ->runtime_resume()
1228 * by writing back the values saved in bank->context.
1229 */
1230 wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1231 if (wake_low)
1232 __raw_writel(wake_low | bank->context.fallingdetect,
1233 bank->base + bank->regs->fallingdetect);
1234 wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1235 if (wake_hi)
1236 __raw_writel(wake_hi | bank->context.risingdetect,
1237 bank->base + bank->regs->risingdetect);
1238
2dc983c5
TKD		 1239 if (bank->power_mode != OFF_MODE) {
1240 bank->power_mode = 0;
41d87cbd 1241 goto update_gpio_context_count;
2dc983c5
TKD		 1242 }
1243 /*
1244 * If going to OFF, remove triggering for all
1245 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1246 * generated. See OMAP2420 Errata item 1.101.
1247 */
2dc983c5
TKD		 1248 bank->saved_datain = __raw_readl(bank->base +
1249 bank->regs->datain);
1250 l1 = __raw_readl(bank->base + bank->regs->fallingdetect);
1251 l2 = __raw_readl(bank->base + bank->regs->risingdetect);
3f1686a9 1252
2dc983c5
TKD		 1253 bank->saved_fallingdetect = l1;
1254 bank->saved_risingdetect = l2;
1255 l1 &= ~bank->enabled_non_wakeup_gpios;
1256 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9 1257
2dc983c5
TKD		 1258 __raw_writel(l1, bank->base + bank->regs->fallingdetect);
1259 __raw_writel(l2, bank->base + bank->regs->risingdetect);
3f1686a9 1260
2dc983c5 1261 bank->workaround_enabled = true;
3f1686a9 1262
41d87cbd 1263update_gpio_context_count:
2dc983c5
TKD		 1264 if (bank->get_context_loss_count)
1265 bank->context_loss_count =
60a3437d
TKD		 1266 bank->get_context_loss_count(bank->dev);
1267
72f83af9 1268 _gpio_dbck_disable(bank);
2dc983c5 1269 spin_unlock_irqrestore(&bank->lock, flags);
55b93c32 1270
2dc983c5 1271 return 0;
3ac4fa99
JY		 1272}
1273
2dc983c5 1274static int omap_gpio_runtime_resume(struct device *dev)
3ac4fa99 1275{
2dc983c5
TKD		 1276 struct platform_device *pdev = to_platform_device(dev);
1277 struct gpio_bank *bank = platform_get_drvdata(pdev);
1278 int context_lost_cnt_after;
1279 u32 l = 0, gen, gen0, gen1;
1280 unsigned long flags;
8865b9b6 1281
2dc983c5 1282 spin_lock_irqsave(&bank->lock, flags);
72f83af9 1283 _gpio_dbck_enable(bank);
68942edb
KH		 1284
1285 /*
1286 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1287 * GPIOs were set to edge trigger also in order to be able to
1288 * generate a PRCM wakeup. Here we restore the
1289 * pre-runtime_suspend() values for edge triggering.
1290 */
1291 __raw_writel(bank->context.fallingdetect,
1292 bank->base + bank->regs->fallingdetect);
1293 __raw_writel(bank->context.risingdetect,
1294 bank->base + bank->regs->risingdetect);
1295
960edffe 1296 if (!bank->workaround_enabled) {
2dc983c5
TKD		 1297 spin_unlock_irqrestore(&bank->lock, flags);
1298 return 0;
1299 }
55b93c32 1300
2dc983c5
TKD		 1301 if (bank->get_context_loss_count) {
1302 context_lost_cnt_after =
1303 bank->get_context_loss_count(bank->dev);
1304 if (context_lost_cnt_after != bank->context_loss_count ||
1305 !context_lost_cnt_after) {
1306 omap_gpio_restore_context(bank);
1307 } else {
1308 spin_unlock_irqrestore(&bank->lock, flags);
1309 return 0;
60a3437d 1310 }
2dc983c5 1311 }
43ffcd9a 1312
2dc983c5
TKD		 1313 __raw_writel(bank->saved_fallingdetect,
1314 bank->base + bank->regs->fallingdetect);
1315 __raw_writel(bank->saved_risingdetect,
1316 bank->base + bank->regs->risingdetect);
1317 l = __raw_readl(bank->base + bank->regs->datain);
3f1686a9 1318
2dc983c5
TKD		 1319 /*
1320 * Check if any of the non-wakeup interrupt GPIOs have changed
1321 * state. If so, generate an IRQ by software. This is
1322 * horribly racy, but it's the best we can do to work around
1323 * this silicon bug.
1324 */
1325 l ^= bank->saved_datain;
1326 l &= bank->enabled_non_wakeup_gpios;
3f1686a9 1327
2dc983c5
TKD		 1328 /*
1329 * No need to generate IRQs for the rising edge for gpio IRQs
1330 * configured with falling edge only; and vice versa.
1331 */
1332 gen0 = l & bank->saved_fallingdetect;
1333 gen0 &= bank->saved_datain;
82dbb9d3 1334
2dc983c5
TKD		 1335 gen1 = l & bank->saved_risingdetect;
1336 gen1 &= ~(bank->saved_datain);
82dbb9d3 1337
2dc983c5
TKD		 1338 /* FIXME: Consider GPIO IRQs with level detections properly! */
1339 gen = l & (~(bank->saved_fallingdetect) & ~(bank->saved_risingdetect));
1340 /* Consider all GPIO IRQs needed to be updated */
1341 gen |= gen0 | gen1;
82dbb9d3 1342
2dc983c5
TKD		 1343 if (gen) {
1344 u32 old0, old1;
82dbb9d3 1345
2dc983c5
TKD		 1346 old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1347 old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
3f1686a9 1348
2dc983c5
TKD		 1349 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1350 __raw_writel(old0 | gen, bank->base +
9ea14d8c 1351 bank->regs->leveldetect0);
2dc983c5 1352 __raw_writel(old1 | gen, bank->base +
9ea14d8c 1353 bank->regs->leveldetect1);
2dc983c5 1354 }
9ea14d8c 1355
2dc983c5
TKD		 1356 if (cpu_is_omap44xx()) {
1357 __raw_writel(old0 | l, bank->base +
9ea14d8c 1358 bank->regs->leveldetect0);
2dc983c5 1359 __raw_writel(old1 | l, bank->base +
9ea14d8c 1360 bank->regs->leveldetect1);
3ac4fa99 1361 }
2dc983c5
TKD		 1362 __raw_writel(old0, bank->base + bank->regs->leveldetect0);
1363 __raw_writel(old1, bank->base + bank->regs->leveldetect1);
1364 }
1365
1366 bank->workaround_enabled = false;
1367 spin_unlock_irqrestore(&bank->lock, flags);
1368
1369 return 0;
1370}
1371#endif /* CONFIG_PM_RUNTIME */
1372
1373void omap2_gpio_prepare_for_idle(int pwr_mode)
1374{
1375 struct gpio_bank *bank;
1376
1377 list_for_each_entry(bank, &omap_gpio_list, node) {
2dc983c5
TKD		 1378 if (!bank->mod_usage || !bank->loses_context)
1379 continue;
1380
1381 bank->power_mode = pwr_mode;
1382
2dc983c5
TKD		 1383 pm_runtime_put_sync_suspend(bank->dev);
1384 }
1385}
1386
1387void omap2_gpio_resume_after_idle(void)
1388{
1389 struct gpio_bank *bank;
1390
1391 list_for_each_entry(bank, &omap_gpio_list, node) {
2dc983c5
TKD		 1392 if (!bank->mod_usage || !bank->loses_context)
1393 continue;
1394
2dc983c5 1395 pm_runtime_get_sync(bank->dev);
3ac4fa99 1396 }
3ac4fa99
JY		 1397}
1398
2dc983c5 1399#if defined(CONFIG_PM_RUNTIME)
60a3437d 1400static void omap_gpio_restore_context(struct gpio_bank *bank)
40c670f0 1401{
60a3437d 1402 __raw_writel(bank->context.wake_en,
ae10f233
TKD		 1403 bank->base + bank->regs->wkup_en);
1404 __raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
60a3437d 1405 __raw_writel(bank->context.leveldetect0,
ae10f233 1406 bank->base + bank->regs->leveldetect0);
60a3437d 1407 __raw_writel(bank->context.leveldetect1,
ae10f233 1408 bank->base + bank->regs->leveldetect1);
60a3437d 1409 __raw_writel(bank->context.risingdetect,
ae10f233 1410 bank->base + bank->regs->risingdetect);
60a3437d 1411 __raw_writel(bank->context.fallingdetect,
ae10f233 1412 bank->base + bank->regs->fallingdetect);
f86bcc30
NM		 1413 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1414 __raw_writel(bank->context.dataout,
1415 bank->base + bank->regs->set_dataout);
1416 else
1417 __raw_writel(bank->context.dataout,
1418 bank->base + bank->regs->dataout);
6d13eaaf
NM		 1419 __raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1420
ae547354
NM		 1421 if (bank->dbck_enable_mask) {
1422 __raw_writel(bank->context.debounce, bank->base +
1423 bank->regs->debounce);
1424 __raw_writel(bank->context.debounce_en,
1425 bank->base + bank->regs->debounce_en);
1426 }
ba805be5
NM		 1427
1428 __raw_writel(bank->context.irqenable1,
1429 bank->base + bank->regs->irqenable);
1430 __raw_writel(bank->context.irqenable2,
1431 bank->base + bank->regs->irqenable2);
40c670f0 1432}
2dc983c5 1433#endif /* CONFIG_PM_RUNTIME */
55b93c32
TKD		 1434#else
1435#define omap_gpio_suspend NULL
1436#define omap_gpio_resume NULL
2dc983c5
TKD		 1437#define omap_gpio_runtime_suspend NULL
1438#define omap_gpio_runtime_resume NULL
40c670f0
RN		 1439#endif
1440
55b93c32
TKD		 1441static const struct dev_pm_ops gpio_pm_ops = {
1442 SET_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
2dc983c5
TKD		 1443 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1444 NULL)
55b93c32
TKD		 1445};
1446
384ebe1c
BC		 1447#if defined(CONFIG_OF)
1448static struct omap_gpio_reg_offs omap2_gpio_regs = {
1449 .revision = OMAP24XX_GPIO_REVISION,
1450 .direction = OMAP24XX_GPIO_OE,
1451 .datain = OMAP24XX_GPIO_DATAIN,
1452 .dataout = OMAP24XX_GPIO_DATAOUT,
1453 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1454 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1455 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1456 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1457 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1458 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1459 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1460 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1461 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1462 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1463 .ctrl = OMAP24XX_GPIO_CTRL,
1464 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1465 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1466 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1467 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1468 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1469};
1470
1471static struct omap_gpio_reg_offs omap4_gpio_regs = {
1472 .revision = OMAP4_GPIO_REVISION,
1473 .direction = OMAP4_GPIO_OE,
1474 .datain = OMAP4_GPIO_DATAIN,
1475 .dataout = OMAP4_GPIO_DATAOUT,
1476 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1477 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1478 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1479 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1480 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1481 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1482 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1483 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1484 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1485 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1486 .ctrl = OMAP4_GPIO_CTRL,
1487 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1488 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1489 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1490 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1491 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1492};
1493
1494static struct omap_gpio_platform_data omap2_pdata = {
1495 .regs = &omap2_gpio_regs,
1496 .bank_width = 32,
1497 .dbck_flag = false,
1498};
1499
1500static struct omap_gpio_platform_data omap3_pdata = {
1501 .regs = &omap2_gpio_regs,
1502 .bank_width = 32,
1503 .dbck_flag = true,
1504};
1505
1506static struct omap_gpio_platform_data omap4_pdata = {
1507 .regs = &omap4_gpio_regs,
1508 .bank_width = 32,
1509 .dbck_flag = true,
1510};
1511
1512static const struct of_device_id omap_gpio_match[] = {
1513 {
1514 .compatible = "ti,omap4-gpio",
1515 .data = &omap4_pdata,
1516 },
1517 {
1518 .compatible = "ti,omap3-gpio",
1519 .data = &omap3_pdata,
1520 },
1521 {
1522 .compatible = "ti,omap2-gpio",
1523 .data = &omap2_pdata,
1524 },
1525 { },
1526};
1527MODULE_DEVICE_TABLE(of, omap_gpio_match);
1528#endif
1529
77640aab
VC		 1530static struct platform_driver omap_gpio_driver = {
1531 .probe = omap_gpio_probe,
1532 .driver = {
1533 .name = "omap_gpio",
55b93c32 1534 .pm = &gpio_pm_ops,
384ebe1c 1535 .of_match_table = of_match_ptr(omap_gpio_match),
77640aab
VC		 1536 },
1537};
1538
5e1c5ff4 1539/*
77640aab
VC		 1540 * gpio driver register needs to be done before
1541 * machine_init functions access gpio APIs.
1542 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 1543 */
77640aab 1544static int __init omap_gpio_drv_reg(void)
5e1c5ff4 1545{
77640aab 1546 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 1547}
77640aab 1548postcore_initcall(omap_gpio_drv_reg);
kernel source for telekom puls (alcatel/mediatek)