[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-langwell.c

/*
 * Moorestown platform Langwell chip GPIO driver
 *
 * Copyright (c) 2008 - 2009,  Intel Corporation.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

/* Supports:
 * Moorestown platform Langwell chip.
 * Medfield platform Penwell chip.
 * Whitney point.
 */

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/stddef.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/slab.h>
#include <linux/pm_runtime.h>

/*
 * Langwell chip has 64 pins and thus there are 2 32bit registers to control
 * each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
 * registers to control them, so we only define the order here instead of a
 * structure, to get a bit offset for a pin (use GPDR as an example):
 *
 * nreg = ngpio / 32;
 * reg = offset / 32;
 * bit = offset % 32;
 * reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
 *
 * so the bit of reg_addr is to control pin offset's GPDR feature
*/

enum GPIO_REG {
	GPLR = 0,	/* pin level read-only */
	GPDR,		/* pin direction */
	GPSR,		/* pin set */
	GPCR,		/* pin clear */
	GRER,		/* rising edge detect */
	GFER,		/* falling edge detect */
	GEDR,		/* edge detect result */
	GAFR,		/* alt function */
};

struct lnw_gpio {
	struct gpio_chip		chip;
	void				*reg_base;
	spinlock_t			lock;
	unsigned			irq_base;
	struct pci_dev			*pdev;
};

static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned offset,
			enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 32;
	void __iomem *ptr;

	ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
	return ptr;
}

static void __iomem *gpio_reg_2bit(struct gpio_chip *chip, unsigned offset,
				   enum GPIO_REG reg_type)
{
	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
	unsigned nreg = chip->ngpio / 32;
	u8 reg = offset / 16;
	void __iomem *ptr;

	ptr = (void __iomem *)(lnw->reg_base + reg_type * nreg * 4 + reg * 4);
	return ptr;
}

static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	u32 value = readl(gafr);
	int shift = (offset % 16) << 1, af = (value >> shift) & 3;

	if (af) {
		value &= ~(3 << shift);
		writel(value, gafr);
	}
	return 0;
}

static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
{
	void __iomem *gplr = gpio_reg(chip, offset, GPLR);

	return readl(gplr) & BIT(offset % 32);
}

static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
{
	void __iomem *gpsr, *gpcr;

	if (value) {
		gpsr = gpio_reg(chip, offset, GPSR);
		writel(BIT(offset % 32), gpsr);
	} else {
		gpcr = gpio_reg(chip, offset, GPCR);
		writel(BIT(offset % 32), gpcr);
	}
}

static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	u32 value;
	unsigned long flags;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value &= ~BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_direction_output(struct gpio_chip *chip,
			unsigned offset, int value)
{
	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
	unsigned long flags;

	lnw_gpio_set(chip, offset, value);

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	value = readl(gpdr);
	value |= BIT(offset % 32);
	writel(value, gpdr);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
{
	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
	return lnw->irq_base + offset;
}

static int lnw_irq_type(struct irq_data *d, unsigned type)
{
	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
	u32 gpio = d->irq - lnw->irq_base;
	unsigned long flags;
	u32 value;
	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);

	if (gpio >= lnw->chip.ngpio)
		return -EINVAL;

	if (lnw->pdev)
		pm_runtime_get(&lnw->pdev->dev);

	spin_lock_irqsave(&lnw->lock, flags);
	if (type & IRQ_TYPE_EDGE_RISING)
		value = readl(grer) | BIT(gpio % 32);
	else
		value = readl(grer) & (~BIT(gpio % 32));
	writel(value, grer);

	if (type & IRQ_TYPE_EDGE_FALLING)
		value = readl(gfer) | BIT(gpio % 32);
	else
		value = readl(gfer) & (~BIT(gpio % 32));
	writel(value, gfer);
	spin_unlock_irqrestore(&lnw->lock, flags);

	if (lnw->pdev)
		pm_runtime_put(&lnw->pdev->dev);

	return 0;
}

static void lnw_irq_unmask(struct irq_data *d)
{
}

static void lnw_irq_mask(struct irq_data *d)
{
}

static struct irq_chip lnw_irqchip = {
	.name		= "LNW-GPIO",
	.irq_mask	= lnw_irq_mask,
	.irq_unmask	= lnw_irq_unmask,
	.irq_set_type	= lnw_irq_type,
};

static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = {   /* pin number */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
	{ 0, }
};
MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);

static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
{
	struct irq_data *data = irq_desc_get_irq_data(desc);
	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	struct irq_chip *chip = irq_data_get_irq_chip(data);
	u32 base, gpio, mask;
	unsigned long pending;
	void __iomem *gedr;

	/* check GPIO controller to check which pin triggered the interrupt */
	for (base = 0; base < lnw->chip.ngpio; base += 32) {
		gedr = gpio_reg(&lnw->chip, base, GEDR);
		pending = readl(gedr);
		while (pending) {
			gpio = __ffs(pending);
			mask = BIT(gpio);
			pending &= ~mask;
			/* Clear before handling so we can't lose an edge */
			writel(mask, gedr);
			generic_handle_irq(lnw->irq_base + base + gpio);
		}
	}

	chip->irq_eoi(data);
}

#ifdef CONFIG_PM
static int lnw_gpio_runtime_resume(struct device *dev)
{
	return 0;
}

static int lnw_gpio_runtime_suspend(struct device *dev)
{
	return 0;
}

static int lnw_gpio_runtime_idle(struct device *dev)
{
	int err = pm_schedule_suspend(dev, 500);

	if (!err)
		return 0;

	return -EBUSY;
}

#else
#define lnw_gpio_runtime_suspend	NULL
#define lnw_gpio_runtime_resume		NULL
#define lnw_gpio_runtime_idle		NULL
#endif

static const struct dev_pm_ops lnw_gpio_pm_ops = {
	.runtime_suspend = lnw_gpio_runtime_suspend,
	.runtime_resume = lnw_gpio_runtime_resume,
	.runtime_idle = lnw_gpio_runtime_idle,
};

static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
			const struct pci_device_id *id)
{
	void *base;
	int i;
	resource_size_t start, len;
	struct lnw_gpio *lnw;
	u32 irq_base;
	u32 gpio_base;
	int retval = 0;

	retval = pci_enable_device(pdev);
	if (retval)
		goto done;

	retval = pci_request_regions(pdev, "langwell_gpio");
	if (retval) {
		dev_err(&pdev->dev, "error requesting resources\n");
		goto err2;
	}
	/* get the irq_base from bar1 */
	start = pci_resource_start(pdev, 1);
	len = pci_resource_len(pdev, 1);
	base = ioremap_nocache(start, len);
	if (!base) {
		dev_err(&pdev->dev, "error mapping bar1\n");
		goto err3;
	}
	irq_base = *(u32 *)base;
	gpio_base = *((u32 *)base + 1);
	/* release the IO mapping, since we already get the info from bar1 */
	iounmap(base);
	/* get the register base from bar0 */
	start = pci_resource_start(pdev, 0);
	len = pci_resource_len(pdev, 0);
	base = ioremap_nocache(start, len);
	if (!base) {
		dev_err(&pdev->dev, "error mapping bar0\n");
		retval = -EFAULT;
		goto err3;
	}

	lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
	if (!lnw) {
		dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
		retval = -ENOMEM;
		goto err4;
	}
	lnw->reg_base = base;
	lnw->irq_base = irq_base;
	lnw->chip.label = dev_name(&pdev->dev);
	lnw->chip.request = lnw_gpio_request;
	lnw->chip.direction_input = lnw_gpio_direction_input;
	lnw->chip.direction_output = lnw_gpio_direction_output;
	lnw->chip.get = lnw_gpio_get;
	lnw->chip.set = lnw_gpio_set;
	lnw->chip.to_irq = lnw_gpio_to_irq;
	lnw->chip.base = gpio_base;
	lnw->chip.ngpio = id->driver_data;
	lnw->chip.can_sleep = 0;
	lnw->pdev = pdev;
	pci_set_drvdata(pdev, lnw);
	retval = gpiochip_add(&lnw->chip);
	if (retval) {
		dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
		goto err5;
	}
	irq_set_handler_data(pdev->irq, lnw);
	irq_set_chained_handler(pdev->irq, lnw_irq_handler);
	for (i = 0; i < lnw->chip.ngpio; i++) {
		irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
					      handle_simple_irq, "demux");
		irq_set_chip_data(i + lnw->irq_base, lnw);
	}

	spin_lock_init(&lnw->lock);

	pm_runtime_put_noidle(&pdev->dev);
	pm_runtime_allow(&pdev->dev);

	goto done;
err5:
	kfree(lnw);
err4:
	iounmap(base);
err3:
	pci_release_regions(pdev);
err2:
	pci_disable_device(pdev);
done:
	return retval;
}

static struct pci_driver lnw_gpio_driver = {
	.name		= "langwell_gpio",
	.id_table	= lnw_gpio_ids,
	.probe		= lnw_gpio_probe,
	.driver		= {
		.pm	= &lnw_gpio_pm_ops,
	},
};


static int __devinit wp_gpio_probe(struct platform_device *pdev)
{
	struct lnw_gpio *lnw;
	struct gpio_chip *gc;
	struct resource *rc;
	int retval = 0;

	rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!rc)
		return -EINVAL;

	lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
	if (!lnw) {
		dev_err(&pdev->dev,
			"can't allocate whitneypoint_gpio chip data\n");
		return -ENOMEM;
	}
	lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
	if (lnw->reg_base == NULL) {
		retval = -EINVAL;
		goto err_kmalloc;
	}
	spin_lock_init(&lnw->lock);
	gc = &lnw->chip;
	gc->label = dev_name(&pdev->dev);
	gc->owner = THIS_MODULE;
	gc->direction_input = lnw_gpio_direction_input;
	gc->direction_output = lnw_gpio_direction_output;
	gc->get = lnw_gpio_get;
	gc->set = lnw_gpio_set;
	gc->to_irq = NULL;
	gc->base = 0;
	gc->ngpio = 64;
	gc->can_sleep = 0;
	retval = gpiochip_add(gc);
	if (retval) {
		dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
								retval);
		goto err_ioremap;
	}
	platform_set_drvdata(pdev, lnw);
	return 0;
err_ioremap:
	iounmap(lnw->reg_base);
err_kmalloc:
	kfree(lnw);
	return retval;
}

static int __devexit wp_gpio_remove(struct platform_device *pdev)
{
	struct lnw_gpio *lnw = platform_get_drvdata(pdev);
	int err;
	err = gpiochip_remove(&lnw->chip);
	if (err)
		dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
	iounmap(lnw->reg_base);
	kfree(lnw);
	platform_set_drvdata(pdev, NULL);
	return 0;
}

static struct platform_driver wp_gpio_driver = {
	.probe		= wp_gpio_probe,
	.remove		= __devexit_p(wp_gpio_remove),
	.driver		= {
		.name	= "wp_gpio",
		.owner	= THIS_MODULE,
	},
};

static int __init lnw_gpio_init(void)
{
	int ret;
	ret =  pci_register_driver(&lnw_gpio_driver);
	if (ret < 0)
		return ret;
	ret = platform_driver_register(&wp_gpio_driver);
	if (ret < 0)
		pci_unregister_driver(&lnw_gpio_driver);
	return ret;
}

device_initcall(lnw_gpio_init);
Commit	Line	Data
c103de24 GL	1	/*
	2	* Moorestown platform Langwell chip GPIO driver
	3	*
8bf02617 AD	4	* Copyright (c) 2008 - 2009, Intel Corporation.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope that it will be useful,
	11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	* GNU General Public License for more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program; if not, write to the Free Software
	17	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	18	*/
	19
	20	/* Supports:
	21	* Moorestown platform Langwell chip.
8081c84c	22	* Medfield platform Penwell chip.
72b4379e	23	* Whitney point.
8bf02617 AD	24	*/
	25
	26	#include <linux/module.h>
	27	#include <linux/pci.h>
72b4379e	28	#include <linux/platform_device.h>
8bf02617 AD	29	#include <linux/kernel.h>
	30	#include <linux/delay.h>
	31	#include <linux/stddef.h>
	32	#include <linux/interrupt.h>
	33	#include <linux/init.h>
	34	#include <linux/irq.h>
	35	#include <linux/io.h>
	36	#include <linux/gpio.h>
5a0e3ad6	37	#include <linux/slab.h>
7812803a	38	#include <linux/pm_runtime.h>
8bf02617	39
8081c84c AD	40	/*
	41	* Langwell chip has 64 pins and thus there are 2 32bit registers to control
	42	* each feature, while Penwell chip has 96 pins for each block, and need 3 32bit
	43	* registers to control them, so we only define the order here instead of a
	44	* structure, to get a bit offset for a pin (use GPDR as an example):
	45	*
	46	* nreg = ngpio / 32;
	47	* reg = offset / 32;
	48	* bit = offset % 32;
	49	* reg_addr = reg_base + GPDR * nreg * 4 + reg * 4;
	50	*
	51	* so the bit of reg_addr is to control pin offset's GPDR feature
	52	*/
	53
	54	enum GPIO_REG {
	55	GPLR = 0, /* pin level read-only */
	56	GPDR, /* pin direction */
	57	GPSR, /* pin set */
	58	GPCR, /* pin clear */
	59	GRER, /* rising edge detect */
	60	GFER, /* falling edge detect */
	61	GEDR, /* edge detect result */
8c0f7b10	62	GAFR, /* alt function */
8bf02617 AD	63	};
	64
	65	struct lnw_gpio {
	66	struct gpio_chip chip;
8081c84c	67	void *reg_base;
8bf02617 AD	68	spinlock_t lock;
8bf02617 AD	69	unsigned irq_base;
7812803a	70	struct pci_dev *pdev;
8bf02617 AD	71	};
8bf02617 AD	72
8081c84c AD	73	static void __iomem gpio_reg(struct gpio_chip chip, unsigned offset,
8081c84c AD	74	enum GPIO_REG reg_type)
8bf02617 AD	75	{
8bf02617 AD	76	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
8081c84c	77	unsigned nreg = chip->ngpio / 32;
8bf02617	78	u8 reg = offset / 32;
8081c84c AD	79	void __iomem *ptr;
	80
	81	ptr = (void __iomem )(lnw->reg_base + reg_type nreg * 4 + reg * 4);
	82	return ptr;
	83	}
	84
8c0f7b10 AH	85	static void __iomem gpio_reg_2bit(struct gpio_chip chip, unsigned offset,
	86	enum GPIO_REG reg_type)
	87	{
	88	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
	89	unsigned nreg = chip->ngpio / 32;
	90	u8 reg = offset / 16;
	91	void __iomem *ptr;
	92
	93	ptr = (void __iomem )(lnw->reg_base + reg_type nreg * 4 + reg * 4);
	94	return ptr;
	95	}
	96
	97	static int lnw_gpio_request(struct gpio_chip *chip, unsigned offset)
	98	{
	99	void __iomem *gafr = gpio_reg_2bit(chip, offset, GAFR);
	100	u32 value = readl(gafr);
	101	int shift = (offset % 16) << 1, af = (value >> shift) & 3;
	102
	103	if (af) {
	104	value &= ~(3 << shift);
	105	writel(value, gafr);
	106	}
	107	return 0;
	108	}
	109
8081c84c AD	110	static int lnw_gpio_get(struct gpio_chip *chip, unsigned offset)
	111	{
	112	void __iomem *gplr = gpio_reg(chip, offset, GPLR);
8bf02617	113
8bf02617 AD	114	return readl(gplr) & BIT(offset % 32);
	115	}
	116
	117	static void lnw_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	118	{
8bf02617 AD	119	void __iomem gpsr, gpcr;
	120
	121	if (value) {
8081c84c	122	gpsr = gpio_reg(chip, offset, GPSR);
8bf02617 AD	123	writel(BIT(offset % 32), gpsr);
8bf02617 AD	124	} else {
8081c84c	125	gpcr = gpio_reg(chip, offset, GPCR);
8bf02617 AD	126	writel(BIT(offset % 32), gpcr);
	127	}
	128	}
	129
	130	static int lnw_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	131	{
	132	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
8081c84c	133	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617 AD	134	u32 value;
8bf02617 AD	135	unsigned long flags;
8bf02617	136
7812803a KCA	137	if (lnw->pdev)
	138	pm_runtime_get(&lnw->pdev->dev);
	139
8bf02617 AD	140	spin_lock_irqsave(&lnw->lock, flags);
	141	value = readl(gpdr);
	142	value &= ~BIT(offset % 32);
	143	writel(value, gpdr);
	144	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	145
	146	if (lnw->pdev)
	147	pm_runtime_put(&lnw->pdev->dev);
	148
8bf02617 AD	149	return 0;
	150	}
	151
	152	static int lnw_gpio_direction_output(struct gpio_chip *chip,
	153	unsigned offset, int value)
	154	{
	155	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
8081c84c	156	void __iomem *gpdr = gpio_reg(chip, offset, GPDR);
8bf02617	157	unsigned long flags;
8bf02617 AD	158
8bf02617 AD	159	lnw_gpio_set(chip, offset, value);
7812803a KCA	160
	161	if (lnw->pdev)
	162	pm_runtime_get(&lnw->pdev->dev);
	163
8bf02617 AD	164	spin_lock_irqsave(&lnw->lock, flags);
8bf02617 AD	165	value = readl(gpdr);
6eab04a8	166	value \|= BIT(offset % 32);
8bf02617 AD	167	writel(value, gpdr);
8bf02617 AD	168	spin_unlock_irqrestore(&lnw->lock, flags);
7812803a KCA	169
	170	if (lnw->pdev)
	171	pm_runtime_put(&lnw->pdev->dev);
	172
8bf02617 AD	173	return 0;
	174	}
	175
	176	static int lnw_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
	177	{
	178	struct lnw_gpio *lnw = container_of(chip, struct lnw_gpio, chip);
	179	return lnw->irq_base + offset;
	180	}
	181
5ffd72c6	182	static int lnw_irq_type(struct irq_data *d, unsigned type)
8bf02617	183	{
5ffd72c6 LB	184	struct lnw_gpio *lnw = irq_data_get_irq_chip_data(d);
5ffd72c6 LB	185	u32 gpio = d->irq - lnw->irq_base;
8bf02617 AD	186	unsigned long flags;
8bf02617 AD	187	u32 value;
8081c84c AD	188	void __iomem *grer = gpio_reg(&lnw->chip, gpio, GRER);
8081c84c AD	189	void __iomem *gfer = gpio_reg(&lnw->chip, gpio, GFER);
8bf02617	190
4efec627	191	if (gpio >= lnw->chip.ngpio)
8bf02617	192	return -EINVAL;
7812803a KCA	193
	194	if (lnw->pdev)
	195	pm_runtime_get(&lnw->pdev->dev);
	196
8bf02617 AD	197	spin_lock_irqsave(&lnw->lock, flags);
	198	if (type & IRQ_TYPE_EDGE_RISING)
	199	value = readl(grer) \| BIT(gpio % 32);
	200	else
	201	value = readl(grer) & (~BIT(gpio % 32));
	202	writel(value, grer);
	203
	204	if (type & IRQ_TYPE_EDGE_FALLING)
	205	value = readl(gfer) \| BIT(gpio % 32);
	206	else
	207	value = readl(gfer) & (~BIT(gpio % 32));
	208	writel(value, gfer);
	209	spin_unlock_irqrestore(&lnw->lock, flags);
	210
7812803a KCA	211	if (lnw->pdev)
	212	pm_runtime_put(&lnw->pdev->dev);
	213
8bf02617	214	return 0;
fd0574cb	215	}
8bf02617	216
5ffd72c6	217	static void lnw_irq_unmask(struct irq_data *d)
8bf02617	218	{
fd0574cb	219	}
8bf02617	220
5ffd72c6	221	static void lnw_irq_mask(struct irq_data *d)
8bf02617	222	{
fd0574cb	223	}
8bf02617 AD	224
	225	static struct irq_chip lnw_irqchip = {
	226	.name = "LNW-GPIO",
5ffd72c6 LB	227	.irq_mask = lnw_irq_mask,
	228	.irq_unmask = lnw_irq_unmask,
	229	.irq_set_type = lnw_irq_type,
8bf02617 AD	230	};
8bf02617 AD	231
8081c84c AD	232	static DEFINE_PCI_DEVICE_TABLE(lnw_gpio_ids) = { /* pin number */
	233	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x080f), .driver_data = 64 },
	234	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081f), .driver_data = 96 },
	235	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x081a), .driver_data = 96 },
8bf02617 AD	236	{ 0, }
	237	};
	238	MODULE_DEVICE_TABLE(pci, lnw_gpio_ids);
	239
	240	static void lnw_irq_handler(unsigned irq, struct irq_desc *desc)
	241	{
20e2aa91 TG	242	struct irq_data *data = irq_desc_get_irq_data(desc);
	243	struct lnw_gpio *lnw = irq_data_get_irq_handler_data(data);
	244	struct irq_chip *chip = irq_data_get_irq_chip(data);
84bead6c	245	u32 base, gpio, mask;
732063b9	246	unsigned long pending;
8bf02617	247	void __iomem *gedr;
8bf02617 AD	248
8bf02617 AD	249	/* check GPIO controller to check which pin triggered the interrupt */
8081c84c AD	250	for (base = 0; base < lnw->chip.ngpio; base += 32) {
8081c84c AD	251	gedr = gpio_reg(&lnw->chip, base, GEDR);
84bead6c	252	pending = readl(gedr);
732063b9	253	while (pending) {
2345b20f	254	gpio = __ffs(pending);
84bead6c TG	255	mask = BIT(gpio);
	256	pending &= ~mask;
	257	/* Clear before handling so we can't lose an edge */
	258	writel(mask, gedr);
732063b9 TG	259	generic_handle_irq(lnw->irq_base + base + gpio);
732063b9 TG	260	}
8bf02617	261	}
0766d20f	262
20e2aa91	263	chip->irq_eoi(data);
8bf02617 AD	264	}
8bf02617 AD	265
7812803a KCA	266	#ifdef CONFIG_PM
	267	static int lnw_gpio_runtime_resume(struct device *dev)
	268	{
	269	return 0;
	270	}
	271
	272	static int lnw_gpio_runtime_suspend(struct device *dev)
	273	{
	274	return 0;
	275	}
	276
	277	static int lnw_gpio_runtime_idle(struct device *dev)
	278	{
	279	int err = pm_schedule_suspend(dev, 500);
	280
	281	if (!err)
	282	return 0;
	283
	284	return -EBUSY;
	285	}
	286
	287	#else
	288	#define lnw_gpio_runtime_suspend NULL
	289	#define lnw_gpio_runtime_resume NULL
	290	#define lnw_gpio_runtime_idle NULL
	291	#endif
	292
	293	static const struct dev_pm_ops lnw_gpio_pm_ops = {
	294	.runtime_suspend = lnw_gpio_runtime_suspend,
	295	.runtime_resume = lnw_gpio_runtime_resume,
	296	.runtime_idle = lnw_gpio_runtime_idle,
	297	};
	298
8bf02617 AD	299	static int __devinit lnw_gpio_probe(struct pci_dev *pdev,
	300	const struct pci_device_id *id)
	301	{
	302	void *base;
	303	int i;
	304	resource_size_t start, len;
	305	struct lnw_gpio *lnw;
	306	u32 irq_base;
	307	u32 gpio_base;
	308	int retval = 0;
	309
	310	retval = pci_enable_device(pdev);
	311	if (retval)
	312	goto done;
	313
	314	retval = pci_request_regions(pdev, "langwell_gpio");
	315	if (retval) {
	316	dev_err(&pdev->dev, "error requesting resources\n");
	317	goto err2;
	318	}
	319	/* get the irq_base from bar1 */
	320	start = pci_resource_start(pdev, 1);
	321	len = pci_resource_len(pdev, 1);
	322	base = ioremap_nocache(start, len);
	323	if (!base) {
	324	dev_err(&pdev->dev, "error mapping bar1\n");
	325	goto err3;
	326	}
	327	irq_base = (u32 )base;
	328	gpio_base = ((u32 )base + 1);
	329	/* release the IO mapping, since we already get the info from bar1 */
	330	iounmap(base);
	331	/* get the register base from bar0 */
	332	start = pci_resource_start(pdev, 0);
	333	len = pci_resource_len(pdev, 0);
	334	base = ioremap_nocache(start, len);
	335	if (!base) {
	336	dev_err(&pdev->dev, "error mapping bar0\n");
	337	retval = -EFAULT;
	338	goto err3;
	339	}
	340
	341	lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
	342	if (!lnw) {
	343	dev_err(&pdev->dev, "can't allocate langwell_gpio chip data\n");
	344	retval = -ENOMEM;
	345	goto err4;
	346	}
	347	lnw->reg_base = base;
	348	lnw->irq_base = irq_base;
	349	lnw->chip.label = dev_name(&pdev->dev);
8c0f7b10	350	lnw->chip.request = lnw_gpio_request;
8bf02617 AD	351	lnw->chip.direction_input = lnw_gpio_direction_input;
	352	lnw->chip.direction_output = lnw_gpio_direction_output;
	353	lnw->chip.get = lnw_gpio_get;
	354	lnw->chip.set = lnw_gpio_set;
	355	lnw->chip.to_irq = lnw_gpio_to_irq;
	356	lnw->chip.base = gpio_base;
8081c84c	357	lnw->chip.ngpio = id->driver_data;
8bf02617	358	lnw->chip.can_sleep = 0;
7812803a	359	lnw->pdev = pdev;
8bf02617 AD	360	pci_set_drvdata(pdev, lnw);
	361	retval = gpiochip_add(&lnw->chip);
	362	if (retval) {
	363	dev_err(&pdev->dev, "langwell gpiochip_add error %d\n", retval);
	364	goto err5;
	365	}
674db906 TG	366	irq_set_handler_data(pdev->irq, lnw);
674db906 TG	367	irq_set_chained_handler(pdev->irq, lnw_irq_handler);
8bf02617	368	for (i = 0; i < lnw->chip.ngpio; i++) {
674db906 TG	369	irq_set_chip_and_handler_name(i + lnw->irq_base, &lnw_irqchip,
	370	handle_simple_irq, "demux");
	371	irq_set_chip_data(i + lnw->irq_base, lnw);
8bf02617 AD	372	}
	373
	374	spin_lock_init(&lnw->lock);
7812803a KCA	375
	376	pm_runtime_put_noidle(&pdev->dev);
	377	pm_runtime_allow(&pdev->dev);
	378
8bf02617 AD	379	goto done;
	380	err5:
	381	kfree(lnw);
	382	err4:
	383	iounmap(base);
	384	err3:
	385	pci_release_regions(pdev);
	386	err2:
	387	pci_disable_device(pdev);
	388	done:
	389	return retval;
	390	}
	391
	392	static struct pci_driver lnw_gpio_driver = {
	393	.name = "langwell_gpio",
	394	.id_table = lnw_gpio_ids,
	395	.probe = lnw_gpio_probe,
7812803a KCA	396	.driver = {
	397	.pm = &lnw_gpio_pm_ops,
	398	},
8bf02617 AD	399	};
8bf02617 AD	400
72b4379e AC	401
	402	static int __devinit wp_gpio_probe(struct platform_device *pdev)
	403	{
	404	struct lnw_gpio *lnw;
	405	struct gpio_chip *gc;
	406	struct resource *rc;
	407	int retval = 0;
	408
	409	rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	410	if (!rc)
	411	return -EINVAL;
	412
	413	lnw = kzalloc(sizeof(struct lnw_gpio), GFP_KERNEL);
	414	if (!lnw) {
	415	dev_err(&pdev->dev,
	416	"can't allocate whitneypoint_gpio chip data\n");
	417	return -ENOMEM;
	418	}
	419	lnw->reg_base = ioremap_nocache(rc->start, resource_size(rc));
	420	if (lnw->reg_base == NULL) {
	421	retval = -EINVAL;
	422	goto err_kmalloc;
	423	}
	424	spin_lock_init(&lnw->lock);
	425	gc = &lnw->chip;
	426	gc->label = dev_name(&pdev->dev);
	427	gc->owner = THIS_MODULE;
	428	gc->direction_input = lnw_gpio_direction_input;
	429	gc->direction_output = lnw_gpio_direction_output;
	430	gc->get = lnw_gpio_get;
	431	gc->set = lnw_gpio_set;
	432	gc->to_irq = NULL;
	433	gc->base = 0;
	434	gc->ngpio = 64;
	435	gc->can_sleep = 0;
	436	retval = gpiochip_add(gc);
	437	if (retval) {
	438	dev_err(&pdev->dev, "whitneypoint gpiochip_add error %d\n",
	439	retval);
	440	goto err_ioremap;
	441	}
	442	platform_set_drvdata(pdev, lnw);
	443	return 0;
	444	err_ioremap:
	445	iounmap(lnw->reg_base);
	446	err_kmalloc:
	447	kfree(lnw);
	448	return retval;
	449	}
	450
	451	static int __devexit wp_gpio_remove(struct platform_device *pdev)
	452	{
	453	struct lnw_gpio *lnw = platform_get_drvdata(pdev);
	454	int err;
	455	err = gpiochip_remove(&lnw->chip);
	456	if (err)
	457	dev_err(&pdev->dev, "failed to remove gpio_chip.\n");
	458	iounmap(lnw->reg_base);
	459	kfree(lnw);
	460	platform_set_drvdata(pdev, NULL);
	461	return 0;
	462	}
	463
	464	static struct platform_driver wp_gpio_driver = {
465	.probe = wp_gpio_probe,
466	.remove = __devexit_p(wp_gpio_remove),
467	.driver = {
468	.name = "wp_gpio",
469	.owner = THIS_MODULE,
470	},
471	};
472
8bf02617 AD	473	static int __init lnw_gpio_init(void)
8bf02617 AD	474	{
72b4379e AC	475	int ret;
	476	ret = pci_register_driver(&lnw_gpio_driver);
	477	if (ret < 0)
	478	return ret;
	479	ret = platform_driver_register(&wp_gpio_driver);
	480	if (ret < 0)
	481	pci_unregister_driver(&lnw_gpio_driver);
	482	return ret;
8bf02617 AD	483	}
	484
	485	device_initcall(lnw_gpio_init);