[GitHub/mt8127/android_kernel_alcatel_ttab.git] / drivers / gpio / gpio-ich.c

/*
 * Intel ICH6-10, Series 5 and 6 GPIO driver
 *
 * Copyright (C) 2010 Extreme Engineering Solutions.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

#include <linux/module.h>
#include <linux/pci.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
#include <linux/mfd/lpc_ich.h>

#define DRV_NAME "gpio_ich"

/*
 * GPIO register offsets in GPIO I/O space.
 * Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
 * LVLx registers.  Logic in the read/write functions takes a register and
 * an absolute bit number and determines the proper register offset and bit
 * number in that register.  For example, to read the value of GPIO bit 50
 * the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
 * bit 18 (50%32).
 */
enum GPIO_REG {
	GPIO_USE_SEL = 0,
	GPIO_IO_SEL,
	GPIO_LVL,
};

static const u8 ichx_regs[3][3] = {
	{0x00, 0x30, 0x40},	/* USE_SEL[1-3] offsets */
	{0x04, 0x34, 0x44},	/* IO_SEL[1-3] offsets */
	{0x0c, 0x38, 0x48},	/* LVL[1-3] offsets */
};

#define ICHX_WRITE(val, reg, base_res)	outl(val, (reg) + (base_res)->start)
#define ICHX_READ(reg, base_res)	inl((reg) + (base_res)->start)

struct ichx_desc {
	/* Max GPIO pins the chipset can have */
	uint ngpio;

	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	bool uses_gpe0;

	/* USE_SEL is bogus on some chipsets, eg 3100 */
	u32 use_sel_ignore[3];

	/* Some chipsets have quirks, let these use their own request/get */
	int (*request)(struct gpio_chip *chip, unsigned offset);
	int (*get)(struct gpio_chip *chip, unsigned offset);
};

static struct {
	spinlock_t lock;
	struct platform_device *dev;
	struct gpio_chip chip;
	struct resource *gpio_base;	/* GPIO IO base */
	struct resource *pm_base;	/* Power Mangagment IO base */
	struct ichx_desc *desc;	/* Pointer to chipset-specific description */
	u32 orig_gpio_ctrl;	/* Orig CTRL value, used to restore on exit */
} ichx_priv;

static int modparam_gpiobase = -1;	/* dynamic */
module_param_named(gpiobase, modparam_gpiobase, int, 0444);
MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
			   "which is the default.");

static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
{
	unsigned long flags;
	u32 data, tmp;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;
	int ret = 0;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	if (val)
		data |= 1 << bit;
	else
		data &= ~(1 << bit);
	ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
	if (verify && data != tmp)
		ret = -EPERM;

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return ret;
}

static int ichx_read_bit(int reg, unsigned nr)
{
	unsigned long flags;
	u32 data;
	int reg_nr = nr / 32;
	int bit = nr & 0x1f;

	spin_lock_irqsave(&ichx_priv.lock, flags);

	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);

	spin_unlock_irqrestore(&ichx_priv.lock, flags);

	return data & (1 << bit) ? 1 : 0;
}

static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
{
	/*
	 * Try setting pin as an input and verify it worked since many pins
	 * are output-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
					int val)
{
	/* Set GPIO output value. */
	ichx_write_bit(GPIO_LVL, nr, val, 0);

	/*
	 * Try setting pin as an output and verify it worked since many pins
	 * are input-only.
	 */
	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
		return -EINVAL;

	return 0;
}

static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	return ichx_read_bit(GPIO_LVL, nr);
}

static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
{
	unsigned long flags;
	u32 data;

	/*
	 * GPI 0 - 15 need to be read from the power management registers on
	 * a ICH6/3100 bridge.
	 */
	if (nr < 16) {
		if (!ichx_priv.pm_base)
			return -ENXIO;

		spin_lock_irqsave(&ichx_priv.lock, flags);

		/* GPI 0 - 15 are latched, write 1 to clear*/
		ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
		data = ICHX_READ(0, ichx_priv.pm_base);

		spin_unlock_irqrestore(&ichx_priv.lock, flags);

		return (data >> 16) & (1 << nr) ? 1 : 0;
	} else {
		return ichx_gpio_get(chip, nr);
	}
}

static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Note we assume the BIOS properly set a bridge's USE value.  Some
	 * chips (eg Intel 3100) have bogus USE values though, so first see if
	 * the chipset's USE value can be trusted for this specific bit.
	 * If it can't be trusted, assume that the pin can be used as a GPIO.
	 */
	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
		return 1;

	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
}

static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
{
	/*
	 * Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
	 * bridge as they are controlled by USE register bits 0 and 1.  See
	 * "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
	 * additional info.
	 */
	if (nr == 16 || nr == 17)
		nr -= 16;

	return ichx_gpio_request(chip, nr);
}

static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
{
	ichx_write_bit(GPIO_LVL, nr, val, 0);
}

static void __devinit ichx_gpiolib_setup(struct gpio_chip *chip)
{
	chip->owner = THIS_MODULE;
	chip->label = DRV_NAME;
	chip->dev = &ichx_priv.dev->dev;

	/* Allow chip-specific overrides of request()/get() */
	chip->request = ichx_priv.desc->request ?
		ichx_priv.desc->request : ichx_gpio_request;
	chip->get = ichx_priv.desc->get ?
		ichx_priv.desc->get : ichx_gpio_get;

	chip->set = ichx_gpio_set;
	chip->direction_input = ichx_gpio_direction_input;
	chip->direction_output = ichx_gpio_direction_output;
	chip->base = modparam_gpiobase;
	chip->ngpio = ichx_priv.desc->ngpio;
	chip->can_sleep = 0;
	chip->dbg_show = NULL;
}

/* ICH6-based, 631xesb-based */
static struct ichx_desc ich6_desc = {
	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
};

/* Intel 3100 */
static struct ichx_desc i3100_desc = {
	/*
	 * Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
	 * the Intel 3100.  See "Table 712. GPIO Summary Table" of 3100
	 * Datasheet for more info.
	 */
	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},

	/* The 3100 needs fixups for GPIO 0 - 17 */
	.request = ich6_gpio_request,
	.get = ich6_gpio_get,

	/* GPIO 0-15 are read in the GPE0_STS PM register */
	.uses_gpe0 = true,

	.ngpio = 50,
};

/* ICH7 and ICH8-based */
static struct ichx_desc ich7_desc = {
	.ngpio = 50,
};

/* ICH9-based */
static struct ichx_desc ich9_desc = {
	.ngpio = 61,
};

/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
static struct ichx_desc ich10_cons_desc = {
	.ngpio = 61,
};
static struct ichx_desc ich10_corp_desc = {
	.ngpio = 72,
};

/* Intel 5 series, 6 series, 3400 series, and C200 series */
static struct ichx_desc intel5_desc = {
	.ngpio = 76,
};

static int __devinit ichx_gpio_probe(struct platform_device *pdev)
{
	struct resource *res_base, *res_pm;
	int err;
	struct lpc_ich_info *ich_info = pdev->dev.platform_data;

	if (!ich_info)
		return -ENODEV;

	ichx_priv.dev = pdev;

	switch (ich_info->gpio_version) {
	case ICH_I3100_GPIO:
		ichx_priv.desc = &i3100_desc;
		break;
	case ICH_V5_GPIO:
		ichx_priv.desc = &intel5_desc;
		break;
	case ICH_V6_GPIO:
		ichx_priv.desc = &ich6_desc;
		break;
	case ICH_V7_GPIO:
		ichx_priv.desc = &ich7_desc;
		break;
	case ICH_V9_GPIO:
		ichx_priv.desc = &ich9_desc;
		break;
	case ICH_V10CORP_GPIO:
		ichx_priv.desc = &ich10_corp_desc;
		break;
	case ICH_V10CONS_GPIO:
		ichx_priv.desc = &ich10_cons_desc;
		break;
	default:
		return -ENODEV;
	}

	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
	if (!res_base || !res_base->start || !res_base->end)
		return -ENODEV;

	if (!request_region(res_base->start, resource_size(res_base),
				pdev->name))
		return -EBUSY;

	ichx_priv.gpio_base = res_base;

	/*
	 * If necessary, determine the I/O address of ACPI/power management
	 * registers which are needed to read the the GPE0 register for GPI pins
	 * 0 - 15 on some chipsets.
	 */
	if (!ichx_priv.desc->uses_gpe0)
		goto init;

	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
	if (!res_pm) {
		pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
		goto init;
	}

	if (!request_region(res_pm->start, resource_size(res_pm),
			pdev->name)) {
		pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
		goto init;
	}

	ichx_priv.pm_base = res_pm;

init:
	ichx_gpiolib_setup(&ichx_priv.chip);
	err = gpiochip_add(&ichx_priv.chip);
	if (err) {
		pr_err("Failed to register GPIOs\n");
		goto add_err;
	}

	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
	       ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);

	return 0;

add_err:
	release_region(ichx_priv.gpio_base->start,
			resource_size(ichx_priv.gpio_base));
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));
	return err;
}

static int __devexit ichx_gpio_remove(struct platform_device *pdev)
{
	int err;

	err = gpiochip_remove(&ichx_priv.chip);
	if (err) {
		dev_err(&pdev->dev, "%s failed, %d\n",
				"gpiochip_remove()", err);
		return err;
	}

	release_region(ichx_priv.gpio_base->start,
				resource_size(ichx_priv.gpio_base));
	if (ichx_priv.pm_base)
		release_region(ichx_priv.pm_base->start,
				resource_size(ichx_priv.pm_base));

	return 0;
}

static struct platform_driver ichx_gpio_driver = {
	.driver		= {
		.owner	= THIS_MODULE,
		.name	= DRV_NAME,
	},
	.probe		= ichx_gpio_probe,
	.remove		= __devexit_p(ichx_gpio_remove),
};

module_platform_driver(ichx_gpio_driver);

MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:"DRV_NAME);
Commit	Line	Data
6ed9f9c4 PT	1	/*
	2	* Intel ICH6-10, Series 5 and 6 GPIO driver
	3	*
	4	* Copyright (C) 2010 Extreme Engineering Solutions.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
	22
	23	#include <linux/module.h>
	24	#include <linux/pci.h>
	25	#include <linux/gpio.h>
	26	#include <linux/platform_device.h>
	27	#include <linux/mfd/lpc_ich.h>
	28
	29	#define DRV_NAME "gpio_ich"
	30
	31	/*
	32	* GPIO register offsets in GPIO I/O space.
	33	* Each chunk of 32 GPIOs is manipulated via its own USE_SELx, IO_SELx, and
	34	* LVLx registers. Logic in the read/write functions takes a register and
	35	* an absolute bit number and determines the proper register offset and bit
	36	* number in that register. For example, to read the value of GPIO bit 50
	37	* the code would access offset ichx_regs[2(=GPIO_LVL)][1(=50/32)],
	38	* bit 18 (50%32).
	39	*/
	40	enum GPIO_REG {
	41	GPIO_USE_SEL = 0,
	42	GPIO_IO_SEL,
	43	GPIO_LVL,
	44	};
	45
	46	static const u8 ichx_regs[3][3] = {
	47	{0x00, 0x30, 0x40}, /* USE_SEL[1-3] offsets */
	48	{0x04, 0x34, 0x44}, /* IO_SEL[1-3] offsets */
	49	{0x0c, 0x38, 0x48}, /* LVL[1-3] offsets */
	50	};
	51
	52	#define ICHX_WRITE(val, reg, base_res) outl(val, (reg) + (base_res)->start)
	53	#define ICHX_READ(reg, base_res) inl((reg) + (base_res)->start)
	54
	55	struct ichx_desc {
	56	/* Max GPIO pins the chipset can have */
	57	uint ngpio;
	58
	59	/* Whether the chipset has GPIO in GPE0_STS in the PM IO region */
	60	bool uses_gpe0;
	61
	62	/* USE_SEL is bogus on some chipsets, eg 3100 */
	63	u32 use_sel_ignore[3];
	64
65	/* Some chipsets have quirks, let these use their own request/get */
66	int (request)(struct gpio_chip chip, unsigned offset);
67	int (get)(struct gpio_chip chip, unsigned offset);
68	};
69
70	static struct {
71	spinlock_t lock;
72	struct platform_device *dev;
73	struct gpio_chip chip;
74	struct resource gpio_base; / GPIO IO base */
75	struct resource pm_base; / Power Mangagment IO base */
76	struct ichx_desc desc; / Pointer to chipset-specific description */
77	u32 orig_gpio_ctrl; /* Orig CTRL value, used to restore on exit */
78	} ichx_priv;
79
80	static int modparam_gpiobase = -1; /* dynamic */
81	module_param_named(gpiobase, modparam_gpiobase, int, 0444);
82	MODULE_PARM_DESC(gpiobase, "The GPIO number base. -1 means dynamic, "
83	"which is the default.");
84
85	static int ichx_write_bit(int reg, unsigned nr, int val, int verify)
86	{
87	unsigned long flags;
88	u32 data, tmp;
89	int reg_nr = nr / 32;
90	int bit = nr & 0x1f;
91	int ret = 0;
92
93	spin_lock_irqsave(&ichx_priv.lock, flags);
94
95	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
96	if (val)
97	data \|= 1 << bit;
98	else
99	data &= ~(1 << bit);
100	ICHX_WRITE(data, ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
101	tmp = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
102	if (verify && data != tmp)
103	ret = -EPERM;
104
105	spin_unlock_irqrestore(&ichx_priv.lock, flags);
106
107	return ret;
108	}
109
110	static int ichx_read_bit(int reg, unsigned nr)
111	{
112	unsigned long flags;
113	u32 data;
114	int reg_nr = nr / 32;
115	int bit = nr & 0x1f;
116
117	spin_lock_irqsave(&ichx_priv.lock, flags);
118
119	data = ICHX_READ(ichx_regs[reg][reg_nr], ichx_priv.gpio_base);
120
121	spin_unlock_irqrestore(&ichx_priv.lock, flags);
122
123	return data & (1 << bit) ? 1 : 0;
124	}
125
126	static int ichx_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
127	{
128	/*
129	* Try setting pin as an input and verify it worked since many pins
130	* are output-only.
131	*/
132	if (ichx_write_bit(GPIO_IO_SEL, nr, 1, 1))
133	return -EINVAL;
134
135	return 0;
136	}
137
138	static int ichx_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
139	int val)
140	{
141	/* Set GPIO output value. */
142	ichx_write_bit(GPIO_LVL, nr, val, 0);
143
144	/*
145	* Try setting pin as an output and verify it worked since many pins
146	* are input-only.
147	*/
148	if (ichx_write_bit(GPIO_IO_SEL, nr, 0, 1))
149	return -EINVAL;
150
151	return 0;
152	}
153
154	static int ichx_gpio_get(struct gpio_chip *chip, unsigned nr)
155	{
156	return ichx_read_bit(GPIO_LVL, nr);
157	}
158
159	static int ich6_gpio_get(struct gpio_chip *chip, unsigned nr)
160	{
161	unsigned long flags;
162	u32 data;
163
164	/*
165	* GPI 0 - 15 need to be read from the power management registers on
166	* a ICH6/3100 bridge.
167	*/
168	if (nr < 16) {
169	if (!ichx_priv.pm_base)
170	return -ENXIO;
171
172	spin_lock_irqsave(&ichx_priv.lock, flags);
173
174	/* GPI 0 - 15 are latched, write 1 to clear*/
175	ICHX_WRITE(1 << (16 + nr), 0, ichx_priv.pm_base);
176	data = ICHX_READ(0, ichx_priv.pm_base);
177
178	spin_unlock_irqrestore(&ichx_priv.lock, flags);
179
180	return (data >> 16) & (1 << nr) ? 1 : 0;
181	} else {
182	return ichx_gpio_get(chip, nr);
183	}
184	}
185
186	static int ichx_gpio_request(struct gpio_chip *chip, unsigned nr)
187	{
188	/*
189	* Note we assume the BIOS properly set a bridge's USE value. Some
190	* chips (eg Intel 3100) have bogus USE values though, so first see if
191	* the chipset's USE value can be trusted for this specific bit.
192	* If it can't be trusted, assume that the pin can be used as a GPIO.
193	*/
194	if (ichx_priv.desc->use_sel_ignore[nr / 32] & (1 << (nr & 0x1f)))
195	return 1;
196
197	return ichx_read_bit(GPIO_USE_SEL, nr) ? 0 : -ENODEV;
198	}
199
200	static int ich6_gpio_request(struct gpio_chip *chip, unsigned nr)
201	{
202	/*
203	* Fixups for bits 16 and 17 are necessary on the Intel ICH6/3100
204	* bridge as they are controlled by USE register bits 0 and 1. See
205	* "Table 704 GPIO_USE_SEL1 register" in the i3100 datasheet for
206	* additional info.
207	*/
208	if (nr == 16 \|\| nr == 17)
209	nr -= 16;
210
211	return ichx_gpio_request(chip, nr);
212	}
213
214	static void ichx_gpio_set(struct gpio_chip *chip, unsigned nr, int val)
215	{
216	ichx_write_bit(GPIO_LVL, nr, val, 0);
217	}
218
219	static void __devinit ichx_gpiolib_setup(struct gpio_chip *chip)
220	{
221	chip->owner = THIS_MODULE;
222	chip->label = DRV_NAME;
223	chip->dev = &ichx_priv.dev->dev;
224
225	/* Allow chip-specific overrides of request()/get() */
226	chip->request = ichx_priv.desc->request ?
227	ichx_priv.desc->request : ichx_gpio_request;
228	chip->get = ichx_priv.desc->get ?
229	ichx_priv.desc->get : ichx_gpio_get;
230
231	chip->set = ichx_gpio_set;
232	chip->direction_input = ichx_gpio_direction_input;
233	chip->direction_output = ichx_gpio_direction_output;
234	chip->base = modparam_gpiobase;
235	chip->ngpio = ichx_priv.desc->ngpio;
236	chip->can_sleep = 0;
237	chip->dbg_show = NULL;
238	}
239
240	/* ICH6-based, 631xesb-based */
241	static struct ichx_desc ich6_desc = {
242	/* Bridges using the ICH6 controller need fixups for GPIO 0 - 17 */
243	.request = ich6_gpio_request,
244	.get = ich6_gpio_get,
245
246	/* GPIO 0-15 are read in the GPE0_STS PM register */
247	.uses_gpe0 = true,
248
249	.ngpio = 50,
250	};
251
252	/* Intel 3100 */
253	static struct ichx_desc i3100_desc = {
254	/*
255	* Bits 16,17, 20 of USE_SEL and bit 16 of USE_SEL2 always read 0 on
256	* the Intel 3100. See "Table 712. GPIO Summary Table" of 3100
257	* Datasheet for more info.
258	*/
259	.use_sel_ignore = {0x00130000, 0x00010000, 0x0},
260
261	/* The 3100 needs fixups for GPIO 0 - 17 */
262	.request = ich6_gpio_request,
263	.get = ich6_gpio_get,
264
265	/* GPIO 0-15 are read in the GPE0_STS PM register */
266	.uses_gpe0 = true,
267
268	.ngpio = 50,
269	};
270
271	/* ICH7 and ICH8-based */
272	static struct ichx_desc ich7_desc = {
273	.ngpio = 50,
274	};
275
276	/* ICH9-based */
277	static struct ichx_desc ich9_desc = {
278	.ngpio = 61,
279	};
280
281	/* ICH10-based - Consumer/corporate versions have different amount of GPIO */
282	static struct ichx_desc ich10_cons_desc = {
283	.ngpio = 61,
284	};
285	static struct ichx_desc ich10_corp_desc = {
286	.ngpio = 72,
287	};
288
289	/* Intel 5 series, 6 series, 3400 series, and C200 series */
290	static struct ichx_desc intel5_desc = {
291	.ngpio = 76,
292	};
293
294	static int __devinit ichx_gpio_probe(struct platform_device *pdev)
295	{
296	struct resource res_base, res_pm;
297	int err;
298	struct lpc_ich_info *ich_info = pdev->dev.platform_data;
299
300	if (!ich_info)
301	return -ENODEV;
302
303	ichx_priv.dev = pdev;
304
305	switch (ich_info->gpio_version) {
306	case ICH_I3100_GPIO:
307	ichx_priv.desc = &i3100_desc;
308	break;
309	case ICH_V5_GPIO:
310	ichx_priv.desc = &intel5_desc;
311	break;
312	case ICH_V6_GPIO:
313	ichx_priv.desc = &ich6_desc;
314	break;
315	case ICH_V7_GPIO:
316	ichx_priv.desc = &ich7_desc;
317	break;
318	case ICH_V9_GPIO:
319	ichx_priv.desc = &ich9_desc;
320	break;
321	case ICH_V10CORP_GPIO:
322	ichx_priv.desc = &ich10_corp_desc;
323	break;
324	case ICH_V10CONS_GPIO:
325	ichx_priv.desc = &ich10_cons_desc;
326	break;
327	default:
328	return -ENODEV;
329	}
330
331	res_base = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPIO);
332	if (!res_base \|\| !res_base->start \|\| !res_base->end)
333	return -ENODEV;
334
335	if (!request_region(res_base->start, resource_size(res_base),
336	pdev->name))
337	return -EBUSY;
338
339	ichx_priv.gpio_base = res_base;
340
341	/*
342	* If necessary, determine the I/O address of ACPI/power management
343	* registers which are needed to read the the GPE0 register for GPI pins
344	* 0 - 15 on some chipsets.
345	*/
346	if (!ichx_priv.desc->uses_gpe0)
347	goto init;
348
349	res_pm = platform_get_resource(pdev, IORESOURCE_IO, ICH_RES_GPE0);
350	if (!res_pm) {
351	pr_warn("ACPI BAR is unavailable, GPI 0 - 15 unavailable\n");
352	goto init;
353	}
354
355	if (!request_region(res_pm->start, resource_size(res_pm),
356	pdev->name)) {
357	pr_warn("ACPI BAR is busy, GPI 0 - 15 unavailable\n");
358	goto init;
359	}
360
361	ichx_priv.pm_base = res_pm;
362
363	init:
364	ichx_gpiolib_setup(&ichx_priv.chip);
365	err = gpiochip_add(&ichx_priv.chip);
366	if (err) {
367	pr_err("Failed to register GPIOs\n");
368	goto add_err;
369	}
370
371	pr_info("GPIO from %d to %d on %s\n", ichx_priv.chip.base,
372	ichx_priv.chip.base + ichx_priv.chip.ngpio - 1, DRV_NAME);
373
374	return 0;
375
376	add_err:
377	release_region(ichx_priv.gpio_base->start,
378	resource_size(ichx_priv.gpio_base));
379	if (ichx_priv.pm_base)
380	release_region(ichx_priv.pm_base->start,
381	resource_size(ichx_priv.pm_base));
382	return err;
383	}
384
385	static int __devexit ichx_gpio_remove(struct platform_device *pdev)
386	{
387	int err;
388
389	err = gpiochip_remove(&ichx_priv.chip);
390	if (err) {
391	dev_err(&pdev->dev, "%s failed, %d\n",
392	"gpiochip_remove()", err);
393	return err;
394	}
395
396	release_region(ichx_priv.gpio_base->start,
397	resource_size(ichx_priv.gpio_base));
398	if (ichx_priv.pm_base)
399	release_region(ichx_priv.pm_base->start,
400	resource_size(ichx_priv.pm_base));
401
402	return 0;
403	}
404
405	static struct platform_driver ichx_gpio_driver = {
406	.driver = {
407	.owner = THIS_MODULE,
408	.name = DRV_NAME,
409	},
410	.probe = ichx_gpio_probe,
411	.remove = __devexit_p(ichx_gpio_remove),
412	};
413
414	module_platform_driver(ichx_gpio_driver);
415
416	MODULE_AUTHOR("Peter Tyser <ptyser@xes-inc.com>");
417	MODULE_DESCRIPTION("GPIO interface for Intel ICH series");
418	MODULE_LICENSE("GPL");
419	MODULE_ALIAS("platform:"DRV_NAME);